From 06ad86361ab29d344a5e2e22903c2739743c77be Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Danny=20M=C3=B6sch?= Date: Fri, 10 May 2024 07:56:35 +0200 Subject: [PATCH 001/824] [NFC] Prefer `str.resize(len)` over `str.substr(0, len)` (#91067) --- llvm/include/llvm/Analysis/DOTGraphTraitsPass.h | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h b/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h index da72fb511f82..7aea7a3b0f6d 100644 --- a/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h +++ b/llvm/include/llvm/Analysis/DOTGraphTraitsPass.h @@ -87,13 +87,12 @@ private: }; static inline void shortenFileName(std::string &FN, unsigned char len = 250) { - - FN = FN.substr(0, len); - + if (FN.length() > len) + FN.resize(len); auto strLen = FN.length(); while (strLen > 0) { - if (auto it = nameObj.find(FN); it != nameObj.end()) { - FN = FN.substr(0, --len); + if (nameObj.find(FN) != nameObj.end()) { + FN.resize(--len); } else { nameObj.insert(FN); break; -- GitLab From 135d92f903161e66ff82ab846acfbc5015ef3096 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Thu, 9 May 2024 23:12:08 -0700 Subject: [PATCH 002/824] [Driver] Use StringRef::operator== instead of StringRef::equals (NFC) (#91698) I'm planning to remove StringRef::equals in favor of StringRef::operator==. - StringRef::operator==/!= outnumber StringRef::equals by a factor of 13 under clang/ in terms of their usage. - The elimination of StringRef::equals brings StringRef closer to std::string_view, which has operator== but not equals. - S == "foo" is more readable than S.equals("foo"), especially for !Long.Expression.equals("str") vs Long.Expression != "str". --- clang/lib/Driver/Driver.cpp | 6 +- clang/lib/Driver/ToolChains/AIX.cpp | 4 +- clang/lib/Driver/ToolChains/AMDGPU.cpp | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 66 +++++++++++----------- clang/lib/Driver/ToolChains/CommonArgs.cpp | 2 +- clang/lib/Driver/ToolChains/Flang.cpp | 13 ++--- 6 files changed, 45 insertions(+), 48 deletions(-) diff --git a/clang/lib/Driver/Driver.cpp b/clang/lib/Driver/Driver.cpp index 114320f5d314..7b36d8e5084c 100644 --- a/clang/lib/Driver/Driver.cpp +++ b/clang/lib/Driver/Driver.cpp @@ -564,9 +564,9 @@ static llvm::Triple computeTargetTriple(const Driver &D, StringRef ObjectMode = *ObjectModeValue; llvm::Triple::ArchType AT = llvm::Triple::UnknownArch; - if (ObjectMode.equals("64")) { + if (ObjectMode == "64") { AT = Target.get64BitArchVariant().getArch(); - } else if (ObjectMode.equals("32")) { + } else if (ObjectMode == "32") { AT = Target.get32BitArchVariant().getArch(); } else { D.Diag(diag::err_drv_invalid_object_mode) << ObjectMode; @@ -6694,7 +6694,7 @@ llvm::StringRef clang::driver::getDriverMode(StringRef ProgName, return Opt.consume_front(OptName) ? Opt : ""; } -bool driver::IsClangCL(StringRef DriverMode) { return DriverMode.equals("cl"); } +bool driver::IsClangCL(StringRef DriverMode) { return DriverMode == "cl"; } llvm::Error driver::expandResponseFiles(SmallVectorImpl &Args, bool ClangCLMode, diff --git a/clang/lib/Driver/ToolChains/AIX.cpp b/clang/lib/Driver/ToolChains/AIX.cpp index aab98506adb9..85825e1ea65b 100644 --- a/clang/lib/Driver/ToolChains/AIX.cpp +++ b/clang/lib/Driver/ToolChains/AIX.cpp @@ -481,8 +481,8 @@ static void addTocDataOptions(const llvm::opt::ArgList &Args, // Currently only supported for small code model. if (TOCDataGloballyinEffect && - (Args.getLastArgValue(options::OPT_mcmodel_EQ).equals("large") || - Args.getLastArgValue(options::OPT_mcmodel_EQ).equals("medium"))) { + (Args.getLastArgValue(options::OPT_mcmodel_EQ) == "large" || + Args.getLastArgValue(options::OPT_mcmodel_EQ) == "medium")) { D.Diag(clang::diag::warn_drv_unsupported_tocdata); return; } diff --git a/clang/lib/Driver/ToolChains/AMDGPU.cpp b/clang/lib/Driver/ToolChains/AMDGPU.cpp index 07965b487ea7..9ffea57b005d 100644 --- a/clang/lib/Driver/ToolChains/AMDGPU.cpp +++ b/clang/lib/Driver/ToolChains/AMDGPU.cpp @@ -732,7 +732,7 @@ AMDGPUToolChain::TranslateArgs(const DerivedArgList &Args, StringRef BoundArch, checkTargetID(*DAL); - if (!Args.getLastArgValue(options::OPT_x).equals("cl")) + if (Args.getLastArgValue(options::OPT_x) != "cl") return DAL; // Phase 1 (.cl -> .bc) diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 775dc249999e..449eb9b2a965 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -1526,7 +1526,7 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args, CmdArgs.push_back( Args.MakeArgString(Twine("-msign-return-address=") + Scope)); - if (!Scope.equals("none")) + if (Scope != "none") CmdArgs.push_back( Args.MakeArgString(Twine("-msign-return-address-key=") + Key)); if (BranchProtectionPAuthLR) @@ -1719,10 +1719,9 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args, if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits_EQ)) { StringRef Val = A->getValue(); const Driver &D = getToolChain().getDriver(); - if (Val.equals("128") || Val.equals("256") || Val.equals("512") || - Val.equals("1024") || Val.equals("2048") || Val.equals("128+") || - Val.equals("256+") || Val.equals("512+") || Val.equals("1024+") || - Val.equals("2048+")) { + if (Val == "128" || Val == "256" || Val == "512" || Val == "1024" || + Val == "2048" || Val == "128+" || Val == "256+" || Val == "512+" || + Val == "1024+" || Val == "2048+") { unsigned Bits = 0; if (!Val.consume_back("+")) { bool Invalid = Val.getAsInteger(10, Bits); (void)Invalid; @@ -1736,7 +1735,7 @@ void Clang::AddAArch64TargetArgs(const ArgList &Args, CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(Bits / 128))); // Silently drop requests for vector-length agnostic code as it's implied. - } else if (!Val.equals("scalable")) + } else if (Val != "scalable") // Handle the unsupported values passed to msve-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; @@ -2098,7 +2097,7 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args, // If the value is "zvl", use MinVLen from march. Otherwise, try to parse // as integer as long as we have a MinVLen. unsigned Bits = 0; - if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { + if (Val == "zvl" && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { Bits = MinVLen; } else if (!Val.getAsInteger(10, Bits)) { // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that @@ -2115,7 +2114,7 @@ void Clang::AddRISCVTargetArgs(const ArgList &Args, Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin))); CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin))); - } else if (!Val.equals("scalable")) { + } else if (Val != "scalable") { // Handle the unsupported values passed to mrvv-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; @@ -2865,13 +2864,13 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_fcomplex_arithmetic_EQ: { LangOptions::ComplexRangeKind RangeVal; StringRef Val = A->getValue(); - if (Val.equals("full")) + if (Val == "full") RangeVal = LangOptions::ComplexRangeKind::CX_Full; - else if (Val.equals("improved")) + else if (Val == "improved") RangeVal = LangOptions::ComplexRangeKind::CX_Improved; - else if (Val.equals("promoted")) + else if (Val == "promoted") RangeVal = LangOptions::ComplexRangeKind::CX_Promoted; - else if (Val.equals("basic")) + else if (Val == "basic") RangeVal = LangOptions::ComplexRangeKind::CX_Basic; else { D.Diag(diag::err_drv_unsupported_option_argument) @@ -2910,24 +2909,24 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, FPContract = "on"; StringRef Val = A->getValue(); - if (OFastEnabled && !Val.equals("fast")) { - // Only -ffp-model=fast is compatible with OFast, ignore. + if (OFastEnabled && Val != "fast") { + // Only -ffp-model=fast is compatible with OFast, ignore. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-model=" + Val) << "-Ofast"; break; } StrictFPModel = false; - if (!FPModel.empty() && !FPModel.equals(Val)) + if (!FPModel.empty() && FPModel != Val) D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-model=" + FPModel) << Args.MakeArgString("-ffp-model=" + Val); - if (Val.equals("fast")) { + if (Val == "fast") { FPModel = Val; applyFastMath(); - } else if (Val.equals("precise")) { + } else if (Val == "precise") { FPModel = Val; FPContract = "on"; - } else if (Val.equals("strict")) { + } else if (Val == "strict") { StrictFPModel = true; FPExceptionBehavior = "strict"; FPModel = Val; @@ -2957,7 +2956,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_fno_signed_zeros: SignedZeros = false; break; case options::OPT_ftrapping_math: if (!TrappingMathPresent && !FPExceptionBehavior.empty() && - !FPExceptionBehavior.equals("strict")) + FPExceptionBehavior != "strict") // Warn that previous value of option is overridden. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-exception-behavior=" + @@ -2969,7 +2968,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, break; case options::OPT_fno_trapping_math: if (!TrappingMathPresent && !FPExceptionBehavior.empty() && - !FPExceptionBehavior.equals("ignore")) + FPExceptionBehavior != "ignore") // Warn that previous value of option is overridden. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-exception-behavior=" + @@ -3008,8 +3007,8 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // Validate and pass through -ffp-contract option. case options::OPT_ffp_contract: { StringRef Val = A->getValue(); - if (Val.equals("fast") || Val.equals("on") || Val.equals("off") || - Val.equals("fast-honor-pragmas")) { + if (Val == "fast" || Val == "on" || Val == "off" || + Val == "fast-honor-pragmas") { FPContract = Val; LastSeenFfpContractOption = Val; } else @@ -3022,16 +3021,16 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, case options::OPT_ffp_exception_behavior_EQ: { StringRef Val = A->getValue(); if (!TrappingMathPresent && !FPExceptionBehavior.empty() && - !FPExceptionBehavior.equals(Val)) + FPExceptionBehavior != Val) // Warn that previous value of option is overridden. D.Diag(clang::diag::warn_drv_overriding_option) << Args.MakeArgString("-ffp-exception-behavior=" + FPExceptionBehavior) << Args.MakeArgString("-ffp-exception-behavior=" + Val); TrappingMath = TrappingMathPresent = false; - if (Val.equals("ignore") || Val.equals("maytrap")) + if (Val == "ignore" || Val == "maytrap") FPExceptionBehavior = Val; - else if (Val.equals("strict")) { + else if (Val == "strict") { FPExceptionBehavior = Val; TrappingMath = TrappingMathPresent = true; } else @@ -3043,8 +3042,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // Validate and pass through -ffp-eval-method option. case options::OPT_ffp_eval_method_EQ: { StringRef Val = A->getValue(); - if (Val.equals("double") || Val.equals("extended") || - Val.equals("source")) + if (Val == "double" || Val == "extended" || Val == "source") FPEvalMethod = Val; else D.Diag(diag::err_drv_unsupported_option_argument) @@ -3056,18 +3054,18 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, StringRef Val = A->getValue(); const llvm::Triple::ArchType Arch = TC.getArch(); if (Arch == llvm::Triple::x86 || Arch == llvm::Triple::x86_64) { - if (Val.equals("standard") || Val.equals("fast")) + if (Val == "standard" || Val == "fast") Float16ExcessPrecision = Val; // To make it GCC compatible, allow the value of "16" which // means disable excess precision, the same meaning than clang's // equivalent value "none". - else if (Val.equals("16")) + else if (Val == "16") Float16ExcessPrecision = "none"; else D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; } else { - if (!(Val.equals("standard") || Val.equals("fast"))) + if (!(Val == "standard" || Val == "fast")) D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; } @@ -3149,7 +3147,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, // subsequent options conflict then emit warning diagnostic. if (HonorINFs && HonorNaNs && !AssociativeMath && !ReciprocalMath && SignedZeros && TrappingMath && RoundingFPMath && !ApproxFunc && - FPContract.equals("off")) + FPContract == "off") // OK: Current Arg doesn't conflict with -ffp-model=strict ; else { @@ -3195,7 +3193,7 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, if (TrappingMath) { // FP Exception Behavior is also set to strict - assert(FPExceptionBehavior.equals("strict")); + assert(FPExceptionBehavior == "strict"); } // The default is IEEE. @@ -3244,8 +3242,8 @@ static void RenderFloatingPointOptions(const ToolChain &TC, const Driver &D, if (!HonorINFs && !HonorNaNs && !MathErrno && AssociativeMath && ApproxFunc && ReciprocalMath && !SignedZeros && !TrappingMath && !RoundingFPMath) { CmdArgs.push_back("-ffast-math"); - if (FPModel.equals("fast")) { - if (FPContract.equals("fast")) + if (FPModel == "fast") { + if (FPContract == "fast") // All set, do nothing. ; else if (FPContract.empty()) diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index 6796b43a1550..71e993119436 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -346,7 +346,7 @@ void tools::addDirectoryList(const ArgList &Args, ArgStringList &CmdArgs, return; // Nothing to do. StringRef Name(ArgName); - if (Name.equals("-I") || Name.equals("-L") || Name.empty()) + if (Name == "-I" || Name == "-L" || Name.empty()) CombinedArg = true; StringRef Dirs(DirList); diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 436a9c418a5f..d275528b6905 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -170,10 +170,9 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, if (Arg *A = Args.getLastArg(options::OPT_msve_vector_bits_EQ)) { StringRef Val = A->getValue(); const Driver &D = getToolChain().getDriver(); - if (Val.equals("128") || Val.equals("256") || Val.equals("512") || - Val.equals("1024") || Val.equals("2048") || Val.equals("128+") || - Val.equals("256+") || Val.equals("512+") || Val.equals("1024+") || - Val.equals("2048+")) { + if (Val == "128" || Val == "256" || Val == "512" || Val == "1024" || + Val == "2048" || Val == "128+" || Val == "256+" || Val == "512+" || + Val == "1024+" || Val == "2048+") { unsigned Bits = 0; if (!Val.consume_back("+")) { [[maybe_unused]] bool Invalid = Val.getAsInteger(10, Bits); @@ -187,7 +186,7 @@ void Flang::AddAArch64TargetArgs(const ArgList &Args, CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(Bits / 128))); // Silently drop requests for vector-length agnostic code as it's implied. - } else if (!Val.equals("scalable")) + } else if (Val != "scalable") // Handle the unsupported values passed to msve-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; @@ -214,7 +213,7 @@ void Flang::AddRISCVTargetArgs(const ArgList &Args, // If the value is "zvl", use MinVLen from march. Otherwise, try to parse // as integer as long as we have a MinVLen. unsigned Bits = 0; - if (Val.equals("zvl") && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { + if (Val == "zvl" && MinVLen >= llvm::RISCV::RVVBitsPerBlock) { Bits = MinVLen; } else if (!Val.getAsInteger(10, Bits)) { // Only accept power of 2 values beteen RVVBitsPerBlock and 65536 that @@ -231,7 +230,7 @@ void Flang::AddRISCVTargetArgs(const ArgList &Args, Args.MakeArgString("-mvscale-max=" + llvm::Twine(VScaleMin))); CmdArgs.push_back( Args.MakeArgString("-mvscale-min=" + llvm::Twine(VScaleMin))); - } else if (!Val.equals("scalable")) { + } else if (Val != "scalable") { // Handle the unsupported values passed to mrvv-vector-bits. D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << Val; -- GitLab From e7e13c6ffec58fe67a23d173387e96d5ebb8f84b Mon Sep 17 00:00:00 2001 From: Lang Hames Date: Fri, 10 May 2024 16:09:34 +1000 Subject: [PATCH 003/824] [ORC] Fix another error fall-through in EPCGenericDylibManager::lookupAsync. The early return added in this commit should have been added in cbf1535cc81. No test-case: This would require a deliberately injected failure in a remote-JIT test and we don't have the infrastructure for that at the moment. rdar://126772381 --- llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp b/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp index 7c0d89012922..298bde46ab75 100644 --- a/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp +++ b/llvm/lib/ExecutionEngine/Orc/EPCGenericDylibManager.cpp @@ -92,6 +92,7 @@ void EPCGenericDylibManager::lookupAsync(tpctypes::DylibHandle H, if (SerializationErr) { cantFail(Result.takeError()); Complete(std::move(SerializationErr)); + return; } Complete(std::move(Result)); }, -- GitLab From 0ebe48f068c0ca69f76ed68b621c9294acd75f76 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 10 May 2024 14:31:43 +0800 Subject: [PATCH 004/824] [RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701) This further splits off #91440 to inch RISCVInsertVSETVLI closer to post vector regalloc. As noted in #91440, most of the diffs are from moving vsetvli insertion after the vxrm/csr insertion passes, but these are getting conflated with the changes from moving to LiveIntervals. One idea was that we could try and remove some of these diffs by manually moving back the vsetvlis past the vxrm/csr instructions. But this meant having to touch up the LiveIntervals again which seemed to lead to even more diffs. This instead just moves RISCVInsertVSETVLI after RISCVInsertReadWriteCSR and RISCVInsertWriteVXRM so we can isolate those changes. --- llvm/lib/Target/RISCV/RISCVTargetMachine.cpp | 2 +- llvm/test/CodeGen/RISCV/O0-pipeline.ll | 2 +- llvm/test/CodeGen/RISCV/O3-pipeline.ll | 2 +- llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/commutable.ll | 12 +- llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll | 56 +-- llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll | 352 +++++++++--------- llvm/test/CodeGen/RISCV/rvv/cttz-sdnode.ll | 32 +- .../CodeGen/RISCV/rvv/double-round-conv.ll | 32 +- .../RISCV/rvv/fixed-vectors-ceil-vp.ll | 38 +- .../CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll | 8 +- .../CodeGen/RISCV/rvv/fixed-vectors-cttz.ll | 16 +- .../RISCV/rvv/fixed-vectors-floor-vp.ll | 38 +- .../RISCV/rvv/fixed-vectors-round-vp.ll | 38 +- .../RISCV/rvv/fixed-vectors-roundeven-vp.ll | 38 +- .../RISCV/rvv/fixed-vectors-roundtozero-vp.ll | 38 +- .../CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll | 38 +- .../CodeGen/RISCV/rvv/float-round-conv.ll | 48 +-- llvm/test/CodeGen/RISCV/rvv/floor-vp.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/frm-insert.ll | 84 ++--- .../test/CodeGen/RISCV/rvv/half-round-conv.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/masked-tama.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll | 8 +- llvm/test/CodeGen/RISCV/rvv/round-vp.ll | 52 +-- llvm/test/CodeGen/RISCV/rvv/roundeven-vp.ll | 52 +-- llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll | 52 +-- .../rvv/rvv-peephole-vmerge-masked-vops.ll | 4 +- .../RISCV/rvv/rvv-peephole-vmerge-vops.ll | 14 +- .../CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll | 40 +- .../CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll | 40 +- llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll | 22 +- llvm/test/CodeGen/RISCV/rvv/vaadd.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vaaddu-sdnode.ll | 36 +- llvm/test/CodeGen/RISCV/rvv/vaaddu.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vasub.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vasubu.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vfadd.ll | 234 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfdiv.ll | 234 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfmacc.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmadd.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmsac.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmsub.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfmul.ll | 234 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll | 192 +++++----- llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfrec7.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfredosum.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfredusum.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll | 120 +++--- llvm/test/CodeGen/RISCV/rvv/vfwadd.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll | 244 ++++++------ llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll | 72 ++-- llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwmul.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll | 88 ++--- llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll | 88 ++--- llvm/test/CodeGen/RISCV/rvv/vfwsub.ll | 144 +++---- llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll | 244 ++++++------ llvm/test/CodeGen/RISCV/rvv/vnclip.ll | 180 ++++----- llvm/test/CodeGen/RISCV/rvv/vnclipu.ll | 180 ++++----- llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll | 160 ++++---- llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll | 176 ++++----- llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll | 24 +- llvm/test/CodeGen/RISCV/rvv/vxrm.mir | 6 +- 86 files changed, 4519 insertions(+), 4519 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp index b79568539046..7b2dcadc4191 100644 --- a/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp +++ b/llvm/lib/Target/RISCV/RISCVTargetMachine.cpp @@ -541,9 +541,9 @@ void RISCVPassConfig::addPreRegAlloc() { addPass(createRISCVPreRAExpandPseudoPass()); if (TM->getOptLevel() != CodeGenOptLevel::None) addPass(createRISCVMergeBaseOffsetOptPass()); - addPass(createRISCVInsertVSETVLIPass()); addPass(createRISCVInsertReadWriteCSRPass()); addPass(createRISCVInsertWriteVXRMPass()); + addPass(createRISCVInsertVSETVLIPass()); } void RISCVPassConfig::addFastRegAlloc() { diff --git a/llvm/test/CodeGen/RISCV/O0-pipeline.ll b/llvm/test/CodeGen/RISCV/O0-pipeline.ll index 56bd4bd0c08f..c4a7f9562534 100644 --- a/llvm/test/CodeGen/RISCV/O0-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O0-pipeline.ll @@ -40,9 +40,9 @@ ; CHECK-NEXT: Finalize ISel and expand pseudo-instructions ; CHECK-NEXT: Local Stack Slot Allocation ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass -; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass ; CHECK-NEXT: RISC-V Insert Write VXRM Pass +; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: Init Undef Pass ; CHECK-NEXT: Eliminate PHI nodes for register allocation ; CHECK-NEXT: Two-Address instruction pass diff --git a/llvm/test/CodeGen/RISCV/O3-pipeline.ll b/llvm/test/CodeGen/RISCV/O3-pipeline.ll index 04b055f9b216..4a71d3276d26 100644 --- a/llvm/test/CodeGen/RISCV/O3-pipeline.ll +++ b/llvm/test/CodeGen/RISCV/O3-pipeline.ll @@ -115,9 +115,9 @@ ; RV64-NEXT: RISC-V Optimize W Instructions ; CHECK-NEXT: RISC-V Pre-RA pseudo instruction expansion pass ; CHECK-NEXT: RISC-V Merge Base Offset -; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: RISC-V Insert Read/Write CSR Pass ; CHECK-NEXT: RISC-V Insert Write VXRM Pass +; CHECK-NEXT: RISC-V Insert VSETVLI pass ; CHECK-NEXT: Detect Dead Lanes ; CHECK-NEXT: Init Undef Pass ; CHECK-NEXT: Process Implicit Definitions diff --git a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll index 5b271606f08a..aa11e012af20 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ceil-vp.ll @@ -15,8 +15,8 @@ define @vp_ceil_vv_nxv1f16( %va, @vp_ceil_vv_nxv2f16( %va, @vp_ceil_vv_nxv4f16( %va, @vp_ceil_vv_nxv8f16( %va, @vp_ceil_vv_nxv16f16( %va, @vp_ceil_vv_nxv32f16( %va, @vp_ceil_vv_nxv1f32( %va, @vp_ceil_vv_nxv2f32( %va, @vp_ceil_vv_nxv4f32( %va, @vp_ceil_vv_nxv8f32( %va, @vp_ceil_vv_nxv16f32( %va, @vp_ceil_vv_nxv1f64( %va, @vp_ceil_vv_nxv2f64( %va, @vp_ceil_vv_nxv4f64( %va, @vp_ceil_vv_nxv7f64( %va, @vp_ceil_vv_nxv8f64( %va, @vp_ceil_vv_nxv16f64( %va, < ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a2, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a2 @@ -750,8 +750,8 @@ define @vp_ceil_vv_nxv16f64( %va, < ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable.ll b/llvm/test/CodeGen/RISCV/rvv/commutable.ll index d94b529bac01..5bca2eeb3fdd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/commutable.ll +++ b/llvm/test/CodeGen/RISCV/rvv/commutable.ll @@ -720,8 +720,8 @@ declare @llvm.riscv.vaadd.nxv1i64.nxv1i64(, define @commutable_vaadd_vv( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: commutable_vaadd_vv: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 @@ -737,8 +737,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( @commutable_vaadd_vv_masked( %0, %1, %mask, iXLen %2) { ; CHECK-LABEL: commutable_vaadd_vv_masked: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t ; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma @@ -755,8 +755,8 @@ declare @llvm.riscv.vaaddu.nxv1i64.nxv1i64( define @commutable_vaaddu_vv( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: commutable_vaaddu_vv: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 @@ -772,8 +772,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( @commutable_vaaddu_vv_masked( %0, %1, %mask, iXLen %2) { ; CHECK-LABEL: commutable_vaaddu_vv_masked: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t ; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma @@ -790,8 +790,8 @@ declare @llvm.riscv.vsmul.nxv1i64.nxv1i64(, define @commutable_vsmul_vv( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: commutable_vsmul_vv: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vadd.vv v8, v8, v8 @@ -807,8 +807,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( @commutable_vsmul_vv_masked( %0, %1, %mask, iXLen %2) { ; CHECK-LABEL: commutable_vsmul_vv_masked: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v10, v8, v9, v0.t ; CHECK-NEXT: vsmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll index d756cfcf7077..41ec102c34ef 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-sdnode.ll @@ -806,8 +806,8 @@ define @ctlz_nxv1i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv1i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -878,8 +878,8 @@ define @ctlz_nxv2i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv2i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -950,8 +950,8 @@ define @ctlz_nxv4i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv4i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -1022,8 +1022,8 @@ define @ctlz_nxv8i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv8i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -1094,8 +1094,8 @@ define @ctlz_nxv16i32( %va) { ; ; CHECK-F-LABEL: ctlz_nxv16i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -1107,8 +1107,8 @@ define @ctlz_nxv16i32( %va) { ; ; CHECK-D-LABEL: ctlz_nxv16i32: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: vsrl.vi v8, v8, 23 ; CHECK-D-NEXT: li a1, 158 @@ -1234,8 +1234,8 @@ define @ctlz_nxv1i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32F-NEXT: vmv.v.x v9, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vwsubu.wv v9, v9, v8 @@ -1262,8 +1262,8 @@ define @ctlz_nxv1i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv1i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -1390,8 +1390,8 @@ define @ctlz_nxv2i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32F-NEXT: vmv.v.x v10, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vwsubu.wv v10, v10, v8 @@ -1418,8 +1418,8 @@ define @ctlz_nxv2i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv2i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -1546,8 +1546,8 @@ define @ctlz_nxv4i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32F-NEXT: vmv.v.x v12, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vwsubu.wv v12, v12, v8 @@ -1574,8 +1574,8 @@ define @ctlz_nxv4i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv4i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -1702,8 +1702,8 @@ define @ctlz_nxv8i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32F-NEXT: vmv.v.x v16, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v24, v8 ; RV32F-NEXT: vsrl.vi v8, v24, 23 ; RV32F-NEXT: vwsubu.wv v16, v16, v8 @@ -1730,8 +1730,8 @@ define @ctlz_nxv8i64( %va) { ; ; CHECK-D-LABEL: ctlz_nxv8i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -2497,8 +2497,8 @@ define @ctlz_zero_undef_nxv1i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv1i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2564,8 +2564,8 @@ define @ctlz_zero_undef_nxv2i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv2i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2631,8 +2631,8 @@ define @ctlz_zero_undef_nxv4i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv4i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2698,8 +2698,8 @@ define @ctlz_zero_undef_nxv8i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv8i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2765,8 +2765,8 @@ define @ctlz_zero_undef_nxv16i32( %va) { ; ; CHECK-F-LABEL: ctlz_zero_undef_nxv16i32: ; CHECK-F: # %bb.0: -; CHECK-F-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-F-NEXT: fsrmi a0, 1 +; CHECK-F-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-F-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-F-NEXT: vsrl.vi v8, v8, 23 ; CHECK-F-NEXT: li a1, 158 @@ -2776,8 +2776,8 @@ define @ctlz_zero_undef_nxv16i32( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv16i32: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: vsrl.vi v8, v8, 23 ; CHECK-D-NEXT: li a1, 158 @@ -2900,8 +2900,8 @@ define @ctlz_zero_undef_nxv1i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32F-NEXT: vmv.v.x v9, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vwsubu.wv v9, v9, v8 @@ -2923,8 +2923,8 @@ define @ctlz_zero_undef_nxv1i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv1i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -3048,8 +3048,8 @@ define @ctlz_zero_undef_nxv2i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; RV32F-NEXT: vmv.v.x v10, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vwsubu.wv v10, v10, v8 @@ -3071,8 +3071,8 @@ define @ctlz_zero_undef_nxv2i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv2i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -3196,8 +3196,8 @@ define @ctlz_zero_undef_nxv4i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32F-NEXT: vmv.v.x v12, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vwsubu.wv v12, v12, v8 @@ -3219,8 +3219,8 @@ define @ctlz_zero_undef_nxv4i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv4i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 @@ -3345,8 +3345,8 @@ define @ctlz_zero_undef_nxv8i64( %va) { ; RV32F-NEXT: li a0, 190 ; RV32F-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV32F-NEXT: vmv.v.x v8, a0 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v24, v16 ; RV32F-NEXT: vsrl.vi v16, v24, 23 ; RV32F-NEXT: vwsubu.wv v8, v8, v16 @@ -3367,8 +3367,8 @@ define @ctlz_zero_undef_nxv8i64( %va) { ; ; CHECK-D-LABEL: ctlz_zero_undef_nxv8i64: ; CHECK-D: # %bb.0: -; CHECK-D-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-D-NEXT: fsrmi a0, 1 +; CHECK-D-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-D-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-D-NEXT: li a1, 52 ; CHECK-D-NEXT: vsrl.vx v8, v8, a1 diff --git a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll index 2a75e5ce7175..86086f5dc88f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll @@ -937,15 +937,15 @@ declare @llvm.vp.ctlz.nxv16i32(, i1 immar define @vp_ctlz_nxv16i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv16i32: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i32: @@ -960,15 +960,15 @@ define @vp_ctlz_nxv16i32( %va, @vp_ctlz_nxv16i32_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv16i32_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vsrl.vi v8, v8, 23 -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 32 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 32 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i32_unmasked: @@ -985,16 +985,16 @@ declare @llvm.vp.ctlz.nxv1i64(, i1 immarg, define @vp_ctlz_nxv1i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv1i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i64: @@ -1009,16 +1009,16 @@ define @vp_ctlz_nxv1i64( %va, @vp_ctlz_nxv1i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv1i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv1i64_unmasked: @@ -1035,16 +1035,16 @@ declare @llvm.vp.ctlz.nxv2i64(, i1 immarg, define @vp_ctlz_nxv2i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv2i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i64: @@ -1059,16 +1059,16 @@ define @vp_ctlz_nxv2i64( %va, @vp_ctlz_nxv2i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv2i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv2i64_unmasked: @@ -1085,16 +1085,16 @@ declare @llvm.vp.ctlz.nxv4i64(, i1 immarg, define @vp_ctlz_nxv4i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv4i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i64: @@ -1109,16 +1109,16 @@ define @vp_ctlz_nxv4i64( %va, @vp_ctlz_nxv4i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv4i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv4i64_unmasked: @@ -1135,16 +1135,16 @@ declare @llvm.vp.ctlz.nxv7i64(, i1 immarg, define @vp_ctlz_nxv7i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv7i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv7i64: @@ -1159,16 +1159,16 @@ define @vp_ctlz_nxv7i64( %va, @vp_ctlz_nxv7i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv7i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv7i64_unmasked: @@ -1185,16 +1185,16 @@ declare @llvm.vp.ctlz.nxv8i64(, i1 immarg, define @vp_ctlz_nxv8i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv8i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i64: @@ -1209,16 +1209,16 @@ define @vp_ctlz_nxv8i64( %va, @vp_ctlz_nxv8i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_nxv8i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: li a1, 64 -; CHECK-NEXT: vminu.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: li a0, 64 +; CHECK-NEXT: vminu.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv8i64_unmasked: @@ -1244,10 +1244,10 @@ define @vp_ctlz_nxv16i64( %va, @vp_ctlz_nxv16i64( %va, @vp_ctlz_nxv16i64_unmasked( %va, i ; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: and a2, a3, a2 +; CHECK-NEXT: fsrmi a3, 1 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a2, 1 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16 -; CHECK-NEXT: fsrm a2 +; CHECK-NEXT: fsrm a3 ; CHECK-NEXT: li a2, 52 ; CHECK-NEXT: vsrl.vx v16, v16, a2 ; CHECK-NEXT: li a3, 1086 @@ -1315,13 +1315,13 @@ define @vp_ctlz_nxv16i64_unmasked( %va, i ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: .LBB47_2: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vsrl.vx v8, v8, a2 ; CHECK-NEXT: vrsub.vx v8, v8, a3 ; CHECK-NEXT: vminu.vx v8, v8, a4 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_nxv16i64_unmasked: @@ -2198,13 +2198,13 @@ define @vp_ctlz_zero_undef_nxv8i32_unmasked( @vp_ctlz_zero_undef_nxv16i32( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t ; CHECK-NEXT: vsrl.vi v8, v8, 23, v0.t -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32: @@ -2219,13 +2219,13 @@ define @vp_ctlz_zero_undef_nxv16i32( %va, define @vp_ctlz_zero_undef_nxv16i32_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 ; CHECK-NEXT: vsrl.vi v8, v8, 23 -; CHECK-NEXT: li a1, 158 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 158 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i32_unmasked: @@ -2241,14 +2241,14 @@ define @vp_ctlz_zero_undef_nxv16i32_unmasked( @vp_ctlz_zero_undef_nxv1i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64: @@ -2263,14 +2263,14 @@ define @vp_ctlz_zero_undef_nxv1i64( %va, @vp_ctlz_zero_undef_nxv1i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv1i64_unmasked: @@ -2286,14 +2286,14 @@ define @vp_ctlz_zero_undef_nxv1i64_unmasked( @vp_ctlz_zero_undef_nxv2i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64: @@ -2308,14 +2308,14 @@ define @vp_ctlz_zero_undef_nxv2i64( %va, @vp_ctlz_zero_undef_nxv2i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv2i64_unmasked: @@ -2331,14 +2331,14 @@ define @vp_ctlz_zero_undef_nxv2i64_unmasked( @vp_ctlz_zero_undef_nxv4i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64: @@ -2353,14 +2353,14 @@ define @vp_ctlz_zero_undef_nxv4i64( %va, @vp_ctlz_zero_undef_nxv4i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv4i64_unmasked: @@ -2376,14 +2376,14 @@ define @vp_ctlz_zero_undef_nxv4i64_unmasked( @vp_ctlz_zero_undef_nxv7i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64: @@ -2398,14 +2398,14 @@ define @vp_ctlz_zero_undef_nxv7i64( %va, @vp_ctlz_zero_undef_nxv7i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv7i64_unmasked: @@ -2421,14 +2421,14 @@ define @vp_ctlz_zero_undef_nxv7i64_unmasked( @vp_ctlz_zero_undef_nxv8i64( %va, %m, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1, v0.t -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0, v0.t +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0, v0.t +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64: @@ -2443,14 +2443,14 @@ define @vp_ctlz_zero_undef_nxv8i64( %va, @vp_ctlz_zero_undef_nxv8i64_unmasked( %va, i32 zeroext %evl) { ; CHECK-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: li a1, 52 -; CHECK-NEXT: vsrl.vx v8, v8, a1 -; CHECK-NEXT: li a1, 1086 -; CHECK-NEXT: vrsub.vx v8, v8, a1 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: li a0, 52 +; CHECK-NEXT: vsrl.vx v8, v8, a0 +; CHECK-NEXT: li a0, 1086 +; CHECK-NEXT: vrsub.vx v8, v8, a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv8i64_unmasked: @@ -2474,10 +2474,10 @@ define @vp_ctlz_zero_undef_nxv16i64( %va, ; CHECK-NEXT: sltu a3, a0, a2 ; CHECK-NEXT: addi a3, a3, -1 ; CHECK-NEXT: and a2, a3, a2 +; CHECK-NEXT: fsrmi a3, 1 ; CHECK-NEXT: vsetvli zero, a2, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a2, 1 ; CHECK-NEXT: vfcvt.f.xu.v v16, v16, v0.t -; CHECK-NEXT: fsrm a2 +; CHECK-NEXT: fsrm a3 ; CHECK-NEXT: li a2, 52 ; CHECK-NEXT: vsrl.vx v16, v16, a2, v0.t ; CHECK-NEXT: li a3, 1086 @@ -2486,13 +2486,13 @@ define @vp_ctlz_zero_undef_nxv16i64( %va, ; CHECK-NEXT: # %bb.1: ; CHECK-NEXT: mv a0, a1 ; CHECK-NEXT: .LBB94_2: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8, v0.t ; CHECK-NEXT: vsrl.vx v8, v8, a2, v0.t ; CHECK-NEXT: vrsub.vx v8, v8, a3, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; CHECK-ZVBB-LABEL: vp_ctlz_zero_undef_nxv16i64: @@ -2528,10 +2528,10 @@ define @vp_ctlz_zero_undef_nxv16i64_unmasked( @vp_ctlz_zero_undef_nxv16i64_unmasked( @cttz_nxv1i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v9, v8 ; RV32F-NEXT: vsrl.vi v8, v9, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma @@ -1237,8 +1237,8 @@ define @cttz_nxv1i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v9, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v9 ; RV64F-NEXT: vsrl.vi v9, v10, 23 ; RV64F-NEXT: li a1, 127 @@ -1381,8 +1381,8 @@ define @cttz_nxv2i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma @@ -1399,8 +1399,8 @@ define @cttz_nxv2i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v10, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v12, v10 ; RV64F-NEXT: vsrl.vi v10, v12, 23 ; RV64F-NEXT: li a1, 127 @@ -1543,8 +1543,8 @@ define @cttz_nxv4i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v12, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v12 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma @@ -1561,8 +1561,8 @@ define @cttz_nxv4i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64F-NEXT: vrsub.vi v12, v8, 0 ; RV64F-NEXT: vand.vv v12, v8, v12 -; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v16, v12 ; RV64F-NEXT: vsrl.vi v12, v16, 23 ; RV64F-NEXT: li a1, 127 @@ -1705,8 +1705,8 @@ define @cttz_nxv8i64( %va) { ; RV32F-NEXT: vmseq.vx v0, v8, zero ; RV32F-NEXT: vrsub.vi v16, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v16 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma @@ -1723,8 +1723,8 @@ define @cttz_nxv8i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64F-NEXT: vrsub.vi v16, v8, 0 ; RV64F-NEXT: vand.vv v16, v8, v16 -; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v24, v16 ; RV64F-NEXT: vsrl.vi v16, v24, 23 ; RV64F-NEXT: li a1, 127 @@ -2892,8 +2892,8 @@ define @cttz_zero_undef_nxv1i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v9, v8 ; RV32F-NEXT: vsrl.vi v8, v9, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m1, ta, ma @@ -2908,8 +2908,8 @@ define @cttz_zero_undef_nxv1i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v9, v8 ; RV64F-NEXT: vsrl.vi v9, v9, 23 ; RV64F-NEXT: li a1, 127 @@ -3026,8 +3026,8 @@ define @cttz_zero_undef_nxv2i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: vsrl.vi v8, v10, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m2, ta, ma @@ -3042,8 +3042,8 @@ define @cttz_zero_undef_nxv2i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v8 ; RV64F-NEXT: vsrl.vi v10, v10, 23 ; RV64F-NEXT: li a1, 127 @@ -3160,8 +3160,8 @@ define @cttz_zero_undef_nxv4i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32F-NEXT: vrsub.vi v12, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v12 -; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: vsrl.vi v8, v12, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m4, ta, ma @@ -3176,8 +3176,8 @@ define @cttz_zero_undef_nxv4i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64F-NEXT: vrsub.vi v12, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v12 -; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v12, v8 ; RV64F-NEXT: vsrl.vi v12, v12, 23 ; RV64F-NEXT: li a1, 127 @@ -3294,8 +3294,8 @@ define @cttz_zero_undef_nxv8i64( %va) { ; RV32F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV32F-NEXT: vrsub.vi v16, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v16 -; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: fsrmi a0, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v16, v8 ; RV32F-NEXT: vsrl.vi v8, v16, 23 ; RV32F-NEXT: vsetvli zero, zero, e64, m8, ta, ma @@ -3310,8 +3310,8 @@ define @cttz_zero_undef_nxv8i64( %va) { ; RV64F-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; RV64F-NEXT: vrsub.vi v16, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v16 -; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: fsrmi a0, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v16, v8 ; RV64F-NEXT: vsrl.vi v16, v16, 23 ; RV64F-NEXT: li a1, 127 diff --git a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll index ee9ad097b442..8c63c2d4be8c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/double-round-conv.ll @@ -677,8 +677,8 @@ define @ceil_nxv1f64_to_ui16( %x) { define @ceil_nxv1f64_to_si32( %x) { ; RV32-LABEL: ceil_nxv1f64_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfncvt.x.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -686,8 +686,8 @@ define @ceil_nxv1f64_to_si32( %x) { ; ; RV64-LABEL: ceil_nxv1f64_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfncvt.x.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -700,8 +700,8 @@ define @ceil_nxv1f64_to_si32( %x) { define @ceil_nxv1f64_to_ui32( %x) { ; RV32-LABEL: ceil_nxv1f64_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -709,8 +709,8 @@ define @ceil_nxv1f64_to_ui32( %x) { ; ; RV64-LABEL: ceil_nxv1f64_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -723,16 +723,16 @@ define @ceil_nxv1f64_to_ui32( %x) { define @ceil_nxv1f64_to_si64( %x) { ; RV32-LABEL: ceil_nxv1f64_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f64_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -744,16 +744,16 @@ define @ceil_nxv1f64_to_si64( %x) { define @ceil_nxv1f64_to_ui64( %x) { ; RV32-LABEL: ceil_nxv1f64_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f64_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -951,8 +951,8 @@ define @ceil_nxv4f64_to_ui16( %x) { define @ceil_nxv4f64_to_si32( %x) { ; RV32-LABEL: ceil_nxv4f64_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfncvt.x.f.w v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v12 @@ -960,8 +960,8 @@ define @ceil_nxv4f64_to_si32( %x) { ; ; RV64-LABEL: ceil_nxv4f64_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfncvt.x.f.w v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v12 @@ -974,8 +974,8 @@ define @ceil_nxv4f64_to_si32( %x) { define @ceil_nxv4f64_to_ui32( %x) { ; RV32-LABEL: ceil_nxv4f64_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v12 @@ -983,8 +983,8 @@ define @ceil_nxv4f64_to_ui32( %x) { ; ; RV64-LABEL: ceil_nxv4f64_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v12 @@ -997,16 +997,16 @@ define @ceil_nxv4f64_to_ui32( %x) { define @ceil_nxv4f64_to_si64( %x) { ; RV32-LABEL: ceil_nxv4f64_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f64_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -1018,16 +1018,16 @@ define @ceil_nxv4f64_to_si64( %x) { define @ceil_nxv4f64_to_ui64( %x) { ; RV32-LABEL: ceil_nxv4f64_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f64_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll index 5d024f140fd5..3e2af7e8267b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ceil-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_ceil_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_ceil_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_ceil_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_ceil_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 3 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_ceil_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext %e ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 3 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_ceil_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_ceil_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_ceil_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %evl ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_ceil_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_ceil_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_ceil_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_ceil_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext %e ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_ceil_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_ceil_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_ceil_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroex ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll index 277146cc1403..49e5a1c79c43 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-ctlz.ll @@ -353,8 +353,8 @@ define void @ctlz_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v9, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v10, 23 @@ -762,8 +762,8 @@ define void @ctlz_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v10, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v12, 23 @@ -1152,8 +1152,8 @@ define void @ctlz_zero_undef_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v9, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v10, 23 @@ -1537,8 +1537,8 @@ define void @ctlz_zero_undef_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: li a1, 190 ; RV32F-NEXT: vmv.v.x v10, a1 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v12, 23 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll index 8c8da6d1e003..ea3a78ae0bec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-cttz.ll @@ -336,8 +336,8 @@ define void @cttz_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v9, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v9 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v9, v10, 23 @@ -357,8 +357,8 @@ define void @cttz_v2i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v9, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v9 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v9, v10, 23 @@ -737,8 +737,8 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v10, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v12, v10 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v10, v12, 23 @@ -758,8 +758,8 @@ define void @cttz_v4i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v10, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v12, v10 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v10, v12, 23 @@ -1115,8 +1115,8 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v9, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v9 -; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v9, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v9, 23 @@ -1133,8 +1133,8 @@ define void @cttz_zero_undef_v2i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v9, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v9 -; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v9, v8 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v8, v9, 23 @@ -1486,8 +1486,8 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind { ; RV32F-NEXT: vle64.v v8, (a0) ; RV32F-NEXT: vrsub.vi v10, v8, 0 ; RV32F-NEXT: vand.vv v8, v8, v10 -; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: fsrmi a1, 1 +; RV32F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV32F-NEXT: vfncvt.f.xu.w v10, v8 ; RV32F-NEXT: fsrm a1 ; RV32F-NEXT: vsrl.vi v8, v10, 23 @@ -1504,8 +1504,8 @@ define void @cttz_zero_undef_v4i64(ptr %x, ptr %y) nounwind { ; RV64F-NEXT: vle64.v v8, (a0) ; RV64F-NEXT: vrsub.vi v10, v8, 0 ; RV64F-NEXT: vand.vv v8, v8, v10 -; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: fsrmi a1, 1 +; RV64F-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; RV64F-NEXT: vfncvt.f.xu.w v10, v8 ; RV64F-NEXT: fsrm a1 ; RV64F-NEXT: vsrl.vi v8, v10, 23 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll index 6c2be509f7c2..287dd510674d 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-floor-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_floor_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_floor_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_floor_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_floor_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 2 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_floor_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 2 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_floor_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_floor_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_floor_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_floor_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_floor_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_floor_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_floor_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_floor_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_floor_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_floor_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 2 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll index 6f045349423c..716cf7b0f46f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-round-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_round_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_round_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_round_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_round_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext %evl) ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_round_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 4 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_round_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_round_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_round_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_round_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext %ev ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_round_v16f32(<16 x float> %va, <16 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_round_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_round_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_round_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroext % ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_round_v15f64(<15 x double> %va, <15 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_round_v16f64(<16 x double> %va, <16 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_round_v32f64(<32 x double> %va, <32 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 4 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll index 738d7e37c50b..603f9397dc90 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundeven-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_roundeven_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_roundeven_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext % ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_roundeven_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext % ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 0 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_roundeven_v16f16(<16 x half> %va, <16 x i1> %m, i32 zeroe ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_roundeven_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_roundeven_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_roundeven_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroext ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_roundeven_v16f32(<16 x float> %va, <16 x i1> %m, i32 zer ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_roundeven_v2f64(<2 x double> %va, <2 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_roundeven_v4f64(<4 x double> %va, <4 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_roundeven_v8f64(<8 x double> %va, <8 x i1> %m, i32 zeroe ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_roundeven_v15f64(<15 x double> %va, <15 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_roundeven_v16f64(<16 x double> %va, <16 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_roundeven_v32f64(<32 x double> %va, <32 x i1> %m, i32 z ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll index 6f5b7875266b..a5adfc36887a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-roundtozero-vp.ll @@ -19,8 +19,8 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf4, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -38,8 +38,8 @@ define <2 x half> @vp_roundtozero_v2f16(<2 x half> %va, <2 x i1> %m, i32 zeroext ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -101,8 +101,8 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, mf2, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -120,8 +120,8 @@ define <4 x half> @vp_roundtozero_v4f16(<4 x half> %va, <4 x i1> %m, i32 zeroext ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v0, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v9, v0.t ; ZVFHMIN-NEXT: fsrm a0 ; ZVFHMIN-NEXT: vfcvt.f.x.v v8, v8, v0.t @@ -183,8 +183,8 @@ define <8 x half> @vp_roundtozero_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext ; ZVFH-NEXT: vfabs.v v9, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, mu ; ZVFH-NEXT: vmflt.vf v0, v9, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; ZVFH-NEXT: vfcvt.x.f.v v9, v8, v0.t ; ZVFH-NEXT: fsrm a0 ; ZVFH-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -203,8 +203,8 @@ define <8 x half> @vp_roundtozero_v8f16(<8 x half> %va, <8 x i1> %m, i32 zeroext ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v9, v12, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v9 ; ZVFHMIN-NEXT: vfcvt.x.f.v v12, v10, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -268,8 +268,8 @@ define <16 x half> @vp_roundtozero_v16f16(<16 x half> %va, <16 x i1> %m, i32 zer ; ZVFH-NEXT: vfabs.v v12, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, mu ; ZVFH-NEXT: vmflt.vf v10, v12, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m2, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v10 ; ZVFH-NEXT: vfcvt.x.f.v v12, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -289,8 +289,8 @@ define <16 x half> @vp_roundtozero_v16f16(<16 x half> %va, <16 x i1> %m, i32 zer ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v10, v16, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v10 ; ZVFHMIN-NEXT: vfcvt.x.f.v v16, v12, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -353,8 +353,8 @@ define <2 x float> @vp_roundtozero_v2f32(<2 x float> %va, <2 x i1> %m, i32 zeroe ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, mf2, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -395,8 +395,8 @@ define <4 x float> @vp_roundtozero_v4f32(<4 x float> %va, <4 x i1> %m, i32 zeroe ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -438,8 +438,8 @@ define <8 x float> @vp_roundtozero_v8f32(<8 x float> %va, <8 x i1> %m, i32 zeroe ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -482,8 +482,8 @@ define <16 x float> @vp_roundtozero_v16f32(<16 x float> %va, <16 x i1> %m, i32 z ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -525,8 +525,8 @@ define <2 x double> @vp_roundtozero_v2f64(<2 x double> %va, <2 x i1> %m, i32 zer ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -568,8 +568,8 @@ define <4 x double> @vp_roundtozero_v4f64(<4 x double> %va, <4 x i1> %m, i32 zer ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -612,8 +612,8 @@ define <8 x double> @vp_roundtozero_v8f64(<8 x double> %va, <8 x i1> %m, i32 zer ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -656,8 +656,8 @@ define <15 x double> @vp_roundtozero_v15f64(<15 x double> %va, <15 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -700,8 +700,8 @@ define <16 x double> @vp_roundtozero_v16f64(<16 x double> %va, <16 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -764,8 +764,8 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a1, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a1 @@ -788,8 +788,8 @@ define <32 x double> @vp_roundtozero_v32f64(<32 x double> %va, <32 x i1> %m, i32 ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll index 70b547759938..600290a62515 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vaaddu.ll @@ -5,8 +5,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -20,8 +20,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vx_v8i8_floor(<8 x i8> %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_v8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -53,8 +53,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor_sexti16(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vv_v8i8_floor_zexti32(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_floor_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i32> @@ -83,8 +83,8 @@ define <8 x i8> @vaaddu_vv_v8i8_floor_lshr2(<8 x i8> %x, <8 x i8> %y) { define <8 x i16> @vaaddu_vv_v8i16_floor(<8 x i16> %x, <8 x i16> %y) { ; CHECK-LABEL: vaaddu_vv_v8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -98,8 +98,8 @@ define <8 x i16> @vaaddu_vv_v8i16_floor(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @vaaddu_vx_v8i16_floor(<8 x i16> %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_v8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -115,8 +115,8 @@ define <8 x i16> @vaaddu_vx_v8i16_floor(<8 x i16> %x, i16 %y) { define <8 x i32> @vaaddu_vv_v8i32_floor(<8 x i32> %x, <8 x i32> %y) { ; CHECK-LABEL: vaaddu_vv_v8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -130,8 +130,8 @@ define <8 x i32> @vaaddu_vv_v8i32_floor(<8 x i32> %x, <8 x i32> %y) { define <8 x i32> @vaaddu_vx_v8i32_floor(<8 x i32> %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_v8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -147,8 +147,8 @@ define <8 x i32> @vaaddu_vx_v8i32_floor(<8 x i32> %x, i32 %y) { define <8 x i64> @vaaddu_vv_v8i64_floor(<8 x i64> %x, <8 x i64> %y) { ; CHECK-LABEL: vaaddu_vv_v8i64_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> @@ -197,8 +197,8 @@ define <8 x i64> @vaaddu_vx_v8i64_floor(<8 x i64> %x, i64 %y) { ; ; RV64-LABEL: vaaddu_vx_v8i64_floor: ; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: csrwi vxrm, 2 +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> @@ -214,8 +214,8 @@ define <8 x i64> @vaaddu_vx_v8i64_floor(<8 x i64> %x, i64 %y) { define <8 x i8> @vaaddu_vv_v8i8_ceil(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -230,8 +230,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vx_v8i8_ceil(<8 x i8> %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_v8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i16> @@ -267,8 +267,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_sexti16(<8 x i8> %x, <8 x i8> %y) { define <8 x i8> @vaaddu_vv_v8i8_ceil_zexti32(<8 x i8> %x, <8 x i8> %y) { ; CHECK-LABEL: vaaddu_vv_v8i8_ceil_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i8> %x to <8 x i32> @@ -305,8 +305,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_add2(<8 x i8> %x, <8 x i8> %y) { ; CHECK-NEXT: vsetivli zero, 8, e8, mf2, ta, ma ; CHECK-NEXT: vwaddu.vv v10, v8, v9 ; CHECK-NEXT: li a0, 2 -; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli zero, zero, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v10, a0 ; CHECK-NEXT: vsetvli zero, zero, e8, mf2, ta, ma ; CHECK-NEXT: vnsrl.wi v8, v8, 0 @@ -323,8 +323,8 @@ define <8 x i8> @vaaddu_vv_v8i8_ceil_add2(<8 x i8> %x, <8 x i8> %y) { define <8 x i16> @vaaddu_vv_v8i16_ceil(<8 x i16> %x, <8 x i16> %y) { ; CHECK-LABEL: vaaddu_vv_v8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -339,8 +339,8 @@ define <8 x i16> @vaaddu_vv_v8i16_ceil(<8 x i16> %x, <8 x i16> %y) { define <8 x i16> @vaaddu_vx_v8i16_ceil(<8 x i16> %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_v8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i16> %x to <8 x i32> @@ -357,8 +357,8 @@ define <8 x i16> @vaaddu_vx_v8i16_ceil(<8 x i16> %x, i16 %y) { define <8 x i32> @vaaddu_vv_v8i32_ceil(<8 x i32> %x, <8 x i32> %y) { ; CHECK-LABEL: vaaddu_vv_v8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -373,8 +373,8 @@ define <8 x i32> @vaaddu_vv_v8i32_ceil(<8 x i32> %x, <8 x i32> %y) { define <8 x i32> @vaaddu_vx_v8i32_ceil(<8 x i32> %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_v8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext <8 x i32> %x to <8 x i64> @@ -391,8 +391,8 @@ define <8 x i32> @vaaddu_vx_v8i32_ceil(<8 x i32> %x, i32 %y) { define <8 x i64> @vaaddu_vv_v8i64_ceil(<8 x i64> %x, <8 x i64> %y) { ; CHECK-LABEL: vaaddu_vv_v8i64_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> @@ -443,8 +443,8 @@ define <8 x i64> @vaaddu_vx_v8i64_ceil(<8 x i64> %x, i64 %y) { ; ; RV64-LABEL: vaaddu_vx_v8i64_ceil: ; RV64: # %bb.0: -; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: csrwi vxrm, 0 +; RV64-NEXT: vsetivli zero, 8, e64, m4, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext <8 x i64> %x to <8 x i128> diff --git a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll index 9dcb6d211cb9..b7661bd826fe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/float-round-conv.ll @@ -487,8 +487,8 @@ define @ceil_nxv1f32_to_ui8( %x) { define @ceil_nxv1f32_to_si16( %x) { ; RV32-LABEL: ceil_nxv1f32_to_si16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV32-NEXT: vfncvt.x.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -496,8 +496,8 @@ define @ceil_nxv1f32_to_si16( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_si16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV64-NEXT: vfncvt.x.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -510,8 +510,8 @@ define @ceil_nxv1f32_to_si16( %x) { define @ceil_nxv1f32_to_ui16( %x) { ; RV32-LABEL: ceil_nxv1f32_to_ui16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -519,8 +519,8 @@ define @ceil_nxv1f32_to_ui16( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_ui16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -533,16 +533,16 @@ define @ceil_nxv1f32_to_ui16( %x) { define @ceil_nxv1f32_to_si32( %x) { ; RV32-LABEL: ceil_nxv1f32_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f32_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -554,16 +554,16 @@ define @ceil_nxv1f32_to_si32( %x) { define @ceil_nxv1f32_to_ui32( %x) { ; RV32-LABEL: ceil_nxv1f32_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv1f32_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -575,8 +575,8 @@ define @ceil_nxv1f32_to_ui32( %x) { define @ceil_nxv1f32_to_si64( %x) { ; RV32-LABEL: ceil_nxv1f32_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfwcvt.x.f.v v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -584,8 +584,8 @@ define @ceil_nxv1f32_to_si64( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfwcvt.x.f.v v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -598,8 +598,8 @@ define @ceil_nxv1f32_to_si64( %x) { define @ceil_nxv1f32_to_ui64( %x) { ; RV32-LABEL: ceil_nxv1f32_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV32-NEXT: vfwcvt.xu.f.v v9, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv1r.v v8, v9 @@ -607,8 +607,8 @@ define @ceil_nxv1f32_to_ui64( %x) { ; ; RV64-LABEL: ceil_nxv1f32_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; RV64-NEXT: vfwcvt.xu.f.v v9, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv1r.v v8, v9 @@ -713,8 +713,8 @@ define @ceil_nxv4f32_to_ui8( %x) { define @ceil_nxv4f32_to_si16( %x) { ; RV32-LABEL: ceil_nxv4f32_to_si16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV32-NEXT: vfncvt.x.f.w v10, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v10 @@ -722,8 +722,8 @@ define @ceil_nxv4f32_to_si16( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_si16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV64-NEXT: vfncvt.x.f.w v10, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v10 @@ -736,8 +736,8 @@ define @ceil_nxv4f32_to_si16( %x) { define @ceil_nxv4f32_to_ui16( %x) { ; RV32-LABEL: ceil_nxv4f32_to_ui16: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV32-NEXT: vfncvt.xu.f.w v10, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv.v.v v8, v10 @@ -745,8 +745,8 @@ define @ceil_nxv4f32_to_ui16( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_ui16: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; RV64-NEXT: vfncvt.xu.f.w v10, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv.v.v v8, v10 @@ -759,16 +759,16 @@ define @ceil_nxv4f32_to_ui16( %x) { define @ceil_nxv4f32_to_si32( %x) { ; RV32-LABEL: ceil_nxv4f32_to_si32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfcvt.x.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f32_to_si32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfcvt.x.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -780,16 +780,16 @@ define @ceil_nxv4f32_to_si32( %x) { define @ceil_nxv4f32_to_ui32( %x) { ; RV32-LABEL: ceil_nxv4f32_to_ui32: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfcvt.xu.f.v v8, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: ret ; ; RV64-LABEL: ceil_nxv4f32_to_ui32: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfcvt.xu.f.v v8, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: ret @@ -801,8 +801,8 @@ define @ceil_nxv4f32_to_ui32( %x) { define @ceil_nxv4f32_to_si64( %x) { ; RV32-LABEL: ceil_nxv4f32_to_si64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfwcvt.x.f.v v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv4r.v v8, v12 @@ -810,8 +810,8 @@ define @ceil_nxv4f32_to_si64( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_si64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfwcvt.x.f.v v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv4r.v v8, v12 @@ -824,8 +824,8 @@ define @ceil_nxv4f32_to_si64( %x) { define @ceil_nxv4f32_to_ui64( %x) { ; RV32-LABEL: ceil_nxv4f32_to_ui64: ; RV32: # %bb.0: -; RV32-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV32-NEXT: fsrmi a0, 3 +; RV32-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV32-NEXT: vfwcvt.xu.f.v v12, v8 ; RV32-NEXT: fsrm a0 ; RV32-NEXT: vmv4r.v v8, v12 @@ -833,8 +833,8 @@ define @ceil_nxv4f32_to_ui64( %x) { ; ; RV64-LABEL: ceil_nxv4f32_to_ui64: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; RV64-NEXT: fsrmi a0, 3 +; RV64-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; RV64-NEXT: vfwcvt.xu.f.v v12, v8 ; RV64-NEXT: fsrm a0 ; RV64-NEXT: vmv4r.v v8, v12 diff --git a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll index 9c4706b2bda7..d464b491bbbe 100644 --- a/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/floor-vp.ll @@ -15,8 +15,8 @@ define @vp_floor_nxv1f16( %va, @vp_floor_nxv2f16( %va, @vp_floor_nxv4f16( %va, @vp_floor_nxv8f16( %va, @vp_floor_nxv16f16( %va, @vp_floor_nxv32f16( %va, @vp_floor_nxv1f32( %va, @vp_floor_nxv2f32( %va, @vp_floor_nxv4f32( %va, @vp_floor_nxv8f32( %va, @vp_floor_nxv16f32( %va, @vp_floor_nxv1f64( %va, @vp_floor_nxv2f64( %va, @vp_floor_nxv4f64( %va, @vp_floor_nxv7f64( %va, @vp_floor_nxv8f64( %va, @vp_floor_nxv16f64( %va, @vp_floor_nxv16f64( %va, @llvm.riscv.vfadd.nxv1f32.nxv1f32( define @test( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: test: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: vfadd.vv v8, v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; UNOPT-LABEL: test: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v8 ; UNOPT-NEXT: fsrm a0 @@ -48,20 +48,20 @@ entry: define @test2( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 ; CHECK-NEXT: fsrmi 1 ; CHECK-NEXT: vfadd.vv v8, v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret ; ; UNOPT-LABEL: test2: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: fsrmi a0, 1 ; UNOPT-NEXT: vfadd.vv v8, v8, v8 ; UNOPT-NEXT: fsrm a0 @@ -132,12 +132,12 @@ define @before_call1( %0, @before_call1( %0, @after_call1( %0, @after_call1( %0, @before_asm1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: before_asm1: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret ; ; UNOPT-LABEL: before_asm1: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: #APP ; UNOPT-NEXT: #NO_APP ; UNOPT-NEXT: ret @@ -416,20 +416,20 @@ entry: define @after_asm1( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: after_asm1: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP ; CHECK-NEXT: ret ; ; UNOPT-LABEL: after_asm1: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a1, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a1 ; UNOPT-NEXT: #APP ; UNOPT-NEXT: #NO_APP ; UNOPT-NEXT: ret @@ -476,10 +476,10 @@ declare i32 @llvm.get.rounding() define @test5( %0, %1, i64 %2, ptr %p) nounwind { ; CHECK-LABEL: test5: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a2, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a2 ; CHECK-NEXT: frrm a0 ; CHECK-NEXT: slli a0, a0, 2 ; CHECK-NEXT: lui a2, 66 @@ -492,10 +492,10 @@ define @test5( %0, ; ; UNOPT-LABEL: test5: ; UNOPT: # %bb.0: # %entry +; UNOPT-NEXT: fsrmi a2, 0 ; UNOPT-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; UNOPT-NEXT: fsrmi a0, 0 ; UNOPT-NEXT: vfadd.vv v8, v8, v9 -; UNOPT-NEXT: fsrm a0 +; UNOPT-NEXT: fsrm a2 ; UNOPT-NEXT: frrm a0 ; UNOPT-NEXT: slli a0, a0, 2 ; UNOPT-NEXT: lui a2, 66 @@ -559,10 +559,10 @@ define @after_fsrm2( %0, @after_fsrm3( %0, @llvm.ceil.nxv1f16() define @ceil_nxv1f16_to_si8( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_si8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -263,8 +263,8 @@ define @ceil_nxv1f16_to_si8( %x) { define @ceil_nxv1f16_to_ui8( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_ui8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf8, ta, ma ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -277,8 +277,8 @@ define @ceil_nxv1f16_to_ui8( %x) { define @ceil_nxv1f16_to_si16( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_si16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -290,8 +290,8 @@ define @ceil_nxv1f16_to_si16( %x) { define @ceil_nxv1f16_to_ui16( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_ui16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -303,8 +303,8 @@ define @ceil_nxv1f16_to_ui16( %x) { define @ceil_nxv1f16_to_si32( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_si32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -317,8 +317,8 @@ define @ceil_nxv1f16_to_si32( %x) { define @ceil_nxv1f16_to_ui32( %x) { ; CHECK-LABEL: ceil_nxv1f16_to_ui32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, mf4, ta, ma ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -451,8 +451,8 @@ declare @llvm.ceil.nxv4f16() define @ceil_nxv4f16_to_si8( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_si8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vfncvt.x.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -465,8 +465,8 @@ define @ceil_nxv4f16_to_si8( %x) { define @ceil_nxv4f16_to_ui8( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_ui8: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e8, mf2, ta, ma ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv1r.v v8, v9 @@ -479,8 +479,8 @@ define @ceil_nxv4f16_to_ui8( %x) { define @ceil_nxv4f16_to_si16( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_si16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -492,8 +492,8 @@ define @ceil_nxv4f16_to_si16( %x) { define @ceil_nxv4f16_to_ui16( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_ui16: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -505,8 +505,8 @@ define @ceil_nxv4f16_to_ui16( %x) { define @ceil_nxv4f16_to_si32( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_si32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfwcvt.x.f.v v10, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv2r.v v8, v10 @@ -519,8 +519,8 @@ define @ceil_nxv4f16_to_si32( %x) { define @ceil_nxv4f16_to_ui32( %x) { ; CHECK-LABEL: ceil_nxv4f16_to_ui32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 3 +; CHECK-NEXT: vsetvli a1, zero, e16, m1, ta, ma ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vmv2r.v v8, v10 diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll index d81079da64bd..f87fa3ec6f16 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tama.ll @@ -516,8 +516,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -543,8 +543,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -570,8 +570,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -597,8 +597,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll index c8bff58b00e4..4098270d365a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll @@ -489,8 +489,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -515,8 +515,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -541,8 +541,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -567,8 +567,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll index 409a008ec7cf..4cd7e143be66 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll @@ -489,8 +489,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -515,8 +515,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -541,8 +541,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -567,8 +567,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll b/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll index 90054bcc5f36..c8719e6a2e7c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll @@ -489,8 +489,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -515,8 +515,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -541,8 +541,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8( define @intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vssrl_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vssrl.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -567,8 +567,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll index eb4994914fad..edeac1acf3b0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/round-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/round-vp.ll @@ -19,8 +19,8 @@ define @vp_round_nxv1f16( %va, @vp_round_nxv1f16( %va, @vp_round_nxv2f16( %va, @vp_round_nxv2f16( %va, @vp_round_nxv4f16( %va, @vp_round_nxv4f16( %va, @vp_round_nxv8f16( %va, @vp_round_nxv8f16( %va, @vp_round_nxv16f16( %va, @vp_round_nxv16f16( %va, @vp_round_nxv32f16( %va, @vp_round_nxv32f16( %va, @vp_round_nxv32f16( %va, @vp_round_nxv32f16_unmasked( %va ; ZVFHMIN-NEXT: fmv.w.x fa5, a2 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a2, 4 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v16 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a2 @@ -615,8 +615,8 @@ define @vp_round_nxv1f32( %va, @vp_round_nxv2f32( %va, @vp_round_nxv4f32( %va, @vp_round_nxv8f32( %va, @vp_round_nxv16f32( %va, @vp_round_nxv1f64( %va, @vp_round_nxv2f64( %va, @vp_round_nxv4f64( %va, @vp_round_nxv7f64( %va, @vp_round_nxv8f64( %va, @vp_round_nxv16f64( %va, @vp_round_nxv16f64( %va, @vp_roundeven_nxv1f16( %va, @vp_roundeven_nxv1f16( %va, @vp_roundeven_nxv2f16( %va, @vp_roundeven_nxv2f16( %va, @vp_roundeven_nxv4f16( %va, @vp_roundeven_nxv4f16( %va, @vp_roundeven_nxv8f16( %va, @vp_roundeven_nxv8f16( %va, @vp_roundeven_nxv16f16( %va, @vp_roundeven_nxv16f16( %va, @vp_roundeven_nxv32f16( %va, @vp_roundeven_nxv32f16( %va, @vp_roundeven_nxv32f16( %va, @vp_roundeven_nxv32f16_unmasked( ; ZVFHMIN-NEXT: fmv.w.x fa5, a2 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a2, 0 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v16 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a2 @@ -615,8 +615,8 @@ define @vp_roundeven_nxv1f32( %va, @vp_roundeven_nxv2f32( %va, @vp_roundeven_nxv4f32( %va, @vp_roundeven_nxv8f32( %va, @vp_roundeven_nxv16f32( %va, < ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -831,8 +831,8 @@ define @vp_roundeven_nxv1f64( %va, @vp_roundeven_nxv2f64( %va, @vp_roundeven_nxv4f64( %va, @vp_roundeven_nxv7f64( %va, @vp_roundeven_nxv8f64( %va, @vp_roundeven_nxv16f64( %va, ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a2, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a2 @@ -1092,8 +1092,8 @@ define @vp_roundeven_nxv16f64( %va, ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll index 79c940bdf089..71a53c525551 100644 --- a/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll +++ b/llvm/test/CodeGen/RISCV/rvv/roundtozero-vp.ll @@ -19,8 +19,8 @@ define @vp_roundtozero_nxv1f16( %va, @vp_roundtozero_nxv1f16( %va, @vp_roundtozero_nxv2f16( %va, @vp_roundtozero_nxv2f16( %va, @vp_roundtozero_nxv4f16( %va, @vp_roundtozero_nxv4f16( %va, @vp_roundtozero_nxv8f16( %va, @vp_roundtozero_nxv8f16( %va, @vp_roundtozero_nxv16f16( %va, < ; ZVFH-NEXT: vfabs.v v16, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, mu ; ZVFH-NEXT: vmflt.vf v12, v16, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m4, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v12 ; ZVFH-NEXT: vfcvt.x.f.v v16, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -375,8 +375,8 @@ define @vp_roundtozero_nxv16f16( %va, < ; ZVFHMIN-NEXT: fmv.w.x fa5, a0 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v12, v24, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v12 ; ZVFHMIN-NEXT: vfcvt.x.f.v v24, v16, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -440,8 +440,8 @@ define @vp_roundtozero_nxv32f16( %va, < ; ZVFH-NEXT: vfabs.v v24, v8, v0.t ; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, mu ; ZVFH-NEXT: vmflt.vf v16, v24, fa5, v0.t -; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, ma ; ZVFH-NEXT: fsrmi a0, 1 +; ZVFH-NEXT: vsetvli zero, zero, e16, m8, ta, ma ; ZVFH-NEXT: vmv1r.v v0, v16 ; ZVFH-NEXT: vfcvt.x.f.v v24, v8, v0.t ; ZVFH-NEXT: fsrm a0 @@ -479,8 +479,8 @@ define @vp_roundtozero_nxv32f16( %va, < ; ZVFHMIN-NEXT: fmv.w.x fa5, a2 ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v17, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a2, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v17 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a2 @@ -501,8 +501,8 @@ define @vp_roundtozero_nxv32f16( %va, < ; ZVFHMIN-NEXT: vfabs.v v8, v24, v0.t ; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; ZVFHMIN-NEXT: vmflt.vf v16, v8, fa5, v0.t -; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: fsrmi a0, 1 +; ZVFHMIN-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; ZVFHMIN-NEXT: vmv1r.v v0, v16 ; ZVFHMIN-NEXT: vfcvt.x.f.v v8, v24, v0.t ; ZVFHMIN-NEXT: fsrm a0 @@ -567,8 +567,8 @@ define @vp_roundtozero_nxv32f16_unmasked( @vp_roundtozero_nxv1f32( %va, @vp_roundtozero_nxv2f32( %va, @vp_roundtozero_nxv4f32( %va, @vp_roundtozero_nxv8f32( %va, @vp_roundtozero_nxv16f32( %va, ; CHECK-NEXT: fmv.w.x fa5, a0 ; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e32, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -831,8 +831,8 @@ define @vp_roundtozero_nxv1f64( %va, ; CHECK-NEXT: vfabs.v v9, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, mu ; CHECK-NEXT: vmflt.vf v0, v9, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m1, ta, ma ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t @@ -874,8 +874,8 @@ define @vp_roundtozero_nxv2f64( %va, ; CHECK-NEXT: vfabs.v v12, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, mu ; CHECK-NEXT: vmflt.vf v10, v12, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m2, ta, ma ; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -918,8 +918,8 @@ define @vp_roundtozero_nxv4f64( %va, ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, mu ; CHECK-NEXT: vmflt.vf v12, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma ; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -962,8 +962,8 @@ define @vp_roundtozero_nxv7f64( %va, ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -1006,8 +1006,8 @@ define @vp_roundtozero_nxv8f64( %va, ; CHECK-NEXT: vfabs.v v24, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v16, v24, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: vfcvt.x.f.v v24, v8, v0.t ; CHECK-NEXT: fsrm a0 @@ -1068,8 +1068,8 @@ define @vp_roundtozero_nxv16f64( %v ; CHECK-NEXT: vfabs.v v8, v16, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v25, v8, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a2, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v25 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t ; CHECK-NEXT: fsrm a2 @@ -1092,8 +1092,8 @@ define @vp_roundtozero_nxv16f64( %v ; CHECK-NEXT: vfabs.v v16, v8, v0.t ; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, mu ; CHECK-NEXT: vmflt.vf v24, v16, fa5, v0.t -; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: fsrmi a0, 1 +; CHECK-NEXT: vsetvli zero, zero, e64, m8, ta, ma ; CHECK-NEXT: vmv1r.v v0, v24 ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t ; CHECK-NEXT: fsrm a0 diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll index 8cefbac59ce6..033a1d7e297f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll @@ -215,10 +215,10 @@ declare @llvm.vp.merge.nxv2i32(, @vmerge_vfcvt_rm( %passthru, %a, %m, i32 zeroext %evl) { ; CHECK-LABEL: vmerge_vfcvt_rm: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 2 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 2 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %floor = call @llvm.floor.nxv2f32( %a) diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll index 64b3a6f2b4b3..1a3a1a6c1ee6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll +++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll @@ -919,8 +919,8 @@ entry: define @test_vaaddu( %var_11, i16 zeroext %var_9, %var_5, %var_0) { ; CHECK-LABEL: test_vaaddu: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetivli zero, 3, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetivli zero, 3, e16, mf4, ta, mu ; CHECK-NEXT: vaaddu.vx v9, v8, a0, v0.t ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret @@ -966,13 +966,13 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32( define @vfredusum( %passthru, %x, %y, %m, i64 %vl) { ; CHECK-LABEL: vfredusum: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vmv1r.v v11, v8 ; CHECK-NEXT: vfredusum.vs v11, v9, v10 ; CHECK-NEXT: vsetvli zero, zero, e32, m1, tu, ma ; CHECK-NEXT: vmerge.vvm v8, v8, v11, v0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret %a = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32( %passthru, @@ -1002,10 +1002,10 @@ define @vredsum_allones_mask( %passthru, @vfredusum_allones_mask( %passthru, %x, %y, i64 %vl) { ; CHECK-LABEL: vfredusum_allones_mask: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret %a = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32( %passthru, @@ -1136,10 +1136,10 @@ define @vpmerge_vwsub.w_tied( %passthru, @vpmerge_vfwsub.w_tied( %passthru, %x, %y, %mask, i32 zeroext %vl) { ; CHECK-LABEL: vpmerge_vfwsub.w_tied: ; CHECK: # %bb.0: +; CHECK-NEXT: fsrmi a1, 1 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 1 ; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret %vl.zext = zext i32 %vl to i64 %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( %passthru, %passthru, %y, i64 1, i64 %vl.zext) diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll index b44b57394321..3c19616576f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_x_f_qf.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv1i8.nxv1f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv1i8_nxv1f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv1i8.nxv1f32.iXLen( @@ -64,10 +64,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv2i8.nxv2f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv2i8_nxv2f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv2i8_nxv2f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv2i8.nxv2f32.iXLen( @@ -115,10 +115,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv4i8.nxv4f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv4i8_nxv4f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv4i8_nxv4f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv4i8.nxv4f32.iXLen( @@ -166,10 +166,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv8i8.nxv8f32.iXLen( define @intrinsic_sf_vfnrclip_x_f_qf_nxv8i8_nxv8f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.iXL define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv8i8_nxv8f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv8i8.nxv8f32.iXLen( @@ -217,10 +217,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.nxv16i8.nxv16f32.iXLen define @intrinsic_sf_vfnrclip_x_f_qf_nxv16i8_nxv16f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv16i8.nxv16f32. define @intrinsic_sf_vfnrclip_x_f_qf_mask_nxv16i8_nxv16f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_x_f_qf_mask_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.x.f.qf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.x.f.qf.mask.nxv16i8.nxv16f32.iXLen( diff --git a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll index bc2f7ca7dc86..dbcee311c6e3 100644 --- a/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll +++ b/llvm/test/CodeGen/RISCV/rvv/sf_vfnrclip_xu_f_qf.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv1i8.nxv1f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv1i8_nxv1f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv1i8_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv1i8.nxv1f32.iXLen( @@ -64,10 +64,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv2i8.nxv2f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv2i8_nxv2f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv2i8_nxv2f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv2i8_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv2i8.nxv2f32.iXLen( @@ -115,10 +115,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv4i8.nxv4f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv4i8_nxv4f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv4i8_nxv4f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv4i8_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv4i8.nxv4f32.iXLen( @@ -166,10 +166,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv8i8.nxv8f32.iXLen( define @intrinsic_sf_vfnrclip_xu_f_qf_nxv8i8_nxv8f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.iX define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv8i8_nxv8f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv8i8_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv8i8.nxv8f32.iXLen( @@ -217,10 +217,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.nxv16i8.nxv16f32.iXLe define @intrinsic_sf_vfnrclip_xu_f_qf_nxv16i8_nxv16f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv16i8.nxv16f32 define @intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv16i8_nxv16f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_sf_vfnrclip_xu_f_qf_mask_nxv16i8_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: sf.vfnrclip.xu.f.qf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.sf.vfnrclip.xu.f.qf.mask.nxv16i8.nxv16f32.iXLen( diff --git a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll index 2926a23c8b27..25e3468dcb62 100644 --- a/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/unmasked-tu.ll @@ -110,8 +110,8 @@ declare @llvm.riscv.vaadd.rm.nxv1i8.nxv1i8( define @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vaadd.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vaaddu.rm.nxv1i8.nxv1i8( define @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vaaddu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -199,8 +199,8 @@ declare @llvm.riscv.vasub.rm.nxv1i8.nxv1i8( define @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vasub.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -222,8 +222,8 @@ declare @llvm.riscv.vasubu.rm.nxv1i8.nxv1i8( define @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vasubu.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -950,8 +950,8 @@ declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vnclip.wv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -974,8 +974,8 @@ declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vnclipu.wv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -1271,8 +1271,8 @@ declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vsmul.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -1301,16 +1301,16 @@ define @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64( @llvm.riscv.vssra.nxv1i8.nxv1i8( define @intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vssra_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vssra.vv v8, v9, v10 ; CHECK-NEXT: ret entry: @@ -1400,8 +1400,8 @@ declare @llvm.riscv.vssrl.nxv1i8.nxv1i8( define @intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vssrl_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, tu, ma ; CHECK-NEXT: vssrl.vv v8, v9, v10 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vaadd.ll b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll index 82cd4bf162b9..096e60b6285f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaadd.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vaadd.nxv1i8.nxv1i8( define @intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.nxv1i8( define @intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vaadd.nxv2i8.nxv2i8( define @intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i8.nxv2i8( define @intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vaadd.nxv4i8.nxv4i8( define @intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i8.nxv4i8( define @intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vaadd.nxv8i8.nxv8i8( define @intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i8.nxv8i8( define @intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vaadd.nxv16i8.nxv16i8( define @intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i8.nxv16i8( define @intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vaadd.nxv32i8.nxv32i8( define @intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vaadd.mask.nxv32i8.nxv32i8( define @intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vaadd.nxv64i8.nxv64i8( define @intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vaadd_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vaadd.nxv1i16.nxv1i16( define @intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i16.nxv1i16( define @intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vaadd.nxv2i16.nxv2i16( define @intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i16.nxv2i16( define @intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vaadd.nxv4i16.nxv4i16( define @intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i16.nxv4i16( define @intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vaadd.nxv8i16.nxv8i16( define @intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i16.nxv8i16( define @intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vaadd.nxv16i16.nxv16i16( define @intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i16.nxv16i16( define @intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vaadd.nxv32i16.nxv32i16( define @intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vaadd.nxv1i32.nxv1i32( define @intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i32.nxv1i32( define @intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vaadd.nxv2i32.nxv2i32( define @intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i32.nxv2i32( define @intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vaadd.nxv4i32.nxv4i32( define @intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i32.nxv4i32( define @intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vaadd.nxv8i32.nxv8i32( define @intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i32.nxv8i32( define @intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vaadd.nxv16i32.nxv16i32( define @intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vaadd.nxv1i64.nxv1i64( define @intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( define @intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vaadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vaadd.nxv2i64.nxv2i64( define @intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i64.nxv2i64( define @intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vaadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vaadd.nxv4i64.nxv4i64( define @intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i64.nxv4i64( define @intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vaadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vaadd.nxv8i64.nxv8i64( define @intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vaadd_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vaadd.nxv1i8.i8( define @intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i8.i8( define @intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vaadd.nxv2i8.i8( define @intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i8.i8( define @intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vaadd.nxv4i8.i8( define @intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i8.i8( define @intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vaadd.nxv8i8.i8( define @intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i8.i8( define @intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vaadd.nxv16i8.i8( define @intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i8.i8( define @intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vaadd.nxv32i8.i8( define @intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vaadd.mask.nxv32i8.i8( define @intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vaadd.nxv64i8.i8( define @intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vaadd.mask.nxv64i8.i8( define @intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vaadd.nxv1i16.i16( define @intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i16.i16( define @intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vaadd.nxv2i16.i16( define @intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i16.i16( define @intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vaadd.nxv4i16.i16( define @intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i16.i16( define @intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vaadd.nxv8i16.i16( define @intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i16.i16( define @intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vaadd.nxv16i16.i16( define @intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i16.i16( define @intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vaadd.nxv32i16.i16( define @intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vaadd.mask.nxv32i16.i16( define @intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vaadd.nxv1i32.i32( define @intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vaadd.mask.nxv1i32.i32( define @intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vaadd.nxv2i32.i32( define @intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vaadd.mask.nxv2i32.i32( define @intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vaadd.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vaadd.nxv4i32.i32( define @intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vaadd.mask.nxv4i32.i32( define @intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vaadd.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vaadd.nxv8i32.i32( define @intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vaadd.mask.nxv8i32.i32( define @intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vaadd.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vaadd.nxv16i32.i32( define @intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaadd_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vaadd.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vaadd.mask.nxv16i32.i32( define @intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaadd_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaadd.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vaadd_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaadd_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaadd_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaadd_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaadd_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaadd_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaadd_vx_nxv8i64_nxv8i64_i64( @intrinsic_vaadd_mask_vx_nxv8i64_nxv8i64_i64( @vaaddu_vv_nxv8i8_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -20,8 +20,8 @@ define @vaaddu_vv_nxv8i8_floor( %x, @vaaddu_vx_nxv8i8_floor( %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i8_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -52,8 +52,8 @@ define @vaaddu_vv_nxv8i8_floor_sexti16( %x, < define @vaaddu_vv_nxv8i8_floor_zexti32( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_floor_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -82,8 +82,8 @@ define @vaaddu_vv_nxv8i8_floor_lshr2( %x, @vaaddu_vv_nxv8i16_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext %x to @@ -97,8 +97,8 @@ define @vaaddu_vv_nxv8i16_floor( %x, @vaaddu_vx_nxv8i16_floor( %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i16_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -114,8 +114,8 @@ define @vaaddu_vx_nxv8i16_floor( %x, i16 %y define @vaaddu_vv_nxv8i32_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext %x to @@ -129,8 +129,8 @@ define @vaaddu_vv_nxv8i32_floor( %x, @vaaddu_vx_nxv8i32_floor( %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i32_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -146,8 +146,8 @@ define @vaaddu_vx_nxv8i32_floor( %x, i32 %y define @vaaddu_vv_nxv8i64_floor( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i64_floor: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret %xzv = zext %x to @@ -175,8 +175,8 @@ define @vaaddu_vx_nxv8i64_floor( %x, i64 %y ; ; RV64-LABEL: vaaddu_vx_nxv8i64_floor: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: csrwi vxrm, 2 +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext %x to @@ -192,8 +192,8 @@ define @vaaddu_vx_nxv8i64_floor( %x, i64 %y define @vaaddu_vv_nxv8i8_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -208,8 +208,8 @@ define @vaaddu_vv_nxv8i8_ceil( %x, @vaaddu_vx_nxv8i8_ceil( %x, i8 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i8_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a1, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -245,8 +245,8 @@ define @vaaddu_vv_nxv8i8_ceil_sexti16( %x, @vaaddu_vv_nxv8i8_ceil_zexti32( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i8_ceil_zexti32: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret %xzv = zext %x to @@ -299,8 +299,8 @@ define @vaaddu_vv_nxv8i8_ceil_add2( %x, @vaaddu_vv_nxv8i16_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret %xzv = zext %x to @@ -315,8 +315,8 @@ define @vaaddu_vv_nxv8i16_ceil( %x, @vaaddu_vx_nxv8i16_ceil( %x, i16 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i16_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a1, zero, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -333,8 +333,8 @@ define @vaaddu_vx_nxv8i16_ceil( %x, i16 %y) define @vaaddu_vv_nxv8i32_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret %xzv = zext %x to @@ -349,8 +349,8 @@ define @vaaddu_vv_nxv8i32_ceil( %x, @vaaddu_vx_nxv8i32_ceil( %x, i32 %y) { ; CHECK-LABEL: vaaddu_vx_nxv8i32_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret %xzv = zext %x to @@ -367,8 +367,8 @@ define @vaaddu_vx_nxv8i32_ceil( %x, i32 %y) define @vaaddu_vv_nxv8i64_ceil( %x, %y) { ; CHECK-LABEL: vaaddu_vv_nxv8i64_ceil: ; CHECK: # %bb.0: -; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret %xzv = zext %x to @@ -397,8 +397,8 @@ define @vaaddu_vx_nxv8i64_ceil( %x, i64 %y) ; ; RV64-LABEL: vaaddu_vx_nxv8i64_ceil: ; RV64: # %bb.0: -; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: csrwi vxrm, 0 +; RV64-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; RV64-NEXT: vaaddu.vx v8, v8, a0 ; RV64-NEXT: ret %xzv = zext %x to diff --git a/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll index eba87d7061d3..a15a1932360a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vaaddu.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vaaddu.nxv1i8.nxv1i8( define @intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i8.nxv1i8( define @intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vaaddu.nxv2i8.nxv2i8( define @intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i8.nxv2i8( define @intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vaaddu.nxv4i8.nxv4i8( define @intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i8.nxv4i8( define @intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vaaddu.nxv8i8.nxv8i8( define @intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i8.nxv8i8( define @intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vaaddu.nxv16i8.nxv16i8( define @intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i8.nxv16i8( define @intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vaaddu.nxv32i8.nxv32i8( define @intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vaaddu.mask.nxv32i8.nxv32i8( define @intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vaaddu.nxv64i8.nxv64i8( define @intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vaaddu_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vaaddu.nxv1i16.nxv1i16( define @intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i16.nxv1i16( define @intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vaaddu.nxv2i16.nxv2i16( define @intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i16.nxv2i16( define @intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vaaddu.nxv4i16.nxv4i16( define @intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i16.nxv4i16( define @intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vaaddu.nxv8i16.nxv8i16( define @intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i16.nxv8i16( define @intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vaaddu.nxv16i16.nxv16i16( define @intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i16.nxv16i16( define @intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vaaddu.nxv32i16.nxv32i16( define @intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16( ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vaaddu.nxv1i32.nxv1i32( define @intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i32.nxv1i32( define @intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vaaddu.nxv2i32.nxv2i32( define @intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i32.nxv2i32( define @intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vaaddu.nxv4i32.nxv4i32( define @intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i32.nxv4i32( define @intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vaaddu.nxv8i32.nxv8i32( define @intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i32.nxv8i32( define @intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vaaddu.nxv16i32.nxv16i32( define @intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32( ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vaaddu.nxv1i64.nxv1i64( define @intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( define @intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vaaddu.nxv2i64.nxv2i64( define @intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i64.nxv2i64( define @intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vaaddu.nxv4i64.nxv4i64( define @intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i64.nxv4i64( define @intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vaaddu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vaaddu.nxv8i64.nxv8i64( define @intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vaaddu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vaaddu_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vaaddu.nxv1i8.i8( define @intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i8.i8( define @intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vaaddu.nxv2i8.i8( define @intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i8.i8( define @intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vaaddu.nxv4i8.i8( define @intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i8.i8( define @intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vaaddu.nxv8i8.i8( define @intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i8.i8( define @intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vaaddu.nxv16i8.i8( define @intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i8.i8( define @intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vaaddu.nxv32i8.i8( define @intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vaaddu.mask.nxv32i8.i8( define @intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vaaddu.nxv64i8.i8( define @intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vaaddu.mask.nxv64i8.i8( define @intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vaaddu.nxv1i16.i16( define @intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i16.i16( define @intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vaaddu.nxv2i16.i16( define @intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i16.i16( define @intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vaaddu.nxv4i16.i16( define @intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i16.i16( define @intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vaaddu.nxv8i16.i16( define @intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i16.i16( define @intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vaaddu.nxv16i16.i16( define @intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i16.i16( define @intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vaaddu.nxv32i16.i16( define @intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vaaddu.mask.nxv32i16.i16( define @intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vaaddu.nxv1i32.i32( define @intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vaaddu.mask.nxv1i32.i32( define @intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vaaddu.nxv2i32.i32( define @intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vaaddu.mask.nxv2i32.i32( define @intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vaaddu.nxv4i32.i32( define @intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vaaddu.mask.nxv4i32.i32( define @intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vaaddu.nxv8i32.i32( define @intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vaaddu.mask.nxv8i32.i32( define @intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vaaddu.nxv16i32.i32( define @intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vaaddu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vaaddu.mask.nxv16i32.i32( define @intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vaaddu_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vaaddu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vaaddu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaaddu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vaaddu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaaddu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vaaddu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaaddu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vaaddu_vx_nxv8i64_nxv8i64_i64( @intrinsic_vaaddu_mask_vx_nxv8i64_nxv8i64_i64( @llvm.riscv.vasub.nxv1i8.nxv1i8( define @intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vasub.mask.nxv1i8.nxv1i8( define @intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vasub.nxv2i8.nxv2i8( define @intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vasub.mask.nxv2i8.nxv2i8( define @intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vasub.nxv4i8.nxv4i8( define @intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vasub.mask.nxv4i8.nxv4i8( define @intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vasub.nxv8i8.nxv8i8( define @intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vasub.mask.nxv8i8.nxv8i8( define @intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vasub.nxv16i8.nxv16i8( define @intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vasub.mask.nxv16i8.nxv16i8( define @intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vasub.nxv32i8.nxv32i8( define @intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vasub.mask.nxv32i8.nxv32i8( define @intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vasub.nxv64i8.nxv64i8( define @intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vasub_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vasub.nxv1i16.nxv1i16( define @intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vasub.mask.nxv1i16.nxv1i16( define @intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vasub.nxv2i16.nxv2i16( define @intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vasub.mask.nxv2i16.nxv2i16( define @intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vasub.nxv4i16.nxv4i16( define @intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vasub.mask.nxv4i16.nxv4i16( define @intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vasub.nxv8i16.nxv8i16( define @intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vasub.mask.nxv8i16.nxv8i16( define @intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vasub.nxv16i16.nxv16i16( define @intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vasub.mask.nxv16i16.nxv16i16( define @intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vasub.nxv32i16.nxv32i16( define @intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vasub.nxv1i32.nxv1i32( define @intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vasub.mask.nxv1i32.nxv1i32( define @intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vasub.nxv2i32.nxv2i32( define @intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vasub.mask.nxv2i32.nxv2i32( define @intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vasub.nxv4i32.nxv4i32( define @intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vasub.mask.nxv4i32.nxv4i32( define @intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vasub.nxv8i32.nxv8i32( define @intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vasub.mask.nxv8i32.nxv8i32( define @intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vasub.nxv16i32.nxv16i32( define @intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasub.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vasub.nxv1i64.nxv1i64( define @intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vasub.mask.nxv1i64.nxv1i64( define @intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vasub.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vasub.nxv2i64.nxv2i64( define @intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vasub.mask.nxv2i64.nxv2i64( define @intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vasub.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vasub.nxv4i64.nxv4i64( define @intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vasub.mask.nxv4i64.nxv4i64( define @intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vasub.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vasub.nxv8i64.nxv8i64( define @intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vasub.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vasub_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vasub.nxv1i8.i8( define @intrinsic_vasub_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vasub.mask.nxv1i8.i8( define @intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vasub.nxv2i8.i8( define @intrinsic_vasub_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vasub.mask.nxv2i8.i8( define @intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vasub.nxv4i8.i8( define @intrinsic_vasub_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vasub.mask.nxv4i8.i8( define @intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vasub.nxv8i8.i8( define @intrinsic_vasub_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vasub.mask.nxv8i8.i8( define @intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vasub.nxv16i8.i8( define @intrinsic_vasub_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vasub.mask.nxv16i8.i8( define @intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vasub.nxv32i8.i8( define @intrinsic_vasub_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vasub.mask.nxv32i8.i8( define @intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vasub.nxv64i8.i8( define @intrinsic_vasub_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vasub.mask.nxv64i8.i8( define @intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vasub.nxv1i16.i16( define @intrinsic_vasub_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vasub.mask.nxv1i16.i16( define @intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vasub.nxv2i16.i16( define @intrinsic_vasub_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vasub.mask.nxv2i16.i16( define @intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vasub.nxv4i16.i16( define @intrinsic_vasub_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vasub.mask.nxv4i16.i16( define @intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vasub.nxv8i16.i16( define @intrinsic_vasub_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vasub.mask.nxv8i16.i16( define @intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vasub.nxv16i16.i16( define @intrinsic_vasub_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vasub.mask.nxv16i16.i16( define @intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vasub.nxv32i16.i16( define @intrinsic_vasub_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vasub.mask.nxv32i16.i16( define @intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vasub.nxv1i32.i32( define @intrinsic_vasub_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vasub.mask.nxv1i32.i32( define @intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vasub.nxv2i32.i32( define @intrinsic_vasub_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vasub.mask.nxv2i32.i32( define @intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vasub.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vasub.nxv4i32.i32( define @intrinsic_vasub_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vasub.mask.nxv4i32.i32( define @intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vasub.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vasub.nxv8i32.i32( define @intrinsic_vasub_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vasub.mask.nxv8i32.i32( define @intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vasub.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vasub.nxv16i32.i32( define @intrinsic_vasub_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasub_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vasub.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vasub.mask.nxv16i32.i32( define @intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasub_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasub.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vasub_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasub_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasub_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasub_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasub_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasub_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasub_vx_nxv8i64_nxv8i64_i64( @intrinsic_vasub_mask_vx_nxv8i64_nxv8i64_i64( @llvm.riscv.vasubu.nxv1i8.nxv1i8( define @intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i8.nxv1i8( define @intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vasubu.nxv2i8.nxv2i8( define @intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i8.nxv2i8( define @intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vasubu.nxv4i8.nxv4i8( define @intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i8.nxv4i8( define @intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vasubu.nxv8i8.nxv8i8( define @intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -181,8 +181,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i8.nxv8i8( define @intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -205,8 +205,8 @@ declare @llvm.riscv.vasubu.nxv16i8.nxv16i8( define @intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i8.nxv16i8( define @intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -253,8 +253,8 @@ declare @llvm.riscv.vasubu.nxv32i8.nxv32i8( define @intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -277,8 +277,8 @@ declare @llvm.riscv.vasubu.mask.nxv32i8.nxv32i8( define @intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -301,8 +301,8 @@ declare @llvm.riscv.vasubu.nxv64i8.nxv64i8( define @intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -326,8 +326,8 @@ define @intrinsic_vasubu_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vasubu.nxv1i16.nxv1i16( define @intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -374,8 +374,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i16.nxv1i16( define @intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -398,8 +398,8 @@ declare @llvm.riscv.vasubu.nxv2i16.nxv2i16( define @intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -422,8 +422,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i16.nxv2i16( define @intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -446,8 +446,8 @@ declare @llvm.riscv.vasubu.nxv4i16.nxv4i16( define @intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -470,8 +470,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i16.nxv4i16( define @intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -494,8 +494,8 @@ declare @llvm.riscv.vasubu.nxv8i16.nxv8i16( define @intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -518,8 +518,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i16.nxv8i16( define @intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -542,8 +542,8 @@ declare @llvm.riscv.vasubu.nxv16i16.nxv16i16( define @intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -566,8 +566,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i16.nxv16i16( define @intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -590,8 +590,8 @@ declare @llvm.riscv.vasubu.nxv32i16.nxv32i16( define @intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -615,8 +615,8 @@ define @intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16( ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -639,8 +639,8 @@ declare @llvm.riscv.vasubu.nxv1i32.nxv1i32( define @intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i32.nxv1i32( define @intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -687,8 +687,8 @@ declare @llvm.riscv.vasubu.nxv2i32.nxv2i32( define @intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -711,8 +711,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i32.nxv2i32( define @intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -735,8 +735,8 @@ declare @llvm.riscv.vasubu.nxv4i32.nxv4i32( define @intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -759,8 +759,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i32.nxv4i32( define @intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -783,8 +783,8 @@ declare @llvm.riscv.vasubu.nxv8i32.nxv8i32( define @intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -807,8 +807,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i32.nxv8i32( define @intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vasubu.nxv16i32.nxv16i32( define @intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -856,8 +856,8 @@ define @intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32( ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasubu.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -880,8 +880,8 @@ declare @llvm.riscv.vasubu.nxv1i64.nxv1i64( define @intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -904,8 +904,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i64.nxv1i64( define @intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vasubu.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -928,8 +928,8 @@ declare @llvm.riscv.vasubu.nxv2i64.nxv2i64( define @intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -952,8 +952,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i64.nxv2i64( define @intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vasubu.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -976,8 +976,8 @@ declare @llvm.riscv.vasubu.nxv4i64.nxv4i64( define @intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1000,8 +1000,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i64.nxv4i64( define @intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vasubu.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1024,8 +1024,8 @@ declare @llvm.riscv.vasubu.nxv8i64.nxv8i64( define @intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vasubu.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1049,8 +1049,8 @@ define @intrinsic_vasubu_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vasubu.nxv1i8.i8( define @intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i8.i8( define @intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1121,8 +1121,8 @@ declare @llvm.riscv.vasubu.nxv2i8.i8( define @intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i8.i8( define @intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1169,8 +1169,8 @@ declare @llvm.riscv.vasubu.nxv4i8.i8( define @intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i8.i8( define @intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1217,8 +1217,8 @@ declare @llvm.riscv.vasubu.nxv8i8.i8( define @intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i8.i8( define @intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1265,8 +1265,8 @@ declare @llvm.riscv.vasubu.nxv16i8.i8( define @intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1289,8 +1289,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i8.i8( define @intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1313,8 +1313,8 @@ declare @llvm.riscv.vasubu.nxv32i8.i8( define @intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1337,8 +1337,8 @@ declare @llvm.riscv.vasubu.mask.nxv32i8.i8( define @intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1361,8 +1361,8 @@ declare @llvm.riscv.vasubu.nxv64i8.i8( define @intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1385,8 +1385,8 @@ declare @llvm.riscv.vasubu.mask.nxv64i8.i8( define @intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1409,8 +1409,8 @@ declare @llvm.riscv.vasubu.nxv1i16.i16( define @intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1433,8 +1433,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i16.i16( define @intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1457,8 +1457,8 @@ declare @llvm.riscv.vasubu.nxv2i16.i16( define @intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1481,8 +1481,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i16.i16( define @intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1505,8 +1505,8 @@ declare @llvm.riscv.vasubu.nxv4i16.i16( define @intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1529,8 +1529,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i16.i16( define @intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1553,8 +1553,8 @@ declare @llvm.riscv.vasubu.nxv8i16.i16( define @intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1577,8 +1577,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i16.i16( define @intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1601,8 +1601,8 @@ declare @llvm.riscv.vasubu.nxv16i16.i16( define @intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1625,8 +1625,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i16.i16( define @intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1649,8 +1649,8 @@ declare @llvm.riscv.vasubu.nxv32i16.i16( define @intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1673,8 +1673,8 @@ declare @llvm.riscv.vasubu.mask.nxv32i16.i16( define @intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1697,8 +1697,8 @@ declare @llvm.riscv.vasubu.nxv1i32.i32( define @intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1721,8 +1721,8 @@ declare @llvm.riscv.vasubu.mask.nxv1i32.i32( define @intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vasubu.nxv2i32.i32( define @intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vasubu.mask.nxv2i32.i32( define @intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vasubu.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1793,8 +1793,8 @@ declare @llvm.riscv.vasubu.nxv4i32.i32( define @intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1817,8 +1817,8 @@ declare @llvm.riscv.vasubu.mask.nxv4i32.i32( define @intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vasubu.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ declare @llvm.riscv.vasubu.nxv8i32.i32( define @intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1865,8 +1865,8 @@ declare @llvm.riscv.vasubu.mask.nxv8i32.i32( define @intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vasubu.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1889,8 +1889,8 @@ declare @llvm.riscv.vasubu.nxv16i32.i32( define @intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vasubu_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vasubu.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1913,8 +1913,8 @@ declare @llvm.riscv.vasubu.mask.nxv16i32.i32( define @intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vasubu_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 1 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vasubu.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1950,8 +1950,8 @@ define @intrinsic_vasubu_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasubu_mask_vx_nxv1i64_nxv1i64_i64( @intrinsic_vasubu_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasubu_mask_vx_nxv2i64_nxv2i64_i64( @intrinsic_vasubu_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasubu_mask_vx_nxv4i64_nxv4i64_i64( @intrinsic_vasubu_vx_nxv8i64_nxv8i64_i64( @intrinsic_vasubu_mask_vx_nxv8i64_nxv8i64_i64( @llvm.riscv.vfadd.nxv1f16.nxv1f16( define @intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f16.nxv1f16( @@ -48,10 +48,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16( define @intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f16.nxv1f16( @@ -73,10 +73,10 @@ declare @llvm.riscv.vfadd.nxv2f16.nxv2f16( define @intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f16.nxv2f16( @@ -98,10 +98,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16( define @intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f16.nxv2f16( @@ -123,10 +123,10 @@ declare @llvm.riscv.vfadd.nxv4f16.nxv4f16( define @intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f16.nxv4f16( @@ -148,10 +148,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16( define @intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f16.nxv4f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfadd.nxv8f16.nxv8f16( define @intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f16.nxv8f16( @@ -198,10 +198,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16( define @intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f16.nxv8f16( @@ -223,10 +223,10 @@ declare @llvm.riscv.vfadd.nxv16f16.nxv16f16( define @intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f16.nxv16f16( @@ -248,10 +248,10 @@ declare @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16( define @intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv16f16.nxv16f16( @@ -273,10 +273,10 @@ declare @llvm.riscv.vfadd.nxv32f16.nxv32f16( define @intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv32f16.nxv32f16( @@ -299,8 +299,8 @@ define @intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16( ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -324,10 +324,10 @@ declare @llvm.riscv.vfadd.nxv1f32.nxv1f32( define @intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f32.nxv1f32( @@ -349,10 +349,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32( define @intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f32.nxv1f32( @@ -374,10 +374,10 @@ declare @llvm.riscv.vfadd.nxv2f32.nxv2f32( define @intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f32.nxv2f32( @@ -399,10 +399,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32( define @intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f32.nxv2f32( @@ -424,10 +424,10 @@ declare @llvm.riscv.vfadd.nxv4f32.nxv4f32( define @intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f32.nxv4f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32( define @intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f32.nxv4f32( @@ -474,10 +474,10 @@ declare @llvm.riscv.vfadd.nxv8f32.nxv8f32( define @intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f32.nxv8f32( @@ -499,10 +499,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32( define @intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f32.nxv8f32( @@ -524,10 +524,10 @@ declare @llvm.riscv.vfadd.nxv16f32.nxv16f32( define @intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f32.nxv16f32( @@ -550,8 +550,8 @@ define @intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32 ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfadd.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -575,10 +575,10 @@ declare @llvm.riscv.vfadd.nxv1f64.nxv1f64( define @intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f64.nxv1f64( @@ -600,10 +600,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64( define @intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f64.nxv1f64( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfadd.nxv2f64.nxv2f64( define @intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f64.nxv2f64( @@ -650,10 +650,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64( define @intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f64.nxv2f64( @@ -675,10 +675,10 @@ declare @llvm.riscv.vfadd.nxv4f64.nxv4f64( define @intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f64.nxv4f64( @@ -700,10 +700,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64( define @intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f64.nxv4f64( @@ -725,10 +725,10 @@ declare @llvm.riscv.vfadd.nxv8f64.nxv8f64( define @intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f64.nxv8f64( @@ -751,8 +751,8 @@ define @intrinsic_vfadd_mask_vv_nxv8f64_nxv8f64_nxv8f64( @llvm.riscv.vfadd.nxv1f16.f16( define @intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f16.f16( @@ -801,10 +801,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f16.f16( define @intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f16.f16( @@ -826,10 +826,10 @@ declare @llvm.riscv.vfadd.nxv2f16.f16( define @intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f16.f16( @@ -851,10 +851,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f16.f16( define @intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f16.f16( @@ -876,10 +876,10 @@ declare @llvm.riscv.vfadd.nxv4f16.f16( define @intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f16.f16( @@ -901,10 +901,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f16.f16( define @intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f16.f16( @@ -926,10 +926,10 @@ declare @llvm.riscv.vfadd.nxv8f16.f16( define @intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f16.f16( @@ -951,10 +951,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f16.f16( define @intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f16.f16( @@ -976,10 +976,10 @@ declare @llvm.riscv.vfadd.nxv16f16.f16( define @intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f16.f16( @@ -1001,10 +1001,10 @@ declare @llvm.riscv.vfadd.mask.nxv16f16.f16( define @intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv16f16.f16( @@ -1026,10 +1026,10 @@ declare @llvm.riscv.vfadd.nxv32f16.f16( define @intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv32f16.f16( @@ -1051,10 +1051,10 @@ declare @llvm.riscv.vfadd.mask.nxv32f16.f16( define @intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv32f16.f16( @@ -1076,10 +1076,10 @@ declare @llvm.riscv.vfadd.nxv1f32.f32( define @intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f32.f32( @@ -1101,10 +1101,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f32.f32( define @intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f32.f32( @@ -1126,10 +1126,10 @@ declare @llvm.riscv.vfadd.nxv2f32.f32( define @intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f32.f32( @@ -1151,10 +1151,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f32.f32( define @intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f32.f32( @@ -1176,10 +1176,10 @@ declare @llvm.riscv.vfadd.nxv4f32.f32( define @intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f32.f32( @@ -1201,10 +1201,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f32.f32( define @intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f32.f32( @@ -1226,10 +1226,10 @@ declare @llvm.riscv.vfadd.nxv8f32.f32( define @intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f32.f32( @@ -1251,10 +1251,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f32.f32( define @intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f32.f32( @@ -1276,10 +1276,10 @@ declare @llvm.riscv.vfadd.nxv16f32.f32( define @intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv16f32.f32( @@ -1301,10 +1301,10 @@ declare @llvm.riscv.vfadd.mask.nxv16f32.f32( define @intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv16f32.f32( @@ -1326,10 +1326,10 @@ declare @llvm.riscv.vfadd.nxv1f64.f64( define @intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv1f64.f64( @@ -1351,10 +1351,10 @@ declare @llvm.riscv.vfadd.mask.nxv1f64.f64( define @intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv1f64.f64( @@ -1376,10 +1376,10 @@ declare @llvm.riscv.vfadd.nxv2f64.f64( define @intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv2f64.f64( @@ -1401,10 +1401,10 @@ declare @llvm.riscv.vfadd.mask.nxv2f64.f64( define @intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv2f64.f64( @@ -1426,10 +1426,10 @@ declare @llvm.riscv.vfadd.nxv4f64.f64( define @intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv4f64.f64( @@ -1451,10 +1451,10 @@ declare @llvm.riscv.vfadd.mask.nxv4f64.f64( define @intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv4f64.f64( @@ -1476,10 +1476,10 @@ declare @llvm.riscv.vfadd.nxv8f64.f64( define @intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfadd_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.nxv8f64.f64( @@ -1501,10 +1501,10 @@ declare @llvm.riscv.vfadd.mask.nxv8f64.f64( define @intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfadd_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfadd.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll index 626848839b07..bc8440920cd8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-x.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( define @intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f16.nxv1i16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16( define @intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f16.nxv1i16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( define @intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f16.nxv2i16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16( define @intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f16.nxv2i16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( define @intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f16.nxv4i16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16( define @intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f16.nxv4i16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( define @intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f16.nxv8i16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16( define @intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f16.nxv8i16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( define @intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f16.nxv16i16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16( define @intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f16.nxv16i16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( define @intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv32f16.nxv32i16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16( define @intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv32f16.nxv32i16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( define @intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f32.nxv1i32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32( define @intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f32.nxv1i32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( define @intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f32.nxv2i32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32( define @intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f32.nxv2i32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( define @intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f32.nxv4i32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32( define @intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f32.nxv4i32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( define @intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f32.nxv8i32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32( define @intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f32.nxv8i32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( define @intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv16f32.nxv16i32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32( define @intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv16f32.nxv16i32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64( define @intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv1f64.nxv1i64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64( define @intrinsic_vfcvt_mask_f.x.v_nxv1f64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv1f64.nxv1i64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64( define @intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv2f64.nxv2i64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64( define @intrinsic_vfcvt_mask_f.x.v_nxv2f64_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv2f64.nxv2i64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64( define @intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv4f64.nxv4i64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64( define @intrinsic_vfcvt_mask_f.x.v_nxv4f64_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv4f64.nxv4i64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64( define @intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.x.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.nxv8f64.nxv8i64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64( define @intrinsic_vfcvt_mask_f.x.v_nxv8f64_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.x.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.x.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.x.v.mask.nxv8f64.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll index 9109df44ec7f..9cf47f993ee4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-f-xu.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( define @intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f16.nxv1i16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f16_nxv1i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f16.nxv1i16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( define @intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f16.nxv2i16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f16_nxv2i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f16.nxv2i16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( define @intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f16.nxv4i16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f16_nxv4i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f16.nxv4i16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( define @intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f16.nxv8i16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f16_nxv8i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f16.nxv8i16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( define @intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f16.nxv16i16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f16_nxv16i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f16.nxv16i16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( define @intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv32f16.nxv32i16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16( define @intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv32f16_nxv32i16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv32f16.nxv32i16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( define @intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f32.nxv1i32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f32_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f32.nxv1i32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( define @intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f32.nxv2i32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f32_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f32.nxv2i32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( define @intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f32.nxv4i32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f32_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f32.nxv4i32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( define @intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f32.nxv8i32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f32_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f32.nxv8i32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( define @intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv16f32.nxv16i32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32( define @intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv16f32_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv16f32.nxv16i32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64( define @intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv1f64.nxv1i64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv1f64_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv1f64_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv1f64.nxv1i64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64( define @intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv2f64.nxv2i64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv2f64_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv2f64_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv2f64.nxv2i64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64( define @intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv4f64.nxv4i64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv4f64_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv4f64_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv4f64.nxv4i64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64( define @intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_f.xu.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.nxv8f64.nxv8i64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64( define @intrinsic_vfcvt_mask_f.xu.v_nxv8f64_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_f.xu.v_nxv8f64_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.f.xu.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.f.xu.v.mask.nxv8f64.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll index 1147ec331b78..68a85530ea24 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-x-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( define @intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i16.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16( define @intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i16.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( define @intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i16.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16( define @intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i16.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( define @intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i16.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16( define @intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i16.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( define @intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i16.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16( define @intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i16.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( define @intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i16.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16( define @intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i16.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( define @intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv32i16.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16( define @intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv32i16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( define @intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i32.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32( define @intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i32.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( define @intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i32.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32( define @intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i32.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( define @intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i32.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32( define @intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i32.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( define @intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i32.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32( define @intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( define @intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv16i32.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32( define @intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv16i32.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64( define @intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv1i64.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64( define @intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv1i64.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64( define @intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv2i64.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64( define @intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv2i64.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64( define @intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv4i64.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64( define @intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv4i64.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64( define @intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_x.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.nxv8i64.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64( define @intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_x.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.x.f.v.mask.nxv8i64.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll index cd227196b4f4..93716ba7f451 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfcvt-xu-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( define @intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i16.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i16.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( define @intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i16.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i16.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( define @intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i16.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i16.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( define @intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i16.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i16.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( define @intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i16.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i16.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( define @intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv32i16.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16( define @intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv32i16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv32i16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( define @intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i32.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i32.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( define @intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i32.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i32.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( define @intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i32.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i32.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( define @intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i32.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( define @intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv16i32.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32( define @intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv16i32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv16i32.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64( define @intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv1i64.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv1i64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv1i64.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64( define @intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv2i64.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv2i64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv2i64.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64( define @intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv4i64.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv4i64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv4i64.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64( define @intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_xu.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.nxv8i64.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64( define @intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfcvt_mask_xu.f.v_nxv8i64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfcvt.xu.f.v.mask.nxv8i64.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll index 7e77fb7dc2ed..3f67c433bcbf 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfdiv.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfdiv.nxv1f16.nxv1f16( define @intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f16.nxv1f16( define @intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfdiv.nxv2f16.nxv2f16( define @intrinsic_vfdiv_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f16.nxv2f16( define @intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfdiv.nxv4f16.nxv4f16( define @intrinsic_vfdiv_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f16.nxv4f16( define @intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfdiv.nxv8f16.nxv8f16( define @intrinsic_vfdiv_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f16.nxv8f16( define @intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfdiv.nxv16f16.nxv16f16( define @intrinsic_vfdiv_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfdiv.mask.nxv16f16.nxv16f16( define @intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfdiv.nxv32f16.nxv32f16( define @intrinsic_vfdiv_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv32f16.nxv32f16( @@ -289,8 +289,8 @@ define @intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16( ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -314,10 +314,10 @@ declare @llvm.riscv.vfdiv.nxv1f32.nxv1f32( define @intrinsic_vfdiv_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f32.nxv1f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f32.nxv1f32( define @intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f32.nxv1f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfdiv.nxv2f32.nxv2f32( define @intrinsic_vfdiv_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f32.nxv2f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f32.nxv2f32( define @intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f32.nxv2f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfdiv.nxv4f32.nxv4f32( define @intrinsic_vfdiv_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f32.nxv4f32( @@ -439,10 +439,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f32.nxv4f32( define @intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f32.nxv4f32( @@ -464,10 +464,10 @@ declare @llvm.riscv.vfdiv.nxv8f32.nxv8f32( define @intrinsic_vfdiv_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f32.nxv8f32( @@ -489,10 +489,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f32.nxv8f32( define @intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f32.nxv8f32( @@ -514,10 +514,10 @@ declare @llvm.riscv.vfdiv.nxv16f32.nxv16f32( define @intrinsic_vfdiv_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f32.nxv16f32( @@ -540,8 +540,8 @@ define @intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32 ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfdiv.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -565,10 +565,10 @@ declare @llvm.riscv.vfdiv.nxv1f64.nxv1f64( define @intrinsic_vfdiv_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f64.nxv1f64( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f64.nxv1f64( define @intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f64.nxv1f64( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfdiv.nxv2f64.nxv2f64( define @intrinsic_vfdiv_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f64.nxv2f64( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f64.nxv2f64( define @intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f64.nxv2f64( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfdiv.nxv4f64.nxv4f64( define @intrinsic_vfdiv_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f64.nxv4f64( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f64.nxv4f64( define @intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f64.nxv4f64( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfdiv.nxv8f64.nxv8f64( define @intrinsic_vfdiv_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f64.nxv8f64( @@ -741,8 +741,8 @@ define @intrinsic_vfdiv_mask_vv_nxv8f64_nxv8f64_nxv8f64( @llvm.riscv.vfdiv.nxv1f16.f16( define @intrinsic_vfdiv_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f16.f16( @@ -791,10 +791,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f16.f16( define @intrinsic_vfdiv_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f16.f16( @@ -816,10 +816,10 @@ declare @llvm.riscv.vfdiv.nxv2f16.f16( define @intrinsic_vfdiv_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f16.f16( @@ -841,10 +841,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f16.f16( define @intrinsic_vfdiv_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f16.f16( @@ -866,10 +866,10 @@ declare @llvm.riscv.vfdiv.nxv4f16.f16( define @intrinsic_vfdiv_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f16.f16( @@ -891,10 +891,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f16.f16( define @intrinsic_vfdiv_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f16.f16( @@ -916,10 +916,10 @@ declare @llvm.riscv.vfdiv.nxv8f16.f16( define @intrinsic_vfdiv_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f16.f16( @@ -941,10 +941,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f16.f16( define @intrinsic_vfdiv_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f16.f16( @@ -966,10 +966,10 @@ declare @llvm.riscv.vfdiv.nxv16f16.f16( define @intrinsic_vfdiv_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f16.f16( @@ -991,10 +991,10 @@ declare @llvm.riscv.vfdiv.mask.nxv16f16.f16( define @intrinsic_vfdiv_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f16.f16( @@ -1016,10 +1016,10 @@ declare @llvm.riscv.vfdiv.nxv32f16.f16( define @intrinsic_vfdiv_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv32f16.f16( @@ -1041,10 +1041,10 @@ declare @llvm.riscv.vfdiv.mask.nxv32f16.f16( define @intrinsic_vfdiv_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv32f16.f16( @@ -1066,10 +1066,10 @@ declare @llvm.riscv.vfdiv.nxv1f32.f32( define @intrinsic_vfdiv_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f32.f32( @@ -1091,10 +1091,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f32.f32( define @intrinsic_vfdiv_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f32.f32( @@ -1116,10 +1116,10 @@ declare @llvm.riscv.vfdiv.nxv2f32.f32( define @intrinsic_vfdiv_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f32.f32( @@ -1141,10 +1141,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f32.f32( define @intrinsic_vfdiv_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f32.f32( @@ -1166,10 +1166,10 @@ declare @llvm.riscv.vfdiv.nxv4f32.f32( define @intrinsic_vfdiv_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f32.f32( @@ -1191,10 +1191,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f32.f32( define @intrinsic_vfdiv_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f32.f32( @@ -1216,10 +1216,10 @@ declare @llvm.riscv.vfdiv.nxv8f32.f32( define @intrinsic_vfdiv_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f32.f32( @@ -1241,10 +1241,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f32.f32( define @intrinsic_vfdiv_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f32.f32( @@ -1266,10 +1266,10 @@ declare @llvm.riscv.vfdiv.nxv16f32.f32( define @intrinsic_vfdiv_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv16f32.f32( @@ -1291,10 +1291,10 @@ declare @llvm.riscv.vfdiv.mask.nxv16f32.f32( define @intrinsic_vfdiv_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv16f32.f32( @@ -1316,10 +1316,10 @@ declare @llvm.riscv.vfdiv.nxv1f64.f64( define @intrinsic_vfdiv_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv1f64.f64( @@ -1341,10 +1341,10 @@ declare @llvm.riscv.vfdiv.mask.nxv1f64.f64( define @intrinsic_vfdiv_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv1f64.f64( @@ -1366,10 +1366,10 @@ declare @llvm.riscv.vfdiv.nxv2f64.f64( define @intrinsic_vfdiv_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv2f64.f64( @@ -1391,10 +1391,10 @@ declare @llvm.riscv.vfdiv.mask.nxv2f64.f64( define @intrinsic_vfdiv_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv2f64.f64( @@ -1416,10 +1416,10 @@ declare @llvm.riscv.vfdiv.nxv4f64.f64( define @intrinsic_vfdiv_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv4f64.f64( @@ -1441,10 +1441,10 @@ declare @llvm.riscv.vfdiv.mask.nxv4f64.f64( define @intrinsic_vfdiv_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv4f64.f64( @@ -1466,10 +1466,10 @@ declare @llvm.riscv.vfdiv.nxv8f64.f64( define @intrinsic_vfdiv_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.nxv8f64.f64( @@ -1491,10 +1491,10 @@ declare @llvm.riscv.vfdiv.mask.nxv8f64.f64( define @intrinsic_vfdiv_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfdiv_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfdiv.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll index 73d0178a939c..5586b52b64ec 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmacc.nxv1f16.nxv1f16( define @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( define @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmacc.nxv2f16.nxv2f16( define @intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( define @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmacc.nxv4f16.nxv4f16( define @intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( define @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmacc.nxv8f16.nxv8f16( define @intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( define @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmacc.nxv16f16.nxv16f16( define @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( define @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmacc.nxv1f32.nxv1f32( define @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( define @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmacc.nxv2f32.nxv2f32( define @intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( define @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmacc.nxv4f32.nxv4f32( define @intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( define @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmacc.nxv8f32.nxv8f32( define @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( define @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmacc.nxv1f64.nxv1f64( define @intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( define @intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmacc.nxv2f64.nxv2f64( define @intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( define @intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmacc.nxv4f64.nxv4f64( define @intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( define @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmacc.nxv1f16.f16( define @intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f16.f16( define @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmacc.nxv2f16.f16( define @intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f16.f16( define @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmacc.nxv4f16.f16( define @intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f16.f16( define @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmacc.nxv8f16.f16( define @intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f16.f16( define @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmacc.nxv16f16.f16( define @intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmacc.mask.nxv16f16.f16( define @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmacc.nxv1f32.f32( define @intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f32.f32( define @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmacc.nxv2f32.f32( define @intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f32.f32( define @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmacc.nxv4f32.f32( define @intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f32.f32( define @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmacc.nxv8f32.f32( define @intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmacc.mask.nxv8f32.f32( define @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmacc.nxv1f64.f64( define @intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmacc.mask.nxv1f64.f64( define @intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmacc.nxv2f64.f64( define @intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmacc.mask.nxv2f64.f64( define @intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmacc.nxv4f64.f64( define @intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmacc.mask.nxv4f64.f64( define @intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmacc.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll index caad65c78e66..c44690d23f08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmadd.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmadd.nxv1f16.nxv1f16( define @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( define @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmadd.nxv2f16.nxv2f16( define @intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( define @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmadd.nxv4f16.nxv4f16( define @intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( define @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmadd.nxv8f16.nxv8f16( define @intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( define @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmadd.nxv16f16.nxv16f16( define @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( define @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmadd.nxv1f32.nxv1f32( define @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( define @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmadd.nxv2f32.nxv2f32( define @intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( define @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmadd.nxv4f32.nxv4f32( define @intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( define @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmadd.nxv8f32.nxv8f32( define @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( define @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmadd.nxv1f64.nxv1f64( define @intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( define @intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmadd.nxv2f64.nxv2f64( define @intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( define @intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmadd.nxv4f64.nxv4f64( define @intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( define @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmadd.nxv1f16.f16( define @intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f16.f16( define @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmadd.nxv2f16.f16( define @intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f16.f16( define @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmadd.nxv4f16.f16( define @intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f16.f16( define @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmadd.nxv8f16.f16( define @intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f16.f16( define @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmadd.nxv16f16.f16( define @intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmadd.mask.nxv16f16.f16( define @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmadd.nxv1f32.f32( define @intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f32.f32( define @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmadd.nxv2f32.f32( define @intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f32.f32( define @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmadd.nxv4f32.f32( define @intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f32.f32( define @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmadd.nxv8f32.f32( define @intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmadd.mask.nxv8f32.f32( define @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmadd.nxv1f64.f64( define @intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmadd.mask.nxv1f64.f64( define @intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmadd.nxv2f64.f64( define @intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmadd.mask.nxv2f64.f64( define @intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmadd.nxv4f64.f64( define @intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmadd.mask.nxv4f64.f64( define @intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmadd.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll index e668a70050e4..4eac7b63fd88 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmsac.nxv1f16.nxv1f16( define @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( define @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmsac.nxv2f16.nxv2f16( define @intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( define @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmsac.nxv4f16.nxv4f16( define @intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( define @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmsac.nxv8f16.nxv8f16( define @intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( define @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmsac.nxv16f16.nxv16f16( define @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( define @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmsac.nxv1f32.nxv1f32( define @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( define @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmsac.nxv2f32.nxv2f32( define @intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( define @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmsac.nxv4f32.nxv4f32( define @intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( define @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmsac.nxv8f32.nxv8f32( define @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( define @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmsac.nxv1f64.nxv1f64( define @intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( define @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmsac.nxv2f64.nxv2f64( define @intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( define @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmsac.nxv4f64.nxv4f64( define @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( define @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmsac.nxv1f16.f16( define @intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f16.f16( define @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmsac.nxv2f16.f16( define @intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f16.f16( define @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmsac.nxv4f16.f16( define @intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f16.f16( define @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmsac.nxv8f16.f16( define @intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f16.f16( define @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmsac.nxv16f16.f16( define @intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmsac.mask.nxv16f16.f16( define @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmsac.nxv1f32.f32( define @intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f32.f32( define @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmsac.nxv2f32.f32( define @intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f32.f32( define @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmsac.nxv4f32.f32( define @intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f32.f32( define @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmsac.nxv8f32.f32( define @intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmsac.mask.nxv8f32.f32( define @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmsac.nxv1f64.f64( define @intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmsac.mask.nxv1f64.f64( define @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmsac.nxv2f64.f64( define @intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmsac.mask.nxv2f64.f64( define @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmsac.nxv4f64.f64( define @intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmsac.mask.nxv4f64.f64( define @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsac.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll index 4cda25e18911..626b40e132c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmsub.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmsub.nxv1f16.nxv1f16( define @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( define @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmsub.nxv2f16.nxv2f16( define @intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( define @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmsub.nxv4f16.nxv4f16( define @intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( define @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmsub.nxv8f16.nxv8f16( define @intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( define @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmsub.nxv16f16.nxv16f16( define @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( define @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmsub.nxv1f32.nxv1f32( define @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( define @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfmsub.nxv2f32.nxv2f32( define @intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( define @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfmsub.nxv4f32.nxv4f32( define @intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( define @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfmsub.nxv8f32.nxv8f32( define @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( define @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfmsub.nxv1f64.nxv1f64( define @intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( define @intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfmsub.nxv2f64.nxv2f64( define @intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( define @intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfmsub.nxv4f64.nxv4f64( define @intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( define @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfmsub.nxv1f16.f16( define @intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f16.f16( define @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfmsub.nxv2f16.f16( define @intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f16.f16( define @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfmsub.nxv4f16.f16( define @intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f16.f16( define @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfmsub.nxv8f16.f16( define @intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f16.f16( define @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfmsub.nxv16f16.f16( define @intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfmsub.mask.nxv16f16.f16( define @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfmsub.nxv1f32.f32( define @intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f32.f32( define @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfmsub.nxv2f32.f32( define @intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f32.f32( define @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfmsub.nxv4f32.f32( define @intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f32.f32( define @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfmsub.nxv8f32.f32( define @intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfmsub.mask.nxv8f32.f32( define @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfmsub.nxv1f64.f64( define @intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfmsub.mask.nxv1f64.f64( define @intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfmsub.nxv2f64.f64( define @intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfmsub.mask.nxv2f64.f64( define @intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfmsub.nxv4f64.f64( define @intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfmsub.mask.nxv4f64.f64( define @intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmsub.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll index ee1d197e091f..b73d03fe36c7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfmul.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfmul.nxv1f16.nxv1f16( define @intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16( define @intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfmul.nxv2f16.nxv2f16( define @intrinsic_vfmul_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f16.nxv2f16( define @intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfmul.nxv4f16.nxv4f16( define @intrinsic_vfmul_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f16.nxv4f16( define @intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfmul.nxv8f16.nxv8f16( define @intrinsic_vfmul_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f16.nxv8f16( define @intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfmul.nxv16f16.nxv16f16( define @intrinsic_vfmul_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfmul.mask.nxv16f16.nxv16f16( define @intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfmul.nxv32f16.nxv32f16( define @intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv32f16.nxv32f16( @@ -289,8 +289,8 @@ define @intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16( ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv32f16_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -314,10 +314,10 @@ declare @llvm.riscv.vfmul.nxv1f32.nxv1f32( define @intrinsic_vfmul_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f32.nxv1f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f32.nxv1f32( define @intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f32.nxv1f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfmul.nxv2f32.nxv2f32( define @intrinsic_vfmul_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f32.nxv2f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f32.nxv2f32( define @intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f32.nxv2f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfmul.nxv4f32.nxv4f32( define @intrinsic_vfmul_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f32.nxv4f32( @@ -439,10 +439,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f32.nxv4f32( define @intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f32.nxv4f32( @@ -464,10 +464,10 @@ declare @llvm.riscv.vfmul.nxv8f32.nxv8f32( define @intrinsic_vfmul_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f32.nxv8f32( @@ -489,10 +489,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f32.nxv8f32( define @intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f32.nxv8f32( @@ -514,10 +514,10 @@ declare @llvm.riscv.vfmul.nxv16f32.nxv16f32( define @intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f32.nxv16f32( @@ -540,8 +540,8 @@ define @intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32 ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv16f32_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vfmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -565,10 +565,10 @@ declare @llvm.riscv.vfmul.nxv1f64.nxv1f64( define @intrinsic_vfmul_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f64.nxv1f64( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f64.nxv1f64( define @intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f64.nxv1f64( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfmul.nxv2f64.nxv2f64( define @intrinsic_vfmul_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f64.nxv2f64( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f64.nxv2f64( define @intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f64.nxv2f64( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfmul.nxv4f64.nxv4f64( define @intrinsic_vfmul_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f64.nxv4f64( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f64.nxv4f64( define @intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f64.nxv4f64( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfmul.nxv8f64.nxv8f64( define @intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vv_nxv8f64_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f64.nxv8f64( @@ -741,8 +741,8 @@ define @intrinsic_vfmul_mask_vv_nxv8f64_nxv8f64_nxv8f64( @llvm.riscv.vfmul.nxv1f16.f16( define @intrinsic_vfmul_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f16.f16( @@ -791,10 +791,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f16.f16( define @intrinsic_vfmul_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f16.f16( @@ -816,10 +816,10 @@ declare @llvm.riscv.vfmul.nxv2f16.f16( define @intrinsic_vfmul_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f16.f16( @@ -841,10 +841,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f16.f16( define @intrinsic_vfmul_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f16.f16( @@ -866,10 +866,10 @@ declare @llvm.riscv.vfmul.nxv4f16.f16( define @intrinsic_vfmul_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f16.f16( @@ -891,10 +891,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f16.f16( define @intrinsic_vfmul_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f16.f16( @@ -916,10 +916,10 @@ declare @llvm.riscv.vfmul.nxv8f16.f16( define @intrinsic_vfmul_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f16.f16( @@ -941,10 +941,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f16.f16( define @intrinsic_vfmul_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f16.f16( @@ -966,10 +966,10 @@ declare @llvm.riscv.vfmul.nxv16f16.f16( define @intrinsic_vfmul_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f16.f16( @@ -991,10 +991,10 @@ declare @llvm.riscv.vfmul.mask.nxv16f16.f16( define @intrinsic_vfmul_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv16f16.f16( @@ -1016,10 +1016,10 @@ declare @llvm.riscv.vfmul.nxv32f16.f16( define @intrinsic_vfmul_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv32f16.f16( @@ -1041,10 +1041,10 @@ declare @llvm.riscv.vfmul.mask.nxv32f16.f16( define @intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv32f16.f16( @@ -1066,10 +1066,10 @@ declare @llvm.riscv.vfmul.nxv1f32.f32( define @intrinsic_vfmul_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f32.f32( @@ -1091,10 +1091,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f32.f32( define @intrinsic_vfmul_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f32.f32( @@ -1116,10 +1116,10 @@ declare @llvm.riscv.vfmul.nxv2f32.f32( define @intrinsic_vfmul_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f32.f32( @@ -1141,10 +1141,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f32.f32( define @intrinsic_vfmul_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f32.f32( @@ -1166,10 +1166,10 @@ declare @llvm.riscv.vfmul.nxv4f32.f32( define @intrinsic_vfmul_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f32.f32( @@ -1191,10 +1191,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f32.f32( define @intrinsic_vfmul_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f32.f32( @@ -1216,10 +1216,10 @@ declare @llvm.riscv.vfmul.nxv8f32.f32( define @intrinsic_vfmul_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f32.f32( @@ -1241,10 +1241,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f32.f32( define @intrinsic_vfmul_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f32.f32( @@ -1266,10 +1266,10 @@ declare @llvm.riscv.vfmul.nxv16f32.f32( define @intrinsic_vfmul_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv16f32.f32( @@ -1291,10 +1291,10 @@ declare @llvm.riscv.vfmul.mask.nxv16f32.f32( define @intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv16f32.f32( @@ -1316,10 +1316,10 @@ declare @llvm.riscv.vfmul.nxv1f64.f64( define @intrinsic_vfmul_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv1f64.f64( @@ -1341,10 +1341,10 @@ declare @llvm.riscv.vfmul.mask.nxv1f64.f64( define @intrinsic_vfmul_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv1f64.f64( @@ -1366,10 +1366,10 @@ declare @llvm.riscv.vfmul.nxv2f64.f64( define @intrinsic_vfmul_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv2f64.f64( @@ -1391,10 +1391,10 @@ declare @llvm.riscv.vfmul.mask.nxv2f64.f64( define @intrinsic_vfmul_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv2f64.f64( @@ -1416,10 +1416,10 @@ declare @llvm.riscv.vfmul.nxv4f64.f64( define @intrinsic_vfmul_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv4f64.f64( @@ -1441,10 +1441,10 @@ declare @llvm.riscv.vfmul.mask.nxv4f64.f64( define @intrinsic_vfmul_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv4f64.f64( @@ -1466,10 +1466,10 @@ declare @llvm.riscv.vfmul.nxv8f64.f64( define @intrinsic_vfmul_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfmul_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.nxv8f64.f64( @@ -1491,10 +1491,10 @@ declare @llvm.riscv.vfmul.mask.nxv8f64.f64( define @intrinsic_vfmul_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfmul_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfmul.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll index 2de7d78df881..183ffa8a668a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-f.ll @@ -15,10 +15,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv1f16.nxv1f32( define @intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32( define @intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f16.nxv1f32( @@ -62,10 +62,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv2f16.nxv2f32( define @intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -86,10 +86,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32( define @intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f16.nxv2f32( @@ -109,10 +109,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv4f16.nxv4f32( define @intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -133,10 +133,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32( define @intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f16.nxv4f32( @@ -156,10 +156,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv8f16.nxv8f32( define @intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -180,10 +180,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32( define @intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f16.nxv8f32( @@ -203,10 +203,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv16f16.nxv16f32( define @intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv16f16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -227,10 +227,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32( define @intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv16f16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv16f16.nxv16f32( @@ -250,10 +250,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv1f32.nxv1f64( define @intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -274,10 +274,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64( define @intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv1f32.nxv1f64( @@ -297,10 +297,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv2f32.nxv2f64( define @intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv2f32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -321,10 +321,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64( define @intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv2f32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv2f32.nxv2f64( @@ -344,10 +344,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv4f32.nxv4f64( define @intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv4f32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -368,10 +368,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64( define @intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv4f32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv4f32.nxv4f64( @@ -391,10 +391,10 @@ declare @llvm.riscv.vfncvt.f.f.w.nxv8f32.nxv8f64( define @intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.f.w_nxv8f32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -415,10 +415,10 @@ declare @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64( define @intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.f.w_nxv8f32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.f.w.mask.nxv8f32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll index 7f2714b2fbfc..aef119faf5f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-x.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv1f16.nxv1i32( define @intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32( define @intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv1f16.nxv1i32( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv2f16.nxv2i32( define @intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32( define @intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv2f16.nxv2i32( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv4f16.nxv4i32( define @intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32( define @intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv4f16.nxv4i32( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv8f16.nxv8i32( define @intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32( define @intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv8f16.nxv8i32( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv16f16.nxv16i32( define @intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32( define @intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv16f16.nxv16i32( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv1f32.nxv1i64( define @intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64( define @intrinsic_vfncvt_mask_f.x.w_nxv1f32_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv1f32.nxv1i64( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv2f32.nxv2i64( define @intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64( define @intrinsic_vfncvt_mask_f.x.w_nxv2f32_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv2f32.nxv2i64( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv4f32.nxv4i64( define @intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64( define @intrinsic_vfncvt_mask_f.x.w_nxv4f32_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv4f32.nxv4i64( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.f.x.w.nxv8f32.nxv8i64( define @intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.x.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64( define @intrinsic_vfncvt_mask_f.x.w_nxv8f32_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.x.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.x.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.x.w.mask.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll index 1aeee4317cb3..bc287e4bdef1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-f-xu.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv1f16.nxv1i32( define @intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f16_nxv1i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f16.nxv1i32( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv2f16.nxv2i32( define @intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f16_nxv2i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f16.nxv2i32( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv4f16.nxv4i32( define @intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f16_nxv4i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f16.nxv4i32( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv8f16.nxv8i32( define @intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f16_nxv8i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f16.nxv8i32( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv16f16.nxv16i32( define @intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32( define @intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv16f16_nxv16i32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv16f16.nxv16i32( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv1f32.nxv1i64( define @intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv1f32_nxv1i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv1f32.nxv1i64( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv2f32.nxv2i64( define @intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv2f32_nxv2i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv2f32.nxv2i64( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv4f32.nxv4i64( define @intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv4f32_nxv4i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv4f32.nxv4i64( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.nxv8f32.nxv8i64( define @intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_f.xu.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64( define @intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_f.xu.w_nxv8f32_nxv8i64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.f.xu.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.f.xu.w.mask.nxv8f32.nxv8i64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll index 8309e3fb857f..e4b39c655a10 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-x-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv1i8.nxv1f16( define @intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16( define @intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i8.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv2i8.nxv2f16( define @intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16( define @intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i8.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv4i8.nxv4f16( define @intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16( define @intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i8.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv8i8.nxv8f16( define @intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16( define @intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i8.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv16i8.nxv16f16( define @intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16( define @intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i8.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv32i8.nxv32f16( define @intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16( define @intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv32i8.nxv32f16( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv1i16.nxv1f32( define @intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32( define @intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i16.nxv1f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv2i16.nxv2f32( define @intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32( define @intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i16.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv4i16.nxv4f32( define @intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32( define @intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i16.nxv4f32( @@ -435,10 +435,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv8i16.nxv8f32( define @intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -459,10 +459,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32( define @intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i16.nxv8f32( @@ -482,10 +482,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv16i16.nxv16f32( define @intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -506,10 +506,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32( define @intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv16i16.nxv16f32( @@ -529,10 +529,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv1i32.nxv1f64( define @intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -553,10 +553,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64( define @intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv1i32.nxv1f64( @@ -576,10 +576,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv2i32.nxv2f64( define @intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64( define @intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv2i32.nxv2f64( @@ -623,10 +623,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv4i32.nxv4f64( define @intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -647,10 +647,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64( define @intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv4i32.nxv4f64( @@ -670,10 +670,10 @@ declare @llvm.riscv.vfncvt.x.f.w.nxv8i32.nxv8f64( define @intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_x.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -694,10 +694,10 @@ declare @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64( define @intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_x.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.x.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.x.f.w.mask.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll index 3a3abacc8fc3..fd922438d05b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfncvt-xu-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv1i8.nxv1f16( define @intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i8_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i8.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv2i8.nxv2f16( define @intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i8_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i8.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv4i8.nxv4f16( define @intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i8_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i8.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv8i8.nxv8f16( define @intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i8_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i8.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv16i8.nxv16f16( define @intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i8_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i8.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv32i8.nxv32f16( define @intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16( define @intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv32i8_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv32i8.nxv32f16( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv1i16.nxv1f32( define @intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i16_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i16.nxv1f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv2i16.nxv2f32( define @intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i16.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv4i16.nxv4f32( define @intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i16_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i16.nxv4f32( @@ -435,10 +435,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv8i16.nxv8f32( define @intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -459,10 +459,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i16_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i16.nxv8f32( @@ -482,10 +482,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv16i16.nxv16f32( define @intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -506,10 +506,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32( define @intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv16i16_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv16i16.nxv16f32( @@ -529,10 +529,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv1i32.nxv1f64( define @intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -553,10 +553,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv1i32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv1i32.nxv1f64( @@ -576,10 +576,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv2i32.nxv2f64( define @intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv2i32_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv2i32.nxv2f64( @@ -623,10 +623,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv4i32.nxv4f64( define @intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret entry: @@ -647,10 +647,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv4i32_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv4i32.nxv4f64( @@ -670,10 +670,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.nxv8i32.nxv8f64( define @intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_xu.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret entry: @@ -694,10 +694,10 @@ declare @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64( define @intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfncvt_mask_xu.f.w_nxv8i32_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfncvt.xu.f.w v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfncvt.xu.f.w.mask.nxv8i32.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll index bdfa211dfdcb..01f4715274b6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( define @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( define @intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( define @intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( define @intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( define @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( define @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( define @intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( define @intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( define @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( define @intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( define @intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( define @intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmacc.nxv1f16.f16( define @intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmacc.nxv2f16.f16( define @intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmacc.nxv4f16.f16( define @intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmacc.nxv8f16.f16( define @intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmacc.nxv16f16.f16( define @intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv16f16.f16( define @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmacc.nxv1f32.f32( define @intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmacc.nxv2f32.f32( define @intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmacc.nxv4f32.f32( define @intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmacc.nxv8f32.f32( define @intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv8f32.f32( define @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmacc.nxv1f64.f64( define @intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv1f64.f64( define @intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmacc.nxv2f64.f64( define @intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv2f64.f64( define @intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmacc.nxv4f64.f64( define @intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmacc.mask.nxv4f64.f64( define @intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmacc.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll index 4eb2e7caba24..ae4cfef35e61 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( define @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( define @intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( define @intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( define @intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( define @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( define @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( define @intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( define @intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( define @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( define @intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( define @intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( define @intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmadd.nxv1f16.f16( define @intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmadd.nxv2f16.f16( define @intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmadd.nxv4f16.f16( define @intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmadd.nxv8f16.f16( define @intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmadd.nxv16f16.f16( define @intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv16f16.f16( define @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmadd.nxv1f32.f32( define @intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmadd.nxv2f32.f32( define @intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmadd.nxv4f32.f32( define @intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmadd.nxv8f32.f32( define @intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv8f32.f32( define @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmadd.nxv1f64.f64( define @intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv1f64.f64( define @intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmadd.nxv2f64.f64( define @intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv2f64.f64( define @intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmadd.nxv4f64.f64( define @intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmadd.mask.nxv4f64.f64( define @intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmadd.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll index dc30540bc0af..071f546b4f60 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( define @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( define @intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( define @intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( define @intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( define @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( define @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( define @intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( define @intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( define @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( define @intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( define @intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( define @intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmsac.nxv1f16.f16( define @intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmsac.nxv2f16.f16( define @intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmsac.nxv4f16.f16( define @intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmsac.nxv8f16.f16( define @intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmsac.nxv16f16.f16( define @intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv16f16.f16( define @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmsac.nxv1f32.f32( define @intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmsac.nxv2f32.f32( define @intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmsac.nxv4f32.f32( define @intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmsac.nxv8f32.f32( define @intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv8f32.f32( define @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmsac.nxv1f64.f64( define @intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv1f64.f64( define @intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmsac.nxv2f64.f64( define @intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv2f64.f64( define @intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmsac.nxv4f64.f64( define @intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmsac.mask.nxv4f64.f64( define @intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsac.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll index cadddb016c4f..4922cf40e503 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( define @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( define @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( define @intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( define @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( define @intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( define @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( define @intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( define @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( define @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( define @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( define @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( define @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( define @intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( define @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( define @intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( define @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( define @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( define @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( define @intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( define @intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( define @intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( define @intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( define @intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( define @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfnmsub.nxv1f16.f16( define @intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f16.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f16.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfnmsub.nxv2f16.f16( define @intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f16.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f16.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfnmsub.nxv4f16.f16( define @intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f16.f16( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f16.f16( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfnmsub.nxv8f16.f16( define @intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f16.f16( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f16.f16( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfnmsub.nxv16f16.f16( define @intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv16f16.f16( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv16f16.f16( define @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv16f16.f16( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfnmsub.nxv1f32.f32( define @intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f32.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f32.f32( @@ -913,10 +913,10 @@ declare @llvm.riscv.vfnmsub.nxv2f32.f32( define @intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f32.f32( @@ -938,10 +938,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f32.f32( @@ -963,10 +963,10 @@ declare @llvm.riscv.vfnmsub.nxv4f32.f32( define @intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f32.f32( @@ -988,10 +988,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f32.f32( @@ -1013,10 +1013,10 @@ declare @llvm.riscv.vfnmsub.nxv8f32.f32( define @intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv8f32.f32( @@ -1038,10 +1038,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv8f32.f32( define @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv8f32.f32( @@ -1063,10 +1063,10 @@ declare @llvm.riscv.vfnmsub.nxv1f64.f64( define @intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv1f64.f64( @@ -1088,10 +1088,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv1f64.f64( define @intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv1f64.f64( @@ -1113,10 +1113,10 @@ declare @llvm.riscv.vfnmsub.nxv2f64.f64( define @intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv2f64.f64( @@ -1138,10 +1138,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv2f64.f64( define @intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv2f64.f64( @@ -1163,10 +1163,10 @@ declare @llvm.riscv.vfnmsub.nxv4f64.f64( define @intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.nxv4f64.f64( @@ -1188,10 +1188,10 @@ declare @llvm.riscv.vfnmsub.mask.nxv4f64.f64( define @intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64( %0, double %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfnmsub.mask.nxv4f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll b/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll index f17c226ada0d..f73e7dce9212 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrdiv.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfrdiv.nxv1f16.f16( define @intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv1f16.f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv1f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f16_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f16.f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfrdiv.nxv2f16.f16( define @intrinsic_vfrdiv_vf_nxv2f16_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv2f16.f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv2f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv2f16_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f16_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f16.f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfrdiv.nxv4f16.f16( define @intrinsic_vfrdiv_vf_nxv4f16_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv4f16.f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv4f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv4f16_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f16_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f16.f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfrdiv.nxv8f16.f16( define @intrinsic_vfrdiv_vf_nxv8f16_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv8f16.f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv8f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv8f16_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f16_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f16.f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfrdiv.nxv16f16.f16( define @intrinsic_vfrdiv_vf_nxv16f16_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv16f16.f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv16f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv16f16_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f16_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv16f16.f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfrdiv.nxv32f16.f16( define @intrinsic_vfrdiv_vf_nxv32f16_nxv32f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv32f16.f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv32f16.f16( define @intrinsic_vfrdiv_mask_vf_nxv32f16_nxv32f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv32f16_nxv32f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv32f16.f16( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfrdiv.nxv1f32.f32( define @intrinsic_vfrdiv_vf_nxv1f32_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv1f32.f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv1f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv1f32_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f32_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f32.f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfrdiv.nxv2f32.f32( define @intrinsic_vfrdiv_vf_nxv2f32_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv2f32.f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv2f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv2f32_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f32_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f32.f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfrdiv.nxv4f32.f32( define @intrinsic_vfrdiv_vf_nxv4f32_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv4f32.f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv4f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv4f32_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f32_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f32.f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfrdiv.nxv8f32.f32( define @intrinsic_vfrdiv_vf_nxv8f32_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv8f32.f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv8f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv8f32_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f32_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f32.f32( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfrdiv.nxv16f32.f32( define @intrinsic_vfrdiv_vf_nxv16f32_nxv16f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv16f32.f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv16f32.f32( define @intrinsic_vfrdiv_mask_vf_nxv16f32_nxv16f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv16f32_nxv16f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv16f32.f32( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfrdiv.nxv1f64.f64( define @intrinsic_vfrdiv_vf_nxv1f64_nxv1f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv1f64.f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv1f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv1f64_nxv1f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv1f64_nxv1f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv1f64.f64( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfrdiv.nxv2f64.f64( define @intrinsic_vfrdiv_vf_nxv2f64_nxv2f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv2f64.f64( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv2f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv2f64_nxv2f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv2f64_nxv2f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv2f64.f64( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfrdiv.nxv4f64.f64( define @intrinsic_vfrdiv_vf_nxv4f64_nxv4f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv4f64.f64( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv4f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv4f64_nxv4f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv4f64_nxv4f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv4f64.f64( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfrdiv.nxv8f64.f64( define @intrinsic_vfrdiv_vf_nxv8f64_nxv8f64_f64( %0, double %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.nxv8f64.f64( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfrdiv.mask.nxv8f64.f64( define @intrinsic_vfrdiv_mask_vf_nxv8f64_nxv8f64_f64( %0, %1, double %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfrdiv_mask_vf_nxv8f64_nxv8f64_f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrdiv.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrdiv.mask.nxv8f64.f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll b/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll index 0204f0373d93..914b3b33fbe5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfrec7.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfrec7.nxv1f16( define @intrinsic_vfrec7_v_nxv1f16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfrec7.mask.nxv1f16( define @intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfrec7.nxv2f16( define @intrinsic_vfrec7_v_nxv2f16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfrec7.mask.nxv2f16( define @intrinsic_vfrec7_mask_v_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfrec7.nxv4f16( define @intrinsic_vfrec7_v_nxv4f16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfrec7.mask.nxv4f16( define @intrinsic_vfrec7_mask_v_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfrec7.nxv8f16( define @intrinsic_vfrec7_v_nxv8f16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfrec7.mask.nxv8f16( define @intrinsic_vfrec7_mask_v_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfrec7.nxv16f16( define @intrinsic_vfrec7_v_nxv16f16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfrec7.mask.nxv16f16( define @intrinsic_vfrec7_mask_v_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfrec7.nxv32f16( define @intrinsic_vfrec7_v_nxv32f16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfrec7.mask.nxv32f16( define @intrinsic_vfrec7_mask_v_nxv32f16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfrec7.nxv1f32( define @intrinsic_vfrec7_v_nxv1f32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfrec7.mask.nxv1f32( define @intrinsic_vfrec7_mask_v_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfrec7.nxv2f32( define @intrinsic_vfrec7_v_nxv2f32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfrec7.mask.nxv2f32( define @intrinsic_vfrec7_mask_v_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfrec7.nxv4f32( define @intrinsic_vfrec7_v_nxv4f32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfrec7.mask.nxv4f32( define @intrinsic_vfrec7_mask_v_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfrec7.nxv8f32( define @intrinsic_vfrec7_v_nxv8f32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfrec7.mask.nxv8f32( define @intrinsic_vfrec7_mask_v_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfrec7.nxv16f32( define @intrinsic_vfrec7_v_nxv16f32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfrec7.mask.nxv16f32( define @intrinsic_vfrec7_mask_v_nxv16f32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfrec7.nxv1f64( define @intrinsic_vfrec7_v_nxv1f64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfrec7.mask.nxv1f64( define @intrinsic_vfrec7_mask_v_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfrec7.nxv2f64( define @intrinsic_vfrec7_v_nxv2f64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfrec7.mask.nxv2f64( define @intrinsic_vfrec7_mask_v_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfrec7.nxv4f64( define @intrinsic_vfrec7_v_nxv4f64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfrec7.mask.nxv4f64( define @intrinsic_vfrec7_mask_v_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfrec7.nxv8f64( define @intrinsic_vfrec7_v_nxv8f64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfrec7.mask.nxv8f64( define @intrinsic_vfrec7_mask_v_nxv8f64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfrec7_mask_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfrec7.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfrec7.mask.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll index 19dde75969e3..6de9c82002f5 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredosum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv1f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv1f16.nxv1i1( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv2f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv2f16.nxv2i1( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv4f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv4f16.nxv4i1( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv8f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv8f16.nxv8i1( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv16f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv16f16.nxv16i1( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfredosum.nxv4f16.nxv32f16( define @intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv4f16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1( define @intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv4f16.nxv32f16.nxv32i1( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv1f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv1f32.nxv1i1( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv2f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv2f32.nxv2i1( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv4f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv4f32.nxv4i1( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv8f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1( define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv8f32.nxv8i1( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfredosum.nxv2f32.nxv16f32( define @intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv2f32.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1 define @intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv2f32.nxv16f32.nxv16i1( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv1f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv1f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv1f64.nxv1i1( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv2f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv2f64( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv2f64.nxv2i1( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv4f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv4f64( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv4f64.nxv4i1( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfredosum.nxv1f64.nxv8f64( define @intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.nxv1f64.nxv8f64( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1( define @intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredosum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredosum.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll index bd2a5a901fb8..ffef9ef728a1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfredusum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv1f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv1f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv1f16.nxv1i1( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv2f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv2f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv2f16.nxv2i1( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv4f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv4f16.nxv4i1( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv8f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv8f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv8f16.nxv8i1( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv16f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv16f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv16f16.nxv16i1( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfredusum.nxv4f16.nxv32f16( define @intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv4f16.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1( define @intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv4f16_nxv32f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv4f16.nxv32f16.nxv32i1( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv1f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv1f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv1f32.nxv1i1( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv2f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv2f32.nxv2i1( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv4f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv4f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv4f32.nxv4i1( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv8f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1( define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv8f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv8f32.nxv8i1( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfredusum.nxv2f32.nxv16f32( define @intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv2f32.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1 define @intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv2f32_nxv16f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv2f32.nxv16f32.nxv16i1( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv1f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv1f64( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv1f64.nxv1i1( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv2f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv2f64( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv2f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv2f64.nxv2i1( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv4f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv4f64( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv4f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv4f64.nxv4i1( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfredusum.nxv1f64.nxv8f64( define @intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.nxv1f64.nxv8f64( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1( define @intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfredusum_mask_vs_nxv1f64_nxv8f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfredusum.mask.nxv1f64.nxv8f64.nxv8i1( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll b/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll index 0f61e6a7d406..3e3eea9f353c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfsqrt.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfsqrt.nxv1f16( define @intrinsic_vfsqrt_v_nxv1f16_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv1f16( @@ -35,10 +35,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv1f16( define @intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f16( @@ -58,10 +58,10 @@ declare @llvm.riscv.vfsqrt.nxv2f16( define @intrinsic_vfsqrt_v_nxv2f16_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv2f16( @@ -81,10 +81,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv2f16( define @intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f16( @@ -104,10 +104,10 @@ declare @llvm.riscv.vfsqrt.nxv4f16( define @intrinsic_vfsqrt_v_nxv4f16_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv4f16( @@ -127,10 +127,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv4f16( define @intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f16( @@ -150,10 +150,10 @@ declare @llvm.riscv.vfsqrt.nxv8f16( define @intrinsic_vfsqrt_v_nxv8f16_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv8f16( @@ -173,10 +173,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv8f16( define @intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f16( @@ -196,10 +196,10 @@ declare @llvm.riscv.vfsqrt.nxv16f16( define @intrinsic_vfsqrt_v_nxv16f16_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv16f16( @@ -219,10 +219,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv16f16( define @intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv16f16( @@ -242,10 +242,10 @@ declare @llvm.riscv.vfsqrt.nxv32f16( define @intrinsic_vfsqrt_v_nxv32f16_nxv32f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv32f16( @@ -265,10 +265,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv32f16( define @intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv32f16_nxv32f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfsqrt.nxv1f32( define @intrinsic_vfsqrt_v_nxv1f32_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv1f32( @@ -311,10 +311,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv1f32( define @intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f32( @@ -334,10 +334,10 @@ declare @llvm.riscv.vfsqrt.nxv2f32( define @intrinsic_vfsqrt_v_nxv2f32_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv2f32( @@ -357,10 +357,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv2f32( define @intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f32( @@ -380,10 +380,10 @@ declare @llvm.riscv.vfsqrt.nxv4f32( define @intrinsic_vfsqrt_v_nxv4f32_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv4f32( @@ -403,10 +403,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv4f32( define @intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f32( @@ -426,10 +426,10 @@ declare @llvm.riscv.vfsqrt.nxv8f32( define @intrinsic_vfsqrt_v_nxv8f32_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv8f32( @@ -449,10 +449,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv8f32( define @intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfsqrt.nxv16f32( define @intrinsic_vfsqrt_v_nxv16f32_nxv16f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv16f32( @@ -495,10 +495,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv16f32( define @intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv16f32_nxv16f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv16f32( @@ -518,10 +518,10 @@ declare @llvm.riscv.vfsqrt.nxv1f64( define @intrinsic_vfsqrt_v_nxv1f64_nxv1f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv1f64( @@ -541,10 +541,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv1f64( define @intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv1f64_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv1f64( @@ -564,10 +564,10 @@ declare @llvm.riscv.vfsqrt.nxv2f64( define @intrinsic_vfsqrt_v_nxv2f64_nxv2f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv2f64( @@ -587,10 +587,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv2f64( define @intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv2f64_nxv2f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv2f64( @@ -610,10 +610,10 @@ declare @llvm.riscv.vfsqrt.nxv4f64( define @intrinsic_vfsqrt_v_nxv4f64_nxv4f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv4f64( @@ -633,10 +633,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv4f64( define @intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv4f64_nxv4f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv4f64( @@ -656,10 +656,10 @@ declare @llvm.riscv.vfsqrt.nxv8f64( define @intrinsic_vfsqrt_v_nxv8f64_nxv8f64( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.nxv8f64( @@ -679,10 +679,10 @@ declare @llvm.riscv.vfsqrt.mask.nxv8f64( define @intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfsqrt_mask_v_nxv8f64_nxv8f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfsqrt.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfsqrt.mask.nxv8f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll index cb7047be9753..b42a1fe46e67 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.nxv1f16( @@ -64,10 +64,10 @@ declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.nxv2f16( @@ -115,10 +115,10 @@ declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.nxv4f16( @@ -166,10 +166,10 @@ declare @llvm.riscv.vfwadd.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.nxv8f16( @@ -217,10 +217,10 @@ declare @llvm.riscv.vfwadd.nxv16f32.nxv16f16.nxv16f16( define @intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16 define @intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.nxv16f16( @@ -268,10 +268,10 @@ declare @llvm.riscv.vfwadd.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.nxv1f32( @@ -319,10 +319,10 @@ declare @llvm.riscv.vfwadd.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -345,10 +345,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.nxv2f32( @@ -370,10 +370,10 @@ declare @llvm.riscv.vfwadd.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -396,10 +396,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.nxv4f32( @@ -421,10 +421,10 @@ declare @llvm.riscv.vfwadd.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -447,10 +447,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfwadd.nxv1f32.nxv1f16.f16( define @intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -498,10 +498,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16( define @intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f32.nxv1f16.f16( @@ -523,10 +523,10 @@ declare @llvm.riscv.vfwadd.nxv2f32.nxv2f16.f16( define @intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -549,10 +549,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16( define @intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f32.nxv2f16.f16( @@ -574,10 +574,10 @@ declare @llvm.riscv.vfwadd.nxv4f32.nxv4f16.f16( define @intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16( define @intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f32.nxv4f16.f16( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfwadd.nxv8f32.nxv8f16.f16( define @intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -651,10 +651,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16( define @intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f32.nxv8f16.f16( @@ -676,10 +676,10 @@ declare @llvm.riscv.vfwadd.nxv16f32.nxv16f16.f16( define @intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -702,10 +702,10 @@ declare @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16( define @intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv16f32.nxv16f16.f16( @@ -727,10 +727,10 @@ declare @llvm.riscv.vfwadd.nxv1f64.nxv1f32.f32( define @intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -753,10 +753,10 @@ declare @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32( define @intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv1f64.nxv1f32.f32( @@ -778,10 +778,10 @@ declare @llvm.riscv.vfwadd.nxv2f64.nxv2f32.f32( define @intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -804,10 +804,10 @@ declare @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32( define @intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv2f64.nxv2f32.f32( @@ -829,10 +829,10 @@ declare @llvm.riscv.vfwadd.nxv4f64.nxv4f32.f32( define @intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -855,10 +855,10 @@ declare @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32( define @intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv4f64.nxv4f32.f32( @@ -880,10 +880,10 @@ declare @llvm.riscv.vfwadd.nxv8f64.nxv8f32.f32( define @intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -906,10 +906,10 @@ declare @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32( define @intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd_mask_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.mask.nxv8f64.nxv8f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll index 2a318c53a5fb..76246eba9480 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwadd.w.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( define @intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( define @intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( define @intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( define @intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( define @intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( define @intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( define @intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( define @intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16( define @intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv16f32.nxv16f16( @@ -239,8 +239,8 @@ define @intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16 ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -264,10 +264,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( define @intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f64.nxv1f32( @@ -289,10 +289,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( define @intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( @@ -314,10 +314,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( define @intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f64.nxv2f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( define @intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( define @intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f64.nxv4f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( define @intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32( define @intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f64.nxv8f32( @@ -440,8 +440,8 @@ define @intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vfwadd.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -465,10 +465,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f32.f16( define @intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f32.f16( @@ -490,10 +490,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( @@ -515,10 +515,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f32.f16( define @intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f32.f16( @@ -540,10 +540,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( @@ -565,10 +565,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f32.f16( define @intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f32.f16( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f32.f16( define @intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f32.f16( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfwadd.w.nxv16f32.f16( define @intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv16f32.f16( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( define @intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfwadd.w.nxv1f64.f32( define @intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv1f64.f32( @@ -740,10 +740,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( @@ -765,10 +765,10 @@ declare @llvm.riscv.vfwadd.w.nxv2f64.f32( define @intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv2f64.f32( @@ -790,10 +790,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( @@ -815,10 +815,10 @@ declare @llvm.riscv.vfwadd.w.nxv4f64.f32( define @intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv4f64.f32( @@ -840,10 +840,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( @@ -865,10 +865,10 @@ declare @llvm.riscv.vfwadd.w.nxv8f64.f32( define @intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.nxv8f64.f32( @@ -890,10 +890,10 @@ declare @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( define @intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( @@ -909,10 +909,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.nxv1f16( @@ -928,10 +928,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.nxv2f16( @@ -947,10 +947,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.nxv4f16( @@ -966,10 +966,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.nxv8f16( @@ -985,10 +985,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.nxv16f16( @@ -1004,10 +1004,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.nxv1f32( @@ -1023,10 +1023,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.nxv2f32( @@ -1042,10 +1042,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.nxv4f32( @@ -1061,10 +1061,10 @@ entry: define @intrinsic_vfwadd.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.nxv8f32( @@ -1080,10 +1080,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv1f32_nxv1f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f32.f16( @@ -1099,10 +1099,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv2f32_nxv2f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f32.f16( @@ -1118,10 +1118,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv4f32_nxv4f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f32.f16( @@ -1137,10 +1137,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv8f32_nxv8f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f32.f16( @@ -1156,10 +1156,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv16f32_nxv16f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv16f32.f16( @@ -1175,10 +1175,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv1f64_nxv1f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv1f64.f32( @@ -1194,10 +1194,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv2f64_nxv2f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv2f64.f32( @@ -1213,10 +1213,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv4f64_nxv4f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv4f64.f32( @@ -1232,10 +1232,10 @@ entry: define @intrinsic_vfwadd.w_mask_wf_tie_nxv8f64_nxv8f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_mask_wf_tie_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwadd.w.mask.nxv8f64.f32( @@ -1251,10 +1251,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1270,10 +1270,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1289,10 +1289,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1308,10 +1308,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1327,10 +1327,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1346,10 +1346,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1365,10 +1365,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1384,10 +1384,10 @@ entry: define @intrinsic_vfwadd.w_wv_untie_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwadd.w_wv_untie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwadd.wv v24, v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll index ba7ba4e4c2bb..23b10250dfa4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-x-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i32.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i32.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i32.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i32.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv16i32.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv1i64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv1i64.nxv1f32( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv2i64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv2i64.nxv2f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv4i64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv4i64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_x.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_mask_x.f.v_nxv8i64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_x.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.x.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.x.f.v.mask.nxv8i64.nxv8f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll index 82cea184920b..f6779ec9ba5a 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwcvt-xu-f.ll @@ -12,10 +12,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -36,10 +36,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i32.nxv1f16( @@ -59,10 +59,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -83,10 +83,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i32.nxv2f16( @@ -106,10 +106,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -130,10 +130,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i32.nxv4f16( @@ -153,10 +153,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -177,10 +177,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i32.nxv8f16( @@ -200,10 +200,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -224,10 +224,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16( define @intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv16i32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv16i32.nxv16f16( @@ -247,10 +247,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -271,10 +271,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv1i64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv1i64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv1i64.nxv1f32( @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -318,10 +318,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv2i64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv2i64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv2i64.nxv2f32( @@ -341,10 +341,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -365,10 +365,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv4i64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv4i64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv4i64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_xu.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -412,10 +412,10 @@ declare @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32( define @intrinsic_vfwcvt_mask_xu.f.v_nxv8i64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwcvt_mask_xu.f.v_nxv8i64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwcvt.xu.f.v v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwcvt.xu.f.v.mask.nxv8i64.nxv8f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll index b3ff91d92ce9..225ba1c14031 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( define @intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( define @intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwmacc.nxv2f32.nxv2f16( define @intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( define @intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwmacc.nxv4f32.nxv4f16( define @intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( define @intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwmacc.nxv8f32.nxv8f16( define @intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( define @intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwmacc.nxv16f32.nxv16f16( define @intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( define @intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwmacc.nxv1f64.nxv1f32( define @intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( define @intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwmacc.nxv2f64.nxv2f32( define @intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( define @intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwmacc.nxv4f64.nxv4f32( define @intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( define @intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwmacc.nxv8f64.nxv8f32( define @intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( define @intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwmacc.nxv1f32.f16( define @intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwmacc.nxv2f32.f16( define @intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwmacc.nxv4f32.f16( define @intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwmacc.nxv8f32.f16( define @intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwmacc.nxv16f32.f16( define @intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv16f32.f16( define @intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwmacc.nxv1f64.f32( define @intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv1f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwmacc.nxv2f64.f32( define @intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv2f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwmacc.nxv4f64.f32( define @intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv4f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwmacc.nxv8f64.f32( define @intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwmacc.mask.nxv8f64.f32( define @intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmacc.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll index 103eeb08f8c8..5e3f63b95b2f 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( define @intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( define @intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwmsac.nxv2f32.nxv2f16( define @intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( define @intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwmsac.nxv4f32.nxv4f16( define @intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( define @intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwmsac.nxv8f32.nxv8f16( define @intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( define @intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwmsac.nxv16f32.nxv16f16( define @intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( define @intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwmsac.nxv1f64.nxv1f32( define @intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( define @intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwmsac.nxv2f64.nxv2f32( define @intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( define @intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwmsac.nxv4f64.nxv4f32( define @intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( define @intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwmsac.nxv8f64.nxv8f32( define @intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( define @intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwmsac.nxv1f32.f16( define @intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwmsac.nxv2f32.f16( define @intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwmsac.nxv4f32.f16( define @intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwmsac.nxv8f32.f16( define @intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwmsac.nxv16f32.f16( define @intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv16f32.f16( define @intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwmsac.nxv1f64.f32( define @intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv1f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwmsac.nxv2f64.f32( define @intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv2f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwmsac.nxv4f64.f32( define @intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv4f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwmsac.nxv8f64.f32( define @intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwmsac.mask.nxv8f64.f32( define @intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll b/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll index 2f9fc24de3aa..bc5759f469ad 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwmul.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.nxv1f16( @@ -64,10 +64,10 @@ declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.nxv2f16( @@ -115,10 +115,10 @@ declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.nxv4f16( @@ -166,10 +166,10 @@ declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.nxv8f16( @@ -217,10 +217,10 @@ declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.nxv16f16( define @intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.nxv16f16 define @intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.nxv16f16( @@ -268,10 +268,10 @@ declare @llvm.riscv.vfwmul.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.nxv1f32( @@ -319,10 +319,10 @@ declare @llvm.riscv.vfwmul.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -345,10 +345,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.nxv2f32( @@ -370,10 +370,10 @@ declare @llvm.riscv.vfwmul.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -396,10 +396,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.nxv4f32( @@ -421,10 +421,10 @@ declare @llvm.riscv.vfwmul.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -447,10 +447,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfwmul.nxv1f32.nxv1f16.f16( define @intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -498,10 +498,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.f16( define @intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f32.nxv1f16.f16( @@ -523,10 +523,10 @@ declare @llvm.riscv.vfwmul.nxv2f32.nxv2f16.f16( define @intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -549,10 +549,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.f16( define @intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f32.nxv2f16.f16( @@ -574,10 +574,10 @@ declare @llvm.riscv.vfwmul.nxv4f32.nxv4f16.f16( define @intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.f16( define @intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f32.nxv4f16.f16( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfwmul.nxv8f32.nxv8f16.f16( define @intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -651,10 +651,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.f16( define @intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f32.nxv8f16.f16( @@ -676,10 +676,10 @@ declare @llvm.riscv.vfwmul.nxv16f32.nxv16f16.f16( define @intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -702,10 +702,10 @@ declare @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.f16( define @intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv16f32.nxv16f16.f16( @@ -727,10 +727,10 @@ declare @llvm.riscv.vfwmul.nxv1f64.nxv1f32.f32( define @intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -753,10 +753,10 @@ declare @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.f32( define @intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv1f64.nxv1f32.f32( @@ -778,10 +778,10 @@ declare @llvm.riscv.vfwmul.nxv2f64.nxv2f32.f32( define @intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -804,10 +804,10 @@ declare @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.f32( define @intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv2f64.nxv2f32.f32( @@ -829,10 +829,10 @@ declare @llvm.riscv.vfwmul.nxv4f64.nxv4f32.f32( define @intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -855,10 +855,10 @@ declare @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.f32( define @intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv4f64.nxv4f32.f32( @@ -880,10 +880,10 @@ declare @llvm.riscv.vfwmul.nxv8f64.nxv8f32.f32( define @intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -906,10 +906,10 @@ declare @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.f32( define @intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwmul_mask_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwmul.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwmul.mask.nxv8f64.nxv8f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll index ca2d2a33159b..fc8e15273f08 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmacc.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( define @intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( define @intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16( define @intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( define @intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16( define @intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( define @intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16( define @intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( define @intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16( define @intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( define @intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32( define @intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( define @intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32( define @intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( define @intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32( define @intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( define @intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32( define @intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( define @intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f32.f16( define @intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f32.f16( define @intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f32.f16( define @intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f32.f16( define @intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwnmacc.nxv16f32.f16( define @intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( define @intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwnmacc.nxv1f64.f32( define @intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwnmacc.nxv2f64.f32( define @intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwnmacc.nxv4f64.f32( define @intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwnmacc.nxv8f64.f32( define @intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( define @intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmacc_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmacc.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmacc.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll index 648727dce246..b51faf9082c8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwnmsac.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( define @intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( define @intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16( define @intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( define @intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16( define @intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( define @intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16( define @intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( define @intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16( define @intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( define @intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.nxv16f16( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32( define @intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.nxv1f32( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( define @intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.nxv1f32( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32( define @intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.nxv2f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( define @intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.nxv2f32( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32( define @intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.nxv4f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( define @intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.nxv4f32( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32( define @intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.nxv8f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( define @intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.nxv8f32( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f32.f16( define @intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f32.f16( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f32_f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f32.f16( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f32.f16( define @intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f32.f16( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f32_f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f32.f16( @@ -563,10 +563,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f32.f16( define @intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f32.f16( @@ -588,10 +588,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f32_f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f32.f16( @@ -613,10 +613,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f32.f16( define @intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f32.f16( @@ -638,10 +638,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f32_f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f32.f16( @@ -663,10 +663,10 @@ declare @llvm.riscv.vfwnmsac.nxv16f32.f16( define @intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv16f32.f16( @@ -688,10 +688,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( define @intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16( %0, half %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv16f32_f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv16f32.f16( @@ -713,10 +713,10 @@ declare @llvm.riscv.vfwnmsac.nxv1f64.f32( define @intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv1f64.f32( @@ -738,10 +738,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv1f64_f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv1f64.f32( @@ -763,10 +763,10 @@ declare @llvm.riscv.vfwnmsac.nxv2f64.f32( define @intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv2f64.f32( @@ -788,10 +788,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv2f64_f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv2f64.f32( @@ -813,10 +813,10 @@ declare @llvm.riscv.vfwnmsac.nxv4f64.f32( define @intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv4f64.f32( @@ -838,10 +838,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv4f64_f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv4f64.f32( @@ -863,10 +863,10 @@ declare @llvm.riscv.vfwnmsac.nxv8f64.f32( define @intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.nxv8f64.f32( @@ -888,10 +888,10 @@ declare @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( define @intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32( %0, float %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwnmsac_mask_vf_nxv8f64_f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwnmsac.vf v8, fa0, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwnmsac.mask.nxv8f64.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll index 2184ab413c55..cb2bea0b50e1 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredosum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv1f16.nxv2f32( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv2f16.nxv2f32( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv4f16.nxv2f32( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv8f16.nxv2f32( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f3 define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv16f16.nxv2f32( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( define @intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv2f32.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( define @intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv2f32.nxv32f16( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv1f32.nxv1f64( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv2f32.nxv1f64( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv4f32.nxv1f64( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f6 define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv8f32.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( define @intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.nxv1f64.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f define @intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredosum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredosum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredosum.mask.nxv1f64.nxv16f32.nxv1f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll index d3d76e575978..66c2da047cfa 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwredusum.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv1f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv1f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv1f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.nxv2f32( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv2f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv2f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv2f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.nxv2f32( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv4f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv4f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv4f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.nxv2f32( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv8f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.nxv2f32 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv8f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv8f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.nxv2f32( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv16f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv16f16( @@ -238,10 +238,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.nxv2f3 define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv16f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv16f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.nxv2f32( @@ -263,10 +263,10 @@ declare @llvm.riscv.vfwredusum.nxv2f32.nxv32f16( define @intrinsic_vfwredusum_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv2f32.nxv32f16( @@ -288,10 +288,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16( define @intrinsic_vfwredusum_mask_vs_nxv2f32_nxv32f16_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv2f32_nxv32f16_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16( @@ -313,10 +313,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv1f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv1f32( @@ -338,10 +338,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv1f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv1f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.nxv1f64( @@ -363,10 +363,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv2f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv2f32( @@ -388,10 +388,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv2f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv2f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.nxv1f64( @@ -413,10 +413,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv4f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv4f32( @@ -438,10 +438,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv4f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv4f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v10, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.nxv1f64( @@ -463,10 +463,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv8f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv8f32( @@ -488,10 +488,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.nxv1f6 define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv8f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv8f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v12, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.nxv1f64( @@ -513,10 +513,10 @@ declare @llvm.riscv.vfwredusum.nxv1f64.nxv16f32( define @intrinsic_vfwredusum_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.nxv1f64.nxv16f32( @@ -538,10 +538,10 @@ declare @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.nxv1f define @intrinsic_vfwredusum_mask_vs_nxv1f64_nxv16f32_nxv1f64( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwredusum_mask_vs_nxv1f64_nxv16f32_nxv1f64: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwredusum.vs v8, v16, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.nxv1f64( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll index bb72f70f111b..0e3e5f8aabfd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -39,10 +39,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16( define @intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f32_nxv1f16_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.nxv1f16( @@ -64,10 +64,10 @@ declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -90,10 +90,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16( define @intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f32_nxv2f16_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.nxv2f16( @@ -115,10 +115,10 @@ declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -141,10 +141,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16( define @intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f32_nxv4f16_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.nxv4f16( @@ -166,10 +166,10 @@ declare @llvm.riscv.vfwsub.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -192,10 +192,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16( define @intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f32_nxv8f16_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.nxv8f16( @@ -217,10 +217,10 @@ declare @llvm.riscv.vfwsub.nxv16f32.nxv16f16.nxv16f16( define @intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -243,10 +243,10 @@ declare @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16 define @intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv16f32_nxv16f16_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.nxv16f16( @@ -268,10 +268,10 @@ declare @llvm.riscv.vfwsub.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -294,10 +294,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32( define @intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv1f64_nxv1f32_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.nxv1f32( @@ -319,10 +319,10 @@ declare @llvm.riscv.vfwsub.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v10, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -345,10 +345,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32( define @intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv2f64_nxv2f32_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v10, v11, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.nxv2f32( @@ -370,10 +370,10 @@ declare @llvm.riscv.vfwsub.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v12, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -396,10 +396,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32( define @intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv4f64_nxv4f32_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v12, v14, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.nxv4f32( @@ -421,10 +421,10 @@ declare @llvm.riscv.vfwsub.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v16, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -447,10 +447,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32( define @intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vv_nxv8f64_nxv8f32_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vv v8, v16, v20, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.nxv8f32( @@ -472,10 +472,10 @@ declare @llvm.riscv.vfwsub.nxv1f32.nxv1f16.f16( define @intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -498,10 +498,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16( define @intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f32_nxv1f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f32.nxv1f16.f16( @@ -523,10 +523,10 @@ declare @llvm.riscv.vfwsub.nxv2f32.nxv2f16.f16( define @intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -549,10 +549,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16( define @intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f32_nxv2f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f32.nxv2f16.f16( @@ -574,10 +574,10 @@ declare @llvm.riscv.vfwsub.nxv4f32.nxv4f16.f16( define @intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -600,10 +600,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16( define @intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f32_nxv4f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f32.nxv4f16.f16( @@ -625,10 +625,10 @@ declare @llvm.riscv.vfwsub.nxv8f32.nxv8f16.f16( define @intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -651,10 +651,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16( define @intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f32_nxv8f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f32.nxv8f16.f16( @@ -676,10 +676,10 @@ declare @llvm.riscv.vfwsub.nxv16f32.nxv16f16.f16( define @intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -702,10 +702,10 @@ declare @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16( define @intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv16f32_nxv16f16_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv16f32.nxv16f16.f16( @@ -727,10 +727,10 @@ declare @llvm.riscv.vfwsub.nxv1f64.nxv1f32.f32( define @intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v9, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret entry: @@ -753,10 +753,10 @@ declare @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32( define @intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv1f64_nxv1f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv1f64.nxv1f32.f32( @@ -778,10 +778,10 @@ declare @llvm.riscv.vfwsub.nxv2f64.nxv2f32.f32( define @intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v10, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -804,10 +804,10 @@ declare @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32( define @intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv2f64_nxv2f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv2f64.nxv2f32.f32( @@ -829,10 +829,10 @@ declare @llvm.riscv.vfwsub.nxv4f64.nxv4f32.f32( define @intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v12, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -855,10 +855,10 @@ declare @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32( define @intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv4f64_nxv4f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv4f64.nxv4f32.f32( @@ -880,10 +880,10 @@ declare @llvm.riscv.vfwsub.nxv8f64.nxv8f32.f32( define @intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v16, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -906,10 +906,10 @@ declare @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32( define @intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub_mask_vf_nxv8f64_nxv8f32_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.vf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.mask.nxv8f64.nxv8f32.f32( diff --git a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll index 722fed5138f7..90f92226dcdd 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vfwsub.w.ll @@ -13,10 +13,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( define @intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f32.nxv1f16( @@ -38,10 +38,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( define @intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( @@ -63,10 +63,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( define @intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f32.nxv2f16( @@ -88,10 +88,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( define @intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( @@ -113,10 +113,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( define @intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f32.nxv4f16( @@ -138,10 +138,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( define @intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( @@ -163,10 +163,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( define @intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f32.nxv8f16( @@ -188,10 +188,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( define @intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( @@ -213,10 +213,10 @@ declare @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16( define @intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv16f32.nxv16f16( @@ -239,8 +239,8 @@ define @intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16 ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -264,10 +264,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( define @intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f64.nxv1f32( @@ -289,10 +289,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( define @intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v9, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( @@ -314,10 +314,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( define @intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f64.nxv2f32( @@ -339,10 +339,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( define @intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v10, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( @@ -364,10 +364,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( define @intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f64.nxv4f32( @@ -389,10 +389,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( define @intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v12, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( @@ -414,10 +414,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32( define @intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f64.nxv8f32( @@ -440,8 +440,8 @@ define @intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32 ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl4re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: fsrmi a0, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vfwsub.wv v8, v16, v24, v0.t ; CHECK-NEXT: fsrm a0 ; CHECK-NEXT: ret @@ -465,10 +465,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f32.f16( define @intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f32.f16( @@ -490,10 +490,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( @@ -515,10 +515,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f32.f16( define @intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f32.f16( @@ -540,10 +540,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( @@ -565,10 +565,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f32.f16( define @intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f32.f16( @@ -590,10 +590,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( @@ -615,10 +615,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f32.f16( define @intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f32.f16( @@ -640,10 +640,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( @@ -665,10 +665,10 @@ declare @llvm.riscv.vfwsub.w.nxv16f32.f16( define @intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16( %0, half %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv16f32.f16( @@ -690,10 +690,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( define @intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16( %0, %1, half %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( @@ -715,10 +715,10 @@ declare @llvm.riscv.vfwsub.w.nxv1f64.f32( define @intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv1f64.f32( @@ -740,10 +740,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v9, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( @@ -765,10 +765,10 @@ declare @llvm.riscv.vfwsub.w.nxv2f64.f32( define @intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv2f64.f32( @@ -790,10 +790,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v10, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( @@ -815,10 +815,10 @@ declare @llvm.riscv.vfwsub.w.nxv4f64.f32( define @intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv4f64.f32( @@ -840,10 +840,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v12, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( @@ -865,10 +865,10 @@ declare @llvm.riscv.vfwsub.w.nxv8f64.f32( define @intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32( %0, float %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.nxv8f64.f32( @@ -890,10 +890,10 @@ declare @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( define @intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32( %0, %1, float %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v16, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( @@ -909,10 +909,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.nxv1f16( @@ -928,10 +928,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.nxv2f16( @@ -947,10 +947,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.nxv4f16( @@ -966,10 +966,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.nxv8f16( @@ -985,10 +985,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv16f32_nxv16f32_nxv16f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.nxv16f16( @@ -1004,10 +1004,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v9, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.nxv1f32( @@ -1023,10 +1023,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v10, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.nxv2f32( @@ -1042,10 +1042,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v12, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.nxv4f32( @@ -1061,10 +1061,10 @@ entry: define @intrinsic_vfwsub.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wv_tie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v8, v8, v16, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.nxv8f32( @@ -1080,10 +1080,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f32_nxv1f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f32.f16( @@ -1099,10 +1099,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f32_nxv2f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f32.f16( @@ -1118,10 +1118,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f32_nxv4f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f32.f16( @@ -1137,10 +1137,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f32_nxv8f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f32.f16( @@ -1156,10 +1156,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16( %0, half %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv16f32_nxv16f32_f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv16f32.f16( @@ -1175,10 +1175,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv1f64_nxv1f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv1f64.f32( @@ -1194,10 +1194,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv2f64_nxv2f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv2f64.f32( @@ -1213,10 +1213,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv4f64_nxv4f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv4f64.f32( @@ -1232,10 +1232,10 @@ entry: define @intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32( %0, float %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_mask_wf_tie_nxv8f64_nxv8f64_f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wf v8, v8, fa0, v0.t -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: ret entry: %a = call @llvm.riscv.vfwsub.w.mask.nxv8f64.f32( @@ -1251,10 +1251,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f32_nxv1f32_nxv1f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1270,10 +1270,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f32_nxv2f32_nxv2f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1289,10 +1289,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f32_nxv4f32_nxv4f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1308,10 +1308,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f32_nxv8f32_nxv8f16: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1327,10 +1327,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv1f64_nxv1f64_nxv1f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v10, v9, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret entry: @@ -1346,10 +1346,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv2f64_nxv2f64_nxv2f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v12, v10, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: ret entry: @@ -1365,10 +1365,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv4f64_nxv4f64_nxv4f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v16, v12, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv4r.v v8, v16 ; CHECK-NEXT: ret entry: @@ -1384,10 +1384,10 @@ entry: define @intrinsic_vfwsub.w_wv_untie_nxv8f64_nxv8f64_nxv8f32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vfwsub.w_wv_untie_nxv8f64_nxv8f64_nxv8f32: ; CHECK: # %bb.0: # %entry +; CHECK-NEXT: fsrmi a1, 0 ; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma -; CHECK-NEXT: fsrmi a0, 0 ; CHECK-NEXT: vfwsub.wv v24, v16, v8 -; CHECK-NEXT: fsrm a0 +; CHECK-NEXT: fsrm a1 ; CHECK-NEXT: vmv8r.v v8, v24 ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclip.ll b/llvm/test/CodeGen/RISCV/rvv/vnclip.ll index 54f4c17dd7ed..8902b1a28f8c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclip.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclip.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vnclip.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vnclip.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vnclip.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vnclip.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclip.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -182,8 +182,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -206,8 +206,8 @@ declare @llvm.riscv.vnclip.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclip.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -231,8 +231,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vnclip.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclip.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -280,8 +280,8 @@ declare @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -304,8 +304,8 @@ declare @llvm.riscv.vnclip.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -352,8 +352,8 @@ declare @llvm.riscv.vnclip.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vnclip.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclip.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -425,8 +425,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -449,8 +449,8 @@ declare @llvm.riscv.vnclip.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclip.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -474,8 +474,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -498,8 +498,8 @@ declare @llvm.riscv.vnclip.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclip.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -523,8 +523,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -547,8 +547,8 @@ declare @llvm.riscv.vnclip.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclip.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -571,8 +571,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -595,8 +595,8 @@ declare @llvm.riscv.vnclip.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclip.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -620,8 +620,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclip.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -644,8 +644,8 @@ declare @llvm.riscv.vnclip.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclip.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -669,8 +669,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclip.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -693,8 +693,8 @@ declare @llvm.riscv.vnclip.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclip.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -718,8 +718,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclip.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -741,8 +741,8 @@ declare @llvm.riscv.vnclip.nxv1i8.nxv1i16( define @intrinsic_vnclip_vx_nxv1i8_nxv1i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -765,8 +765,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i8.nxv1i16( define @intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -788,8 +788,8 @@ declare @llvm.riscv.vnclip.nxv2i8.nxv2i16( define @intrinsic_vnclip_vx_nxv2i8_nxv2i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -812,8 +812,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i8.nxv2i16( define @intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -835,8 +835,8 @@ declare @llvm.riscv.vnclip.nxv4i8.nxv4i16( define @intrinsic_vnclip_vx_nxv4i8_nxv4i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i8.nxv4i16( define @intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vnclip.nxv8i8.nxv8i16( define @intrinsic_vnclip_vx_nxv8i8_nxv8i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vnclip.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -907,8 +907,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i8.nxv8i16( define @intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vnclip.nxv16i8.nxv16i16( define @intrinsic_vnclip_vx_nxv16i8_nxv16i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vnclip.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -955,8 +955,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i8.nxv16i16( define @intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vnclip.nxv32i8.nxv32i16( define @intrinsic_vnclip_vx_nxv32i8_nxv32i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vnclip.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1003,8 +1003,8 @@ declare @llvm.riscv.vnclip.mask.nxv32i8.nxv32i16( define @intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vnclip.nxv1i16.nxv1i32( define @intrinsic_vnclip_vx_nxv1i16_nxv1i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1050,8 +1050,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i16.nxv1i32( define @intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1073,8 +1073,8 @@ declare @llvm.riscv.vnclip.nxv2i16.nxv2i32( define @intrinsic_vnclip_vx_nxv2i16_nxv2i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i16.nxv2i32( define @intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1120,8 +1120,8 @@ declare @llvm.riscv.vnclip.nxv4i16.nxv4i32( define @intrinsic_vnclip_vx_nxv4i16_nxv4i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vnclip.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i16.nxv4i32( define @intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1168,8 +1168,8 @@ declare @llvm.riscv.vnclip.nxv8i16.nxv8i32( define @intrinsic_vnclip_vx_nxv8i16_nxv8i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vnclip.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i16.nxv8i32( define @intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1216,8 +1216,8 @@ declare @llvm.riscv.vnclip.nxv16i16.nxv16i32( define @intrinsic_vnclip_vx_nxv16i16_nxv16i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vnclip.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vnclip.mask.nxv16i16.nxv16i32( define @intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1264,8 +1264,8 @@ declare @llvm.riscv.vnclip.nxv1i32.nxv1i64( define @intrinsic_vnclip_vx_nxv1i32_nxv1i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vnclip.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1288,8 +1288,8 @@ declare @llvm.riscv.vnclip.mask.nxv1i32.nxv1i64( define @intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1311,8 +1311,8 @@ declare @llvm.riscv.vnclip.nxv2i32.nxv2i64( define @intrinsic_vnclip_vx_nxv2i32_nxv2i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vnclip.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1336,8 +1336,8 @@ declare @llvm.riscv.vnclip.mask.nxv2i32.nxv2i64( define @intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vnclip.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1359,8 +1359,8 @@ declare @llvm.riscv.vnclip.nxv4i32.nxv4i64( define @intrinsic_vnclip_vx_nxv4i32_nxv4i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vnclip.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1384,8 +1384,8 @@ declare @llvm.riscv.vnclip.mask.nxv4i32.nxv4i64( define @intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vnclip.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1407,8 +1407,8 @@ declare @llvm.riscv.vnclip.nxv8i32.nxv8i64( define @intrinsic_vnclip_vx_nxv8i32_nxv8i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vnclip.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1432,8 +1432,8 @@ declare @llvm.riscv.vnclip.mask.nxv8i32.nxv8i64( define @intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vnclip.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1450,8 +1450,8 @@ entry: define @intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1467,8 +1467,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1485,8 +1485,8 @@ entry: define @intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1502,8 +1502,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1520,8 +1520,8 @@ entry: define @intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1537,8 +1537,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ entry: define @intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclip.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1573,8 +1573,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1591,8 +1591,8 @@ entry: define @intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclip.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1609,8 +1609,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ entry: define @intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclip.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1645,8 +1645,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1663,8 +1663,8 @@ entry: define @intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1680,8 +1680,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1698,8 +1698,8 @@ entry: define @intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1715,8 +1715,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1733,8 +1733,8 @@ entry: define @intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclip.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1751,8 +1751,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ entry: define @intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclip.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1787,8 +1787,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1805,8 +1805,8 @@ entry: define @intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclip.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1823,8 +1823,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ entry: define @intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclip.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1858,8 +1858,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1876,8 +1876,8 @@ entry: define @intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclip.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1894,8 +1894,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclip.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1912,8 +1912,8 @@ entry: define @intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclip.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1930,8 +1930,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclip.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1948,8 +1948,8 @@ entry: define @intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclip_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclip.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1966,8 +1966,8 @@ entry: define @intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclip_mask_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclip.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll b/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll index 39980504f887..a1804e7d98a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vnclipu.ll @@ -13,8 +13,8 @@ declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -37,8 +37,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16.nxv1i8( define @intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i8_nxv1i16_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -85,8 +85,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16.nxv2i8( define @intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i8_nxv2i16_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -109,8 +109,8 @@ declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -133,8 +133,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16.nxv4i8( define @intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i8_nxv4i16_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -157,8 +157,8 @@ declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclipu.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -182,8 +182,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16.nxv8i8( define @intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i8_nxv8i16_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -206,8 +206,8 @@ declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclipu.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -231,8 +231,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16.nxv16i8( define @intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i8_nxv16i16_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vnclipu.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclipu.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -280,8 +280,8 @@ declare @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16.nxv32i8( define @intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv32i8_nxv32i16_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -304,8 +304,8 @@ declare @llvm.riscv.vnclipu.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32.nxv1i16( define @intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i16_nxv1i32_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -352,8 +352,8 @@ declare @llvm.riscv.vnclipu.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32.nxv2i16( define @intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i16_nxv2i32_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vnclipu.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclipu.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -425,8 +425,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32.nxv4i16( define @intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i16_nxv4i32_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -449,8 +449,8 @@ declare @llvm.riscv.vnclipu.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclipu.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -474,8 +474,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32.nxv8i16( define @intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i16_nxv8i32_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -498,8 +498,8 @@ declare @llvm.riscv.vnclipu.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclipu.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -523,8 +523,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32.nxv16i16( define @intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv16i16_nxv16i32_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -547,8 +547,8 @@ declare @llvm.riscv.vnclipu.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclipu.wv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -571,8 +571,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64.nxv1i32( define @intrinsic_vnclipu_mask_wv_nxv1i32_nxv1i64_nxv1i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv1i32_nxv1i64_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -595,8 +595,8 @@ declare @llvm.riscv.vnclipu.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclipu.wv v11, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: ret @@ -620,8 +620,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64.nxv2i32( define @intrinsic_vnclipu_mask_wv_nxv2i32_nxv2i64_nxv2i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv2i32_nxv2i64_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v10, v9, v0.t ; CHECK-NEXT: ret entry: @@ -644,8 +644,8 @@ declare @llvm.riscv.vnclipu.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclipu.wv v14, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: ret @@ -669,8 +669,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64.nxv4i32( define @intrinsic_vnclipu_mask_wv_nxv4i32_nxv4i64_nxv4i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv4i32_nxv4i64_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v12, v10, v0.t ; CHECK-NEXT: ret entry: @@ -693,8 +693,8 @@ declare @llvm.riscv.vnclipu.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclipu.wv v20, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v20 ; CHECK-NEXT: ret @@ -718,8 +718,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64.nxv8i32( define @intrinsic_vnclipu_mask_wv_nxv8i32_nxv8i64_nxv8i32( %0, %1, %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_wv_nxv8i32_nxv8i64_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclipu.wv v8, v16, v12, v0.t ; CHECK-NEXT: ret entry: @@ -741,8 +741,8 @@ declare @llvm.riscv.vnclipu.nxv1i8.nxv1i16( define @intrinsic_vnclipu_vx_nxv1i8_nxv1i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -765,8 +765,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i8.nxv1i16( define @intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i8_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -788,8 +788,8 @@ declare @llvm.riscv.vnclipu.nxv2i8.nxv2i16( define @intrinsic_vnclipu_vx_nxv2i8_nxv2i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -812,8 +812,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i8.nxv2i16( define @intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i8_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -835,8 +835,8 @@ declare @llvm.riscv.vnclipu.nxv4i8.nxv4i16( define @intrinsic_vnclipu_vx_nxv4i8_nxv4i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i8.nxv4i16( define @intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i8_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vnclipu.nxv8i8.nxv8i16( define @intrinsic_vnclipu_vx_nxv8i8_nxv8i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vnclipu.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -907,8 +907,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i8.nxv8i16( define @intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i8_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vnclipu.nxv16i8.nxv16i16( define @intrinsic_vnclipu_vx_nxv16i8_nxv16i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vnclipu.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -955,8 +955,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i8.nxv16i16( define @intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i8_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vnclipu.nxv32i8.nxv32i16( define @intrinsic_vnclipu_vx_nxv32i8_nxv32i16( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vnclipu.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1003,8 +1003,8 @@ declare @llvm.riscv.vnclipu.mask.nxv32i8.nxv32i16( define @intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv32i8_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vnclipu.nxv1i16.nxv1i32( define @intrinsic_vnclipu_vx_nxv1i16_nxv1i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1050,8 +1050,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i16.nxv1i32( define @intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i16_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1073,8 +1073,8 @@ declare @llvm.riscv.vnclipu.nxv2i16.nxv2i32( define @intrinsic_vnclipu_vx_nxv2i16_nxv2i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i16.nxv2i32( define @intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i16_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1120,8 +1120,8 @@ declare @llvm.riscv.vnclipu.nxv4i16.nxv4i32( define @intrinsic_vnclipu_vx_nxv4i16_nxv4i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vnclipu.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1145,8 +1145,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i16.nxv4i32( define @intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i16_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1168,8 +1168,8 @@ declare @llvm.riscv.vnclipu.nxv8i16.nxv8i32( define @intrinsic_vnclipu_vx_nxv8i16_nxv8i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vnclipu.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1193,8 +1193,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i16.nxv8i32( define @intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i16_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1216,8 +1216,8 @@ declare @llvm.riscv.vnclipu.nxv16i16.nxv16i32( define @intrinsic_vnclipu_vx_nxv16i16_nxv16i32( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vnclipu.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1241,8 +1241,8 @@ declare @llvm.riscv.vnclipu.mask.nxv16i16.nxv16i32( define @intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv16i16_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1264,8 +1264,8 @@ declare @llvm.riscv.vnclipu.nxv1i32.nxv1i64( define @intrinsic_vnclipu_vx_nxv1i32_nxv1i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vnclipu.wx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1288,8 +1288,8 @@ declare @llvm.riscv.vnclipu.mask.nxv1i32.nxv1i64( define @intrinsic_vnclipu_mask_vx_nxv1i32_nxv1i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv1i32_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1311,8 +1311,8 @@ declare @llvm.riscv.vnclipu.nxv2i32.nxv2i64( define @intrinsic_vnclipu_vx_nxv2i32_nxv2i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vnclipu.wx v10, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1336,8 +1336,8 @@ declare @llvm.riscv.vnclipu.mask.nxv2i32.nxv2i64( define @intrinsic_vnclipu_mask_vx_nxv2i32_nxv2i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv2i32_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1359,8 +1359,8 @@ declare @llvm.riscv.vnclipu.nxv4i32.nxv4i64( define @intrinsic_vnclipu_vx_nxv4i32_nxv4i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vnclipu.wx v12, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1384,8 +1384,8 @@ declare @llvm.riscv.vnclipu.mask.nxv4i32.nxv4i64( define @intrinsic_vnclipu_mask_vx_nxv4i32_nxv4i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv4i32_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1407,8 +1407,8 @@ declare @llvm.riscv.vnclipu.nxv8i32.nxv8i64( define @intrinsic_vnclipu_vx_nxv8i32_nxv8i64( %0, iXLen %1, iXLen %2) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vnclipu.wx v16, v8, a0 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1432,8 +1432,8 @@ declare @llvm.riscv.vnclipu.mask.nxv8i32.nxv8i64( define @intrinsic_vnclipu_mask_vx_nxv8i32_nxv8i64( %0, %1, iXLen %2, %3, iXLen %4) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vx_nxv8i32_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vnclipu.wx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1450,8 +1450,8 @@ entry: define @intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1467,8 +1467,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i8_nxv1i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1485,8 +1485,8 @@ entry: define @intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1502,8 +1502,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i8_nxv2i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1520,8 +1520,8 @@ entry: define @intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1537,8 +1537,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i8_nxv4i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ entry: define @intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vnclipu.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1573,8 +1573,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i8_nxv8i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1591,8 +1591,8 @@ entry: define @intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vnclipu.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1609,8 +1609,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i8_nxv16i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ entry: define @intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vnclipu.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1645,8 +1645,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv32i8_nxv32i16_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1663,8 +1663,8 @@ entry: define @intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1680,8 +1680,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i16_nxv1i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1698,8 +1698,8 @@ entry: define @intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1715,8 +1715,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i16_nxv2i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1733,8 +1733,8 @@ entry: define @intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vnclipu.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1751,8 +1751,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i16_nxv4i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ entry: define @intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vnclipu.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1787,8 +1787,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i16_nxv8i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1805,8 +1805,8 @@ entry: define @intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vnclipu.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1823,8 +1823,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv16i16_nxv16i32_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1841,8 +1841,8 @@ entry: define @intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vnclipu.wi v8, v8, 9 ; CHECK-NEXT: ret entry: @@ -1858,8 +1858,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv1i32_nxv1i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv1i32_nxv1i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v9, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1876,8 +1876,8 @@ entry: define @intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vnclipu.wi v10, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret @@ -1894,8 +1894,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv2i32_nxv2i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv2i32_nxv2i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v10, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1912,8 +1912,8 @@ entry: define @intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vnclipu.wi v12, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret @@ -1930,8 +1930,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv4i32_nxv4i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv4i32_nxv4i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v12, 9, v0.t ; CHECK-NEXT: ret entry: @@ -1948,8 +1948,8 @@ entry: define @intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32( %0, iXLen %1) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vnclipu.wi v16, v8, 9 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret @@ -1966,8 +1966,8 @@ entry: define @intrinsic_vnclipu_mask_vi_nxv8i32_nxv8i64_i32( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: intrinsic_vnclipu_mask_vi_nxv8i32_nxv8i64_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vnclipu.wi v8, v16, 9, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll index d1fcb0f47cb5..e7d8ae635f75 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv32.ll @@ -15,8 +15,8 @@ declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -39,8 +39,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -63,8 +63,8 @@ declare @llvm.riscv.vsmul.nxv2i8.nxv2i8( define @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -87,8 +87,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.nxv2i8( define @intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -111,8 +111,8 @@ declare @llvm.riscv.vsmul.nxv4i8.nxv4i8( define @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -135,8 +135,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.nxv4i8( define @intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vsmul.nxv8i8.nxv8i8( define @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -183,8 +183,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.nxv8i8( define @intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -207,8 +207,8 @@ declare @llvm.riscv.vsmul.nxv16i8.nxv16i8( define @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -231,8 +231,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.nxv16i8( define @intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vsmul.nxv32i8.nxv32i8( define @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -279,8 +279,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.nxv32i8( define @intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -303,8 +303,8 @@ declare @llvm.riscv.vsmul.nxv64i8.nxv64i8( define @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vsmul.nxv1i16.nxv1i16( define @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.nxv1i16( define @intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vsmul.nxv2i16.nxv2i16( define @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -424,8 +424,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.nxv2i16( define @intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -448,8 +448,8 @@ declare @llvm.riscv.vsmul.nxv4i16.nxv4i16( define @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -472,8 +472,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.nxv4i16( define @intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -496,8 +496,8 @@ declare @llvm.riscv.vsmul.nxv8i16.nxv8i16( define @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -520,8 +520,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.nxv8i16( define @intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -544,8 +544,8 @@ declare @llvm.riscv.vsmul.nxv16i16.nxv16i16( define @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -568,8 +568,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.nxv16i16( define @intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -592,8 +592,8 @@ declare @llvm.riscv.vsmul.nxv32i16.nxv32i16( define @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -617,8 +617,8 @@ define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -641,8 +641,8 @@ declare @llvm.riscv.vsmul.nxv1i32.nxv1i32( define @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -665,8 +665,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.nxv1i32( define @intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -689,8 +689,8 @@ declare @llvm.riscv.vsmul.nxv2i32.nxv2i32( define @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -713,8 +713,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.nxv2i32( define @intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -737,8 +737,8 @@ declare @llvm.riscv.vsmul.nxv4i32.nxv4i32( define @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.nxv4i32( define @intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -785,8 +785,8 @@ declare @llvm.riscv.vsmul.nxv8i32.nxv8i32( define @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -809,8 +809,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.nxv8i32( define @intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -833,8 +833,8 @@ declare @llvm.riscv.vsmul.nxv16i32.nxv16i32( define @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -858,8 +858,8 @@ define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vsmul.nxv1i64.nxv1i64( define @intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -906,8 +906,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( define @intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vsmul.nxv2i64.nxv2i64( define @intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -954,8 +954,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i64.nxv2i64( define @intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vsmul.nxv4i64.nxv4i64( define @intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1002,8 +1002,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i64.nxv4i64( define @intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vsmul.nxv8i64.nxv8i64( define @intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1051,8 +1051,8 @@ define @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vsmul.nxv1i8.i8( define @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1099,8 +1099,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.i8( define @intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1123,8 +1123,8 @@ declare @llvm.riscv.vsmul.nxv2i8.i8( define @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1147,8 +1147,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.i8( define @intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1171,8 +1171,8 @@ declare @llvm.riscv.vsmul.nxv4i8.i8( define @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.i8( define @intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1219,8 +1219,8 @@ declare @llvm.riscv.vsmul.nxv8i8.i8( define @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1243,8 +1243,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.i8( define @intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1267,8 +1267,8 @@ declare @llvm.riscv.vsmul.nxv16i8.i8( define @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1291,8 +1291,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.i8( define @intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1315,8 +1315,8 @@ declare @llvm.riscv.vsmul.nxv32i8.i8( define @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1339,8 +1339,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.i8( define @intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1363,8 +1363,8 @@ declare @llvm.riscv.vsmul.nxv64i8.i8( define @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1387,8 +1387,8 @@ declare @llvm.riscv.vsmul.mask.nxv64i8.i8( define @intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1411,8 +1411,8 @@ declare @llvm.riscv.vsmul.nxv1i16.i16( define @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1435,8 +1435,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.i16( define @intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1459,8 +1459,8 @@ declare @llvm.riscv.vsmul.nxv2i16.i16( define @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1483,8 +1483,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.i16( define @intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1507,8 +1507,8 @@ declare @llvm.riscv.vsmul.nxv4i16.i16( define @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1531,8 +1531,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.i16( define @intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ declare @llvm.riscv.vsmul.nxv8i16.i16( define @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1579,8 +1579,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.i16( define @intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1603,8 +1603,8 @@ declare @llvm.riscv.vsmul.nxv16i16.i16( define @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.i16( define @intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1651,8 +1651,8 @@ declare @llvm.riscv.vsmul.nxv32i16.i16( define @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1675,8 +1675,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i16.i16( define @intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1698,8 +1698,8 @@ declare @llvm.riscv.vsmul.nxv1i32.i32( define @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1722,8 +1722,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.i32( define @intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1745,8 +1745,8 @@ declare @llvm.riscv.vsmul.nxv2i32.i32( define @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1769,8 +1769,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.i32( define @intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1792,8 +1792,8 @@ declare @llvm.riscv.vsmul.nxv4i32.i32( define @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1816,8 +1816,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.i32( define @intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1839,8 +1839,8 @@ declare @llvm.riscv.vsmul.nxv8i32.i32( define @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1863,8 +1863,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.i32( define @intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1886,8 +1886,8 @@ declare @llvm.riscv.vsmul.nxv16i32.i32( define @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i32 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1910,8 +1910,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i32.i32( define @intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i32 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll index 1fe1baf1cef2..66bc5c9103a4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vsmul-rv64.ll @@ -15,8 +15,8 @@ declare @llvm.riscv.vsmul.nxv1i8.nxv1i8( define @intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -39,8 +39,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.nxv1i8( define @intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i8_nxv1i8_nxv1i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -63,8 +63,8 @@ declare @llvm.riscv.vsmul.nxv2i8.nxv2i8( define @intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -87,8 +87,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.nxv2i8( define @intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i8_nxv2i8_nxv2i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -111,8 +111,8 @@ declare @llvm.riscv.vsmul.nxv4i8.nxv4i8( define @intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -135,8 +135,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.nxv4i8( define @intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i8_nxv4i8_nxv4i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vsmul.nxv8i8.nxv8i8( define @intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -183,8 +183,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.nxv8i8( define @intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i8_nxv8i8_nxv8i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -207,8 +207,8 @@ declare @llvm.riscv.vsmul.nxv16i8.nxv16i8( define @intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -231,8 +231,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.nxv16i8( define @intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i8_nxv16i8_nxv16i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -255,8 +255,8 @@ declare @llvm.riscv.vsmul.nxv32i8.nxv32i8( define @intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -279,8 +279,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.nxv32i8( define @intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i8_nxv32i8_nxv32i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -303,8 +303,8 @@ declare @llvm.riscv.vsmul.nxv64i8.nxv64i8( define @intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv64i8_nxv64i8_nxv64i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -328,8 +328,8 @@ define @intrinsic_vsmul_mask_vv_nxv64i8_nxv64i8_nxv64i8( @llvm.riscv.vsmul.nxv1i16.nxv1i16( define @intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -376,8 +376,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.nxv1i16( define @intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i16_nxv1i16_nxv1i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -400,8 +400,8 @@ declare @llvm.riscv.vsmul.nxv2i16.nxv2i16( define @intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -424,8 +424,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.nxv2i16( define @intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i16_nxv2i16_nxv2i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -448,8 +448,8 @@ declare @llvm.riscv.vsmul.nxv4i16.nxv4i16( define @intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -472,8 +472,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.nxv4i16( define @intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i16_nxv4i16_nxv4i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -496,8 +496,8 @@ declare @llvm.riscv.vsmul.nxv8i16.nxv8i16( define @intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -520,8 +520,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.nxv8i16( define @intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i16_nxv8i16_nxv8i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -544,8 +544,8 @@ declare @llvm.riscv.vsmul.nxv16i16.nxv16i16( define @intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -568,8 +568,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.nxv16i16( define @intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i16_nxv16i16_nxv16i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -592,8 +592,8 @@ declare @llvm.riscv.vsmul.nxv32i16.nxv32i16( define @intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -617,8 +617,8 @@ define @intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv32i16_nxv32i16_nxv32i16: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re16.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -641,8 +641,8 @@ declare @llvm.riscv.vsmul.nxv1i32.nxv1i32( define @intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -665,8 +665,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.nxv1i32( define @intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i32_nxv1i32_nxv1i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -689,8 +689,8 @@ declare @llvm.riscv.vsmul.nxv2i32.nxv2i32( define @intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -713,8 +713,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.nxv2i32( define @intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i32_nxv2i32_nxv2i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -737,8 +737,8 @@ declare @llvm.riscv.vsmul.nxv4i32.nxv4i32( define @intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.nxv4i32( define @intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i32_nxv4i32_nxv4i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -785,8 +785,8 @@ declare @llvm.riscv.vsmul.nxv8i32.nxv8i32( define @intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -809,8 +809,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.nxv8i32( define @intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv8i32_nxv8i32_nxv8i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -833,8 +833,8 @@ declare @llvm.riscv.vsmul.nxv16i32.nxv16i32( define @intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -858,8 +858,8 @@ define @intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32(< ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv16i32_nxv16i32_nxv16i32: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: vl8re32.v v24, (a0) -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vv v8, v16, v24, v0.t ; CHECK-NEXT: ret entry: @@ -882,8 +882,8 @@ declare @llvm.riscv.vsmul.nxv1i64.nxv1i64( define @intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -906,8 +906,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( define @intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv1i64_nxv1i64_nxv1i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, mu ; CHECK-NEXT: vsmul.vv v8, v9, v10, v0.t ; CHECK-NEXT: ret entry: @@ -930,8 +930,8 @@ declare @llvm.riscv.vsmul.nxv2i64.nxv2i64( define @intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -954,8 +954,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i64.nxv2i64( define @intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv2i64_nxv2i64_nxv2i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, mu ; CHECK-NEXT: vsmul.vv v8, v10, v12, v0.t ; CHECK-NEXT: ret entry: @@ -978,8 +978,8 @@ declare @llvm.riscv.vsmul.nxv4i64.nxv4i64( define @intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -1002,8 +1002,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i64.nxv4i64( define @intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64( %0, %1, %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vv_nxv4i64_nxv4i64_nxv4i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, mu ; CHECK-NEXT: vsmul.vv v8, v12, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1026,8 +1026,8 @@ declare @llvm.riscv.vsmul.nxv8i64.nxv8i64( define @intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64( %0, %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vv_nxv8i64_nxv8i64_nxv8i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vsmul.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -1051,8 +1051,8 @@ define @intrinsic_vsmul_mask_vv_nxv8i64_nxv8i64_nxv8i64( @llvm.riscv.vsmul.nxv1i8.i8( define @intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1099,8 +1099,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i8.i8( define @intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i8_nxv1i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1123,8 +1123,8 @@ declare @llvm.riscv.vsmul.nxv2i8.i8( define @intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1147,8 +1147,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i8.i8( define @intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i8_nxv2i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1171,8 +1171,8 @@ declare @llvm.riscv.vsmul.nxv4i8.i8( define @intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i8.i8( define @intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i8_nxv4i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1219,8 +1219,8 @@ declare @llvm.riscv.vsmul.nxv8i8.i8( define @intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1243,8 +1243,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i8.i8( define @intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i8_nxv8i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1267,8 +1267,8 @@ declare @llvm.riscv.vsmul.nxv16i8.i8( define @intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1291,8 +1291,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i8.i8( define @intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i8_nxv16i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1315,8 +1315,8 @@ declare @llvm.riscv.vsmul.nxv32i8.i8( define @intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1339,8 +1339,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i8.i8( define @intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i8_nxv32i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1363,8 +1363,8 @@ declare @llvm.riscv.vsmul.nxv64i8.i8( define @intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8( %0, i8 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1387,8 +1387,8 @@ declare @llvm.riscv.vsmul.mask.nxv64i8.i8( define @intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8( %0, %1, i8 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv64i8_nxv64i8_i8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1411,8 +1411,8 @@ declare @llvm.riscv.vsmul.nxv1i16.i16( define @intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1435,8 +1435,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i16.i16( define @intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i16_nxv1i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1459,8 +1459,8 @@ declare @llvm.riscv.vsmul.nxv2i16.i16( define @intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1483,8 +1483,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i16.i16( define @intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i16_nxv2i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1507,8 +1507,8 @@ declare @llvm.riscv.vsmul.nxv4i16.i16( define @intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1531,8 +1531,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i16.i16( define @intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i16_nxv4i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1555,8 +1555,8 @@ declare @llvm.riscv.vsmul.nxv8i16.i16( define @intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1579,8 +1579,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i16.i16( define @intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i16_nxv8i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1603,8 +1603,8 @@ declare @llvm.riscv.vsmul.nxv16i16.i16( define @intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1627,8 +1627,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i16.i16( define @intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i16_nxv16i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1651,8 +1651,8 @@ declare @llvm.riscv.vsmul.nxv32i16.i16( define @intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16( %0, i16 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1675,8 +1675,8 @@ declare @llvm.riscv.vsmul.mask.nxv32i16.i16( define @intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16( %0, %1, i16 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv32i16_nxv32i16_i16: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1699,8 +1699,8 @@ declare @llvm.riscv.vsmul.nxv1i32.i32( define @intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1723,8 +1723,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i32.i32( define @intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i32_nxv1i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1747,8 +1747,8 @@ declare @llvm.riscv.vsmul.nxv2i32.i32( define @intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1771,8 +1771,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i32.i32( define @intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i32_nxv2i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1795,8 +1795,8 @@ declare @llvm.riscv.vsmul.nxv4i32.i32( define @intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1819,8 +1819,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i32.i32( define @intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i32_nxv4i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1843,8 +1843,8 @@ declare @llvm.riscv.vsmul.nxv8i32.i32( define @intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1867,8 +1867,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i32.i32( define @intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i32_nxv8i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1891,8 +1891,8 @@ declare @llvm.riscv.vsmul.nxv16i32.i32( define @intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32( %0, i32 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1915,8 +1915,8 @@ declare @llvm.riscv.vsmul.mask.nxv16i32.i32( define @intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32( %0, %1, i32 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv16i32_nxv16i32_i32: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1938,8 +1938,8 @@ declare @llvm.riscv.vsmul.nxv1i64.i64( define @intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -1962,8 +1962,8 @@ declare @llvm.riscv.vsmul.mask.nxv1i64.i64( define @intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv1i64_nxv1i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, mu ; CHECK-NEXT: vsmul.vx v8, v9, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1985,8 +1985,8 @@ declare @llvm.riscv.vsmul.nxv2i64.i64( define @intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -2009,8 +2009,8 @@ declare @llvm.riscv.vsmul.mask.nxv2i64.i64( define @intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv2i64_nxv2i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, mu ; CHECK-NEXT: vsmul.vx v8, v10, a0, v0.t ; CHECK-NEXT: ret entry: @@ -2032,8 +2032,8 @@ declare @llvm.riscv.vsmul.nxv4i64.i64( define @intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -2056,8 +2056,8 @@ declare @llvm.riscv.vsmul.mask.nxv4i64.i64( define @intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv4i64_nxv4i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, mu ; CHECK-NEXT: vsmul.vx v8, v12, a0, v0.t ; CHECK-NEXT: ret entry: @@ -2079,8 +2079,8 @@ declare @llvm.riscv.vsmul.nxv8i64.i64( define @intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64( %0, i64 %1, i64 %2) nounwind { ; CHECK-LABEL: intrinsic_vsmul_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vsmul.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -2103,8 +2103,8 @@ declare @llvm.riscv.vsmul.mask.nxv8i64.i64( define @intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64( %0, %1, i64 %2, %3, i64 %4) nounwind { ; CHECK-LABEL: intrinsic_vsmul_mask_vx_nxv8i64_nxv8i64_i64: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, mu ; CHECK-NEXT: vsmul.vx v8, v16, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll index 8e28dd490a87..7fd1b05bb444 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv32.ll @@ -5,8 +5,8 @@ define @test_vssra_vv_i8mf8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i32(, define @test_vssra_vx_i8mf8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssra.nxv1i8.i32.i32(, @test_vssra_vv_i8mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i32(, define @test_vssra_vx_i8mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssra.nxv2i8.i32.i32(, @test_vssra_vv_i8mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i32(, define @test_vssra_vx_i8mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssra.nxv4i8.i32.i32(, @test_vssra_vv_i8m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i32(, define @test_vssra_vx_i8m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssra.nxv8i8.i32.i32(, @test_vssra_vv_i8m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i32( @test_vssra_vx_i8m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssra.nxv16i8.i32.i32(, define @test_vssra_vv_i8m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssra.nxv32i8.nxv32i8.i32( @test_vssra_vx_i8m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssra.nxv32i8.i32.i32(, define @test_vssra_vv_i8m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssra.nxv64i8.nxv64i8.i32( @test_vssra_vx_i8m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssra.nxv64i8.i32.i32(, define @test_vssra_vv_i16mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssra.nxv1i16.nxv1i16.i32( @test_vssra_vx_i16mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssra.nxv1i16.i32.i32(, define @test_vssra_vv_i16mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssra.nxv2i16.nxv2i16.i32( @test_vssra_vx_i16mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssra.nxv2i16.i32.i32(, define @test_vssra_vv_i16m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssra.nxv4i16.nxv4i16.i32( @test_vssra_vx_i16m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssra.nxv4i16.i32.i32(, define @test_vssra_vv_i16m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssra.nxv8i16.nxv8i16.i32( @test_vssra_vx_i16m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssra.nxv8i16.i32.i32(, define @test_vssra_vv_i16m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssra.nxv16i16.nxv16i16.i32( @test_vssra_vx_i16m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssra.nxv16i16.i32.i32( @test_vssra_vv_i16m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssra.nxv32i16.nxv32i16.i32( @test_vssra_vx_i16m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssra.nxv32i16.i32.i32( @test_vssra_vv_i32mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssra.nxv1i32.nxv1i32.i32( @test_vssra_vx_i32mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssra.nxv1i32.i32.i32(, define @test_vssra_vv_i32m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssra.nxv2i32.nxv2i32.i32( @test_vssra_vx_i32m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssra.nxv2i32.i32.i32(, define @test_vssra_vv_i32m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssra.nxv4i32.nxv4i32.i32( @test_vssra_vx_i32m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssra.nxv4i32.i32.i32(, define @test_vssra_vv_i32m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssra.nxv8i32.nxv8i32.i32( @test_vssra_vx_i32m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssra.nxv8i32.i32.i32(, define @test_vssra_vv_i32m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssra.nxv16i32.nxv16i32.i32( @test_vssra_vx_i32m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssra.nxv16i32.i32.i32( @test_vssra_vv_i64m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssra.nxv1i64.nxv1i64.i32( @test_vssra_vx_i64m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssra.nxv1i64.i32.i32(, define @test_vssra_vv_i64m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssra.nxv2i64.nxv2i64.i32( @test_vssra_vx_i64m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssra.nxv2i64.i32.i32(, define @test_vssra_vv_i64m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssra.nxv4i64.nxv4i64.i32( @test_vssra_vx_i64m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssra.nxv4i64.i32.i32(, define @test_vssra_vv_i64m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssra.nxv8i64.nxv8i64.i32( @test_vssra_vx_i64m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssra.nxv8i64.i32.i32(, define @test_vssra_vv_i8mf8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.nxv1i8.i32( @test_vssra_vx_i8mf8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.i32.i32( @test_vssra_vv_i8mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.nxv2i8.i32( @test_vssra_vx_i8mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.i32.i32( @test_vssra_vv_i8mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.nxv4i8.i32( @test_vssra_vx_i8mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.i32.i32( @test_vssra_vv_i8m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.nxv8i8.i32( @test_vssra_vx_i8m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.i32.i32( @test_vssra_vv_i8m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.nxv16i8.i32( @test_vssra_vx_i8m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.i32.i32( @test_vssra_vv_i8m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.nxv32i8.i32( @test_vssra_vx_i8m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.i32.i32( @test_vssra_vv_i8m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.nxv64i8.i32( @test_vssra_vx_i8m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.i32.i32( @test_vssra_vv_i16mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.nxv1i16.i32( @test_vssra_vx_i16mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.i32.i32( @test_vssra_vv_i16mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.nxv2i16.i32( @test_vssra_vx_i16mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.i32.i32( @test_vssra_vv_i16m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.nxv4i16.i32( @test_vssra_vx_i16m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.i32.i32( @test_vssra_vv_i16m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.nxv8i16.i32( @test_vssra_vx_i16m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.i32.i32( @test_vssra_vv_i16m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.nxv16i16.i32( @test_vssra_vx_i16m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.i32.i32( @test_vssra_vv_i16m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.nxv32i16.i32( @test_vssra_vx_i16m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.i32.i32( @test_vssra_vv_i32mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.nxv1i32.i32( @test_vssra_vx_i32mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.i32.i32( @test_vssra_vv_i32m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.nxv2i32.i32( @test_vssra_vx_i32m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.i32.i32( @test_vssra_vv_i32m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.nxv4i32.i32( @test_vssra_vx_i32m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.i32.i32( @test_vssra_vv_i32m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.nxv8i32.i32( @test_vssra_vx_i32m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.i32.i32( @test_vssra_vv_i32m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.nxv16i32.i32( @test_vssra_vx_i32m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.i32.i32( @test_vssra_vv_i64m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.nxv1i64.i32( @test_vssra_vx_i64m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.i32.i32( @test_vssra_vv_i64m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.nxv2i64.i32( @test_vssra_vx_i64m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.i32.i32( @test_vssra_vv_i64m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.nxv4i64.i32( @test_vssra_vx_i64m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.i32.i32( @test_vssra_vv_i64m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssra.mask.nxv8i64.nxv8i64.i32( @test_vssra_vx_i64m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll index 96ca5e32cf36..b7a84e58e6e6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssra-rv64.ll @@ -5,8 +5,8 @@ define @test_vssra_vv_i8mf8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssra.nxv1i8.nxv1i8.i64(, define @test_vssra_vx_i8mf8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssra.nxv1i8.i64.i64(, @test_vssra_vv_i8mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssra.nxv2i8.nxv2i8.i64(, define @test_vssra_vx_i8mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssra.nxv2i8.i64.i64(, @test_vssra_vv_i8mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssra.nxv4i8.nxv4i8.i64(, define @test_vssra_vx_i8mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssra.nxv4i8.i64.i64(, @test_vssra_vv_i8m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssra.nxv8i8.nxv8i8.i64(, define @test_vssra_vx_i8m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssra.nxv8i8.i64.i64(, @test_vssra_vv_i8m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssra.nxv16i8.nxv16i8.i64( @test_vssra_vx_i8m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssra.nxv16i8.i64.i64(, define @test_vssra_vv_i8m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssra.nxv32i8.nxv32i8.i64( @test_vssra_vx_i8m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssra.nxv32i8.i64.i64(, define @test_vssra_vv_i8m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssra.nxv64i8.nxv64i8.i64( @test_vssra_vx_i8m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssra.nxv64i8.i64.i64(, define @test_vssra_vv_i16mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssra.nxv1i16.nxv1i16.i64( @test_vssra_vx_i16mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssra.nxv1i16.i64.i64(, define @test_vssra_vv_i16mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssra.nxv2i16.nxv2i16.i64( @test_vssra_vx_i16mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssra.nxv2i16.i64.i64(, define @test_vssra_vv_i16m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssra.nxv4i16.nxv4i16.i64( @test_vssra_vx_i16m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssra.nxv4i16.i64.i64(, define @test_vssra_vv_i16m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssra.nxv8i16.nxv8i16.i64( @test_vssra_vx_i16m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssra.nxv8i16.i64.i64(, define @test_vssra_vv_i16m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssra.nxv16i16.nxv16i16.i64( @test_vssra_vx_i16m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssra.nxv16i16.i64.i64( @test_vssra_vv_i16m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssra.nxv32i16.nxv32i16.i64( @test_vssra_vx_i16m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssra.nxv32i16.i64.i64( @test_vssra_vv_i32mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssra.nxv1i32.nxv1i32.i64( @test_vssra_vx_i32mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssra.nxv1i32.i64.i64(, define @test_vssra_vv_i32m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssra.nxv2i32.nxv2i32.i64( @test_vssra_vx_i32m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssra.nxv2i32.i64.i64(, define @test_vssra_vv_i32m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssra.nxv4i32.nxv4i32.i64( @test_vssra_vx_i32m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssra.nxv4i32.i64.i64(, define @test_vssra_vv_i32m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssra.nxv8i32.nxv8i32.i64( @test_vssra_vx_i32m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssra.nxv8i32.i64.i64(, define @test_vssra_vv_i32m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssra.nxv16i32.nxv16i32.i64( @test_vssra_vx_i32m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssra.nxv16i32.i64.i64( @test_vssra_vv_i64m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssra.nxv1i64.nxv1i64.i64( @test_vssra_vx_i64m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssra.nxv1i64.i64.i64(, define @test_vssra_vv_i64m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssra.nxv2i64.nxv2i64.i64( @test_vssra_vx_i64m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssra.nxv2i64.i64.i64(, define @test_vssra_vv_i64m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssra.nxv4i64.nxv4i64.i64( @test_vssra_vx_i64m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssra.nxv4i64.i64.i64(, define @test_vssra_vv_i64m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssra.nxv8i64.nxv8i64.i64( @test_vssra_vx_i64m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssra.nxv8i64.i64.i64(, define @test_vssra_vv_i8mf8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.nxv1i8.i64( @test_vssra_vx_i8mf8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssra.mask.nxv1i8.i64.i64( @test_vssra_vv_i8mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.nxv2i8.i64( @test_vssra_vx_i8mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssra.mask.nxv2i8.i64.i64( @test_vssra_vv_i8mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.nxv4i8.i64( @test_vssra_vx_i8mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssra.mask.nxv4i8.i64.i64( @test_vssra_vv_i8m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.nxv8i8.i64( @test_vssra_vx_i8m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssra.mask.nxv8i8.i64.i64( @test_vssra_vv_i8m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.nxv16i8.i64( @test_vssra_vx_i8m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssra.mask.nxv16i8.i64.i64( @test_vssra_vv_i8m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.nxv32i8.i64( @test_vssra_vx_i8m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssra.mask.nxv32i8.i64.i64( @test_vssra_vv_i8m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.nxv64i8.i64( @test_vssra_vx_i8m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssra.mask.nxv64i8.i64.i64( @test_vssra_vv_i16mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.nxv1i16.i64( @test_vssra_vx_i16mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssra.mask.nxv1i16.i64.i64( @test_vssra_vv_i16mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.nxv2i16.i64( @test_vssra_vx_i16mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssra.mask.nxv2i16.i64.i64( @test_vssra_vv_i16m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.nxv4i16.i64( @test_vssra_vx_i16m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssra.mask.nxv4i16.i64.i64( @test_vssra_vv_i16m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.nxv8i16.i64( @test_vssra_vx_i16m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssra.mask.nxv8i16.i64.i64( @test_vssra_vv_i16m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.nxv16i16.i64( @test_vssra_vx_i16m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssra.mask.nxv16i16.i64.i64( @test_vssra_vv_i16m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.nxv32i16.i64( @test_vssra_vx_i16m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssra.mask.nxv32i16.i64.i64( @test_vssra_vv_i32mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.nxv1i32.i64( @test_vssra_vx_i32mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssra.mask.nxv1i32.i64.i64( @test_vssra_vv_i32m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.nxv2i32.i64( @test_vssra_vx_i32m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssra.mask.nxv2i32.i64.i64( @test_vssra_vv_i32m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.nxv4i32.i64( @test_vssra_vx_i32m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssra.mask.nxv4i32.i64.i64( @test_vssra_vv_i32m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.nxv8i32.i64( @test_vssra_vx_i32m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssra.mask.nxv8i32.i64.i64( @test_vssra_vv_i32m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.nxv16i32.i64( @test_vssra_vx_i32m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssra.mask.nxv16i32.i64.i64( @test_vssra_vv_i64m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.nxv1i64.i64( @test_vssra_vx_i64m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssra.mask.nxv1i64.i64.i64( @test_vssra_vv_i64m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.nxv2i64.i64( @test_vssra_vx_i64m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssra.mask.nxv2i64.i64.i64( @test_vssra_vv_i64m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.nxv4i64.i64( @test_vssra_vx_i64m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssra.mask.nxv4i64.i64.i64( @test_vssra_vv_i64m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vv_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssra.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssra.mask.nxv8i64.nxv8i64.i64( @test_vssra_vx_i64m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssra_vx_i64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssra.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll index c1a064984dcc..0c2cdff65776 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv32.ll @@ -5,8 +5,8 @@ define @test_vssrl_vv_u8mf8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i32(, define @test_vssrl_vx_u8mf8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssrl.nxv1i8.i32.i32(, @test_vssrl_vv_u8mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i32(, define @test_vssrl_vx_u8mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssrl.nxv2i8.i32.i32(, @test_vssrl_vv_u8mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i32(, define @test_vssrl_vx_u8mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssrl.nxv4i8.i32.i32(, @test_vssrl_vv_u8m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i32(, define @test_vssrl_vx_u8m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssrl.nxv8i8.i32.i32(, @test_vssrl_vv_u8m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i32( @test_vssrl_vx_u8m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssrl.nxv16i8.i32.i32(, define @test_vssrl_vv_u8m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssrl.nxv32i8.nxv32i8.i32( @test_vssrl_vx_u8m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssrl.nxv32i8.i32.i32(, define @test_vssrl_vv_u8m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssrl.nxv64i8.nxv64i8.i32( @test_vssrl_vx_u8m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssrl.nxv64i8.i32.i32(, define @test_vssrl_vv_u16mf4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssrl.nxv1i16.nxv1i16.i32( @test_vssrl_vx_u16mf4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssrl.nxv1i16.i32.i32(, define @test_vssrl_vv_u16mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssrl.nxv2i16.nxv2i16.i32( @test_vssrl_vx_u16mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssrl.nxv2i16.i32.i32(, define @test_vssrl_vv_u16m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssrl.nxv4i16.nxv4i16.i32( @test_vssrl_vx_u16m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssrl.nxv4i16.i32.i32(, define @test_vssrl_vv_u16m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssrl.nxv8i16.nxv8i16.i32( @test_vssrl_vx_u16m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssrl.nxv8i16.i32.i32(, define @test_vssrl_vv_u16m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssrl.nxv16i16.nxv16i16.i32( @test_vssrl_vx_u16m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssrl.nxv16i16.i32.i32( @test_vssrl_vv_u16m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssrl.nxv32i16.nxv32i16.i32( @test_vssrl_vx_u16m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssrl.nxv32i16.i32.i32( @test_vssrl_vv_u32mf2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssrl.nxv1i32.nxv1i32.i32( @test_vssrl_vx_u32mf2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssrl.nxv1i32.i32.i32(, define @test_vssrl_vv_u32m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssrl.nxv2i32.nxv2i32.i32( @test_vssrl_vx_u32m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssrl.nxv2i32.i32.i32(, define @test_vssrl_vv_u32m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssrl.nxv4i32.nxv4i32.i32( @test_vssrl_vx_u32m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssrl.nxv4i32.i32.i32(, define @test_vssrl_vv_u32m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssrl.nxv8i32.nxv8i32.i32( @test_vssrl_vx_u32m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssrl.nxv8i32.i32.i32(, define @test_vssrl_vv_u32m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssrl.nxv16i32.nxv16i32.i32( @test_vssrl_vx_u32m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssrl.nxv16i32.i32.i32( @test_vssrl_vv_u64m1( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssrl.nxv1i64.nxv1i64.i32( @test_vssrl_vx_u64m1( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssrl.nxv1i64.i32.i32(, define @test_vssrl_vv_u64m2( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssrl.nxv2i64.nxv2i64.i32( @test_vssrl_vx_u64m2( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssrl.nxv2i64.i32.i32(, define @test_vssrl_vv_u64m4( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssrl.nxv4i64.nxv4i64.i32( @test_vssrl_vx_u64m4( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssrl.nxv4i64.i32.i32(, define @test_vssrl_vv_u64m8( %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssrl.nxv8i64.nxv8i64.i32( @test_vssrl_vx_u64m8( %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssrl.nxv8i64.i32.i32(, define @test_vssrl_vv_u8mf8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8.i32( @test_vssrl_vx_u8mf8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.i32.i32( @test_vssrl_vv_u8mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.nxv2i8.i32( @test_vssrl_vx_u8mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.i32.i32( @test_vssrl_vv_u8mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.nxv4i8.i32( @test_vssrl_vx_u8mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.i32.i32( @test_vssrl_vv_u8m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.nxv8i8.i32( @test_vssrl_vx_u8m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.i32.i32( @test_vssrl_vv_u8m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.nxv16i8.i32( @test_vssrl_vx_u8m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.i32.i32( @test_vssrl_vv_u8m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.nxv32i8.i32( @test_vssrl_vx_u8m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.i32.i32( @test_vssrl_vv_u8m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8.i32( @test_vssrl_vx_u8m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.i32.i32( @test_vssrl_vv_u16mf4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.nxv1i16.i32( @test_vssrl_vx_u16mf4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.i32.i32( @test_vssrl_vv_u16mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.nxv2i16.i32( @test_vssrl_vx_u16mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.i32.i32( @test_vssrl_vv_u16m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.nxv4i16.i32( @test_vssrl_vx_u16m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.i32.i32( @test_vssrl_vv_u16m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.nxv8i16.i32( @test_vssrl_vx_u16m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.i32.i32( @test_vssrl_vv_u16m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.nxv16i16.i32( @test_vssrl_vx_u16m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.i32.i32( @test_vssrl_vv_u16m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16.i32( @test_vssrl_vx_u16m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.i32.i32( @test_vssrl_vv_u32mf2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.nxv1i32.i32( @test_vssrl_vx_u32mf2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.i32.i32( @test_vssrl_vv_u32m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.nxv2i32.i32( @test_vssrl_vx_u32m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.i32.i32( @test_vssrl_vv_u32m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.nxv4i32.i32( @test_vssrl_vx_u32m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.i32.i32( @test_vssrl_vv_u32m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.nxv8i32.i32( @test_vssrl_vx_u32m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.i32.i32( @test_vssrl_vv_u32m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32.i32( @test_vssrl_vx_u32m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.i32.i32( @test_vssrl_vv_u64m1_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64.i32( @test_vssrl_vx_u64m1_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.i32.i32( @test_vssrl_vv_u64m2_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64.i32( @test_vssrl_vx_u64m2_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.i32.i32( @test_vssrl_vv_u64m4_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64.i32( @test_vssrl_vx_u64m4_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.i32.i32( @test_vssrl_vv_u64m8_m( %mask, %op1, %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64.i32( @test_vssrl_vx_u64m8_m( %mask, %op1, i32 %shift, i32 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll index 0a465db64b7a..fe80854bb264 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vssrl-rv64.ll @@ -5,8 +5,8 @@ define @test_vssrl_vv_u8mf8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -19,8 +19,8 @@ declare @llvm.riscv.vssrl.nxv1i8.nxv1i8.i64(, define @test_vssrl_vx_u8mf8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -33,8 +33,8 @@ declare @llvm.riscv.vssrl.nxv1i8.i64.i64(, @test_vssrl_vv_u8mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -47,8 +47,8 @@ declare @llvm.riscv.vssrl.nxv2i8.nxv2i8.i64(, define @test_vssrl_vx_u8mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -61,8 +61,8 @@ declare @llvm.riscv.vssrl.nxv2i8.i64.i64(, @test_vssrl_vv_u8mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -75,8 +75,8 @@ declare @llvm.riscv.vssrl.nxv4i8.nxv4i8.i64(, define @test_vssrl_vx_u8mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -89,8 +89,8 @@ declare @llvm.riscv.vssrl.nxv4i8.i64.i64(, @test_vssrl_vv_u8m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -103,8 +103,8 @@ declare @llvm.riscv.vssrl.nxv8i8.nxv8i8.i64(, define @test_vssrl_vx_u8m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -117,8 +117,8 @@ declare @llvm.riscv.vssrl.nxv8i8.i64.i64(, @test_vssrl_vv_u8m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -131,8 +131,8 @@ declare @llvm.riscv.vssrl.nxv16i8.nxv16i8.i64( @test_vssrl_vx_u8m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -145,8 +145,8 @@ declare @llvm.riscv.vssrl.nxv16i8.i64.i64(, define @test_vssrl_vv_u8m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -159,8 +159,8 @@ declare @llvm.riscv.vssrl.nxv32i8.nxv32i8.i64( @test_vssrl_vx_u8m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -173,8 +173,8 @@ declare @llvm.riscv.vssrl.nxv32i8.i64.i64(, define @test_vssrl_vv_u8m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -187,8 +187,8 @@ declare @llvm.riscv.vssrl.nxv64i8.nxv64i8.i64( @test_vssrl_vx_u8m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -201,8 +201,8 @@ declare @llvm.riscv.vssrl.nxv64i8.i64.i64(, define @test_vssrl_vv_u16mf4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -215,8 +215,8 @@ declare @llvm.riscv.vssrl.nxv1i16.nxv1i16.i64( @test_vssrl_vx_u16mf4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -229,8 +229,8 @@ declare @llvm.riscv.vssrl.nxv1i16.i64.i64(, define @test_vssrl_vv_u16mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -243,8 +243,8 @@ declare @llvm.riscv.vssrl.nxv2i16.nxv2i16.i64( @test_vssrl_vx_u16mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -257,8 +257,8 @@ declare @llvm.riscv.vssrl.nxv2i16.i64.i64(, define @test_vssrl_vv_u16m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -271,8 +271,8 @@ declare @llvm.riscv.vssrl.nxv4i16.nxv4i16.i64( @test_vssrl_vx_u16m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -285,8 +285,8 @@ declare @llvm.riscv.vssrl.nxv4i16.i64.i64(, define @test_vssrl_vv_u16m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -299,8 +299,8 @@ declare @llvm.riscv.vssrl.nxv8i16.nxv8i16.i64( @test_vssrl_vx_u16m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -313,8 +313,8 @@ declare @llvm.riscv.vssrl.nxv8i16.i64.i64(, define @test_vssrl_vv_u16m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -327,8 +327,8 @@ declare @llvm.riscv.vssrl.nxv16i16.nxv16i16.i64( @test_vssrl_vx_u16m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -341,8 +341,8 @@ declare @llvm.riscv.vssrl.nxv16i16.i64.i64( @test_vssrl_vv_u16m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -355,8 +355,8 @@ declare @llvm.riscv.vssrl.nxv32i16.nxv32i16.i64( @test_vssrl_vx_u16m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -369,8 +369,8 @@ declare @llvm.riscv.vssrl.nxv32i16.i64.i64( @test_vssrl_vv_u32mf2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -383,8 +383,8 @@ declare @llvm.riscv.vssrl.nxv1i32.nxv1i32.i64( @test_vssrl_vx_u32mf2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -397,8 +397,8 @@ declare @llvm.riscv.vssrl.nxv1i32.i64.i64(, define @test_vssrl_vv_u32m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -411,8 +411,8 @@ declare @llvm.riscv.vssrl.nxv2i32.nxv2i32.i64( @test_vssrl_vx_u32m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -425,8 +425,8 @@ declare @llvm.riscv.vssrl.nxv2i32.i64.i64(, define @test_vssrl_vv_u32m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -439,8 +439,8 @@ declare @llvm.riscv.vssrl.nxv4i32.nxv4i32.i64( @test_vssrl_vx_u32m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -453,8 +453,8 @@ declare @llvm.riscv.vssrl.nxv4i32.i64.i64(, define @test_vssrl_vv_u32m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -467,8 +467,8 @@ declare @llvm.riscv.vssrl.nxv8i32.nxv8i32.i64( @test_vssrl_vx_u32m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -481,8 +481,8 @@ declare @llvm.riscv.vssrl.nxv8i32.i64.i64(, define @test_vssrl_vv_u32m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -495,8 +495,8 @@ declare @llvm.riscv.vssrl.nxv16i32.nxv16i32.i64( @test_vssrl_vx_u32m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -509,8 +509,8 @@ declare @llvm.riscv.vssrl.nxv16i32.i64.i64( @test_vssrl_vv_u64m1( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9 ; CHECK-NEXT: ret entry: @@ -523,8 +523,8 @@ declare @llvm.riscv.vssrl.nxv1i64.nxv1i64.i64( @test_vssrl_vx_u64m1( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -537,8 +537,8 @@ declare @llvm.riscv.vssrl.nxv1i64.i64.i64(, define @test_vssrl_vv_u64m2( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -551,8 +551,8 @@ declare @llvm.riscv.vssrl.nxv2i64.nxv2i64.i64( @test_vssrl_vx_u64m2( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -565,8 +565,8 @@ declare @llvm.riscv.vssrl.nxv2i64.i64.i64(, define @test_vssrl_vv_u64m4( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12 ; CHECK-NEXT: ret entry: @@ -579,8 +579,8 @@ declare @llvm.riscv.vssrl.nxv4i64.nxv4i64.i64( @test_vssrl_vx_u64m4( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -593,8 +593,8 @@ declare @llvm.riscv.vssrl.nxv4i64.i64.i64(, define @test_vssrl_vv_u64m8( %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16 ; CHECK-NEXT: ret entry: @@ -607,8 +607,8 @@ declare @llvm.riscv.vssrl.nxv8i64.nxv8i64.i64( @test_vssrl_vx_u64m8( %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0 ; CHECK-NEXT: ret entry: @@ -621,8 +621,8 @@ declare @llvm.riscv.vssrl.nxv8i64.i64.i64(, define @test_vssrl_vv_u8mf8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -635,8 +635,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.nxv1i8.i64( @test_vssrl_vx_u8mf8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -649,8 +649,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i8.i64.i64( @test_vssrl_vv_u8mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -663,8 +663,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.nxv2i8.i64( @test_vssrl_vx_u8mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -677,8 +677,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i8.i64.i64( @test_vssrl_vv_u8mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -691,8 +691,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.nxv4i8.i64( @test_vssrl_vx_u8mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -705,8 +705,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i8.i64.i64( @test_vssrl_vv_u8m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -719,8 +719,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.nxv8i8.i64( @test_vssrl_vx_u8m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -733,8 +733,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i8.i64.i64( @test_vssrl_vv_u8m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -747,8 +747,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.nxv16i8.i64( @test_vssrl_vx_u8m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -761,8 +761,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i8.i64.i64( @test_vssrl_vv_u8m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -775,8 +775,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.nxv32i8.i64( @test_vssrl_vx_u8m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -789,8 +789,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i8.i64.i64( @test_vssrl_vv_u8m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -803,8 +803,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.nxv64i8.i64( @test_vssrl_vx_u8m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u8m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -817,8 +817,8 @@ declare @llvm.riscv.vssrl.mask.nxv64i8.i64.i64( @test_vssrl_vv_u16mf4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -831,8 +831,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.nxv1i16.i64( @test_vssrl_vx_u16mf4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -845,8 +845,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i16.i64.i64( @test_vssrl_vv_u16mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -859,8 +859,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.nxv2i16.i64( @test_vssrl_vx_u16mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -873,8 +873,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i16.i64.i64( @test_vssrl_vv_u16m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -887,8 +887,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.nxv4i16.i64( @test_vssrl_vx_u16m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -901,8 +901,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i16.i64.i64( @test_vssrl_vv_u16m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -915,8 +915,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.nxv8i16.i64( @test_vssrl_vx_u16m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -929,8 +929,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i16.i64.i64( @test_vssrl_vv_u16m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -943,8 +943,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.nxv16i16.i64( @test_vssrl_vx_u16m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -957,8 +957,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i16.i64.i64( @test_vssrl_vv_u16m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -971,8 +971,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.nxv32i16.i64( @test_vssrl_vx_u16m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u16m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e16, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -985,8 +985,8 @@ declare @llvm.riscv.vssrl.mask.nxv32i16.i64.i64( @test_vssrl_vv_u32mf2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -999,8 +999,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.nxv1i32.i64( @test_vssrl_vx_u32mf2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32mf2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, mf2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1013,8 +1013,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i32.i64.i64( @test_vssrl_vv_u32m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1027,8 +1027,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.nxv2i32.i64( @test_vssrl_vx_u32m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1041,8 +1041,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i32.i64.i64( @test_vssrl_vv_u32m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1055,8 +1055,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.nxv4i32.i64( @test_vssrl_vx_u32m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1069,8 +1069,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i32.i64.i64( @test_vssrl_vv_u32m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1083,8 +1083,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.nxv8i32.i64( @test_vssrl_vx_u32m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1097,8 +1097,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i32.i64.i64( @test_vssrl_vv_u32m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1111,8 +1111,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.nxv16i32.i64( @test_vssrl_vx_u32m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u32m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e32, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1125,8 +1125,8 @@ declare @llvm.riscv.vssrl.mask.nxv16i32.i64.i64( @test_vssrl_vv_u64m1_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v9, v0.t ; CHECK-NEXT: ret entry: @@ -1139,8 +1139,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.nxv1i64.i64( @test_vssrl_vx_u64m1_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m1_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m1, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1153,8 +1153,8 @@ declare @llvm.riscv.vssrl.mask.nxv1i64.i64.i64( @test_vssrl_vv_u64m2_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v10, v0.t ; CHECK-NEXT: ret entry: @@ -1167,8 +1167,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.nxv2i64.i64( @test_vssrl_vx_u64m2_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m2_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m2, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1181,8 +1181,8 @@ declare @llvm.riscv.vssrl.mask.nxv2i64.i64.i64( @test_vssrl_vv_u64m4_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v12, v0.t ; CHECK-NEXT: ret entry: @@ -1195,8 +1195,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.nxv4i64.i64( @test_vssrl_vx_u64m4_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m4_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m4, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: @@ -1209,8 +1209,8 @@ declare @llvm.riscv.vssrl.mask.nxv4i64.i64.i64( @test_vssrl_vv_u64m8_m( %mask, %op1, %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vv_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vv v8, v8, v16, v0.t ; CHECK-NEXT: ret entry: @@ -1223,8 +1223,8 @@ declare @llvm.riscv.vssrl.mask.nxv8i64.nxv8i64.i64( @test_vssrl_vx_u64m8_m( %mask, %op1, i64 %shift, i64 %vl) { ; CHECK-LABEL: test_vssrl_vx_u64m8_m: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e64, m8, ta, ma ; CHECK-NEXT: vssrl.vx v8, v8, a0, v0.t ; CHECK-NEXT: ret entry: diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll index 10175218a440..c5f34eee3118 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm-insert.ll @@ -20,8 +20,8 @@ declare @llvm.riscv.vasub.nxv1i8.nxv1i8( define @test1( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: test1: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret @@ -44,8 +44,8 @@ entry: define @test2( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: test2: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 2 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: csrwi vxrm, 0 ; CHECK-NEXT: vaadd.vv v8, v8, v10 @@ -80,12 +80,12 @@ define @test3( %0, %1, @test3( %0, %1, @test4( %0, %1, %2, iXLen %3) nounwind { ; CHECK-LABEL: test4: ; CHECK: # %bb.0: # %entry -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v9 ; CHECK-NEXT: #APP ; CHECK-NEXT: #NO_APP -; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v8, v8, v10 ; CHECK-NEXT: ret entry: @@ -174,8 +174,8 @@ define @test5( %0, %1, @test7( %0, %1, @test12(i1 %c1, %0, ; CHECK-LABEL: test12: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a1, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v9, v8, v9 ; CHECK-NEXT: beqz a0, .LBB11_2 ; CHECK-NEXT: # %bb.1: # %block1 @@ -513,8 +513,8 @@ define @test13(i1 %c1, i1 %c2, i1 %c3, %0, < ; CHECK-LABEL: test13: ; CHECK: # %bb.0: # %entry ; CHECK-NEXT: andi a0, a0, 1 -; CHECK-NEXT: vsetvli zero, a3, e8, mf8, ta, ma ; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsetvli zero, a3, e8, mf8, ta, ma ; CHECK-NEXT: vaadd.vv v10, v8, v9 ; CHECK-NEXT: beqz a0, .LBB12_2 ; CHECK-NEXT: # %bb.1: # %block1 diff --git a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir index eac3cfca209e..2bac1eeb9060 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vxrm.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vxrm.mir @@ -11,14 +11,14 @@ body: | ; MIR-LABEL: name: verify_vxrm ; MIR: liveins: $v8, $v9, $x10 ; MIR-NEXT: {{ $}} - ; MIR-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype ; MIR-NEXT: WriteVXRMImm 0, implicit-def $vxrm - ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef $v8, killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vl, implicit $vtype, implicit $vxrm + ; MIR-NEXT: dead $x0 = PseudoVSETVLI killed renamable $x10, 197 /* e8, mf8, ta, ma */, implicit-def $vl, implicit-def $vtype + ; MIR-NEXT: renamable $v8 = PseudoVAADD_VV_MF8 undef $v8, killed renamable $v8, killed renamable $v9, 0, $noreg, 3 /* e8 */, 0 /* tu, mu */, implicit $vxrm, implicit $vl, implicit $vtype ; MIR-NEXT: PseudoRET implicit $v8 ; ASM-LABEL: verify_vxrm: ; ASM: # %bb.0: - ; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; ASM-NEXT: csrwi vxrm, 0 + ; ASM-NEXT: vsetvli zero, a0, e8, mf8, ta, ma ; ASM-NEXT: vaadd.vv v8, v8, v9 ; ASM-NEXT: ret %0:vr = COPY $v8 -- GitLab From 5bde2aa1080ba90021f8f5e0c48744ddfc0d6f15 Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Fri, 10 May 2024 08:34:42 +0200 Subject: [PATCH 005/824] [lldb] Improve type name parsing (#91586) Parsing of '::' scopes in TypeQuery was very naive and failed for names with '::''s in template arguments. Interestingly, one of the functions it was calling (Type::GetTypeScopeAndBasename) was already doing the same thing, and getting it (mostly (*)) right. This refactors the function so that it can return the scope results, fixing the parsing of names like std::vector>::iterator. Two callers of GetTypeScopeAndBasename are deleted as the functions are not used (I presume they stopped being used once we started pruning type search results more eagerly). (*) This implementation is still not correct when one takes c++ operators into account -- e.g., something like `X<&A::operator<>::T` is a legitimate type name. We do have an implementation that is able to handle names like these (CPlusPlusLanguage::MethodName), but using it is not trivial, because it is hidden in a language plugin and specific to method name parsing. --------- Co-authored-by: Michael Buch --- lldb/include/lldb/Symbol/Type.h | 35 ++++- lldb/include/lldb/Symbol/TypeList.h | 9 -- lldb/include/lldb/Symbol/TypeMap.h | 4 - lldb/source/Symbol/Type.cpp | 130 ++++++++---------- lldb/source/Symbol/TypeList.cpp | 109 --------------- lldb/source/Symbol/TypeMap.cpp | 73 ---------- .../python_api/sbmodule/FindTypes/Makefile | 3 + .../FindTypes/TestSBModuleFindTypes.py | 40 ++++++ .../python_api/sbmodule/FindTypes/main.cpp | 17 +++ lldb/unittests/Symbol/TestType.cpp | 62 ++++----- 10 files changed, 180 insertions(+), 302 deletions(-) create mode 100644 lldb/test/API/python_api/sbmodule/FindTypes/Makefile create mode 100644 lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py create mode 100644 lldb/test/API/python_api/sbmodule/FindTypes/main.cpp diff --git a/lldb/include/lldb/Symbol/Type.h b/lldb/include/lldb/Symbol/Type.h index 1c4f7b5601b0..7aa0852676e4 100644 --- a/lldb/include/lldb/Symbol/Type.h +++ b/lldb/include/lldb/Symbol/Type.h @@ -21,6 +21,8 @@ #include "llvm/ADT/APSInt.h" #include "llvm/ADT/DenseSet.h" +#include "llvm/ADT/STLForwardCompat.h" +#include "llvm/Support/raw_ostream.h" #include #include @@ -492,12 +494,37 @@ public: static int Compare(const Type &a, const Type &b); + // Represents a parsed type name coming out of GetTypeScopeAndBasename. The + // structure holds StringRefs pointing to portions of the original name, and + // so must not be used after the name is destroyed. + struct ParsedName { + lldb::TypeClass type_class = lldb::eTypeClassAny; + + // Scopes of the type, starting with the outermost. Absolute type references + // have a "::" as the first scope. + llvm::SmallVector scope; + + llvm::StringRef basename; + + friend bool operator==(const ParsedName &lhs, const ParsedName &rhs) { + return lhs.type_class == rhs.type_class && lhs.scope == rhs.scope && + lhs.basename == rhs.basename; + } + + friend llvm::raw_ostream &operator<<(llvm::raw_ostream &os, + const ParsedName &name) { + return os << llvm::formatv( + "Type::ParsedName({0:x}, [{1}], {2})", + llvm::to_underlying(name.type_class), + llvm::make_range(name.scope.begin(), name.scope.end()), + name.basename); + } + }; // From a fully qualified typename, split the type into the type basename and // the remaining type scope (namespaces/classes). - static bool GetTypeScopeAndBasename(llvm::StringRef name, - llvm::StringRef &scope, - llvm::StringRef &basename, - lldb::TypeClass &type_class); + static std::optional + GetTypeScopeAndBasename(llvm::StringRef name); + void SetEncodingType(Type *encoding_type) { m_encoding_type = encoding_type; } uint32_t GetEncodingMask(); diff --git a/lldb/include/lldb/Symbol/TypeList.h b/lldb/include/lldb/Symbol/TypeList.h index 403469c989f5..d58772ad5b62 100644 --- a/lldb/include/lldb/Symbol/TypeList.h +++ b/lldb/include/lldb/Symbol/TypeList.h @@ -49,15 +49,6 @@ public: void ForEach(std::function const &callback); - void RemoveMismatchedTypes(llvm::StringRef qualified_typename, - bool exact_match); - - void RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - lldb::TypeClass type_class, bool exact_match); - - void RemoveMismatchedTypes(lldb::TypeClass type_class); - private: typedef collection::iterator iterator; typedef collection::const_iterator const_iterator; diff --git a/lldb/include/lldb/Symbol/TypeMap.h b/lldb/include/lldb/Symbol/TypeMap.h index 433711875e55..89011efab5c3 100644 --- a/lldb/include/lldb/Symbol/TypeMap.h +++ b/lldb/include/lldb/Symbol/TypeMap.h @@ -55,10 +55,6 @@ public: bool Remove(const lldb::TypeSP &type_sp); - void RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - lldb::TypeClass type_class, bool exact_match); - private: typedef collection::iterator iterator; typedef collection::const_iterator const_iterator; diff --git a/lldb/source/Symbol/Type.cpp b/lldb/source/Symbol/Type.cpp index b85c38097ebe..6bf69c2ded28 100644 --- a/lldb/source/Symbol/Type.cpp +++ b/lldb/source/Symbol/Type.cpp @@ -29,6 +29,7 @@ #include "lldb/Target/ExecutionContext.h" #include "lldb/Target/Process.h" #include "lldb/Target/Target.h" +#include "lldb/lldb-enumerations.h" #include "llvm/ADT/StringRef.h" @@ -85,27 +86,23 @@ static CompilerContextKind ConvertTypeClass(lldb::TypeClass type_class) { TypeQuery::TypeQuery(llvm::StringRef name, TypeQueryOptions options) : m_options(options) { - llvm::StringRef scope, basename; - lldb::TypeClass type_class = lldb::eTypeClassAny; - if (Type::GetTypeScopeAndBasename(name, scope, basename, type_class)) { - if (scope.consume_front("::")) - m_options |= e_exact_match; + if (std::optional parsed_name = + Type::GetTypeScopeAndBasename(name)) { + llvm::ArrayRef scope = parsed_name->scope; if (!scope.empty()) { - std::pair scope_pair = - scope.split("::"); - while (!scope_pair.second.empty()) { - m_context.push_back({CompilerContextKind::AnyDeclContext, - ConstString(scope_pair.first.str())}); - scope_pair = scope_pair.second.split("::"); + if (scope[0] == "::") { + m_options |= e_exact_match; + scope = scope.drop_front(); + } + for (llvm::StringRef s : scope) { + m_context.push_back( + {CompilerContextKind::AnyDeclContext, ConstString(s)}); } - m_context.push_back({CompilerContextKind::AnyDeclContext, - ConstString(scope_pair.first.str())}); } - m_context.push_back( - {ConvertTypeClass(type_class), ConstString(basename.str())}); + m_context.push_back({ConvertTypeClass(parsed_name->type_class), + ConstString(parsed_name->basename)}); } else { - m_context.push_back( - {CompilerContextKind::AnyType, ConstString(name.str())}); + m_context.push_back({CompilerContextKind::AnyType, ConstString(name)}); } } @@ -773,65 +770,56 @@ ConstString Type::GetQualifiedName() { return GetForwardCompilerType().GetTypeName(); } -bool Type::GetTypeScopeAndBasename(llvm::StringRef name, - llvm::StringRef &scope, - llvm::StringRef &basename, - TypeClass &type_class) { - type_class = eTypeClassAny; +std::optional +Type::GetTypeScopeAndBasename(llvm::StringRef name) { + ParsedName result; if (name.empty()) - return false; - - // Clear the scope in case we have just a type class and a basename. - scope = llvm::StringRef(); - basename = name; - if (basename.consume_front("struct ")) - type_class = eTypeClassStruct; - else if (basename.consume_front("class ")) - type_class = eTypeClassClass; - else if (basename.consume_front("union ")) - type_class = eTypeClassUnion; - else if (basename.consume_front("enum ")) - type_class = eTypeClassEnumeration; - else if (basename.consume_front("typedef ")) - type_class = eTypeClassTypedef; - - size_t namespace_separator = basename.find("::"); - if (namespace_separator == llvm::StringRef::npos) { - // If "name" started a type class we need to return true with no scope. - return type_class != eTypeClassAny; - } - - size_t template_begin = basename.find('<'); - while (namespace_separator != llvm::StringRef::npos) { - if (template_begin != llvm::StringRef::npos && - namespace_separator > template_begin) { - size_t template_depth = 1; - llvm::StringRef template_arg = - basename.drop_front(template_begin + 1); - while (template_depth > 0 && !template_arg.empty()) { - if (template_arg.front() == '<') - template_depth++; - else if (template_arg.front() == '>') - template_depth--; - template_arg = template_arg.drop_front(1); + return std::nullopt; + + if (name.consume_front("struct ")) + result.type_class = eTypeClassStruct; + else if (name.consume_front("class ")) + result.type_class = eTypeClassClass; + else if (name.consume_front("union ")) + result.type_class = eTypeClassUnion; + else if (name.consume_front("enum ")) + result.type_class = eTypeClassEnumeration; + else if (name.consume_front("typedef ")) + result.type_class = eTypeClassTypedef; + + if (name.consume_front("::")) + result.scope.push_back("::"); + + bool prev_is_colon = false; + size_t template_depth = 0; + size_t name_begin = 0; + for (const auto &pos : llvm::enumerate(name)) { + switch (pos.value()) { + case ':': + if (prev_is_colon && template_depth == 0) { + result.scope.push_back(name.slice(name_begin, pos.index() - 1)); + name_begin = pos.index() + 1; } - if (template_depth != 0) - return false; // We have an invalid type name. Bail out. - if (template_arg.empty()) - break; // The template ends at the end of the full name. - basename = template_arg; - } else { - basename = basename.drop_front(namespace_separator + 2); + break; + case '<': + ++template_depth; + break; + case '>': + if (template_depth == 0) + return std::nullopt; // Invalid name. + --template_depth; + break; } - template_begin = basename.find('<'); - namespace_separator = basename.find("::"); - } - if (basename.size() < name.size()) { - scope = name.take_front(name.size() - basename.size()); - return true; + prev_is_colon = pos.value() == ':'; } - return false; + + if (name_begin < name.size() && template_depth == 0) + result.basename = name.substr(name_begin); + else + return std::nullopt; + + return result; } ModuleSP Type::GetModule() { diff --git a/lldb/source/Symbol/TypeList.cpp b/lldb/source/Symbol/TypeList.cpp index 2e101e0a8f57..574887189315 100644 --- a/lldb/source/Symbol/TypeList.cpp +++ b/lldb/source/Symbol/TypeList.cpp @@ -96,112 +96,3 @@ void TypeList::Dump(Stream *s, bool show_context) { if (Type *t = pos->get()) t->Dump(s, show_context); } - -void TypeList::RemoveMismatchedTypes(llvm::StringRef qualified_typename, - bool exact_match) { - llvm::StringRef type_scope; - llvm::StringRef type_basename; - TypeClass type_class = eTypeClassAny; - if (!Type::GetTypeScopeAndBasename(qualified_typename, type_scope, - type_basename, type_class)) { - type_basename = qualified_typename; - type_scope = ""; - } - return RemoveMismatchedTypes(type_scope, type_basename, type_class, - exact_match); -} - -void TypeList::RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - TypeClass type_class, bool exact_match) { - // Our "collection" type currently is a std::map which doesn't have any good - // way to iterate and remove items from the map so we currently just make a - // new list and add all of the matching types to it, and then swap it into - // m_types at the end - collection matching_types; - - iterator pos, end = m_types.end(); - - for (pos = m_types.begin(); pos != end; ++pos) { - Type *the_type = pos->get(); - bool keep_match = false; - TypeClass match_type_class = eTypeClassAny; - - if (type_class != eTypeClassAny) { - match_type_class = the_type->GetForwardCompilerType().GetTypeClass(); - if ((match_type_class & type_class) == 0) - continue; - } - - ConstString match_type_name_const_str(the_type->GetQualifiedName()); - if (match_type_name_const_str) { - const char *match_type_name = match_type_name_const_str.GetCString(); - llvm::StringRef match_type_scope; - llvm::StringRef match_type_basename; - if (Type::GetTypeScopeAndBasename(match_type_name, match_type_scope, - match_type_basename, - match_type_class)) { - if (match_type_basename == type_basename) { - const size_t type_scope_size = type_scope.size(); - const size_t match_type_scope_size = match_type_scope.size(); - if (exact_match || (type_scope_size == match_type_scope_size)) { - keep_match = match_type_scope == type_scope; - } else { - if (match_type_scope_size > type_scope_size) { - const size_t type_scope_pos = match_type_scope.rfind(type_scope); - if (type_scope_pos == match_type_scope_size - type_scope_size) { - if (type_scope_pos >= 2) { - // Our match scope ends with the type scope we were looking - // for, but we need to make sure what comes before the - // matching type scope is a namespace boundary in case we are - // trying to match: type_basename = "d" type_scope = "b::c::" - // We want to match: - // match_type_scope "a::b::c::" - // But not: - // match_type_scope "a::bb::c::" - // So below we make sure what comes before "b::c::" in - // match_type_scope is "::", or the namespace boundary - if (match_type_scope[type_scope_pos - 1] == ':' && - match_type_scope[type_scope_pos - 2] == ':') { - keep_match = true; - } - } - } - } - } - } - } else { - // The type we are currently looking at doesn't exists in a namespace - // or class, so it only matches if there is no type scope... - keep_match = type_scope.empty() && type_basename == match_type_name; - } - } - - if (keep_match) { - matching_types.push_back(*pos); - } - } - m_types.swap(matching_types); -} - -void TypeList::RemoveMismatchedTypes(TypeClass type_class) { - if (type_class == eTypeClassAny) - return; - - // Our "collection" type currently is a std::map which doesn't have any good - // way to iterate and remove items from the map so we currently just make a - // new list and add all of the matching types to it, and then swap it into - // m_types at the end - collection matching_types; - - iterator pos, end = m_types.end(); - - for (pos = m_types.begin(); pos != end; ++pos) { - Type *the_type = pos->get(); - TypeClass match_type_class = - the_type->GetForwardCompilerType().GetTypeClass(); - if (match_type_class & type_class) - matching_types.push_back(*pos); - } - m_types.swap(matching_types); -} diff --git a/lldb/source/Symbol/TypeMap.cpp b/lldb/source/Symbol/TypeMap.cpp index 8933de53749c..9d7c05f318a1 100644 --- a/lldb/source/Symbol/TypeMap.cpp +++ b/lldb/source/Symbol/TypeMap.cpp @@ -132,76 +132,3 @@ void TypeMap::Dump(Stream *s, bool show_context, for (const auto &pair : m_types) pair.second->Dump(s, show_context, level); } - -void TypeMap::RemoveMismatchedTypes(llvm::StringRef type_scope, - llvm::StringRef type_basename, - TypeClass type_class, bool exact_match) { - // Our "collection" type currently is a std::map which doesn't have any good - // way to iterate and remove items from the map so we currently just make a - // new list and add all of the matching types to it, and then swap it into - // m_types at the end - collection matching_types; - - iterator pos, end = m_types.end(); - - for (pos = m_types.begin(); pos != end; ++pos) { - Type *the_type = pos->second.get(); - bool keep_match = false; - TypeClass match_type_class = eTypeClassAny; - - if (type_class != eTypeClassAny) { - match_type_class = the_type->GetForwardCompilerType().GetTypeClass(); - if ((match_type_class & type_class) == 0) - continue; - } - - ConstString match_type_name_const_str(the_type->GetQualifiedName()); - if (match_type_name_const_str) { - const char *match_type_name = match_type_name_const_str.GetCString(); - llvm::StringRef match_type_scope; - llvm::StringRef match_type_basename; - if (Type::GetTypeScopeAndBasename(match_type_name, match_type_scope, - match_type_basename, - match_type_class)) { - if (match_type_basename == type_basename) { - const size_t type_scope_size = type_scope.size(); - const size_t match_type_scope_size = match_type_scope.size(); - if (exact_match || (type_scope_size == match_type_scope_size)) { - keep_match = match_type_scope == type_scope; - } else { - if (match_type_scope_size > type_scope_size) { - const size_t type_scope_pos = match_type_scope.rfind(type_scope); - if (type_scope_pos == match_type_scope_size - type_scope_size) { - if (type_scope_pos >= 2) { - // Our match scope ends with the type scope we were looking - // for, but we need to make sure what comes before the - // matching type scope is a namespace boundary in case we are - // trying to match: type_basename = "d" type_scope = "b::c::" - // We want to match: - // match_type_scope "a::b::c::" - // But not: - // match_type_scope "a::bb::c::" - // So below we make sure what comes before "b::c::" in - // match_type_scope is "::", or the namespace boundary - if (match_type_scope[type_scope_pos - 1] == ':' && - match_type_scope[type_scope_pos - 2] == ':') { - keep_match = true; - } - } - } - } - } - } - } else { - // The type we are currently looking at doesn't exists in a namespace - // or class, so it only matches if there is no type scope... - keep_match = type_scope.empty() && type_basename == match_type_name; - } - } - - if (keep_match) { - matching_types.insert(*pos); - } - } - m_types.swap(matching_types); -} diff --git a/lldb/test/API/python_api/sbmodule/FindTypes/Makefile b/lldb/test/API/python_api/sbmodule/FindTypes/Makefile new file mode 100644 index 000000000000..99998b20bcb0 --- /dev/null +++ b/lldb/test/API/python_api/sbmodule/FindTypes/Makefile @@ -0,0 +1,3 @@ +CXX_SOURCES := main.cpp + +include Makefile.rules diff --git a/lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py b/lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py new file mode 100644 index 000000000000..5c3d2b4187dd --- /dev/null +++ b/lldb/test/API/python_api/sbmodule/FindTypes/TestSBModuleFindTypes.py @@ -0,0 +1,40 @@ +"""Test the SBModule::FindTypes.""" + +import lldb +from lldbsuite.test.decorators import * +from lldbsuite.test.lldbtest import * +from lldbsuite.test import lldbutil + + +class TestSBModuleFindTypes(TestBase): + def test_lookup_in_template_scopes(self): + self.build() + spec = lldb.SBModuleSpec() + spec.SetFileSpec(lldb.SBFileSpec(self.getBuildArtifact())) + module = lldb.SBModule(spec) + + self.assertEqual( + set([t.GetName() for t in module.FindTypes("LookMeUp")]), + set( + [ + "ns1::Foo::LookMeUp", + "ns2::Bar::LookMeUp", + "ns1::Foo >::LookMeUp", + ] + ), + ) + + self.assertEqual( + set([t.GetName() for t in module.FindTypes("ns1::Foo::LookMeUp")]), + set(["ns1::Foo::LookMeUp"]), + ) + + self.assertEqual( + set( + [ + t.GetName() + for t in module.FindTypes("ns1::Foo >::LookMeUp") + ] + ), + set(["ns1::Foo >::LookMeUp"]), + ) diff --git a/lldb/test/API/python_api/sbmodule/FindTypes/main.cpp b/lldb/test/API/python_api/sbmodule/FindTypes/main.cpp new file mode 100644 index 000000000000..cb2646ce312a --- /dev/null +++ b/lldb/test/API/python_api/sbmodule/FindTypes/main.cpp @@ -0,0 +1,17 @@ +namespace ns1 { +template struct Foo { + struct LookMeUp {}; +}; +} // namespace ns1 + +namespace ns2 { +template struct Bar { + struct LookMeUp {}; +}; +} // namespace ns2 + +ns1::Foo::LookMeUp l1; +ns2::Bar::LookMeUp l2; +ns1::Foo>::LookMeUp l3; + +int main() {} diff --git a/lldb/unittests/Symbol/TestType.cpp b/lldb/unittests/Symbol/TestType.cpp index 73f5811434fd..da849d804e4d 100644 --- a/lldb/unittests/Symbol/TestType.cpp +++ b/lldb/unittests/Symbol/TestType.cpp @@ -10,43 +10,41 @@ #include "gtest/gtest.h" #include "lldb/Symbol/Type.h" +#include "lldb/lldb-enumerations.h" using namespace lldb; using namespace lldb_private; -namespace { -void TestGetTypeScopeAndBasenameHelper(const char *full_type, - bool expected_is_scoped, - const char *expected_scope, - const char *expected_name) { - llvm::StringRef scope, name; - lldb::TypeClass type_class; - bool is_scoped = - Type::GetTypeScopeAndBasename(full_type, scope, name, type_class); - EXPECT_EQ(is_scoped, expected_is_scoped); - if (expected_is_scoped) { - EXPECT_EQ(scope, expected_scope); - EXPECT_EQ(name, expected_name); - } -} -} - TEST(Type, GetTypeScopeAndBasename) { - TestGetTypeScopeAndBasenameHelper("int", false, "", ""); - TestGetTypeScopeAndBasenameHelper("std::string", true, "std::", "string"); - TestGetTypeScopeAndBasenameHelper("std::set", true, "std::", "set"); - TestGetTypeScopeAndBasenameHelper("std::set>", true, - "std::", "set>"); - TestGetTypeScopeAndBasenameHelper("std::string::iterator", true, - "std::string::", "iterator"); - TestGetTypeScopeAndBasenameHelper("std::set::iterator", true, - "std::set::", "iterator"); - TestGetTypeScopeAndBasenameHelper( - "std::set>::iterator", true, - "std::set>::", "iterator"); - TestGetTypeScopeAndBasenameHelper( - "std::set>::iterator", true, - "std::set>::", "iterator"); + EXPECT_EQ(Type::GetTypeScopeAndBasename("int"), + (Type::ParsedName{eTypeClassAny, {}, "int"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::string"), + (Type::ParsedName{eTypeClassAny, {"std"}, "string"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("::std::string"), + (Type::ParsedName{eTypeClassAny, {"::", "std"}, "string"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("struct std::string"), + (Type::ParsedName{eTypeClassStruct, {"std"}, "string"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::set"), + (Type::ParsedName{eTypeClassAny, {"std"}, "set"})); + EXPECT_EQ( + Type::GetTypeScopeAndBasename("std::set>"), + (Type::ParsedName{eTypeClassAny, {"std"}, "set>"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::string::iterator"), + (Type::ParsedName{eTypeClassAny, {"std", "string"}, "iterator"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::set::iterator"), + (Type::ParsedName{eTypeClassAny, {"std", "set"}, "iterator"})); + EXPECT_EQ( + Type::GetTypeScopeAndBasename("std::set>::iterator"), + (Type::ParsedName{ + eTypeClassAny, {"std", "set>"}, "iterator"})); + EXPECT_EQ(Type::GetTypeScopeAndBasename( + "std::set>::iterator"), + (Type::ParsedName{eTypeClassAny, + {"std", "set>"}, + "iterator"})); + + EXPECT_EQ(Type::GetTypeScopeAndBasename("std::"), std::nullopt); + EXPECT_EQ(Type::GetTypeScopeAndBasename("foo<::bar"), std::nullopt); } TEST(Type, CompilerContextPattern) { -- GitLab From 2dbe89d15046bedcc36a5de1242e20aa91a5e598 Mon Sep 17 00:00:00 2001 From: cor3ntin Date: Fri, 10 May 2024 08:50:44 +0200 Subject: [PATCH 006/824] [Clang] Implement __reference_converts_from_temporary (#91199) This completes the required language support for P2255R2. --- clang/docs/LanguageExtensions.rst | 5 +- clang/docs/ReleaseNotes.rst | 3 + clang/include/clang/Basic/TokenKinds.def | 1 + clang/lib/Lex/PPMacroExpansion.cpp | 2 - clang/lib/Parse/ParseDeclCXX.cpp | 5 +- clang/lib/Parse/ParseExpr.cpp | 1 - clang/lib/Sema/SemaExprCXX.cpp | 157 +++++++++++++---------- clang/test/SemaCXX/type-traits.cpp | 80 ++++++++++++ clang/www/cxx_status.html | 10 +- 9 files changed, 182 insertions(+), 82 deletions(-) diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 3627a780886a..a09c409f8f91 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -1662,8 +1662,11 @@ The following type trait primitives are supported by Clang. Those traits marked ``T`` from ``U`` is ill-formed. Deprecated, use ``__reference_constructs_from_temporary``. * ``__reference_constructs_from_temporary(T, U)`` (C++) - Returns true if a reference ``T`` can be constructed from a temporary of type + Returns true if a reference ``T`` can be direct-initialized from a temporary of type a non-cv-qualified ``U``. +* ``__reference_converts_from_temporary(T, U)`` (C++) + Returns true if a reference ``T`` can be copy-initialized from a temporary of type + a non-cv-qualified ``U``. * ``__underlying_type`` (C++, GNU, Microsoft) In addition, the following expression traits are supported: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 4547636318a7..eef627ff2e31 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -182,6 +182,9 @@ C++23 Feature Support - Implemented `P2448R2: Relaxing some constexpr restrictions `_. +- Added a ``__reference_converts_from_temporary`` builtin, completing the necessary compiler support for + `P2255R2: Type trait to determine if a reference binds to a temporary `_. + C++2c Feature Support ^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/TokenKinds.def b/clang/include/clang/Basic/TokenKinds.def index a27fbed358a6..56c4b17f769d 100644 --- a/clang/include/clang/Basic/TokenKinds.def +++ b/clang/include/clang/Basic/TokenKinds.def @@ -537,6 +537,7 @@ TYPE_TRAIT_1(__is_referenceable, IsReferenceable, KEYCXX) TYPE_TRAIT_1(__can_pass_in_regs, CanPassInRegs, KEYCXX) TYPE_TRAIT_2(__reference_binds_to_temporary, ReferenceBindsToTemporary, KEYCXX) TYPE_TRAIT_2(__reference_constructs_from_temporary, ReferenceConstructsFromTemporary, KEYCXX) +TYPE_TRAIT_2(__reference_converts_from_temporary, ReferenceConvertsFromTemporary, KEYCXX) // Embarcadero Expression Traits EXPRESSION_TRAIT(__is_lvalue_expr, IsLValueExpr, KEYCXX) diff --git a/clang/lib/Lex/PPMacroExpansion.cpp b/clang/lib/Lex/PPMacroExpansion.cpp index a5f22f01682d..a478e0badb0c 100644 --- a/clang/lib/Lex/PPMacroExpansion.cpp +++ b/clang/lib/Lex/PPMacroExpansion.cpp @@ -1714,8 +1714,6 @@ void Preprocessor::ExpandBuiltinMacro(Token &Tok) { return llvm::StringSwitch(II->getName()) .Case("__array_rank", true) .Case("__array_extent", true) - .Case("__reference_binds_to_temporary", true) - .Case("__reference_constructs_from_temporary", true) #define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) .Case("__" #Trait, true) #include "clang/Basic/TransformTypeTraits.def" .Default(false); diff --git a/clang/lib/Parse/ParseDeclCXX.cpp b/clang/lib/Parse/ParseDeclCXX.cpp index 8e0e86824829..96c9708c3711 100644 --- a/clang/lib/Parse/ParseDeclCXX.cpp +++ b/clang/lib/Parse/ParseDeclCXX.cpp @@ -1779,9 +1779,8 @@ void Parser::ParseClassSpecifier(tok::TokenKind TagTokKind, tok::kw___is_union, tok::kw___is_unsigned, tok::kw___is_void, - tok::kw___is_volatile, - tok::kw___reference_binds_to_temporary, - tok::kw___reference_constructs_from_temporary)) + tok::kw___is_volatile + )) // GNU libstdc++ 4.2 and libc++ use certain intrinsic names as the // name of struct templates, but some are keywords in GCC >= 4.3 // and Clang. Therefore, when we see the token sequence "struct diff --git a/clang/lib/Parse/ParseExpr.cpp b/clang/lib/Parse/ParseExpr.cpp index 5f5f9a79c8c4..0551b8314f9f 100644 --- a/clang/lib/Parse/ParseExpr.cpp +++ b/clang/lib/Parse/ParseExpr.cpp @@ -1166,7 +1166,6 @@ ExprResult Parser::ParseCastExpression(CastParseKind ParseKind, REVERTIBLE_TYPE_TRAIT(__is_void); REVERTIBLE_TYPE_TRAIT(__is_volatile); REVERTIBLE_TYPE_TRAIT(__reference_binds_to_temporary); - REVERTIBLE_TYPE_TRAIT(__reference_constructs_from_temporary); #define TRANSFORM_TYPE_TRAIT_DEF(_, Trait) \ REVERTIBLE_TYPE_TRAIT(RTT_JOIN(__, Trait)); #include "clang/Basic/TransformTypeTraits.def" diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index c1cb03e4ec7a..ae844bc69914 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -5627,6 +5627,77 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT, static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceInfo *Lhs, const TypeSourceInfo *Rhs, SourceLocation KeyLoc); +static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, + const TypeSourceInfo *Lhs, + const TypeSourceInfo *Rhs, + SourceLocation KeyLoc) { + + QualType LhsT = Lhs->getType(); + QualType RhsT = Rhs->getType(); + + // C++0x [meta.rel]p4: + // Given the following function prototype: + // + // template + // typename add_rvalue_reference::type create(); + // + // the predicate condition for a template specialization + // is_convertible shall be satisfied if and only if + // the return expression in the following code would be + // well-formed, including any implicit conversions to the return + // type of the function: + // + // To test() { + // return create(); + // } + // + // Access checking is performed as if in a context unrelated to To and + // From. Only the validity of the immediate context of the expression + // of the return-statement (including conversions to the return type) + // is considered. + // + // We model the initialization as a copy-initialization of a temporary + // of the appropriate type, which for this expression is identical to the + // return statement (since NRVO doesn't apply). + + // Functions aren't allowed to return function or array types. + if (RhsT->isFunctionType() || RhsT->isArrayType()) + return ExprError(); + + // A function definition requires a complete, non-abstract return type. + if (!Self.isCompleteType(Rhs->getTypeLoc().getBeginLoc(), RhsT) || + Self.isAbstractType(Rhs->getTypeLoc().getBeginLoc(), RhsT)) + return ExprError(); + + // Compute the result of add_rvalue_reference. + if (LhsT->isObjectType() || LhsT->isFunctionType()) + LhsT = Self.Context.getRValueReferenceType(LhsT); + + // Build a fake source and destination for initialization. + InitializedEntity To(InitializedEntity::InitializeTemporary(RhsT)); + OpaqueValueExpr From(KeyLoc, LhsT.getNonLValueExprType(Self.Context), + Expr::getValueKindForType(LhsT)); + Expr *FromPtr = &From; + InitializationKind Kind = + InitializationKind::CreateCopy(KeyLoc, SourceLocation()); + + // Perform the initialization in an unevaluated context within a SFINAE + // trap at translation unit scope. + EnterExpressionEvaluationContext Unevaluated( + Self, Sema::ExpressionEvaluationContext::Unevaluated); + Sema::SFINAETrap SFINAE(Self, /*AccessCheckingSFINAE=*/true); + Sema::ContextRAII TUContext(Self, Self.Context.getTranslationUnitDecl()); + InitializationSequence Init(Self, To, Kind, FromPtr); + if (Init.Failed()) + return ExprError(); + + ExprResult Result = Init.Perform(Self, To, Kind, FromPtr); + if (Result.isInvalid() || SFINAE.hasErrorOccurred()) + return ExprError(); + + return Result; +} + static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, SourceLocation KWLoc, ArrayRef Args, @@ -5640,13 +5711,16 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, // Evaluate ReferenceBindsToTemporary and ReferenceConstructsFromTemporary // alongside the IsConstructible traits to avoid duplication. - if (Kind <= BTT_Last && Kind != BTT_ReferenceBindsToTemporary && Kind != BTT_ReferenceConstructsFromTemporary) + if (Kind <= BTT_Last && Kind != BTT_ReferenceBindsToTemporary && + Kind != BTT_ReferenceConstructsFromTemporary && + Kind != BTT_ReferenceConvertsFromTemporary) return EvaluateBinaryTypeTrait(S, Kind, Args[0], Args[1], RParenLoc); switch (Kind) { case clang::BTT_ReferenceBindsToTemporary: case clang::BTT_ReferenceConstructsFromTemporary: + case clang::BTT_ReferenceConvertsFromTemporary: case clang::TT_IsConstructible: case clang::TT_IsNothrowConstructible: case clang::TT_IsTriviallyConstructible: { @@ -5710,8 +5784,10 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, Sema::ContextRAII TUContext(S, S.Context.getTranslationUnitDecl()); InitializedEntity To( InitializedEntity::InitializeTemporary(S.Context, Args[0])); - InitializationKind InitKind(InitializationKind::CreateDirect(KWLoc, KWLoc, - RParenLoc)); + InitializationKind InitKind( + Kind == clang::BTT_ReferenceConvertsFromTemporary + ? InitializationKind::CreateCopy(KWLoc, KWLoc) + : InitializationKind::CreateDirect(KWLoc, KWLoc, RParenLoc)); InitializationSequence Init(S, To, InitKind, ArgExprs); if (Init.Failed()) return false; @@ -5723,7 +5799,9 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, if (Kind == clang::TT_IsConstructible) return true; - if (Kind == clang::BTT_ReferenceBindsToTemporary || Kind == clang::BTT_ReferenceConstructsFromTemporary) { + if (Kind == clang::BTT_ReferenceBindsToTemporary || + Kind == clang::BTT_ReferenceConstructsFromTemporary || + Kind == clang::BTT_ReferenceConvertsFromTemporary) { if (!T->isReferenceType()) return false; @@ -5737,9 +5815,12 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, if (U->isReferenceType()) return false; - TypeSourceInfo *TPtr = S.Context.CreateTypeSourceInfo(S.Context.getPointerType(S.BuiltinRemoveReference(T, UnaryTransformType::RemoveCVRef, {}))); - TypeSourceInfo *UPtr = S.Context.CreateTypeSourceInfo(S.Context.getPointerType(S.BuiltinRemoveReference(U, UnaryTransformType::RemoveCVRef, {}))); - return EvaluateBinaryTypeTrait(S, TypeTrait::BTT_IsConvertibleTo, UPtr, TPtr, RParenLoc); + TypeSourceInfo *TPtr = S.Context.CreateTypeSourceInfo( + S.Context.getPointerType(T.getNonReferenceType())); + TypeSourceInfo *UPtr = S.Context.CreateTypeSourceInfo( + S.Context.getPointerType(U.getNonReferenceType())); + return !CheckConvertibilityForTypeTraits(S, UPtr, TPtr, RParenLoc) + .isInvalid(); } if (Kind == clang::TT_IsNothrowConstructible) @@ -5945,68 +6026,12 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI case BTT_IsConvertible: case BTT_IsConvertibleTo: case BTT_IsNothrowConvertible: { - // C++0x [meta.rel]p4: - // Given the following function prototype: - // - // template - // typename add_rvalue_reference::type create(); - // - // the predicate condition for a template specialization - // is_convertible shall be satisfied if and only if - // the return expression in the following code would be - // well-formed, including any implicit conversions to the return - // type of the function: - // - // To test() { - // return create(); - // } - // - // Access checking is performed as if in a context unrelated to To and - // From. Only the validity of the immediate context of the expression - // of the return-statement (including conversions to the return type) - // is considered. - // - // We model the initialization as a copy-initialization of a temporary - // of the appropriate type, which for this expression is identical to the - // return statement (since NRVO doesn't apply). - - // Functions aren't allowed to return function or array types. - if (RhsT->isFunctionType() || RhsT->isArrayType()) - return false; - - // A return statement in a void function must have void type. if (RhsT->isVoidType()) return LhsT->isVoidType(); - // A function definition requires a complete, non-abstract return type. - if (!Self.isCompleteType(Rhs->getTypeLoc().getBeginLoc(), RhsT) || - Self.isAbstractType(Rhs->getTypeLoc().getBeginLoc(), RhsT)) - return false; - - // Compute the result of add_rvalue_reference. - if (LhsT->isObjectType() || LhsT->isFunctionType()) - LhsT = Self.Context.getRValueReferenceType(LhsT); - - // Build a fake source and destination for initialization. - InitializedEntity To(InitializedEntity::InitializeTemporary(RhsT)); - OpaqueValueExpr From(KeyLoc, LhsT.getNonLValueExprType(Self.Context), - Expr::getValueKindForType(LhsT)); - Expr *FromPtr = &From; - InitializationKind Kind(InitializationKind::CreateCopy(KeyLoc, - SourceLocation())); - - // Perform the initialization in an unevaluated context within a SFINAE - // trap at translation unit scope. - EnterExpressionEvaluationContext Unevaluated( - Self, Sema::ExpressionEvaluationContext::Unevaluated); - Sema::SFINAETrap SFINAE(Self, /*AccessCheckingSFINAE=*/true); - Sema::ContextRAII TUContext(Self, Self.Context.getTranslationUnitDecl()); - InitializationSequence Init(Self, To, Kind, FromPtr); - if (Init.Failed()) - return false; - - ExprResult Result = Init.Perform(Self, To, Kind, FromPtr); - if (Result.isInvalid() || SFINAE.hasErrorOccurred()) + ExprResult Result = + CheckConvertibilityForTypeTraits(Self, Lhs, Rhs, KeyLoc); + if (Result.isInvalid()) return false; if (BTT != BTT_IsNothrowConvertible) diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp index 01991887b284..f2fd45762abf 100644 --- a/clang/test/SemaCXX/type-traits.cpp +++ b/clang/test/SemaCXX/type-traits.cpp @@ -2908,6 +2908,12 @@ struct ConvertsToRef { operator RefType() const { return static_cast(obj); } mutable T obj = 42; }; +template +class ConvertsToRefPrivate { + operator RefType() const { return static_cast(obj); } + mutable T obj = 42; +}; + void reference_binds_to_temporary_checks() { static_assert(!(__reference_binds_to_temporary(int &, int &))); @@ -2937,6 +2943,8 @@ void reference_binds_to_temporary_checks() { static_assert((__is_constructible(int const &, LongRef))); static_assert((__reference_binds_to_temporary(int const &, LongRef))); + static_assert(!__reference_binds_to_temporary(int const &, ConvertsToRefPrivate)); + // Test that it doesn't accept non-reference types as input. static_assert(!(__reference_binds_to_temporary(int, long))); @@ -2944,6 +2952,17 @@ void reference_binds_to_temporary_checks() { static_assert((__reference_binds_to_temporary(const int &, long))); } + +struct ExplicitConversionRvalueRef { + operator int(); + explicit operator int&&(); +}; + +struct ExplicitConversionRef { + operator int(); + explicit operator int&(); +}; + void reference_constructs_from_temporary_checks() { static_assert(!__reference_constructs_from_temporary(int &, int &)); static_assert(!__reference_constructs_from_temporary(int &, int &&)); @@ -2973,6 +2992,8 @@ void reference_constructs_from_temporary_checks() { static_assert(__is_constructible(int const &, LongRef)); static_assert(__reference_constructs_from_temporary(int const &, LongRef)); + static_assert(!__reference_constructs_from_temporary(int const &, ConvertsToRefPrivate)); + // Test that it doesn't accept non-reference types as input. static_assert(!__reference_constructs_from_temporary(int, long)); @@ -2987,6 +3008,65 @@ void reference_constructs_from_temporary_checks() { static_assert(!__reference_constructs_from_temporary(const int&, int&&)); static_assert(__reference_constructs_from_temporary(int&&, long&&)); static_assert(__reference_constructs_from_temporary(int&&, long)); + + + static_assert(!__reference_constructs_from_temporary(int&, ExplicitConversionRef)); + static_assert(!__reference_constructs_from_temporary(const int&, ExplicitConversionRef)); + static_assert(!__reference_constructs_from_temporary(int&&, ExplicitConversionRvalueRef)); + + +} + +void reference_converts_from_temporary_checks() { + static_assert(!__reference_converts_from_temporary(int &, int &)); + static_assert(!__reference_converts_from_temporary(int &, int &&)); + + static_assert(!__reference_converts_from_temporary(int const &, int &)); + static_assert(!__reference_converts_from_temporary(int const &, int const &)); + static_assert(!__reference_converts_from_temporary(int const &, int &&)); + + static_assert(!__reference_converts_from_temporary(int &, long &)); // doesn't construct + + static_assert(__reference_converts_from_temporary(int const &, long &)); + static_assert(__reference_converts_from_temporary(int const &, long &&)); + static_assert(__reference_converts_from_temporary(int &&, long &)); + + using LRef = ConvertsToRef; + using RRef = ConvertsToRef; + using CLRef = ConvertsToRef; + using LongRef = ConvertsToRef; + static_assert(__is_constructible(int &, LRef)); + static_assert(!__reference_converts_from_temporary(int &, LRef)); + + static_assert(__is_constructible(int &&, RRef)); + static_assert(!__reference_converts_from_temporary(int &&, RRef)); + + static_assert(__is_constructible(int const &, CLRef)); + static_assert(!__reference_converts_from_temporary(int &&, CLRef)); + + static_assert(__is_constructible(int const &, LongRef)); + static_assert(__reference_converts_from_temporary(int const &, LongRef)); + static_assert(!__reference_converts_from_temporary(int const &, ConvertsToRefPrivate)); + + + // Test that it doesn't accept non-reference types as input. + static_assert(!__reference_converts_from_temporary(int, long)); + + static_assert(__reference_converts_from_temporary(const int &, long)); + + // Additional checks + static_assert(__reference_converts_from_temporary(POD const&, Derives)); + static_assert(__reference_converts_from_temporary(int&&, int)); + static_assert(__reference_converts_from_temporary(const int&, int)); + static_assert(!__reference_converts_from_temporary(int&&, int&&)); + static_assert(!__reference_converts_from_temporary(const int&, int&&)); + static_assert(__reference_converts_from_temporary(int&&, long&&)); + static_assert(__reference_converts_from_temporary(int&&, long)); + + static_assert(!__reference_converts_from_temporary(int&, ExplicitConversionRef)); + static_assert(__reference_converts_from_temporary(const int&, ExplicitConversionRef)); + static_assert(__reference_converts_from_temporary(int&&, ExplicitConversionRvalueRef)); + } void array_rank() { diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index 6e0599cc9fe0..1338f544ffcb 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -347,15 +347,7 @@ C++23, informally referred to as C++26.

Type trait to determine if a reference binds to a temporary P2255R2 - -
Partial - Clang provides __reference_constructs_from_temporary type - trait builtin, with which std::reference_constructs_from_temporary - is implemented. __reference_converts_from_temporary needs to be - provided, following the normal cross-vendor convention to implement - traits requiring compiler support directly. -
- + Clang 19 -- GitLab From 7e52ad3b5b9509d0873965e8492ab01141342822 Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Fri, 10 May 2024 15:49:53 +0900 Subject: [PATCH 007/824] Fix a warning for #91455 [-Wc++20-extensions] --- .../Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp b/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp index 0a2514a2d7c1..d194742dbea7 100644 --- a/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/WatchedLiteralsSolverTest.cpp @@ -20,7 +20,7 @@ SolverTest::createSolverWithLowTimeout() { namespace { INSTANTIATE_TYPED_TEST_SUITE_P(WatchedLiteralsSolverTest, SolverTest, - WatchedLiteralsSolver); + WatchedLiteralsSolver, ); } // namespace } // namespace clang::dataflow::test -- GitLab From 2a61eebc66c0903cf3834a520b1f975ac3cdf92b Mon Sep 17 00:00:00 2001 From: NAKAMURA Takumi Date: Thu, 9 May 2024 19:34:43 +0900 Subject: [PATCH 008/824] Cleanup asserts in BranchParameters and DecisionParameters --- clang/lib/CodeGen/CoverageMappingGen.cpp | 5 +---- llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h | 5 +---- llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h | 8 ++++++-- llvm/lib/ProfileData/Coverage/CoverageMapping.cpp | 2 -- llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp | 1 - 5 files changed, 8 insertions(+), 13 deletions(-) diff --git a/clang/lib/CodeGen/CoverageMappingGen.cpp b/clang/lib/CodeGen/CoverageMappingGen.cpp index 733686d4946b..ce2f39aeb082 100644 --- a/clang/lib/CodeGen/CoverageMappingGen.cpp +++ b/clang/lib/CodeGen/CoverageMappingGen.cpp @@ -191,10 +191,7 @@ public: bool isBranch() const { return FalseCount.has_value(); } bool isMCDCDecision() const { - const auto *DecisionParams = - std::get_if(&MCDCParams); - assert(!DecisionParams || DecisionParams->NumConditions > 0); - return DecisionParams; + return std::holds_alternative(MCDCParams); } const auto &getMCDCDecisionParams() const { diff --git a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h index 7a8b6639f297..da0310404524 100644 --- a/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h +++ b/llvm/include/llvm/ProfileData/Coverage/CoverageMapping.h @@ -462,10 +462,7 @@ public: CounterMappingRegion getDecisionRegion() const { return Region; } unsigned getNumConditions() const { - unsigned NumConditions = Region.getDecisionParams().NumConditions; - assert(NumConditions != 0 && - "In MC/DC, NumConditions should never be zero!"); - return NumConditions; + return Region.getDecisionParams().NumConditions; } unsigned getNumTestVectors() const { return TV.size(); } bool isCondFolded(unsigned Condition) const { return Folded[Condition]; } diff --git a/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h b/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h index 8c78bed4dec5..191e4ead95ea 100644 --- a/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h +++ b/llvm/include/llvm/ProfileData/Coverage/MCDCTypes.h @@ -33,7 +33,9 @@ struct DecisionParameters { DecisionParameters() = delete; DecisionParameters(unsigned BitmapIdx, unsigned NumConditions) - : BitmapIdx(BitmapIdx), NumConditions(NumConditions) {} + : BitmapIdx(BitmapIdx), NumConditions(NumConditions) { + assert(NumConditions > 0); + } }; struct BranchParameters { @@ -44,7 +46,9 @@ struct BranchParameters { BranchParameters() = delete; BranchParameters(ConditionID ID, const ConditionIDs &Conds) - : ID(ID), Conds(Conds) {} + : ID(ID), Conds(Conds) { + assert(ID >= 0); + } }; /// The type of MC/DC-specific parameters. diff --git a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp index 6c77ce017c03..8c81bbe8e9c4 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMapping.cpp @@ -338,7 +338,6 @@ public: #endif for (const auto *Branch : Branches) { const auto &BranchParams = Branch->getBranchParams(); - assert(BranchParams.ID >= 0 && "CondID isn't set"); assert(SeenIDs.insert(BranchParams.ID).second && "Duplicate CondID"); NextIDs[BranchParams.ID] = BranchParams.Conds; } @@ -694,7 +693,6 @@ private: assert(Branch.Kind == CounterMappingRegion::MCDCBranchRegion); auto ConditionID = Branch.getBranchParams().ID; - assert(ConditionID >= 0 && "ConditionID should be positive"); if (ConditionIDs.contains(ConditionID) || ConditionID >= DecisionParams.NumConditions) diff --git a/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp b/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp index 5036bde5aca7..adfd22804356 100644 --- a/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp +++ b/llvm/lib/ProfileData/Coverage/CoverageMappingWriter.cpp @@ -256,7 +256,6 @@ void CoverageMappingWriter::write(raw_ostream &OS) { // They are written as internal values plus 1. const auto &BranchParams = I->getBranchParams(); ParamsShouldBeNull = false; - assert(BranchParams.ID >= 0); unsigned ID1 = BranchParams.ID + 1; unsigned TID1 = BranchParams.Conds[true] + 1; unsigned FID1 = BranchParams.Conds[false] + 1; -- GitLab From 6ce4c4ca2bb846c2b8d64dc2b3d3496785c9edff Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Thu, 9 May 2024 23:56:56 -0700 Subject: [PATCH 009/824] [clang-format][NFC] Drop a redundant clang::format:: --- clang/lib/Format/UnwrappedLineParser.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/Format/UnwrappedLineParser.cpp b/clang/lib/Format/UnwrappedLineParser.cpp index 71557b127fb7..310b75485e08 100644 --- a/clang/lib/Format/UnwrappedLineParser.cpp +++ b/clang/lib/Format/UnwrappedLineParser.cpp @@ -3385,7 +3385,7 @@ void UnwrappedLineParser::parseAccessSpecifier() { /// \brief Parses a requires, decides if it is a clause or an expression. /// \pre The current token has to be the requires keyword. /// \returns true if it parsed a clause. -bool clang::format::UnwrappedLineParser::parseRequires() { +bool UnwrappedLineParser::parseRequires() { assert(FormatTok->is(tok::kw_requires) && "'requires' expected"); auto RequiresToken = FormatTok; -- GitLab From 6aac30fa43f094ac25269bda163dc89a88cb8da7 Mon Sep 17 00:00:00 2001 From: Jack Styles Date: Fri, 10 May 2024 08:09:02 +0100 Subject: [PATCH 010/824] Update FEAT_PAuth_LR behaviour for AArch64 (#90614) Currently, LLVM enables `-mbranch-protection=standard` as `bti+pac-ret`. To align LLVM with the behaviour in GNU, this has been updated to `bti+pac-ret+pc` when FEAT_PAuth_LR is enabled as an optional feature via the `-mcpu=` options. If this is not enabled, then this will revert to the existing behaviour. --- clang/lib/Basic/Targets/AArch64.cpp | 2 +- clang/lib/Driver/ToolChains/Clang.cpp | 20 ++++++++++++++++++- .../Preprocessor/aarch64-target-features.c | 4 ++++ llvm/docs/ReleaseNotes.rst | 5 +++++ .../llvm/TargetParser/AArch64TargetParser.h | 2 ++ .../llvm/TargetParser/ARMTargetParserCommon.h | 2 +- llvm/lib/TargetParser/AArch64TargetParser.cpp | 5 +++++ .../TargetParser/ARMTargetParserCommon.cpp | 3 ++- 8 files changed, 39 insertions(+), 4 deletions(-) diff --git a/clang/lib/Basic/Targets/AArch64.cpp b/clang/lib/Basic/Targets/AArch64.cpp index 4b1545339f69..5db1ce78c657 100644 --- a/clang/lib/Basic/Targets/AArch64.cpp +++ b/clang/lib/Basic/Targets/AArch64.cpp @@ -225,7 +225,7 @@ bool AArch64TargetInfo::validateBranchProtection(StringRef Spec, StringRef, BranchProtectionInfo &BPI, StringRef &Err) const { llvm::ARM::ParsedBranchProtection PBP; - if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err)) + if (!llvm::ARM::parseBranchProtection(Spec, PBP, Err, HasPAuthLR)) return false; BPI.SignReturnAddr = diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 449eb9b2a965..f81c2024ae48 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -55,6 +55,7 @@ #include "llvm/Support/Path.h" #include "llvm/Support/Process.h" #include "llvm/Support/YAMLParser.h" +#include "llvm/TargetParser/AArch64TargetParser.h" #include "llvm/TargetParser/ARMTargetParserCommon.h" #include "llvm/TargetParser/Host.h" #include "llvm/TargetParser/LoongArchTargetParser.h" @@ -1511,7 +1512,24 @@ static void CollectARMPACBTIOptions(const ToolChain &TC, const ArgList &Args, } else { StringRef DiagMsg; llvm::ARM::ParsedBranchProtection PBP; - if (!llvm::ARM::parseBranchProtection(A->getValue(), PBP, DiagMsg)) + bool EnablePAuthLR = false; + + // To know if we need to enable PAuth-LR As part of the standard branch + // protection option, it needs to be determined if the feature has been + // activated in the `march` argument. This information is stored within the + // CmdArgs variable and can be found using a search. + if (isAArch64) { + auto isPAuthLR = [](const char *member) { + llvm::AArch64::ExtensionInfo pauthlr_extension = + llvm::AArch64::getExtensionByID(llvm::AArch64::AEK_PAUTHLR); + return (pauthlr_extension.Feature.compare(member) == 0); + }; + + if (std::any_of(CmdArgs.begin(), CmdArgs.end(), isPAuthLR)) + EnablePAuthLR = true; + } + if (!llvm::ARM::parseBranchProtection(A->getValue(), PBP, DiagMsg, + EnablePAuthLR)) D.Diag(diag::err_drv_unsupported_option_argument) << A->getSpelling() << DiagMsg; if (!isAArch64 && PBP.Key == "b_key") diff --git a/clang/test/Preprocessor/aarch64-target-features.c b/clang/test/Preprocessor/aarch64-target-features.c index 4d10eeafa884..82304a15a04a 100644 --- a/clang/test/Preprocessor/aarch64-target-features.c +++ b/clang/test/Preprocessor/aarch64-target-features.c @@ -616,6 +616,9 @@ // ================== Check Armv9.5-A Pointer Authentication Enhancements(PAuth_LR). // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s // RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s +// RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR-OFF,CHECK-BRANCH-PROTECTION-NO-PC %s +// RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a+pauth-lr -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC %s +// RUN: %clang -target arm64-none-linux-gnu -march=armv9.5-a+nopauth-lr -mbranch-protection=standard -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR-OFF,CHECK-BRANCH-PROTECTION-NO-PC %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR-OFF %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=none -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=bti -x c -E -dM %s -o - | FileCheck -check-prefix=CHECK-PAUTH-LR %s @@ -636,6 +639,7 @@ // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=pac-ret+pc+b-key -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC-BKEY %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=pac-ret+pc+leaf -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC-LEAF %s // RUN: %clang -target arm64-none-linux-gnu -march=armv8-a+pauth-lr -mbranch-protection=pac-ret+pc+leaf+b-key -x c -E -dM %s -o - | FileCheck -check-prefixes=CHECK-PAUTH-LR,CHECK-BRANCH-PROTECTION-PC-LEAF-BKEY %s +// CHECK-BRANCH-PROTECTION-NO-PC: #define __ARM_FEATURE_PAC_DEFAULT 1 // CHECK-BRANCH-PROTECTION-PC: #define __ARM_FEATURE_PAC_DEFAULT 9 // CHECK-BRANCH-PROTECTION-PC-BKEY: #define __ARM_FEATURE_PAC_DEFAULT 10 // CHECK-BRANCH-PROTECTION-PC-LEAF: #define __ARM_FEATURE_PAC_DEFAULT 13 diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 26f1d33f6800..f2577e1684f5 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -76,6 +76,11 @@ Changes to the AArch64 Backend * Added support for Cortex-A78AE, Cortex-A520AE, Cortex-A720AE, Cortex-R82AE, Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs. +* ``-mbranch-protection=standard`` now enables FEAT_PAuth_LR by + default when the feature is enabled. The new behaviour results + in ``standard`` being equal to ``bti+pac-ret+pc`` when ``+pauth-lr`` + is passed as part of ``-mcpu=`` options. + Changes to the AMDGPU Backend ----------------------------- diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 1124420daf8d..20c3f95173c2 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -676,6 +676,8 @@ inline constexpr Alias CpuAliases[] = {{"cobalt-100", "neoverse-n2"}, inline constexpr Alias ExtAliases[] = {{"rdma", "rdm"}}; +const ExtensionInfo &getExtensionByID(ArchExtKind(ExtID)); + bool getExtensionFeatures( const AArch64::ExtensionBitset &Extensions, std::vector &Features); diff --git a/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h b/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h index 8ae553ca80dd..f6115718e9f5 100644 --- a/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h +++ b/llvm/include/llvm/TargetParser/ARMTargetParserCommon.h @@ -46,7 +46,7 @@ struct ParsedBranchProtection { }; bool parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, - StringRef &Err); + StringRef &Err, bool EnablePAuthLR = false); } // namespace ARM } // namespace llvm diff --git a/llvm/lib/TargetParser/AArch64TargetParser.cpp b/llvm/lib/TargetParser/AArch64TargetParser.cpp index 71099462d5ec..026214e7e2ea 100644 --- a/llvm/lib/TargetParser/AArch64TargetParser.cpp +++ b/llvm/lib/TargetParser/AArch64TargetParser.cpp @@ -280,3 +280,8 @@ bool AArch64::ExtensionSet::parseModifier(StringRef Modifier) { } return false; } + +const AArch64::ExtensionInfo & +AArch64::getExtensionByID(AArch64::ArchExtKind ExtID) { + return lookupExtensionByID(ExtID); +} diff --git a/llvm/lib/TargetParser/ARMTargetParserCommon.cpp b/llvm/lib/TargetParser/ARMTargetParserCommon.cpp index 45d04f9bcbfb..d6ce6581bb1a 100644 --- a/llvm/lib/TargetParser/ARMTargetParserCommon.cpp +++ b/llvm/lib/TargetParser/ARMTargetParserCommon.cpp @@ -139,7 +139,7 @@ ARM::EndianKind ARM::parseArchEndian(StringRef Arch) { // returned in `PBP`. Returns false in error, with `Err` containing // an erroneous part of the spec. bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, - StringRef &Err) { + StringRef &Err, bool EnablePAuthLR) { PBP = {"none", "a_key", false, false, false}; if (Spec == "none") return true; // defaults are ok @@ -148,6 +148,7 @@ bool ARM::parseBranchProtection(StringRef Spec, ParsedBranchProtection &PBP, PBP.Scope = "non-leaf"; PBP.BranchTargetEnforcement = true; PBP.GuardedControlStack = true; + PBP.BranchProtectionPAuthLR = EnablePAuthLR; return true; } -- GitLab From 5d24217c2c1c06358168cae65d3ff8632b28cd7d Mon Sep 17 00:00:00 2001 From: Petr Hosek Date: Fri, 10 May 2024 00:38:52 -0700 Subject: [PATCH 011/824] [Clang] Pass -fseparate-named-sections from the driver (#91567) This is a follow up to #91028. --- clang/lib/Driver/ToolChains/Clang.cpp | 2 ++ clang/test/Driver/fseparate-named-sections.c | 4 ++++ 2 files changed, 6 insertions(+) create mode 100644 clang/test/Driver/fseparate-named-sections.c diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index f81c2024ae48..42feb1650574 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -6146,6 +6146,8 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptOutFlag(CmdArgs, options::OPT_funique_section_names, options::OPT_fno_unique_section_names); + Args.addOptInFlag(CmdArgs, options::OPT_fseparate_named_sections, + options::OPT_fno_separate_named_sections); Args.addOptInFlag(CmdArgs, options::OPT_funique_internal_linkage_names, options::OPT_fno_unique_internal_linkage_names); Args.addOptInFlag(CmdArgs, options::OPT_funique_basic_block_section_names, diff --git a/clang/test/Driver/fseparate-named-sections.c b/clang/test/Driver/fseparate-named-sections.c new file mode 100644 index 000000000000..6264b8fcf0d8 --- /dev/null +++ b/clang/test/Driver/fseparate-named-sections.c @@ -0,0 +1,4 @@ +// RUN: %clang -### -fseparate-named-sections %s -c 2>&1 | FileCheck -check-prefix=CHECK-OPT %s +// RUN: %clang -### -fseparate-named-sections -fno-separate-named-sections %s -c 2>&1 | FileCheck -check-prefix=CHECK-NOOPT %s +// CHECK-OPT: "-fseparate-named-sections" +// CHECK-NOOPT-NOT: "-fseparate-named-sections" -- GitLab From a76518cadc5eaa6b6d07334e2b5bc08382aabe49 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 10 May 2024 09:20:48 +0100 Subject: [PATCH 012/824] [lldb][ELF] Return address class map changes from symbol table parsing methods (#91585) Instead of updating the member of the ObjectFileELF instance. This means that if one object file asks another to parse the symbol table, that first object's can update its address class map with the same changes that the other object did. (I'm not returning a reference to the other object's m_address_class_map member because there may be other things in there not related to the symbol table being parsed) This will fix the code added in https://github.com/llvm/llvm-project/pull/90622 which broke the test `Expr/TestStringLiteralExpr.test` on 32 bit Arm Linux. This happened because we had the program file, then asked for a better object file, which returned the same program file again. This creates a second ObjectFileELF for the same file, so when we tell the second instance to parse the symbol table it actually calls into the first instance, leaving the address class map of the second instance empty. Which caused us to put an Arm breakpoint instuction at a Thumb return address and broke the ability to call mmap. --- .../Plugins/ObjectFile/ELF/ObjectFileELF.cpp | 77 ++++++++++++------- .../Plugins/ObjectFile/ELF/ObjectFileELF.h | 21 ++--- 2 files changed, 60 insertions(+), 38 deletions(-) diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp index 1646ee9aa34a..d88f2d083019 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.cpp @@ -2060,13 +2060,17 @@ static char FindArmAarch64MappingSymbol(const char *symbol_name) { #define IS_MICROMIPS(ST_OTHER) (((ST_OTHER)&STO_MIPS_ISA) == STO_MICROMIPS) // private -unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, - SectionList *section_list, - const size_t num_symbols, - const DataExtractor &symtab_data, - const DataExtractor &strtab_data) { +std::pair +ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, + SectionList *section_list, const size_t num_symbols, + const DataExtractor &symtab_data, + const DataExtractor &strtab_data) { ELFSymbol symbol; lldb::offset_t offset = 0; + // The changes these symbols would make to the class map. We will also update + // m_address_class_map but need to tell the caller what changed because the + // caller may be another object file. + FileAddressToAddressClassMap address_class_map; static ConstString text_section_name(".text"); static ConstString init_section_name(".init"); @@ -2213,18 +2217,18 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, switch (mapping_symbol) { case 'a': // $a[.]* - marks an ARM instruction sequence - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; break; case 'b': case 't': // $b[.]* - marks a THUMB BL instruction sequence // $t[.]* - marks a THUMB instruction sequence - m_address_class_map[symbol.st_value] = + address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; break; case 'd': // $d[.]* - marks a data item sequence (e.g. lit pool) - m_address_class_map[symbol.st_value] = AddressClass::eData; + address_class_map[symbol.st_value] = AddressClass::eData; break; } } @@ -2238,11 +2242,11 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, switch (mapping_symbol) { case 'x': // $x[.]* - marks an A64 instruction sequence - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; break; case 'd': // $d[.]* - marks a data item sequence (e.g. lit pool) - m_address_class_map[symbol.st_value] = AddressClass::eData; + address_class_map[symbol.st_value] = AddressClass::eData; break; } } @@ -2260,11 +2264,11 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, // conjunction with symbol.st_value to produce the final // symbol_value that we store in the symtab. symbol_value_offset = -1; - m_address_class_map[symbol.st_value ^ 1] = + address_class_map[symbol.st_value ^ 1] = AddressClass::eCodeAlternateISA; } else { // This address is ARM - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; } } } @@ -2285,17 +2289,17 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, */ if (arch.IsMIPS()) { if (IS_MICROMIPS(symbol.st_other)) - m_address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; + address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; else if ((symbol.st_value & 1) && (symbol_type == eSymbolTypeCode)) { symbol.st_value = symbol.st_value & (~1ull); - m_address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; + address_class_map[symbol.st_value] = AddressClass::eCodeAlternateISA; } else { if (symbol_type == eSymbolTypeCode) - m_address_class_map[symbol.st_value] = AddressClass::eCode; + address_class_map[symbol.st_value] = AddressClass::eCode; else if (symbol_type == eSymbolTypeData) - m_address_class_map[symbol.st_value] = AddressClass::eData; + address_class_map[symbol.st_value] = AddressClass::eData; else - m_address_class_map[symbol.st_value] = AddressClass::eUnknown; + address_class_map[symbol.st_value] = AddressClass::eUnknown; } } } @@ -2392,24 +2396,33 @@ unsigned ObjectFileELF::ParseSymbols(Symtab *symtab, user_id_t start_id, dc_symbol.SetIsWeak(true); symtab->AddSymbol(dc_symbol); } - return i; + + m_address_class_map.merge(address_class_map); + return {i, address_class_map}; } -unsigned ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, - user_id_t start_id, - lldb_private::Section *symtab) { +std::pair +ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, user_id_t start_id, + lldb_private::Section *symtab) { if (symtab->GetObjectFile() != this) { // If the symbol table section is owned by a different object file, have it // do the parsing. ObjectFileELF *obj_file_elf = static_cast(symtab->GetObjectFile()); - return obj_file_elf->ParseSymbolTable(symbol_table, start_id, symtab); + auto [num_symbols, address_class_map] = + obj_file_elf->ParseSymbolTable(symbol_table, start_id, symtab); + + // The other object file returned the changes it made to its address + // class map, make the same changes to ours. + m_address_class_map.merge(address_class_map); + + return {num_symbols, address_class_map}; } // Get section list for this object file. SectionList *section_list = m_sections_up.get(); if (!section_list) - return 0; + return {}; user_id_t symtab_id = symtab->GetID(); const ELFSectionHeaderInfo *symtab_hdr = GetSectionHeaderByIndex(symtab_id); @@ -2435,7 +2448,7 @@ unsigned ObjectFileELF::ParseSymbolTable(Symtab *symbol_table, } } - return 0; + return {0, {}}; } size_t ObjectFileELF::ParseDynamicSymbols() { @@ -2972,8 +2985,12 @@ void ObjectFileELF::ParseSymtab(Symtab &lldb_symtab) { // while the reverse is not necessarily true. Section *symtab = section_list->FindSectionByType(eSectionTypeELFSymbolTable, true).get(); - if (symtab) - symbol_id += ParseSymbolTable(&lldb_symtab, symbol_id, symtab); + if (symtab) { + auto [num_symbols, address_class_map] = + ParseSymbolTable(&lldb_symtab, symbol_id, symtab); + m_address_class_map.merge(address_class_map); + symbol_id += num_symbols; + } // The symtab section is non-allocable and can be stripped, while the // .dynsym section which should always be always be there. To support the @@ -2986,8 +3003,12 @@ void ObjectFileELF::ParseSymtab(Symtab &lldb_symtab) { Section *dynsym = section_list->FindSectionByType(eSectionTypeELFDynamicSymbols, true) .get(); - if (dynsym) - symbol_id += ParseSymbolTable(&lldb_symtab, symbol_id, dynsym); + if (dynsym) { + auto [num_symbols, address_class_map] = + ParseSymbolTable(&lldb_symtab, symbol_id, dynsym); + symbol_id += num_symbols; + m_address_class_map.merge(address_class_map); + } } // DT_JMPREL diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h index bc8e34981a9d..716bbe01638f 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h @@ -285,18 +285,19 @@ private: /// Populates the symbol table with all non-dynamic linker symbols. This /// method will parse the symbols only once. Returns the number of symbols - /// parsed. - unsigned ParseSymbolTable(lldb_private::Symtab *symbol_table, - lldb::user_id_t start_id, - lldb_private::Section *symtab); + /// parsed and a map of address types (used by targets like Arm that have + /// an alternative ISA mode like Thumb). + std::pair + ParseSymbolTable(lldb_private::Symtab *symbol_table, lldb::user_id_t start_id, + lldb_private::Section *symtab); /// Helper routine for ParseSymbolTable(). - unsigned ParseSymbols(lldb_private::Symtab *symbol_table, - lldb::user_id_t start_id, - lldb_private::SectionList *section_list, - const size_t num_symbols, - const lldb_private::DataExtractor &symtab_data, - const lldb_private::DataExtractor &strtab_data); + std::pair + ParseSymbols(lldb_private::Symtab *symbol_table, lldb::user_id_t start_id, + lldb_private::SectionList *section_list, + const size_t num_symbols, + const lldb_private::DataExtractor &symtab_data, + const lldb_private::DataExtractor &strtab_data); /// Scans the relocation entries and adds a set of artificial symbols to the /// given symbol table for each PLT slot. Returns the number of symbols -- GitLab From 23b673e5b4b73b42864fcd7d63c1e974317ed4d6 Mon Sep 17 00:00:00 2001 From: David Green Date: Fri, 10 May 2024 09:27:02 +0100 Subject: [PATCH 013/824] [DAG][AArch64] Handle vscale addressing modes in reassociationCanBreakAddressingModePattern (#89908) reassociationCanBreakAddressingModePattern tries to prevent bad add reassociations that would break adrressing mode patterns. This adds support for vscale offset addressing modes, making sure we don't break patterns that already exist. It does not optimize _to_ the correct addressing modes yet, but prevents us from optimizating _away_ from them. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 42 ++++++++++++++- llvm/test/CodeGen/AArch64/sve-reassocadd.ll | 54 +++++++------------ 2 files changed, 58 insertions(+), 38 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 4589d201d620..fddc97d8901a 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -1083,7 +1083,44 @@ bool DAGCombiner::reassociationCanBreakAddressingModePattern(unsigned Opc, // (load/store (add, (add, x, y), offset2)) -> // (load/store (add, (add, x, offset2), y)). - if (Opc != ISD::ADD || N0.getOpcode() != ISD::ADD) + if (N0.getOpcode() != ISD::ADD) + return false; + + // Check for vscale addressing modes. + // (load/store (add/sub (add x, y), vscale)) + // (load/store (add/sub (add x, y), (lsl vscale, C))) + // (load/store (add/sub (add x, y), (mul vscale, C))) + if ((N1.getOpcode() == ISD::VSCALE || + ((N1.getOpcode() == ISD::SHL || N1.getOpcode() == ISD::MUL) && + N1.getOperand(0).getOpcode() == ISD::VSCALE && + isa(N1.getOperand(1)))) && + N1.getValueType().getFixedSizeInBits() <= 64) { + int64_t ScalableOffset = + N1.getOpcode() == ISD::VSCALE + ? N1.getConstantOperandVal(0) + : (N1.getOperand(0).getConstantOperandVal(0) * + (N1.getOpcode() == ISD::SHL ? (1 << N1.getConstantOperandVal(1)) + : N1.getConstantOperandVal(1))); + if (Opc == ISD::SUB) + ScalableOffset = -ScalableOffset; + if (all_of(N->uses(), [&](SDNode *Node) { + if (auto *LoadStore = dyn_cast(Node); + LoadStore && LoadStore->getBasePtr().getNode() == N) { + TargetLoweringBase::AddrMode AM; + AM.HasBaseReg = true; + AM.ScalableOffset = ScalableOffset; + EVT VT = LoadStore->getMemoryVT(); + unsigned AS = LoadStore->getAddressSpace(); + Type *AccessTy = VT.getTypeForEVT(*DAG.getContext()); + return TLI.isLegalAddressingMode(DAG.getDataLayout(), AM, AccessTy, + AS); + } + return false; + })) + return true; + } + + if (Opc != ISD::ADD) return false; auto *C2 = dyn_cast(N1); @@ -3971,7 +4008,8 @@ SDValue DAGCombiner::visitSUB(SDNode *N) { // Hoist one-use addition by non-opaque constant: // (x + C) - y -> (x - y) + C - if (N0.getOpcode() == ISD::ADD && N0.hasOneUse() && + if (!reassociationCanBreakAddressingModePattern(ISD::SUB, DL, N, N0, N1) && + N0.getOpcode() == ISD::ADD && N0.hasOneUse() && isConstantOrConstantVector(N0.getOperand(1), /*NoOpaques=*/true)) { SDValue Sub = DAG.getNode(ISD::SUB, DL, VT, N0.getOperand(0), N1); return DAG.getNode(ISD::ADD, DL, VT, Sub, N0.getOperand(1)); diff --git a/llvm/test/CodeGen/AArch64/sve-reassocadd.ll b/llvm/test/CodeGen/AArch64/sve-reassocadd.ll index c7261200a567..f54098b29a27 100644 --- a/llvm/test/CodeGen/AArch64/sve-reassocadd.ll +++ b/llvm/test/CodeGen/AArch64/sve-reassocadd.ll @@ -22,11 +22,9 @@ entry: define @i8_4s_1v(ptr %b) { ; CHECK-LABEL: i8_4s_1v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: mov w9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9] +; CHECK-NEXT: add x8, x0, #4 +; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 4 @@ -58,11 +56,9 @@ entry: define @i16_8s_1v(ptr %b) { ; CHECK-LABEL: i16_8s_1v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] +; CHECK-NEXT: add x8, x0, #8 +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 8 @@ -94,11 +90,9 @@ entry: define @i16_8s_2v(ptr %b) { ; CHECK-LABEL: i16_8s_2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #2 ; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] +; CHECK-NEXT: add x8, x0, #8 +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, #2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 8 @@ -130,11 +124,9 @@ entry: define @i32_16s_2v(ptr %b) { ; CHECK-LABEL: i32_16s_2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2] +; CHECK-NEXT: add x8, x0, #16 +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 16 @@ -166,11 +158,9 @@ entry: define @i64_32s_2v(ptr %b) { ; CHECK-LABEL: i64_32s_2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: rdvl x8, #1 ; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: add x8, x0, x8 -; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3] +; CHECK-NEXT: add x8, x0, #32 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #1, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 32 @@ -203,11 +193,9 @@ entry: define @i8_4s_m2v(ptr %b) { ; CHECK-LABEL: i8_4s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.b -; CHECK-NEXT: mov w9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, x9] +; CHECK-NEXT: add x8, x0, #4 +; CHECK-NEXT: ld1b { z0.b }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 4 @@ -239,11 +227,9 @@ entry: define @i16_8s_m2v(ptr %b) { ; CHECK-LABEL: i16_8s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.h -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, x9, lsl #1] +; CHECK-NEXT: add x8, x0, #8 +; CHECK-NEXT: ld1h { z0.h }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 8 @@ -275,11 +261,9 @@ entry: define @i32_16s_m2v(ptr %b) { ; CHECK-LABEL: i32_16s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.s -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, x9, lsl #2] +; CHECK-NEXT: add x8, x0, #16 +; CHECK-NEXT: ld1w { z0.s }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 16 @@ -311,11 +295,9 @@ entry: define @i64_32s_m2v(ptr %b) { ; CHECK-LABEL: i64_32s_m2v: ; CHECK: // %bb.0: // %entry -; CHECK-NEXT: cnth x8, all, mul #4 ; CHECK-NEXT: ptrue p0.d -; CHECK-NEXT: mov x9, #4 // =0x4 -; CHECK-NEXT: sub x8, x0, x8 -; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, x9, lsl #3] +; CHECK-NEXT: add x8, x0, #32 +; CHECK-NEXT: ld1d { z0.d }, p0/z, [x8, #-2, mul vl] ; CHECK-NEXT: ret entry: %add.ptr = getelementptr inbounds i8, ptr %b, i64 32 -- GitLab From e6d29be566d19a6558597ed1ede4783e85485749 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 10 May 2024 09:56:11 +0100 Subject: [PATCH 014/824] [clang] fix FMV test for Win x Arm builds (#91490) --- clang/test/Driver/aarch64-fmv.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/test/Driver/aarch64-fmv.c b/clang/test/Driver/aarch64-fmv.c index 873a88964e9b..e7d01d1d5906 100644 --- a/clang/test/Driver/aarch64-fmv.c +++ b/clang/test/Driver/aarch64-fmv.c @@ -11,8 +11,8 @@ // RUN: %clang --target=aarch64-linux-android23 --rtlib=compiler-rt -### -c %s 2>&1 | FileCheck -check-prefix=FMV-ENABLED %s // FMV is disabled without compiler-rt: -// RUN: %clang --target=aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s -// RUN: %clang --target=aarch64-linux-gnu -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --rtlib=libgcc --target=aarch64 -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s +// RUN: %clang --rtlib=libgcc --target=aarch64-linux-gnu -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s // Disabled for older android versions: // RUN: %clang --rtlib=compiler-rt --target=aarch64-linux-android -### -c %s 2>&1 | FileCheck -check-prefix=FMV-DISABLED %s -- GitLab From 641949654910a533076e35517d084e2961adbdfa Mon Sep 17 00:00:00 2001 From: Abid Qadeer Date: Fri, 10 May 2024 10:12:24 +0100 Subject: [PATCH 015/824] [flang][OMPIRBuilder] Keep debug location in sync with insert point. (#89953) A customer reported an issue which I have reduced to the test in the PR. If built with debug info enabled, the build fails with the following error in the verifier. !dbg attachment points at wrong subprogram for function The problem happened because some of the functions in OMPIRBuilder.cpp updated the insertion point with the passed in location but did not change the current debug location. This caused a stale debug location to be attached to the instruction. I have solved it by replacing restoreIP with updateToLocation which updates both the insertion point and debug location. The updateToLocation is used in many places already, so this PR brings functions that I have changed in line with rest of the file. Slight issue is that I am not checking the return type of updateToLocation as there is no good value I could return in that case. But if we have a condition where updateToLocation will return false, these functions will fail in any case. I have added a test that checks that build does not fail. I was not sure what is the correct location for the test should be. Happy to move it to more appropriate location. --- flang/test/Integration/debug-loc-1.f90 | 30 +++++++++++++++++++++++ llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp | 12 ++++----- 2 files changed, 36 insertions(+), 6 deletions(-) create mode 100644 flang/test/Integration/debug-loc-1.f90 diff --git a/flang/test/Integration/debug-loc-1.f90 b/flang/test/Integration/debug-loc-1.f90 new file mode 100644 index 000000000000..5fe2c8e31dd9 --- /dev/null +++ b/flang/test/Integration/debug-loc-1.f90 @@ -0,0 +1,30 @@ +!RUN: %flang_fc1 -emit-llvm -debug-info-kind=line-tables-only -fopenmp %s -o - | FileCheck %s + +! Test that this file builds without an error. + +module debugloc +contains +subroutine test1 +implicit none + integer :: i + real, save :: var + +! CHECK: DILocation(line: [[@LINE+1]], {{.*}}) +!$omp parallel do +do i=1,100 + var = var + 0.1 +end do +!$omp end parallel do + +end subroutine test1 + +subroutine test2 + +real, save :: tp +!$omp threadprivate (tp) +! CHECK: DILocation(line: [[@LINE+1]], {{.*}}) + tp = tp + 1 + +end subroutine test2 + +end module debugloc diff --git a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp index 9f0c07ef0da9..42ea20919a5e 100644 --- a/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp +++ b/llvm/lib/Frontend/OpenMP/OMPIRBuilder.cpp @@ -4401,7 +4401,7 @@ CallInst *OpenMPIRBuilder::createOMPAlloc(const LocationDescription &Loc, Value *Size, Value *Allocator, std::string Name) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4418,7 +4418,7 @@ CallInst *OpenMPIRBuilder::createOMPFree(const LocationDescription &Loc, Value *Addr, Value *Allocator, std::string Name) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4434,7 +4434,7 @@ CallInst *OpenMPIRBuilder::createOMPInteropInit( omp::OMPInteropType InteropType, Value *Device, Value *NumDependences, Value *DependenceAddress, bool HaveNowaitClause) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4462,7 +4462,7 @@ CallInst *OpenMPIRBuilder::createOMPInteropDestroy( const LocationDescription &Loc, Value *InteropVar, Value *Device, Value *NumDependences, Value *DependenceAddress, bool HaveNowaitClause) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); @@ -4491,7 +4491,7 @@ CallInst *OpenMPIRBuilder::createOMPInteropUse(const LocationDescription &Loc, Value *DependenceAddress, bool HaveNowaitClause) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); Value *Ident = getOrCreateIdent(SrcLocStr, SrcLocStrSize); @@ -4517,7 +4517,7 @@ CallInst *OpenMPIRBuilder::createCachedThreadPrivate( const LocationDescription &Loc, llvm::Value *Pointer, llvm::ConstantInt *Size, const llvm::Twine &Name) { IRBuilder<>::InsertPointGuard IPG(Builder); - Builder.restoreIP(Loc.IP); + updateToLocation(Loc); uint32_t SrcLocStrSize; Constant *SrcLocStr = getOrCreateSrcLocStr(Loc, SrcLocStrSize); -- GitLab From fc57f88f007497a4ead0ec8607ac66e1847b02d6 Mon Sep 17 00:00:00 2001 From: cor3ntin Date: Fri, 10 May 2024 11:15:26 +0200 Subject: [PATCH 016/824] [Clang] Fix Undefined Behavior introduced by #91199 (#91718) We stack allocated an OpaqueExpr that would be used after it was destroyed. e.g https://lab.llvm.org/buildbot/#/builders/57/builds/34909 --- clang/lib/Sema/SemaExprCXX.cpp | 26 +++++++++++++------------- 1 file changed, 13 insertions(+), 13 deletions(-) diff --git a/clang/lib/Sema/SemaExprCXX.cpp b/clang/lib/Sema/SemaExprCXX.cpp index ae844bc69914..c181092113e1 100644 --- a/clang/lib/Sema/SemaExprCXX.cpp +++ b/clang/lib/Sema/SemaExprCXX.cpp @@ -5627,10 +5627,9 @@ static bool EvaluateUnaryTypeTrait(Sema &Self, TypeTrait UTT, static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceInfo *Lhs, const TypeSourceInfo *Rhs, SourceLocation KeyLoc); -static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, - const TypeSourceInfo *Lhs, - const TypeSourceInfo *Rhs, - SourceLocation KeyLoc) { +static ExprResult CheckConvertibilityForTypeTraits( + Sema &Self, const TypeSourceInfo *Lhs, const TypeSourceInfo *Rhs, + SourceLocation KeyLoc, llvm::BumpPtrAllocator &OpaqueExprAllocator) { QualType LhsT = Lhs->getType(); QualType RhsT = Rhs->getType(); @@ -5675,9 +5674,9 @@ static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, // Build a fake source and destination for initialization. InitializedEntity To(InitializedEntity::InitializeTemporary(RhsT)); - OpaqueValueExpr From(KeyLoc, LhsT.getNonLValueExprType(Self.Context), - Expr::getValueKindForType(LhsT)); - Expr *FromPtr = &From; + Expr *From = new (OpaqueExprAllocator.Allocate()) + OpaqueValueExpr(KeyLoc, LhsT.getNonLValueExprType(Self.Context), + Expr::getValueKindForType(LhsT)); InitializationKind Kind = InitializationKind::CreateCopy(KeyLoc, SourceLocation()); @@ -5687,11 +5686,11 @@ static ExprResult CheckConvertibilityForTypeTraits(Sema &Self, Self, Sema::ExpressionEvaluationContext::Unevaluated); Sema::SFINAETrap SFINAE(Self, /*AccessCheckingSFINAE=*/true); Sema::ContextRAII TUContext(Self, Self.Context.getTranslationUnitDecl()); - InitializationSequence Init(Self, To, Kind, FromPtr); + InitializationSequence Init(Self, To, Kind, From); if (Init.Failed()) return ExprError(); - ExprResult Result = Init.Perform(Self, To, Kind, FromPtr); + ExprResult Result = Init.Perform(Self, To, Kind, From); if (Result.isInvalid() || SFINAE.hasErrorOccurred()) return ExprError(); @@ -5819,7 +5818,8 @@ static bool EvaluateBooleanTypeTrait(Sema &S, TypeTrait Kind, S.Context.getPointerType(T.getNonReferenceType())); TypeSourceInfo *UPtr = S.Context.CreateTypeSourceInfo( S.Context.getPointerType(U.getNonReferenceType())); - return !CheckConvertibilityForTypeTraits(S, UPtr, TPtr, RParenLoc) + return !CheckConvertibilityForTypeTraits(S, UPtr, TPtr, RParenLoc, + OpaqueExprAllocator) .isInvalid(); } @@ -6028,9 +6028,9 @@ static bool EvaluateBinaryTypeTrait(Sema &Self, TypeTrait BTT, const TypeSourceI case BTT_IsNothrowConvertible: { if (RhsT->isVoidType()) return LhsT->isVoidType(); - - ExprResult Result = - CheckConvertibilityForTypeTraits(Self, Lhs, Rhs, KeyLoc); + llvm::BumpPtrAllocator OpaqueExprAllocator; + ExprResult Result = CheckConvertibilityForTypeTraits(Self, Lhs, Rhs, KeyLoc, + OpaqueExprAllocator); if (Result.isInvalid()) return false; -- GitLab From 1aca8ed5a7eeed264fdc2694deca8a4a4dba3689 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 10 May 2024 09:25:03 +0000 Subject: [PATCH 017/824] [lldb][ELF] Add a comment to explain address class map type It was pointed out that ordering is crucial here, so note that. I also looked into using a vector instead, as described in https://llvm.org/docs/ProgrammersManual.html#dss-sortedvectorset. Which this is in theory perfect for, but we have at least 2 places that update the map and both would need to sort/unique each time. Plus this code is pretty bug prone. If there is future refactoring it's one thing to consider. --- lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h | 3 +++ 1 file changed, 3 insertions(+) diff --git a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h index 716bbe01638f..844e981b1d89 100644 --- a/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h +++ b/lldb/source/Plugins/ObjectFile/ELF/ObjectFileELF.h @@ -187,6 +187,9 @@ private: typedef DynamicSymbolColl::iterator DynamicSymbolCollIter; typedef DynamicSymbolColl::const_iterator DynamicSymbolCollConstIter; + /// An ordered map of file address to address class. Used on architectures + /// like Arm where there is an alternative ISA mode like Thumb. The container + /// is ordered so that it can be binary searched. typedef std::map FileAddressToAddressClassMap; -- GitLab From b277bf56d7654877a1c4b59dc08bc96b4d75b649 Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Fri, 10 May 2024 10:53:57 +0100 Subject: [PATCH 018/824] [LLVM][CodeGen][SVE] Clean up lowering of VECTOR_SPLICE operations. (#91330) Remove DAG combine that is performing type legalisation and instead add isel patterns for all legal types. --- .../SelectionDAG/SelectionDAGBuilder.cpp | 3 +- .../Target/AArch64/AArch64ISelLowering.cpp | 38 ++----- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 23 ++-- llvm/lib/Target/AArch64/SVEInstrFormats.td | 17 +-- .../AArch64/named-vector-shuffles-sve.ll | 104 ++++++++++++++++++ 5 files changed, 136 insertions(+), 49 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index eac4297b89b5..b76036a22992 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -12240,9 +12240,8 @@ void SelectionDAGBuilder::visitVectorSplice(const CallInst &I) { // VECTOR_SHUFFLE doesn't support a scalable mask so use a dedicated node. if (VT.isScalableVector()) { - MVT IdxVT = TLI.getVectorIdxTy(DAG.getDataLayout()); setValue(&I, DAG.getNode(ISD::VECTOR_SPLICE, DL, VT, V1, V2, - DAG.getConstant(Imm, DL, IdxVT))); + DAG.getVectorIdxConstant(Imm, DL))); return; } diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 7344387ffe55..29b66a72d21d 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -1048,9 +1048,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setTargetDAGCombine(ISD::INTRINSIC_WO_CHAIN); setTargetDAGCombine({ISD::ANY_EXTEND, ISD::ZERO_EXTEND, ISD::SIGN_EXTEND, - ISD::VECTOR_SPLICE, ISD::SIGN_EXTEND_INREG, - ISD::CONCAT_VECTORS, ISD::EXTRACT_SUBVECTOR, - ISD::INSERT_SUBVECTOR, ISD::STORE, ISD::BUILD_VECTOR}); + ISD::SIGN_EXTEND_INREG, ISD::CONCAT_VECTORS, + ISD::EXTRACT_SUBVECTOR, ISD::INSERT_SUBVECTOR, + ISD::STORE, ISD::BUILD_VECTOR}); setTargetDAGCombine(ISD::TRUNCATE); setTargetDAGCombine(ISD::LOAD); @@ -1580,6 +1580,7 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::MLOAD, VT, Custom); setOperationAction(ISD::INSERT_SUBVECTOR, VT, Custom); setOperationAction(ISD::SPLAT_VECTOR, VT, Legal); + setOperationAction(ISD::VECTOR_SPLICE, VT, Custom); if (!Subtarget->isLittleEndian()) setOperationAction(ISD::BITCAST, VT, Expand); @@ -10102,10 +10103,9 @@ SDValue AArch64TargetLowering::LowerVECTOR_SPLICE(SDValue Op, Op.getOperand(1)); } - // This will select to an EXT instruction, which has a maximum immediate - // value of 255, hence 2048-bits is the maximum value we can lower. - if (IdxVal >= 0 && - IdxVal < int64_t(2048 / Ty.getVectorElementType().getSizeInBits())) + // We can select to an EXT instruction when indexing the first 256 bytes. + unsigned BlockSize = AArch64::SVEBitsPerBlock / Ty.getVectorMinNumElements(); + if (IdxVal >= 0 && (IdxVal * BlockSize / 8) < 256) return Op; return SDValue(); @@ -24255,28 +24255,6 @@ performInsertVectorEltCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) { return performPostLD1Combine(N, DCI, true); } -static SDValue performSVESpliceCombine(SDNode *N, SelectionDAG &DAG) { - EVT Ty = N->getValueType(0); - if (Ty.isInteger()) - return SDValue(); - - EVT IntTy = Ty.changeVectorElementTypeToInteger(); - EVT ExtIntTy = getPackedSVEVectorVT(IntTy.getVectorElementCount()); - if (ExtIntTy.getVectorElementType().getScalarSizeInBits() < - IntTy.getVectorElementType().getScalarSizeInBits()) - return SDValue(); - - SDLoc DL(N); - SDValue LHS = DAG.getAnyExtOrTrunc(DAG.getBitcast(IntTy, N->getOperand(0)), - DL, ExtIntTy); - SDValue RHS = DAG.getAnyExtOrTrunc(DAG.getBitcast(IntTy, N->getOperand(1)), - DL, ExtIntTy); - SDValue Idx = N->getOperand(2); - SDValue Splice = DAG.getNode(ISD::VECTOR_SPLICE, DL, ExtIntTy, LHS, RHS, Idx); - SDValue Trunc = DAG.getAnyExtOrTrunc(Splice, DL, IntTy); - return DAG.getBitcast(Ty, Trunc); -} - static SDValue performFPExtendCombine(SDNode *N, SelectionDAG &DAG, TargetLowering::DAGCombinerInfo &DCI, const AArch64Subtarget *Subtarget) { @@ -24661,8 +24639,6 @@ SDValue AArch64TargetLowering::PerformDAGCombine(SDNode *N, case ISD::MGATHER: case ISD::MSCATTER: return performMaskedGatherScatterCombine(N, DCI, DAG); - case ISD::VECTOR_SPLICE: - return performSVESpliceCombine(N, DAG); case ISD::FP_EXTEND: return performFPExtendCombine(N, DAG, DCI, Subtarget); case AArch64ISD::BRCOND: diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 62e68de1359f..64e545aa26b4 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1994,14 +1994,21 @@ let Predicates = [HasSVEorSME] in { (LASTB_VPZ_D (PTRUE_D 31), ZPR:$Z1), dsub))>; // Splice with lane bigger or equal to 0 - def : Pat<(nxv16i8 (vector_splice (nxv16i8 ZPR:$Z1), (nxv16i8 ZPR:$Z2), (i64 (sve_ext_imm_0_255 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; - def : Pat<(nxv8i16 (vector_splice (nxv8i16 ZPR:$Z1), (nxv8i16 ZPR:$Z2), (i64 (sve_ext_imm_0_127 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; - def : Pat<(nxv4i32 (vector_splice (nxv4i32 ZPR:$Z1), (nxv4i32 ZPR:$Z2), (i64 (sve_ext_imm_0_63 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; - def : Pat<(nxv2i64 (vector_splice (nxv2i64 ZPR:$Z1), (nxv2i64 ZPR:$Z2), (i64 (sve_ext_imm_0_31 i32:$index)))), - (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + foreach VT = [nxv16i8] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_255 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + + foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_127 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + + foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_63 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; + + foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in + def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_31 i32:$index)))), + (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>; defm CMPHI_PPzZZ : sve_int_cmp_0<0b001, "cmphi", SETUGT, SETULT>; diff --git a/llvm/lib/Target/AArch64/SVEInstrFormats.td b/llvm/lib/Target/AArch64/SVEInstrFormats.td index 69c3238c7d61..fc7d3cdda4ac 100644 --- a/llvm/lib/Target/AArch64/SVEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SVEInstrFormats.td @@ -7060,16 +7060,17 @@ multiclass sve_int_perm_splice { def _S : sve_int_perm_splice<0b10, asm, ZPR32>; def _D : sve_int_perm_splice<0b11, asm, ZPR64>; - def : SVE_3_Op_Pat(NAME # _B)>; - def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _S)>; - def : SVE_3_Op_Pat(NAME # _D)>; + foreach VT = [nxv16i8] in + def : SVE_3_Op_Pat(NAME # _B)>; - def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _S)>; - def : SVE_3_Op_Pat(NAME # _D)>; + foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in + def : SVE_3_Op_Pat(NAME # _H)>; - def : SVE_3_Op_Pat(NAME # _H)>; + foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in + def : SVE_3_Op_Pat(NAME # _S)>; + + foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in + def : SVE_3_Op_Pat(NAME # _D)>; } class sve2_int_perm_splice_cons sz8_64, string asm, diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll index f5763cd61033..d1171bc31247 100644 --- a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll +++ b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll @@ -692,6 +692,104 @@ define @splice_nxv2f64_neg3( %a, %res } +define @splice_nxv2bf16_neg_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv2bf16_neg_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d, vl1 +; CHECK-NEXT: rev p0.d, p0.d +; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 -1) + ret %res +} + +define @splice_nxv2bf16_neg2_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv2bf16_neg2_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.d, vl2 +; CHECK-NEXT: rev p0.d, p0.d +; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 -2) + ret %res +} + +define @splice_nxv2bf16_first_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv2bf16_first_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 1) + ret %res +} + +define @splice_nxv2bf16_last_idx( %a, %b) vscale_range(16,16) #0 { +; CHECK-LABEL: splice_nxv2bf16_last_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv2bf16( %a, %b, i32 31) + ret %res +} + +define @splice_nxv4bf16_neg_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv4bf16_neg_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s, vl1 +; CHECK-NEXT: rev p0.s, p0.s +; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 -1) + ret %res +} + +define @splice_nxv4bf16_neg3_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv4bf16_neg3_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ptrue p0.s, vl3 +; CHECK-NEXT: rev p0.s, p0.s +; CHECK-NEXT: splice z0.s, p0, z0.s, z1.s +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 -3) + ret %res +} + +define @splice_nxv4bf16_first_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv4bf16_first_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 1) + ret %res +} + +define @splice_nxv4bf16_last_idx( %a, %b) vscale_range(16,16) #0 { +; CHECK-LABEL: splice_nxv4bf16_last_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #252 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv4bf16( %a, %b, i32 63) + ret %res +} + +define @splice_nxv8bf16_first_idx( %a, %b) #0 { +; CHECK-LABEL: splice_nxv8bf16_first_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #2 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv8bf16( %a, %b, i32 1) + ret %res +} + +define @splice_nxv8bf16_last_idx( %a, %b) vscale_range(16,16) #0 { +; CHECK-LABEL: splice_nxv8bf16_last_idx: +; CHECK: // %bb.0: +; CHECK-NEXT: ext z0.b, z0.b, z1.b, #254 +; CHECK-NEXT: ret + %res = call @llvm.vector.splice.nxv8bf16( %a, %b, i32 127) + ret %res +} + ; Ensure predicate based splice is promoted to use ZPRs. define @splice_nxv2i1( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i1: @@ -834,12 +932,14 @@ declare @llvm.vector.splice.nxv2i1(, @llvm.vector.splice.nxv4i1(, , i32) declare @llvm.vector.splice.nxv8i1(, , i32) declare @llvm.vector.splice.nxv16i1(, , i32) + declare @llvm.vector.splice.nxv2i8(, , i32) declare @llvm.vector.splice.nxv16i8(, , i32) declare @llvm.vector.splice.nxv8i16(, , i32) declare @llvm.vector.splice.nxv4i32(, , i32) declare @llvm.vector.splice.nxv8i32(, , i32) declare @llvm.vector.splice.nxv2i64(, , i32) + declare @llvm.vector.splice.nxv2f16(, , i32) declare @llvm.vector.splice.nxv4f16(, , i32) declare @llvm.vector.splice.nxv8f16(, , i32) @@ -848,4 +948,8 @@ declare @llvm.vector.splice.nxv4f32(, < declare @llvm.vector.splice.nxv16f32(, , i32) declare @llvm.vector.splice.nxv2f64(, , i32) +declare @llvm.vector.splice.nxv2bf16(, , i32) +declare @llvm.vector.splice.nxv4bf16(, , i32) +declare @llvm.vector.splice.nxv8bf16(, , i32) + attributes #0 = { nounwind "target-features"="+sve" } -- GitLab From 64d4ade3bb7d0d8cc87a777f4964e68f2f25edf9 Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 10 May 2024 11:14:26 +0100 Subject: [PATCH 019/824] [AArch64] Add intrinsics for 16-bit non-widening FMLA/FMLS (#88553) According to the specification in https://github.com/ARM-software/acle/pull/309 add the following intrinsics void svmla[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmla[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) void svmls[_single]_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) void svmla_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmla_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmls_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) void svmls_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) void svmla_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmla_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm, uint64_t imm_idx) void svmls_lane_za16[_f16]_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm, uint64_t imm_idx) as well as the corresponding `_bf16` variants. --- clang/include/clang/Basic/arm_sme.td | 34 + .../acle_sme2_fmlas16.c | 592 ++++++++++++++++++ .../acle_sme2_fmlas16.c | 90 +++ .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 59 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 54 +- .../AArch64/sme2-intrinsics-fmlas16.ll | 462 ++++++++++++++ 6 files changed, 1254 insertions(+), 37 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c create mode 100644 clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 1ac6d5170ea2..77ea53fb83fa 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -458,6 +458,40 @@ let TargetGuard = "sme2,sme-f64f64" in { def SVMLS_LANE_VG1x4_F64 : Inst<"svmls_lane_za64[_{d}]_vg1x4", "vm4di", "d", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_1>]>; } +let TargetGuard = "sme-f16f16" in { + def SVMLA_MULTI_VG1x2_F16 : Inst<"svmla_za16[_f16]_vg1x2", "vm22", "h", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_MULTI_VG1x4_F16 : Inst<"svmla_za16[_f16]_vg1x4", "vm44", "h", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x2_F16 : Inst<"svmls_za16[_f16]_vg1x2", "vm22", "h", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x4_F16 : Inst<"svmls_za16[_f16]_vg1x4", "vm44", "h", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_SINGLE_VG1x2_F16 : Inst<"svmla[_single]_za16[_f16]_vg1x2", "vm2d", "h", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_SINGLE_VG1x4_F16 : Inst<"svmla[_single]_za16[_f16]_vg1x4", "vm4d", "h", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x2_F16 : Inst<"svmls[_single]_za16[_f16]_vg1x2", "vm2d", "h", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x4_F16 : Inst<"svmls[_single]_za16[_f16]_vg1x4", "vm4d", "h", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_LANE_VG1x2_F16 : Inst<"svmla_lane_za16[_f16]_vg1x2", "vm2di", "h", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLA_LANE_VG1x4_F16 : Inst<"svmla_lane_za16[_f16]_vg1x4", "vm4di", "h", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x2_F16 : Inst<"svmls_lane_za16[_f16]_vg1x2", "vm2di", "h", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x4_F16 : Inst<"svmls_lane_za16[_f16]_vg1x4", "vm4di", "h", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; +} + +let TargetGuard = "sme2,b16b16" in { + def SVMLA_MULTI_VG1x2_BF16 : Inst<"svmla_za16[_bf16]_vg1x2", "vm22", "b", MergeNone, "aarch64_sme_fmla_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_MULTI_VG1x4_BF16 : Inst<"svmla_za16[_bf16]_vg1x4", "vm44", "b", MergeNone, "aarch64_sme_fmla_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x2_BF16 : Inst<"svmls_za16[_bf16]_vg1x2", "vm22", "b", MergeNone, "aarch64_sme_fmls_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_MULTI_VG1x4_BF16 : Inst<"svmls_za16[_bf16]_vg1x4", "vm44", "b", MergeNone, "aarch64_sme_fmls_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_SINGLE_VG1x2_BF16 : Inst<"svmla[_single]_za16[_bf16]_vg1x2", "vm2d", "b", MergeNone, "aarch64_sme_fmla_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLA_SINGLE_VG1x4_BF16 : Inst<"svmla[_single]_za16[_bf16]_vg1x4", "vm4d", "b", MergeNone, "aarch64_sme_fmla_single_vg1x4", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x2_BF16 : Inst<"svmls[_single]_za16[_bf16]_vg1x2", "vm2d", "b", MergeNone, "aarch64_sme_fmls_single_vg1x2", [IsStreaming, IsInOutZA], []>; + def SVMLS_SINGLE_VG1x4_BF16 : Inst<"svmls[_single]_za16[_bf16]_vg1x4", "vm4d", "b", MergeNone, "aarch64_sme_fmls_single_vg1x4", [IsStreaming, IsInOutZA], []>; + + def SVMLA_LANE_VG1x2_BF16 : Inst<"svmla_lane_za16[_bf16]_vg1x2", "vm2di", "b", MergeNone, "aarch64_sme_fmla_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLA_LANE_VG1x4_BF16 : Inst<"svmla_lane_za16[_bf16]_vg1x4", "vm4di", "b", MergeNone, "aarch64_sme_fmla_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x2_BF16 : Inst<"svmls_lane_za16[_bf16]_vg1x2", "vm2di", "b", MergeNone, "aarch64_sme_fmls_lane_vg1x2", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; + def SVMLS_LANE_VG1x4_BF16 : Inst<"svmls_lane_za16[_bf16]_vg1x4", "vm4di", "b", MergeNone, "aarch64_sme_fmls_lane_vg1x4", [IsStreaming, IsInOutZA], [ImmCheck<3, ImmCheck0_7>]>; +} + // FMLAL/FMLSL/UMLAL/SMLAL // SMLALL/UMLALL/USMLALL/SUMLALL let TargetGuard = "sme2" in { diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c new file mode 100644 index 000000000000..ecc415545414 --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c @@ -0,0 +1,592 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefix CHECK-CXX +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -Werror -Wall -emit-llvm -o - %s | FileCheck %s --check-prefix CHECK-CXX + +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +sme-f16f16 -target-feature +b16b16 -O2 -S -Werror -Wall %s -o /dev/null + +// REQUIRES: aarch64-registered-target +#include + +#ifdef SME_OVERLOADED_FORMS +#define SME_ACLE_FUNC(A1, A2_UNUSED, A3, A4_UNUSED, A5) A1##A3##A5 +#else +#define SME_ACLE_FUNC(A1, A2, A3, A4, A5) A1##A2##A3##A4##A5 +#endif + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmla_single_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,_single,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmla_single_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,_single,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmls_single_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,_single,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z32test_svmls_single_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,_single,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmla_za16_f16_vg1x2j13svfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmla_za16_f16_vg1x4j13svfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla,,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmls_za16_f16_vg1x2j13svfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,,_za16,_f16,_vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z25test_svmls_za16_f16_vg1x4j13svfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls,,_za16,_f16,_vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmla_lane_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane,,_za16,_f16,_vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmla_lane_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane,,_za16,_f16,_vg1x4)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_f16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmls_lane_za16_f16_vg1x2j13svfloat16x2_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv16f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_f16_vg1x2(uint32_t slice, svfloat16x2_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane,,_za16,_f16,_vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_f16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z30test_svmls_lane_za16_f16_vg1x4j13svfloat16x4_tu13__SVFloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8f16.nxv32f16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_f16_vg1x4(uint32_t slice, svfloat16x4_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane,,_za16,_f16,_vg1x4)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmla_single_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, _single, _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_single_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmla_single_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_single_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, _single, _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmls_single_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, _single, _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_single_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z33test_svmls_single_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_single_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, _single, _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmla_za16_bf16_vg1x2j14svbfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, , _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmla_za16_bf16_vg1x4j14svbfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla, , _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmls_za16_bf16_vg1x2j14svbfloat16x2_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16x2_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, , _za16, _bf16, _vg1x2)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmls_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z26test_svmls_za16_bf16_vg1x4j14svbfloat16x4_tS_( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: [[TMP4:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 0) +// CHECK-CXX-NEXT: [[TMP5:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 8) +// CHECK-CXX-NEXT: [[TMP6:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 16) +// CHECK-CXX-NEXT: [[TMP7:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZM]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[TMP4]], [[TMP5]], [[TMP6]], [[TMP7]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16x4_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls, , _za16, _bf16, _vg1x4)(slice, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmla_lane_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane, , _za16, _bf16, _vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmla_lane_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmla_lane_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmla_lane_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmla_lane, , _za16, _bf16, _vg1x4)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_bf16_vg1x2( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmls_lane_za16_bf16_vg1x2j14svbfloat16x2_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv16bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_bf16_vg1x2(uint32_t slice, svbfloat16x2_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane, , _za16, _bf16, _vg1x2)(slice, zn, zm, 7); +} + +// CHECK-LABEL: define dso_local void @test_svmls_lane_za16_bf16_vg1x4( +// CHECK-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z31test_svmls_lane_za16_bf16_vg1x4j14svbfloat16x4_tu14__SVBfloat16_t( +// CHECK-CXX-SAME: i32 noundef [[SLICE:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 0) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 8) +// CHECK-CXX-NEXT: [[TMP2:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 16) +// CHECK-CXX-NEXT: [[TMP3:%.*]] = tail call @llvm.vector.extract.nxv8bf16.nxv32bf16( [[ZN]], i64 24) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 [[SLICE]], [[TMP0]], [[TMP1]], [[TMP2]], [[TMP3]], [[ZM]], i32 7) +// CHECK-CXX-NEXT: ret void +// +void test_svmls_lane_za16_bf16_vg1x4(uint32_t slice, svbfloat16x4_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmls_lane, , _za16, _bf16, _vg1x4)(slice, zn, zm, 7); +} diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c new file mode 100644 index 000000000000..b1582569971d --- /dev/null +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_fmlas16.c @@ -0,0 +1,90 @@ +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -verify -emit-llvm %s + +// REQUIRES: aarch64-registered-target + +#include + + +void test_features_f16f16(uint32_t slice, + svfloat16_t zm, + svfloat16x2_t zn2, svfloat16x2_t zm2, + svfloat16x4_t zn4, svfloat16x4_t zm4, + svbfloat16_t bzm, + svbfloat16x2_t bzn2, svbfloat16x2_t bzm2, + svbfloat16x4_t bzn4, svbfloat16x4_t bzm4) + + __arm_streaming __arm_inout("za") { + // expected-error@+1 {{'svmla_single_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmla_single_za16_f16_vg1x2(slice, zn2, zm); + // expected-error@+1 {{'svmla_single_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmla_single_za16_f16_vg1x4(slice, zn4, zm); + // expected-error@+1 {{'svmls_single_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmls_single_za16_f16_vg1x2(slice, zn2, zm); + // expected-error@+1 {{'svmls_single_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmls_single_za16_f16_vg1x4(slice, zn4, zm); + // expected-error@+1 {{'svmla_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmla_za16_f16_vg1x2(slice, zn2, zm2); + // expected-error@+1 {{'svmla_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmla_za16_f16_vg1x4(slice, zn4, zm4); + // expected-error@+1 {{'svmls_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmls_za16_f16_vg1x2(slice, zn2, zm2); + // expected-error@+1 {{'svmls_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmls_za16_f16_vg1x4(slice, zn4, zm4); + // expected-error@+1 {{'svmla_lane_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmla_lane_za16_f16_vg1x2(slice, zn2, zm, 7); + // expected-error@+1 {{'svmla_lane_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmla_lane_za16_f16_vg1x4(slice, zn4, zm, 7); + // expected-error@+1 {{'svmls_lane_za16_f16_vg1x2' needs target feature sme-f16f16}} + svmls_lane_za16_f16_vg1x2(slice, zn2, zm, 7); + // expected-error@+1 {{'svmls_lane_za16_f16_vg1x4' needs target feature sme-f16f16}} + svmls_lane_za16_f16_vg1x4(slice, zn4, zm, 7); + + // expected-error@+1 {{'svmla_single_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmla_single_za16_bf16_vg1x2(slice, bzn2, bzm); + // expected-error@+1 {{'svmla_single_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmla_single_za16_bf16_vg1x4(slice, bzn4, bzm); + // expected-error@+1 {{'svmls_single_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmls_single_za16_bf16_vg1x2(slice, bzn2, bzm); + // expected-error@+1 {{'svmls_single_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmls_single_za16_bf16_vg1x4(slice, bzn4, bzm); + // expected-error@+1 {{'svmla_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmla_za16_bf16_vg1x2(slice, bzn2, bzm2); + // expected-error@+1 {{'svmla_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmla_za16_bf16_vg1x4(slice, bzn4, bzm4); + // expected-error@+1 {{'svmls_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmls_za16_bf16_vg1x2(slice, bzn2, bzm2); + // expected-error@+1 {{'svmls_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmls_za16_bf16_vg1x4(slice, bzn4, bzm4); + // expected-error@+1 {{'svmla_lane_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmla_lane_za16_bf16_vg1x2(slice, bzn2, bzm, 7); + // expected-error@+1 {{'svmla_lane_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmla_lane_za16_bf16_vg1x4(slice, bzn4, bzm, 7); + // expected-error@+1 {{'svmls_lane_za16_bf16_vg1x2' needs target feature sme2,b16b16}} + svmls_lane_za16_bf16_vg1x2(slice, bzn2, bzm, 7); + // expected-error@+1 {{'svmls_lane_za16_bf16_vg1x4' needs target feature sme2,b16b16}} + svmls_lane_za16_bf16_vg1x4(slice, bzn4, bzm, 7); +} + + +void test_imm(uint32_t slice, svfloat16_t zm, svfloat16x2_t zn2,svfloat16x4_t zn4, + svbfloat16_t bzm, svbfloat16x2_t bzn2, svbfloat16x4_t bzn4) + __arm_streaming __arm_inout("za") { + + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_f16_vg1x2(slice, zn2, zm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_f16_vg1x4(slice, zn4, zm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_f16_vg1x2(slice, zn2, zm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_f16_vg1x4(slice, zn4, zm, -1); + + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_bf16_vg1x2(slice, bzn2, bzm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmla_lane_za16_bf16_vg1x4(slice, bzn4, bzm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_bf16_vg1x2(slice, bzn2, bzm, -1); + // expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 7]}} + svmls_lane_za16_bf16_vg1x4(slice, bzn4, bzm, -1); +} \ No newline at end of file diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 574178c8d524..a2e8c530c1df 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -797,22 +797,20 @@ defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16 defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; defm FSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fsub", 0b0101, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; -} -let Predicates = [HasSMEF16F16] in { -defm FMLA_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmla", 0b00, 0b100, ZZ_h_mul_r, ZPR4b16>; -defm FMLA_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmla", 0b000, ZZZZ_h_mul_r, ZPR4b16>; -defm FMLA_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmla", 0b0011100, MatrixOp16, ZZ_h, ZPR4b16>; -defm FMLA_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmla", 0b0111100, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm FMLA_VG2_M2Z4Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmla", 0b0100001, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; -defm FMLA_VG4_M4Z4Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmla", 0b0100001, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; - -defm FMLS_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmls", 0b00, 0b101, ZZ_h_mul_r, ZPR4b16>; -defm FMLS_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmls", 0b001, ZZZZ_h_mul_r, ZPR4b16>; -defm FMLS_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmls", 0b0011101, MatrixOp16, ZZ_h, ZPR4b16>; -defm FMLS_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmls", 0b0111101, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm FMLS_VG2_M2Z2Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmls", 0b0100011, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; -defm FMLS_VG4_M4Z2Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; +defm FMLA_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmla", 0b00, 0b100, ZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_lane_vg1x2>; +defm FMLA_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmla", 0b000, ZZZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_lane_vg1x4>; +defm FMLA_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg2_single<"fmla", 0b0011100, MatrixOp16, ZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_single_vg1x2>; +defm FMLA_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg4_single<"fmla", 0b0111100, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmla_single_vg1x4>; +defm FMLA_VG2_M2Z4Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmla", 0b0100001, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmla_vg1x2>; +defm FMLA_VG4_M4Z4Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmla", 0b0100001, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmla_vg1x4>; + +defm FMLS_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmls", 0b00, 0b101, ZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_lane_vg1x2>; +defm FMLS_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmls", 0b001, ZZZZ_h_mul_r, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_lane_vg1x4>; +defm FMLS_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg2_single<"fmls", 0b0011101, MatrixOp16, ZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_single_vg1x2>; +defm FMLS_VG4_M4ZZ_H : sme2_dot_mla_add_sub_array_vg4_single<"fmls", 0b0111101, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8f16, int_aarch64_sme_fmls_single_vg1x4>; +defm FMLS_VG2_M2Z2Z_H : sme2_dot_mla_add_sub_array_vg2_multi<"fmls", 0b0100011, MatrixOp16, ZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmls_vg1x2>; +defm FMLS_VG4_M4Z2Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, int_aarch64_sme_fmls_vg1x4>; defm FCVT_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvt", 0b0>; defm FCVTL_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvtl", 0b1>; @@ -827,20 +825,19 @@ defm BFADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfadd", 0b1100, MatrixOp defm BFSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"bfsub", 0b1101, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; defm BFSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"bfsub", 0b1101, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFMLA_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmla", 0b00, 0b110, ZZ_h_mul_r, ZPR4b16>; -defm BFMLA_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmla", 0b010, ZZZZ_h_mul_r, ZPR4b16>; -defm BFMLA_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmla", 0b1011100, MatrixOp16, ZZ_h, ZPR4b16>; -defm BFMLA_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmla", 0b1111100, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm BFMLA_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmla", 0b1100001, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFMLA_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmla", 0b1100001, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; - -defm BFMLS_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmls", 0b00, 0b111, ZZ_h_mul_r, ZPR4b16>; -defm BFMLS_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmls", 0b011, ZZZZ_h_mul_r, ZPR4b16>; -defm BFMLS_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmls", 0b1011101, MatrixOp16, ZZ_h, ZPR4b16>; -defm BFMLS_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg24_single<"bfmls", 0b1111101, MatrixOp16, ZZZZ_h, ZPR4b16>; -defm BFMLS_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmls", 0b1100011, MatrixOp16, ZZ_h_mul_r, nxv8bf16, null_frag>; -defm BFMLS_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmls", 0b1100011, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, null_frag>; +defm BFMLA_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmla", 0b00, 0b110, ZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_lane_vg1x2>; +defm BFMLA_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmla", 0b010, ZZZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_lane_vg1x4>; +defm BFMLA_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg2_single<"bfmla", 0b1011100, MatrixOp16, ZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_single_vg1x2>; +defm BFMLA_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg4_single<"bfmla", 0b1111100, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmla_single_vg1x4>; +defm BFMLA_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmla", 0b1100001, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmla_vg1x2>; +defm BFMLA_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmla", 0b1100001, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmla_vg1x4>; +defm BFMLS_VG2_M2ZZI : sme2p1_multi_vec_array_vg2_index_16b<"bfmls", 0b00, 0b111, ZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_lane_vg1x2>; +defm BFMLS_VG4_M4ZZI : sme2p1_multi_vec_array_vg4_index_16b<"bfmls", 0b011, ZZZZ_h_mul_r, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_lane_vg1x4>; +defm BFMLS_VG2_M2ZZ : sme2_dot_mla_add_sub_array_vg2_single<"bfmls", 0b1011101, MatrixOp16, ZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_single_vg1x2>; +defm BFMLS_VG4_M4ZZ : sme2_dot_mla_add_sub_array_vg4_single<"bfmls", 0b1111101, MatrixOp16, ZZZZ_h, ZPR4b16, nxv8bf16, int_aarch64_sme_fmls_single_vg1x4>; +defm BFMLS_VG2_M2Z2Z : sme2_dot_mla_add_sub_array_vg2_multi<"bfmls", 0b1100011, MatrixOp16, ZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmls_vg1x2>; +defm BFMLS_VG4_M4Z4Z : sme2_dot_mla_add_sub_array_vg4_multi<"bfmls", 0b1100011, MatrixOp16, ZZZZ_h_mul_r, nxv8bf16, int_aarch64_sme_fmls_vg1x4>; defm BFMAX_VG2_2ZZ : sme2p1_bf_max_min_vector_vg2_single<"bfmax", 0b0010000>; defm BFMAX_VG4_4ZZ : sme2p1_bf_max_min_vector_vg4_single<"bfmax", 0b0010000>; @@ -909,9 +906,9 @@ def LUTI4_S_4ZZT2Z : sme2_luti4_vector_vg4_strided<0b00, 0b00, "luti4">; } //[HasSME2p1, HasSME_LUTv2] let Predicates = [HasSMEF8F16] in { -defm FVDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_16b<"fvdot", 0b11, 0b110, ZZ_b_mul_r, ZPR4b8>; -defm FDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_16b<"fdot", 0b11, 0b010, ZZ_b_mul_r, ZPR4b8>; -defm FDOT_VG4_M4ZZI_BtoH : sme2p1_multi_vec_array_vg4_index_16b<"fdot", 0b100, ZZZZ_b_mul_r, ZPR4b8>; +defm FVDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_f8f16<"fvdot", 0b11, 0b110, ZZ_b_mul_r, ZPR4b8>; +defm FDOT_VG2_M2ZZI_BtoH : sme2p1_multi_vec_array_vg2_index_f8f16<"fdot", 0b11, 0b010, ZZ_b_mul_r, ZPR4b8>; +defm FDOT_VG4_M4ZZI_BtoH : sme2p1_multi_vec_array_vg4_index_f8f16<"fdot", 0b100, ZZZZ_b_mul_r, ZPR4b8>; defm FDOT_VG2_M2ZZ_BtoH : sme2_dot_mla_add_sub_array_vg24_single<"fdot", 0b0010001, MatrixOp16, ZZ_b, ZPR4b8>; defm FDOT_VG4_M4ZZ_BtoH : sme2_dot_mla_add_sub_array_vg24_single<"fdot", 0b0110001, MatrixOp16, ZZZZ_b, ZPR4b8>; // TODO: Replace nxv16i8 by nxv16f8 diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 3363aab4b093..724dd07225cd 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -2448,9 +2448,29 @@ multiclass sme2_multi_vec_array_vg2_index_32b sz, bits< } // SME2.1 multi-vec ternary indexed two registers 16-bit -// SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers multiclass sme2p1_multi_vec_array_vg2_index_16b sz, bits<3> op, - RegisterOperand multi_vector_ty, ZPRRegOp zpr_ty> { + RegisterOperand multi_vector_ty, ZPRRegOp vector_ty, + ValueType vt, SDPatternOperator intrinsic> { + def NAME : sme2_multi_vec_array_vg2_index, SMEPseudo2Instr { + bits<3> i; + let Inst{11-10} = i{2-1}; + let Inst{3} = i{0}; + } + + def _PSEUDO : sme2_za_array_2op_multi_index_pseudo; + + def : SME2_ZA_TwoOp_VG2_Multi_Index_Pat; + + def : InstAlias(NAME) MatrixOp16:$ZAda, MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, + multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexH:$i), 0>; +} + +// SME2 multi-vec indexed FP8 two-way dot product to FP16 two registers +multiclass sme2p1_multi_vec_array_vg2_index_f8f16 sz, bits<3> op, + RegisterOperand multi_vector_ty, ZPRRegOp zpr_ty> { def NAME : sme2_multi_vec_array_vg2_index { @@ -2569,10 +2589,10 @@ multiclass sme2_multi_vec_array_vg4_index_32b op, multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexS32b_timm:$i), 0>; } -// SME2.1 multi-vec ternary indexed four registers 16-bit -multiclass sme2p1_multi_vec_array_vg4_index_16b op, - RegisterOperand multi_vector_ty, - ZPRRegOp zpr_ty> { +// SME2.1 multi-vec ternary indexed four registers 16-bit (FP8) +multiclass sme2p1_multi_vec_array_vg4_index_f8f16 op, + RegisterOperand multi_vector_ty, + ZPRRegOp zpr_ty> { def NAME : sme2_multi_vec_array_vg4_index<0b0,{0b1,?,?,op,?}, MatrixOp16, multi_vector_ty, zpr_ty, VectorIndexH, mnemonic>{ @@ -2586,6 +2606,28 @@ multiclass sme2p1_multi_vec_array_vg4_index_16b op, sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, zpr_ty:$Zm, VectorIndexH:$i), 0>; } +// SME2.1 multi-vec ternary indexed four registers 16-bit +multiclass sme2p1_multi_vec_array_vg4_index_16b op, + RegisterOperand multi_vector_ty, + ZPRRegOp vector_ty, ValueType vt, + SDPatternOperator intrinsic> { + def NAME : sme2_multi_vec_array_vg4_index<0b0,{0b1,?,?,op,?}, MatrixOp16, + multi_vector_ty, vector_ty, + VectorIndexH, mnemonic>, SMEPseudo2Instr { + bits<3> i; + let Inst{11-10} = i{2-1}; + let Inst{3} = i{0}; + } + + def _PSEUDO : sme2_za_array_2op_multi_index_pseudo; + + def : SME2_ZA_TwoOp_VG4_Multi_Index_Pat; + + def : InstAlias(NAME) MatrixOp16:$ZAda, MatrixIndexGPR32Op8_11:$Rv, + sme_elm_idx0_7:$imm3, multi_vector_ty:$Zn, vector_ty:$Zm, VectorIndexH:$i), 0>; +} + // SME2 multi-vec ternary indexed four registers 64-bit class sme2_multi_vec_array_vg4_index_64b op, RegisterOperand multi_vector_ty, diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll new file mode 100644 index 000000000000..3e807b7e6338 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-fmlas16.ll @@ -0,0 +1,462 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --filter-out "// kill:.*$" --version 4 +; RUN: llc -verify-machineinstrs < %s | FileCheck %s + +target triple = "aarch64-linux" + +define void @test_fmla_f16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmla_f16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8f16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmla_f16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmla_f16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: fmla za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8f16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmls_f16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmls_f16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8f16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmls_f16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmls_f16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: fmls za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8f16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmla_f16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmla_f16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: fmla za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8f16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmls_f16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmls_f16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: fmls za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8f16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmla_f16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: fmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmla_f16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmla_f16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +define void @test_fmls_f16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: fmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8f16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmls_f16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmls_f16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8f16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +define void @test_fmla_bf16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmla_bf16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x2.nxv8bf16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmla_bf16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmla_bf16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: bfmla za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.single.vg1x4.nxv8bf16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmls_bf16_vg2_single(i32 %slice, %a0, %a1, %b) #0 { +; CHECK-LABEL: test_fmls_bf16_vg2_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h +; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h +; CHECK: ret + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 %slice, %a0, %a1, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x2.nxv8bf16(i32 %slice.7, %a0, %a1, %b) + ret void +} + +define void @test_fmls_bf16_vg4_single(i32 %slice, %a0, %a1, +; CHECK-LABEL: test_fmls_bf16_vg4_single: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h +; CHECK: bfmls za.h[w8, 7, vgx4], { z0.h - z3.h }, z4.h +; CHECK: ret + %a2, %a3, %b) #0 { + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 %slice, %a0, %a1, + %a2, %a3, %b) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.single.vg1x4.nxv8bf16(i32 %slice.7, %a0, %a1, + %a2, %a3, %b) + ret void +} + +define void @test_fmla_bf16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmla_bf16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: bfmla za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.vg1x4.nxv8bf16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmls_bf16_vg2_multi(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg2_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, { z2.h, z3.h } +; CHECK: ret + %a0, %a1, + %b0, %b1) #0 { + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b0, %b1) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b0, %b1) + ret void +} + +define void @test_fmls_bf16_vg4_multi(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg4_multi: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: bfmls za.h[w8, 7, vgx4], { z0.h - z3.h }, { z4.h - z7.h } +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) #0 { + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.vg1x4.nxv8bf16(i32 %slice.7, + %a0, %a1, + %a2, %a3, + %b0, %b1, + %b2, %b3) + ret void +} + +define void @test_fmla_bf16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: bfmla za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmla_bf16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmla_bf16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: bfmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmla.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +define void @test_fmls_bf16_vg2_index(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg2_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: bfmls za.h[w8, 7, vgx2], { z0.h, z1.h }, z2.h[7] +; CHECK: ret + %a0, %a1, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 %slice, + %a0, %a1, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x2.nxv8bf16(i32 %slice.7, + %a0, %a1, + %b, i32 7); + ret void +} + +define void @test_fmls_bf16_vg4_index(i32 %slice, +; CHECK-LABEL: test_fmls_bf16_vg4_index: +; CHECK: // %bb.0: +; CHECK: mov w8, w0 +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: bfmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z4.h[7] +; CHECK: ret + %a0, %a1, + %a2, %a3, + %b) #0 { + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + %slice.7 = add i32 %slice, 7 + call void @llvm.aarch64.sme.fmls.lane.vg1x4.nxv8bf16(i32 %slice, + %a0, %a1, + %a2, %a3, + %b, i32 7); + ret void +} + +attributes #0 = { nounwind "target-features"="+sme2p1,+sme-f16f16,+b16b16" } -- GitLab From 2e8d8155969f90b8f17634ce9a8e4541fb21dbab Mon Sep 17 00:00:00 2001 From: Graham Hunter Date: Fri, 10 May 2024 11:22:11 +0100 Subject: [PATCH 020/824] [TTI] Support scalable offsets in getScalingFactorCost (#88113) Part of the work to support vscale-relative immediates in LSR. --- llvm/include/llvm/Analysis/TargetTransformInfo.h | 6 +++--- llvm/include/llvm/Analysis/TargetTransformInfoImpl.h | 8 +++++--- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 5 +++-- llvm/lib/Analysis/TargetTransformInfo.cpp | 2 +- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp | 5 +++-- llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h | 2 +- llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp | 5 +++-- llvm/lib/Target/ARM/ARMTargetTransformInfo.h | 2 +- llvm/lib/Target/X86/X86TargetTransformInfo.cpp | 5 +++-- llvm/lib/Target/X86/X86TargetTransformInfo.h | 2 +- llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp | 6 ++++-- 11 files changed, 28 insertions(+), 20 deletions(-) diff --git a/llvm/include/llvm/Analysis/TargetTransformInfo.h b/llvm/include/llvm/Analysis/TargetTransformInfo.h index 1c76821fe5e4..f0eb83c143e2 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfo.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfo.h @@ -834,7 +834,7 @@ public: /// If the AM is not supported, it returns a negative value. /// TODO: Handle pre/postinc as well. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace = 0) const; @@ -1891,7 +1891,7 @@ public: virtual bool hasVolatileVariant(Instruction *I, unsigned AddrSpace) = 0; virtual bool prefersVectorizedAddressing() = 0; virtual InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) = 0; virtual bool LSRWithInstrQueries() = 0; @@ -2403,7 +2403,7 @@ public: return Impl.prefersVectorizedAddressing(); } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) override { return Impl.getScalingFactorCost(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, diff --git a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h index 4d5cd963e092..262ebdb3cbef 100644 --- a/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h +++ b/llvm/include/llvm/Analysis/TargetTransformInfoImpl.h @@ -32,6 +32,7 @@ class Function; /// Base class for use as a mix-in that aids implementing /// a TargetTransformInfo-compatible class. class TargetTransformInfoImplBase { + protected: typedef TargetTransformInfo TTI; @@ -326,12 +327,13 @@ public: bool prefersVectorizedAddressing() const { return true; } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { // Guess that all legal addressing mode are free. - if (isLegalAddressingMode(Ty, BaseGV, BaseOffset, HasBaseReg, Scale, - AddrSpace)) + if (isLegalAddressingMode(Ty, BaseGV, BaseOffset.getFixed(), HasBaseReg, + Scale, AddrSpace, /*I=*/nullptr, + BaseOffset.getScalable())) return 0; return -1; } diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index bcb60c656296..fa481886b268 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -404,13 +404,14 @@ public: } InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) { TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) return 0; return -1; diff --git a/llvm/lib/Analysis/TargetTransformInfo.cpp b/llvm/lib/Analysis/TargetTransformInfo.cpp index 33c899fe8899..00443ace46f7 100644 --- a/llvm/lib/Analysis/TargetTransformInfo.cpp +++ b/llvm/lib/Analysis/TargetTransformInfo.cpp @@ -531,7 +531,7 @@ bool TargetTransformInfo::prefersVectorizedAddressing() const { } InstructionCost TargetTransformInfo::getScalingFactorCost( - Type *Ty, GlobalValue *BaseGV, int64_t BaseOffset, bool HasBaseReg, + Type *Ty, GlobalValue *BaseGV, StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { InstructionCost Cost = TTIImpl->getScalingFactorCost( Ty, BaseGV, BaseOffset, HasBaseReg, Scale, AddrSpace); diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp index 4b410826f4bb..f49c73dc7951 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.cpp @@ -4183,7 +4183,7 @@ bool AArch64TTIImpl::preferPredicateOverEpilogue(TailFoldingInfo *TFI) { InstructionCost AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { // Scaling factors are not free at all. // Operands | Rt Latency @@ -4194,9 +4194,10 @@ AArch64TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, // Rt, [Xn, Wm, #imm] | TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) // Scale represents reg2 * scale, thus account for 1 if // it is not equal to 0 or 1. diff --git a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h index 678c132e6a80..2f44aaa3e26a 100644 --- a/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h +++ b/llvm/lib/Target/AArch64/AArch64TargetTransformInfo.h @@ -407,7 +407,7 @@ public: /// If the AM is supported, the return value must be >= 0. /// If the AM is not supported, it returns a negative value. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const; /// @} diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp index ee87f7f0e555..7db2e8ee7e6f 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.cpp @@ -2571,14 +2571,15 @@ bool ARMTTIImpl::preferPredicatedReductionSelect( } InstructionCost ARMTTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) { if (ST->hasFPAO()) return AM.Scale < 0 ? 1 : 0; // positive offsets execute faster diff --git a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h index 58eab45b9641..8c4b92b85688 100644 --- a/llvm/lib/Target/ARM/ARMTargetTransformInfo.h +++ b/llvm/lib/Target/ARM/ARMTargetTransformInfo.h @@ -303,7 +303,7 @@ public: /// If the AM is supported, the return value must be >= 0. /// If the AM is not supported, the return value must be negative. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const; bool maybeLoweredToCall(Instruction &I); diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp index 6b7cddc6d72e..d43480d0a012 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.cpp +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.cpp @@ -6741,7 +6741,7 @@ InstructionCost X86TTIImpl::getInterleavedMemoryOpCost( } InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const { // Scaling factors are not free at all. @@ -6764,9 +6764,10 @@ InstructionCost X86TTIImpl::getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, // vmovaps %ymm1, (%r8) can use port 2, 3, or 7. TargetLoweringBase::AddrMode AM; AM.BaseGV = BaseGV; - AM.BaseOffs = BaseOffset; + AM.BaseOffs = BaseOffset.getFixed(); AM.HasBaseReg = HasBaseReg; AM.Scale = Scale; + AM.ScalableOffset = BaseOffset.getScalable(); if (getTLI()->isLegalAddressingMode(DL, AM, Ty, AddrSpace)) // Scale represents reg2 * scale, thus account for 1 // as soon as we use a second register. diff --git a/llvm/lib/Target/X86/X86TargetTransformInfo.h b/llvm/lib/Target/X86/X86TargetTransformInfo.h index b50193074573..d720cc136b8a 100644 --- a/llvm/lib/Target/X86/X86TargetTransformInfo.h +++ b/llvm/lib/Target/X86/X86TargetTransformInfo.h @@ -253,7 +253,7 @@ public: /// If the AM is supported, the return value must be >= 0. /// If the AM is not supported, it returns a negative value. InstructionCost getScalingFactorCost(Type *Ty, GlobalValue *BaseGV, - int64_t BaseOffset, bool HasBaseReg, + StackOffset BaseOffset, bool HasBaseReg, int64_t Scale, unsigned AddrSpace) const; bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1, diff --git a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp index ec42e2d6e193..eb1904ccaff3 100644 --- a/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp +++ b/llvm/lib/Transforms/Scalar/LoopStrengthReduce.cpp @@ -1817,10 +1817,12 @@ static InstructionCost getScalingFactorCost(const TargetTransformInfo &TTI, case LSRUse::Address: { // Check the scaling factor cost with both the min and max offsets. InstructionCost ScaleCostMinOffset = TTI.getScalingFactorCost( - LU.AccessTy.MemTy, F.BaseGV, F.BaseOffset + LU.MinOffset, F.HasBaseReg, + LU.AccessTy.MemTy, F.BaseGV, + StackOffset::getFixed(F.BaseOffset + LU.MinOffset), F.HasBaseReg, F.Scale, LU.AccessTy.AddrSpace); InstructionCost ScaleCostMaxOffset = TTI.getScalingFactorCost( - LU.AccessTy.MemTy, F.BaseGV, F.BaseOffset + LU.MaxOffset, F.HasBaseReg, + LU.AccessTy.MemTy, F.BaseGV, + StackOffset::getFixed(F.BaseOffset + LU.MaxOffset), F.HasBaseReg, F.Scale, LU.AccessTy.AddrSpace); assert(ScaleCostMinOffset.isValid() && ScaleCostMaxOffset.isValid() && -- GitLab From 28767afd53353d9333b0adf6f0fafa1592092532 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 10 May 2024 11:47:13 +0100 Subject: [PATCH 021/824] [LAA] Support backward dependences with non-constant distance. (#91525) Following up to 933f49248, also update the code reasoning about backwards dependences to support non-constant distances. Update the code to use the signed minimum distance instead of a constant distance This means e checked the lower bound of the dependence distance and the distance may be larger at runtime (and safe for vectorization). Whether to classify it as Unknown or Backwards depends on the vector width and LAA was updated to take TTI to get the maximum vector register width. If the minimum dependence distance is larger than the max vector width, we consider it as backwards-vectorizable. Otherwise we classify them as Unknown, so we re-try with runtime checks. PR: https://github.com/llvm/llvm-project/pull/91525 --- .../llvm/Analysis/LoopAccessAnalysis.h | 23 +- llvm/lib/Analysis/LoopAccessAnalysis.cpp | 93 ++++-- llvm/lib/Transforms/Scalar/LoopFlatten.cpp | 2 +- .../Transforms/Scalar/LoopVersioningLICM.cpp | 2 +- .../multiple-strides-rt-memory-checks.ll | 2 +- .../non-constant-distance-backward.ll | 292 ++++++++++-------- .../Transforms/Vectorize/VPlanSlpTest.cpp | 2 +- 7 files changed, 247 insertions(+), 169 deletions(-) diff --git a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h index cf998e66ee48..6ebd0fb8477a 100644 --- a/llvm/include/llvm/Analysis/LoopAccessAnalysis.h +++ b/llvm/include/llvm/Analysis/LoopAccessAnalysis.h @@ -181,8 +181,10 @@ public: const SmallVectorImpl &Instrs) const; }; - MemoryDepChecker(PredicatedScalarEvolution &PSE, const Loop *L) - : PSE(PSE), InnermostLoop(L) {} + MemoryDepChecker(PredicatedScalarEvolution &PSE, const Loop *L, + unsigned MaxTargetVectorWidthInBits) + : PSE(PSE), InnermostLoop(L), + MaxTargetVectorWidthInBits(MaxTargetVectorWidthInBits) {} /// Register the location (instructions are given increasing numbers) /// of a write access. @@ -314,6 +316,12 @@ private: /// RecordDependences is true. SmallVector Dependences; + /// The maximum width of a target's vector registers multiplied by 2 to also + /// roughly account for additional interleaving. Is used to decide if a + /// backwards dependence with non-constant stride should be classified as + /// backwards-vectorizable or unknown (triggering a runtime check). + unsigned MaxTargetVectorWidthInBits = 0; + /// Check whether there is a plausible dependence between the two /// accesses. /// @@ -575,8 +583,9 @@ private: /// PSE must be emitted in order for the results of this analysis to be valid. class LoopAccessInfo { public: - LoopAccessInfo(Loop *L, ScalarEvolution *SE, const TargetLibraryInfo *TLI, - AAResults *AA, DominatorTree *DT, LoopInfo *LI); + LoopAccessInfo(Loop *L, ScalarEvolution *SE, const TargetTransformInfo *TTI, + const TargetLibraryInfo *TLI, AAResults *AA, DominatorTree *DT, + LoopInfo *LI); /// Return true we can analyze the memory accesses in the loop and there are /// no memory dependence cycles. Note that for dependences between loads & @@ -799,12 +808,14 @@ class LoopAccessInfoManager { AAResults &AA; DominatorTree &DT; LoopInfo &LI; + TargetTransformInfo *TTI; const TargetLibraryInfo *TLI = nullptr; public: LoopAccessInfoManager(ScalarEvolution &SE, AAResults &AA, DominatorTree &DT, - LoopInfo &LI, const TargetLibraryInfo *TLI) - : SE(SE), AA(AA), DT(DT), LI(LI), TLI(TLI) {} + LoopInfo &LI, TargetTransformInfo *TTI, + const TargetLibraryInfo *TLI) + : SE(SE), AA(AA), DT(DT), LI(LI), TTI(TTI), TLI(TLI) {} const LoopAccessInfo &getInfo(Loop &L); diff --git a/llvm/lib/Analysis/LoopAccessAnalysis.cpp b/llvm/lib/Analysis/LoopAccessAnalysis.cpp index 6fc7da168b42..d071e5332440 100644 --- a/llvm/lib/Analysis/LoopAccessAnalysis.cpp +++ b/llvm/lib/Analysis/LoopAccessAnalysis.cpp @@ -31,6 +31,7 @@ #include "llvm/Analysis/ScalarEvolution.h" #include "llvm/Analysis/ScalarEvolutionExpressions.h" #include "llvm/Analysis/TargetLibraryInfo.h" +#include "llvm/Analysis/TargetTransformInfo.h" #include "llvm/Analysis/ValueTracking.h" #include "llvm/Analysis/VectorUtils.h" #include "llvm/IR/BasicBlock.h" @@ -2122,17 +2123,24 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( return Dependence::Forward; } - if (!C) { - // TODO: FoundNonConstantDistanceDependence is used as a necessary condition - // to consider retrying with runtime checks. Historically, we did not set it - // when strides were different but there is no inherent reason to. + int64_t MinDistance = SE.getSignedRangeMin(Dist).getSExtValue(); + // Below we only handle strictly positive distances. + if (MinDistance <= 0) { FoundNonConstantDistanceDependence |= CommonStride.has_value(); - LLVM_DEBUG(dbgs() << "LAA: Dependence because of non-constant distance\n"); return Dependence::Unknown; } - if (!SE.isKnownPositive(Dist)) - return Dependence::Unknown; + if (!isa(Dist)) { + // Previously this case would be treated as Unknown, possibly setting + // FoundNonConstantDistanceDependence to force re-trying with runtime + // checks. Until the TODO below is addressed, set it here to preserve + // original behavior w.r.t. re-trying with runtime checks. + // TODO: FoundNonConstantDistanceDependence is used as a necessary + // condition to consider retrying with runtime checks. Historically, we + // did not set it when strides were different but there is no inherent + // reason to. + FoundNonConstantDistanceDependence |= CommonStride.has_value(); + } if (!HasSameSize) { LLVM_DEBUG(dbgs() << "LAA: ReadWrite-Write positive dependency with " @@ -2140,14 +2148,9 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( return Dependence::Unknown; } - // The logic below currently only supports StrideA == StrideB, i.e. there's a - // common stride. if (!CommonStride) return Dependence::Unknown; - const APInt &Val = C->getAPInt(); - int64_t Distance = Val.getSExtValue(); - // Bail out early if passed-in parameters make vectorization not feasible. unsigned ForcedFactor = (VectorizerParams::VectorizationFactor ? VectorizerParams::VectorizationFactor : 1); @@ -2172,8 +2175,8 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // | A[0] | | A[2] | | A[4] | | A[6] | | // | B[0] | | B[2] | | B[4] | // - // Distance needs for vectorizing iterations except the last iteration: - // 4 * 2 * (MinNumIter - 1). Distance needs for the last iteration: 4. + // MinDistance needs for vectorizing iterations except the last iteration: + // 4 * 2 * (MinNumIter - 1). MinDistance needs for the last iteration: 4. // So the minimum distance needed is: 4 * 2 * (MinNumIter - 1) + 4. // // If MinNumIter is 2, it is vectorizable as the minimum distance needed is @@ -2182,11 +2185,22 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // If MinNumIter is 4 (Say if a user forces the vectorization factor to be 4), // the minimum distance needed is 28, which is greater than distance. It is // not safe to do vectorization. + + // We know that Dist is positive, but it may not be constant. Use the signed + // minimum for computations below, as this ensures we compute the closest + // possible dependence distance. uint64_t MinDistanceNeeded = - TypeByteSize * (*CommonStride) * (MinNumIter - 1) + TypeByteSize; - if (MinDistanceNeeded > static_cast(Distance)) { - LLVM_DEBUG(dbgs() << "LAA: Failure because of positive distance " - << Distance << '\n'); + TypeByteSize * *CommonStride * (MinNumIter - 1) + TypeByteSize; + if (MinDistanceNeeded > static_cast(MinDistance)) { + if (!isa(Dist)) { + // For non-constant distances, we checked the lower bound of the + // dependence distance and the distance may be larger at runtime (and safe + // for vectorization). Classify it as Unknown, so we re-try with runtime + // checks. + return Dependence::Unknown; + } + LLVM_DEBUG(dbgs() << "LAA: Failure because of positive minimum distance " + << MinDistance << '\n'); return Dependence::Backward; } @@ -2215,12 +2229,13 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // is 8, which is less than 2 and forbidden vectorization, But actually // both A and B could be vectorized by 2 iterations. MinDepDistBytes = - std::min(static_cast(Distance), MinDepDistBytes); + std::min(static_cast(MinDistance), MinDepDistBytes); bool IsTrueDataDependence = (!AIsWrite && BIsWrite); uint64_t MinDepDistBytesOld = MinDepDistBytes; if (IsTrueDataDependence && EnableForwardingConflictDetection && - couldPreventStoreLoadForward(Distance, TypeByteSize)) { + isa(Dist) && + couldPreventStoreLoadForward(MinDistance, TypeByteSize)) { // Sanity check that we didn't update MinDepDistBytes when calling // couldPreventStoreLoadForward assert(MinDepDistBytes == MinDepDistBytesOld && @@ -2232,10 +2247,18 @@ MemoryDepChecker::Dependence::DepType MemoryDepChecker::isDependent( // An update to MinDepDistBytes requires an update to MaxSafeVectorWidthInBits // since there is a backwards dependency. - uint64_t MaxVF = MinDepDistBytes / (TypeByteSize * (*CommonStride)); - LLVM_DEBUG(dbgs() << "LAA: Positive distance " << Val.getSExtValue() + uint64_t MaxVF = MinDepDistBytes / (TypeByteSize * *CommonStride); + LLVM_DEBUG(dbgs() << "LAA: Positive min distance " << MinDistance << " with max VF = " << MaxVF << '\n'); + uint64_t MaxVFInBits = MaxVF * TypeByteSize * 8; + if (!isa(Dist) && MaxVFInBits < MaxTargetVectorWidthInBits) { + // For non-constant distances, we checked the lower bound of the dependence + // distance and the distance may be larger at runtime (and safe for + // vectorization). Classify it as Unknown, so we re-try with runtime checks. + return Dependence::Unknown; + } + MaxSafeVectorWidthInBits = std::min(MaxSafeVectorWidthInBits, MaxVFInBits); return Dependence::BackwardVectorizable; } @@ -3018,11 +3041,28 @@ void LoopAccessInfo::collectStridedAccess(Value *MemAccess) { } LoopAccessInfo::LoopAccessInfo(Loop *L, ScalarEvolution *SE, + const TargetTransformInfo *TTI, const TargetLibraryInfo *TLI, AAResults *AA, DominatorTree *DT, LoopInfo *LI) : PSE(std::make_unique(*SE, *L)), - PtrRtChecking(nullptr), - DepChecker(std::make_unique(*PSE, L)), TheLoop(L) { + PtrRtChecking(nullptr), TheLoop(L) { + unsigned MaxTargetVectorWidthInBits = std::numeric_limits::max(); + if (TTI) { + TypeSize FixedWidth = + TTI->getRegisterBitWidth(TargetTransformInfo::RGK_FixedWidthVector); + if (FixedWidth.isNonZero()) { + // Scale the vector width by 2 as rough estimate to also consider + // interleaving. + MaxTargetVectorWidthInBits = FixedWidth.getFixedValue() * 2; + } + + TypeSize ScalableWidth = + TTI->getRegisterBitWidth(TargetTransformInfo::RGK_ScalableVector); + if (ScalableWidth.isNonZero()) + MaxTargetVectorWidthInBits = std::numeric_limits::max(); + } + DepChecker = + std::make_unique(*PSE, L, MaxTargetVectorWidthInBits); PtrRtChecking = std::make_unique(*DepChecker, SE); if (canAnalyzeLoop()) { analyzeLoop(AA, LI, TLI, DT); @@ -3082,7 +3122,7 @@ const LoopAccessInfo &LoopAccessInfoManager::getInfo(Loop &L) { if (I.second) I.first->second = - std::make_unique(&L, &SE, TLI, &AA, &DT, &LI); + std::make_unique(&L, &SE, TTI, TLI, &AA, &DT, &LI); return *I.first->second; } @@ -3111,8 +3151,9 @@ LoopAccessInfoManager LoopAccessAnalysis::run(Function &F, auto &AA = FAM.getResult(F); auto &DT = FAM.getResult(F); auto &LI = FAM.getResult(F); + auto &TTI = FAM.getResult(F); auto &TLI = FAM.getResult(F); - return LoopAccessInfoManager(SE, AA, DT, LI, &TLI); + return LoopAccessInfoManager(SE, AA, DT, LI, &TTI, &TLI); } AnalysisKey LoopAccessAnalysis::Key; diff --git a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp index 0e9cf328f149..a7f8a22ece27 100644 --- a/llvm/lib/Transforms/Scalar/LoopFlatten.cpp +++ b/llvm/lib/Transforms/Scalar/LoopFlatten.cpp @@ -1005,7 +1005,7 @@ PreservedAnalyses LoopFlattenPass::run(LoopNest &LN, LoopAnalysisManager &LAM, // in simplified form, and also needs LCSSA. Running // this pass will simplify all loops that contain inner loops, // regardless of whether anything ends up being flattened. - LoopAccessInfoManager LAIM(AR.SE, AR.AA, AR.DT, AR.LI, nullptr); + LoopAccessInfoManager LAIM(AR.SE, AR.AA, AR.DT, AR.LI, &AR.TTI, nullptr); for (Loop *InnerLoop : LN.getLoops()) { auto *OuterLoop = InnerLoop->getParentLoop(); if (!OuterLoop) diff --git a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp index f39c24484840..663715948241 100644 --- a/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp +++ b/llvm/lib/Transforms/Scalar/LoopVersioningLICM.cpp @@ -582,7 +582,7 @@ PreservedAnalyses LoopVersioningLICMPass::run(Loop &L, LoopAnalysisManager &AM, const Function *F = L.getHeader()->getParent(); OptimizationRemarkEmitter ORE(F); - LoopAccessInfoManager LAIs(*SE, *AA, *DT, LAR.LI, nullptr); + LoopAccessInfoManager LAIs(*SE, *AA, *DT, LAR.LI, nullptr, nullptr); if (!LoopVersioningLICM(AA, SE, &ORE, LAIs, LAR.LI, &L).run(DT)) return PreservedAnalyses::all(); return getLoopPassPreservedAnalyses(); diff --git a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll index 3b4f2a170d8c..d96a6ea7c555 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll @@ -23,7 +23,7 @@ ; CHECK: function 'Test': ; CHECK: .inner: -; CHECK-NEXT: Memory dependences are safe with run-time checks +; CHECK-NEXT: Memory dependences are safe with a maximum safe vector width of 2048 bits with run-time checks ; CHECK-NEXT: Dependences: ; CHECK-NEXT: Run-time memory checks: ; CHECK: Check 0: diff --git a/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll index 5a95dcca1050..0058135a30d6 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/non-constant-distance-backward.ll @@ -1,45 +1,47 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py UTC_ARGS: --version 4 -; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck %s -; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx %s 2>&1 | FileCheck %s -; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx -mattr=+sve %s 2>&1 | FileCheck %s +; RUN: opt -passes='print' -disable-output %s 2>&1 | FileCheck --check-prefixes=COMMON,MAXLEN %s +; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx %s 2>&1 | FileCheck --check-prefixes=COMMON,VW128 %s +; RUN: opt -passes='print' -disable-output -mtriple=arm64-apple-macosx -mattr=+sve %s 2>&1 | FileCheck --check-prefixes=COMMON,MAXLEN %s ; REQUIRES: aarch64-registered-target target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +; If the dependence distance is not a constant, whether it gets identified as backwards or unknown depends on the minimum distance and the target's vector length. + define void @backward_min_distance_8(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_8' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP1]]: -; CHECK-NEXT: (Low: {(1 + %A),+,1}<%outer.header> High: {(257 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(1 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP2]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; COMMON-LABEL: 'backward_min_distance_8' +; COMMON-NEXT: loop: +; COMMON-NEXT: Memory dependences are safe with run-time checks +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Check 0: +; COMMON-NEXT: Comparing group ([[GRP1:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; COMMON-NEXT: Against group ([[GRP2:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; COMMON-NEXT: Grouped accesses: +; COMMON-NEXT: Group [[GRP1]]: +; COMMON-NEXT: (Low: {(1 + %A),+,1}<%outer.header> High: {(257 + %A),+,1}<%outer.header>) +; COMMON-NEXT: Member: {{\{\{}}(1 + %A),+,1}<%outer.header>,+,1}<%loop> +; COMMON-NEXT: Group [[GRP2]]: +; COMMON-NEXT: (Low: %A High: (256 + %A)) +; COMMON-NEXT: Member: {%A,+,1}<%loop> +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: +; COMMON-NEXT: outer.header: +; COMMON-NEXT: Report: loop is not the innermost loop +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Grouped accesses: +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: ; entry: br label %outer.header @@ -70,38 +72,38 @@ exit: } define void @backward_min_distance_120(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_120' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP3]]: -; CHECK-NEXT: (Low: {(15 + %A),+,1}<%outer.header> High: {(271 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(15 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP4]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; COMMON-LABEL: 'backward_min_distance_120' +; COMMON-NEXT: loop: +; COMMON-NEXT: Memory dependences are safe with run-time checks +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Check 0: +; COMMON-NEXT: Comparing group ([[GRP3:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; COMMON-NEXT: Against group ([[GRP4:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; COMMON-NEXT: Grouped accesses: +; COMMON-NEXT: Group [[GRP3]]: +; COMMON-NEXT: (Low: {(15 + %A),+,1}<%outer.header> High: {(271 + %A),+,1}<%outer.header>) +; COMMON-NEXT: Member: {{\{\{}}(15 + %A),+,1}<%outer.header>,+,1}<%loop> +; COMMON-NEXT: Group [[GRP4]]: +; COMMON-NEXT: (Low: %A High: (256 + %A)) +; COMMON-NEXT: Member: {%A,+,1}<%loop> +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: +; COMMON-NEXT: outer.header: +; COMMON-NEXT: Report: loop is not the innermost loop +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Grouped accesses: +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: ; entry: br label %outer.header @@ -131,41 +133,39 @@ exit: ret void } - -declare void @llvm.assume(i1) define void @backward_min_distance_128(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_128' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP5:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP6:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP5]]: -; CHECK-NEXT: (Low: {(16 + %A),+,1}<%outer.header> High: {(272 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(16 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP6]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; COMMON-LABEL: 'backward_min_distance_128' +; COMMON-NEXT: loop: +; COMMON-NEXT: Memory dependences are safe with run-time checks +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Check 0: +; COMMON-NEXT: Comparing group ([[GRP13:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; COMMON-NEXT: Against group ([[GRP14:0x[0-9a-f]+]]): +; COMMON-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; COMMON-NEXT: Grouped accesses: +; COMMON-NEXT: Group [[GRP13]]: +; COMMON-NEXT: (Low: {(16 + %A),+,1}<%outer.header> High: {(272 + %A),+,1}<%outer.header>) +; COMMON-NEXT: Member: {{\{\{}}(16 + %A),+,1}<%outer.header>,+,1}<%loop> +; COMMON-NEXT: Group [[GRP14]]: +; COMMON-NEXT: (Low: %A High: (256 + %A)) +; COMMON-NEXT: Member: {%A,+,1}<%loop> +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: +; COMMON-NEXT: outer.header: +; COMMON-NEXT: Report: loop is not the innermost loop +; COMMON-NEXT: Dependences: +; COMMON-NEXT: Run-time memory checks: +; COMMON-NEXT: Grouped accesses: +; COMMON-EMPTY: +; COMMON-NEXT: Non vectorizable stores to invariant address were not found in loop. +; COMMON-NEXT: SCEV assumptions: +; COMMON-EMPTY: +; COMMON-NEXT: Expressions re-written: ; entry: br label %outer.header @@ -196,38 +196,64 @@ exit: } define void @backward_min_distance_256(ptr %A, i64 %N) { -; CHECK-LABEL: 'backward_min_distance_256' -; CHECK-NEXT: loop: -; CHECK-NEXT: Memory dependences are safe with run-time checks -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Check 0: -; CHECK-NEXT: Comparing group ([[GRP7:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv -; CHECK-NEXT: Against group ([[GRP8:0x[0-9a-f]+]]): -; CHECK-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv -; CHECK-NEXT: Grouped accesses: -; CHECK-NEXT: Group [[GRP7]]: -; CHECK-NEXT: (Low: {(32 + %A),+,1}<%outer.header> High: {(288 + %A),+,1}<%outer.header>) -; CHECK-NEXT: Member: {{\{\{}}(32 + %A),+,1}<%outer.header>,+,1}<%loop> -; CHECK-NEXT: Group [[GRP8]]: -; CHECK-NEXT: (Low: %A High: (256 + %A)) -; CHECK-NEXT: Member: {%A,+,1}<%loop> -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: -; CHECK-NEXT: outer.header: -; CHECK-NEXT: Report: loop is not the innermost loop -; CHECK-NEXT: Dependences: -; CHECK-NEXT: Run-time memory checks: -; CHECK-NEXT: Grouped accesses: -; CHECK-EMPTY: -; CHECK-NEXT: Non vectorizable stores to invariant address were not found in loop. -; CHECK-NEXT: SCEV assumptions: -; CHECK-EMPTY: -; CHECK-NEXT: Expressions re-written: +; MAXLEN-LABEL: 'backward_min_distance_256' +; MAXLEN-NEXT: loop: +; MAXLEN-NEXT: Memory dependences are safe with run-time checks +; MAXLEN-NEXT: Dependences: +; MAXLEN-NEXT: Run-time memory checks: +; MAXLEN-NEXT: Check 0: +; MAXLEN-NEXT: Comparing group ([[GRP17:0x[0-9a-f]+]]): +; MAXLEN-NEXT: %gep.off.iv = getelementptr inbounds i8, ptr %gep.off, i64 %iv +; MAXLEN-NEXT: Against group ([[GRP18:0x[0-9a-f]+]]): +; MAXLEN-NEXT: %gep = getelementptr inbounds i8, ptr %A, i64 %iv +; MAXLEN-NEXT: Grouped accesses: +; MAXLEN-NEXT: Group [[GRP17]]: +; MAXLEN-NEXT: (Low: {(32 + %A),+,1}<%outer.header> High: {(288 + %A),+,1}<%outer.header>) +; MAXLEN-NEXT: Member: {{\{\{}}(32 + %A),+,1}<%outer.header>,+,1}<%loop> +; MAXLEN-NEXT: Group [[GRP18]]: +; MAXLEN-NEXT: (Low: %A High: (256 + %A)) +; MAXLEN-NEXT: Member: {%A,+,1}<%loop> +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Non vectorizable stores to invariant address were not found in loop. +; MAXLEN-NEXT: SCEV assumptions: +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Expressions re-written: +; MAXLEN-NEXT: outer.header: +; MAXLEN-NEXT: Report: loop is not the innermost loop +; MAXLEN-NEXT: Dependences: +; MAXLEN-NEXT: Run-time memory checks: +; MAXLEN-NEXT: Grouped accesses: +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Non vectorizable stores to invariant address were not found in loop. +; MAXLEN-NEXT: SCEV assumptions: +; MAXLEN-EMPTY: +; MAXLEN-NEXT: Expressions re-written: +; +; VW128-LABEL: 'backward_min_distance_256' +; VW128-NEXT: loop: +; VW128-NEXT: Memory dependences are safe with a maximum safe vector width of 256 bits +; VW128-NEXT: Dependences: +; VW128-NEXT: BackwardVectorizable: +; VW128-NEXT: %l = load i8, ptr %gep, align 4 -> +; VW128-NEXT: store i8 %add, ptr %gep.off.iv, align 4 +; VW128-EMPTY: +; VW128-NEXT: Run-time memory checks: +; VW128-NEXT: Grouped accesses: +; VW128-EMPTY: +; VW128-NEXT: Non vectorizable stores to invariant address were not found in loop. +; VW128-NEXT: SCEV assumptions: +; VW128-EMPTY: +; VW128-NEXT: Expressions re-written: +; VW128-NEXT: outer.header: +; VW128-NEXT: Report: loop is not the innermost loop +; VW128-NEXT: Dependences: +; VW128-NEXT: Run-time memory checks: +; VW128-NEXT: Grouped accesses: +; VW128-EMPTY: +; VW128-NEXT: Non vectorizable stores to invariant address were not found in loop. +; VW128-NEXT: SCEV assumptions: +; VW128-EMPTY: +; VW128-NEXT: Expressions re-written: ; entry: br label %outer.header diff --git a/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp b/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp index 396919763c93..910fc24455a6 100644 --- a/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp +++ b/llvm/unittests/Transforms/Vectorize/VPlanSlpTest.cpp @@ -44,7 +44,7 @@ protected: AARes.reset(new AAResults(TLI)); AARes->addAAResult(*BasicAA); PSE.reset(new PredicatedScalarEvolution(*SE, *L)); - LAI.reset(new LoopAccessInfo(L, &*SE, &TLI, &*AARes, &*DT, &*LI)); + LAI.reset(new LoopAccessInfo(L, &*SE, nullptr, &TLI, &*AARes, &*DT, &*LI)); IAI.reset(new InterleavedAccessInfo(*PSE, L, &*DT, &*LI, &*LAI)); IAI->analyzeInterleaving(false); return {Plan, *IAI}; -- GitLab From fa4e8995cb6b6281a94261bee34242a39fd9f462 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 10 May 2024 11:47:05 +0100 Subject: [PATCH 022/824] [AArch64] Make wfxt a full Extension (#90987) Before #90987 WFxT did not have an AEK_WFXT, so it was assumed to be an FMV-only extension. However it also had a SubtargetFeature. This commit combines the two. This fixes an issue where -mattr=+wfxt was ignored, but has the side effect of allowing +wfxt as an option to -march. --- llvm/lib/Target/AArch64/AArch64Features.td | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index ddc324ea14ed..755a1bdc8e23 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -90,7 +90,6 @@ def : FMVOnlyExtension<"FEAT_SVE_BF16", "sve-bf16", "+sve,+bf16,+fullfp16,+fp-ar def : FMVOnlyExtension<"FEAT_SVE_EBF16", "sve-ebf16", "+sve,+bf16,+fullfp16,+fp-armv8,+neon", 330>; def : FMVOnlyExtension<"FEAT_SVE_I8MM", "sve-i8mm", "+sve,+i8mm,+fullfp16,+fp-armv8,+neon", 340>; def : FMVOnlyExtension<"FEAT_SVE_PMULL128", "sve2-pmull128", "+sve2,+sve,+sve2-aes,+fullfp16,+fp-armv8,+neon", 390>; -def : FMVOnlyExtension<"FEAT_WFXT", "wfxt", "+wfxt", 550>; // Each SubtargetFeature which corresponds to an Arm Architecture feature should @@ -596,9 +595,9 @@ def FeatureMatMulFP64 : Extension<"f64mm", "MatMulFP64", def FeatureXS : SubtargetFeature<"xs", "HasXS", "true", "Enable Armv8.7-A limited-TLB-maintenance instruction (FEAT_XS)">; -// FIXME link with FMVExtension? -def FeatureWFxT : SubtargetFeature<"wfxt", "HasWFxT", - "true", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)">; +def FeatureWFxT : Extension<"wfxt", "WFxT", + "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [], + "FEAT_WFXT", "", 550>; def FeatureHCX : SubtargetFeature< "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; -- GitLab From 2371a6410dd83e82862e1c4dce1f7411efbe6b1c Mon Sep 17 00:00:00 2001 From: Momchil Velikov Date: Fri, 10 May 2024 11:57:08 +0100 Subject: [PATCH 023/824] [AArch64] Add intrinsics for non-widening FMOPA/FMOPS (#88105) According to the specification in https://github.com/ARM-software/acle/pull/309 this adds the intrinsics void svmopa_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); void svmops_za16[_f16]_m(uint64_t tile, svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za"); as well as the corresponding `bf16` variants. --- clang/include/clang/Basic/arm_sme.td | 24 +++++ .../acle_sme2_mopa_nonwide.c | 97 +++++++++++++++++++ .../acle_sme2_mopa_nonwide.c | 34 +++++++ llvm/include/llvm/IR/IntrinsicsAArch64.td | 3 + .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 10 +- llvm/lib/Target/AArch64/SMEInstrFormats.td | 16 ++- .../CodeGen/AArch64/sme2-intrinsics-mopa.ll | 42 ++++++++ 7 files changed, 219 insertions(+), 7 deletions(-) create mode 100644 clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c create mode 100644 clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c create mode 100644 llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll diff --git a/clang/include/clang/Basic/arm_sme.td b/clang/include/clang/Basic/arm_sme.td index 77ea53fb83fa..7808ee559932 100644 --- a/clang/include/clang/Basic/arm_sme.td +++ b/clang/include/clang/Basic/arm_sme.td @@ -708,3 +708,27 @@ let TargetGuard = "sme2" in { def SVLUTI2_LANE_ZT_X2 : Inst<"svluti2_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti2_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_7>]>; def SVLUTI4_LANE_ZT_X2 : Inst<"svluti4_lane_zt_{d}_x2", "2.di[i", "cUcsUsiUibhf", MergeNone, "aarch64_sme_luti4_lane_zt_x2", [IsStreaming, IsInZT0], [ImmCheck<0, ImmCheck0_0>, ImmCheck<2, ImmCheck0_3>]>; } + +//////////////////////////////////////////////////////////////////////////////// +// SME2p1 - FMOPA, FMOPS (non-widening) +let TargetGuard = "sme2,b16b16" in { + def SVMOPA_BF16_NW : SInst<"svmopa_za16[_bf16]_m", "viPPdd", "b", + MergeNone, "aarch64_sme_mopa", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; + def SVMOPS_BF16_NW : SInst<"svmops_za16[_bf16]_m", "viPPdd", "b", + MergeNone, "aarch64_sme_mops", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; +} + +let TargetGuard = "sme-f16f16" in { + def SVMOPA_F16_NW : SInst<"svmopa_za16[_f16]_m", "viPPdd", "h", + MergeNone, "aarch64_sme_mopa", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; + def SVMOPS_F16_NW : SInst<"svmops_za16[_f16]_m", "viPPdd", "h", + MergeNone, "aarch64_sme_mops", + [IsStreaming, IsInOutZA], + [ImmCheck<0, ImmCheck0_1>]>; +} diff --git a/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c new file mode 100644 index 000000000000..626bb6d3cf6f --- /dev/null +++ b/clang/test/CodeGen/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c @@ -0,0 +1,97 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 4 +// RUN: %clang_cc1 -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK +// RUN: %clang_cc1 -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK-CXX +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -O2 -Werror -emit-llvm -o - %s | FileCheck %s -check-prefixes=CHECK-CXX + +// RUN: %clang_cc1 -DSME_OVERLOADED_FORMS -x c++ -fclang-abi-compat=latest -triple aarch64-none-linux-gnu -target-feature +sme2p1 -target-feature +b16b16 -target-feature +sme-f16f16 -S -O2 -Werror -o /dev/null %s + +// REQUIRES: aarch64-registered-target + +#include + +#ifdef SME_OVERLOADED_FORMS +#define SME_ACLE_FUNC(A1,A2_UNUSED,A3) A1##A3 +#else +#define SME_ACLE_FUNC(A1,A2,A3) A1##A2##A3 +#endif + +// CHECK-LABEL: define dso_local void @test_svmopa_za16_bf16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmopa_za16_bf16u10__SVBool_tS_u14__SVBfloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0:[0-9]+]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmopa_za16_bf16(svbool_t pn, svbool_t pm, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmopa_za16, _bf16, _m)(0, pn, pm, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmops_za16_bf16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z21test_svmops_za16_bf16u10__SVBool_tS_u14__SVBfloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8bf16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmops_za16_bf16(svbool_t pn, svbool_t pm, svbfloat16_t zn, svbfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmops_za16, _bf16, _m)(0, pn, pm, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmopa_za16_f16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmopa_za16_f16u10__SVBool_tS_u13__SVFloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mopa.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmopa_za16_f16(svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmopa_za16, _f16, _m)(0, pn, pm, zn, zm); +} + +// CHECK-LABEL: define dso_local void @test_svmops_za16_f16( +// CHECK-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-NEXT: entry: +// CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-NEXT: ret void +// +// CHECK-CXX-LABEL: define dso_local void @_Z20test_svmops_za16_f16u10__SVBool_tS_u13__SVFloat16_tS0_( +// CHECK-CXX-SAME: [[PN:%.*]], [[PM:%.*]], [[ZN:%.*]], [[ZM:%.*]]) local_unnamed_addr #[[ATTR0]] { +// CHECK-CXX-NEXT: entry: +// CHECK-CXX-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PN]]) +// CHECK-CXX-NEXT: [[TMP1:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PM]]) +// CHECK-CXX-NEXT: tail call void @llvm.aarch64.sme.mops.nxv8f16(i32 0, [[TMP0]], [[TMP1]], [[ZN]], [[ZM]]) +// CHECK-CXX-NEXT: ret void +// +void test_svmops_za16_f16(svbool_t pn, svbool_t pm, svfloat16_t zn, svfloat16_t zm) __arm_streaming __arm_inout("za") { + SME_ACLE_FUNC(svmops_za16, _f16, _m)(0, pn, pm, zn, zm); +} diff --git a/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c new file mode 100644 index 000000000000..201ad4b8ff7f --- /dev/null +++ b/clang/test/Sema/aarch64-sme2-intrinsics/acle_sme2_mopa_nonwide.c @@ -0,0 +1,34 @@ +// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sme -verify -emit-llvm %s + +// REQUIRES: aarch64-registered-target + +#include + +void test_features(svbool_t pn, svbool_t pm, + svfloat16_t zn, svfloat16_t zm, + svbfloat16_t znb, svbfloat16_t zmb) + __arm_streaming __arm_inout("za") { +// expected-error@+1 {{'svmopa_za16_bf16_m' needs target feature sme2,b16b16}} + svmopa_za16_bf16_m(0, pn, pm, znb, zmb); +// expected-error@+1 {{'svmops_za16_bf16_m' needs target feature sme2,b16b16}} + svmops_za16_bf16_m(0, pn, pm, znb, zmb); +// expected-error@+1 {{'svmopa_za16_f16_m' needs target feature sme-f16f16}} + svmopa_za16_f16_m(0, pn, pm, zn, zm); +// expected-error@+1 {{'svmops_za16_f16_m' needs target feature sme-f16f16}} + svmops_za16_f16_m(0, pn, pm, zn, zm); +} + +void test_imm(svbool_t pn, svbool_t pm, + svfloat16_t zn, svfloat16_t zm, + svbfloat16_t znb, svbfloat16_t zmb) + __arm_streaming __arm_inout("za") { +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmopa_za16_bf16_m(-1, pn, pm, znb, zmb); +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmops_za16_bf16_m(-1, pn, pm, znb, zmb); +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmopa_za16_f16_m(-1, pn, pm, zn, zm); +// expected-error@+1 {{argument value 18446744073709551615 is outside the valid range [0, 1]}} + svmops_za16_f16_m(-1, pn, pm, zn, zm); +} + diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index e31e00a9c76f..e0630a6649dd 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -3649,3 +3649,6 @@ def int_aarch64_sve_pmov_to_pred_lane_zero : SVE2_1VectorArg_Pred_Intrinsic; def int_aarch64_sve_pmov_to_vector_lane_merging : SVE2_Pred_1VectorArgIndexed_Intrinsic; def int_aarch64_sve_pmov_to_vector_lane_zeroing : SVE2_Pred_1VectorArg_Intrinsic; + +def int_aarch64_sme_mopa_nonwide : SME_OuterProduct_Intrinsic; +def int_aarch64_sme_mops_nonwide : SME_OuterProduct_Intrinsic; diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index a2e8c530c1df..c5cbdce476ca 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -815,8 +815,8 @@ defm FMLS_VG4_M4Z2Z_H : sme2_dot_mla_add_sub_array_vg4_multi<"fmls", 0b0100011, defm FCVT_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvt", 0b0>; defm FCVTL_2ZZ_H : sme2p1_fp_cvt_vector_vg2_single<"fcvtl", 0b1>; -defm FMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmopa", 0b0, 0b0, 0b11, ZPR16>; -defm FMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmops", 0b0, 0b1, 0b11, ZPR16>; +defm FMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmopa", 0b0, 0b0, nxv8f16, int_aarch64_sme_mopa>; +defm FMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"fmops", 0b0, 0b1, nxv8f16, int_aarch64_sme_mops>; } let Predicates = [HasSME2, HasB16B16] in { @@ -862,8 +862,8 @@ defm BFMINNM_VG4_4Z2Z : sme2p1_bf_max_min_vector_vg4_multi<"bfminnm", 0b0010011 defm BFCLAMP_VG2_2ZZZ: sme2p1_bfclamp_vector_vg2_multi<"bfclamp">; defm BFCLAMP_VG4_4ZZZ: sme2p1_bfclamp_vector_vg4_multi<"bfclamp">; -defm BFMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmopa", 0b1, 0b0, 0b11, ZPR16>; -defm BFMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmops", 0b1, 0b1, 0b11, ZPR16>; +defm BFMOPA_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmopa", 0b1, 0b0, nxv8bf16, int_aarch64_sme_mopa>; +defm BFMOPS_MPPZZ_H : sme2p1_fmop_tile_fp16<"bfmops", 0b1, 0b1, nxv8bf16, int_aarch64_sme_mops>; } let Predicates = [HasSME2, HasFP8] in { @@ -925,7 +925,7 @@ defm FMLAL_VG4_M4ZZ_BtoH : sme2_fp_mla_long_array_vg4_single<"fmlal", 0b001, M defm FMLAL_VG2_M2Z2Z_BtoH : sme2_fp_mla_long_array_vg2_multi<"fmlal", 0b100, MatrixOp16, ZZ_b_mul_r, nxv16i8, null_frag>; defm FMLAL_VG4_M4Z4Z_BtoH : sme2_fp_mla_long_array_vg4_multi<"fmlal", 0b100, MatrixOp16, ZZZZ_b_mul_r, nxv16i8, null_frag>; -defm FMOPA_MPPZZ_BtoH : sme2p1_fmop_tile_fp16<"fmopa", 0b1, 0b0, 0b01, ZPR8>; +defm FMOPA_MPPZZ_BtoH : sme2p1_fmop_tile_f8f16<"fmopa", 0b1, 0b0, 0b01>; } //[HasSMEF8F16] diff --git a/llvm/lib/Target/AArch64/SMEInstrFormats.td b/llvm/lib/Target/AArch64/SMEInstrFormats.td index 724dd07225cd..50ee37b0dfeb 100644 --- a/llvm/lib/Target/AArch64/SMEInstrFormats.td +++ b/llvm/lib/Target/AArch64/SMEInstrFormats.td @@ -286,14 +286,26 @@ multiclass sme_outer_product_fp64 def : SME_ZA_Tile_TwoPred_TwoVec_Pat; } -multiclass sme2p1_fmop_tile_fp16 op, ZPRRegOp zpr_ty>{ - def NAME : sme_fp_outer_product_inst { +multiclass sme2p1_fmop_tile_f8f16 op> { + def NAME : sme_fp_outer_product_inst { bits<1> ZAda; let Inst{2-1} = 0b00; let Inst{0} = ZAda; } } +multiclass sme2p1_fmop_tile_fp16 { + def NAME : sme_fp_outer_product_inst, SMEPseudo2Instr { + bits<1> ZAda; + let Inst{2-1} = 0b00; + let Inst{0} = ZAda; + } + + def NAME # _PSEUDO : sme_outer_product_pseudo, SMEPseudo2Instr; + + def : SME_ZA_Tile_TwoPred_TwoVec_Pat; +} + class sme_int_outer_product_inst opc, bit sz, bit sme2, MatrixTileOperand za_ty, ZPRRegOp zpr_ty, string mnemonic> diff --git a/llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll b/llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll new file mode 100644 index 000000000000..fa0fd4360702 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/sme2-intrinsics-mopa.ll @@ -0,0 +1,42 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -verify-machineinstrs < %s | FileCheck %s + +target triple = "aarch64-linux" + +define void @mopa_bf16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mopa_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: bfmopa za0.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mopa.nxv8bf16(i32 0, %pn, %pm, %zn, %zm) + ret void +} + +define void @mopa_f16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mopa_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmopa za1.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mopa.nxv8f16(i32 1, %pn, %pm, %zn, %zm) + ret void +} + +define void @mops_bf16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mops_bf16: +; CHECK: // %bb.0: +; CHECK-NEXT: bfmops za0.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mops.nxv8bf16(i32 0, %pn, %pm, %zn, %zm) + ret void +} + +define void @mops_f16( %pn, %pm, %zn, %zm) #0 { +; CHECK-LABEL: mops_f16: +; CHECK: // %bb.0: +; CHECK-NEXT: fmops za1.h, p0/m, p1/m, z0.h, z1.h +; CHECK-NEXT: ret + call void @llvm.aarch64.sme.mops.nxv8f16(i32 1, %pn, %pm, %zn, %zm) + ret void +} + +attributes #0 = {nounwind "target-features" = "+sme,+sme2p1,+bf16,+sme-f16f16,+b16b16" } -- GitLab From f5e49279c01436971001e107a0a3435510b9ae98 Mon Sep 17 00:00:00 2001 From: Petar Avramovic Date: Fri, 10 May 2024 13:02:05 +0200 Subject: [PATCH 024/824] AMDGPU: fix isSafeToSink expecting exactly one predecessor (#89224) isSafeToSink needs to check if machine cycle has divergent exit branch but first it needs the MBB that contains cycle exit branch. Early-tailduplication can delete exit block created by structurize-cfg so there is still exactly one cycle exit block but the new cycle exit block can have multiple predecessors. Simplify search for MBBs that contain cycle exit branch by introducing helper method getExitingBlocks in GenericCycle. Fixes #89200 --- llvm/include/llvm/ADT/GenericCycleImpl.h | 15 +++ llvm/include/llvm/ADT/GenericCycleInfo.h | 4 + llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 12 +-- .../AMDGPU/GlobalISel/is-safe-to-sink-bug.ll | 93 +++++++++++++++++++ 4 files changed, 117 insertions(+), 7 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll diff --git a/llvm/include/llvm/ADT/GenericCycleImpl.h b/llvm/include/llvm/ADT/GenericCycleImpl.h index 74faff98b903..ab9c421a4469 100644 --- a/llvm/include/llvm/ADT/GenericCycleImpl.h +++ b/llvm/include/llvm/ADT/GenericCycleImpl.h @@ -66,6 +66,21 @@ void GenericCycle::getExitBlocks( } } +template +void GenericCycle::getExitingBlocks( + SmallVectorImpl &TmpStorage) const { + TmpStorage.clear(); + + for (BlockT *Block : blocks()) { + for (BlockT *Succ : successors(Block)) { + if (!contains(Succ)) { + TmpStorage.push_back(Block); + break; + } + } + } +} + template auto GenericCycle::getCyclePreheader() const -> BlockT * { BlockT *Predecessor = getCyclePredecessor(); diff --git a/llvm/include/llvm/ADT/GenericCycleInfo.h b/llvm/include/llvm/ADT/GenericCycleInfo.h index 83c4c2759d46..b601fc9bae38 100644 --- a/llvm/include/llvm/ADT/GenericCycleInfo.h +++ b/llvm/include/llvm/ADT/GenericCycleInfo.h @@ -126,6 +126,10 @@ public: /// branched to. void getExitBlocks(SmallVectorImpl &TmpStorage) const; + /// Return all blocks of this cycle that have successor outside of this cycle. + /// These blocks have cycle exit branch. + void getExitingBlocks(SmallVectorImpl &TmpStorage) const; + /// Return the preheader block for this cycle. Pre-header is well-defined for /// reducible cycle in docs/LoopTerminology.rst as: the only one entering /// block and its only edge is to the entry block. Return null for irreducible diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index 6599d0abd135..08351c49b223 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -213,15 +213,13 @@ bool SIInstrInfo::isSafeToSink(MachineInstr &MI, // Check if there is a FromCycle that contains SgprDef's basic block but // does not contain SuccToSinkTo and also has divergent exit condition. while (FromCycle && !FromCycle->contains(ToCycle)) { - // After structurize-cfg, there should be exactly one cycle exit. - SmallVector ExitBlocks; - FromCycle->getExitBlocks(ExitBlocks); - assert(ExitBlocks.size() == 1); - assert(ExitBlocks[0]->getSinglePredecessor()); + SmallVector ExitingBlocks; + FromCycle->getExitingBlocks(ExitingBlocks); // FromCycle has divergent exit condition. - if (hasDivergentBranch(ExitBlocks[0]->getSinglePredecessor())) { - return false; + for (MachineBasicBlock *ExitingBlock : ExitingBlocks) { + if (hasDivergentBranch(ExitingBlock)) + return false; } FromCycle = FromCycle->getParentCycle(); diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll new file mode 100644 index 000000000000..d3bc661f5940 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/is-safe-to-sink-bug.ll @@ -0,0 +1,93 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=amdgcn -mcpu=gfx1030 -global-isel -verify-machineinstrs < %s | FileCheck %s + +; early-tailduplication deletes cycle exit block created by structurize-cfg +; that had exactly one predecessor. Now, new cycle exit block has two +; predecessors, we need to find predecessor that belongs to the cycle. + +define amdgpu_ps void @_amdgpu_ps_main(i1 %arg) { +; CHECK-LABEL: _amdgpu_ps_main: +; CHECK: ; %bb.0: ; %bb +; CHECK-NEXT: s_mov_b32 s4, 0 +; CHECK-NEXT: v_and_b32_e32 v0, 1, v0 +; CHECK-NEXT: s_mov_b32 s5, s4 +; CHECK-NEXT: s_mov_b32 s6, s4 +; CHECK-NEXT: s_mov_b32 s7, s4 +; CHECK-NEXT: s_mov_b32 s8, SCRATCH_RSRC_DWORD0 +; CHECK-NEXT: s_buffer_load_dword s1, s[4:7], 0x0 +; CHECK-NEXT: s_mov_b32 s9, SCRATCH_RSRC_DWORD1 +; CHECK-NEXT: s_mov_b32 s10, -1 +; CHECK-NEXT: s_mov_b32 s11, 0x31c16000 +; CHECK-NEXT: s_add_u32 s8, s8, s0 +; CHECK-NEXT: v_cmp_ne_u32_e64 s0, 0, v0 +; CHECK-NEXT: s_addc_u32 s9, s9, 0 +; CHECK-NEXT: s_mov_b32 s32, 0 +; CHECK-NEXT: s_waitcnt lgkmcnt(0) +; CHECK-NEXT: s_cmp_ge_i32 s1, 0 +; CHECK-NEXT: s_cbranch_scc0 .LBB0_2 +; CHECK-NEXT: .LBB0_1: ; %bb12 +; CHECK-NEXT: v_cndmask_b32_e64 v0, 1.0, 0, s4 +; CHECK-NEXT: v_mov_b32_e32 v1, 0 +; CHECK-NEXT: v_mov_b32_e32 v2, 0 +; CHECK-NEXT: v_mov_b32_e32 v3, 0 +; CHECK-NEXT: v_mov_b32_e32 v4, 0 +; CHECK-NEXT: s_mov_b64 s[0:1], s[8:9] +; CHECK-NEXT: s_mov_b64 s[2:3], s[10:11] +; CHECK-NEXT: s_swappc_b64 s[30:31], 0 +; CHECK-NEXT: .LBB0_2: ; %bb2.preheader +; CHECK-NEXT: s_mov_b32 s1, 0 +; CHECK-NEXT: v_mov_b32_e32 v0, s1 +; CHECK-NEXT: s_branch .LBB0_4 +; CHECK-NEXT: .p2align 6 +; CHECK-NEXT: .LBB0_3: ; %bb6 +; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=1 +; CHECK-NEXT: s_or_b32 exec_lo, exec_lo, s3 +; CHECK-NEXT: s_and_b32 s2, 1, s2 +; CHECK-NEXT: v_or_b32_e32 v1, 1, v0 +; CHECK-NEXT: v_cmp_ne_u32_e64 s2, 0, s2 +; CHECK-NEXT: v_cmp_gt_i32_e32 vcc_lo, 0, v0 +; CHECK-NEXT: v_mov_b32_e32 v0, v1 +; CHECK-NEXT: s_and_b32 s4, s2, s1 +; CHECK-NEXT: s_andn2_b32 s1, s1, exec_lo +; CHECK-NEXT: s_and_b32 s2, exec_lo, s4 +; CHECK-NEXT: s_or_b32 s1, s1, s2 +; CHECK-NEXT: s_cbranch_vccz .LBB0_1 +; CHECK-NEXT: .LBB0_4: ; %bb2 +; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: s_mov_b32 s2, 0 +; CHECK-NEXT: s_and_saveexec_b32 s3, s0 +; CHECK-NEXT: s_cbranch_execz .LBB0_3 +; CHECK-NEXT: ; %bb.5: ; %bb5 +; CHECK-NEXT: ; in Loop: Header=BB0_4 Depth=1 +; CHECK-NEXT: s_mov_b32 s2, 1 +; CHECK-NEXT: s_branch .LBB0_3 +bb: + %i = call i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32> zeroinitializer, i32 0, i32 0) + %i1 = icmp slt i32 %i, 0 + br i1 %i1, label %bb2, label %bb12 + +bb2: + %i3 = phi i1 [ %i9, %bb6 ], [ false, %bb ] + %i4 = phi i32 [ %i10, %bb6 ], [ 0, %bb ] + br i1 %arg, label %bb5, label %bb6 + +bb5: + br label %bb6 + +bb6: + %i7 = phi i32 [ 0, %bb2 ], [ 1, %bb5 ] + %i8 = icmp ne i32 %i7, 0 + %i9 = select i1 %i8, i1 %i3, i1 false + %i10 = or i32 %i4, 1 + %i11 = icmp slt i32 %i4, 0 + br i1 %i11, label %bb2, label %bb12 + +bb12: + %i13 = phi i1 [ false, %bb ], [ %i9, %bb6 ] + %i14 = select i1 %i13, float 0.000000e+00, float 1.000000e+00 + %i15 = insertelement <4 x float> zeroinitializer, float %i14, i64 0 + call amdgpu_gfx addrspace(4) void null(<4 x float> %i15, i32 0) + unreachable +} + +declare i32 @llvm.amdgcn.s.buffer.load.i32(<4 x i32>, i32, i32 immarg) -- GitLab From 73681b8fee930274e6dc11d4471b44666d6d0dfd Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Fri, 10 May 2024 12:12:44 +0100 Subject: [PATCH 025/824] [NFC][LLVM] Simplify SVE isel DAG patterns. (#91510) We have many instances of (Ty ZPR:$op) than can be written as Ty:$Op. Whilst other operands can also be simplified this patch focuses on removing redundant instances of PPR, PNR and ZPR only. --- .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 624 +++++++++--------- 1 file changed, 311 insertions(+), 313 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 64e545aa26b4..d4405a230613 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -1269,33 +1269,33 @@ let Predicates = [HasSVE] in { multiclass sve_masked_gather_x2_scaled { // base + vector of scaled offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, nxv2i64:$offs)), (!cast(Inst # _SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit scaled offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32))), (!cast(Inst # _SXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit scaled offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), (!cast(Inst # _UXTW_SCALED) PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_gather_x2_unscaled { // vector of pointers + immediate offset (includes zero) - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), (i64 ImmTy:$imm), (nxv2i64 ZPR:$ptrs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, (i64 ImmTy:$imm), nxv2i64:$ptrs)), (!cast(Inst # _IMM) PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>; // base + vector of offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, nxv2i64:$offs)), (!cast(Inst) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32))), (!cast(Inst # _SXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit offsets - def : Pat<(Ty (Load (SVEDup0Undef), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))))), (!cast(Inst # _UXTW) PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_gather_x4 { - def : Pat<(Ty (Load (SVEDup0Undef), (nxv4i1 PPR:$gp), GPR64:$base, (nxv4i32 ZPR:$offs))), + def : Pat<(Ty (Load (SVEDup0Undef), nxv4i1:$gp, GPR64:$base, nxv4i32:$offs)), (Inst PPR:$gp, GPR64:$base, ZPR:$offs)>; } @@ -1503,33 +1503,33 @@ let Predicates = [HasSVE] in { multiclass sve_masked_scatter_x2_scaled { // base + vector of scaled offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, nxv2i64:$offs), (!cast(Inst # _SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit scaled offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32)), (!cast(Inst # _SXTW_SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit scaled offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), (!cast(Inst # _UXTW_SCALED) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_scatter_x2_unscaled { // vector of pointers + immediate offset (includes zero) - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), (i64 ImmTy:$imm), (nxv2i64 ZPR:$ptrs)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, (i64 ImmTy:$imm), nxv2i64:$ptrs), (!cast(Inst # _IMM) ZPR:$data, PPR:$gp, ZPR:$ptrs, ImmTy:$imm)>; // base + vector of offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (nxv2i64 ZPR:$offs)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, nxv2i64:$offs), (!cast(Inst) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of signed 32bit offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (sext_inreg (nxv2i64 ZPR:$offs), nxv2i32)), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (sext_inreg nxv2i64:$offs, nxv2i32)), (!cast(Inst # _SXTW) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; // base + vector of unsigned 32bit offsets - def : Pat<(Store (Ty ZPR:$data), (nxv2i1 PPR:$gp), GPR64:$base, (and (nxv2i64 ZPR:$offs), (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), + def : Pat<(Store Ty:$data, nxv2i1:$gp, GPR64:$base, (and nxv2i64:$offs, (nxv2i64 (splat_vector (i64 0xFFFFFFFF))))), (!cast(Inst # _UXTW) ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; } multiclass sve_masked_scatter_x4 { - def : Pat<(Store (Ty ZPR:$data), (nxv4i1 PPR:$gp), GPR64:$base, (nxv4i32 ZPR:$offs)), + def : Pat<(Store Ty:$data, nxv4i1:$gp, GPR64:$base, nxv4i32:$offs), (Inst ZPR:$data, PPR:$gp, GPR64:$base, ZPR:$offs)>; } @@ -1791,159 +1791,159 @@ let Predicates = [HasSVEorSME] in { defm TRN2_PPP : sve_int_perm_bin_perm_pp<0b101, "trn2", AArch64trn2, int_aarch64_sve_trn2_b16, int_aarch64_sve_trn2_b32, int_aarch64_sve_trn2_b64>; // Extract lo/hi halves of legal predicate types. - def : Pat<(nxv1i1 (extract_subvector (nxv2i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv2i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv1i1 (extract_subvector (nxv2i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv2i1:$Ps, (i64 1))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv2i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv2i1 (extract_subvector nxv4i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv2i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv2i1 (extract_subvector nxv4i1:$Ps, (i64 2))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv4i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv4i1 (extract_subvector nxv8i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv4i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv4i1 (extract_subvector nxv8i1:$Ps, (i64 4))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv8i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv8i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP PPR:$Ps)>; - def : Pat<(nxv8i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv8i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKHI_PP PPR:$Ps)>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 1))), (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 2))), (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv4i1 PPR:$Ps), (i64 3))), + def : Pat<(nxv1i1 (extract_subvector nxv4i1:$Ps, (i64 3))), (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 2))), (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv2i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv2i1 (extract_subvector nxv8i1:$Ps, (i64 6))), (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 4))), (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv4i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 12))), + def : Pat<(nxv4i1 (extract_subvector nxv16i1:$Ps, (i64 12))), (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 1))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 2))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 3))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 3))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 5))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 5))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 6))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv8i1 PPR:$Ps), (i64 7))), + def : Pat<(nxv1i1 (extract_subvector nxv8i1:$Ps, (i64 7))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 2))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 6))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 10))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 10))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 12))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 12))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv2i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 14))), + def : Pat<(nxv2i1 (extract_subvector nxv16i1:$Ps, (i64 14))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps)))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 0))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 0))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 1))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 1))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 2))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 2))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 3))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 3))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 4))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 4))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 5))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 5))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 6))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 6))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 7))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 7))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 8))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 8))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 9))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 9))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 10))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 10))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 11))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 11))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 12))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 12))), (PUNPKLO_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 13))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 13))), (PUNPKHI_PP (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 14))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 14))), (PUNPKLO_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; - def : Pat<(nxv1i1 (extract_subvector (nxv16i1 PPR:$Ps), (i64 15))), + def : Pat<(nxv1i1 (extract_subvector nxv16i1:$Ps, (i64 15))), (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP (PUNPKHI_PP PPR:$Ps))))>; // Extract subvectors from FP SVE vectors - def : Pat<(nxv2f16 (extract_subvector (nxv4f16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2f16 (extract_subvector nxv4f16:$Zs, (i64 0))), (UUNPKLO_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2f16 (extract_subvector (nxv4f16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2f16 (extract_subvector nxv4f16:$Zs, (i64 2))), (UUNPKHI_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv4f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv4f16 (extract_subvector nxv8f16:$Zs, (i64 0))), (UUNPKLO_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv4f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv4f16 (extract_subvector nxv8f16:$Zs, (i64 4))), (UUNPKHI_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv2f32 (extract_subvector (nxv4f32 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2f32 (extract_subvector nxv4f32:$Zs, (i64 0))), (UUNPKLO_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2f32 (extract_subvector (nxv4f32 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2f32 (extract_subvector nxv4f32:$Zs, (i64 2))), (UUNPKHI_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2bf16 (extract_subvector (nxv4bf16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2bf16 (extract_subvector nxv4bf16:$Zs, (i64 0))), (UUNPKLO_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv2bf16 (extract_subvector (nxv4bf16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2bf16 (extract_subvector nxv4bf16:$Zs, (i64 2))), (UUNPKHI_ZZ_D ZPR:$Zs)>; - def : Pat<(nxv4bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv4bf16 (extract_subvector nxv8bf16:$Zs, (i64 0))), (UUNPKLO_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv4bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv4bf16 (extract_subvector nxv8bf16:$Zs, (i64 4))), (UUNPKHI_ZZ_S ZPR:$Zs)>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 0))), (UUNPKLO_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 2))), (UUNPKHI_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 4))), (UUNPKLO_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2f16 (extract_subvector (nxv8f16 ZPR:$Zs), (i64 6))), + def : Pat<(nxv2f16 (extract_subvector nxv8f16:$Zs, (i64 6))), (UUNPKHI_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 0))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 0))), (UUNPKLO_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 2))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 2))), (UUNPKHI_ZZ_D (UUNPKLO_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 4))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 4))), (UUNPKLO_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; - def : Pat<(nxv2bf16 (extract_subvector (nxv8bf16 ZPR:$Zs), (i64 6))), + def : Pat<(nxv2bf16 (extract_subvector nxv8bf16:$Zs, (i64 6))), (UUNPKHI_ZZ_D (UUNPKHI_ZZ_S ZPR:$Zs))>; // extract/insert 64-bit fixed length vector from/into a scalable vector foreach VT = [v8i8, v4i16, v2i32, v1i64, v4f16, v2f32, v1f64, v4bf16] in { - def : Pat<(VT (vector_extract_subvec (SVEContainerVT.Value ZPR:$Zs), (i64 0))), + def : Pat<(VT (vector_extract_subvec SVEContainerVT.Value:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, dsub)>; def : Pat<(SVEContainerVT.Value (vector_insert_subvec undef, (VT V64:$src), (i64 0))), (INSERT_SUBREG (IMPLICIT_DEF), $src, dsub)>; @@ -1951,7 +1951,7 @@ let Predicates = [HasSVEorSME] in { // extract/insert 128-bit fixed length vector from/into a scalable vector foreach VT = [v16i8, v8i16, v4i32, v2i64, v8f16, v4f32, v2f64, v8bf16] in { - def : Pat<(VT (vector_extract_subvec (SVEContainerVT.Value ZPR:$Zs), (i64 0))), + def : Pat<(VT (vector_extract_subvec SVEContainerVT.Value:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, zsub)>; def : Pat<(SVEContainerVT.Value (vector_insert_subvec undef, (VT V128:$src), (i64 0))), (INSERT_SUBREG (IMPLICIT_DEF), $src, zsub)>; @@ -1980,34 +1980,34 @@ let Predicates = [HasSVEorSME] in { (UZP1_ZZZ_H $v1, $v2)>; // Splice with lane equal to -1 - def : Pat<(nxv16i8 (vector_splice (nxv16i8 ZPR:$Z1), (nxv16i8 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv16i8 (vector_splice nxv16i8:$Z1, nxv16i8:$Z2, (i64 -1))), (INSR_ZV_B ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_B (PTRUE_B 31), ZPR:$Z1), bsub))>; - def : Pat<(nxv8i16 (vector_splice (nxv8i16 ZPR:$Z1), (nxv8i16 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv8i16 (vector_splice nxv8i16:$Z1, nxv8i16:$Z2, (i64 -1))), (INSR_ZV_H ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_H (PTRUE_H 31), ZPR:$Z1), hsub))>; - def : Pat<(nxv4i32 (vector_splice (nxv4i32 ZPR:$Z1), (nxv4i32 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv4i32 (vector_splice nxv4i32:$Z1, nxv4i32:$Z2, (i64 -1))), (INSR_ZV_S ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_S (PTRUE_S 31), ZPR:$Z1), ssub))>; - def : Pat<(nxv2i64 (vector_splice (nxv2i64 ZPR:$Z1), (nxv2i64 ZPR:$Z2), (i64 -1))), + def : Pat<(nxv2i64 (vector_splice nxv2i64:$Z1, nxv2i64:$Z2, (i64 -1))), (INSR_ZV_D ZPR:$Z2, (INSERT_SUBREG (IMPLICIT_DEF), (LASTB_VPZ_D (PTRUE_D 31), ZPR:$Z1), dsub))>; // Splice with lane bigger or equal to 0 foreach VT = [nxv16i8] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_255 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_255 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; foreach VT = [nxv8i16, nxv8f16, nxv8bf16] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_127 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_127 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; foreach VT = [nxv4i32, nxv4f16, nxv4f32, nxv4bf16] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_63 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_63 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; foreach VT = [nxv2i64, nxv2f16, nxv2f32, nxv2f64, nxv2bf16] in - def : Pat<(VT (vector_splice (VT ZPR:$Z1), (VT ZPR:$Z2), (i64 (sve_ext_imm_0_31 i32:$index)))), + def : Pat<(VT (vector_splice VT:$Z1, VT:$Z2, (i64 (sve_ext_imm_0_31 i32:$index)))), (EXT_ZZI ZPR:$Z1, ZPR:$Z2, imm0_255:$index)>; defm CMPHS_PPzZZ : sve_int_cmp_0<0b000, "cmphs", SETUGE, SETULE>; @@ -2263,59 +2263,59 @@ let Predicates = [HasSVEorSME] in { defm FCVTZU_ZPmZ_DtoD : sve_fp_2op_p_zd< 0b1111111, "fcvtzu", ZPR64, ZPR64, null_frag, AArch64fcvtzu_mt, nxv2i64, nxv2i1, nxv2f64, ElementSizeD>; //These patterns exist to improve the code quality of conversions on unpacked types. - def : Pat<(nxv2f32 (AArch64fcvte_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f16 ZPR:$Zs), (nxv2f32 ZPR:$Zd))), + def : Pat<(nxv2f32 (AArch64fcvte_mt (nxv2i1 (SVEAllActive:$Pg)), nxv2f16:$Zs, nxv2f32:$Zd)), (FCVT_ZPmZ_HtoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; // FP_ROUND has an additional 'precise' flag which indicates the type of rounding. // This is ignored by the pattern below where it is matched by (i64 timm0_1) - def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive):$Pg), (nxv2f32 ZPR:$Zs), (i64 timm0_1), (nxv2f16 ZPR:$Zd))), + def : Pat<(nxv2f16 (AArch64fcvtr_mt (nxv2i1 (SVEAllActive:$Pg)), nxv2f32:$Zs, (i64 timm0_1), nxv2f16:$Zd)), (FCVT_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; // Signed integer -> Floating-point def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (nxv2f16 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i16), nxv2f16:$Zd)), (SCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv4f16 (AArch64scvtf_mt (nxv4i1 (SVEAllActive):$Pg), - (sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (nxv4f16 ZPR:$Zd))), + (sext_inreg nxv4i32:$Zs, nxv4i16), nxv4f16:$Zd)), (SCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv2f16 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f16 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i32), nxv2f16:$Zd)), (SCVTF_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv2f32 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f32 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i32), nxv2f32:$Zd)), (SCVTF_ZPmZ_StoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; def : Pat<(nxv2f64 (AArch64scvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (nxv2f64 ZPR:$Zd))), + (sext_inreg nxv2i64:$Zs, nxv2i32), nxv2f64:$Zd)), (SCVTF_ZPmZ_StoD_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; // Unsigned integer -> Floating-point - def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFF)))), (nxv2f16 ZPR:$Zd))), + def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFF)))), nxv2f16:$Zd)), (UCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), (nxv2f16 ZPR:$Zd))), + def : Pat<(nxv2f16 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), nxv2f16:$Zd)), (UCVTF_ZPmZ_StoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv4f16 (AArch64ucvtf_mt (nxv4i1 (SVEAllActive):$Pg), - (and (nxv4i32 ZPR:$Zs), - (nxv4i32 (splat_vector (i32 0xFFFF)))), (nxv4f16 ZPR:$Zd))), + def : Pat<(nxv4f16 (AArch64ucvtf_mt (nxv4i1 (SVEAllActive:$Pg)), + (and nxv4i32:$Zs, + (nxv4i32 (splat_vector (i32 0xFFFF)))), nxv4f16:$Zd)), (UCVTF_ZPmZ_HtoH_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f32 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), (nxv2f32 ZPR:$Zd))), + def : Pat<(nxv2f32 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), nxv2f32:$Zd)), (UCVTF_ZPmZ_StoS_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; - def : Pat<(nxv2f64 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive):$Pg), - (and (nxv2i64 ZPR:$Zs), - (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), (nxv2f64 ZPR:$Zd))), + def : Pat<(nxv2f64 (AArch64ucvtf_mt (nxv2i1 (SVEAllActive:$Pg)), + (and nxv2i64:$Zs, + (nxv2i64 (splat_vector (i64 0xFFFFFFFF)))), nxv2f64:$Zd)), (UCVTF_ZPmZ_StoD_UNDEF ZPR:$Zd, PPR:$Pg, ZPR:$Zs)>; defm FRINTN_ZPmZ : sve_fp_2op_p_zd_HSD<0b00000, "frintn", AArch64frintn_mt>; @@ -2510,12 +2510,12 @@ let Predicates = [HasSVEorSME] in { defm : ld1rq_pat; defm : ld1rq_pat; - def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i32), (SXTW_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i16), (SXTH_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv2i64 ZPR:$Zs), nxv2i8), (SXTB_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i16), (SXTH_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv4i32 ZPR:$Zs), nxv4i8), (SXTB_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; - def : Pat<(sext_inreg (nxv8i16 ZPR:$Zs), nxv8i8), (SXTB_ZPmZ_H_UNDEF (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv2i64:$Zs, nxv2i32), (SXTW_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv2i64:$Zs, nxv2i16), (SXTH_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv2i64:$Zs, nxv2i8), (SXTB_ZPmZ_D_UNDEF (IMPLICIT_DEF), (PTRUE_D 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv4i32:$Zs, nxv4i16), (SXTH_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv4i32:$Zs, nxv4i8), (SXTB_ZPmZ_S_UNDEF (IMPLICIT_DEF), (PTRUE_S 31), ZPR:$Zs)>; + def : Pat<(sext_inreg nxv8i16:$Zs, nxv8i8), (SXTB_ZPmZ_H_UNDEF (IMPLICIT_DEF), (PTRUE_H 31), ZPR:$Zs)>; // General case that we ideally never want to match. def : Pat<(vscale GPR64:$scale), (MADDXrrr (UBFMXri (RDVLI_XI 1), 4, 63), $scale, XZR)>; @@ -2621,109 +2621,109 @@ let Predicates = [HasSVEorSME] in { // constraint that none of the bits change when stored to memory as one // type, and reloaded as another type. let Predicates = [IsLE] in { - def : Pat<(nxv16i8 (bitconvert (nxv8i16 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv4i32 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv2i64 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv8f16 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv4f32 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv16i8 (bitconvert (nxv2f64 ZPR:$src))), (nxv16i8 ZPR:$src)>; - - def : Pat<(nxv8i16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8i16 ZPR:$src)>; - - def : Pat<(nxv4i32 (bitconvert (nxv16i8 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv8i16 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv2i64 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv8f16 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv4f32 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv2f64 ZPR:$src))), (nxv4i32 ZPR:$src)>; - - def : Pat<(nxv2i64 (bitconvert (nxv16i8 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv8i16 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv4i32 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv2f64 ZPR:$src))), (nxv2i64 ZPR:$src)>; - - def : Pat<(nxv8f16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8f16 ZPR:$src)>; - - def : Pat<(nxv4f32 (bitconvert (nxv16i8 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv8i16 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv4i32 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv2i64 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv8f16 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv2f64 ZPR:$src))), (nxv4f32 ZPR:$src)>; - - def : Pat<(nxv2f64 (bitconvert (nxv16i8 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv8i16 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv4i32 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv2i64 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv8f16 ZPR:$src))), (nxv2f64 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv4f32 ZPR:$src))), (nxv2f64 ZPR:$src)>; - - def : Pat<(nxv8bf16 (bitconvert (nxv16i8 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv8i16 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv4i32 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv2i64 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv8f16 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv4f32 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - def : Pat<(nxv8bf16 (bitconvert (nxv2f64 ZPR:$src))), (nxv8bf16 ZPR:$src)>; - - def : Pat<(nxv16i8 (bitconvert (nxv8bf16 ZPR:$src))), (nxv16i8 ZPR:$src)>; - def : Pat<(nxv8i16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8i16 ZPR:$src)>; - def : Pat<(nxv4i32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4i32 ZPR:$src)>; - def : Pat<(nxv2i64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2i64 ZPR:$src)>; - def : Pat<(nxv8f16 (bitconvert (nxv8bf16 ZPR:$src))), (nxv8f16 ZPR:$src)>; - def : Pat<(nxv4f32 (bitconvert (nxv8bf16 ZPR:$src))), (nxv4f32 ZPR:$src)>; - def : Pat<(nxv2f64 (bitconvert (nxv8bf16 ZPR:$src))), (nxv2f64 ZPR:$src)>; - - def : Pat<(nxv16i1 (bitconvert (aarch64svcount PNR:$src))), (nxv16i1 PPR:$src)>; - def : Pat<(aarch64svcount (bitconvert (nxv16i1 PPR:$src))), (aarch64svcount PNR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv8i16:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv4i32:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv2i64:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv8f16:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv4f32:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv16i8 (bitconvert nxv2f64:$src)), (nxv16i8 ZPR:$src)>; + + def : Pat<(nxv8i16 (bitconvert nxv16i8:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv4i32:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv2i64:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv8f16:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv4f32:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv2f64:$src)), (nxv8i16 ZPR:$src)>; + + def : Pat<(nxv4i32 (bitconvert nxv16i8:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv8i16:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv2i64:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv8f16:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv4f32:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv2f64:$src)), (nxv4i32 ZPR:$src)>; + + def : Pat<(nxv2i64 (bitconvert nxv16i8:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv8i16:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv4i32:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv8f16:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv4f32:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv2f64:$src)), (nxv2i64 ZPR:$src)>; + + def : Pat<(nxv8f16 (bitconvert nxv16i8:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv8i16:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv4i32:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv2i64:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv4f32:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv2f64:$src)), (nxv8f16 ZPR:$src)>; + + def : Pat<(nxv4f32 (bitconvert nxv16i8:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv8i16:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv4i32:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv2i64:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv8f16:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv2f64:$src)), (nxv4f32 ZPR:$src)>; + + def : Pat<(nxv2f64 (bitconvert nxv16i8:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv8i16:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv4i32:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv2i64:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv8f16:$src)), (nxv2f64 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv4f32:$src)), (nxv2f64 ZPR:$src)>; + + def : Pat<(nxv8bf16 (bitconvert nxv16i8:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv8i16:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv4i32:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv2i64:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv8f16:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv4f32:$src)), (nxv8bf16 ZPR:$src)>; + def : Pat<(nxv8bf16 (bitconvert nxv2f64:$src)), (nxv8bf16 ZPR:$src)>; + + def : Pat<(nxv16i8 (bitconvert nxv8bf16:$src)), (nxv16i8 ZPR:$src)>; + def : Pat<(nxv8i16 (bitconvert nxv8bf16:$src)), (nxv8i16 ZPR:$src)>; + def : Pat<(nxv4i32 (bitconvert nxv8bf16:$src)), (nxv4i32 ZPR:$src)>; + def : Pat<(nxv2i64 (bitconvert nxv8bf16:$src)), (nxv2i64 ZPR:$src)>; + def : Pat<(nxv8f16 (bitconvert nxv8bf16:$src)), (nxv8f16 ZPR:$src)>; + def : Pat<(nxv4f32 (bitconvert nxv8bf16:$src)), (nxv4f32 ZPR:$src)>; + def : Pat<(nxv2f64 (bitconvert nxv8bf16:$src)), (nxv2f64 ZPR:$src)>; + + def : Pat<(nxv16i1 (bitconvert aarch64svcount:$src)), (nxv16i1 PPR:$src)>; + def : Pat<(aarch64svcount (bitconvert nxv16i1:$src)), (aarch64svcount PNR:$src)>; } // These allow casting from/to unpacked predicate types. - def : Pat<(nxv16i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv16i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv8i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv4i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv2i1 (reinterpret_cast (nxv1i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv16i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv8i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv4i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; - def : Pat<(nxv1i1 (reinterpret_cast (nxv2i1 PPR:$src))), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv16i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv8i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv4i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv2i1 (reinterpret_cast nxv1i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv16i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv8i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv4i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; + def : Pat<(nxv1i1 (reinterpret_cast nxv2i1:$src)), (COPY_TO_REGCLASS PPR:$src, PPR)>; // These allow casting from/to unpacked floating-point types. - def : Pat<(nxv2f16 (reinterpret_cast (nxv8f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8f16 (reinterpret_cast (nxv2f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv4f16 (reinterpret_cast (nxv8f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8f16 (reinterpret_cast (nxv4f16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv2f32 (reinterpret_cast (nxv4f32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv4f32 (reinterpret_cast (nxv2f32 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv2bf16 (reinterpret_cast (nxv8bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8bf16 (reinterpret_cast (nxv2bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv4bf16 (reinterpret_cast (nxv8bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; - def : Pat<(nxv8bf16 (reinterpret_cast (nxv4bf16 ZPR:$src))), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv2f16 (reinterpret_cast nxv8f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8f16 (reinterpret_cast nxv2f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv4f16 (reinterpret_cast nxv8f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8f16 (reinterpret_cast nxv4f16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv2f32 (reinterpret_cast nxv4f32:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv4f32 (reinterpret_cast nxv2f32:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv2bf16 (reinterpret_cast nxv8bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8bf16 (reinterpret_cast nxv2bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv4bf16 (reinterpret_cast nxv8bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; + def : Pat<(nxv8bf16 (reinterpret_cast nxv4bf16:$src)), (COPY_TO_REGCLASS ZPR:$src, ZPR)>; def : Pat<(nxv16i1 (and PPR:$Ps1, PPR:$Ps2)), (AND_PPzPP (PTRUE_B 31), PPR:$Ps1, PPR:$Ps2)>; @@ -2788,14 +2788,14 @@ let Predicates = [HasSVEorSME] in { multiclass pred_store { let AddedComplexity = 1 in { - def _reg_reg : Pat<(Store (Ty ZPR:$vec), (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp)), + def _reg_reg : Pat<(Store Ty:$vec, (AddrCP GPR64:$base, GPR64:$offset), PredTy:$gp), (RegRegInst ZPR:$vec, PPR:$gp, GPR64:$base, GPR64:$offset)>; } let AddedComplexity = 2 in { - def _reg_imm : Pat<(Store (Ty ZPR:$vec), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), (PredTy PPR:$gp)), + def _reg_imm : Pat<(Store Ty:$vec, (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), PredTy:$gp), (RegImmInst ZPR:$vec, PPR:$gp, GPR64:$base, simm4s1:$offset)>; } - def _default : Pat<(Store (Ty ZPR:$vec), GPR64:$base, (PredTy PPR:$gp)), + def _default : Pat<(Store Ty:$vec, GPR64:$base, PredTy:$gp), (RegImmInst ZPR:$vec, PPR:$gp, GPR64:$base, (i64 0))>; } @@ -2840,15 +2840,15 @@ let Predicates = [HasSVEorSME] in { Instruction RegImmInst, Instruction PTrue, ComplexPattern AddrCP> { let AddedComplexity = 1 in { - def _reg : Pat<(Store (Ty ZPR:$val), (AddrCP GPR64sp:$base, GPR64:$offset)), + def _reg : Pat<(Store Ty:$val, (AddrCP GPR64sp:$base, GPR64:$offset)), (RegRegInst ZPR:$val, (PTrue 31), GPR64sp:$base, GPR64:$offset)>; } let AddedComplexity = 2 in { - def _imm : Pat<(Store (Ty ZPR:$val), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)), + def _imm : Pat<(Store Ty:$val, (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset)), (RegImmInst ZPR:$val, (PTrue 31), GPR64sp:$base, simm4s1:$offset)>; } - def : Pat<(Store (Ty ZPR:$val), GPR64:$base), + def : Pat<(Store Ty:$val, GPR64:$base), (RegImmInst ZPR:$val, (PTrue 31), GPR64:$base, (i64 0))>; } @@ -2927,7 +2927,7 @@ let Predicates = [HasSVEorSME] in { let Predicates = [IsLE] in { def : Pat<(Ty (load (am_sve_regreg_lsl0 GPR64sp:$base, GPR64:$offset))), (LD1B (PTRUE_B 31), GPR64sp:$base, GPR64:$offset)>; - def : Pat<(store (Ty ZPR:$val), (am_sve_regreg_lsl0 GPR64sp:$base, GPR64:$offset)), + def : Pat<(store Ty:$val, (am_sve_regreg_lsl0 GPR64sp:$base, GPR64:$offset)), (ST1B ZPR:$val, (PTRUE_B 31), GPR64sp:$base, GPR64:$offset)>; } } @@ -3095,18 +3095,18 @@ let Predicates = [HasSVEorSME] in { SDPatternOperator Store, ValueType PredTy, ValueType MemVT, ComplexPattern AddrCP> { // reg + reg let AddedComplexity = 1 in { - def : Pat<(Store (Ty ZPR:$vec), (AddrCP GPR64:$base, GPR64:$offset), (PredTy PPR:$gp), MemVT), + def : Pat<(Store Ty:$vec, (AddrCP GPR64:$base, GPR64:$offset), PredTy:$gp, MemVT), (RegRegInst ZPR:$vec, PPR:$gp, GPR64sp:$base, GPR64:$offset)>; } // scalar + immediate (mul vl) let AddedComplexity = 2 in { - def : Pat<(Store (Ty ZPR:$vec), (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), (PredTy PPR:$gp), MemVT), + def : Pat<(Store Ty:$vec, (am_sve_indexed_s4 GPR64sp:$base, simm4s1:$offset), PredTy:$gp, MemVT), (RegImmInst ZPR:$vec, PPR:$gp, GPR64sp:$base, simm4s1:$offset)>; } // base - def : Pat<(Store (Ty ZPR:$vec), GPR64:$base, (PredTy PPR:$gp), MemVT), + def : Pat<(Store Ty:$vec, GPR64:$base, (PredTy PPR:$gp), MemVT), (RegImmInst ZPR:$vec, PPR:$gp, GPR64:$base, (i64 0))>; } @@ -3158,44 +3158,44 @@ let Predicates = [HasSVEorSME] in { (INSERT_SUBREG (nxv2f64 (IMPLICIT_DEF)), FPR64:$src, dsub)>; // Insert scalar into vector[0] - def : Pat<(nxv16i8 (vector_insert (nxv16i8 ZPR:$vec), (i32 GPR32:$src), 0)), + def : Pat<(nxv16i8 (vector_insert nxv16i8:$vec, (i32 GPR32:$src), 0)), (CPY_ZPmR_B ZPR:$vec, (PTRUE_B 1), GPR32:$src)>; - def : Pat<(nxv8i16 (vector_insert (nxv8i16 ZPR:$vec), (i32 GPR32:$src), 0)), + def : Pat<(nxv8i16 (vector_insert nxv8i16:$vec, (i32 GPR32:$src), 0)), (CPY_ZPmR_H ZPR:$vec, (PTRUE_H 1), GPR32:$src)>; - def : Pat<(nxv4i32 (vector_insert (nxv4i32 ZPR:$vec), (i32 GPR32:$src), 0)), + def : Pat<(nxv4i32 (vector_insert nxv4i32:$vec, (i32 GPR32:$src), 0)), (CPY_ZPmR_S ZPR:$vec, (PTRUE_S 1), GPR32:$src)>; - def : Pat<(nxv2i64 (vector_insert (nxv2i64 ZPR:$vec), (i64 GPR64:$src), 0)), + def : Pat<(nxv2i64 (vector_insert nxv2i64:$vec, (i64 GPR64:$src), 0)), (CPY_ZPmR_D ZPR:$vec, (PTRUE_D 1), GPR64:$src)>; - def : Pat<(nxv8f16 (vector_insert (nxv8f16 ZPR:$vec), (f16 FPR16:$src), 0)), + def : Pat<(nxv8f16 (vector_insert nxv8f16:$vec, (f16 FPR16:$src), 0)), (SEL_ZPZZ_H (PTRUE_H 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), ZPR:$vec)>; - def : Pat<(nxv8bf16 (vector_insert (nxv8bf16 ZPR:$vec), (bf16 FPR16:$src), 0)), + def : Pat<(nxv8bf16 (vector_insert nxv8bf16:$vec, (bf16 FPR16:$src), 0)), (SEL_ZPZZ_H (PTRUE_H 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR16:$src, hsub), ZPR:$vec)>; - def : Pat<(nxv4f32 (vector_insert (nxv4f32 ZPR:$vec), (f32 FPR32:$src), 0)), + def : Pat<(nxv4f32 (vector_insert nxv4f32:$vec, (f32 FPR32:$src), 0)), (SEL_ZPZZ_S (PTRUE_S 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR32:$src, ssub), ZPR:$vec)>; - def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), 0)), + def : Pat<(nxv2f64 (vector_insert nxv2f64:$vec, (f64 FPR64:$src), 0)), (SEL_ZPZZ_D (PTRUE_D 1), (INSERT_SUBREG (IMPLICIT_DEF), FPR64:$src, dsub), ZPR:$vec)>; // Insert scalar into vector with scalar index - def : Pat<(nxv16i8 (vector_insert (nxv16i8 ZPR:$vec), GPR32:$src, GPR64:$index)), + def : Pat<(nxv16i8 (vector_insert nxv16i8:$vec, GPR32:$src, GPR64:$index)), (CPY_ZPmR_B ZPR:$vec, (CMPEQ_PPzZZ_B (PTRUE_B 31), (INDEX_II_B 0, 1), (DUP_ZR_B (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), GPR32:$src)>; - def : Pat<(nxv8i16 (vector_insert (nxv8i16 ZPR:$vec), GPR32:$src, GPR64:$index)), + def : Pat<(nxv8i16 (vector_insert nxv8i16:$vec, GPR32:$src, GPR64:$index)), (CPY_ZPmR_H ZPR:$vec, (CMPEQ_PPzZZ_H (PTRUE_H 31), (INDEX_II_H 0, 1), (DUP_ZR_H (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), GPR32:$src)>; - def : Pat<(nxv4i32 (vector_insert (nxv4i32 ZPR:$vec), GPR32:$src, GPR64:$index)), + def : Pat<(nxv4i32 (vector_insert nxv4i32:$vec, GPR32:$src, GPR64:$index)), (CPY_ZPmR_S ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), GPR32:$src)>; - def : Pat<(nxv2i64 (vector_insert (nxv2i64 ZPR:$vec), GPR64:$src, GPR64:$index)), + def : Pat<(nxv2i64 (vector_insert nxv2i64:$vec, GPR64:$src, GPR64:$index)), (CPY_ZPmR_D ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), @@ -3203,55 +3203,55 @@ let Predicates = [HasSVEorSME] in { GPR64:$src)>; // Insert FP scalar into vector with scalar index - def : Pat<(nxv2f16 (vector_insert (nxv2f16 ZPR:$vec), (f16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv2f16 (vector_insert nxv2f16:$vec, (f16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), (DUP_ZR_D GPR64:$index)), $src)>; - def : Pat<(nxv4f16 (vector_insert (nxv4f16 ZPR:$vec), (f16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv4f16 (vector_insert nxv4f16:$vec, (f16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv8f16 (vector_insert (nxv8f16 ZPR:$vec), (f16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv8f16 (vector_insert nxv8f16:$vec, (f16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_H (PTRUE_H 31), (INDEX_II_H 0, 1), (DUP_ZR_H (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv2bf16 (vector_insert (nxv2bf16 ZPR:$vec), (bf16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv2bf16 (vector_insert nxv2bf16:$vec, (bf16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), (DUP_ZR_D GPR64:$index)), $src)>; - def : Pat<(nxv4bf16 (vector_insert (nxv4bf16 ZPR:$vec), (bf16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv4bf16 (vector_insert nxv4bf16:$vec, (bf16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv8bf16 (vector_insert (nxv8bf16 ZPR:$vec), (bf16 FPR16:$src), GPR64:$index)), + def : Pat<(nxv8bf16 (vector_insert nxv8bf16:$vec, (bf16 FPR16:$src), GPR64:$index)), (CPY_ZPmV_H ZPR:$vec, (CMPEQ_PPzZZ_H (PTRUE_H 31), (INDEX_II_H 0, 1), (DUP_ZR_H (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv2f32 (vector_insert (nxv2f32 ZPR:$vec), (f32 FPR32:$src), GPR64:$index)), + def : Pat<(nxv2f32 (vector_insert nxv2f32:$vec, (f32 FPR32:$src), GPR64:$index)), (CPY_ZPmV_S ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), (DUP_ZR_D GPR64:$index)), $src) >; - def : Pat<(nxv4f32 (vector_insert (nxv4f32 ZPR:$vec), (f32 FPR32:$src), GPR64:$index)), + def : Pat<(nxv4f32 (vector_insert nxv4f32:$vec, (f32 FPR32:$src), GPR64:$index)), (CPY_ZPmV_S ZPR:$vec, (CMPEQ_PPzZZ_S (PTRUE_S 31), (INDEX_II_S 0, 1), (DUP_ZR_S (i32 (EXTRACT_SUBREG GPR64:$index, sub_32)))), $src)>; - def : Pat<(nxv2f64 (vector_insert (nxv2f64 ZPR:$vec), (f64 FPR64:$src), GPR64:$index)), + def : Pat<(nxv2f64 (vector_insert nxv2f64:$vec, (f64 FPR64:$src), GPR64:$index)), (CPY_ZPmV_D ZPR:$vec, (CMPEQ_PPzZZ_D (PTRUE_D 31), (INDEX_II_D 0, 1), @@ -3259,139 +3259,139 @@ let Predicates = [HasSVEorSME] in { $src)>; // Extract element from vector with scalar index - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), GPR64:$index)), + def : Pat<(i32 (vector_extract nxv16i8:$vec, GPR64:$index)), (LASTB_RPZ_B (WHILELS_PXX_B XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), GPR64:$index)), + def : Pat<(i32 (vector_extract nxv8i16:$vec, GPR64:$index)), (LASTB_RPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), GPR64:$index)), + def : Pat<(i32 (vector_extract nxv4i32:$vec, GPR64:$index)), (LASTB_RPZ_S (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), GPR64:$index)), + def : Pat<(i64 (vector_extract nxv2i64:$vec, GPR64:$index)), (LASTB_RPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$vec), GPR64:$index)), + def : Pat<(f16 (vector_extract nxv8f16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$vec), GPR64:$index)), + def : Pat<(f16 (vector_extract nxv4f16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$vec), GPR64:$index)), + def : Pat<(f16 (vector_extract nxv2f16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$vec), GPR64:$index)), + def : Pat<(bf16 (vector_extract nxv8bf16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_H XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$vec), GPR64:$index)), + def : Pat<(bf16 (vector_extract nxv4bf16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$vec), GPR64:$index)), + def : Pat<(bf16 (vector_extract nxv2bf16:$vec, GPR64:$index)), (LASTB_VPZ_H (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$vec), GPR64:$index)), + def : Pat<(f32 (vector_extract nxv4f32:$vec, GPR64:$index)), (LASTB_VPZ_S (WHILELS_PXX_S XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$vec), GPR64:$index)), + def : Pat<(f32 (vector_extract nxv2f32:$vec, GPR64:$index)), (LASTB_VPZ_S (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; - def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$vec), GPR64:$index)), + def : Pat<(f64 (vector_extract nxv2f64:$vec, GPR64:$index)), (LASTB_VPZ_D (WHILELS_PXX_D XZR, GPR64:$index), ZPR:$vec)>; // Extract element from vector with immediate index - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), sve_elm_idx_extdup_b:$index)), + def : Pat<(i32 (vector_extract nxv16i8:$vec, sve_elm_idx_extdup_b:$index)), (EXTRACT_SUBREG (DUP_ZZI_B ZPR:$vec, sve_elm_idx_extdup_b:$index), ssub)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), sve_elm_idx_extdup_h:$index)), + def : Pat<(i32 (vector_extract nxv8i16:$vec, sve_elm_idx_extdup_h:$index)), (EXTRACT_SUBREG (DUP_ZZI_H ZPR:$vec, sve_elm_idx_extdup_h:$index), ssub)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(i32 (vector_extract nxv4i32:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), ssub)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(i64 (vector_extract nxv2i64:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), dsub)>; - def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$vec), sve_elm_idx_extdup_h:$index)), + def : Pat<(f16 (vector_extract nxv8f16:$vec, sve_elm_idx_extdup_h:$index)), (EXTRACT_SUBREG (DUP_ZZI_H ZPR:$vec, sve_elm_idx_extdup_h:$index), hsub)>; - def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(f16 (vector_extract nxv4f16:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), hsub)>; - def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(f16 (vector_extract nxv2f16:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), hsub)>; - def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$vec), sve_elm_idx_extdup_h:$index)), + def : Pat<(bf16 (vector_extract nxv8bf16:$vec, sve_elm_idx_extdup_h:$index)), (EXTRACT_SUBREG (DUP_ZZI_H ZPR:$vec, sve_elm_idx_extdup_h:$index), hsub)>; - def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(bf16 (vector_extract nxv4bf16:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), hsub)>; - def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(bf16 (vector_extract nxv2bf16:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), hsub)>; - def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$vec), sve_elm_idx_extdup_s:$index)), + def : Pat<(f32 (vector_extract nxv4f32:$vec, sve_elm_idx_extdup_s:$index)), (EXTRACT_SUBREG (DUP_ZZI_S ZPR:$vec, sve_elm_idx_extdup_s:$index), ssub)>; - def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(f32 (vector_extract nxv2f32:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), ssub)>; - def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$vec), sve_elm_idx_extdup_d:$index)), + def : Pat<(f64 (vector_extract nxv2f64:$vec, sve_elm_idx_extdup_d:$index)), (EXTRACT_SUBREG (DUP_ZZI_D ZPR:$vec, sve_elm_idx_extdup_d:$index), dsub)>; // Extract element from vector with immediate index that's within the bottom 128-bits. let Predicates = [IsNeonAvailable], AddedComplexity = 1 in { - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index)), + def : Pat<(i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index)), (UMOVvi8 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index)), + def : Pat<(i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index)), (UMOVvi16 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index)), + def : Pat<(i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index)), (UMOVvi32 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$vec), VectorIndexD:$index)), + def : Pat<(i64 (vector_extract nxv2i64:$vec, VectorIndexD:$index)), (UMOVvi64 (v2i64 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexD:$index)>; } // End IsNeonAvailable let Predicates = [IsNeonAvailable] in { - def : Pat<(sext_inreg (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index), i8), + def : Pat<(sext_inreg (vector_extract nxv16i8:$vec, VectorIndexB:$index), i8), (SMOVvi8to32 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>; - def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv16i8 ZPR:$vec), VectorIndexB:$index))), i8), + def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv16i8:$vec, VectorIndexB:$index))), i8), (SMOVvi8to64 (v16i8 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexB:$index)>; - def : Pat<(sext_inreg (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index), i16), + def : Pat<(sext_inreg (vector_extract nxv8i16:$vec, VectorIndexH:$index), i16), (SMOVvi16to32 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; - def : Pat<(sext_inreg (anyext (i32 (vector_extract (nxv8i16 ZPR:$vec), VectorIndexH:$index))), i16), + def : Pat<(sext_inreg (anyext (i32 (vector_extract nxv8i16:$vec, VectorIndexH:$index))), i16), (SMOVvi16to64 (v8i16 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexH:$index)>; - def : Pat<(sext (i32 (vector_extract (nxv4i32 ZPR:$vec), VectorIndexS:$index))), + def : Pat<(sext (i32 (vector_extract nxv4i32:$vec, VectorIndexS:$index))), (SMOVvi32to64 (v4i32 (EXTRACT_SUBREG ZPR:$vec, zsub)), VectorIndexS:$index)>; } // End IsNeonAvailable // Extract first element from vector. let AddedComplexity = 2 in { - def : Pat<(i32 (vector_extract (nxv16i8 ZPR:$Zs), (i64 0))), + def : Pat<(i32 (vector_extract nxv16i8:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(i32 (vector_extract (nxv8i16 ZPR:$Zs), (i64 0))), + def : Pat<(i32 (vector_extract nxv8i16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(i32 (vector_extract (nxv4i32 ZPR:$Zs), (i64 0))), + def : Pat<(i32 (vector_extract nxv4i32:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(i64 (vector_extract (nxv2i64 ZPR:$Zs), (i64 0))), + def : Pat<(i64 (vector_extract nxv2i64:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, dsub)>; - def : Pat<(f16 (vector_extract (nxv8f16 ZPR:$Zs), (i64 0))), + def : Pat<(f16 (vector_extract nxv8f16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(f16 (vector_extract (nxv4f16 ZPR:$Zs), (i64 0))), + def : Pat<(f16 (vector_extract nxv4f16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(f16 (vector_extract (nxv2f16 ZPR:$Zs), (i64 0))), + def : Pat<(f16 (vector_extract nxv2f16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(bf16 (vector_extract (nxv8bf16 ZPR:$Zs), (i64 0))), + def : Pat<(bf16 (vector_extract nxv8bf16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(bf16 (vector_extract (nxv4bf16 ZPR:$Zs), (i64 0))), + def : Pat<(bf16 (vector_extract nxv4bf16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(bf16 (vector_extract (nxv2bf16 ZPR:$Zs), (i64 0))), + def : Pat<(bf16 (vector_extract nxv2bf16:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, hsub)>; - def : Pat<(f32 (vector_extract (nxv4f32 ZPR:$Zs), (i64 0))), + def : Pat<(f32 (vector_extract nxv4f32:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(f32 (vector_extract (nxv2f32 ZPR:$Zs), (i64 0))), + def : Pat<(f32 (vector_extract nxv2f32:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, ssub)>; - def : Pat<(f64 (vector_extract (nxv2f64 ZPR:$Zs), (i64 0))), + def : Pat<(f64 (vector_extract nxv2f64:$Zs, (i64 0))), (EXTRACT_SUBREG ZPR:$Zs, dsub)>; } multiclass sve_predicated_add { - def : Pat<(nxv16i8 (add ZPR:$op, (extend (nxv16i1 PPR:$pred)))), + def : Pat<(nxv16i8 (add ZPR:$op, (extend nxv16i1:$pred))), (ADD_ZPmZ_B PPR:$pred, ZPR:$op, (DUP_ZI_B value, 0))>; - def : Pat<(nxv8i16 (add ZPR:$op, (extend (nxv8i1 PPR:$pred)))), + def : Pat<(nxv8i16 (add ZPR:$op, (extend nxv8i1:$pred))), (ADD_ZPmZ_H PPR:$pred, ZPR:$op, (DUP_ZI_H value, 0))>; - def : Pat<(nxv4i32 (add ZPR:$op, (extend (nxv4i1 PPR:$pred)))), + def : Pat<(nxv4i32 (add ZPR:$op, (extend nxv4i1:$pred))), (ADD_ZPmZ_S PPR:$pred, ZPR:$op, (DUP_ZI_S value, 0))>; - def : Pat<(nxv2i64 (add ZPR:$op, (extend (nxv2i1 PPR:$pred)))), + def : Pat<(nxv2i64 (add ZPR:$op, (extend nxv2i1:$pred))), (ADD_ZPmZ_D PPR:$pred, ZPR:$op, (DUP_ZI_D value, 0))>; } defm : sve_predicated_add; defm : sve_predicated_add; - def : Pat<(nxv16i8 (sub ZPR:$op, (sext (nxv16i1 PPR:$pred)))), + def : Pat<(nxv16i8 (sub ZPR:$op, (sext nxv16i1:$pred))), (SUB_ZPmZ_B PPR:$pred, ZPR:$op, (DUP_ZI_B 255, 0))>; - def : Pat<(nxv8i16 (sub ZPR:$op, (sext (nxv8i1 PPR:$pred)))), + def : Pat<(nxv8i16 (sub ZPR:$op, (sext nxv8i1:$pred))), (SUB_ZPmZ_H PPR:$pred, ZPR:$op, (DUP_ZI_H 255, 0))>; - def : Pat<(nxv4i32 (sub ZPR:$op, (sext (nxv4i1 PPR:$pred)))), + def : Pat<(nxv4i32 (sub ZPR:$op, (sext nxv4i1:$pred))), (SUB_ZPmZ_S PPR:$pred, ZPR:$op, (DUP_ZI_S 255, 0))>; - def : Pat<(nxv2i64 (sub ZPR:$op, (sext (nxv2i1 PPR:$pred)))), + def : Pat<(nxv2i64 (sub ZPR:$op, (sext nxv2i1:$pred))), (SUB_ZPmZ_D PPR:$pred, ZPR:$op, (DUP_ZI_D 255, 0))>; } // End HasSVEorSME @@ -3995,8 +3995,7 @@ defm STNT1D_4Z_IMM : sve2p1_mem_cst_si_4z<"stnt1d", 0b11, 0b1, ZZZZ_d_mul_r>; multiclass store_pn_x2 { - def : Pat<(Store (Ty ZPR:$vec0), (Ty ZPR:$vec1), - (aarch64svcount PNR:$PNg), GPR64:$base), + def : Pat<(Store Ty:$vec0, Ty:$vec1, aarch64svcount:$PNg, GPR64:$base), (RegImmInst (REG_SEQUENCE ZPR2Mul2, Ty:$vec0, zsub0, Ty:$vec1, zsub1), PNR:$PNg, GPR64:$base, (i64 0))>; } @@ -4021,8 +4020,7 @@ defm : store_pn_x2; multiclass store_pn_x4 { - def : Pat<(Store (Ty ZPR:$vec0), (Ty ZPR:$vec1), (Ty ZPR:$vec2), (Ty ZPR:$vec3), - (aarch64svcount PNR:$PNg), GPR64:$base), + def : Pat<(Store Ty:$vec0, Ty:$vec1, Ty:$vec2, Ty:$vec3, aarch64svcount:$PNg, GPR64:$base), (RegImmInst (REG_SEQUENCE ZPR4Mul4, Ty:$vec0, zsub0, Ty:$vec1, zsub1, Ty:$vec2, zsub2, Ty:$vec3, zsub3), PNR:$PNg, GPR64:$base, (i64 0))>; -- GitLab From 5ad7a210ff850eed1f255f81f0609efedabe3bb7 Mon Sep 17 00:00:00 2001 From: Tomas Matheson Date: Fri, 10 May 2024 12:14:11 +0100 Subject: [PATCH 026/824] [AArch64] wfxt must depend on itself (#90987) --- llvm/lib/Target/AArch64/AArch64Features.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index 755a1bdc8e23..3425ac413302 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -597,7 +597,7 @@ def FeatureXS : SubtargetFeature<"xs", "HasXS", def FeatureWFxT : Extension<"wfxt", "WFxT", "Enable Armv8.7-A WFET and WFIT instruction (FEAT_WFxT)", [], - "FEAT_WFXT", "", 550>; + "FEAT_WFXT", "+wfxt", 550>; def FeatureHCX : SubtargetFeature< "hcx", "HasHCX", "true", "Enable Armv8.7-A HCRX_EL2 system register (FEAT_HCX)">; -- GitLab From f52ca632787a5d4227689726e14dae6749e1e650 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 10 May 2024 12:26:45 +0100 Subject: [PATCH 027/824] [LAA] Drop x86_64 target triple to fix test on builds with X86. Follow-up o fix test after 28767afd53353d9333b0adf6f0fafa1592092532. --- .../LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll index d96a6ea7c555..cb50b2c75ccb 100644 --- a/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll +++ b/llvm/test/Analysis/LoopAccessAnalysis/multiple-strides-rt-memory-checks.ll @@ -23,14 +23,13 @@ ; CHECK: function 'Test': ; CHECK: .inner: -; CHECK-NEXT: Memory dependences are safe with a maximum safe vector width of 2048 bits with run-time checks +; CHECK-NEXT: Memory dependences are safe with run-time checks ; CHECK-NEXT: Dependences: ; CHECK-NEXT: Run-time memory checks: ; CHECK: Check 0: ; CHECK: Check 1: target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" -target triple = "x86_64-unknown-linux-gnu" %struct.s = type { [32 x i32], [32 x i32], [32 x [32 x i32]] } -- GitLab From 200f3bd39562f4d605f13567398025d30fa27d61 Mon Sep 17 00:00:00 2001 From: Qizhi Hu <836744285@qq.com> Date: Fri, 10 May 2024 20:14:08 +0800 Subject: [PATCH 028/824] [Clang][Sema] access checking of friend declaration should not be delayed (#91430) attempt to fix https://github.com/llvm/llvm-project/issues/12361 Consider this example: ```cpp class D { class E{ class F{}; friend void foo(D::E::F& q); }; friend void foo(D::E::F& q); }; void foo(D::E::F& q) {} ``` The first friend declaration of foo is correct. After that, the second friend declaration delayed access checking and set its previous declaration to be the first one. When doing access checking of `F`(which is private filed of `E`), we put its canonical declaration(the first friend declaration) into `EffectiveContext.Functions`. Actually, we are still checking the first one. This is incorrect due to the delayed checking. Creating a new scope to indicate we are parsing a friend declaration and doing access checking in time. --- clang/docs/ReleaseNotes.rst | 1 + clang/include/clang/Sema/Scope.h | 6 ++++++ clang/lib/Parse/ParseDecl.cpp | 7 +++++-- clang/lib/Sema/Scope.cpp | 1 + clang/lib/Sema/SemaAccess.cpp | 30 +++++++++++++++++++++++++----- clang/test/SemaCXX/PR12361.cpp | 30 ++++++++++++++++++++++++++++++ 6 files changed, 68 insertions(+), 7 deletions(-) create mode 100644 clang/test/SemaCXX/PR12361.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index eef627ff2e31..7c5dcc59c701 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -706,6 +706,7 @@ Bug Fixes to C++ Support within initializers for variables that are usable in constant expressions or are constant initialized, rather than evaluating them as a part of the larger manifestly constant evaluated expression. +- Fix a bug in access control checking due to dealyed checking of friend declaration. Fixes (#GH12361). Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Sema/Scope.h b/clang/include/clang/Sema/Scope.h index 1752a25111a7..084db7303421 100644 --- a/clang/include/clang/Sema/Scope.h +++ b/clang/include/clang/Sema/Scope.h @@ -159,6 +159,9 @@ public: /// This is a scope of type alias declaration. TypeAliasScope = 0x20000000, + + /// This is a scope of friend declaration. + FriendScope = 0x40000000, }; private: @@ -586,6 +589,9 @@ public: /// Determine whether this scope is a type alias scope. bool isTypeAliasScope() const { return getFlags() & Scope::TypeAliasScope; } + /// Determine whether this scope is a friend scope. + bool isFriendScope() const { return getFlags() & Scope::FriendScope; } + /// Returns if rhs has a higher scope depth than this. /// /// The caller is responsible for calling this only if one of the two scopes diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index 2c11ae693c35..5b5fc02ad402 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -4331,9 +4331,12 @@ void Parser::ParseDeclarationSpecifiers( // friend case tok::kw_friend: - if (DSContext == DeclSpecContext::DSC_class) + if (DSContext == DeclSpecContext::DSC_class) { isInvalid = DS.SetFriendSpec(Loc, PrevSpec, DiagID); - else { + Scope *CurS = getCurScope(); + if (!isInvalid && CurS) + CurS->setFlags(CurS->getFlags() | Scope::FriendScope); + } else { PrevSpec = ""; // not actually used by the diagnostic DiagID = diag::err_friend_invalid_in_context; isInvalid = true; diff --git a/clang/lib/Sema/Scope.cpp b/clang/lib/Sema/Scope.cpp index 11a41753a1bd..c08073e80ff3 100644 --- a/clang/lib/Sema/Scope.cpp +++ b/clang/lib/Sema/Scope.cpp @@ -229,6 +229,7 @@ void Scope::dumpImpl(raw_ostream &OS) const { {ClassInheritanceScope, "ClassInheritanceScope"}, {CatchScope, "CatchScope"}, {OpenACCComputeConstructScope, "OpenACCComputeConstructScope"}, + {FriendScope, "FriendScope"}, }; for (auto Info : FlagInfo) { diff --git a/clang/lib/Sema/SemaAccess.cpp b/clang/lib/Sema/SemaAccess.cpp index 6a707eeb66d0..979a64b065f3 100644 --- a/clang/lib/Sema/SemaAccess.cpp +++ b/clang/lib/Sema/SemaAccess.cpp @@ -1473,12 +1473,32 @@ static Sema::AccessResult CheckAccess(Sema &S, SourceLocation Loc, // specifier, like this: // A::private_type A::foo() { ... } // - // Or we might be parsing something that will turn out to be a friend: - // void foo(A::private_type); - // void B::foo(A::private_type); + // friend declaration should not be delayed because it may lead to incorrect + // redeclaration chain, such as: + // class D { + // class E{ + // class F{}; + // friend void foo(D::E::F& q); + // }; + // friend void foo(D::E::F& q); + // }; if (S.DelayedDiagnostics.shouldDelayDiagnostics()) { - S.DelayedDiagnostics.add(DelayedDiagnostic::makeAccess(Loc, Entity)); - return Sema::AR_delayed; + // [class.friend]p9: + // A member nominated by a friend declaration shall be accessible in the + // class containing the friend declaration. The meaning of the friend + // declaration is the same whether the friend declaration appears in the + // private, protected, or public ([class.mem]) portion of the class + // member-specification. + Scope *TS = S.getCurScope(); + bool IsFriendDeclaration = false; + while (TS && !IsFriendDeclaration) { + IsFriendDeclaration = TS->isFriendScope(); + TS = TS->getParent(); + } + if (!IsFriendDeclaration) { + S.DelayedDiagnostics.add(DelayedDiagnostic::makeAccess(Loc, Entity)); + return Sema::AR_delayed; + } } EffectiveContext EC(S.CurContext); diff --git a/clang/test/SemaCXX/PR12361.cpp b/clang/test/SemaCXX/PR12361.cpp new file mode 100644 index 000000000000..95ceb45b7ba0 --- /dev/null +++ b/clang/test/SemaCXX/PR12361.cpp @@ -0,0 +1,30 @@ + // RUN: %clang_cc1 -fsyntax-only -verify -std=c++98 %s + // RUN: %clang_cc1 -fsyntax-only -verify -std=c++17 %s + +class D { + class E{ + class F{}; // expected-note{{implicitly declared private here}} + friend void foo(D::E::F& q); + }; + friend void foo(D::E::F& q); // expected-error{{'F' is a private member of 'D::E'}} + }; + +void foo(D::E::F& q) {} + +class D1 { + class E1{ + class F1{}; // expected-note{{implicitly declared private here}} + friend D1::E1::F1 foo1(); + }; + friend D1::E1::F1 foo1(); // expected-error{{'F1' is a private member of 'D1::E1'}} + }; + +D1::E1::F1 foo1() { return D1::E1::F1(); } + +class D2 { + class E2{ + class F2{}; + friend void foo2(); + }; + friend void foo2(){ D2::E2::F2 c;} + }; -- GitLab From 8c852ab57932a5cd954cb0d050c3d2ab486428df Mon Sep 17 00:00:00 2001 From: Younan Zhang Date: Fri, 10 May 2024 20:47:15 +0800 Subject: [PATCH 029/824] [Clang][Sema] Revise the transformation of CTAD parameters of nested class templates (#91628) This fixes a regression introduced by bee78b88f. When we form a deduction guide for a constructor, basically, we do the following work: - Collect template parameters from the constructor's surrounding class template, if present. - Collect template parameters from the constructor. - Splice these template parameters together into a new template parameter list. - Turn all the references (e.g. the function parameter list) to the invented parameter list by applying a `TreeTransform` to the function type. In the previous fix, we handled cases of nested class templates by substituting the "outer" template parameters (i.e. those not declared at the surrounding class template or the constructor) with the instantiating template arguments. The approach per se makes sense, but there was a flaw in the following case: ```cpp template struct X { template struct Y { template Y(T) {} }; template Y(T) -> Y; }; X::Y y(42); ``` While we're transforming the parameters for `Y(T)`, we first attempt to transform all references to `V` and `T`; then, we handle the references to outer parameters `U` and `Us` using the template arguments from `X` by transforming the same `ParamDecl`. However, the first step results in the reference `T` being `` because the invented `T` is the last of the parameter list of the deduction guide, and what we're substituting with is a corresponding parameter pack (which is `Us`, though empty). Hence we're messing up the substitution. I think we can resolve it by reversing the substitution order, which means handling outer template parameters first and then the inner parameters. There's no release note because this is a regression in 18, and I hope we can catch up with the last release. Fixes https://github.com/llvm/llvm-project/issues/88142 --- clang/lib/Sema/SemaTemplate.cpp | 25 ++++++++++++++----- .../nested-implicit-deduction-guides.cpp | 14 +++++++++++ 2 files changed, 33 insertions(+), 6 deletions(-) diff --git a/clang/lib/Sema/SemaTemplate.cpp b/clang/lib/Sema/SemaTemplate.cpp index 2fce2238f9c1..480c0103ae33 100644 --- a/clang/lib/Sema/SemaTemplate.cpp +++ b/clang/lib/Sema/SemaTemplate.cpp @@ -2492,9 +2492,6 @@ struct ConvertConstructorToDeductionGuideTransform { Args.addOuterRetainedLevel(); } - if (NestedPattern) - Args.addOuterRetainedLevels(NestedPattern->getTemplateDepth()); - FunctionProtoTypeLoc FPTL = CD->getTypeSourceInfo()->getTypeLoc() .getAsAdjusted(); assert(FPTL && "no prototype for constructor declaration"); @@ -2584,11 +2581,27 @@ private: // -- The types of the function parameters are those of the constructor. for (auto *OldParam : TL.getParams()) { - ParmVarDecl *NewParam = - transformFunctionTypeParam(OldParam, Args, MaterializedTypedefs); - if (NestedPattern && NewParam) + ParmVarDecl *NewParam = OldParam; + // Given + // template struct C { + // template struct D { + // template D(U, V); + // }; + // }; + // First, transform all the references to template parameters that are + // defined outside of the surrounding class template. That is T in the + // above example. + if (NestedPattern) { NewParam = transformFunctionTypeParam(NewParam, OuterInstantiationArgs, MaterializedTypedefs); + if (!NewParam) + return QualType(); + } + // Then, transform all the references to template parameters that are + // defined at the class template and the constructor. In this example, + // they're U and V, respectively. + NewParam = + transformFunctionTypeParam(NewParam, Args, MaterializedTypedefs); if (!NewParam) return QualType(); ParamTypes.push_back(NewParam->getType()); diff --git a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp index 38b6706595a1..f289dc045286 100644 --- a/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp +++ b/clang/test/SemaTemplate/nested-implicit-deduction-guides.cpp @@ -84,3 +84,17 @@ nested_init_list::concept_fail nil_invalid{1, ""}; // expected-note@#INIT_LIST_INNER_INVALID {{candidate template ignored: substitution failure [with F = const char *]: constraints not satisfied for class template 'concept_fail' [with F = const char *]}} // expected-note@#INIT_LIST_INNER_INVALID {{candidate function template not viable: requires 1 argument, but 2 were provided}} // expected-note@#INIT_LIST_INNER_INVALID {{candidate function template not viable: requires 0 arguments, but 2 were provided}} + +namespace GH88142 { + +template struct X { + template struct Y { + template Y(T) {} + }; + + template Y(T) -> Y; +}; + +X::Y y(42); + +} // namespace PR88142 -- GitLab From 452f4393c70e0ffecf8e394f82b1eaeaa8d224af Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 10 May 2024 13:47:22 +0100 Subject: [PATCH 030/824] [InstCombine] Precommit tests for #86111 The upcoming patch adds logic to prefer to use constants close to power-of-two in these ashr exact + slt/ult patterns when it has a choice on which constant can be used. --- .../Transforms/InstCombine/icmp-shr-lt-gt.ll | 61 +++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll index 1b8efe4351c6..4dd5b0925914 100644 --- a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll +++ b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll @@ -3800,3 +3800,64 @@ define i1 @ashrslt_03_15_exact(i4 %x) { ret i1 %c } +; TODO: The resulting compared constant can be safely replaced with one that +; is closer to a power of two. +define i1 @ashr_slt_exact_near_pow2_cmpval(i8 %x) { +; CHECK-LABEL: @ashr_slt_exact_near_pow2_cmpval( +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp slt i8 %s, 5 + ret i1 %c +} + +define i1 @ashr_ult_exact_near_pow2_cmpval(i8 %x) { +; CHECK-LABEL: @ashr_ult_exact_near_pow2_cmpval( +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp ult i8 %s, 5 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_ashr_slt_noexact(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_ashr_slt_noexact( +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr i8 %x, 1 + %c = icmp slt i8 %s, 5 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_ashr_wrong_cmp_pred(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_ashr_wrong_cmp_pred( +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[X:%.*]], 10 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp eq i8 %s, 5 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_isnt_close_to_pow2(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_isnt_close_to_pow2( +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 12 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 1 + %c = icmp slt i8 %s, 6 + ret i1 %c +} + +define i1 @negtest_near_pow2_cmpval_would_overflow_into_signbit(i8 %x) { +; CHECK-LABEL: @negtest_near_pow2_cmpval_would_overflow_into_signbit( +; CHECK-NEXT: [[C:%.*]] = icmp sgt i8 [[X:%.*]], -1 +; CHECK-NEXT: ret i1 [[C]] +; + %s = ashr exact i8 %x, 2 + %c = icmp ult i8 %s, 33 + ret i1 %c +} -- GitLab From 3be8e2c95d3dca5b2fdea889649a69dce8605e65 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 10 May 2024 13:50:03 +0100 Subject: [PATCH 031/824] [InstCombine] Prefer to keep power-of-2 constants when combining ashr exact and slt/ult of a constant (#86111) We have flexibility in what constant to use when combining an `ashr exact` with a slt or ult of a constant, and it's not possible to revisit this decision later in the compilation pipeline after the `ashr exact` is removed. Keeping a constant close to power-of-2 (pow2val + 1) should be no worse than neutral, and in some cases may allow better codegen later on for targets that can more cheaply generate power of 2 (which may be selectable if converting back to setle/setge) or near power of 2 constants. Alive2 proofs: and --- .../lib/Transforms/InstCombine/InstCombineCompares.cpp | 10 ++++++++++ llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll | 10 ++++------ 2 files changed, 14 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index e1a3194a1beb..9883d02c87a3 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -2479,6 +2479,16 @@ Instruction *InstCombinerImpl::foldICmpShrConstant(ICmpInst &Cmp, // those conditions rather than checking them. This is difficult because of // undef/poison (PR34838). if (IsAShr && Shr->hasOneUse()) { + if (IsExact && (Pred == CmpInst::ICMP_SLT || Pred == CmpInst::ICMP_ULT) && + (C - 1).isPowerOf2() && C.countLeadingZeros() > ShAmtVal) { + // When C - 1 is a power of two and the transform can be legally + // performed, prefer this form so the produced constant is close to a + // power of two. + // icmp slt/ult (ashr exact X, ShAmtC), C + // --> icmp slt/ult X, (C - 1) << ShAmtC) + 1 + APInt ShiftedC = (C - 1).shl(ShAmtVal) + 1; + return new ICmpInst(Pred, X, ConstantInt::get(ShrTy, ShiftedC)); + } if (IsExact || Pred == CmpInst::ICMP_SLT || Pred == CmpInst::ICMP_ULT) { // When ShAmtC can be shifted losslessly: // icmp PRED (ashr exact X, ShAmtC), C --> icmp PRED X, (C << ShAmtC) diff --git a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll index 4dd5b0925914..5f09964fd93a 100644 --- a/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll +++ b/llvm/test/Transforms/InstCombine/icmp-shr-lt-gt.ll @@ -3379,7 +3379,7 @@ define i1 @ashrslt_01_01_exact(i4 %x) { define i1 @ashrslt_01_02_exact(i4 %x) { ; CHECK-LABEL: @ashrslt_01_02_exact( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 4 +; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 3 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i4 %x, 1 @@ -3389,7 +3389,7 @@ define i1 @ashrslt_01_02_exact(i4 %x) { define i1 @ashrslt_01_03_exact(i4 %x) { ; CHECK-LABEL: @ashrslt_01_03_exact( -; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 6 +; CHECK-NEXT: [[C:%.*]] = icmp slt i4 [[X:%.*]], 5 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i4 %x, 1 @@ -3800,11 +3800,9 @@ define i1 @ashrslt_03_15_exact(i4 %x) { ret i1 %c } -; TODO: The resulting compared constant can be safely replaced with one that -; is closer to a power of two. define i1 @ashr_slt_exact_near_pow2_cmpval(i8 %x) { ; CHECK-LABEL: @ashr_slt_exact_near_pow2_cmpval( -; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 10 +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[X:%.*]], 9 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i8 %x, 1 @@ -3814,7 +3812,7 @@ define i1 @ashr_slt_exact_near_pow2_cmpval(i8 %x) { define i1 @ashr_ult_exact_near_pow2_cmpval(i8 %x) { ; CHECK-LABEL: @ashr_ult_exact_near_pow2_cmpval( -; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X:%.*]], 10 +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[X:%.*]], 9 ; CHECK-NEXT: ret i1 [[C]] ; %s = ashr exact i8 %x, 1 -- GitLab From d48bf8aef2abeb915b1e04e1b78051869088df42 Mon Sep 17 00:00:00 2001 From: DianQK Date: Fri, 10 May 2024 19:19:51 +0800 Subject: [PATCH 032/824] Reapply "[InlineCost] Correct the default branch cost for the switch statement (#85160)" This reverts commit c6e4f6309184814dfc4bb855ddbdb5375cc971e0. --- llvm/lib/Analysis/InlineCost.cpp | 25 ++-- .../Inline/inline-cost-switch-default.ll | 130 ++++++++++++++++++ .../Inline/inline-switch-default-2.ll | 21 +-- .../Inline/inline-switch-default.ll | 26 +--- 4 files changed, 153 insertions(+), 49 deletions(-) create mode 100644 llvm/test/Transforms/Inline/inline-cost-switch-default.ll diff --git a/llvm/lib/Analysis/InlineCost.cpp b/llvm/lib/Analysis/InlineCost.cpp index a531064e304d..f5b17dca4973 100644 --- a/llvm/lib/Analysis/InlineCost.cpp +++ b/llvm/lib/Analysis/InlineCost.cpp @@ -701,21 +701,26 @@ class InlineCostCallAnalyzer final : public CallAnalyzer { void onFinalizeSwitch(unsigned JumpTableSize, unsigned NumCaseCluster, bool DefaultDestUndefined) override { - if (!DefaultDestUndefined) - addCost(2 * InstrCost); // If suitable for a jump table, consider the cost for the table size and // branch to destination. // Maximum valid cost increased in this function. if (JumpTableSize) { + // Suppose a default branch includes one compare and one conditional + // branch if it's reachable. + if (!DefaultDestUndefined) + addCost(2 * InstrCost); + // Suppose a jump table requires one load and one jump instruction. int64_t JTCost = - static_cast(JumpTableSize) * InstrCost + 4 * InstrCost; + static_cast(JumpTableSize) * InstrCost + 2 * InstrCost; addCost(JTCost); return; } if (NumCaseCluster <= 3) { // Suppose a comparison includes one compare and one conditional branch. - addCost(NumCaseCluster * 2 * InstrCost); + // We can reduce a set of instructions if the default branch is + // undefined. + addCost((NumCaseCluster - DefaultDestUndefined) * 2 * InstrCost); return; } @@ -1152,7 +1157,7 @@ private: // FIXME: These constants are taken from the heuristic-based cost visitor. // These should be removed entirely in a later revision to avoid reliance on // heuristics in the ML inliner. - static constexpr int JTCostMultiplier = 4; + static constexpr int JTCostMultiplier = 2; static constexpr int CaseClusterCostMultiplier = 2; static constexpr int SwitchDefaultDestCostMultiplier = 2; static constexpr int SwitchCostMultiplier = 2; @@ -1235,11 +1240,10 @@ private: void onFinalizeSwitch(unsigned JumpTableSize, unsigned NumCaseCluster, bool DefaultDestUndefined) override { - if (!DefaultDestUndefined) - increment(InlineCostFeatureIndex::switch_default_dest_penalty, - SwitchDefaultDestCostMultiplier * InstrCost); - if (JumpTableSize) { + if (!DefaultDestUndefined) + increment(InlineCostFeatureIndex::switch_default_dest_penalty, + SwitchDefaultDestCostMultiplier * InstrCost); int64_t JTCost = static_cast(JumpTableSize) * InstrCost + JTCostMultiplier * InstrCost; increment(InlineCostFeatureIndex::jump_table_penalty, JTCost); @@ -1248,7 +1252,8 @@ private: if (NumCaseCluster <= 3) { increment(InlineCostFeatureIndex::case_cluster_penalty, - NumCaseCluster * CaseClusterCostMultiplier * InstrCost); + (NumCaseCluster - DefaultDestUndefined) * + CaseClusterCostMultiplier * InstrCost); return; } diff --git a/llvm/test/Transforms/Inline/inline-cost-switch-default.ll b/llvm/test/Transforms/Inline/inline-cost-switch-default.ll new file mode 100644 index 000000000000..e3768ac8233a --- /dev/null +++ b/llvm/test/Transforms/Inline/inline-cost-switch-default.ll @@ -0,0 +1,130 @@ +; RUN: opt -S -passes=inline %s -debug-only=inline-cost -min-jump-table-entries=4 --disable-output 2>&1 | FileCheck %s -check-prefix=LOOKUPTABLE -match-full-lines +; RUN: opt -S -passes=inline %s -debug-only=inline-cost -min-jump-table-entries=5 --disable-output 2>&1 | FileCheck %s -check-prefix=SWITCH -match-full-lines +; REQUIRES: x86_64-linux, asserts + +target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define i64 @main(i64 %a) { + %b = call i64 @small_switch_default(i64 %a) + %c = call i64 @small_switch_no_default(i64 %a) + %d = call i64 @lookup_table_default(i64 %a) + %e = call i64 @lookup_table_no_default(i64 %a) + ret i64 %b +} + +; SWITCH-LABEL: Analyzing call of small_switch_default{{.*}} +; SWITCH: Cost: 0 +define i64 @small_switch_default(i64 %a) { + switch i64 %a, label %default_branch [ + i64 -1, label %branch_0 + i64 8, label %branch_1 + i64 52, label %branch_2 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +default_branch: + br label %exit + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ], [ 3, %default_branch ] + ret i64 %b +} + +; SWITCH-LABEL: Analyzing call of small_switch_no_default{{.*}} +; SWITCH: Cost: -10 +define i64 @small_switch_no_default(i64 %a) { + switch i64 %a, label %unreachabledefault [ + i64 -1, label %branch_0 + i64 8, label %branch_1 + i64 52, label %branch_2 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +unreachabledefault: + unreachable + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ] + ret i64 %b +} + +; LOOKUPTABLE-LABEL: Analyzing call of lookup_table_default{{.*}} +; LOOKUPTABLE: Cost: 10 +; SWITCH-LABEL: Analyzing call of lookup_table_default{{.*}} +; SWITCH: Cost: 20 +define i64 @lookup_table_default(i64 %a) { + switch i64 %a, label %default_branch [ + i64 0, label %branch_0 + i64 1, label %branch_1 + i64 2, label %branch_2 + i64 3, label %branch_3 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +branch_3: + br label %exit + +default_branch: + br label %exit + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ], [ 7, %branch_3 ], [ 3, %default_branch ] + ret i64 %b +} + +; LOOKUPTABLE-LABEL: Analyzing call of lookup_table_no_default{{.*}} +; LOOKUPTABLE: Cost: 0 +; SWITCH-LABEL: Analyzing call of lookup_table_no_default{{.*}} +; SWITCH: Cost: 20 +define i64 @lookup_table_no_default(i64 %a) { + switch i64 %a, label %unreachabledefault [ + i64 0, label %branch_0 + i64 1, label %branch_1 + i64 2, label %branch_2 + i64 3, label %branch_3 + ] + +branch_0: + br label %exit + +branch_1: + br label %exit + +branch_2: + br label %exit + +branch_3: + br label %exit + +unreachabledefault: + unreachable + +exit: + %b = phi i64 [ 5, %branch_0 ], [ 9, %branch_1 ], [ 2, %branch_2 ], [ 7, %branch_3 ] + ret i64 %b +} diff --git a/llvm/test/Transforms/Inline/inline-switch-default-2.ll b/llvm/test/Transforms/Inline/inline-switch-default-2.ll index 82dae1c27648..169cb2cff9b8 100644 --- a/llvm/test/Transforms/Inline/inline-switch-default-2.ll +++ b/llvm/test/Transforms/Inline/inline-switch-default-2.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt %s -S -passes=inline -inline-threshold=21 | FileCheck %s +; RUN: opt %s -S -passes=inline -inline-threshold=11 | FileCheck %s ; Check for scenarios without TTI. @@ -16,24 +16,7 @@ define i64 @foo1(i64 %a) { define i64 @foo2(i64 %a) { ; CHECK-LABEL: define i64 @foo2( ; CHECK-SAME: i64 [[A:%.*]]) { -; CHECK-NEXT: switch i64 [[A]], label [[UNREACHABLEDEFAULT_I:%.*]] [ -; CHECK-NEXT: i64 0, label [[BRANCH_0_I:%.*]] -; CHECK-NEXT: i64 2, label [[BRANCH_2_I:%.*]] -; CHECK-NEXT: i64 4, label [[BRANCH_4_I:%.*]] -; CHECK-NEXT: i64 6, label [[BRANCH_6_I:%.*]] -; CHECK-NEXT: ] -; CHECK: branch_0.i: -; CHECK-NEXT: br label [[BAR2_EXIT:%.*]] -; CHECK: branch_2.i: -; CHECK-NEXT: br label [[BAR2_EXIT]] -; CHECK: branch_4.i: -; CHECK-NEXT: br label [[BAR2_EXIT]] -; CHECK: branch_6.i: -; CHECK-NEXT: br label [[BAR2_EXIT]] -; CHECK: unreachabledefault.i: -; CHECK-NEXT: unreachable -; CHECK: bar2.exit: -; CHECK-NEXT: [[B_I:%.*]] = phi i64 [ 5, [[BRANCH_0_I]] ], [ 9, [[BRANCH_2_I]] ], [ 2, [[BRANCH_4_I]] ], [ 7, [[BRANCH_6_I]] ] +; CHECK-NEXT: [[B_I:%.*]] = call i64 @bar2(i64 [[A]]) ; CHECK-NEXT: ret i64 [[B_I]] ; %b = call i64 @bar2(i64 %a) diff --git a/llvm/test/Transforms/Inline/inline-switch-default.ll b/llvm/test/Transforms/Inline/inline-switch-default.ll index 44f1304e82df..288d414fe0e0 100644 --- a/llvm/test/Transforms/Inline/inline-switch-default.ll +++ b/llvm/test/Transforms/Inline/inline-switch-default.ll @@ -1,6 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 -; RUN: opt %s -S -passes=inline -inline-threshold=26 -min-jump-table-entries=4 | FileCheck %s -check-prefix=LOOKUPTABLE -; RUN: opt %s -S -passes=inline -inline-threshold=21 -min-jump-table-entries=5 | FileCheck %s -check-prefix=SWITCH +; RUN: opt %s -S -passes=inline -inline-threshold=16 -min-jump-table-entries=4 | FileCheck %s -check-prefix=LOOKUPTABLE +; RUN: opt %s -S -passes=inline -inline-threshold=11 -min-jump-table-entries=5 | FileCheck %s -check-prefix=SWITCH +; REQUIRES: x86_64-linux target datalayout = "e-m:e-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" target triple = "x86_64-unknown-linux-gnu" @@ -22,6 +23,8 @@ define i64 @foo1(i64 %a) { ret i64 %b } +; Since the default branch is undefined behavior, +; we can inline `bar2`: https://github.com/llvm/llvm-project/issues/90929 define i64 @foo2(i64 %a) { ; LOOKUPTABLE-LABEL: define i64 @foo2( ; LOOKUPTABLE-SAME: i64 [[A:%.*]]) { @@ -47,24 +50,7 @@ define i64 @foo2(i64 %a) { ; ; SWITCH-LABEL: define i64 @foo2( ; SWITCH-SAME: i64 [[A:%.*]]) { -; SWITCH-NEXT: switch i64 [[A]], label [[UNREACHABLEDEFAULT_I:%.*]] [ -; SWITCH-NEXT: i64 0, label [[BRANCH_0_I:%.*]] -; SWITCH-NEXT: i64 2, label [[BRANCH_2_I:%.*]] -; SWITCH-NEXT: i64 4, label [[BRANCH_4_I:%.*]] -; SWITCH-NEXT: i64 6, label [[BRANCH_6_I:%.*]] -; SWITCH-NEXT: ] -; SWITCH: branch_0.i: -; SWITCH-NEXT: br label [[BAR2_EXIT:%.*]] -; SWITCH: branch_2.i: -; SWITCH-NEXT: br label [[BAR2_EXIT]] -; SWITCH: branch_4.i: -; SWITCH-NEXT: br label [[BAR2_EXIT]] -; SWITCH: branch_6.i: -; SWITCH-NEXT: br label [[BAR2_EXIT]] -; SWITCH: unreachabledefault.i: -; SWITCH-NEXT: unreachable -; SWITCH: bar2.exit: -; SWITCH-NEXT: [[B_I:%.*]] = phi i64 [ 5, [[BRANCH_0_I]] ], [ 9, [[BRANCH_2_I]] ], [ 2, [[BRANCH_4_I]] ], [ 7, [[BRANCH_6_I]] ] +; SWITCH-NEXT: [[B_I:%.*]] = call i64 @bar2(i64 [[A]]) ; SWITCH-NEXT: ret i64 [[B_I]] ; %b = call i64 @bar2(i64 %a) -- GitLab From 561b6ab96e9d5b38a5d2672e6cc6823389b75a3f Mon Sep 17 00:00:00 2001 From: Xing Xue Date: Fri, 10 May 2024 09:23:02 -0400 Subject: [PATCH 033/824] [OpenMP][AIX] Implement __kmp_get_load_balance() for AIX (#91520) AIX has the `/proc` filesystem where `/proc//lwp//lwpsinfo` has the thread state in binary, similar to Linux's `/proc//task//stat` where the state is in ASCII. However, the definition of state info `R` in `lwpsinfo` is `runnable`. In Linux, state `R` means the thread is `running`. Therefore, `lwpsinfo` is not ideal for our purpose of getting the current load of the system. This patch uses `perfstat_cpu()` in AIX system library `libperfstat.a` to obtain the number of threads current running on logical CPUs. --- openmp/runtime/CMakeLists.txt | 9 ++-- openmp/runtime/src/z_Linux_util.cpp | 83 +++++++++++++++++++++++++---- 2 files changed, 80 insertions(+), 12 deletions(-) diff --git a/openmp/runtime/CMakeLists.txt b/openmp/runtime/CMakeLists.txt index 57ed54bcdc7b..bcae02eba6a5 100644 --- a/openmp/runtime/CMakeLists.txt +++ b/openmp/runtime/CMakeLists.txt @@ -132,10 +132,13 @@ set(LIBOMP_ASMFLAGS "" CACHE STRING "Appended user specified assembler flags.") set(LIBOMP_LDFLAGS "" CACHE STRING "Appended user specified linker flags.") -if("${LIBOMP_ARCH}" STREQUAL "ppc" AND ${CMAKE_SYSTEM_NAME} MATCHES "AIX") - # PPC (32-bit) on AIX needs libatomic for __atomic_load_8, etc. - set(LIBOMP_LIBFLAGS "-latomic" CACHE STRING +if(${CMAKE_SYSTEM_NAME} MATCHES "AIX") + set(LIBOMP_LIBFLAGS "-lperfstat" CACHE STRING "Appended user specified linked libs flags. (e.g., -lm)") + if("${LIBOMP_ARCH}" STREQUAL "ppc") + # PPC (32-bit) on AIX needs libatomic for __atomic_load_8, etc. + set(LIBOMP_LIBFLAGS "${LIBOMP_LIBFLAGS} -latomic") + endif() else() set(LIBOMP_LIBFLAGS "" CACHE STRING "Appended user specified linked libs flags. (e.g., -lm)") diff --git a/openmp/runtime/src/z_Linux_util.cpp b/openmp/runtime/src/z_Linux_util.cpp index affb577a5393..7c90740ae5bd 100644 --- a/openmp/runtime/src/z_Linux_util.cpp +++ b/openmp/runtime/src/z_Linux_util.cpp @@ -31,6 +31,7 @@ #include #if KMP_OS_AIX #include +#include #else #include #endif @@ -2427,6 +2428,79 @@ int __kmp_get_load_balance(int max) { return ret_avg; } +#elif KMP_OS_AIX + +// The function returns number of running (not sleeping) threads, or -1 in case +// of error. +int __kmp_get_load_balance(int max) { + + static int glb_running_threads = 0; // Saved count of the running threads for + // the thread balance algorithm. + static double glb_call_time = 0; // Thread balance algorithm call time. + int running_threads = 0; // Number of running threads in the system. + + double call_time = 0.0; + + __kmp_elapsed(&call_time); + + if (glb_call_time && + (call_time - glb_call_time < __kmp_load_balance_interval)) + return glb_running_threads; + + glb_call_time = call_time; + + if (max <= 0) { + max = INT_MAX; + } + + // Check how many perfstat_cpu_t structures are available. + int logical_cpus = perfstat_cpu(NULL, NULL, sizeof(perfstat_cpu_t), 0); + if (logical_cpus <= 0) { + glb_call_time = -1; + return -1; + } + + perfstat_cpu_t *cpu_stat = (perfstat_cpu_t *)KMP_INTERNAL_MALLOC( + logical_cpus * sizeof(perfstat_cpu_t)); + if (cpu_stat == NULL) { + glb_call_time = -1; + return -1; + } + + // Set first CPU as the name of the first logical CPU for which the info is + // desired. + perfstat_id_t first_cpu_name; + strcpy(first_cpu_name.name, FIRST_CPU); + + // Get the stat info of logical CPUs. + int rc = perfstat_cpu(&first_cpu_name, cpu_stat, sizeof(perfstat_cpu_t), + logical_cpus); + KMP_DEBUG_ASSERT(rc == logical_cpus); + if (rc <= 0) { + KMP_INTERNAL_FREE(cpu_stat); + glb_call_time = -1; + return -1; + } + for (int i = 0; i < logical_cpus; ++i) { + running_threads += cpu_stat[i].runque; + if (running_threads >= max) + break; + } + + // There _might_ be a timing hole where the thread executing this + // code gets skipped in the load balance, and running_threads is 0. + // Assert in the debug builds only!!! + KMP_DEBUG_ASSERT(running_threads > 0); + if (running_threads <= 0) + running_threads = 1; + + KMP_INTERNAL_FREE(cpu_stat); + + glb_running_threads = running_threads; + + return running_threads; +} + #else // Linux* OS // The function returns number of running (not sleeping) threads, or -1 in case @@ -2498,14 +2572,9 @@ int __kmp_get_load_balance(int max) { proc_entry = readdir(proc_dir); while (proc_entry != NULL) { -#if KMP_OS_AIX - // Proc entry name starts with a digit. Assume it is a process' directory. - if (isdigit(proc_entry->d_name[0])) { -#else // Proc entry is a directory and name starts with a digit. Assume it is a // process' directory. if (proc_entry->d_type == DT_DIR && isdigit(proc_entry->d_name[0])) { -#endif #ifdef KMP_DEBUG ++total_processes; @@ -2549,11 +2618,7 @@ int __kmp_get_load_balance(int max) { task_entry = readdir(task_dir); while (task_entry != NULL) { // It is a directory and name starts with a digit. -#if KMP_OS_AIX - if (isdigit(task_entry->d_name[0])) { -#else if (proc_entry->d_type == DT_DIR && isdigit(task_entry->d_name[0])) { -#endif // Construct complete stat file path. Easiest way would be: // __kmp_str_buf_print( & stat_path, "%s/%s/stat", task_path.str, -- GitLab From 195d8ac26d91ca798733c3a5f58d67992d43503d Mon Sep 17 00:00:00 2001 From: Xiang Li Date: Fri, 10 May 2024 06:29:23 -0700 Subject: [PATCH 034/824] [DirectX] Fix DXIL part header version encoding (#91506) Move MinorVersion be the lower 8 bit. Set DXIL version in DXContainerObjectWriter::writeObject. Fixes #89952 --- llvm/include/llvm/BinaryFormat/DXContainer.h | 2 +- llvm/include/llvm/TargetParser/Triple.h | 2 +- llvm/lib/MC/MCDXContainerWriter.cpp | 3 + llvm/lib/TargetParser/Triple.cpp | 2 + llvm/test/CodeGen/DirectX/embed-dxil.ll | 4 +- llvm/unittests/Object/DXContainerTest.cpp | 59 +++++++++++++++++--- 6 files changed, 61 insertions(+), 11 deletions(-) diff --git a/llvm/include/llvm/BinaryFormat/DXContainer.h b/llvm/include/llvm/BinaryFormat/DXContainer.h index e8d03f806715..e5fcda63910d 100644 --- a/llvm/include/llvm/BinaryFormat/DXContainer.h +++ b/llvm/include/llvm/BinaryFormat/DXContainer.h @@ -103,8 +103,8 @@ struct PartHeader { struct BitcodeHeader { uint8_t Magic[4]; // ACSII "DXIL". - uint8_t MajorVersion; // DXIL version. uint8_t MinorVersion; // DXIL version. + uint8_t MajorVersion; // DXIL version. uint16_t Unused; uint32_t Offset; // Offset to LLVM bitcode (from start of header). uint32_t Size; // Size of LLVM bitcode (in bytes). diff --git a/llvm/include/llvm/TargetParser/Triple.h b/llvm/include/llvm/TargetParser/Triple.h index 8f9d99816931..b3bb354b38ff 100644 --- a/llvm/include/llvm/TargetParser/Triple.h +++ b/llvm/include/llvm/TargetParser/Triple.h @@ -429,7 +429,7 @@ public: /// (SubArch). This should only be called with Vulkan SPIR-V triples. VersionTuple getVulkanVersion() const; - /// Parse the DXIL version number from the DXIL version + /// Parse the DXIL version number from the OSVersion and DXIL version /// (SubArch). This should only be called with DXIL triples. VersionTuple getDXILVersion() const; diff --git a/llvm/lib/MC/MCDXContainerWriter.cpp b/llvm/lib/MC/MCDXContainerWriter.cpp index 0580dc7e4282..015899278f37 100644 --- a/llvm/lib/MC/MCDXContainerWriter.cpp +++ b/llvm/lib/MC/MCDXContainerWriter.cpp @@ -127,6 +127,9 @@ uint64_t DXContainerObjectWriter::writeObject(MCAssembler &Asm, // The program header's size field is in 32-bit words. Header.Size = (SectionSize + sizeof(dxbc::ProgramHeader) + 3) / 4; memcpy(Header.Bitcode.Magic, "DXIL", 4); + VersionTuple DXILVersion = TT.getDXILVersion(); + Header.Bitcode.MajorVersion = DXILVersion.getMajor(); + Header.Bitcode.MinorVersion = DXILVersion.getMinor().value_or(0); Header.Bitcode.Offset = sizeof(dxbc::BitcodeHeader); Header.Bitcode.Size = SectionSize; if (sys::IsBigEndianHost) diff --git a/llvm/lib/TargetParser/Triple.cpp b/llvm/lib/TargetParser/Triple.cpp index f8269a51dc0b..4fc1ff5aaa05 100644 --- a/llvm/lib/TargetParser/Triple.cpp +++ b/llvm/lib/TargetParser/Triple.cpp @@ -1510,6 +1510,8 @@ VersionTuple Triple::getDXILVersion() const { if (getArch() != dxil || getOS() != ShaderModel) llvm_unreachable("invalid DXIL triple"); StringRef Arch = getArchName(); + if (getSubArch() == NoSubArch) + Arch = getDXILArchNameFromShaderModel(getOSName()); Arch.consume_front("dxilv"); VersionTuple DXILVersion = parseVersionFromName(Arch); // FIXME: validate DXIL version against Shader Model version. diff --git a/llvm/test/CodeGen/DirectX/embed-dxil.ll b/llvm/test/CodeGen/DirectX/embed-dxil.ll index 306e5c385b5a..9f4fb19d86fa 100644 --- a/llvm/test/CodeGen/DirectX/embed-dxil.ll +++ b/llvm/test/CodeGen/DirectX/embed-dxil.ll @@ -42,8 +42,8 @@ define i32 @add(i32 %a, i32 %b) { ; DXC-NEXT: MinorVersion: 5 ; DXC-NEXT: ShaderKind: 6 ; DXC-NEXT: Size: [[#div(SIZE,4)]] -; DXC-NEXT: DXILMajorVersion: [[#]] -; DXC-NEXT: DXILMinorVersion: [[#]] +; DXC-NEXT: DXILMajorVersion: 1 +; DXC-NEXT: DXILMinorVersion: 5 ; DXC-NEXT: DXILSize: [[#SIZE - 24]] ; DXC-NEXT: DXIL: [ 0x42, 0x43, 0xC0, 0xDE, ; DXC: - Name: SFI0 diff --git a/llvm/unittests/Object/DXContainerTest.cpp b/llvm/unittests/Object/DXContainerTest.cpp index da640225617d..098da331ab56 100644 --- a/llvm/unittests/Object/DXContainerTest.cpp +++ b/llvm/unittests/Object/DXContainerTest.cpp @@ -126,6 +126,51 @@ TEST(DXCFile, ParseOverlappingParts) { "Part offset for part 1 begins before the previous part ends")); } +// This test verify DXILMajorVersion and DXILMinorVersion are correctly parsed. +// This test is based on the binary output constructed from this yaml. +// --- !dxcontainer +// Header: +// Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, +// 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] +// Version: +// Major: 1 +// Minor: 0 +// PartCount: 1 +// Parts: +// - Name: DXIL +// Size: 28 +// Program: +// MajorVersion: 6 +// MinorVersion: 5 +// ShaderKind: 5 +// Size: 8 +// DXILMajorVersion: 1 +// DXILMinorVersion: 5 +// DXILSize: 4 +// DXIL: [ 0x42, 0x43, 0xC0, 0xDE, ] +// ... +TEST(DXCFile, ParseDXILPart) { + uint8_t Buffer[] = { + 0x44, 0x58, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, + 0x48, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, + 0x44, 0x58, 0x49, 0x4c, 0x1c, 0x00, 0x00, 0x00, 0x65, 0x00, 0x05, 0x00, + 0x08, 0x00, 0x00, 0x00, 0x44, 0x58, 0x49, 0x4c, 0x05, 0x01, 0x00, 0x00, + 0x10, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x42, 0x43, 0xc0, 0xde}; + DXContainer C = + llvm::cantFail(DXContainer::create(getMemoryBuffer<116>(Buffer))); + EXPECT_EQ(C.getHeader().PartCount, 1u); + const std::optional &DXIL = C.getDXIL(); + EXPECT_TRUE(DXIL.has_value()); + dxbc::ProgramHeader Header = DXIL->first; + EXPECT_EQ(Header.MajorVersion, 6u); + EXPECT_EQ(Header.MinorVersion, 5u); + EXPECT_EQ(Header.ShaderKind, 5u); + EXPECT_EQ(Header.Size, 8u); + EXPECT_EQ(Header.Bitcode.MajorVersion, 1u); + EXPECT_EQ(Header.Bitcode.MinorVersion, 5u); +} + TEST(DXCFile, ParseEmptyParts) { uint8_t Buffer[] = { 0x44, 0x58, 0x42, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, @@ -240,8 +285,8 @@ Parts: MinorVersion: 0 ShaderKind: 14 Size: 6 - DXILMajorVersion: 0 - DXILMinorVersion: 1 + DXILMajorVersion: 1 + DXILMinorVersion: 0 DXILSize: 0 ... )"; @@ -361,8 +406,8 @@ Parts: // MinorVersion: 0 // ShaderKind: 14 // Size: 6 -// DXILMajorVersion: 0 -// DXILMinorVersion: 1 +// DXILMajorVersion: 1 +// DXILMinorVersion: 0 // DXILSize: 0 // - Name: PSV0 // Size: 36 @@ -477,7 +522,7 @@ TEST(DXCFile, MaliciousFiles) { // // --- !dxcontainer // Header: -// Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, +// Hash: [ 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, // 0x0, 0x0, 0x0, 0x0, 0x0, 0x0 ] // Version: // Major: 1 @@ -491,8 +536,8 @@ TEST(DXCFile, MaliciousFiles) { // MinorVersion: 0 // ShaderKind: 14 // Size: 6 -// DXILMajorVersion: 0 -// DXILMinorVersion: 1 +// DXILMajorVersion: 1 +// DXILMinorVersion: 0 // DXILSize: 0 // - Name: PSV0 // Size: 100 -- GitLab From 4cf3f032283d8426c9b7829c7ccf0ab01939c7db Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Fri, 10 May 2024 21:51:07 +0800 Subject: [PATCH 035/824] [clang-tidy] use llvm::any_of refactor getAnalyzerCheckersAndPackages [NFC] (#91713) --- clang-tools-extra/clang-tidy/ClangTidy.cpp | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/clang-tools-extra/clang-tidy/ClangTidy.cpp b/clang-tools-extra/clang-tidy/ClangTidy.cpp index b877ea06dc05..1cd7cdd10bc2 100644 --- a/clang-tools-extra/clang-tidy/ClangTidy.cpp +++ b/clang-tools-extra/clang-tidy/ClangTidy.cpp @@ -373,11 +373,11 @@ static CheckersList getAnalyzerCheckersAndPackages(ClangTidyContext &Context, const auto &RegisteredCheckers = AnalyzerOptions::getRegisteredCheckers(IncludeExperimental); - bool AnalyzerChecksEnabled = false; - for (StringRef CheckName : RegisteredCheckers) { - std::string ClangTidyCheckName((AnalyzerCheckNamePrefix + CheckName).str()); - AnalyzerChecksEnabled |= Context.isCheckEnabled(ClangTidyCheckName); - } + const bool AnalyzerChecksEnabled = + llvm::any_of(RegisteredCheckers, [&](StringRef CheckName) -> bool { + return Context.isCheckEnabled( + (AnalyzerCheckNamePrefix + CheckName).str()); + }); if (!AnalyzerChecksEnabled) return List; -- GitLab From 8fc9e3d577c02d2b97c952fbafb75db0100462a9 Mon Sep 17 00:00:00 2001 From: David Green Date: Fri, 10 May 2024 14:58:48 +0100 Subject: [PATCH 036/824] [DAG] Lower frem of power-2 using div/trunc/mul+sub (#91148) If we are lowering a frem and the divisor is known to be an integer power-2, we can use the formula 'frem = x - trunc(x / d) * d'. This avoids the more expensive call to fmod. The results are identical as fmod so long as d is a power-2 (so the mul does not round incorrectly), and the sign of the return is either always positive or not important for zeroes (nsz). Unfortunately Alive2 does not handle this well at the moment. I was using exhaustive checking to test this: (https://gist.github.com/davemgreen/6078015f30d3bacd1e9572f8db5d4b64). I found this in cpythons implementation of float_pow. I currently added it as a DAG combine for frem with power-2 fp constants. --- llvm/include/llvm/CodeGen/SelectionDAG.h | 8 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 20 +- .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 + llvm/test/CodeGen/AArch64/frem-power2.ll | 373 ++++++++++-------- llvm/test/CodeGen/ARM/frem-power2.ll | 18 +- 5 files changed, 273 insertions(+), 163 deletions(-) diff --git a/llvm/include/llvm/CodeGen/SelectionDAG.h b/llvm/include/llvm/CodeGen/SelectionDAG.h index 4b1b58d4af0b..c08e57ba3f67 100644 --- a/llvm/include/llvm/CodeGen/SelectionDAG.h +++ b/llvm/include/llvm/CodeGen/SelectionDAG.h @@ -1996,6 +1996,10 @@ public: /// is set. bool isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth = 0) const; + /// Test if the given _fp_ value is known to be an integer power-of-2, either + /// positive or negative. + bool isKnownToBeAPowerOfTwoFP(SDValue Val, unsigned Depth = 0) const; + /// Return the number of times the sign bit of the register is replicated into /// the other bits. We know that at least 1 bit is always equal to the sign /// bit (itself), but other cases can give us information. For example, @@ -2111,6 +2115,10 @@ public: /// Test whether the given SDValue is known to contain non-zero value(s). bool isKnownNeverZero(SDValue Op, unsigned Depth = 0) const; + /// Test whether the given float value is known to be positive. +0.0, +inf and + /// +nan are considered positive, -0.0, -inf and -nan are not. + bool cannotBeOrderedNegativeFP(SDValue Op) const; + /// Test whether two SDValues are known to compare equal. This /// is true if they are the same value, or if one is negative zero and the /// other positive zero. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index fddc97d8901a..be919b7a8922 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -17365,17 +17365,35 @@ SDValue DAGCombiner::visitFREM(SDNode *N) { EVT VT = N->getValueType(0); SDNodeFlags Flags = N->getFlags(); SelectionDAG::FlagInserter FlagsInserter(DAG, N); + SDLoc DL(N); if (SDValue R = DAG.simplifyFPBinop(N->getOpcode(), N0, N1, Flags)) return R; // fold (frem c1, c2) -> fmod(c1,c2) - if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, SDLoc(N), VT, {N0, N1})) + if (SDValue C = DAG.FoldConstantArithmetic(ISD::FREM, DL, VT, {N0, N1})) return C; if (SDValue NewSel = foldBinOpIntoSelect(N)) return NewSel; + // Lower frem N0, N1 => x - trunc(N0 / N1) * N1, providing N1 is an integer + // power of 2. + if (!TLI.isOperationLegal(ISD::FREM, VT) && + TLI.isOperationLegalOrCustom(ISD::FMUL, VT) && + TLI.isOperationLegalOrCustom(ISD::FDIV, VT) && + TLI.isOperationLegalOrCustom(ISD::FTRUNC, VT) && + DAG.isKnownToBeAPowerOfTwoFP(N1) && + (Flags.hasNoSignedZeros() || DAG.cannotBeOrderedNegativeFP(N0))) { + SDValue Div = DAG.getNode(ISD::FDIV, DL, VT, N0, N1); + SDValue Rnd = DAG.getNode(ISD::FTRUNC, DL, VT, Div); + if (TLI.isFMAFasterThanFMulAndFAdd(DAG.getMachineFunction(), VT)) + return DAG.getNode(ISD::FMA, DL, VT, DAG.getNode(ISD::FNEG, DL, VT, Rnd), + N1, N0); + SDValue Mul = DAG.getNode(ISD::FMUL, DL, VT, Rnd, N1); + return DAG.getNode(ISD::FSUB, DL, VT, N0, Mul); + } + return SDValue(); } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index eef5acd03234..9c1f3c1e3431 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -4373,6 +4373,16 @@ bool SelectionDAG::isKnownToBeAPowerOfTwo(SDValue Val, unsigned Depth) const { return false; } +bool SelectionDAG::isKnownToBeAPowerOfTwoFP(SDValue Val, unsigned Depth) const { + if (ConstantFPSDNode *C1 = isConstOrConstSplatFP(Val, true)) + return C1->getValueAPF().getExactLog2Abs() >= 0; + + if (Val.getOpcode() == ISD::UINT_TO_FP || Val.getOpcode() == ISD::SINT_TO_FP) + return isKnownToBeAPowerOfTwo(Val.getOperand(0), Depth + 1); + + return false; +} + unsigned SelectionDAG::ComputeNumSignBits(SDValue Op, unsigned Depth) const { EVT VT = Op.getValueType(); @@ -5555,6 +5565,13 @@ bool SelectionDAG::isKnownNeverZero(SDValue Op, unsigned Depth) const { return computeKnownBits(Op, Depth).isNonZero(); } +bool SelectionDAG::cannotBeOrderedNegativeFP(SDValue Op) const { + if (ConstantFPSDNode *C1 = isConstOrConstSplatFP(Op, true)) + return !C1->isNegative(); + + return Op.getOpcode() == ISD::FABS; +} + bool SelectionDAG::isEqualTo(SDValue A, SDValue B) const { // Check the obvious case. if (A == B) return true; diff --git a/llvm/test/CodeGen/AArch64/frem-power2.ll b/llvm/test/CodeGen/AArch64/frem-power2.ll index 5d627fcd6b65..402e03c5e265 100644 --- a/llvm/test/CodeGen/AArch64/frem-power2.ll +++ b/llvm/test/CodeGen/AArch64/frem-power2.ll @@ -13,31 +13,57 @@ entry: } define float @frem2_nsz(float %x) { -; CHECK-LABEL: frem2_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem nsz float %x, 2.0 ret float %fmod } define float @frem2_fast(float %x) { -; CHECK-LABEL: frem2_fast: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_fast: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov s1, #0.50000000 +; CHECK-SD-NEXT: fmov s2, #-2.00000000 +; CHECK-SD-NEXT: fmul s1, s0, s1 +; CHECK-SD-NEXT: frintz s1, s1 +; CHECK-SD-NEXT: fmadd s0, s1, s2, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_fast: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem fast float %x, 2.0 ret float %fmod } define float @frem2_abs(float %x) { -; CHECK-LABEL: frem2_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: fmov s1, #2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fmov s1, #2.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: fmov s1, #2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 2.0 @@ -47,14 +73,11 @@ entry: define half @hrem2_nsz(half %x) { ; CHECK-SD-LABEL: hrem2_nsz: ; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; CHECK-SD-NEXT: .cfi_def_cfa_offset 16 -; CHECK-SD-NEXT: .cfi_offset w30, -16 -; CHECK-SD-NEXT: fcvt s0, h0 -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: fcvt h0, s0 -; CHECK-SD-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; CHECK-SD-NEXT: fmov h1, #2.00000000 +; CHECK-SD-NEXT: fmov h2, #-2.00000000 +; CHECK-SD-NEXT: fdiv h1, h0, h1 +; CHECK-SD-NEXT: frintz h1, h1 +; CHECK-SD-NEXT: fmadd h0, h1, h2, h0 ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: hrem2_nsz: @@ -75,10 +98,18 @@ entry: } define double @drem2_nsz(double %x) { -; CHECK-LABEL: drem2_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov d1, #2.00000000 -; CHECK-NEXT: b fmod +; CHECK-SD-LABEL: drem2_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov d1, #2.00000000 +; CHECK-SD-NEXT: fdiv d2, d0, d1 +; CHECK-SD-NEXT: frintz d2, d2 +; CHECK-SD-NEXT: fmsub d0, d2, d1, d0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: drem2_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov d1, #2.00000000 +; CHECK-GI-NEXT: b fmod entry: %fmod = frem nsz double %x, 2.0 ret double %fmod @@ -105,10 +136,16 @@ entry: } define float @frem1_nsz(float %x) { -; CHECK-LABEL: frem1_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #1.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem1_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: frintz s1, s0 +; CHECK-SD-NEXT: fsub s0, s0, s1 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem1_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #1.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem nsz float %x, 1.0 ret float %fmod @@ -125,21 +162,38 @@ entry: } define float @fremm2_nsz(float %x) { -; CHECK-LABEL: fremm2_nsz: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fmov s1, #-2.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: fremm2_nsz: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fmov s1, #-2.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: fremm2_nsz: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fmov s1, #-2.00000000 +; CHECK-GI-NEXT: b fmodf entry: %fmod = frem nsz float %x, -2.0 ret float %fmod } define float @frem4_abs(float %x) { -; CHECK-LABEL: frem4_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: fmov s1, #4.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem4_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fmov s1, #4.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem4_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: fmov s1, #4.00000000 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 4.0 @@ -147,11 +201,20 @@ entry: } define float @frem16_abs(float %x) { -; CHECK-LABEL: frem16_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: fmov s1, #16.00000000 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem16_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fmov s1, #16.00000000 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem16_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: fmov s1, #16.00000000 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 16.0 @@ -159,12 +222,22 @@ entry: } define float @frem4294967296_abs(float %x) { -; CHECK-LABEL: frem4294967296_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: mov w8, #1333788672 // =0x4f800000 -; CHECK-NEXT: fmov s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem4294967296_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: mov w8, #1333788672 // =0x4f800000 +; CHECK-SD-NEXT: fmov s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem4294967296_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: mov w8, #1333788672 // =0x4f800000 +; CHECK-GI-NEXT: fmov s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 4294967296.0 @@ -172,12 +245,22 @@ entry: } define float @frem1152921504606846976_abs(float %x) { -; CHECK-LABEL: frem1152921504606846976_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: mov w8, #1568669696 // =0x5d800000 -; CHECK-NEXT: fmov s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem1152921504606846976_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: mov w8, #1568669696 // =0x5d800000 +; CHECK-SD-NEXT: fmov s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem1152921504606846976_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: mov w8, #1568669696 // =0x5d800000 +; CHECK-GI-NEXT: fmov s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 1152921504606846976.0 @@ -185,12 +268,22 @@ entry: } define float @frem4611686018427387904_abs(float %x) { -; CHECK-LABEL: frem4611686018427387904_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: mov w8, #1585446912 // =0x5e800000 -; CHECK-NEXT: fmov s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem4611686018427387904_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: mov w8, #1585446912 // =0x5e800000 +; CHECK-SD-NEXT: fmov s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem4611686018427387904_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: mov w8, #1585446912 // =0x5e800000 +; CHECK-GI-NEXT: fmov s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 4611686018427387904.0 @@ -198,11 +291,20 @@ entry: } define float @frem9223372036854775808_abs(float %x) { -; CHECK-LABEL: frem9223372036854775808_abs: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: fabs s0, s0 -; CHECK-NEXT: movi v1.2s, #95, lsl #24 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem9223372036854775808_abs: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: movi v1.2s, #95, lsl #24 +; CHECK-SD-NEXT: fabs s0, s0 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem9223372036854775808_abs: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: fabs s0, s0 +; CHECK-GI-NEXT: movi v1.2s, #95, lsl #24 +; CHECK-GI-NEXT: b fmodf entry: %a = tail call float @llvm.fabs.f32(float %x) %fmod = frem float %a, 9223372036854775808.0 @@ -212,42 +314,10 @@ entry: define <4 x float> @frem2_nsz_vec(<4 x float> %x) { ; CHECK-SD-LABEL: frem2_nsz_vec: ; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: sub sp, sp, #48 -; CHECK-SD-NEXT: str x30, [sp, #32] // 8-byte Folded Spill -; CHECK-SD-NEXT: .cfi_def_cfa_offset 48 -; CHECK-SD-NEXT: .cfi_offset w30, -16 -; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Folded Spill -; CHECK-SD-NEXT: mov s0, v0.s[1] -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v0.s[1], v1.s[0] -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[2] -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v1.s[2], v0.s[0] -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[3] -; CHECK-SD-NEXT: str q1, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: fmov s1, #2.00000000 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: ldr x30, [sp, #32] // 8-byte Folded Reload -; CHECK-SD-NEXT: mov v1.s[3], v0.s[0] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: add sp, sp, #48 +; CHECK-SD-NEXT: movi v1.4s, #64, lsl #24 +; CHECK-SD-NEXT: fdiv v2.4s, v0.4s, v1.4s +; CHECK-SD-NEXT: frintz v2.4s, v2.4s +; CHECK-SD-NEXT: fmls v0.4s, v1.4s, v2.4s ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: frem2_nsz_vec: @@ -302,48 +372,12 @@ entry: define <4 x float> @frem1152921504606846976_absv(<4 x float> %x) { ; CHECK-SD-LABEL: frem1152921504606846976_absv: ; CHECK-SD: // %bb.0: // %entry -; CHECK-SD-NEXT: sub sp, sp, #48 -; CHECK-SD-NEXT: str d8, [sp, #32] // 8-byte Folded Spill -; CHECK-SD-NEXT: str x30, [sp, #40] // 8-byte Folded Spill -; CHECK-SD-NEXT: .cfi_def_cfa_offset 48 -; CHECK-SD-NEXT: .cfi_offset w30, -8 -; CHECK-SD-NEXT: .cfi_offset b8, -16 -; CHECK-SD-NEXT: fabs v0.4s, v0.4s ; CHECK-SD-NEXT: mov w8, #1568669696 // =0x5d800000 -; CHECK-SD-NEXT: fmov s8, w8 -; CHECK-SD-NEXT: str q0, [sp, #16] // 16-byte Folded Spill -; CHECK-SD-NEXT: mov s0, v0.s[1] -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 killed $q0 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v0.s[1], v1.s[0] -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: str q0, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[2] -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: mov v1.s[2], v0.s[0] -; CHECK-SD-NEXT: ldr q0, [sp, #16] // 16-byte Folded Reload -; CHECK-SD-NEXT: mov s0, v0.s[3] -; CHECK-SD-NEXT: str q1, [sp] // 16-byte Folded Spill -; CHECK-SD-NEXT: fmov s1, s8 -; CHECK-SD-NEXT: bl fmodf -; CHECK-SD-NEXT: ldr q1, [sp] // 16-byte Folded Reload -; CHECK-SD-NEXT: // kill: def $s0 killed $s0 def $q0 -; CHECK-SD-NEXT: ldr x30, [sp, #40] // 8-byte Folded Reload -; CHECK-SD-NEXT: ldr d8, [sp, #32] // 8-byte Folded Reload -; CHECK-SD-NEXT: mov v1.s[3], v0.s[0] -; CHECK-SD-NEXT: mov v0.16b, v1.16b -; CHECK-SD-NEXT: add sp, sp, #48 +; CHECK-SD-NEXT: fabs v0.4s, v0.4s +; CHECK-SD-NEXT: dup v1.4s, w8 +; CHECK-SD-NEXT: fdiv v2.4s, v0.4s, v1.4s +; CHECK-SD-NEXT: frintz v2.4s, v2.4s +; CHECK-SD-NEXT: fmls v0.4s, v1.4s, v2.4s ; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: frem1152921504606846976_absv: @@ -401,12 +435,22 @@ entry: } define float @frem2_nsz_sitofp(float %x, i32 %sa) { -; CHECK-LABEL: frem2_nsz_sitofp: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: mov w8, #1 // =0x1 -; CHECK-NEXT: lsl w8, w8, w0 -; CHECK-NEXT: scvtf s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_nsz_sitofp: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov w8, #1 // =0x1 +; CHECK-SD-NEXT: lsl w8, w8, w0 +; CHECK-SD-NEXT: scvtf s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_nsz_sitofp: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: lsl w8, w8, w0 +; CHECK-GI-NEXT: scvtf s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %s = shl i32 1, %sa %y = sitofp i32 %s to float @@ -415,12 +459,22 @@ entry: } define float @frem2_nsz_uitofp(float %x, i32 %sa) { -; CHECK-LABEL: frem2_nsz_uitofp: -; CHECK: // %bb.0: // %entry -; CHECK-NEXT: mov w8, #1 // =0x1 -; CHECK-NEXT: lsl w8, w8, w0 -; CHECK-NEXT: ucvtf s1, w8 -; CHECK-NEXT: b fmodf +; CHECK-SD-LABEL: frem2_nsz_uitofp: +; CHECK-SD: // %bb.0: // %entry +; CHECK-SD-NEXT: mov w8, #1 // =0x1 +; CHECK-SD-NEXT: lsl w8, w8, w0 +; CHECK-SD-NEXT: ucvtf s1, w8 +; CHECK-SD-NEXT: fdiv s2, s0, s1 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s1, s0 +; CHECK-SD-NEXT: ret +; +; CHECK-GI-LABEL: frem2_nsz_uitofp: +; CHECK-GI: // %bb.0: // %entry +; CHECK-GI-NEXT: mov w8, #1 // =0x1 +; CHECK-GI-NEXT: lsl w8, w8, w0 +; CHECK-GI-NEXT: ucvtf s1, w8 +; CHECK-GI-NEXT: b fmodf entry: %s = shl i32 1, %sa %y = uitofp i32 %s to float @@ -432,10 +486,13 @@ define float @frem2_const_sitofp(float %x, i32 %sa) { ; CHECK-SD-LABEL: frem2_const_sitofp: ; CHECK-SD: // %bb.0: // %entry ; CHECK-SD-NEXT: mov w8, #1 // =0x1 -; CHECK-SD-NEXT: fmov s0, #12.50000000 +; CHECK-SD-NEXT: fmov s1, #12.50000000 ; CHECK-SD-NEXT: lsl w8, w8, w0 -; CHECK-SD-NEXT: scvtf s1, w8 -; CHECK-SD-NEXT: b fmodf +; CHECK-SD-NEXT: scvtf s0, w8 +; CHECK-SD-NEXT: fdiv s2, s1, s0 +; CHECK-SD-NEXT: frintz s2, s2 +; CHECK-SD-NEXT: fmsub s0, s2, s0, s1 +; CHECK-SD-NEXT: ret ; ; CHECK-GI-LABEL: frem2_const_sitofp: ; CHECK-GI: // %bb.0: // %entry diff --git a/llvm/test/CodeGen/ARM/frem-power2.ll b/llvm/test/CodeGen/ARM/frem-power2.ll index 8052c8c35bcf..7f52943175ac 100644 --- a/llvm/test/CodeGen/ARM/frem-power2.ll +++ b/llvm/test/CodeGen/ARM/frem-power2.ll @@ -37,13 +37,23 @@ define float @frem4_nsz(float %x) { ; ; CHECK-FP-LABEL: frem4_nsz: ; CHECK-FP: @ %bb.0: @ %entry -; CHECK-FP-NEXT: mov.w r1, #1082130432 -; CHECK-FP-NEXT: b fmodf +; CHECK-FP-NEXT: vmov.f32 s0, #4.000000e+00 +; CHECK-FP-NEXT: vmov s2, r0 +; CHECK-FP-NEXT: vdiv.f32 s4, s2, s0 +; CHECK-FP-NEXT: vrintz.f32 s4, s4 +; CHECK-FP-NEXT: vfms.f32 s2, s4, s0 +; CHECK-FP-NEXT: vmov r0, s2 +; CHECK-FP-NEXT: bx lr ; ; CHECK-M33-LABEL: frem4_nsz: ; CHECK-M33: @ %bb.0: @ %entry -; CHECK-M33-NEXT: mov.w r1, #1082130432 -; CHECK-M33-NEXT: b fmodf +; CHECK-M33-NEXT: vmov.f32 s0, #4.000000e+00 +; CHECK-M33-NEXT: vmov s2, r0 +; CHECK-M33-NEXT: vdiv.f32 s4, s2, s0 +; CHECK-M33-NEXT: vrintz.f32 s4, s4 +; CHECK-M33-NEXT: vmls.f32 s2, s4, s0 +; CHECK-M33-NEXT: vmov r0, s2 +; CHECK-M33-NEXT: bx lr entry: %fmod = frem nsz float %x, 4.0 ret float %fmod -- GitLab From 63177422a834f4b81d59b827b5f2a1c5a9083749 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Fri, 10 May 2024 07:02:10 -0700 Subject: [PATCH 037/824] [OpenACC][NFC] Fix isa behavior for OpenACC types I discovered while working on a different patch that I'd not implemented the 'classof' for any of the Clauses, which resulted in 'isa' always returning 'true' for all of the types. This patch goes through all the existing clauses and adds 'classof' such that it will work correctly. Additionally, in doing this, I found a bug where I was doing a cast to the wrong type in the ASTWriter, so this fixes that problem as well. --- clang/include/clang/AST/OpenACCClause.h | 71 ++++++++++++++++++++++++- clang/include/clang/AST/StmtOpenACC.h | 4 ++ clang/lib/AST/OpenACCClause.cpp | 27 ++++++++++ clang/lib/Serialization/ASTWriter.cpp | 2 +- 4 files changed, 102 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/AST/OpenACCClause.h b/clang/include/clang/AST/OpenACCClause.h index d8332816a499..3d0b1ab9d31e 100644 --- a/clang/include/clang/AST/OpenACCClause.h +++ b/clang/include/clang/AST/OpenACCClause.h @@ -36,7 +36,7 @@ public: SourceLocation getBeginLoc() const { return Location.getBegin(); } SourceLocation getEndLoc() const { return Location.getEnd(); } - static bool classof(const OpenACCClause *) { return true; } + static bool classof(const OpenACCClause *) { return false; } using child_iterator = StmtIterator; using const_child_iterator = ConstStmtIterator; @@ -63,6 +63,8 @@ protected: : OpenACCClause(K, BeginLoc, EndLoc), LParenLoc(LParenLoc) {} public: + static bool classof(const OpenACCClause *C); + SourceLocation getLParenLoc() const { return LParenLoc; } child_range children() { @@ -92,6 +94,9 @@ protected: } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Default; + } OpenACCDefaultClauseKind getDefaultClauseKind() const { return DefaultClauseKind; } @@ -116,6 +121,8 @@ protected: ConditionExpr(ConditionExpr) {} public: + static bool classof(const OpenACCClause *C); + bool hasConditionExpr() const { return ConditionExpr; } const Expr *getConditionExpr() const { return ConditionExpr; } Expr *getConditionExpr() { return ConditionExpr; } @@ -143,6 +150,9 @@ protected: Expr *ConditionExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::If; + } static OpenACCIfClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *ConditionExpr, SourceLocation EndLoc); @@ -154,6 +164,9 @@ class OpenACCSelfClause : public OpenACCClauseWithCondition { Expr *ConditionExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Self; + } static OpenACCSelfClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *ConditionExpr, SourceLocation EndLoc); @@ -180,6 +193,7 @@ protected: llvm::ArrayRef getExprs() const { return Exprs; } public: + static bool classof(const OpenACCClause *C); child_range children() { return child_range(reinterpret_cast(Exprs.begin()), reinterpret_cast(Exprs.end())); @@ -214,6 +228,9 @@ class OpenACCWaitClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Wait; + } static OpenACCWaitClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *DevNumExpr, SourceLocation QueuesLoc, @@ -246,6 +263,9 @@ class OpenACCNumGangsClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::NumGangs; + } static OpenACCNumGangsClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef IntExprs, SourceLocation EndLoc); @@ -275,6 +295,7 @@ protected: } public: + static bool classof(const OpenACCClause *C); bool hasIntExpr() const { return !getExprs().empty(); } const Expr *getIntExpr() const { return hasIntExpr() ? getExprs()[0] : nullptr; @@ -288,6 +309,9 @@ class OpenACCNumWorkersClause : public OpenACCClauseWithSingleIntExpr { Expr *IntExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::NumWorkers; + } static OpenACCNumWorkersClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, @@ -299,6 +323,9 @@ class OpenACCVectorLengthClause : public OpenACCClauseWithSingleIntExpr { Expr *IntExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::VectorLength; + } static OpenACCVectorLengthClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *IntExpr, SourceLocation EndLoc); @@ -309,6 +336,9 @@ class OpenACCAsyncClause : public OpenACCClauseWithSingleIntExpr { Expr *IntExpr, SourceLocation EndLoc); public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Async; + } static OpenACCAsyncClause *Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, Expr *IntExpr, @@ -326,6 +356,7 @@ protected: : OpenACCClauseWithExprs(K, BeginLoc, LParenLoc, EndLoc) {} public: + static bool classof(const OpenACCClause *C); ArrayRef getVarList() { return getExprs(); } ArrayRef getVarList() const { return getExprs(); } }; @@ -344,6 +375,9 @@ class OpenACCPrivateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Private; + } static OpenACCPrivateClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -363,6 +397,9 @@ class OpenACCFirstPrivateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::FirstPrivate; + } static OpenACCFirstPrivateClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -382,6 +419,9 @@ class OpenACCDevicePtrClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::DevicePtr; + } static OpenACCDevicePtrClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -401,6 +441,9 @@ class OpenACCAttachClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Attach; + } static OpenACCAttachClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -420,6 +463,9 @@ class OpenACCNoCreateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::NoCreate; + } static OpenACCNoCreateClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -439,6 +485,9 @@ class OpenACCPresentClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Present; + } static OpenACCPresentClause * Create(const ASTContext &C, SourceLocation BeginLoc, SourceLocation LParenLoc, ArrayRef VarList, SourceLocation EndLoc); @@ -462,6 +511,11 @@ class OpenACCCopyClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Copy || + C->getClauseKind() == OpenACCClauseKind::PCopy || + C->getClauseKind() == OpenACCClauseKind::PresentOrCopy; + } static OpenACCCopyClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, SourceLocation BeginLoc, SourceLocation LParenLoc, @@ -488,6 +542,11 @@ class OpenACCCopyInClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::CopyIn || + C->getClauseKind() == OpenACCClauseKind::PCopyIn || + C->getClauseKind() == OpenACCClauseKind::PresentOrCopyIn; + } bool isReadOnly() const { return IsReadOnly; } static OpenACCCopyInClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, @@ -515,6 +574,11 @@ class OpenACCCopyOutClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::CopyOut || + C->getClauseKind() == OpenACCClauseKind::PCopyOut || + C->getClauseKind() == OpenACCClauseKind::PresentOrCopyOut; + } bool isZero() const { return IsZero; } static OpenACCCopyOutClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, @@ -542,6 +606,11 @@ class OpenACCCreateClause final } public: + static bool classof(const OpenACCClause *C) { + return C->getClauseKind() == OpenACCClauseKind::Create || + C->getClauseKind() == OpenACCClauseKind::PCreate || + C->getClauseKind() == OpenACCClauseKind::PresentOrCreate; + } bool isZero() const { return IsZero; } static OpenACCCreateClause * Create(const ASTContext &C, OpenACCClauseKind Spelling, diff --git a/clang/include/clang/AST/StmtOpenACC.h b/clang/include/clang/AST/StmtOpenACC.h index 66f8f844e0b2..b706864798ba 100644 --- a/clang/include/clang/AST/StmtOpenACC.h +++ b/clang/include/clang/AST/StmtOpenACC.h @@ -93,6 +93,10 @@ protected: } public: + static bool classof(const Stmt *T) { + return false; + } + child_range children() { if (getAssociatedStmt()) return child_range(&AssociatedStmt, &AssociatedStmt + 1); diff --git a/clang/lib/AST/OpenACCClause.cpp b/clang/lib/AST/OpenACCClause.cpp index be079556a87a..ee13437b97b4 100644 --- a/clang/lib/AST/OpenACCClause.cpp +++ b/clang/lib/AST/OpenACCClause.cpp @@ -17,6 +17,33 @@ using namespace clang; +bool OpenACCClauseWithParams::classof(const OpenACCClause *C) { + return OpenACCClauseWithCondition::classof(C) || + OpenACCClauseWithExprs::classof(C); +} +bool OpenACCClauseWithExprs::classof(const OpenACCClause *C) { + return OpenACCWaitClause::classof(C) || OpenACCNumGangsClause::classof(C) || + OpenACCClauseWithSingleIntExpr::classof(C) || + OpenACCClauseWithVarList::classof(C); +} +bool OpenACCClauseWithVarList::classof(const OpenACCClause *C) { + return OpenACCPrivateClause::classof(C) || + OpenACCFirstPrivateClause::classof(C) || + OpenACCDevicePtrClause::classof(C) || + OpenACCDevicePtrClause::classof(C) || + OpenACCAttachClause::classof(C) || OpenACCNoCreateClause::classof(C) || + OpenACCPresentClause::classof(C) || OpenACCCopyClause::classof(C) || + OpenACCCopyInClause::classof(C) || OpenACCCopyOutClause::classof(C) || + OpenACCCreateClause::classof(C); +} +bool OpenACCClauseWithCondition::classof(const OpenACCClause *C) { + return OpenACCIfClause::classof(C) || OpenACCSelfClause::classof(C); +} +bool OpenACCClauseWithSingleIntExpr::classof(const OpenACCClause *C) { + return OpenACCNumWorkersClause::classof(C) || + OpenACCVectorLengthClause::classof(C) || + OpenACCAsyncClause::classof(C); +} OpenACCDefaultClause *OpenACCDefaultClause::Create(const ASTContext &C, OpenACCDefaultClauseKind K, SourceLocation BeginLoc, diff --git a/clang/lib/Serialization/ASTWriter.cpp b/clang/lib/Serialization/ASTWriter.cpp index e7b9050165bb..ab07cf3efa45 100644 --- a/clang/lib/Serialization/ASTWriter.cpp +++ b/clang/lib/Serialization/ASTWriter.cpp @@ -7816,7 +7816,7 @@ void ASTRecordWriter::writeOpenACCClause(const OpenACCClause *C) { return; } case OpenACCClauseKind::Self: { - const auto *SC = cast(C); + const auto *SC = cast(C); writeSourceLocation(SC->getLParenLoc()); writeBool(SC->hasConditionExpr()); if (SC->hasConditionExpr()) -- GitLab From 331f22af4b4c849a97c97e6803e0c8cab57fa10b Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 10 May 2024 15:04:38 +0100 Subject: [PATCH 038/824] [AMDGPU] Remove unnecessary predicates from aliases. NFC. (#91602) So long as the target of the alias is predicated with HasImageInsts or similar, the alias itself does not need this predicate. --- llvm/lib/Target/AMDGPU/EXPInstructions.td | 1 - llvm/lib/Target/AMDGPU/MIMGInstructions.td | 1 - 2 files changed, 2 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/EXPInstructions.td b/llvm/lib/Target/AMDGPU/EXPInstructions.td index e02652e62a57..5e426b5acd50 100644 --- a/llvm/lib/Target/AMDGPU/EXPInstructions.td +++ b/llvm/lib/Target/AMDGPU/EXPInstructions.td @@ -125,7 +125,6 @@ multiclass VEXPORT_Real_gfx12 { } def : AMDGPUMnemonicAlias<"exp", "export"> { let AssemblerPredicate = isGFX12Plus; - let OtherPredicates = [HasExportInsts]; } } diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td index 9f6277f1257f..351263d07976 100644 --- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td +++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td @@ -1079,7 +1079,6 @@ multiclass MIMG_Atomic_Addr_Helper_m { let AssemblerPredicate = isGFX12Plus; - let OtherPredicates = [HasImageInsts]; bit IsAtomicRet; // Unused MIMGBaseOpcode BaseOpcode; // Unused int VDataDwords; // Unused -- GitLab From 52271a5c11f6abde1fa1221db304212b5eb8ec7c Mon Sep 17 00:00:00 2001 From: Hui Date: Fri, 10 May 2024 15:13:00 +0100 Subject: [PATCH 039/824] [libc++] Make `constexpr std::variant`. Implement P2231R1 (#83335) Fixes #86686 --- libcxx/docs/ReleaseNotes/19.rst | 1 + libcxx/docs/Status/Cxx20.rst | 1 - libcxx/docs/Status/Cxx20Papers.csv | 2 +- libcxx/include/variant | 212 ++++---- .../variant.variant/variant.assign/T.pass.cpp | 202 ++++++- .../variant.assign/copy.pass.cpp | 430 +++++++++------ .../variant.assign/move.pass.cpp | 316 ++++++----- .../variant.ctor/copy.pass.cpp | 106 ++-- .../variant.ctor/default.pass.cpp | 26 +- .../variant.ctor/move.pass.cpp | 113 ++-- .../variant.dtor/dtor.pass.cpp | 71 ++- .../variant.mod/emplace_index_args.pass.cpp | 44 +- .../emplace_index_init_list_args.pass.cpp | 35 +- .../variant.mod/emplace_type_args.pass.cpp | 51 +- .../emplace_type_init_list_args.pass.cpp | 44 +- .../variant.swap/swap.pass.cpp | 504 +++++++++--------- 16 files changed, 1322 insertions(+), 836 deletions(-) diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 3fc007f45985..83fcd40bb80c 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -52,6 +52,7 @@ Implemented Papers - P3029R1 - Better ``mdspan``'s CTAD - P2387R3 - Pipe support for user-defined range adaptors - P2713R1 - Escaping improvements in ``std::format`` +- P2231R1 - Missing ``constexpr`` in ``std::optional`` and ``std::variant`` Improvements and New Features ----------------------------- diff --git a/libcxx/docs/Status/Cxx20.rst b/libcxx/docs/Status/Cxx20.rst index 23289dc6e596..b08b99394fbb 100644 --- a/libcxx/docs/Status/Cxx20.rst +++ b/libcxx/docs/Status/Cxx20.rst @@ -47,7 +47,6 @@ Paper Status .. [#note-P0619] P0619: Only sections D.8, D.9, D.10 and D.13 are implemented. Sections D.4, D.7, D.11, and D.12 remain undone. .. [#note-P0883.1] P0883: shared_ptr and floating-point changes weren't applied as they themselves aren't implemented yet. .. [#note-P0883.2] P0883: ``ATOMIC_FLAG_INIT`` was marked deprecated in version 14.0, but was undeprecated with the implementation of LWG3659 in version 15.0. - .. [#note-P2231] P2231: Optional is complete. The changes to variant haven't been implemented yet. .. [#note-P0660] P0660: The paper is implemented but the features are experimental and can be enabled via ``-fexperimental-library``. .. [#note-P0355] P0355: The implementation status is: diff --git a/libcxx/docs/Status/Cxx20Papers.csv b/libcxx/docs/Status/Cxx20Papers.csv index d31720b7576d..955aa5f614af 100644 --- a/libcxx/docs/Status/Cxx20Papers.csv +++ b/libcxx/docs/Status/Cxx20Papers.csv @@ -192,7 +192,7 @@ "`P2106R0 `__","LWG","Alternative wording for GB315 and GB316","Prague","|Complete|","15.0","|ranges|" "`P2116R0 `__","LWG","Remove tuple-like protocol support from fixed-extent span","Prague","|Complete|","11.0" "","","","","","","" -"`P2231R1 `__","LWG","Missing constexpr in std::optional and std::variant","June 2021","|Partial| [#note-P2231]_","13.0" +"`P2231R1 `__","LWG","Missing constexpr in std::optional and std::variant","June 2021","|Complete|","19.0" "`P2325R3 `__","LWG","Views should not be required to be default constructible","June 2021","|Complete|","16.0","|ranges|" "`P2210R2 `__","LWG","Superior String Splitting","June 2021","|Complete|","16.0","|ranges|" "`P2216R3 `__","LWG","std::format improvements","June 2021","|Complete|","15.0" diff --git a/libcxx/include/variant b/libcxx/include/variant index 34150bd45284..631ffceab5f6 100644 --- a/libcxx/include/variant +++ b/libcxx/include/variant @@ -42,26 +42,28 @@ namespace std { in_place_index_t, initializer_list, Args&&...); // 20.7.2.2, destructor - ~variant(); + constexpr ~variant(); // constexpr since c++20 // 20.7.2.3, assignment constexpr variant& operator=(const variant&); constexpr variant& operator=(variant&&) noexcept(see below); - template variant& operator=(T&&) noexcept(see below); + template + constexpr variant& operator=(T&&) noexcept(see below); // constexpr since c++20 // 20.7.2.4, modifiers template - T& emplace(Args&&...); + constexpr T& emplace(Args&&...); // constexpr since c++20 template - T& emplace(initializer_list, Args&&...); + constexpr T& emplace(initializer_list, Args&&...); // constexpr since c++20 template - variant_alternative_t& emplace(Args&&...); + constexpr variant_alternative_t& emplace(Args&&...); // constexpr since c++20 template - variant_alternative_t& emplace(initializer_list, Args&&...); + constexpr variant_alternative_t& + emplace(initializer_list, Args&&...); // constexpr since c++20 // 20.7.2.5, value status constexpr bool valueless_by_exception() const noexcept; @@ -221,6 +223,7 @@ namespace std { #include <__functional/operations.h> #include <__functional/unary_function.h> #include <__memory/addressof.h> +#include <__memory/construct_at.h> #include <__tuple/find_index.h> #include <__tuple/sfinae_helpers.h> #include <__type_traits/add_const.h> @@ -663,7 +666,8 @@ private: template struct _LIBCPP_TEMPLATE_VIS __alt { - using __value_type = _Tp; + using __value_type = _Tp; + static constexpr size_t __index = _Index; template _LIBCPP_HIDE_FROM_ABI explicit constexpr __alt(in_place_t, _Args&&... __args) @@ -678,7 +682,7 @@ union _LIBCPP_TEMPLATE_VIS __union; template <_Trait _DestructibleTrait, size_t _Index> union _LIBCPP_TEMPLATE_VIS __union<_DestructibleTrait, _Index> {}; -# define _LIBCPP_VARIANT_UNION(destructible_trait, destructor) \ +# define _LIBCPP_VARIANT_UNION(destructible_trait, destructor_definition) \ template \ union _LIBCPP_TEMPLATE_VIS __union { \ public: \ @@ -692,13 +696,11 @@ union _LIBCPP_TEMPLATE_VIS __union<_DestructibleTrait, _Index> {}; _LIBCPP_HIDE_FROM_ABI explicit constexpr __union(in_place_index_t<_Ip>, _Args&&... __args) \ : __tail(in_place_index<_Ip - 1>, std::forward<_Args>(__args)...) {} \ \ - __union(const __union&) = default; \ - __union(__union&&) = default; \ - \ - destructor; \ - \ - __union& operator=(const __union&) = default; \ - __union& operator=(__union&&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union(const __union&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union(__union&&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union& operator=(const __union&) = default; \ + _LIBCPP_HIDE_FROM_ABI __union& operator=(__union&&) = default; \ + destructor_definition; \ \ private: \ char __dummy; \ @@ -708,10 +710,11 @@ union _LIBCPP_TEMPLATE_VIS __union<_DestructibleTrait, _Index> {}; friend struct __access::__union; \ } -_LIBCPP_VARIANT_UNION(_Trait::_TriviallyAvailable, ~__union() = default); +_LIBCPP_VARIANT_UNION(_Trait::_TriviallyAvailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__union() = default); _LIBCPP_VARIANT_UNION( - _Trait::_Available, _LIBCPP_HIDE_FROM_ABI ~__union() {} _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_UNION(_Trait::_Unavailable, ~__union() = delete); + _Trait::_Available, _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__union() {} _LIBCPP_EAT_SEMICOLON); +_LIBCPP_VARIANT_UNION(_Trait::_Unavailable, _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__union() = delete); # undef _LIBCPP_VARIANT_UNION @@ -754,7 +757,7 @@ protected: template class _LIBCPP_TEMPLATE_VIS __dtor; -# define _LIBCPP_VARIANT_DESTRUCTOR(destructible_trait, destructor, destroy) \ +# define _LIBCPP_VARIANT_DESTRUCTOR(destructible_trait, destructor_definition, destroy) \ template \ class _LIBCPP_TEMPLATE_VIS __dtor<__traits<_Types...>, destructible_trait> \ : public __base { \ @@ -764,28 +767,27 @@ class _LIBCPP_TEMPLATE_VIS __dtor; public: \ using __base_type::__base_type; \ using __base_type::operator=; \ - \ - __dtor(const __dtor&) = default; \ - __dtor(__dtor&&) = default; \ - __dtor& operator=(const __dtor&) = default; \ - __dtor& operator=(__dtor&&) = default; \ - destructor; \ + _LIBCPP_HIDE_FROM_ABI __dtor(const __dtor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __dtor(__dtor&&) = default; \ + _LIBCPP_HIDE_FROM_ABI __dtor& operator=(const __dtor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __dtor& operator=(__dtor&&) = default; \ + destructor_definition; \ \ protected: \ - inline _LIBCPP_HIDE_FROM_ABI destroy; \ + destroy; \ } _LIBCPP_VARIANT_DESTRUCTOR( _Trait::_TriviallyAvailable, - ~__dtor() = default, // - _LIBCPP_HIDE_FROM_ABI void __destroy() noexcept { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__dtor() = default, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __destroy() noexcept { this->__index = __variant_npos<__index_t>; } _LIBCPP_EAT_SEMICOLON); _LIBCPP_VARIANT_DESTRUCTOR( _Trait::_Available, - _LIBCPP_HIDE_FROM_ABI ~__dtor() { __destroy(); } _LIBCPP_EAT_SEMICOLON, - _LIBCPP_HIDE_FROM_ABI void __destroy() noexcept { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__dtor() { __destroy(); } _LIBCPP_EAT_SEMICOLON, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __destroy() noexcept { if (!this->valueless_by_exception()) { __visitation::__base::__visit_alt( [](auto& __alt) noexcept { @@ -797,7 +799,9 @@ _LIBCPP_VARIANT_DESTRUCTOR( this->__index = __variant_npos<__index_t>; } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_DESTRUCTOR(_Trait::_Unavailable, ~__dtor() = delete, void __destroy() noexcept = delete); +_LIBCPP_VARIANT_DESTRUCTOR(_Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~__dtor() = delete, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __destroy() noexcept = delete); # undef _LIBCPP_VARIANT_DESTRUCTOR @@ -810,23 +814,18 @@ public: using __base_type::operator=; protected: - template - _LIBCPP_HIDE_FROM_ABI static _Tp& __construct_alt(__alt<_Ip, _Tp>& __a, _Args&&... __args) { - ::new ((void*)std::addressof(__a)) __alt<_Ip, _Tp>(in_place, std::forward<_Args>(__args)...); - return __a.__value; - } - template - _LIBCPP_HIDE_FROM_ABI static void __generic_construct(__ctor& __lhs, _Rhs&& __rhs) { + _LIBCPP_HIDE_FROM_ABI static _LIBCPP_CONSTEXPR_SINCE_CXX20 void __generic_construct(__ctor& __lhs, _Rhs&& __rhs) { __lhs.__destroy(); if (!__rhs.valueless_by_exception()) { auto __rhs_index = __rhs.index(); __visitation::__base::__visit_alt_at( __rhs_index, - [](auto& __lhs_alt, auto&& __rhs_alt) { - __construct_alt(__lhs_alt, std::forward(__rhs_alt).__value); + [&__lhs](auto&& __rhs_alt) { + std::__construct_at(std::addressof(__lhs.__data), + in_place_index<__decay_t::__index>, + std::forward(__rhs_alt).__value); }, - __lhs, std::forward<_Rhs>(__rhs)); __lhs.__index = __rhs_index; } @@ -836,7 +835,7 @@ protected: template class _LIBCPP_TEMPLATE_VIS __move_constructor; -# define _LIBCPP_VARIANT_MOVE_CONSTRUCTOR(move_constructible_trait, move_constructor) \ +# define _LIBCPP_VARIANT_MOVE_CONSTRUCTOR(move_constructible_trait, move_constructor_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __move_constructor<__traits<_Types...>, move_constructible_trait> \ : public __ctor<__traits<_Types...>> { \ @@ -846,32 +845,35 @@ class _LIBCPP_TEMPLATE_VIS __move_constructor; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __move_constructor(const __move_constructor&) = default; \ - ~__move_constructor() = default; \ - __move_constructor& operator=(const __move_constructor&) = default; \ - __move_constructor& operator=(__move_constructor&&) = default; \ - move_constructor; \ + _LIBCPP_HIDE_FROM_ABI __move_constructor(const __move_constructor&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__move_constructor() = default; \ + _LIBCPP_HIDE_FROM_ABI __move_constructor& operator=(const __move_constructor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __move_constructor& operator=(__move_constructor&&) = default; \ + move_constructor_definition; \ } -_LIBCPP_VARIANT_MOVE_CONSTRUCTOR(_Trait::_TriviallyAvailable, - __move_constructor(__move_constructor&& __that) = default); +_LIBCPP_VARIANT_MOVE_CONSTRUCTOR( + _Trait::_TriviallyAvailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_constructor(__move_constructor&& __that) = default); _LIBCPP_VARIANT_MOVE_CONSTRUCTOR( _Trait::_Available, - _LIBCPP_HIDE_FROM_ABI __move_constructor(__move_constructor&& __that) noexcept( + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_constructor(__move_constructor&& __that) noexcept( __all...>::value) : __move_constructor(__valueless_t{}) { this->__generic_construct(*this, std::move(__that)); } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_MOVE_CONSTRUCTOR(_Trait::_Unavailable, __move_constructor(__move_constructor&&) = delete); +_LIBCPP_VARIANT_MOVE_CONSTRUCTOR( + _Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_constructor(__move_constructor&&) = delete); # undef _LIBCPP_VARIANT_MOVE_CONSTRUCTOR template class _LIBCPP_TEMPLATE_VIS __copy_constructor; -# define _LIBCPP_VARIANT_COPY_CONSTRUCTOR(copy_constructible_trait, copy_constructor) \ +# define _LIBCPP_VARIANT_COPY_CONSTRUCTOR(copy_constructible_trait, copy_constructor_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __copy_constructor<__traits<_Types...>, copy_constructible_trait> \ : public __move_constructor<__traits<_Types...>> { \ @@ -881,21 +883,25 @@ class _LIBCPP_TEMPLATE_VIS __copy_constructor; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __copy_constructor(__copy_constructor&&) = default; \ - ~__copy_constructor() = default; \ - __copy_constructor& operator=(const __copy_constructor&) = default; \ - __copy_constructor& operator=(__copy_constructor&&) = default; \ - copy_constructor; \ - } // namespace __variant_detail + _LIBCPP_HIDE_FROM_ABI __copy_constructor(__copy_constructor&&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__copy_constructor() = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_constructor& operator=(const __copy_constructor&) = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_constructor& operator=(__copy_constructor&&) = default; \ + copy_constructor_definition; \ + } -_LIBCPP_VARIANT_COPY_CONSTRUCTOR(_Trait::_TriviallyAvailable, - __copy_constructor(const __copy_constructor& __that) = default); +_LIBCPP_VARIANT_COPY_CONSTRUCTOR( + _Trait::_TriviallyAvailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_constructor(const __copy_constructor& __that) = default); _LIBCPP_VARIANT_COPY_CONSTRUCTOR( - _Trait::_Available, _LIBCPP_HIDE_FROM_ABI __copy_constructor(const __copy_constructor& __that) + _Trait::_Available, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_constructor(const __copy_constructor& __that) : __copy_constructor(__valueless_t{}) { this->__generic_construct(*this, __that); } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_COPY_CONSTRUCTOR(_Trait::_Unavailable, __copy_constructor(const __copy_constructor&) = delete); +_LIBCPP_VARIANT_COPY_CONSTRUCTOR( + _Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_constructor(const __copy_constructor&) = delete); # undef _LIBCPP_VARIANT_COPY_CONSTRUCTOR @@ -908,22 +914,24 @@ public: using __base_type::operator=; template - _LIBCPP_HIDE_FROM_ABI auto& __emplace(_Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 auto& __emplace(_Args&&... __args) { this->__destroy(); - auto& __res = this->__construct_alt(__access::__base::__get_alt<_Ip>(*this), std::forward<_Args>(__args)...); + std::__construct_at(std::addressof(this->__data), in_place_index<_Ip>, std::forward<_Args>(__args)...); this->__index = _Ip; - return __res; + return __access::__base::__get_alt<_Ip>(*this).__value; } protected: template - _LIBCPP_HIDE_FROM_ABI void __assign_alt(__alt<_Ip, _Tp>& __a, _Arg&& __arg) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __assign_alt(__alt<_Ip, _Tp>& __a, _Arg&& __arg) { if (this->index() == _Ip) { __a.__value = std::forward<_Arg>(__arg); } else { struct { - _LIBCPP_HIDDEN void operator()(true_type) const { __this->__emplace<_Ip>(std::forward<_Arg>(__arg)); } - _LIBCPP_HIDDEN void operator()(false_type) const { + _LIBCPP_HIDDEN _LIBCPP_CONSTEXPR_SINCE_CXX20 void operator()(true_type) const { + __this->__emplace<_Ip>(std::forward<_Arg>(__arg)); + } + _LIBCPP_HIDDEN _LIBCPP_CONSTEXPR_SINCE_CXX20 void operator()(false_type) const { __this->__emplace<_Ip>(_Tp(std::forward<_Arg>(__arg))); } __assignment* __this; @@ -934,7 +942,7 @@ protected: } template - _LIBCPP_HIDE_FROM_ABI void __generic_assign(_That&& __that) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __generic_assign(_That&& __that) { if (this->valueless_by_exception() && __that.valueless_by_exception()) { // do nothing. } else if (__that.valueless_by_exception()) { @@ -954,7 +962,7 @@ protected: template class _LIBCPP_TEMPLATE_VIS __move_assignment; -# define _LIBCPP_VARIANT_MOVE_ASSIGNMENT(move_assignable_trait, move_assignment) \ +# define _LIBCPP_VARIANT_MOVE_ASSIGNMENT(move_assignable_trait, move_assignment_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __move_assignment<__traits<_Types...>, move_assignable_trait> \ : public __assignment<__traits<_Types...>> { \ @@ -964,33 +972,36 @@ class _LIBCPP_TEMPLATE_VIS __move_assignment; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __move_assignment(const __move_assignment&) = default; \ - __move_assignment(__move_assignment&&) = default; \ - ~__move_assignment() = default; \ - __move_assignment& operator=(const __move_assignment&) = default; \ - move_assignment; \ + _LIBCPP_HIDE_FROM_ABI __move_assignment(const __move_assignment&) = default; \ + _LIBCPP_HIDE_FROM_ABI __move_assignment(__move_assignment&&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__move_assignment() = default; \ + _LIBCPP_HIDE_FROM_ABI __move_assignment& operator=(const __move_assignment&) = default; \ + move_assignment_definition; \ } _LIBCPP_VARIANT_MOVE_ASSIGNMENT(_Trait::_TriviallyAvailable, - __move_assignment& operator=(__move_assignment&& __that) = default); + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_assignment& operator=( + __move_assignment&& __that) = default); _LIBCPP_VARIANT_MOVE_ASSIGNMENT( _Trait::_Available, - _LIBCPP_HIDE_FROM_ABI __move_assignment& + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_assignment& operator=(__move_assignment&& __that) noexcept( __all<(is_nothrow_move_constructible_v<_Types> && is_nothrow_move_assignable_v<_Types>)...>::value) { this->__generic_assign(std::move(__that)); return *this; } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_MOVE_ASSIGNMENT(_Trait::_Unavailable, __move_assignment& operator=(__move_assignment&&) = delete); +_LIBCPP_VARIANT_MOVE_ASSIGNMENT( + _Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __move_assignment& operator=(__move_assignment&&) = delete); # undef _LIBCPP_VARIANT_MOVE_ASSIGNMENT template class _LIBCPP_TEMPLATE_VIS __copy_assignment; -# define _LIBCPP_VARIANT_COPY_ASSIGNMENT(copy_assignable_trait, copy_assignment) \ +# define _LIBCPP_VARIANT_COPY_ASSIGNMENT(copy_assignable_trait, copy_assignment_definition) \ template \ class _LIBCPP_TEMPLATE_VIS __copy_assignment<__traits<_Types...>, copy_assignable_trait> \ : public __move_assignment<__traits<_Types...>> { \ @@ -1000,23 +1011,28 @@ class _LIBCPP_TEMPLATE_VIS __copy_assignment; using __base_type::__base_type; \ using __base_type::operator=; \ \ - __copy_assignment(const __copy_assignment&) = default; \ - __copy_assignment(__copy_assignment&&) = default; \ - ~__copy_assignment() = default; \ - __copy_assignment& operator=(__copy_assignment&&) = default; \ - copy_assignment; \ + _LIBCPP_HIDE_FROM_ABI __copy_assignment(const __copy_assignment&) = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_assignment(__copy_assignment&&) = default; \ + _LIBCPP_HIDE_FROM_ABI ~__copy_assignment() = default; \ + _LIBCPP_HIDE_FROM_ABI __copy_assignment& operator=(__copy_assignment&&) = default; \ + copy_assignment_definition; \ } _LIBCPP_VARIANT_COPY_ASSIGNMENT(_Trait::_TriviallyAvailable, - __copy_assignment& operator=(const __copy_assignment& __that) = default); + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_assignment& operator=( + const __copy_assignment& __that) = default); _LIBCPP_VARIANT_COPY_ASSIGNMENT( - _Trait::_Available, _LIBCPP_HIDE_FROM_ABI __copy_assignment& operator=(const __copy_assignment& __that) { + _Trait::_Available, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_assignment& + operator=(const __copy_assignment& __that) { this->__generic_assign(__that); return *this; } _LIBCPP_EAT_SEMICOLON); -_LIBCPP_VARIANT_COPY_ASSIGNMENT(_Trait::_Unavailable, __copy_assignment& operator=(const __copy_assignment&) = delete); +_LIBCPP_VARIANT_COPY_ASSIGNMENT(_Trait::_Unavailable, + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __copy_assignment& operator=( + const __copy_assignment&) = delete); # undef _LIBCPP_VARIANT_COPY_ASSIGNMENT @@ -1032,11 +1048,11 @@ public: _LIBCPP_HIDE_FROM_ABI __impl& operator=(__impl&&) = default; template - _LIBCPP_HIDE_FROM_ABI void __assign(_Arg&& __arg) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __assign(_Arg&& __arg) { this->__assign_alt(__access::__base::__get_alt<_Ip>(*this), std::forward<_Arg>(__arg)); } - inline _LIBCPP_HIDE_FROM_ABI void __swap(__impl& __that) { + inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void __swap(__impl& __that) { if (this->valueless_by_exception() && __that.valueless_by_exception()) { // do nothing. } else if (this->index() == __that.index()) { @@ -1081,7 +1097,7 @@ public: } private: - inline _LIBCPP_HIDE_FROM_ABI bool __move_nothrow() const { + constexpr inline _LIBCPP_HIDE_FROM_ABI bool __move_nothrow() const { constexpr bool __results[] = {is_nothrow_move_constructible_v<_Types>...}; return this->valueless_by_exception() || __results[this->index()]; } @@ -1223,7 +1239,7 @@ public: _Args&&... __args) noexcept(is_nothrow_constructible_v<_Tp, initializer_list< _Up>&, _Args...>) : __impl_(in_place_index<_Ip>, __il, std::forward<_Args>(__args)...) {} - _LIBCPP_HIDE_FROM_ABI ~variant() = default; + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 ~variant() = default; _LIBCPP_HIDE_FROM_ABI constexpr variant& operator=(const variant&) = default; _LIBCPP_HIDE_FROM_ABI constexpr variant& operator=(variant&&) = default; @@ -1233,7 +1249,7 @@ public: class _Tp = __variant_detail::__best_match_t<_Arg, _Types...>, size_t _Ip = __find_detail::__find_unambiguous_index_sfinae<_Tp, _Types...>::value, enable_if_t && is_constructible_v<_Tp, _Arg>, int> = 0> - _LIBCPP_HIDE_FROM_ABI variant& + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 variant& operator=(_Arg&& __arg) noexcept(is_nothrow_assignable_v<_Tp&, _Arg> && is_nothrow_constructible_v<_Tp, _Arg>) { __impl_.template __assign<_Ip>(std::forward<_Arg>(__arg)); return *this; @@ -1244,7 +1260,7 @@ public: enable_if_t<(_Ip < sizeof...(_Types)), int> = 0, class _Tp = variant_alternative_t<_Ip, variant<_Types...>>, enable_if_t, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(_Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(_Args&&... __args) { return __impl_.template __emplace<_Ip>(std::forward<_Args>(__args)...); } @@ -1254,7 +1270,7 @@ public: enable_if_t<(_Ip < sizeof...(_Types)), int> = 0, class _Tp = variant_alternative_t<_Ip, variant<_Types...>>, enable_if_t&, _Args...>, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { return __impl_.template __emplace<_Ip>(__il, std::forward<_Args>(__args)...); } @@ -1262,7 +1278,7 @@ public: class... _Args, size_t _Ip = __find_detail::__find_unambiguous_index_sfinae<_Tp, _Types...>::value, enable_if_t, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(_Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(_Args&&... __args) { return __impl_.template __emplace<_Ip>(std::forward<_Args>(__args)...); } @@ -1271,7 +1287,7 @@ public: class... _Args, size_t _Ip = __find_detail::__find_unambiguous_index_sfinae<_Tp, _Types...>::value, enable_if_t&, _Args...>, int> = 0> - _LIBCPP_HIDE_FROM_ABI _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _Tp& emplace(initializer_list<_Up> __il, _Args&&... __args) { return __impl_.template __emplace<_Ip>(__il, std::forward<_Args>(__args)...); } @@ -1285,7 +1301,7 @@ public: enable_if_t< __all<(__dependent_type, _Dummy>::value && __dependent_type, _Dummy>::value)...>::value, int> = 0> - _LIBCPP_HIDE_FROM_ABI void swap(variant& __that) noexcept( + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 void swap(variant& __that) noexcept( __all<(is_nothrow_move_constructible_v<_Types> && is_nothrow_swappable_v<_Types>)...>::value) { __impl_.__swap(__that.__impl_); } @@ -1568,7 +1584,7 @@ visit(_Visitor&& __visitor, _Vs&&... __vs) { # endif template -_LIBCPP_HIDE_FROM_ABI auto +_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 auto swap(variant<_Types...>& __lhs, variant<_Types...>& __rhs) noexcept(noexcept(__lhs.swap(__rhs))) -> decltype(__lhs.swap(__rhs)) { return __lhs.swap(__rhs); diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp index 4b9eaba2d2ba..98faf84fa52d 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/T.pass.cpp @@ -33,17 +33,17 @@ struct Dummy { struct ThrowsCtorT { ThrowsCtorT(int) noexcept(false) {} - ThrowsCtorT &operator=(int) noexcept { return *this; } + ThrowsCtorT& operator=(int) noexcept { return *this; } }; struct ThrowsAssignT { ThrowsAssignT(int) noexcept {} - ThrowsAssignT &operator=(int) noexcept(false) { return *this; } + ThrowsAssignT& operator=(int) noexcept(false) { return *this; } }; struct NoThrowT { NoThrowT(int) noexcept {} - NoThrowT &operator=(int) noexcept { return *this; } + NoThrowT& operator=(int) noexcept { return *this; } }; } // namespace MetaHelpers @@ -55,7 +55,7 @@ struct ThrowsCtorT { int value; ThrowsCtorT() : value(0) {} ThrowsCtorT(int) noexcept(false) { throw 42; } - ThrowsCtorT &operator=(int v) noexcept { + ThrowsCtorT& operator=(int v) noexcept { value = v; return *this; } @@ -64,9 +64,12 @@ struct ThrowsCtorT { struct MoveCrashes { int value; MoveCrashes(int v = 0) noexcept : value{v} {} - MoveCrashes(MoveCrashes &&) noexcept { assert(false); } - MoveCrashes &operator=(MoveCrashes &&) noexcept { assert(false); return *this; } - MoveCrashes &operator=(int v) noexcept { + MoveCrashes(MoveCrashes&&) noexcept { assert(false); } + MoveCrashes& operator=(MoveCrashes&&) noexcept { + assert(false); + return *this; + } + MoveCrashes& operator=(int v) noexcept { value = v; return *this; } @@ -76,8 +79,8 @@ struct ThrowsCtorTandMove { int value; ThrowsCtorTandMove() : value(0) {} ThrowsCtorTandMove(int) noexcept(false) { throw 42; } - ThrowsCtorTandMove(ThrowsCtorTandMove &&) noexcept(false) { assert(false); } - ThrowsCtorTandMove &operator=(int v) noexcept { + ThrowsCtorTandMove(ThrowsCtorTandMove&&) noexcept(false) { assert(false); } + ThrowsCtorTandMove& operator=(int v) noexcept { value = v; return *this; } @@ -87,14 +90,14 @@ struct ThrowsAssignT { int value; ThrowsAssignT() : value(0) {} ThrowsAssignT(int v) noexcept : value(v) {} - ThrowsAssignT &operator=(int) noexcept(false) { throw 42; } + ThrowsAssignT& operator=(int) noexcept(false) { throw 42; } }; struct NoThrowT { int value; NoThrowT() : value(0) {} NoThrowT(int v) noexcept : value(v) {} - NoThrowT &operator=(int v) noexcept { + NoThrowT& operator=(int v) noexcept { value = v; return *this; } @@ -103,7 +106,7 @@ struct NoThrowT { #endif // !defined(TEST_HAS_NO_EXCEPTIONS) } // namespace RuntimeHelpers -void test_T_assignment_noexcept() { +constexpr void test_T_assignment_noexcept() { using namespace MetaHelpers; { using V = std::variant; @@ -119,17 +122,17 @@ void test_T_assignment_noexcept() { } } -void test_T_assignment_sfinae() { +constexpr void test_T_assignment_sfinae() { { using V = std::variant; static_assert(!std::is_assignable::value, "ambiguous"); } { using V = std::variant; - static_assert(!std::is_assignable::value, "ambiguous"); + static_assert(!std::is_assignable::value, "ambiguous"); } { - using V = std::variant; + using V = std::variant; static_assert(!std::is_assignable::value, "no matching operator="); } { @@ -138,8 +141,7 @@ void test_T_assignment_sfinae() { } { using V = std::variant, bool>; - static_assert(!std::is_assignable>::value, - "no explicit bool in operator="); + static_assert(!std::is_assignable>::value, "no explicit bool in operator="); struct X { operator void*(); }; @@ -152,12 +154,11 @@ void test_T_assignment_sfinae() { operator X(); }; using V = std::variant; - static_assert(std::is_assignable::value, - "regression on user-defined conversions in operator="); + static_assert(std::is_assignable::value, "regression on user-defined conversions in operator="); } } -void test_T_assignment_basic() { +TEST_CONSTEXPR_CXX20 void test_T_assignment_basic() { { std::variant v(43); v = 42; @@ -184,19 +185,146 @@ void test_T_assignment_basic() { } { std::variant v = true; - v = "bar"; + v = "bar"; assert(v.index() == 0); assert(std::get<0>(v) == "bar"); } +} + +void test_T_assignment_basic_no_constexpr() { + std::variant> v; + v = nullptr; + assert(v.index() == 1); + assert(std::get<1>(v) == nullptr); +} + +struct TraceStat { + int construct = 0; + int copy_construct = 0; + int copy_assign = 0; + int move_construct = 0; + int move_assign = 0; + int T_copy_assign = 0; + int T_move_assign = 0; + int destroy = 0; +}; + +template +struct Trace { + struct T {}; + + constexpr Trace(TraceStat* s) noexcept(CtorNoexcept) : stat(s) { ++s->construct; } + constexpr Trace(T) noexcept(CtorNoexcept) : stat(nullptr) {} + constexpr Trace(const Trace& o) : stat(o.stat) { ++stat->copy_construct; } + constexpr Trace(Trace&& o) noexcept(MoveCtorNoexcept) : stat(o.stat) { ++stat->move_construct; } + constexpr Trace& operator=(const Trace&) { + ++stat->copy_assign; + return *this; + } + constexpr Trace& operator=(Trace&&) noexcept { + ++stat->move_assign; + return *this; + } + + constexpr Trace& operator=(const T&) { + ++stat->T_copy_assign; + return *this; + } + constexpr Trace& operator=(T&&) noexcept { + ++stat->T_move_assign; + return *this; + } + TEST_CONSTEXPR_CXX20 ~Trace() { ++stat->destroy; } + + TraceStat* stat; +}; + +TEST_CONSTEXPR_CXX20 void test_T_assignment_performs_construction() { { - std::variant> v; - v = nullptr; - assert(v.index() == 1); - assert(std::get<1>(v) == nullptr); + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 0); + } + { + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 1); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 1); + } + + { + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 0); + } + + { + using V = std::variant>; + TraceStat stat; + V v{1}; + v = &stat; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.destroy == 0); } } -void test_T_assignment_performs_construction() { +TEST_CONSTEXPR_CXX20 void test_T_assignment_performs_assignment() { + { + using V = std::variant>; + TraceStat stat; + V v{&stat}; + v = Trace::T{}; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.T_copy_assign == 0); + assert(stat.T_move_assign == 1); + assert(stat.destroy == 0); + } + { + using V = std::variant>; + TraceStat stat; + V v{&stat}; + Trace::T t; + v = t; + assert(stat.construct == 1); + assert(stat.copy_construct == 0); + assert(stat.move_construct == 0); + assert(stat.copy_assign == 0); + assert(stat.move_assign == 0); + assert(stat.T_copy_assign == 1); + assert(stat.T_move_assign == 0); + assert(stat.destroy == 0); + } +} + +void test_T_assignment_performs_construction_throw() { using namespace RuntimeHelpers; #ifndef TEST_HAS_NO_EXCEPTIONS { @@ -220,7 +348,7 @@ void test_T_assignment_performs_construction() { #endif // TEST_HAS_NO_EXCEPTIONS } -void test_T_assignment_performs_assignment() { +void test_T_assignment_performs_assignment_throw() { using namespace RuntimeHelpers; #ifndef TEST_HAS_NO_EXCEPTIONS { @@ -262,7 +390,7 @@ void test_T_assignment_performs_assignment() { #endif // TEST_HAS_NO_EXCEPTIONS } -void test_T_assignment_vector_bool() { +TEST_CONSTEXPR_CXX20 void test_T_assignment_vector_bool() { std::vector vec = {true}; std::variant v; v = vec[0]; @@ -270,7 +398,13 @@ void test_T_assignment_vector_bool() { assert(std::get<0>(v) == true); } -int main(int, char**) { +void non_constexpr_test() { + test_T_assignment_basic_no_constexpr(); + test_T_assignment_performs_construction_throw(); + test_T_assignment_performs_assignment_throw(); +} + +TEST_CONSTEXPR_CXX20 bool test() { test_T_assignment_basic(); test_T_assignment_performs_construction(); test_T_assignment_performs_assignment(); @@ -278,5 +412,15 @@ int main(int, char**) { test_T_assignment_sfinae(); test_T_assignment_vector_bool(); + return true; +} + +int main(int, char**) { + test(); + non_constexpr_test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp index 096d365d2d75..a6d3f34114eb 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/copy.pass.cpp @@ -22,88 +22,108 @@ #include "test_macros.h" struct NoCopy { - NoCopy(const NoCopy &) = delete; - NoCopy &operator=(const NoCopy &) = default; + NoCopy(const NoCopy&) = delete; + NoCopy& operator=(const NoCopy&) = default; }; struct CopyOnly { - CopyOnly(const CopyOnly &) = default; - CopyOnly(CopyOnly &&) = delete; - CopyOnly &operator=(const CopyOnly &) = default; - CopyOnly &operator=(CopyOnly &&) = delete; + CopyOnly(const CopyOnly&) = default; + CopyOnly(CopyOnly&&) = delete; + CopyOnly& operator=(const CopyOnly&) = default; + CopyOnly& operator=(CopyOnly&&) = delete; }; struct MoveOnly { - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; - MoveOnly &operator=(const MoveOnly &) = default; + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; + MoveOnly& operator=(const MoveOnly&) = default; }; struct MoveOnlyNT { - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&) {} - MoveOnlyNT &operator=(const MoveOnlyNT &) = default; + MoveOnlyNT(const MoveOnlyNT&) = delete; + MoveOnlyNT(MoveOnlyNT&&) {} + MoveOnlyNT& operator=(const MoveOnlyNT&) = default; }; struct CopyAssign { - static int alive; - static int copy_construct; - static int copy_assign; - static int move_construct; - static int move_assign; - static void reset() { - copy_construct = copy_assign = move_construct = move_assign = alive = 0; - } - CopyAssign(int v) : value(v) { ++alive; } - CopyAssign(const CopyAssign &o) : value(o.value) { - ++alive; - ++copy_construct; - } - CopyAssign(CopyAssign &&o) noexcept : value(o.value) { + constexpr CopyAssign(int v, int* alv, int* cpy_ctr, int* cpy_assi, int* move_ctr, int* move_assi) + : value(v), + alive(alv), + copy_construct(cpy_ctr), + copy_assign(cpy_assi), + move_construct(move_ctr), + move_assign(move_assi) { + ++*alive; + } + constexpr CopyAssign(const CopyAssign& o) + : value(o.value), + alive(o.alive), + copy_construct(o.copy_construct), + copy_assign(o.copy_assign), + move_construct(o.move_construct), + move_assign(o.move_assign) { + ++*alive; + ++*copy_construct; + } + constexpr CopyAssign(CopyAssign&& o) noexcept + : value(o.value), + alive(o.alive), + copy_construct(o.copy_construct), + copy_assign(o.copy_assign), + move_construct(o.move_construct), + move_assign(o.move_assign) { o.value = -1; - ++alive; - ++move_construct; - } - CopyAssign &operator=(const CopyAssign &o) { - value = o.value; - ++copy_assign; + ++*alive; + ++*move_construct; + } + constexpr CopyAssign& operator=(const CopyAssign& o) { + value = o.value; + alive = o.alive; + copy_construct = o.copy_construct; + copy_assign = o.copy_assign; + move_construct = o.move_construct; + move_assign = o.move_assign; + ++*copy_assign; return *this; } - CopyAssign &operator=(CopyAssign &&o) noexcept { - value = o.value; - o.value = -1; - ++move_assign; + constexpr CopyAssign& operator=(CopyAssign&& o) noexcept { + value = o.value; + alive = o.alive; + copy_construct = o.copy_construct; + copy_assign = o.copy_assign; + move_construct = o.move_construct; + move_assign = o.move_assign; + o.value = -1; + ++*move_assign; return *this; } - ~CopyAssign() { --alive; } + TEST_CONSTEXPR_CXX20 ~CopyAssign() { --*alive; } int value; + int* alive; + int* copy_construct; + int* copy_assign; + int* move_construct; + int* move_assign; }; -int CopyAssign::alive = 0; -int CopyAssign::copy_construct = 0; -int CopyAssign::copy_assign = 0; -int CopyAssign::move_construct = 0; -int CopyAssign::move_assign = 0; - struct CopyMaybeThrows { - CopyMaybeThrows(const CopyMaybeThrows &); - CopyMaybeThrows &operator=(const CopyMaybeThrows &); + CopyMaybeThrows(const CopyMaybeThrows&); + CopyMaybeThrows& operator=(const CopyMaybeThrows&); }; struct CopyDoesThrow { - CopyDoesThrow(const CopyDoesThrow &) noexcept(false); - CopyDoesThrow &operator=(const CopyDoesThrow &) noexcept(false); + CopyDoesThrow(const CopyDoesThrow&) noexcept(false); + CopyDoesThrow& operator=(const CopyDoesThrow&) noexcept(false); }; - struct NTCopyAssign { constexpr NTCopyAssign(int v) : value(v) {} - NTCopyAssign(const NTCopyAssign &) = default; - NTCopyAssign(NTCopyAssign &&) = default; - NTCopyAssign &operator=(const NTCopyAssign &that) { + NTCopyAssign(const NTCopyAssign&) = default; + NTCopyAssign(NTCopyAssign&&) = default; + NTCopyAssign& operator=(const NTCopyAssign& that) { value = that.value; return *this; }; - NTCopyAssign &operator=(NTCopyAssign &&) = delete; + NTCopyAssign& operator=(NTCopyAssign&&) = delete; int value; }; @@ -112,10 +132,10 @@ static_assert(std::is_copy_assignable::value, ""); struct TCopyAssign { constexpr TCopyAssign(int v) : value(v) {} - TCopyAssign(const TCopyAssign &) = default; - TCopyAssign(TCopyAssign &&) = default; - TCopyAssign &operator=(const TCopyAssign &) = default; - TCopyAssign &operator=(TCopyAssign &&) = delete; + TCopyAssign(const TCopyAssign&) = default; + TCopyAssign(TCopyAssign&&) = default; + TCopyAssign& operator=(const TCopyAssign&) = default; + TCopyAssign& operator=(TCopyAssign&&) = delete; int value; }; @@ -123,11 +143,11 @@ static_assert(std::is_trivially_copy_assignable::value, ""); struct TCopyAssignNTMoveAssign { constexpr TCopyAssignNTMoveAssign(int v) : value(v) {} - TCopyAssignNTMoveAssign(const TCopyAssignNTMoveAssign &) = default; - TCopyAssignNTMoveAssign(TCopyAssignNTMoveAssign &&) = default; - TCopyAssignNTMoveAssign &operator=(const TCopyAssignNTMoveAssign &) = default; - TCopyAssignNTMoveAssign &operator=(TCopyAssignNTMoveAssign &&that) { - value = that.value; + TCopyAssignNTMoveAssign(const TCopyAssignNTMoveAssign&) = default; + TCopyAssignNTMoveAssign(TCopyAssignNTMoveAssign&&) = default; + TCopyAssignNTMoveAssign& operator=(const TCopyAssignNTMoveAssign&) = default; + TCopyAssignNTMoveAssign& operator=(TCopyAssignNTMoveAssign&& that) { + value = that.value; that.value = -1; return *this; } @@ -139,17 +159,20 @@ static_assert(std::is_trivially_copy_assignable_v, ""); #ifndef TEST_HAS_NO_EXCEPTIONS struct CopyThrows { CopyThrows() = default; - CopyThrows(const CopyThrows &) { throw 42; } - CopyThrows &operator=(const CopyThrows &) { throw 42; } + CopyThrows(const CopyThrows&) { throw 42; } + CopyThrows& operator=(const CopyThrows&) { throw 42; } }; struct CopyCannotThrow { static int alive; CopyCannotThrow() { ++alive; } - CopyCannotThrow(const CopyCannotThrow &) noexcept { ++alive; } - CopyCannotThrow(CopyCannotThrow &&) noexcept { assert(false); } - CopyCannotThrow &operator=(const CopyCannotThrow &) noexcept = default; - CopyCannotThrow &operator=(CopyCannotThrow &&) noexcept { assert(false); return *this; } + CopyCannotThrow(const CopyCannotThrow&) noexcept { ++alive; } + CopyCannotThrow(CopyCannotThrow&&) noexcept { assert(false); } + CopyCannotThrow& operator=(const CopyCannotThrow&) noexcept = default; + CopyCannotThrow& operator=(CopyCannotThrow&&) noexcept { + assert(false); + return *this; + } }; int CopyCannotThrow::alive = 0; @@ -157,10 +180,10 @@ int CopyCannotThrow::alive = 0; struct MoveThrows { static int alive; MoveThrows() { ++alive; } - MoveThrows(const MoveThrows &) { ++alive; } - MoveThrows(MoveThrows &&) { throw 42; } - MoveThrows &operator=(const MoveThrows &) { return *this; } - MoveThrows &operator=(MoveThrows &&) { throw 42; } + MoveThrows(const MoveThrows&) { ++alive; } + MoveThrows(MoveThrows&&) { throw 42; } + MoveThrows& operator=(const MoveThrows&) { return *this; } + MoveThrows& operator=(MoveThrows&&) { throw 42; } ~MoveThrows() { --alive; } }; @@ -169,20 +192,21 @@ int MoveThrows::alive = 0; struct MakeEmptyT { static int alive; MakeEmptyT() { ++alive; } - MakeEmptyT(const MakeEmptyT &) { + MakeEmptyT(const MakeEmptyT&) { ++alive; // Don't throw from the copy constructor since variant's assignment // operator performs a copy before committing to the assignment. } - MakeEmptyT(MakeEmptyT &&) { throw 42; } - MakeEmptyT &operator=(const MakeEmptyT &) { throw 42; } - MakeEmptyT &operator=(MakeEmptyT &&) { throw 42; } + MakeEmptyT(MakeEmptyT&&) { throw 42; } + MakeEmptyT& operator=(const MakeEmptyT&) { throw 42; } + MakeEmptyT& operator=(MakeEmptyT&&) { throw 42; } ~MakeEmptyT() { --alive; } }; int MakeEmptyT::alive = 0; -template void makeEmpty(Variant &v) { +template +void makeEmpty(Variant& v) { Variant v2(std::in_place_type); try { v = std::move(v2); @@ -193,7 +217,7 @@ template void makeEmpty(Variant &v) { } #endif // TEST_HAS_NO_EXCEPTIONS -void test_copy_assignment_not_noexcept() { +constexpr void test_copy_assignment_not_noexcept() { { using V = std::variant; static_assert(!std::is_nothrow_copy_assignable::value, ""); @@ -204,7 +228,7 @@ void test_copy_assignment_not_noexcept() { } } -void test_copy_assignment_sfinae() { +constexpr void test_copy_assignment_sfinae() { { using V = std::variant; static_assert(std::is_copy_assignable::value, ""); @@ -259,7 +283,7 @@ void test_copy_assignment_empty_empty() { makeEmpty(v1); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -275,7 +299,7 @@ void test_copy_assignment_non_empty_empty() { V v1(std::in_place_index<0>, 42); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -285,7 +309,7 @@ void test_copy_assignment_non_empty_empty() { V v1(std::in_place_index<2>, "hello"); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -301,7 +325,7 @@ void test_copy_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_index<0>, 42); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -311,7 +335,7 @@ void test_copy_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_type, "hello"); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -319,14 +343,18 @@ void test_copy_assignment_empty_non_empty() { #endif // TEST_HAS_NO_EXCEPTIONS } -template struct Result { std::size_t index; T value; }; +template +struct Result { + std::size_t index; + T value; +}; -void test_copy_assignment_same_index() { +TEST_CONSTEXPR_CXX20 void test_copy_assignment_same_index() { { using V = std::variant; V v1(43); V v2(42); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -335,40 +363,28 @@ void test_copy_assignment_same_index() { using V = std::variant; V v1(43l); V v2(42l); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; - V v1(std::in_place_type, 43); - V v2(std::in_place_type, 42); - CopyAssign::reset(); - V &vref = (v1 = v2); + using V = std::variant; + int alive = 0; + int copy_construct = 0; + int copy_assign = 0; + int move_construct = 0; + int move_assign = 0; + V v1(std::in_place_type, 43, &alive, ©_construct, ©_assign, &move_construct, &move_assign); + V v2(std::in_place_type, 42, &alive, ©_construct, ©_assign, &move_construct, &move_assign); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(CopyAssign::copy_construct == 0); - assert(CopyAssign::move_construct == 0); - assert(CopyAssign::copy_assign == 1); + assert(copy_construct == 0); + assert(move_construct == 0); + assert(copy_assign == 1); } -#ifndef TEST_HAS_NO_EXCEPTIONS - using MET = MakeEmptyT; - { - using V = std::variant; - V v1(std::in_place_type); - MET &mref = std::get<1>(v1); - V v2(std::in_place_type); - try { - v1 = v2; - assert(false); - } catch (...) { - } - assert(v1.index() == 1); - assert(&std::get<1>(v1) == &mref); - } -#endif // TEST_HAS_NO_EXCEPTIONS // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). { @@ -429,34 +445,88 @@ void test_copy_assignment_same_index() { } } -void test_copy_assignment_different_index() { +TEST_CONSTEXPR_CXX20 void test_copy_assignment_different_index() { { using V = std::variant; V v1(43); V v2(42l); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; - CopyAssign::reset(); + using V = std::variant; + int alive = 0; + int copy_construct = 0; + int copy_assign = 0; + int move_construct = 0; + int move_assign = 0; V v1(std::in_place_type, 43u); - V v2(std::in_place_type, 42); - assert(CopyAssign::copy_construct == 0); - assert(CopyAssign::move_construct == 0); - assert(CopyAssign::alive == 1); - V &vref = (v1 = v2); + V v2(std::in_place_type, 42, &alive, ©_construct, ©_assign, &move_construct, &move_assign); + assert(copy_construct == 0); + assert(move_construct == 0); + assert(alive == 1); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(CopyAssign::alive == 2); - assert(CopyAssign::copy_construct == 1); - assert(CopyAssign::move_construct == 1); - assert(CopyAssign::copy_assign == 0); + assert(alive == 2); + assert(copy_construct == 1); + assert(move_construct == 1); + assert(copy_assign == 0); + } + + // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). + { + struct { + constexpr Result operator()() const { + using V = std::variant; + V v(43); + V v2(42l); + v = v2; + return {v.index(), std::get<1>(v)}; + } + } test; + constexpr auto result = test(); + static_assert(result.index == 1, ""); + static_assert(result.value == 42l, ""); } + { + struct { + constexpr Result operator()() const { + using V = std::variant; + V v(std::in_place_type, 43u); + V v2(std::in_place_type, 42); + v = v2; + return {v.index(), std::get<1>(v).value}; + } + } test; + constexpr auto result = test(); + static_assert(result.index == 1, ""); + static_assert(result.value == 42, ""); + } +} + +void test_assignment_throw() { #ifndef TEST_HAS_NO_EXCEPTIONS + using MET = MakeEmptyT; + // same index + { + using V = std::variant; + V v1(std::in_place_type); + MET& mref = std::get<1>(v1); + V v2(std::in_place_type); + try { + v1 = v2; + assert(false); + } catch (...) { + } + assert(v1.index() == 1); + assert(&std::get<1>(v1) == &mref); + } + + // difference indices { using V = std::variant; V v1(std::in_place_type, "hello"); @@ -496,7 +566,7 @@ void test_copy_assignment_different_index() { using V = std::variant; V v1(std::in_place_type); V v2(std::in_place_type, "hello"); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -507,7 +577,7 @@ void test_copy_assignment_different_index() { using V = std::variant; V v1(std::in_place_type); V v2(std::in_place_type, "hello"); - V &vref = (v1 = v2); + V& vref = (v1 = v2); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -515,69 +585,83 @@ void test_copy_assignment_different_index() { assert(std::get<2>(v2) == "hello"); } #endif // TEST_HAS_NO_EXCEPTIONS - - // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). - { - struct { - constexpr Result operator()() const { - using V = std::variant; - V v(43); - V v2(42l); - v = v2; - return {v.index(), std::get<1>(v)}; - } - } test; - constexpr auto result = test(); - static_assert(result.index == 1, ""); - static_assert(result.value == 42l, ""); - } - { - struct { - constexpr Result operator()() const { - using V = std::variant; - V v(std::in_place_type, 43u); - V v2(std::in_place_type, 42); - v = v2; - return {v.index(), std::get<1>(v).value}; - } - } test; - constexpr auto result = test(); - static_assert(result.index == 1, ""); - static_assert(result.value == 42, ""); - } } -template -constexpr bool test_constexpr_assign_imp( - std::variant&& v, ValueType&& new_value) -{ - const std::variant cp( - std::forward(new_value)); +template +constexpr void test_constexpr_assign_imp(T&& v, ValueType&& new_value) { + using Variant = std::decay_t; + const Variant cp(std::forward(new_value)); v = cp; - return v.index() == NewIdx && - std::get(v) == std::get(cp); + assert(v.index() == NewIdx); + assert(std::get(v) == std::get(cp)); } -void test_constexpr_copy_assignment() { +constexpr void test_constexpr_copy_assignment_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; static_assert(std::is_trivially_copyable::value, ""); static_assert(std::is_trivially_copy_assignable::value, ""); - static_assert(test_constexpr_assign_imp<0>(V(42l), 101l), ""); - static_assert(test_constexpr_assign_imp<0>(V(nullptr), 101l), ""); - static_assert(test_constexpr_assign_imp<1>(V(42l), nullptr), ""); - static_assert(test_constexpr_assign_imp<2>(V(42l), 101), ""); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), 101); } -int main(int, char**) { +struct NonTrivialCopyAssign { + int i = 0; + constexpr NonTrivialCopyAssign(int ii) : i(ii) {} + constexpr NonTrivialCopyAssign(const NonTrivialCopyAssign& other) : i(other.i) {} + constexpr NonTrivialCopyAssign& operator=(const NonTrivialCopyAssign& o) { + i = o.i; + return *this; + } + TEST_CONSTEXPR_CXX20 ~NonTrivialCopyAssign() = default; + friend constexpr bool operator==(const NonTrivialCopyAssign& x, const NonTrivialCopyAssign& y) { return x.i == y.i; } +}; + +constexpr void test_constexpr_copy_assignment_non_trivial() { + // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). + using V = std::variant; + static_assert(!std::is_trivially_copyable::value, ""); + static_assert(!std::is_trivially_copy_assignable::value, ""); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), NonTrivialCopyAssign(5)); + test_constexpr_assign_imp<2>(V(NonTrivialCopyAssign(3)), NonTrivialCopyAssign(5)); +} + +void non_constexpr_test() { test_copy_assignment_empty_empty(); test_copy_assignment_non_empty_empty(); test_copy_assignment_empty_non_empty(); - test_copy_assignment_same_index(); - test_copy_assignment_different_index(); + test_assignment_throw(); +} + +constexpr bool cxx17_constexpr_test() { test_copy_assignment_sfinae(); test_copy_assignment_not_noexcept(); - test_constexpr_copy_assignment(); + test_constexpr_copy_assignment_trivial(); + return true; +} + +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_copy_assignment_same_index(); + test_copy_assignment_different_index(); + test_constexpr_copy_assignment_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp index 84094347aed3..157ff68f3748 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.assign/move.pass.cpp @@ -24,71 +24,70 @@ #include "variant_test_helpers.h" struct NoCopy { - NoCopy(const NoCopy &) = delete; - NoCopy &operator=(const NoCopy &) = default; + NoCopy(const NoCopy&) = delete; + NoCopy& operator=(const NoCopy&) = default; }; struct CopyOnly { - CopyOnly(const CopyOnly &) = default; - CopyOnly(CopyOnly &&) = delete; - CopyOnly &operator=(const CopyOnly &) = default; - CopyOnly &operator=(CopyOnly &&) = delete; + CopyOnly(const CopyOnly&) = default; + CopyOnly(CopyOnly&&) = delete; + CopyOnly& operator=(const CopyOnly&) = default; + CopyOnly& operator=(CopyOnly&&) = delete; }; struct MoveOnly { - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; - MoveOnly &operator=(const MoveOnly &) = delete; - MoveOnly &operator=(MoveOnly &&) = default; + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; + MoveOnly& operator=(const MoveOnly&) = delete; + MoveOnly& operator=(MoveOnly&&) = default; }; struct MoveOnlyNT { - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&) {} - MoveOnlyNT &operator=(const MoveOnlyNT &) = delete; - MoveOnlyNT &operator=(MoveOnlyNT &&) = default; + MoveOnlyNT(const MoveOnlyNT&) = delete; + MoveOnlyNT(MoveOnlyNT&&) {} + MoveOnlyNT& operator=(const MoveOnlyNT&) = delete; + MoveOnlyNT& operator=(MoveOnlyNT&&) = default; }; struct MoveOnlyOddNothrow { - MoveOnlyOddNothrow(MoveOnlyOddNothrow &&) noexcept(false) {} - MoveOnlyOddNothrow(const MoveOnlyOddNothrow &) = delete; - MoveOnlyOddNothrow &operator=(MoveOnlyOddNothrow &&) noexcept = default; - MoveOnlyOddNothrow &operator=(const MoveOnlyOddNothrow &) = delete; + MoveOnlyOddNothrow(MoveOnlyOddNothrow&&) noexcept(false) {} + MoveOnlyOddNothrow(const MoveOnlyOddNothrow&) = delete; + MoveOnlyOddNothrow& operator=(MoveOnlyOddNothrow&&) noexcept = default; + MoveOnlyOddNothrow& operator=(const MoveOnlyOddNothrow&) = delete; }; struct MoveAssignOnly { - MoveAssignOnly(MoveAssignOnly &&) = delete; - MoveAssignOnly &operator=(MoveAssignOnly &&) = default; + MoveAssignOnly(MoveAssignOnly&&) = delete; + MoveAssignOnly& operator=(MoveAssignOnly&&) = default; }; struct MoveAssign { - static int move_construct; - static int move_assign; - static void reset() { move_construct = move_assign = 0; } - MoveAssign(int v) : value(v) {} - MoveAssign(MoveAssign &&o) : value(o.value) { - ++move_construct; + constexpr MoveAssign(int v, int* move_ctor, int* move_assi) + : value(v), move_construct(move_ctor), move_assign(move_assi) {} + constexpr MoveAssign(MoveAssign&& o) : value(o.value), move_construct(o.move_construct), move_assign(o.move_assign) { + ++*move_construct; o.value = -1; } - MoveAssign &operator=(MoveAssign &&o) { - value = o.value; - ++move_assign; + constexpr MoveAssign& operator=(MoveAssign&& o) { + value = o.value; + move_construct = o.move_construct; + move_assign = o.move_assign; + ++*move_assign; o.value = -1; return *this; } int value; + int* move_construct; + int* move_assign; }; -int MoveAssign::move_construct = 0; -int MoveAssign::move_assign = 0; - struct NTMoveAssign { constexpr NTMoveAssign(int v) : value(v) {} - NTMoveAssign(const NTMoveAssign &) = default; - NTMoveAssign(NTMoveAssign &&) = default; - NTMoveAssign &operator=(const NTMoveAssign &that) = default; - NTMoveAssign &operator=(NTMoveAssign &&that) { - value = that.value; + NTMoveAssign(const NTMoveAssign&) = default; + NTMoveAssign(NTMoveAssign&&) = default; + NTMoveAssign& operator=(const NTMoveAssign& that) = default; + NTMoveAssign& operator=(NTMoveAssign&& that) { + value = that.value; that.value = -1; return *this; }; @@ -100,10 +99,10 @@ static_assert(std::is_move_assignable::value, ""); struct TMoveAssign { constexpr TMoveAssign(int v) : value(v) {} - TMoveAssign(const TMoveAssign &) = delete; - TMoveAssign(TMoveAssign &&) = default; - TMoveAssign &operator=(const TMoveAssign &) = delete; - TMoveAssign &operator=(TMoveAssign &&) = default; + TMoveAssign(const TMoveAssign&) = delete; + TMoveAssign(TMoveAssign&&) = default; + TMoveAssign& operator=(const TMoveAssign&) = delete; + TMoveAssign& operator=(TMoveAssign&&) = default; int value; }; @@ -111,13 +110,13 @@ static_assert(std::is_trivially_move_assignable::value, ""); struct TMoveAssignNTCopyAssign { constexpr TMoveAssignNTCopyAssign(int v) : value(v) {} - TMoveAssignNTCopyAssign(const TMoveAssignNTCopyAssign &) = default; - TMoveAssignNTCopyAssign(TMoveAssignNTCopyAssign &&) = default; - TMoveAssignNTCopyAssign &operator=(const TMoveAssignNTCopyAssign &that) { + TMoveAssignNTCopyAssign(const TMoveAssignNTCopyAssign&) = default; + TMoveAssignNTCopyAssign(TMoveAssignNTCopyAssign&&) = default; + TMoveAssignNTCopyAssign& operator=(const TMoveAssignNTCopyAssign& that) { value = that.value; return *this; } - TMoveAssignNTCopyAssign &operator=(TMoveAssignNTCopyAssign &&) = default; + TMoveAssignNTCopyAssign& operator=(TMoveAssignNTCopyAssign&&) = default; int value; }; @@ -127,16 +126,13 @@ struct TrivialCopyNontrivialMove { TrivialCopyNontrivialMove(TrivialCopyNontrivialMove const&) = default; TrivialCopyNontrivialMove(TrivialCopyNontrivialMove&&) noexcept {} TrivialCopyNontrivialMove& operator=(TrivialCopyNontrivialMove const&) = default; - TrivialCopyNontrivialMove& operator=(TrivialCopyNontrivialMove&&) noexcept { - return *this; - } + TrivialCopyNontrivialMove& operator=(TrivialCopyNontrivialMove&&) noexcept { return *this; } }; static_assert(std::is_trivially_copy_assignable_v, ""); static_assert(!std::is_trivially_move_assignable_v, ""); - -void test_move_assignment_noexcept() { +constexpr void test_move_assignment_noexcept() { { using V = std::variant; static_assert(std::is_nothrow_move_assignable::value, ""); @@ -163,7 +159,7 @@ void test_move_assignment_noexcept() { } } -void test_move_assignment_sfinae() { +constexpr void test_move_assignment_sfinae() { { using V = std::variant; static_assert(std::is_move_assignable::value, ""); @@ -228,7 +224,7 @@ void test_move_assignment_empty_empty() { makeEmpty(v1); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -244,7 +240,7 @@ void test_move_assignment_non_empty_empty() { V v1(std::in_place_index<0>, 42); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -254,7 +250,7 @@ void test_move_assignment_non_empty_empty() { V v1(std::in_place_index<2>, "hello"); V v2(std::in_place_index<0>); makeEmpty(v2); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.valueless_by_exception()); assert(v1.index() == std::variant_npos); @@ -270,7 +266,7 @@ void test_move_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_index<0>, 42); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -280,7 +276,7 @@ void test_move_assignment_empty_non_empty() { V v1(std::in_place_index<0>); makeEmpty(v1); V v2(std::in_place_type, "hello"); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 2); assert(std::get<2>(v1) == "hello"); @@ -288,14 +284,18 @@ void test_move_assignment_empty_non_empty() { #endif // TEST_HAS_NO_EXCEPTIONS } -template struct Result { std::size_t index; T value; }; +template +struct Result { + std::size_t index; + T value; +}; -void test_move_assignment_same_index() { +TEST_CONSTEXPR_CXX20 void test_move_assignment_same_index() { { using V = std::variant; V v1(43); V v2(42); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 0); assert(std::get<0>(v1) == 42); @@ -304,39 +304,24 @@ void test_move_assignment_same_index() { using V = std::variant; V v1(43l); V v2(42l); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; - V v1(std::in_place_type, 43); - V v2(std::in_place_type, 42); - MoveAssign::reset(); - V &vref = (v1 = std::move(v2)); + using V = std::variant; + int move_construct = 0; + int move_assign = 0; + V v1(std::in_place_type, 43, &move_construct, &move_assign); + V v2(std::in_place_type, 42, &move_construct, &move_assign); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(MoveAssign::move_construct == 0); - assert(MoveAssign::move_assign == 1); - } -#ifndef TEST_HAS_NO_EXCEPTIONS - using MET = MakeEmptyT; - { - using V = std::variant; - V v1(std::in_place_type); - MET &mref = std::get<1>(v1); - V v2(std::in_place_type); - try { - v1 = std::move(v2); - assert(false); - } catch (...) { - } - assert(v1.index() == 1); - assert(&std::get<1>(v1) == &mref); + assert(move_construct == 0); + assert(move_assign == 1); } -#endif // TEST_HAS_NO_EXCEPTIONS // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). { @@ -383,52 +368,29 @@ void test_move_assignment_same_index() { } } -void test_move_assignment_different_index() { +TEST_CONSTEXPR_CXX20 void test_move_assignment_different_index() { { using V = std::variant; V v1(43); V v2(42l); - V &vref = (v1 = std::move(v2)); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1) == 42); } { - using V = std::variant; + using V = std::variant; + int move_construct = 0; + int move_assign = 0; V v1(std::in_place_type, 43u); - V v2(std::in_place_type, 42); - MoveAssign::reset(); - V &vref = (v1 = std::move(v2)); + V v2(std::in_place_type, 42, &move_construct, &move_assign); + V& vref = (v1 = std::move(v2)); assert(&vref == &v1); assert(v1.index() == 1); assert(std::get<1>(v1).value == 42); - assert(MoveAssign::move_construct == 1); - assert(MoveAssign::move_assign == 0); + assert(move_construct == 1); + assert(move_assign == 0); } -#ifndef TEST_HAS_NO_EXCEPTIONS - using MET = MakeEmptyT; - { - using V = std::variant; - V v1(std::in_place_type); - V v2(std::in_place_type); - try { - v1 = std::move(v2); - assert(false); - } catch (...) { - } - assert(v1.valueless_by_exception()); - assert(v1.index() == std::variant_npos); - } - { - using V = std::variant; - V v1(std::in_place_type); - V v2(std::in_place_type, "hello"); - V &vref = (v1 = std::move(v2)); - assert(&vref == &v1); - assert(v1.index() == 2); - assert(std::get<2>(v1) == "hello"); - } -#endif // TEST_HAS_NO_EXCEPTIONS // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). { @@ -461,38 +423,126 @@ void test_move_assignment_different_index() { } } -template -constexpr bool test_constexpr_assign_imp( - std::variant&& v, ValueType&& new_value) -{ - std::variant v2( - std::forward(new_value)); +void test_assignment_throw() { +#ifndef TEST_HAS_NO_EXCEPTIONS + using MET = MakeEmptyT; + // same index + { + using V = std::variant; + V v1(std::in_place_type); + MET& mref = std::get<1>(v1); + V v2(std::in_place_type); + try { + v1 = std::move(v2); + assert(false); + } catch (...) { + } + assert(v1.index() == 1); + assert(&std::get<1>(v1) == &mref); + } + + // different indices + { + using V = std::variant; + V v1(std::in_place_type); + V v2(std::in_place_type); + try { + v1 = std::move(v2); + assert(false); + } catch (...) { + } + assert(v1.valueless_by_exception()); + assert(v1.index() == std::variant_npos); + } + { + using V = std::variant; + V v1(std::in_place_type); + V v2(std::in_place_type, "hello"); + V& vref = (v1 = std::move(v2)); + assert(&vref == &v1); + assert(v1.index() == 2); + assert(std::get<2>(v1) == "hello"); + } +#endif // TEST_HAS_NO_EXCEPTIONS +} + +template +constexpr void test_constexpr_assign_imp(T&& v, ValueType&& new_value) { + using Variant = std::decay_t; + Variant v2(std::forward(new_value)); const auto cp = v2; - v = std::move(v2); - return v.index() == NewIdx && - std::get(v) == std::get(cp); + v = std::move(v2); + assert(v.index() == NewIdx); + assert(std::get(v) == std::get(cp)); } -void test_constexpr_move_assignment() { +constexpr void test_constexpr_move_assignment_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; static_assert(std::is_trivially_copyable::value, ""); static_assert(std::is_trivially_move_assignable::value, ""); - static_assert(test_constexpr_assign_imp<0>(V(42l), 101l), ""); - static_assert(test_constexpr_assign_imp<0>(V(nullptr), 101l), ""); - static_assert(test_constexpr_assign_imp<1>(V(42l), nullptr), ""); - static_assert(test_constexpr_assign_imp<2>(V(42l), 101), ""); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), 101); } -int main(int, char**) { +struct NonTrivialMoveAssign { + int i = 0; + constexpr NonTrivialMoveAssign(int ii) : i(ii) {} + constexpr NonTrivialMoveAssign(const NonTrivialMoveAssign& other) = default; + constexpr NonTrivialMoveAssign(NonTrivialMoveAssign&& other) : i(other.i) {} + constexpr NonTrivialMoveAssign& operator=(const NonTrivialMoveAssign&) = default; + constexpr NonTrivialMoveAssign& operator=(NonTrivialMoveAssign&& o) { + i = o.i; + return *this; + } + TEST_CONSTEXPR_CXX20 ~NonTrivialMoveAssign() = default; + friend constexpr bool operator==(const NonTrivialMoveAssign& x, const NonTrivialMoveAssign& y) { return x.i == y.i; } +}; + +TEST_CONSTEXPR_CXX20 void test_constexpr_move_assignment_non_trivial() { + using V = std::variant; + static_assert(!std::is_trivially_copyable::value); + static_assert(!std::is_trivially_move_assignable::value); + test_constexpr_assign_imp<0>(V(42l), 101l); + test_constexpr_assign_imp<0>(V(nullptr), 101l); + test_constexpr_assign_imp<1>(V(42l), nullptr); + test_constexpr_assign_imp<2>(V(42l), NonTrivialMoveAssign(5)); + test_constexpr_assign_imp<2>(V(NonTrivialMoveAssign(3)), NonTrivialMoveAssign(5)); +} + +void non_constexpr_test() { test_move_assignment_empty_empty(); test_move_assignment_non_empty_empty(); test_move_assignment_empty_non_empty(); - test_move_assignment_same_index(); - test_move_assignment_different_index(); + test_assignment_throw(); +} + +constexpr bool cxx17_constexpr_test() { test_move_assignment_sfinae(); test_move_assignment_noexcept(); - test_constexpr_move_assignment(); + test_constexpr_move_assignment_trivial(); + + return true; +} +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_move_assignment_same_index(); + test_move_assignment_different_index(); + test_constexpr_move_assignment_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp index d1e5768f58d2..820ff9e0d1a9 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/copy.pass.cpp @@ -22,30 +22,30 @@ #include "test_workarounds.h" struct NonT { - NonT(int v) : value(v) {} - NonT(const NonT &o) : value(o.value) {} + constexpr NonT(int v) : value(v) {} + constexpr NonT(const NonT& o) : value(o.value) {} int value; }; static_assert(!std::is_trivially_copy_constructible::value, ""); struct NoCopy { - NoCopy(const NoCopy &) = delete; + NoCopy(const NoCopy&) = delete; }; struct MoveOnly { - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; }; struct MoveOnlyNT { - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&) {} + MoveOnlyNT(const MoveOnlyNT&) = delete; + MoveOnlyNT(MoveOnlyNT&&) {} }; struct NTCopy { constexpr NTCopy(int v) : value(v) {} - NTCopy(const NTCopy &that) : value(that.value) {} - NTCopy(NTCopy &&) = delete; + NTCopy(const NTCopy& that) : value(that.value) {} + NTCopy(NTCopy&&) = delete; int value; }; @@ -54,8 +54,8 @@ static_assert(std::is_copy_constructible::value, ""); struct TCopy { constexpr TCopy(int v) : value(v) {} - TCopy(TCopy const &) = default; - TCopy(TCopy &&) = delete; + TCopy(TCopy const&) = default; + TCopy(TCopy&&) = delete; int value; }; @@ -74,20 +74,21 @@ static_assert(std::is_trivially_copy_constructible::value, ""); struct MakeEmptyT { static int alive; MakeEmptyT() { ++alive; } - MakeEmptyT(const MakeEmptyT &) { + MakeEmptyT(const MakeEmptyT&) { ++alive; // Don't throw from the copy constructor since variant's assignment // operator performs a copy before committing to the assignment. } - MakeEmptyT(MakeEmptyT &&) { throw 42; } - MakeEmptyT &operator=(const MakeEmptyT &) { throw 42; } - MakeEmptyT &operator=(MakeEmptyT &&) { throw 42; } + MakeEmptyT(MakeEmptyT&&) { throw 42; } + MakeEmptyT& operator=(const MakeEmptyT&) { throw 42; } + MakeEmptyT& operator=(MakeEmptyT&&) { throw 42; } ~MakeEmptyT() { --alive; } }; int MakeEmptyT::alive = 0; -template void makeEmpty(Variant &v) { +template +void makeEmpty(Variant& v) { Variant v2(std::in_place_type); try { v = std::move(v2); @@ -98,7 +99,7 @@ template void makeEmpty(Variant &v) { } #endif // TEST_HAS_NO_EXCEPTIONS -void test_copy_ctor_sfinae() { +constexpr void test_copy_ctor_sfinae() { { using V = std::variant; static_assert(std::is_copy_constructible::value, ""); @@ -136,7 +137,7 @@ void test_copy_ctor_sfinae() { } } -void test_copy_ctor_basic() { +TEST_CONSTEXPR_CXX20 void test_copy_ctor_basic() { { std::variant v(std::in_place_index<0>, 42); std::variant v2 = v; @@ -214,21 +215,21 @@ void test_copy_ctor_valueless_by_exception() { using V = std::variant; V v1; makeEmpty(v1); - const V &cv1 = v1; + const V& cv1 = v1; V v(cv1); assert(v.valueless_by_exception()); #endif // TEST_HAS_NO_EXCEPTIONS } -template -constexpr bool test_constexpr_copy_ctor_imp(std::variant const& v) { +template +constexpr void test_constexpr_copy_ctor_imp(const T& v) { auto v2 = v; - return v2.index() == v.index() && - v2.index() == Idx && - std::get(v2) == std::get(v); + assert(v2.index() == v.index()); + assert(v2.index() == Idx); + assert(std::get(v2) == std::get(v)); } -void test_constexpr_copy_ctor() { +constexpr void test_constexpr_copy_ctor_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; #ifdef TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE @@ -237,18 +238,57 @@ void test_constexpr_copy_ctor() { static_assert(std::is_trivially_move_constructible::value, ""); static_assert(!std::is_copy_assignable::value, ""); static_assert(!std::is_move_assignable::value, ""); -#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE +#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE static_assert(std::is_trivially_copyable::value, ""); #endif // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE - static_assert(test_constexpr_copy_ctor_imp<0>(V(42l)), ""); - static_assert(test_constexpr_copy_ctor_imp<1>(V(nullptr)), ""); - static_assert(test_constexpr_copy_ctor_imp<2>(V(101)), ""); + static_assert(std::is_trivially_copy_constructible::value, ""); + test_constexpr_copy_ctor_imp<0>(V(42l)); + test_constexpr_copy_ctor_imp<1>(V(nullptr)); + test_constexpr_copy_ctor_imp<2>(V(101)); } -int main(int, char**) { - test_copy_ctor_basic(); - test_copy_ctor_valueless_by_exception(); +struct NonTrivialCopyCtor { + int i = 0; + constexpr NonTrivialCopyCtor(int ii) : i(ii) {} + constexpr NonTrivialCopyCtor(const NonTrivialCopyCtor& other) : i(other.i) {} + constexpr NonTrivialCopyCtor(NonTrivialCopyCtor&& other) = default; + TEST_CONSTEXPR_CXX20 ~NonTrivialCopyCtor() = default; + friend constexpr bool operator==(const NonTrivialCopyCtor& x, const NonTrivialCopyCtor& y) { return x.i == y.i; } +}; + +TEST_CONSTEXPR_CXX20 void test_constexpr_copy_ctor_non_trivial() { + // Test !is_trivially_move_constructible + using V = std::variant; + static_assert(!std::is_trivially_copy_constructible::value, ""); + test_constexpr_copy_ctor_imp<0>(V(42l)); + test_constexpr_copy_ctor_imp<1>(V(NonTrivialCopyCtor(5))); + test_constexpr_copy_ctor_imp<2>(V(nullptr)); +} + +void non_constexpr_test() { test_copy_ctor_valueless_by_exception(); } + +constexpr bool cxx17_constexpr_test() { test_copy_ctor_sfinae(); - test_constexpr_copy_ctor(); + test_constexpr_copy_ctor_trivial(); + + return true; +} + +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_copy_ctor_basic(); + test_constexpr_copy_ctor_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp index 40db038a0033..9abf4d758d84 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/default.pass.cpp @@ -17,6 +17,7 @@ #include #include #include +#include #include "test_macros.h" #include "variant_test_helpers.h" @@ -35,7 +36,7 @@ struct DefaultCtorThrows { }; #endif -void test_default_ctor_sfinae() { +constexpr void test_default_ctor_sfinae() { { using V = std::variant; static_assert(std::is_default_constructible::value, ""); @@ -46,7 +47,7 @@ void test_default_ctor_sfinae() { } } -void test_default_ctor_noexcept() { +constexpr void test_default_ctor_noexcept() { { using V = std::variant; static_assert(std::is_nothrow_default_constructible::value, ""); @@ -63,7 +64,7 @@ void test_default_ctor_throws() { try { V v; assert(false); - } catch (const int &ex) { + } catch (const int& ex) { assert(ex == 42); } catch (...) { assert(false); @@ -71,7 +72,7 @@ void test_default_ctor_throws() { #endif } -void test_default_ctor_basic() { +constexpr void test_default_ctor_basic() { { std::variant v; assert(v.index() == 0); @@ -107,11 +108,24 @@ void test_default_ctor_basic() { } } -int main(int, char**) { +constexpr void issue_86686() { +#if TEST_STD_VER >= 20 + static_assert(std::variant{}.index() == 0); +#endif +} + +constexpr bool test() { test_default_ctor_basic(); test_default_ctor_sfinae(); test_default_ctor_noexcept(); - test_default_ctor_throws(); + issue_86686(); + return true; +} + +int main(int, char**) { + test(); + test_default_ctor_throws(); + static_assert(test()); return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp index e2518fe29caf..4e8453c23cf5 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.ctor/move.pass.cpp @@ -23,31 +23,31 @@ #include "test_workarounds.h" struct ThrowsMove { - ThrowsMove(ThrowsMove &&) noexcept(false) {} + ThrowsMove(ThrowsMove&&) noexcept(false) {} }; struct NoCopy { - NoCopy(const NoCopy &) = delete; + NoCopy(const NoCopy&) = delete; }; struct MoveOnly { int value; - MoveOnly(int v) : value(v) {} - MoveOnly(const MoveOnly &) = delete; - MoveOnly(MoveOnly &&) = default; + constexpr MoveOnly(int v) : value(v) {} + MoveOnly(const MoveOnly&) = delete; + MoveOnly(MoveOnly&&) = default; }; struct MoveOnlyNT { int value; - MoveOnlyNT(int v) : value(v) {} - MoveOnlyNT(const MoveOnlyNT &) = delete; - MoveOnlyNT(MoveOnlyNT &&other) : value(other.value) { other.value = -1; } + constexpr MoveOnlyNT(int v) : value(v) {} + MoveOnlyNT(const MoveOnlyNT&) = delete; + constexpr MoveOnlyNT(MoveOnlyNT&& other) : value(other.value) { other.value = -1; } }; struct NTMove { constexpr NTMove(int v) : value(v) {} - NTMove(const NTMove &) = delete; - NTMove(NTMove &&that) : value(that.value) { that.value = -1; } + NTMove(const NTMove&) = delete; + NTMove(NTMove&& that) : value(that.value) { that.value = -1; } int value; }; @@ -56,8 +56,8 @@ static_assert(std::is_move_constructible::value, ""); struct TMove { constexpr TMove(int v) : value(v) {} - TMove(const TMove &) = delete; - TMove(TMove &&) = default; + TMove(const TMove&) = delete; + TMove(TMove&&) = default; int value; }; @@ -76,20 +76,21 @@ static_assert(std::is_trivially_move_constructible::value, ""); struct MakeEmptyT { static int alive; MakeEmptyT() { ++alive; } - MakeEmptyT(const MakeEmptyT &) { + MakeEmptyT(const MakeEmptyT&) { ++alive; // Don't throw from the copy constructor since variant's assignment // operator performs a copy before committing to the assignment. } - MakeEmptyT(MakeEmptyT &&) { throw 42; } - MakeEmptyT &operator=(const MakeEmptyT &) { throw 42; } - MakeEmptyT &operator=(MakeEmptyT &&) { throw 42; } + MakeEmptyT(MakeEmptyT&&) { throw 42; } + MakeEmptyT& operator=(const MakeEmptyT&) { throw 42; } + MakeEmptyT& operator=(MakeEmptyT&&) { throw 42; } ~MakeEmptyT() { --alive; } }; int MakeEmptyT::alive = 0; -template void makeEmpty(Variant &v) { +template +void makeEmpty(Variant& v) { Variant v2(std::in_place_type); try { v = std::move(v2); @@ -100,7 +101,7 @@ template void makeEmpty(Variant &v) { } #endif // TEST_HAS_NO_EXCEPTIONS -void test_move_noexcept() { +constexpr void test_move_noexcept() { { using V = std::variant; static_assert(std::is_nothrow_move_constructible::value, ""); @@ -119,7 +120,7 @@ void test_move_noexcept() { } } -void test_move_ctor_sfinae() { +constexpr void test_move_ctor_sfinae() { { using V = std::variant; static_assert(std::is_move_constructible::value, ""); @@ -158,9 +159,12 @@ void test_move_ctor_sfinae() { } template -struct Result { std::size_t index; T value; }; +struct Result { + std::size_t index; + T value; +}; -void test_move_ctor_basic() { +TEST_CONSTEXPR_CXX20 void test_move_ctor_basic() { { std::variant v(std::in_place_index<0>, 42); std::variant v2 = std::move(v); @@ -289,16 +293,16 @@ void test_move_ctor_valueless_by_exception() { #endif // TEST_HAS_NO_EXCEPTIONS } -template -constexpr bool test_constexpr_ctor_imp(std::variant const& v) { +template +constexpr void test_constexpr_ctor_imp(const T& v) { auto copy = v; - auto v2 = std::move(copy); - return v2.index() == v.index() && - v2.index() == Idx && - std::get(v2) == std::get(v); + auto v2 = std::move(copy); + assert(v2.index() == v.index()); + assert(v2.index() == Idx); + assert(std::get(v2) == std::get(v)); } -void test_constexpr_move_ctor() { +constexpr void test_constexpr_move_ctor_trivial() { // Make sure we properly propagate triviality, which implies constexpr-ness (see P0602R4). using V = std::variant; #ifdef TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE @@ -307,21 +311,58 @@ void test_constexpr_move_ctor() { static_assert(std::is_trivially_move_constructible::value, ""); static_assert(!std::is_copy_assignable::value, ""); static_assert(!std::is_move_assignable::value, ""); -#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE +#else // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE static_assert(std::is_trivially_copyable::value, ""); #endif // TEST_WORKAROUND_MSVC_BROKEN_IS_TRIVIALLY_COPYABLE static_assert(std::is_trivially_move_constructible::value, ""); - static_assert(test_constexpr_ctor_imp<0>(V(42l)), ""); - static_assert(test_constexpr_ctor_imp<1>(V(nullptr)), ""); - static_assert(test_constexpr_ctor_imp<2>(V(101)), ""); + test_constexpr_ctor_imp<0>(V(42l)); + test_constexpr_ctor_imp<1>(V(nullptr)); + test_constexpr_ctor_imp<2>(V(101)); } -int main(int, char**) { - test_move_ctor_basic(); - test_move_ctor_valueless_by_exception(); +struct NonTrivialMoveCtor { + int i = 0; + constexpr NonTrivialMoveCtor(int ii) : i(ii) {} + constexpr NonTrivialMoveCtor(const NonTrivialMoveCtor& other) = default; + constexpr NonTrivialMoveCtor(NonTrivialMoveCtor&& other) : i(other.i) {} + TEST_CONSTEXPR_CXX20 ~NonTrivialMoveCtor() = default; + friend constexpr bool operator==(const NonTrivialMoveCtor& x, const NonTrivialMoveCtor& y) { return x.i == y.i; } +}; + +TEST_CONSTEXPR_CXX20 void test_constexpr_move_ctor_non_trivial() { + using V = std::variant; + static_assert(!std::is_trivially_move_constructible::value, ""); + test_constexpr_ctor_imp<0>(V(42l)); + test_constexpr_ctor_imp<1>(V(NonTrivialMoveCtor(5))); + test_constexpr_ctor_imp<2>(V(nullptr)); +} + +void non_constexpr_test() { test_move_ctor_valueless_by_exception(); } + +constexpr bool cxx17_constexpr_test() { test_move_noexcept(); test_move_ctor_sfinae(); - test_constexpr_move_ctor(); + test_constexpr_move_ctor_trivial(); + + return true; +} + +TEST_CONSTEXPR_CXX20 bool cxx20_constexpr_test() { + test_move_ctor_basic(); + test_constexpr_move_ctor_non_trivial(); + + return true; +} + +int main(int, char**) { + non_constexpr_test(); + cxx17_constexpr_test(); + cxx20_constexpr_test(); + + static_assert(cxx17_constexpr_test()); +#if TEST_STD_VER >= 20 + static_assert(cxx20_constexpr_test()); +#endif return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp index 2e026038c97a..53c5283b2edc 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.dtor/dtor.pass.cpp @@ -21,55 +21,76 @@ #include "test_macros.h" struct NonTDtor { - static int count; - NonTDtor() = default; - ~NonTDtor() { ++count; } + int* count; + constexpr NonTDtor(int* a, int*) : count(a) {} + TEST_CONSTEXPR_CXX20 ~NonTDtor() { ++*count; } }; -int NonTDtor::count = 0; static_assert(!std::is_trivially_destructible::value, ""); struct NonTDtor1 { - static int count; - NonTDtor1() = default; - ~NonTDtor1() { ++count; } + int* count; + constexpr NonTDtor1(int*, int* b) : count(b) {} + TEST_CONSTEXPR_CXX20 ~NonTDtor1() { ++*count; } }; -int NonTDtor1::count = 0; static_assert(!std::is_trivially_destructible::value, ""); struct TDtor { - TDtor(const TDtor &) {} // non-trivial copy - ~TDtor() = default; + constexpr TDtor() = default; + constexpr TDtor(const TDtor&) {} // non-trivial copy + TEST_CONSTEXPR_CXX20 ~TDtor() = default; }; static_assert(!std::is_trivially_copy_constructible::value, ""); static_assert(std::is_trivially_destructible::value, ""); -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { { using V = std::variant; static_assert(std::is_trivially_destructible::value, ""); + [[maybe_unused]] V v(std::in_place_index<2>); } { using V = std::variant; static_assert(!std::is_trivially_destructible::value, ""); { - V v(std::in_place_index<0>); - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 0); + int count0 = 0; + int count1 = 0; + { + V v(std::in_place_index<0>, &count0, &count1); + assert(count0 == 0); + assert(count1 == 0); + } + assert(count0 == 1); + assert(count1 == 0); + } + { + int count0 = 0; + int count1 = 0; + { V v(std::in_place_index<1>); } + assert(count0 == 0); + assert(count1 == 0); } - assert(NonTDtor::count == 1); - assert(NonTDtor1::count == 0); - NonTDtor::count = 0; - { V v(std::in_place_index<1>); } - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 0); { - V v(std::in_place_index<2>); - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 0); + int count0 = 0; + int count1 = 0; + { + V v(std::in_place_index<2>, &count0, &count1); + assert(count0 == 0); + assert(count1 == 0); + } + assert(count0 == 0); + assert(count1 == 1); } - assert(NonTDtor::count == 0); - assert(NonTDtor1::count == 1); } + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp index 2fe9033dd816..f98d968f0eae 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_args.pass.cpp @@ -26,8 +26,8 @@ #include "variant_test_helpers.h" template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -36,28 +36,32 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { +constexpr void test_emplace_sfinae() { { - using V = std::variant; + using V = std::variant; static_assert(emplace_exists(), ""); static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), - "cannot construct"); + static_assert(!emplace_exists(), "cannot construct"); static_assert(emplace_exists(), ""); - static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), ""); + static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), ""); static_assert(!emplace_exists(), "cannot construct"); - static_assert(emplace_exists(), ""); - static_assert(emplace_exists(), ""); + static_assert(emplace_exists(), ""); + static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "cannot construct"); } } -void test_basic() { +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { { using V = std::variant; V v(42); @@ -70,9 +74,9 @@ void test_basic() { assert(std::get<0>(v) == 42); assert(&ref2 == &std::get<0>(v)); } + { - using V = - std::variant; + using V = std::variant; const int x = 100; V v(std::in_place_index<0>, -1); // default emplace a value @@ -92,9 +96,19 @@ void test_basic() { } } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp index 9068aacc4359..4c635570bd56 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_index_init_list_args.pass.cpp @@ -32,13 +32,12 @@ struct InitList { struct InitListArg { std::size_t size; int value; - constexpr InitListArg(std::initializer_list il, int v) - : size(il.size()), value(v) {} + constexpr InitListArg(std::initializer_list il, int v) : size(il.size()), value(v) {} }; template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -47,13 +46,13 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { - using V = - std::variant; +constexpr void test_emplace_sfinae() { + using V = std::variant; using IL = std::initializer_list; static_assert(!emplace_exists(), "no such constructor"); static_assert(emplace_exists(), ""); @@ -65,8 +64,12 @@ void test_emplace_sfinae() { static_assert(!emplace_exists(), "too many args"); } -void test_basic() { - using V = std::variant; +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { + using V = std::variant; V v; auto& ref1 = v.emplace<1>({1, 2, 3}); static_assert(std::is_same_v, ""); @@ -83,9 +86,19 @@ void test_basic() { assert(&ref3 == &std::get<1>(v)); } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp index 4e9f67775d10..c2ed54d8a625 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_args.pass.cpp @@ -25,8 +25,8 @@ #include "variant_test_helpers.h" template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -35,28 +35,32 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { +constexpr void test_emplace_sfinae() { { - using V = std::variant; + using V = std::variant; static_assert(emplace_exists(), ""); static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), - "cannot construct"); - static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), "cannot construct"); - static_assert(emplace_exists(), ""); - static_assert(!emplace_exists(), ""); - static_assert(emplace_exists(), ""); - static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), "cannot construct"); + static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), "cannot construct"); + static_assert(emplace_exists(), ""); + static_assert(!emplace_exists(), ""); + static_assert(emplace_exists(), ""); + static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "cannot construct"); } } -void test_basic() { +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { { using V = std::variant; V v(42); @@ -70,8 +74,7 @@ void test_basic() { assert(&ref2 == &std::get<0>(v)); } { - using V = - std::variant; + using V = std::variant; const int x = 100; V v(std::in_place_type, -1); // default emplace a value @@ -79,8 +82,8 @@ void test_basic() { static_assert(std::is_same_v, ""); assert(std::get<1>(v) == 0); assert(&ref1 == &std::get<1>(v)); - auto& ref2 = v.emplace(&x); - static_assert(std::is_same_v, ""); + auto& ref2 = v.emplace(&x); + static_assert(std::is_same_v, ""); assert(std::get<2>(v) == &x); assert(&ref2 == &std::get<2>(v)); // emplace with multiple args @@ -91,9 +94,19 @@ void test_basic() { } } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp index 74d834b9b345..644f2418b925 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.mod/emplace_type_init_list_args.pass.cpp @@ -32,13 +32,12 @@ struct InitList { struct InitListArg { std::size_t size; int value; - constexpr InitListArg(std::initializer_list il, int v) - : size(il.size()), value(v) {} + constexpr InitListArg(std::initializer_list il, int v) : size(il.size()), value(v) {} }; template -constexpr auto test_emplace_exists_imp(int) -> decltype( - std::declval().template emplace(std::declval()...), true) { +constexpr auto test_emplace_exists_imp(int) + -> decltype(std::declval().template emplace(std::declval()...), true) { return true; } @@ -47,13 +46,13 @@ constexpr auto test_emplace_exists_imp(long) -> bool { return false; } -template constexpr bool emplace_exists() { +template +constexpr bool emplace_exists() { return test_emplace_exists_imp(0); } -void test_emplace_sfinae() { - using V = - std::variant; +constexpr void test_emplace_sfinae() { + using V = std::variant; using IL = std::initializer_list; static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "args don't match"); @@ -61,31 +60,44 @@ void test_emplace_sfinae() { static_assert(emplace_exists(), ""); static_assert(!emplace_exists(), "args don't match"); static_assert(!emplace_exists(), "too few args"); - static_assert(!emplace_exists(), - "too many args"); + static_assert(!emplace_exists(), "too many args"); } -void test_basic() { - using V = std::variant; +struct NoCtor { + NoCtor() = delete; +}; + +TEST_CONSTEXPR_CXX20 void test_basic() { + using V = std::variant; V v; auto& ref1 = v.emplace({1, 2, 3}); - static_assert(std::is_same_v, ""); + static_assert(std::is_same_v, ""); assert(std::get(v).size == 3); assert(&ref1 == &std::get(v)); auto& ref2 = v.emplace({1, 2, 3, 4}, 42); - static_assert(std::is_same_v, ""); + static_assert(std::is_same_v, ""); assert(std::get(v).size == 4); assert(std::get(v).value == 42); assert(&ref2 == &std::get(v)); auto& ref3 = v.emplace({1}); - static_assert(std::is_same_v, ""); + static_assert(std::is_same_v, ""); assert(std::get(v).size == 1); assert(&ref3 == &std::get(v)); } -int main(int, char**) { +TEST_CONSTEXPR_CXX20 bool test() { test_basic(); test_emplace_sfinae(); + return true; +} + +int main(int, char**) { + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } diff --git a/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp b/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp index 1802bc4670bb..db05691c5581 100644 --- a/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp +++ b/libcxx/test/std/utilities/variant/variant.variant/variant.swap/swap.pass.cpp @@ -25,37 +25,39 @@ #include "variant_test_helpers.h" struct NotSwappable {}; -void swap(NotSwappable &, NotSwappable &) = delete; +void swap(NotSwappable&, NotSwappable&) = delete; struct NotCopyable { - NotCopyable() = default; - NotCopyable(const NotCopyable &) = delete; - NotCopyable &operator=(const NotCopyable &) = delete; + NotCopyable() = default; + NotCopyable(const NotCopyable&) = delete; + NotCopyable& operator=(const NotCopyable&) = delete; }; struct NotCopyableWithSwap { - NotCopyableWithSwap() = default; - NotCopyableWithSwap(const NotCopyableWithSwap &) = delete; - NotCopyableWithSwap &operator=(const NotCopyableWithSwap &) = delete; + NotCopyableWithSwap() = default; + NotCopyableWithSwap(const NotCopyableWithSwap&) = delete; + NotCopyableWithSwap& operator=(const NotCopyableWithSwap&) = delete; }; -void swap(NotCopyableWithSwap &, NotCopyableWithSwap) {} +constexpr void swap(NotCopyableWithSwap&, NotCopyableWithSwap) {} struct NotMoveAssignable { - NotMoveAssignable() = default; - NotMoveAssignable(NotMoveAssignable &&) = default; - NotMoveAssignable &operator=(NotMoveAssignable &&) = delete; + NotMoveAssignable() = default; + NotMoveAssignable(NotMoveAssignable&&) = default; + NotMoveAssignable& operator=(NotMoveAssignable&&) = delete; }; struct NotMoveAssignableWithSwap { - NotMoveAssignableWithSwap() = default; - NotMoveAssignableWithSwap(NotMoveAssignableWithSwap &&) = default; - NotMoveAssignableWithSwap &operator=(NotMoveAssignableWithSwap &&) = delete; + NotMoveAssignableWithSwap() = default; + NotMoveAssignableWithSwap(NotMoveAssignableWithSwap&&) = default; + NotMoveAssignableWithSwap& operator=(NotMoveAssignableWithSwap&&) = delete; }; -void swap(NotMoveAssignableWithSwap &, NotMoveAssignableWithSwap &) noexcept {} +constexpr void swap(NotMoveAssignableWithSwap&, NotMoveAssignableWithSwap&) noexcept {} -template void do_throw() {} +template +constexpr void do_throw() {} -template <> void do_throw() { +template <> +void do_throw() { #ifndef TEST_HAS_NO_EXCEPTIONS throw 42; #else @@ -63,60 +65,49 @@ template <> void do_throw() { #endif } -template +template struct NothrowTypeImp { - static int move_called; - static int move_assign_called; - static int swap_called; - static void reset() { move_called = move_assign_called = swap_called = 0; } - NothrowTypeImp() = default; - explicit NothrowTypeImp(int v) : value(v) {} - NothrowTypeImp(const NothrowTypeImp &o) noexcept(NT_Copy) : value(o.value) { - assert(false); - } // never called by test - NothrowTypeImp(NothrowTypeImp &&o) noexcept(NT_Move) : value(o.value) { - ++move_called; + int value; + int* move_called; + int* move_assign_called; + int* swap_called; + + constexpr NothrowTypeImp(int v, int* mv_ctr, int* mv_assign, int* swap) + : value(v), move_called(mv_ctr), move_assign_called(mv_assign), swap_called(swap) {} + + NothrowTypeImp(const NothrowTypeImp& o) noexcept(NT_Copy) : value(o.value) { assert(false); } // never called by test + + constexpr NothrowTypeImp(NothrowTypeImp&& o) noexcept(NT_Move) + : value(o.value), + move_called(o.move_called), + move_assign_called(o.move_assign_called), + swap_called(o.swap_called) { + ++*move_called; do_throw(); o.value = -1; } - NothrowTypeImp &operator=(const NothrowTypeImp &) noexcept(NT_CopyAssign) { + + NothrowTypeImp& operator=(const NothrowTypeImp&) noexcept(NT_CopyAssign) { assert(false); return *this; } // never called by the tests - NothrowTypeImp &operator=(NothrowTypeImp &&o) noexcept(NT_MoveAssign) { - ++move_assign_called; + + constexpr NothrowTypeImp& operator=(NothrowTypeImp&& o) noexcept(NT_MoveAssign) { + ++*move_assign_called; do_throw(); - value = o.value; + value = o.value; o.value = -1; return *this; } - int value; }; -template -int NothrowTypeImp::move_called = 0; -template -int NothrowTypeImp::move_assign_called = 0; -template -int NothrowTypeImp::swap_called = 0; - -template -void swap(NothrowTypeImp &lhs, - NothrowTypeImp &rhs) noexcept(NT_Swap) { - lhs.swap_called++; + +template +constexpr void +swap(NothrowTypeImp& lhs, + NothrowTypeImp& rhs) noexcept(NT_Swap) { + ++*lhs.swap_called; do_throw(); - int tmp = lhs.value; - lhs.value = rhs.value; - rhs.value = tmp; + std::swap(lhs.value, rhs.value); } // throwing copy, nothrow move ctor/assign, no swap provided @@ -124,53 +115,42 @@ using NothrowMoveable = NothrowTypeImp; // throwing copy and move assign, nothrow move ctor, no swap provided using NothrowMoveCtor = NothrowTypeImp; // nothrow move ctor, throwing move assignment, swap provided -using NothrowMoveCtorWithThrowingSwap = - NothrowTypeImp; +using NothrowMoveCtorWithThrowingSwap = NothrowTypeImp; // throwing move ctor, nothrow move assignment, no swap provided -using ThrowingMoveCtor = - NothrowTypeImp; +using ThrowingMoveCtor = NothrowTypeImp; // throwing special members, nothrowing swap -using ThrowingTypeWithNothrowSwap = - NothrowTypeImp; -using NothrowTypeWithThrowingSwap = - NothrowTypeImp; +using ThrowingTypeWithNothrowSwap = NothrowTypeImp; +using NothrowTypeWithThrowingSwap = NothrowTypeImp; // throwing move assign with nothrow move and nothrow swap -using ThrowingMoveAssignNothrowMoveCtorWithSwap = - NothrowTypeImp; +using ThrowingMoveAssignNothrowMoveCtorWithSwap = NothrowTypeImp; // throwing move assign with nothrow move but no swap. -using ThrowingMoveAssignNothrowMoveCtor = - NothrowTypeImp; +using ThrowingMoveAssignNothrowMoveCtor = NothrowTypeImp; struct NonThrowingNonNoexceptType { - static int move_called; - static void reset() { move_called = 0; } - NonThrowingNonNoexceptType() = default; - NonThrowingNonNoexceptType(int v) : value(v) {} - NonThrowingNonNoexceptType(NonThrowingNonNoexceptType &&o) noexcept(false) - : value(o.value) { - ++move_called; + int value; + int* move_called; + constexpr NonThrowingNonNoexceptType(int v, int* mv_called) : value(v), move_called(mv_called) {} + constexpr NonThrowingNonNoexceptType(NonThrowingNonNoexceptType&& o) noexcept(false) + : value(o.value), move_called(o.move_called) { + ++*move_called; o.value = -1; } - NonThrowingNonNoexceptType & - operator=(NonThrowingNonNoexceptType &&) noexcept(false) { + NonThrowingNonNoexceptType& operator=(NonThrowingNonNoexceptType&&) noexcept(false) { assert(false); // never called by the tests. return *this; } - int value; }; -int NonThrowingNonNoexceptType::move_called = 0; struct ThrowsOnSecondMove { int value; int move_count; ThrowsOnSecondMove(int v) : value(v), move_count(0) {} - ThrowsOnSecondMove(ThrowsOnSecondMove &&o) noexcept(false) - : value(o.value), move_count(o.move_count + 1) { + ThrowsOnSecondMove(ThrowsOnSecondMove&& o) noexcept(false) : value(o.value), move_count(o.move_count + 1) { if (move_count == 2) do_throw(); o.value = -1; } - ThrowsOnSecondMove &operator=(ThrowsOnSecondMove &&) { + ThrowsOnSecondMove& operator=(ThrowsOnSecondMove&&) { assert(false); // not called by test return *this; } @@ -224,265 +204,293 @@ void test_swap_valueless_by_exception() { #endif } -void test_swap_same_alternative() { +TEST_CONSTEXPR_CXX20 void test_swap_same_alternative() { { - using T = ThrowingTypeWithNothrowSwap; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); v1.swap(v2); - assert(T::swap_called == 1); + assert(swap_called == 1); assert(std::get<0>(v1).value == 100); assert(std::get<0>(v2).value == 42); swap(v1, v2); - assert(T::swap_called == 2); + assert(swap_called == 2); assert(std::get<0>(v1).value == 42); assert(std::get<0>(v2).value == 100); + + assert(move_called == 0); + assert(move_assign_called == 0); } { - using T = NothrowMoveable; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); v1.swap(v2); - assert(T::swap_called == 0); - assert(T::move_called == 1); - assert(T::move_assign_called == 2); + assert(swap_called == 0); + assert(move_called == 1); + assert(move_assign_called == 2); assert(std::get<0>(v1).value == 100); assert(std::get<0>(v2).value == 42); - T::reset(); + + move_called = 0; + move_assign_called = 0; + swap_called = 0; + swap(v1, v2); - assert(T::swap_called == 0); - assert(T::move_called == 1); - assert(T::move_assign_called == 2); + assert(swap_called == 0); + assert(move_called == 1); + assert(move_assign_called == 2); assert(std::get<0>(v1).value == 42); assert(std::get<0>(v2).value == 100); } +} + +void test_swap_same_alternative_throws(){ #ifndef TEST_HAS_NO_EXCEPTIONS - { - using T = NothrowTypeWithThrowingSwap; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); - try { - v1.swap(v2); - assert(false); - } catch (int) { - } - assert(T::swap_called == 1); - assert(T::move_called == 0); - assert(T::move_assign_called == 0); - assert(std::get<0>(v1).value == 42); - assert(std::get<0>(v2).value == 100); - } - { - using T = ThrowingMoveCtor; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); - try { - v1.swap(v2); - assert(false); - } catch (int) { - } - assert(T::move_called == 1); // call threw - assert(T::move_assign_called == 0); - assert(std::get<0>(v1).value == - 42); // throw happened before v1 was moved from - assert(std::get<0>(v2).value == 100); + {using V = std::variant; +int move_called = 0; +int move_assign_called = 0; +int swap_called = 0; +V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); +V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); +try { + v1.swap(v2); + assert(false); +} catch (int) { +} +assert(swap_called == 1); +assert(move_called == 0); +assert(move_assign_called == 0); +assert(std::get<0>(v1).value == 42); +assert(std::get<0>(v2).value == 100); +} + +{ + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); + try { + v1.swap(v2); + assert(false); + } catch (int) { } - { - using T = ThrowingMoveAssignNothrowMoveCtor; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<0>, 100); - try { - v1.swap(v2); - assert(false); - } catch (int) { - } - assert(T::move_called == 1); - assert(T::move_assign_called == 1); // call threw and didn't complete - assert(std::get<0>(v1).value == -1); // v1 was moved from - assert(std::get<0>(v2).value == 100); + assert(move_called == 1); // call threw + assert(move_assign_called == 0); + assert(swap_called == 0); + assert(std::get<0>(v1).value == 42); // throw happened before v1 was moved from + assert(std::get<0>(v2).value == 100); +} +{ + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); + V v2(std::in_place_index<0>, 100, &move_called, &move_assign_called, &swap_called); + try { + v1.swap(v2); + assert(false); + } catch (int) { } + assert(move_called == 1); + assert(move_assign_called == 1); // call threw and didn't complete + assert(swap_called == 0); + assert(std::get<0>(v1).value == -1); // v1 was moved from + assert(std::get<0>(v2).value == 100); +} #endif } -void test_swap_different_alternatives() { +TEST_CONSTEXPR_CXX20 void test_swap_different_alternatives() { { - using T = NothrowMoveCtorWithThrowingSwap; - using V = std::variant; - T::reset(); - V v1(std::in_place_index<0>, 42); + using V = std::variant; + int move_called = 0; + int move_assign_called = 0; + int swap_called = 0; + V v1(std::in_place_index<0>, 42, &move_called, &move_assign_called, &swap_called); V v2(std::in_place_index<1>, 100); v1.swap(v2); - assert(T::swap_called == 0); + assert(swap_called == 0); // The libc++ implementation double copies the argument, and not // the variant swap is called on. - LIBCPP_ASSERT(T::move_called == 1); - assert(T::move_called <= 2); - assert(T::move_assign_called == 0); + LIBCPP_ASSERT(move_called == 1); + assert(move_called <= 2); + assert(move_assign_called == 0); assert(std::get<1>(v1) == 100); assert(std::get<0>(v2).value == 42); - T::reset(); + + move_called = 0; + move_assign_called = 0; + swap_called = 0; + swap(v1, v2); - assert(T::swap_called == 0); - LIBCPP_ASSERT(T::move_called == 2); - assert(T::move_called <= 2); - assert(T::move_assign_called == 0); + assert(swap_called == 0); + LIBCPP_ASSERT(move_called == 2); + assert(move_called <= 2); + assert(move_assign_called == 0); assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2) == 100); } +} + +void test_swap_different_alternatives_throws() { #ifndef TEST_HAS_NO_EXCEPTIONS { - using T1 = ThrowingTypeWithNothrowSwap; - using T2 = NonThrowingNonNoexceptType; - using V = std::variant; - T1::reset(); - T2::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + using V = std::variant; + int move_called1 = 0; + int move_assign_called1 = 0; + int swap_called1 = 0; + int move_called2 = 0; + V v1(std::in_place_index<0>, 42, &move_called1, &move_assign_called1, &swap_called1); + V v2(std::in_place_index<1>, 100, &move_called2); try { v1.swap(v2); assert(false); } catch (int) { } - assert(T1::swap_called == 0); - assert(T1::move_called == 1); // throws - assert(T1::move_assign_called == 0); + assert(swap_called1 == 0); + assert(move_called1 == 1); // throws + assert(move_assign_called1 == 0); // FIXME: libc++ shouldn't move from T2 here. - LIBCPP_ASSERT(T2::move_called == 1); - assert(T2::move_called <= 1); + LIBCPP_ASSERT(move_called2 == 1); + assert(move_called2 <= 1); assert(std::get<0>(v1).value == 42); - if (T2::move_called != 0) + if (move_called2 != 0) assert(v2.valueless_by_exception()); else assert(std::get<1>(v2).value == 100); } { - using T1 = NonThrowingNonNoexceptType; - using T2 = ThrowingTypeWithNothrowSwap; - using V = std::variant; - T1::reset(); - T2::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + using V = std::variant; + int move_called1 = 0; + int move_called2 = 0; + int move_assign_called2 = 0; + int swap_called2 = 0; + V v1(std::in_place_index<0>, 42, &move_called1); + V v2(std::in_place_index<1>, 100, &move_called2, &move_assign_called2, &swap_called2); try { v1.swap(v2); assert(false); } catch (int) { } - LIBCPP_ASSERT(T1::move_called == 0); - assert(T1::move_called <= 1); - assert(T2::swap_called == 0); - assert(T2::move_called == 1); // throws - assert(T2::move_assign_called == 0); - if (T1::move_called != 0) + LIBCPP_ASSERT(move_called1 == 0); + assert(move_called1 <= 1); + assert(swap_called2 == 0); + assert(move_called2 == 1); // throws + assert(move_assign_called2 == 0); + if (move_called1 != 0) assert(v1.valueless_by_exception()); else assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2).value == 100); } // FIXME: The tests below are just very libc++ specific -#ifdef _LIBCPP_VERSION +# ifdef _LIBCPP_VERSION { - using T1 = ThrowsOnSecondMove; - using T2 = NonThrowingNonNoexceptType; - using V = std::variant; - T2::reset(); + using V = std::variant; + int move_called = 0; V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + V v2(std::in_place_index<1>, 100, &move_called); v1.swap(v2); - assert(T2::move_called == 2); + assert(move_called == 2); assert(std::get<1>(v1).value == 100); assert(std::get<0>(v2).value == 42); assert(std::get<0>(v2).move_count == 1); } { - using T1 = NonThrowingNonNoexceptType; - using T2 = ThrowsOnSecondMove; - using V = std::variant; - T1::reset(); - V v1(std::in_place_index<0>, 42); + using V = std::variant; + int move_called = 0; + V v1(std::in_place_index<0>, 42, &move_called); V v2(std::in_place_index<1>, 100); try { v1.swap(v2); assert(false); } catch (int) { } - assert(T1::move_called == 1); + assert(move_called == 1); assert(v1.valueless_by_exception()); assert(std::get<0>(v2).value == 42); } -#endif -// testing libc++ extension. If either variant stores a nothrow move -// constructible type v1.swap(v2) provides the strong exception safety -// guarantee. -#ifdef _LIBCPP_VERSION +# endif + // testing libc++ extension. If either variant stores a nothrow move + // constructible type v1.swap(v2) provides the strong exception safety + // guarantee. +# ifdef _LIBCPP_VERSION { - - using T1 = ThrowingTypeWithNothrowSwap; - using T2 = NothrowMoveable; - using V = std::variant; - T1::reset(); - T2::reset(); - V v1(std::in_place_index<0>, 42); - V v2(std::in_place_index<1>, 100); + using V = std::variant; + int move_called1 = 0; + int move_assign_called1 = 0; + int swap_called1 = 0; + int move_called2 = 0; + int move_assign_called2 = 0; + int swap_called2 = 0; + V v1(std::in_place_index<0>, 42, &move_called1, &move_assign_called1, &swap_called1); + V v2(std::in_place_index<1>, 100, &move_called2, &move_assign_called2, &swap_called2); try { v1.swap(v2); assert(false); } catch (int) { } - assert(T1::swap_called == 0); - assert(T1::move_called == 1); - assert(T1::move_assign_called == 0); - assert(T2::swap_called == 0); - assert(T2::move_called == 2); - assert(T2::move_assign_called == 0); + assert(swap_called1 == 0); + assert(move_called1 == 1); + assert(move_assign_called1 == 0); + assert(swap_called2 == 0); + assert(move_called2 == 2); + assert(move_assign_called2 == 0); assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2).value == 100); // swap again, but call v2's swap. - T1::reset(); - T2::reset(); + + move_called1 = 0; + move_assign_called1 = 0; + swap_called1 = 0; + move_called2 = 0; + move_assign_called2 = 0; + swap_called2 = 0; + try { v2.swap(v1); assert(false); } catch (int) { } - assert(T1::swap_called == 0); - assert(T1::move_called == 1); - assert(T1::move_assign_called == 0); - assert(T2::swap_called == 0); - assert(T2::move_called == 2); - assert(T2::move_assign_called == 0); + assert(swap_called1 == 0); + assert(move_called1 == 1); + assert(move_assign_called1 == 0); + assert(swap_called2 == 0); + assert(move_called2 == 2); + assert(move_assign_called2 == 0); assert(std::get<0>(v1).value == 42); assert(std::get<1>(v2).value == 100); } -#endif // _LIBCPP_VERSION +# endif // _LIBCPP_VERSION #endif } template -constexpr auto has_swap_member_imp(int) - -> decltype(std::declval().swap(std::declval()), true) { +constexpr auto has_swap_member_imp(int) -> decltype(std::declval().swap(std::declval()), true) { return true; } -template constexpr auto has_swap_member_imp(long) -> bool { +template +constexpr auto has_swap_member_imp(long) -> bool { return false; } -template constexpr bool has_swap_member() { +template +constexpr bool has_swap_member() { return has_swap_member_imp(0); } -void test_swap_sfinae() { +constexpr void test_swap_sfinae() { { // This variant type does not provide either a member or non-member swap // but is still swappable via the generic swap algorithm, since the @@ -508,7 +516,7 @@ void test_swap_sfinae() { } } -void test_swap_noexcept() { +_LIBCPP_CONSTEXPR_SINCE_CXX20 void test_swap_noexcept() { { using V = std::variant; static_assert(std::is_swappable_v && has_swap_member(), ""); @@ -581,12 +589,28 @@ void test_swap_noexcept() { template class std::variant; #endif -int main(int, char**) { +void non_constexpr_test() { test_swap_valueless_by_exception(); + test_swap_same_alternative_throws(); + test_swap_different_alternatives_throws(); +} + +TEST_CONSTEXPR_CXX20 bool test() { test_swap_same_alternative(); test_swap_different_alternatives(); test_swap_sfinae(); test_swap_noexcept(); + return true; +} + +int main(int, char**) { + non_constexpr_test(); + test(); + +#if TEST_STD_VER >= 20 + static_assert(test()); +#endif + return 0; } -- GitLab From 9232591b04d7a4586e88bdbd1c3e513775c73560 Mon Sep 17 00:00:00 2001 From: Louis Dionne Date: Fri, 10 May 2024 08:42:52 -0600 Subject: [PATCH 040/824] [libc++][NFC] Use TestEachPointerType in TestEachAtomicType (#91480) That way, if we ever expand TestEachPointerType we will pick up those changes in TestEachAtomicType. --- libcxx/test/support/atomic_helpers.h | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/libcxx/test/support/atomic_helpers.h b/libcxx/test/support/atomic_helpers.h index 9a32b1ffe85e..0266a0961067 100644 --- a/libcxx/test/support/atomic_helpers.h +++ b/libcxx/test/support/atomic_helpers.h @@ -116,6 +116,7 @@ template