From d26002ac38ee1dea32053e7d12f1bb5dc420ac2d Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 26 Apr 2024 12:00:26 +0900 Subject: [PATCH 001/301] [InstCombine] Fix use-after-free in OptimizePointerDifference() EmitGEPOffset() may remove the old GEP, so be sure to cache the inbounds flag beforehand. --- llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp index a3775fa6f369..51ac77348ed9 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp @@ -2002,26 +2002,29 @@ Value *InstCombinerImpl::OptimizePointerDifference(Value *LHS, Value *RHS, return nullptr; // To avoid duplicating the offset arithmetic, rewrite the GEP to use the - // computed offset. + // computed offset. This may erase the original GEP, so be sure to cache the + // inbounds flag before emitting the offset. // TODO: We should probably do this even if there is only one GEP. bool RewriteGEPs = GEP2 != nullptr; // Emit the offset of the GEP and an intptr_t. + bool GEP1IsInBounds = GEP1->isInBounds(); Value *Result = EmitGEPOffset(GEP1, RewriteGEPs); // If this is a single inbounds GEP and the original sub was nuw, // then the final multiplication is also nuw. if (auto *I = dyn_cast(Result)) - if (IsNUW && !GEP2 && !Swapped && GEP1->isInBounds() && + if (IsNUW && !GEP2 && !Swapped && GEP1IsInBounds && I->getOpcode() == Instruction::Mul) I->setHasNoUnsignedWrap(); // If we have a 2nd GEP of the same base pointer, subtract the offsets. // If both GEPs are inbounds, then the subtract does not have signed overflow. if (GEP2) { + bool GEP2IsInBounds = GEP2->isInBounds(); Value *Offset = EmitGEPOffset(GEP2, RewriteGEPs); Result = Builder.CreateSub(Result, Offset, "gepdiff", /* NUW */ false, - GEP1->isInBounds() && GEP2->isInBounds()); + GEP1IsInBounds && GEP2IsInBounds); } // If we have p - gep(p, ...) then we have to negate the result. -- GitLab From 28b55342e1a8d7a4fddde0fe1678883cd3b2d868 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Thu, 25 Apr 2024 20:04:26 -0700 Subject: [PATCH 002/301] Revert "[MC] Rename temporary symbols of empty name to ".L0 " (#89693)" This reverts commit 96c45a7fa12619c3abd6b81effe4c80f0916b78b. Broke BOLT builders and all pre-merge testing: https://lab.llvm.org/buildbot/#/builders/244/builds/28097 --- lld/test/ELF/mips-eh_frame-pic.s | 4 +-- llvm/include/llvm/Object/ELFObjectFile.h | 5 +-- llvm/lib/MC/ELFObjectWriter.cpp | 6 ---- llvm/test/CodeGen/RISCV/fixups-diff.ll | 2 +- .../LoongArch/dwarf-loongarch-relocs.ll | 18 +++++------ .../DebugInfo/RISCV/dwarf-riscv-relocs.ll | 12 +++---- .../test/DebugInfo/RISCV/relax-debug-frame.ll | 10 +++--- ...ary-symbol.s => riscv-empty-name-symbol.s} | 5 ++- .../JITLink/RISCV/anonymous_symbol.s | 2 +- llvm/test/MC/ELF/RISCV/gen-dwarf.s | 26 +++++++-------- llvm/test/MC/RISCV/cfi-advance.s | 32 ++++--------------- llvm/test/MC/RISCV/fde-reloc.s | 2 +- llvm/test/MC/RISCV/scoped-relaxation.s | 6 ++-- 13 files changed, 52 insertions(+), 78 deletions(-) rename llvm/test/DebugInfo/Symbolize/ELF/{riscv-temporary-symbol.s => riscv-empty-name-symbol.s} (71%) diff --git a/lld/test/ELF/mips-eh_frame-pic.s b/lld/test/ELF/mips-eh_frame-pic.s index c04dbdf57b08..a84c36b0e5ec 100644 --- a/lld/test/ELF/mips-eh_frame-pic.s +++ b/lld/test/ELF/mips-eh_frame-pic.s @@ -36,8 +36,8 @@ # RELOCS: .rel{{a?}}.eh_frame { # ABS32-RELOCS-NEXT: 0x1C R_MIPS_32 .text # ABS64-RELOCS-NEXT: 0x1C R_MIPS_64/R_MIPS_NONE/R_MIPS_NONE .text -# PIC64-RELOCS-NEXT: 0x1C R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE .L0 -# PIC32-RELOCS-NEXT: 0x1C R_MIPS_PC32 .L0 +# PIC64-RELOCS-NEXT: 0x1C R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE +# PIC32-RELOCS-NEXT: 0x1C R_MIPS_PC32 # RELOCS-NEXT: } # ABS64-EH-FRAME: Augmentation data: 0C diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h index 4494d9b96189..1d457be93741 100644 --- a/llvm/include/llvm/Object/ELFObjectFile.h +++ b/llvm/include/llvm/Object/ELFObjectFile.h @@ -801,8 +801,9 @@ Expected ELFObjectFile::getSymbolFlags(DataRefImpl Sym) const { } else if (EF.getHeader().e_machine == ELF::EM_RISCV) { if (Expected NameOrErr = getSymbolName(Sym)) { StringRef Name = *NameOrErr; - // Mark fake labels (used for label differences) and mapping symbols. - if (Name == ".L0 " || Name.starts_with("$d") || Name.starts_with("$x")) + // Mark empty name symbols (used for label differences) and mapping + // symbols. + if (Name.empty() || Name.starts_with("$d") || Name.starts_with("$x")) Result |= SymbolRef::SF_FormatSpecific; } else { // TODO: Actually report errors helpfully. diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp index b8ef2654ed6e..005521bad6e0 100644 --- a/llvm/lib/MC/ELFObjectWriter.cpp +++ b/llvm/lib/MC/ELFObjectWriter.cpp @@ -725,13 +725,7 @@ void ELFWriter::computeSymbolTable( HasLargeSectionIndex = true; } - // Temporary symbols generated for certain assembler features (.eh_frame, - // .debug_line) of an empty name may be referenced by relocations due to - // linker relaxation. Rename them to ".L0 " to match the gas fake label name - // and allow ld/objcopy --discard-locals to discard such symbols. StringRef Name = Symbol.getName(); - if (Name.empty()) - Name = ".L0 "; // Sections have their own string table if (Symbol.getType() != ELF::STT_SECTION) { diff --git a/llvm/test/CodeGen/RISCV/fixups-diff.ll b/llvm/test/CodeGen/RISCV/fixups-diff.ll index 84a7d18ed150..cc1c87b1fe37 100644 --- a/llvm/test/CodeGen/RISCV/fixups-diff.ll +++ b/llvm/test/CodeGen/RISCV/fixups-diff.ll @@ -27,7 +27,7 @@ entry: ; CHECK: } ; CHECK: Section {{.*}} .rela.eh_frame { -; CHECK-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 +; CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 ; CHECK-NEXT: } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll index d28836d56037..d6a1d8d6e136 100644 --- a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll +++ b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll @@ -18,21 +18,21 @@ ; RELOCS-BOTH: Section ({{.*}}) .rela.debug_frame { ; RELOCS-NORL-NEXT: 0x1C R_LARCH_32 .debug_frame 0x0 ; RELOCS-NORL-NEXT: 0x20 R_LARCH_64 .text 0x0 -; RELOCS-ENRL-NEXT: 0x1C R_LARCH_32 .L0 0x0 -; RELOCS-ENRL-NEXT: 0x20 R_LARCH_64 .L0 0x0 -; RELOCS-ENRL-NEXT: 0x28 R_LARCH_ADD64 .L0 0x0 -; RELOCS-ENRL-NEXT: 0x28 R_LARCH_SUB64 .L0 0x0 -; RELOCS-ENRL-NEXT: 0x3F R_LARCH_ADD6 .L0 0x0 -; RELOCS-ENRL-NEXT: 0x3F R_LARCH_SUB6 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x1C R_LARCH_32 0x0 +; RELOCS-ENRL-NEXT: 0x20 R_LARCH_64 0x0 +; RELOCS-ENRL-NEXT: 0x28 R_LARCH_ADD64 0x0 +; RELOCS-ENRL-NEXT: 0x28 R_LARCH_SUB64 0x0 +; RELOCS-ENRL-NEXT: 0x3F R_LARCH_ADD6 0x0 +; RELOCS-ENRL-NEXT: 0x3F R_LARCH_SUB6 0x0 ; RELOCS-BOTH-NEXT: } ; RELOCS-BOTH: Section ({{.*}}) .rela.debug_line { ; RELOCS-BOTH-NEXT: 0x22 R_LARCH_32 .debug_line_str 0x0 ; RELOCS-BOTH-NEXT: 0x31 R_LARCH_32 .debug_line_str 0x2 ; RELOCS-BOTH-NEXT: 0x46 R_LARCH_32 .debug_line_str 0x1B ; RELOCS-NORL-NEXT: 0x4F R_LARCH_64 .text 0x0 -; RELOCS-ENRL-NEXT: 0x4F R_LARCH_64 .L0 0x0 -; RELOCS-ENRL-NEXT: 0x5F R_LARCH_ADD16 .L0 0x0 -; RELOCS-ENRL-NEXT: 0x5F R_LARCH_SUB16 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x4F R_LARCH_64 0x0 +; RELOCS-ENRL-NEXT: 0x5F R_LARCH_ADD16 0x0 +; RELOCS-ENRL-NEXT: 0x5F R_LARCH_SUB16 0x0 ; RELOCS-BOTH-NEXT: } ; RELOCS-BOTH-NEXT: ] diff --git a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll index 99594b5e01e9..e5de1713f4e0 100644 --- a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll +++ b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll @@ -6,14 +6,14 @@ ; Check that we actually have relocations, otherwise this is kind of pointless. ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_info { -; READOBJ-RELOCS: 0x1B R_RISCV_ADD32 .L0 0x0 -; READOBJ-RELOCS-NEXT: 0x1B R_RISCV_SUB32 .L0 0x0 +; READOBJ-RELOCS: 0x1B R_RISCV_ADD32 0x0 +; READOBJ-RELOCS-NEXT: 0x1B R_RISCV_SUB32 0x0 ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_frame { -; READOBJ-RELOCS: 0x20 R_RISCV_ADD32 .L0 0x0 -; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 +; READOBJ-RELOCS: 0x20 R_RISCV_ADD32 0x0 +; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 0x0 ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_line { -; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 .L0 0x0 -; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 .L0 0x0 +; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 0x0 +; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 0x0 ; Check that we can print the source, even with relocations. ; OBJDUMP-SOURCE: Disassembly of section .text: diff --git a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll index ffef0ec23406..f655a7c0a7ef 100644 --- a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll +++ b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll @@ -4,11 +4,11 @@ ; RUN: | FileCheck -check-prefix=RELAX-DWARFDUMP %s ; ; RELAX: Section ({{.*}}) .rela.eh_frame { -; RELAX-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 -; RELAX-NEXT: 0x30 R_RISCV_32_PCREL .L0 0x0 -; RELAX-NEXT: 0x44 R_RISCV_32_PCREL .L0 0x0 -; RELAX-NEXT: 0x48 R_RISCV_ADD32 .L0 0x0 -; RELAX-NEXT: 0x48 R_RISCV_SUB32 .L0 0x0 +; RELAX-NEXT: 0x1C R_RISCV_32_PCREL 0x0 +; RELAX-NEXT: 0x30 R_RISCV_32_PCREL 0x0 +; RELAX-NEXT: 0x44 R_RISCV_32_PCREL 0x0 +; RELAX-NEXT: 0x48 R_RISCV_ADD32 0x0 +; RELAX-NEXT: 0x48 R_RISCV_SUB32 0x0 ; RELAX-NEXT: } ; RELAX-DWARFDUMP-NOT: error: failed to compute relocation diff --git a/llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s b/llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s similarity index 71% rename from llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s rename to llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s index 0b54f104ab95..1e0fa8a30618 100644 --- a/llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s +++ b/llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s @@ -1,11 +1,10 @@ # REQUIRES: riscv-registered-target -## Ignore .L0 symbols that are generated by LLVM integrated assembler and GNU -## assembler for .debug_line/.eh_frame related assembler directives. +## Ignore empty name symbols. # RUN: llvm-mc -filetype=obj -triple=riscv64 %s -o %t # RUN: llvm-readelf -s %t | FileCheck %s --check-prefix=SYM -# SYM: 0000000000000004 0 NOTYPE LOCAL DEFAULT [[#]] .L0 {{$}} +# SYM: 0000000000000004 0 NOTYPE LOCAL DEFAULT [[#]] {{$}} # SYM: 0000000000000000 0 NOTYPE GLOBAL DEFAULT [[#]] foo ## Make sure we test at an address larger than or equal to an empty name symbol. diff --git a/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s b/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s index e7114e4d643c..a5038022dfe0 100644 --- a/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s +++ b/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s @@ -7,7 +7,7 @@ # the section start and section end. So that by relocating these symbol, the section length # can be calculated. # -# CHECK: Creating defined graph symbol for ELF symbol ".L0 " +# CHECK: Creating defined graph symbol for ELF symbol "" # CHECK: Creating defined graph symbol for ELF symbol "main" .text .globl main diff --git a/llvm/test/MC/ELF/RISCV/gen-dwarf.s b/llvm/test/MC/ELF/RISCV/gen-dwarf.s index 34d02f5da44f..342ed1cc0e7e 100644 --- a/llvm/test/MC/ELF/RISCV/gen-dwarf.s +++ b/llvm/test/MC/ELF/RISCV/gen-dwarf.s @@ -40,28 +40,28 @@ # CHECK-NEXT: 0x00000020: [DW_RLE_end_of_list ] # RELOC: Section ([[#]]) .rela.eh_frame { -# RELOC-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 -# RELOC-NEXT: 0x20 R_RISCV_ADD32 .L0 0x0 -# RELOC-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 -# RELOC-NEXT: 0x25 R_RISCV_SET6 .L0 0x0 -# RELOC-NEXT: 0x25 R_RISCV_SUB6 .L0 0x0 -# RELOC-NEXT: 0x34 R_RISCV_32_PCREL .L0 0x0 +# RELOC-NEXT: 0x1C R_RISCV_32_PCREL 0x0 +# RELOC-NEXT: 0x20 R_RISCV_ADD32 0x0 +# RELOC-NEXT: 0x20 R_RISCV_SUB32 0x0 +# RELOC-NEXT: 0x25 R_RISCV_SET6 0x0 +# RELOC-NEXT: 0x25 R_RISCV_SUB6 0x0 +# RELOC-NEXT: 0x34 R_RISCV_32_PCREL 0x0 # RELOC-NEXT: } # RELOC: Section ([[#]]) .rela.debug_rnglists { # RELOC-NEXT: 0xD R_RISCV_64 .text.foo 0x0 -# RELOC-NEXT: 0x15 R_RISCV_SET_ULEB128 .L0 0x0 +# RELOC-NEXT: 0x15 R_RISCV_SET_ULEB128 0x0 # RELOC-NEXT: 0x15 R_RISCV_SUB_ULEB128 .text.foo 0x0 # RELOC-NEXT: 0x17 R_RISCV_64 .text.bar 0x0 # RELOC-NEXT: } # RELOC: Section ([[#]]) .rela.debug_line { -# RELOC: R_RISCV_ADD16 .L0 0x0 -# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 -# RELOC-NEXT: R_RISCV_ADD16 .L0 0x0 -# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 -# RELOC-NEXT: R_RISCV_ADD16 .L0 0x0 -# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 +# RELOC: R_RISCV_ADD16 0x0 +# RELOC-NEXT: R_RISCV_SUB16 0x0 +# RELOC-NEXT: R_RISCV_ADD16 0x0 +# RELOC-NEXT: R_RISCV_SUB16 0x0 +# RELOC-NEXT: R_RISCV_ADD16 0x0 +# RELOC-NEXT: R_RISCV_SUB16 0x0 # RELOC: } # RELOC: Hex dump of section '.eh_frame': diff --git a/llvm/test/MC/RISCV/cfi-advance.s b/llvm/test/MC/RISCV/cfi-advance.s index b99af38f553a..c4af390be757 100644 --- a/llvm/test/MC/RISCV/cfi-advance.s +++ b/llvm/test/MC/RISCV/cfi-advance.s @@ -1,27 +1,13 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 %s -o %t.o -# RUN: llvm-readelf -sr %t.o | FileCheck %s +# RUN: llvm-readobj -r %t.o | FileCheck -check-prefix=CHECK %s # RUN: llvm-dwarfdump --debug-frame %t.o 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-DWARFDUMP %s - -# CHECK: Relocation section '.rela.text1' at offset {{.*}} contains 1 entries: -# CHECK-NEXT: Offset Info Type Sym. Value Symbol's Name + Addend -# CHECK-NEXT: 00000000 00000313 R_RISCV_CALL_PLT 00000004 .L0 + 0 -# CHECK-EMPTY: -# CHECK-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 3 entries: -# CHECK: Offset Info Type Sym. Value Symbol's Name + Addend -# CHECK-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0 -# CHECK-NEXT: 00000035 00000b35 R_RISCV_SET6 00010178 .L0 + 0 -# CHECK-NEXT: 00000035 00000934 R_RISCV_SUB6 0001016e .L0 + 0 -# CHECK-EMPTY: -# CHECK: Symbol table '.symtab' contains 15 entries: -# CHECK-NEXT: Num: Value Size Type Bind Vis Ndx Name -# CHECK-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND -# CHECK-NEXT: 1: 00000000 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} -# CHECK: 3: 00000004 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}} -# CHECK: 9: 0001016e 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} -# CHECK: 11: 00010178 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} - +# CHECK: .rela.eh_frame { +# CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 +# CHECK-NEXT: 0x35 R_RISCV_SET6 0x0 +# CHECK-NEXT: 0x35 R_RISCV_SUB6 0x0 +# CHECK-NEXT: } # CHECK-DWARFDUMP: DW_CFA_advance_loc1: 104 # CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 # CHECK-DWARFDUMP-NEXT: DW_CFA_advance_loc2: 259 @@ -37,9 +23,6 @@ test: .cfi_startproc nop -## This looks similar to fake label names ".L0 ". Even if this is ".L0 ", -## the assembler will not conflate it with fake labels. -.L0: .zero 100, 0x90 .cfi_def_cfa_offset 8 nop @@ -53,6 +36,3 @@ test: .cfi_def_cfa_offset 8 nop .cfi_endproc - -.section .text1,"ax" -call .L0 diff --git a/llvm/test/MC/RISCV/fde-reloc.s b/llvm/test/MC/RISCV/fde-reloc.s index 81ec426c8b61..1db8929e0747 100644 --- a/llvm/test/MC/RISCV/fde-reloc.s +++ b/llvm/test/MC/RISCV/fde-reloc.s @@ -12,7 +12,7 @@ func: .cfi_endproc # CHECK: Section (4) .rela.eh_frame { -# CHECK-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 +# CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 # CHECK-NEXT: } # CHECK: Hex dump of section '.eh_frame': # CHECK-NEXT: 0x00000000 10000000 00000000 017a5200 017c0101 diff --git a/llvm/test/MC/RISCV/scoped-relaxation.s b/llvm/test/MC/RISCV/scoped-relaxation.s index 56394fd80532..0b797ee5aca5 100644 --- a/llvm/test/MC/RISCV/scoped-relaxation.s +++ b/llvm/test/MC/RISCV/scoped-relaxation.s @@ -9,7 +9,7 @@ .dword function - . # CHECK: 0x0 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x0 R_RISCV_SUB64 .L0 0x0 +# CHECK-NEXT: 0x0 R_RISCV_SUB64 0x0 # Relaxed reference, this will resolve to a pair of `RISCV_ADD64` and # `RISCV_SUB64` relocation. @@ -19,7 +19,7 @@ .option pop # CHECK: 0x8 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x8 R_RISCV_SUB64 .L0 0x0 +# CHECK-NEXT: 0x8 R_RISCV_SUB64 0x0 # Unrelaxed reference, this will resolve to a pair of `RISCV_ADD64` and # `RISCV_SUB64` relocation due to relaxation being sticky to the file. @@ -29,6 +29,6 @@ .option pop # CHECK: 0x10 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x10 R_RISCV_SUB64 .L0 0x0 +# CHECK-NEXT: 0x10 R_RISCV_SUB64 0x0 # CHECK: } -- GitLab From 59bfc31068746dcae4cfb3cc648cd5cf243a3ccd Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Thu, 25 Apr 2024 20:10:37 -0700 Subject: [PATCH 003/301] [CI] Use trunk Clang in BOLT testing --- .ci/monolithic-linux.sh | 1 - 1 file changed, 1 deletion(-) diff --git a/.ci/monolithic-linux.sh b/.ci/monolithic-linux.sh index b347c443da67..b00a4b984a1d 100755 --- a/.ci/monolithic-linux.sh +++ b/.ci/monolithic-linux.sh @@ -48,7 +48,6 @@ cmake -S "${MONOREPO_ROOT}"/llvm -B "${BUILD_DIR}" \ -D LLVM_LIT_ARGS="-v --xunit-xml-output ${BUILD_DIR}/test-results.xml --timeout=1200 --time-tests" \ -D LLVM_ENABLE_LLD=ON \ -D CMAKE_CXX_FLAGS=-gmlt \ - -D BOLT_CLANG_EXE=/usr/bin/clang \ -D LLVM_CCACHE_BUILD=ON \ -D MLIR_ENABLE_BINDINGS_PYTHON=ON -- GitLab From 2de0bedfebb77a6c8a5b0d00902f796fa4022fd6 Mon Sep 17 00:00:00 2001 From: NorthBlue333 <43409865+NorthBlue333@users.noreply.github.com> Date: Fri, 26 Apr 2024 05:34:49 +0200 Subject: [PATCH 004/301] [clang-format] Do not update cursor pos if no includes replacement (#77456) Fix https://github.com/llvm/llvm-project/issues/77450. --------- Signed-off-by: NorthBlue333 Co-authored-by: Owen Pan --- clang/lib/Format/Format.cpp | 3 + clang/unittests/Format/SortIncludesTest.cpp | 122 +++++++++++++++++++- 2 files changed, 122 insertions(+), 3 deletions(-) diff --git a/clang/lib/Format/Format.cpp b/clang/lib/Format/Format.cpp index 373dd4e60bf3..c8d8ec3afbd9 100644 --- a/clang/lib/Format/Format.cpp +++ b/clang/lib/Format/Format.cpp @@ -3116,6 +3116,7 @@ static void sortCppIncludes(const FormatStyle &Style, return; } + const auto OldCursor = Cursor ? *Cursor : 0; std::string result; for (unsigned Index : Indices) { if (!result.empty()) { @@ -3139,6 +3140,8 @@ static void sortCppIncludes(const FormatStyle &Style, // the entire range of blocks. Otherwise, no replacement is generated. if (replaceCRLF(result) == replaceCRLF(std::string(Code.substr( IncludesBeginOffset, IncludesBlockSize)))) { + if (Cursor) + *Cursor = OldCursor; return; } diff --git a/clang/unittests/Format/SortIncludesTest.cpp b/clang/unittests/Format/SortIncludesTest.cpp index 772eb53806b4..824fa0078cd0 100644 --- a/clang/unittests/Format/SortIncludesTest.cpp +++ b/clang/unittests/Format/SortIncludesTest.cpp @@ -6,19 +6,19 @@ // //===----------------------------------------------------------------------===// -#include "FormatTestUtils.h" +#include "FormatTestBase.h" #include "clang/Format/Format.h" #include "llvm/ADT/StringRef.h" #include "llvm/Support/Debug.h" #include "gtest/gtest.h" -#define DEBUG_TYPE "format-test" +#define DEBUG_TYPE "sort-includes-test" namespace clang { namespace format { namespace { -class SortIncludesTest : public ::testing::Test { +class SortIncludesTest : public test::FormatTestBase { protected: std::vector GetCodeRange(StringRef Code) { return std::vector(1, tooling::Range(0, Code.size())); @@ -821,6 +821,122 @@ TEST_F(SortIncludesTest, CalculatesCorrectCursorPositionWithRegrouping) { EXPECT_EQ(27u, newCursor(Code, 28)); // Start of last line } +TEST_F(SortIncludesTest, + CalculatesCorrectCursorPositionWhenNoReplacementsWithRegroupingAndCRLF) { + Style.IncludeBlocks = Style.IBS_Regroup; + FmtStyle.LineEnding = FormatStyle::LE_CRLF; + Style.IncludeCategories = { + {"^\"a\"", 0, 0, false}, {"^\"b\"", 1, 1, false}, {".*", 2, 2, false}}; + std::string Code = "#include \"a\"\r\n" // Start of line: 0 + "\r\n" // Start of line: 14 + "#include \"b\"\r\n" // Start of line: 16 + "\r\n" // Start of line: 30 + "#include \"c\"\r\n" // Start of line: 32 + "\r\n" // Start of line: 46 + "int i;"; // Start of line: 48 + verifyNoChange(Code); + EXPECT_EQ(0u, newCursor(Code, 0)); + EXPECT_EQ(14u, newCursor(Code, 14)); + EXPECT_EQ(16u, newCursor(Code, 16)); + EXPECT_EQ(30u, newCursor(Code, 30)); + EXPECT_EQ(32u, newCursor(Code, 32)); + EXPECT_EQ(46u, newCursor(Code, 46)); + EXPECT_EQ(48u, newCursor(Code, 48)); +} + +TEST_F( + SortIncludesTest, + CalculatesCorrectCursorPositionWhenRemoveLinesReplacementsWithRegroupingAndCRLF) { + Style.IncludeBlocks = Style.IBS_Regroup; + FmtStyle.LineEnding = FormatStyle::LE_CRLF; + Style.IncludeCategories = {{".*", 0, 0, false}}; + std::string Code = "#include \"a\"\r\n" // Start of line: 0 + "\r\n" // Start of line: 14 + "#include \"b\"\r\n" // Start of line: 16 + "\r\n" // Start of line: 30 + "#include \"c\"\r\n" // Start of line: 32 + "\r\n" // Start of line: 46 + "int i;"; // Start of line: 48 + std::string Expected = "#include \"a\"\r\n" // Start of line: 0 + "#include \"b\"\r\n" // Start of line: 14 + "#include \"c\"\r\n" // Start of line: 28 + "\r\n" // Start of line: 42 + "int i;"; // Start of line: 44 + EXPECT_EQ(Expected, sort(Code)); + EXPECT_EQ(0u, newCursor(Code, 0)); + EXPECT_EQ( + 14u, + newCursor(Code, 14)); // cursor on empty line in include block is ignored + EXPECT_EQ(14u, newCursor(Code, 16)); + EXPECT_EQ( + 30u, + newCursor(Code, 30)); // cursor on empty line in include block is ignored + EXPECT_EQ(28u, newCursor(Code, 32)); + EXPECT_EQ(42u, newCursor(Code, 46)); + EXPECT_EQ(44u, newCursor(Code, 48)); +} + +// FIXME: the tests below should pass. +#if 0 +TEST_F( + SortIncludesTest, + CalculatesCorrectCursorPositionWhenNewLineReplacementsWithRegroupingAndCRLF) { + Style.IncludeBlocks = Style.IBS_Regroup; + FmtStyle.LineEnding = FormatStyle::LE_CRLF; + Style.IncludeCategories = { + {"^\"a\"", 0, 0, false}, {"^\"b\"", 1, 1, false}, {".*", 2, 2, false}}; + std::string Code = "#include \"a\"\r\n" // Start of line: 0 + "#include \"b\"\r\n" // Start of line: 14 + "#include \"c\"\r\n" // Start of line: 28 + "\r\n" // Start of line: 42 + "int i;"; // Start of line: 44 + std::string Expected = "#include \"a\"\r\n" // Start of line: 0 + "\r\n" // Start of line: 14 + "#include \"b\"\r\n" // Start of line: 16 + "\r\n" // Start of line: 30 + "#include \"c\"\r\n" // Start of line: 32 + "\r\n" // Start of line: 46 + "int i;"; // Start of line: 48 + EXPECT_EQ(Expected, sort(Code)); + EXPECT_EQ(0u, newCursor(Code, 0)); + EXPECT_EQ(15u, newCursor(Code, 16)); + EXPECT_EQ(30u, newCursor(Code, 32)); + EXPECT_EQ(44u, newCursor(Code, 46)); + EXPECT_EQ(46u, newCursor(Code, 48)); +} + +TEST_F( + SortIncludesTest, + CalculatesCorrectCursorPositionWhenNoNewLineReplacementsWithRegroupingAndCRLF) { + Style.IncludeBlocks = Style.IBS_Regroup; + FmtStyle.LineEnding = FormatStyle::LE_CRLF; + Style.IncludeCategories = { + {"^\"a\"", 0, 0, false}, {"^\"b\"", 1, 1, false}, {".*", 2, 2, false}}; + std::string Code = "#include \"a\"\r\n" // Start of line: 0 + "\r\n" // Start of line: 14 + "#include \"c\"\r\n" // Start of line: 16 + "\r\n" // Start of line: 30 + "#include \"b\"\r\n" // Start of line: 32 + "\r\n" // Start of line: 46 + "int i;"; // Start of line: 48 + std::string Expected = "#include \"a\"\r\n" // Start of line: 0 + "\r\n" // Start of line: 14 + "#include \"b\"\r\n" // Start of line: 16 + "\r\n" // Start of line: 30 + "#include \"c\"\r\n" // Start of line: 32 + "\r\n" // Start of line: 46 + "int i;"; // Start of line: 48 + EXPECT_EQ(Expected, sort(Code)); + EXPECT_EQ(0u, newCursor(Code, 0)); + EXPECT_EQ(14u, newCursor(Code, 14)); + EXPECT_EQ(30u, newCursor(Code, 32)); + EXPECT_EQ(30u, newCursor(Code, 30)); + EXPECT_EQ(15u, newCursor(Code, 15)); + EXPECT_EQ(44u, newCursor(Code, 46)); + EXPECT_EQ(46u, newCursor(Code, 48)); +} +#endif + TEST_F(SortIncludesTest, DeduplicateIncludes) { EXPECT_EQ("#include \n" "#include \n" -- GitLab From e982032199bbc2feb5acec0f6ae023239a40c1ca Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Thu, 25 Apr 2024 20:42:40 -0700 Subject: [PATCH 005/301] [BOLT,RISCV] Remove empty name special case from #68977 The special case is unneeded after #89693. Pull Request: https://github.com/llvm/llvm-project/pull/90004 --- bolt/lib/Rewrite/RewriteInstance.cpp | 6 ------ .../RISCV/{unnamed-sym-no-entry.c => fake-label-no-entry.c} | 4 ++-- 2 files changed, 2 insertions(+), 8 deletions(-) rename bolt/test/RISCV/{unnamed-sym-no-entry.c => fake-label-no-entry.c} (88%) diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index a6b2f3cc0850..3cf0e749f9d6 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -1725,12 +1725,6 @@ void RewriteInstance::adjustFunctionBoundaries() { if (!Function.isSymbolValidInScope(Symbol, SymbolSize)) break; - // Ignore unnamed symbols. Used, for example, by debugging info on RISC-V. - if (BC->isRISCV() && cantFail(Symbol.getName()).empty()) { - ++NextSymRefI; - continue; - } - // Skip basic block labels. This happens on RISC-V with linker relaxation // enabled because every branch needs a relocation and corresponding // symbol. We don't want to add such symbols as entry points. diff --git a/bolt/test/RISCV/unnamed-sym-no-entry.c b/bolt/test/RISCV/fake-label-no-entry.c similarity index 88% rename from bolt/test/RISCV/unnamed-sym-no-entry.c rename to bolt/test/RISCV/fake-label-no-entry.c index b4173506b213..bd125263101b 100644 --- a/bolt/test/RISCV/unnamed-sym-no-entry.c +++ b/bolt/test/RISCV/fake-label-no-entry.c @@ -5,12 +5,12 @@ // RUN: %clang %cflags -g -Wl,-q -o %t %s -/// Verify that the binary indeed contains an unnamed symbol at _start +/// Verify that the binary indeed contains a fake label ".L0 " at _start. // RUN: llvm-readelf -s %t | FileCheck %s --check-prefix=CHECK-ELF // CHECK-ELF-DAG: [[#%x,START:]] {{.*}} FUNC GLOBAL DEFAULT [[#%d,SECTION:]] _start{{$}} // CHECK-ELF-DAG: [[#%x,START]] {{.*}} NOTYPE LOCAL DEFAULT [[#SECTION]] .L0 {{$}} -/// Verify that BOLT did not create an extra entry point for the unnamed symbol +/// Verify that BOLT did not create an extra entry point for the fake label. // RUN: llvm-bolt -o %t.bolt %t --print-cfg | FileCheck %s // CHECK: Binary Function "_start" after building cfg { // CHECK: IsMultiEntry: 0 -- GitLab From 21b84928f99169a5679c9195c2307c2dd4c8f1fd Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Thu, 25 Apr 2024 21:29:24 -0700 Subject: [PATCH 006/301] [msan] Don't crash in CreateShadowCast on vscale (#90126) Code expects `VectorOrPrimitiveTypeSizeInBits` compile time value, which is not available for vscale. In trivial case of the same type we need to do nothing. --- .../Instrumentation/MemorySanitizer.cpp | 2 + .../Instrumentation/MemorySanitizer/vscale.ll | 107 ++++++++++++++++++ 2 files changed, 109 insertions(+) create mode 100644 llvm/test/Instrumentation/MemorySanitizer/vscale.ll diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index e5ef0333696d..66ee2fce8313 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -2506,6 +2506,8 @@ struct MemorySanitizerVisitor : public InstVisitor { Value *CreateShadowCast(IRBuilder<> &IRB, Value *V, Type *dstTy, bool Signed = false) { Type *srcTy = V->getType(); + if (srcTy == dstTy) + return V; size_t srcSizeInBits = VectorOrPrimitiveTypeSizeInBits(srcTy); size_t dstSizeInBits = VectorOrPrimitiveTypeSizeInBits(dstTy); if (srcSizeInBits > 1 && dstSizeInBits == 1) diff --git a/llvm/test/Instrumentation/MemorySanitizer/vscale.ll b/llvm/test/Instrumentation/MemorySanitizer/vscale.ll new file mode 100644 index 000000000000..b1c641881570 --- /dev/null +++ b/llvm/test/Instrumentation/MemorySanitizer/vscale.ll @@ -0,0 +1,107 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt < %s -S -msan-check-access-address=0 -passes="msan" 2>&1 | FileCheck %s + +target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @test_load_store_i32(ptr %a, ptr %b) sanitize_memory { +; CHECK-LABEL: define void @test_load_store_i32( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP1:%.*]] = load , ptr [[A]], align 16 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load , ptr [[TMP4]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store [[_MSLD]], ptr [[TMP7]], align 16 +; CHECK-NEXT: store [[TMP1]], ptr [[B]], align 16 +; CHECK-NEXT: ret void +; + %1 = load , ptr %a + store %1, ptr %b + ret void +} + +define void @test_load_store_add_int(ptr %a, ptr %b) sanitize_memory { +; CHECK-LABEL: define void @test_load_store_add_int( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP1:%.*]] = load , ptr [[A]], align 64 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load , ptr [[TMP4]], align 64 +; CHECK-NEXT: [[TMP5:%.*]] = load , ptr [[B]], align 64 +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080 +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load , ptr [[TMP8]], align 64 +; CHECK-NEXT: [[_MSPROP:%.*]] = or [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP9:%.*]] = add [[TMP1]], [[TMP5]] +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 87960930222080 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: store [[_MSLD1]], ptr [[TMP12]], align 64 +; CHECK-NEXT: store [[TMP5]], ptr [[B]], align 64 +; CHECK-NEXT: ret void +; + %1 = load , ptr %a + %2 = load , ptr %b + %3 = add %1, %2 + store %2, ptr %b + ret void +} + +define void @test_load_store_float(ptr %a, ptr %b) sanitize_memory { +; CHECK-LABEL: define void @test_load_store_float( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP1:%.*]] = load , ptr [[A]], align 16 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load , ptr [[TMP4]], align 16 +; CHECK-NEXT: [[TMP5:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP6:%.*]] = xor i64 [[TMP5]], 87960930222080 +; CHECK-NEXT: [[TMP7:%.*]] = inttoptr i64 [[TMP6]] to ptr +; CHECK-NEXT: store [[_MSLD]], ptr [[TMP7]], align 16 +; CHECK-NEXT: store [[TMP1]], ptr [[B]], align 16 +; CHECK-NEXT: ret void +; + %1 = load , ptr %a + store %1, ptr %b + ret void +} + +define void @test_load_store_add_float(ptr %a, ptr %b) sanitize_memory { +; CHECK-LABEL: define void @test_load_store_add_float( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP1:%.*]] = load , ptr [[A]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load , ptr [[TMP4]], align 8 +; CHECK-NEXT: [[TMP5:%.*]] = load , ptr [[B]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP7:%.*]] = xor i64 [[TMP6]], 87960930222080 +; CHECK-NEXT: [[TMP8:%.*]] = inttoptr i64 [[TMP7]] to ptr +; CHECK-NEXT: [[_MSLD1:%.*]] = load , ptr [[TMP8]], align 8 +; CHECK-NEXT: [[_MSPROP:%.*]] = or [[_MSLD]], [[_MSLD1]] +; CHECK-NEXT: [[TMP9:%.*]] = fadd [[TMP1]], [[TMP5]] +; CHECK-NEXT: [[TMP10:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP11:%.*]] = xor i64 [[TMP10]], 87960930222080 +; CHECK-NEXT: [[TMP12:%.*]] = inttoptr i64 [[TMP11]] to ptr +; CHECK-NEXT: store [[_MSLD1]], ptr [[TMP12]], align 8 +; CHECK-NEXT: store [[TMP5]], ptr [[B]], align 8 +; CHECK-NEXT: ret void +; + %1 = load , ptr %a + %2 = load , ptr %b + %3 = fadd %1, %2 + store %2, ptr %b + ret void +} -- GitLab From 4b255085833b58392d7699aaf5c20ea49559fda9 Mon Sep 17 00:00:00 2001 From: SunilKuravinakop <98882378+SunilKuravinakop@users.noreply.github.com> Date: Fri, 26 Apr 2024 10:31:55 +0530 Subject: [PATCH 007/301] Notifying assume directive as 'worked on'. (#90022) Notifying assume directive as 'worked on'. When checked on slack channel, nobody was working on assume directive. Changes to be committed: modified: clang/docs/OpenMPSupport.rst --------- Co-authored-by: Sunil Kuravinakop --- clang/docs/OpenMPSupport.rst | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/clang/docs/OpenMPSupport.rst b/clang/docs/OpenMPSupport.rst index f8146bc365e8..5e63b2c0f0be 100644 --- a/clang/docs/OpenMPSupport.rst +++ b/clang/docs/OpenMPSupport.rst @@ -310,7 +310,9 @@ implementation. +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | misc | dispatch construct and function variant argument adjustment | :part:`worked on` | D99537, D99679 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ -| misc | assume and assumes directives | :part:`worked on` | | +| misc | assumes directives | :part:`worked on` | | ++------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ +| misc | assume directive | :part:`worked on` | | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ | misc | nothing directive | :good:`done` | D123286 | +------------------------------+--------------------------------------------------------------+--------------------------+-----------------------------------------------------------------------+ -- GitLab From 65fb80beaee235b76023fae3277694c56a1b7d99 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Fri, 26 Apr 2024 07:06:49 +0200 Subject: [PATCH 008/301] [GlobalIsel] Add Gallery to MIR Patterns (#89974) examples for fold of zext(trunc:nuw) --- llvm/docs/GlobalISel/MIRPatterns.rst | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+) diff --git a/llvm/docs/GlobalISel/MIRPatterns.rst b/llvm/docs/GlobalISel/MIRPatterns.rst index 728e32470144..d7dce1b978cd 100644 --- a/llvm/docs/GlobalISel/MIRPatterns.rst +++ b/llvm/docs/GlobalISel/MIRPatterns.rst @@ -514,3 +514,40 @@ of operands. (match (does_not_bind $tmp, $x) (G_MUL $dst, $x, $tmp)), (apply (COPY $dst, $x))>; + + + + +Gallery +======= + +We should use precise patterns that state our intentions. Please avoid +using wip_match_opcode in patterns. + +.. code-block:: text + :caption: Example fold zext(trunc:nuw) + + // Imprecise: matches any G_ZEXT + def zext : GICombineRule< + (defs root:$root), + (match (wip_match_opcode G_ZEXT):$root, + [{ return Helper.matchZextOfTrunc(*${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; + + + // Imprecise: matches G_ZEXT of G_TRUNC + def zext_of_trunc : GICombineRule< + (defs root:$root), + (match (G_TRUNC $src, $x), + (G_ZEXT $root, $src), + [{ return Helper.matchZextOfTrunc(${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFnMO(${root}, ${matchinfo}); }])>; + + + // Precise: matches G_ZEXT of G_TRUNC with nuw flag + def zext_of_trunc_nuw : GICombineRule< + (defs root:$root), + (match (G_TRUNC $src, $x, (MIFlags NoUWrap)), + (G_ZEXT $root, $src), + [{ return Helper.matchZextOfTrunc(${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFnMO(${root}, ${matchinfo}); }])>; -- GitLab From 7840fa91a24ec7b9b771fd105ee1a9e1ba58837f Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Fri, 26 Apr 2024 13:06:28 +0800 Subject: [PATCH 009/301] [RISCV] Fix doPRE not checking for ignored AVLs This fixes a crash introduced in 011a65353b8b4dc018541f86356f2dfa0f124f1a that showed up when compiling with -mrvv-vector-bits=zvl. Beforehand, if a basic block only contained vmv.s.x the AVL register in VSETVLIInfo would have been NoRegister since it ignores VL. In doPRE if AvailableInfo had a register AVL we checked that it dominated, but coincidentally this failed for NoRegister. Now that the ignored AVL case is separated out, check for it and bail. As a side note, it turns out 011a65353b8b4dc018541f86356f2dfa0f124f1a is less NFC than it seems as we can now do PRE on blocks where AvailableInfo's AVL is VLMAX. --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 5 +++++ .../CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir | 13 +++++++++++++ 2 files changed, 18 insertions(+) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index 3feb7ec34754..c40b9031543f 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -1511,6 +1511,11 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) { return; } + // If the AVL isn't used in its predecessors then bail, since we have no AVL + // to insert a vsetvli with. + if (AvailableInfo.hasAVLIgnored()) + return; + // Model the effect of changing the input state of the block MBB to // AvailableInfo. We're looking for two issues here; one legality, // one profitability. diff --git a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir index 596ea1c39fce..16c4a1a0a89e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir +++ b/llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.mir @@ -130,6 +130,10 @@ ret void } + define void @pre_undemanded_vl() { + ret void + } + declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) declare @llvm.riscv.vadd.nxv1i64.nxv1i64.i64(, , , i64) #1 @@ -1041,3 +1045,12 @@ body: | PseudoRET ... +--- +name: pre_undemanded_vl +body: | + bb.0: + PseudoBR %bb.1 + bb.1: + %x:gpr = PseudoVMV_X_S undef $noreg, 6 + PseudoBR %bb.1 +... -- GitLab From f4efa067435c8137718c907bf0de2b891b76552d Mon Sep 17 00:00:00 2001 From: Daniil Kovalev Date: Fri, 26 Apr 2024 08:26:15 +0300 Subject: [PATCH 010/301] [PAC][clang] Define `PointerAuthQualifier` and `PointerAuthenticationMode` (#84384) This brings declarations of `PointerAuthQualifier` class and `PointerAuthenticationMode` enum and related functions required for PAuth support in lldb (see #84387) from downstream Apple's code. See #84387 for tests as well. Co-authored-by: Ahmed Bougacha Co-authored-by: John McCall --------- Co-authored-by: John McCall Co-authored-by: Ahmed Bougacha --- .../EasilySwappableParametersCheck.cpp | 17 +- clang/include/clang/AST/ASTContext.h | 10 + clang/include/clang/AST/AbstractBasicReader.h | 4 +- clang/include/clang/AST/AbstractBasicWriter.h | 4 +- clang/include/clang/AST/Type.h | 254 ++++++++++++++++-- clang/include/clang/Basic/LangOptions.h | 7 + .../include/clang/Basic/PointerAuthOptions.h | 23 ++ 7 files changed, 283 insertions(+), 36 deletions(-) create mode 100644 clang/include/clang/Basic/PointerAuthOptions.h diff --git a/clang-tools-extra/clang-tidy/bugprone/EasilySwappableParametersCheck.cpp b/clang-tools-extra/clang-tidy/bugprone/EasilySwappableParametersCheck.cpp index 84e99c7fafc7..10868129e76d 100644 --- a/clang-tools-extra/clang-tidy/bugprone/EasilySwappableParametersCheck.cpp +++ b/clang-tools-extra/clang-tidy/bugprone/EasilySwappableParametersCheck.cpp @@ -967,7 +967,8 @@ approximateStandardConversionSequence(const TheCheck &Check, QualType From, // Get out the qualifiers of the original type. This will always be // re-applied to the WorkType to ensure it is the same qualification as the // original From was. - auto QualifiersToApply = From.split().Quals.getAsOpaqueValue(); + auto FastQualifiersToApply = static_cast( + From.split().Quals.getAsOpaqueValue() & Qualifiers::FastMask); // LValue->RValue is irrelevant for the check, because it is a thing to be // done at a call site, and will be performed if need be performed. @@ -993,7 +994,7 @@ approximateStandardConversionSequence(const TheCheck &Check, QualType From, // "const double -> double". LLVM_DEBUG(llvm::dbgs() << "--- approximateStdConv. Conversion between numerics.\n"); - WorkType = QualType{ToBuiltin, QualifiersToApply}; + WorkType = QualType{ToBuiltin, FastQualifiersToApply}; } const auto *FromEnum = WorkType->getAs(); @@ -1002,7 +1003,7 @@ approximateStandardConversionSequence(const TheCheck &Check, QualType From, // Unscoped enumerations (or enumerations in C) convert to numerics. LLVM_DEBUG(llvm::dbgs() << "--- approximateStdConv. Unscoped enum to numeric.\n"); - WorkType = QualType{ToBuiltin, QualifiersToApply}; + WorkType = QualType{ToBuiltin, FastQualifiersToApply}; } else if (FromNumeric && ToEnum && ToEnum->isUnscopedEnumerationType()) { // Numeric types convert to enumerations only in C. if (Ctx.getLangOpts().CPlusPlus) { @@ -1013,7 +1014,7 @@ approximateStandardConversionSequence(const TheCheck &Check, QualType From, LLVM_DEBUG(llvm::dbgs() << "--- approximateStdConv. Numeric to unscoped enum.\n"); - WorkType = QualType{ToEnum, QualifiersToApply}; + WorkType = QualType{ToEnum, FastQualifiersToApply}; } // Check for pointer conversions. @@ -1022,14 +1023,14 @@ approximateStandardConversionSequence(const TheCheck &Check, QualType From, if (FromPtr && ToPtr) { if (ToPtr->isVoidPointerType()) { LLVM_DEBUG(llvm::dbgs() << "--- approximateStdConv. To void pointer.\n"); - WorkType = QualType{ToPtr, QualifiersToApply}; + WorkType = QualType{ToPtr, FastQualifiersToApply}; } const auto *FromRecordPtr = FromPtr->getPointeeCXXRecordDecl(); const auto *ToRecordPtr = ToPtr->getPointeeCXXRecordDecl(); if (isDerivedToBase(FromRecordPtr, ToRecordPtr)) { LLVM_DEBUG(llvm::dbgs() << "--- approximateStdConv. Derived* to Base*\n"); - WorkType = QualType{ToPtr, QualifiersToApply}; + WorkType = QualType{ToPtr, FastQualifiersToApply}; } } @@ -1039,7 +1040,7 @@ approximateStandardConversionSequence(const TheCheck &Check, QualType From, const auto *ToRecord = To->getAsCXXRecordDecl(); if (isDerivedToBase(FromRecord, ToRecord)) { LLVM_DEBUG(llvm::dbgs() << "--- approximateStdConv. Derived To Base.\n"); - WorkType = QualType{ToRecord->getTypeForDecl(), QualifiersToApply}; + WorkType = QualType{ToRecord->getTypeForDecl(), FastQualifiersToApply}; } if (Ctx.getLangOpts().CPlusPlus17 && FromPtr && ToPtr) { @@ -1054,7 +1055,7 @@ approximateStandardConversionSequence(const TheCheck &Check, QualType From, !ToFunctionPtr->hasNoexceptExceptionSpec()) { LLVM_DEBUG(llvm::dbgs() << "--- approximateStdConv. noexcept function " "pointer to non-noexcept.\n"); - WorkType = QualType{ToPtr, QualifiersToApply}; + WorkType = QualType{ToPtr, FastQualifiersToApply}; } } diff --git a/clang/include/clang/AST/ASTContext.h b/clang/include/clang/AST/ASTContext.h index a662d94994ec..6dbd06251dda 100644 --- a/clang/include/clang/AST/ASTContext.h +++ b/clang/include/clang/AST/ASTContext.h @@ -2197,6 +2197,16 @@ public: return getQualifiedType(type.getUnqualifiedType(), Qs); } + /// \brief Return a type with the given __ptrauth qualifier. + QualType getPointerAuthType(QualType Ty, PointerAuthQualifier PointerAuth) { + assert(!Ty.getPointerAuth()); + assert(PointerAuth); + + Qualifiers Qs; + Qs.setPointerAuth(PointerAuth); + return getQualifiedType(Ty, Qs); + } + unsigned char getFixedPointScale(QualType Ty) const; unsigned char getFixedPointIBits(QualType Ty) const; llvm::FixedPointSemantics getFixedPointSemantics(QualType Ty) const; diff --git a/clang/include/clang/AST/AbstractBasicReader.h b/clang/include/clang/AST/AbstractBasicReader.h index 1f2797cc7014..ab036f1d445a 100644 --- a/clang/include/clang/AST/AbstractBasicReader.h +++ b/clang/include/clang/AST/AbstractBasicReader.h @@ -213,9 +213,9 @@ public: } Qualifiers readQualifiers() { - static_assert(sizeof(Qualifiers().getAsOpaqueValue()) <= sizeof(uint32_t), + static_assert(sizeof(Qualifiers().getAsOpaqueValue()) <= sizeof(uint64_t), "update this if the value size changes"); - uint32_t value = asImpl().readUInt32(); + uint64_t value = asImpl().readUInt64(); return Qualifiers::fromOpaqueValue(value); } diff --git a/clang/include/clang/AST/AbstractBasicWriter.h b/clang/include/clang/AST/AbstractBasicWriter.h index 07afa388de2c..8e42fcaad1d3 100644 --- a/clang/include/clang/AST/AbstractBasicWriter.h +++ b/clang/include/clang/AST/AbstractBasicWriter.h @@ -196,9 +196,9 @@ public: } void writeQualifiers(Qualifiers value) { - static_assert(sizeof(value.getAsOpaqueValue()) <= sizeof(uint32_t), + static_assert(sizeof(value.getAsOpaqueValue()) <= sizeof(uint64_t), "update this if the value size changes"); - asImpl().writeUInt32(value.getAsOpaqueValue()); + asImpl().writeUInt64(value.getAsOpaqueValue()); } void writeExceptionSpecInfo( diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index 99f45d518c79..dff02d4861b3 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -25,8 +25,10 @@ #include "clang/Basic/Diagnostic.h" #include "clang/Basic/ExceptionSpecificationType.h" #include "clang/Basic/LLVM.h" +#include "clang/Basic/LangOptions.h" #include "clang/Basic/Linkage.h" #include "clang/Basic/PartialDiagnostic.h" +#include "clang/Basic/PointerAuthOptions.h" #include "clang/Basic/SourceLocation.h" #include "clang/Basic/Specifiers.h" #include "clang/Basic/Visibility.h" @@ -139,6 +141,174 @@ using CanQualType = CanQual; #define TYPE(Class, Base) class Class##Type; #include "clang/AST/TypeNodes.inc" +/// Pointer-authentication qualifiers. +class PointerAuthQualifier { + enum : uint32_t { + EnabledShift = 0, + EnabledBits = 1, + EnabledMask = 1 << EnabledShift, + AddressDiscriminatedShift = EnabledShift + EnabledBits, + AddressDiscriminatedBits = 1, + AddressDiscriminatedMask = 1 << AddressDiscriminatedShift, + AuthenticationModeShift = + AddressDiscriminatedShift + AddressDiscriminatedBits, + AuthenticationModeBits = 2, + AuthenticationModeMask = ((1 << AuthenticationModeBits) - 1) + << AuthenticationModeShift, + IsaPointerShift = AuthenticationModeShift + AuthenticationModeBits, + IsaPointerBits = 1, + IsaPointerMask = ((1 << IsaPointerBits) - 1) << IsaPointerShift, + AuthenticatesNullValuesShift = IsaPointerShift + IsaPointerBits, + AuthenticatesNullValuesBits = 1, + AuthenticatesNullValuesMask = ((1 << AuthenticatesNullValuesBits) - 1) + << AuthenticatesNullValuesShift, + KeyShift = AuthenticatesNullValuesShift + AuthenticatesNullValuesBits, + KeyBits = 10, + KeyMask = ((1 << KeyBits) - 1) << KeyShift, + DiscriminatorShift = KeyShift + KeyBits, + DiscriminatorBits = 16, + DiscriminatorMask = ((1u << DiscriminatorBits) - 1) << DiscriminatorShift, + }; + + // bits: |0 |1 |2..3 |4 | + // |Enabled|Address|AuthenticationMode|ISA pointer| + // bits: |5 |6..15| 16...31 | + // |AuthenticatesNull|Key |Discriminator| + uint32_t Data = 0; + + // The following static assertions check that each of the 32 bits is present + // exactly in one of the constants. + static_assert((EnabledBits + AddressDiscriminatedBits + + AuthenticationModeBits + IsaPointerBits + + AuthenticatesNullValuesBits + KeyBits + DiscriminatorBits) == + 32, + "PointerAuthQualifier should be exactly 32 bits"); + static_assert((EnabledMask + AddressDiscriminatedMask + + AuthenticationModeMask + IsaPointerMask + + AuthenticatesNullValuesMask + KeyMask + DiscriminatorMask) == + 0xFFFFFFFF, + "All masks should cover the entire bits"); + static_assert((EnabledMask ^ AddressDiscriminatedMask ^ + AuthenticationModeMask ^ IsaPointerMask ^ + AuthenticatesNullValuesMask ^ KeyMask ^ DiscriminatorMask) == + 0xFFFFFFFF, + "All masks should cover the entire bits"); + + PointerAuthQualifier(unsigned Key, bool IsAddressDiscriminated, + unsigned ExtraDiscriminator, + PointerAuthenticationMode AuthenticationMode, + bool IsIsaPointer, bool AuthenticatesNullValues) + : Data(EnabledMask | + (IsAddressDiscriminated + ? llvm::to_underlying(AddressDiscriminatedMask) + : 0) | + (Key << KeyShift) | + (llvm::to_underlying(AuthenticationMode) + << AuthenticationModeShift) | + (ExtraDiscriminator << DiscriminatorShift) | + (IsIsaPointer << IsaPointerShift) | + (AuthenticatesNullValues << AuthenticatesNullValuesShift)) { + assert(Key <= KeyNoneInternal); + assert(ExtraDiscriminator <= MaxDiscriminator); + assert((Data == 0) == + (getAuthenticationMode() == PointerAuthenticationMode::None)); + } + +public: + enum { + KeyNoneInternal = (1u << KeyBits) - 1, + + /// The maximum supported pointer-authentication key. + MaxKey = KeyNoneInternal - 1, + + /// The maximum supported pointer-authentication discriminator. + MaxDiscriminator = (1u << DiscriminatorBits) - 1 + }; + +public: + PointerAuthQualifier() = default; + + static PointerAuthQualifier + Create(unsigned Key, bool IsAddressDiscriminated, unsigned ExtraDiscriminator, + PointerAuthenticationMode AuthenticationMode, bool IsIsaPointer, + bool AuthenticatesNullValues) { + if (Key == PointerAuthKeyNone) + Key = KeyNoneInternal; + assert(Key <= KeyNoneInternal && "out-of-range key value"); + return PointerAuthQualifier(Key, IsAddressDiscriminated, ExtraDiscriminator, + AuthenticationMode, IsIsaPointer, + AuthenticatesNullValues); + } + + bool isPresent() const { + assert((Data == 0) == + (getAuthenticationMode() == PointerAuthenticationMode::None)); + return Data != 0; + } + + explicit operator bool() const { return isPresent(); } + + unsigned getKey() const { + assert(isPresent()); + return (Data & KeyMask) >> KeyShift; + } + + bool hasKeyNone() const { return isPresent() && getKey() == KeyNoneInternal; } + + bool isAddressDiscriminated() const { + assert(isPresent()); + return (Data & AddressDiscriminatedMask) >> AddressDiscriminatedShift; + } + + unsigned getExtraDiscriminator() const { + assert(isPresent()); + return (Data >> DiscriminatorShift); + } + + PointerAuthenticationMode getAuthenticationMode() const { + return PointerAuthenticationMode((Data & AuthenticationModeMask) >> + AuthenticationModeShift); + } + + bool isIsaPointer() const { + assert(isPresent()); + return (Data & IsaPointerMask) >> IsaPointerShift; + } + + bool authenticatesNullValues() const { + assert(isPresent()); + return (Data & AuthenticatesNullValuesMask) >> AuthenticatesNullValuesShift; + } + + PointerAuthQualifier withoutKeyNone() const { + return hasKeyNone() ? PointerAuthQualifier() : *this; + } + + friend bool operator==(PointerAuthQualifier Lhs, PointerAuthQualifier Rhs) { + return Lhs.Data == Rhs.Data; + } + friend bool operator!=(PointerAuthQualifier Lhs, PointerAuthQualifier Rhs) { + return Lhs.Data != Rhs.Data; + } + + bool isEquivalent(PointerAuthQualifier Other) const { + return withoutKeyNone() == Other.withoutKeyNone(); + } + + uint32_t getAsOpaqueValue() const { return Data; } + + // Deserialize pointer-auth qualifiers from an opaque representation. + static PointerAuthQualifier fromOpaqueValue(uint32_t Opaque) { + PointerAuthQualifier Result; + Result.Data = Opaque; + assert((Result.Data == 0) == + (Result.getAuthenticationMode() == PointerAuthenticationMode::None)); + return Result; + } + + void Profile(llvm::FoldingSetNodeID &ID) const { ID.AddInteger(Data); } +}; + /// The collection of all-type qualifiers we support. /// Clang supports five independent qualifiers: /// * C99: const, volatile, and restrict @@ -147,8 +317,9 @@ using CanQualType = CanQual; /// * Objective C: the GC attributes (none, weak, or strong) class Qualifiers { public: - enum TQ { // NOTE: These flags must be kept in sync with DeclSpec::TQ. - Const = 0x1, + enum TQ : uint64_t { + // NOTE: These flags must be kept in sync with DeclSpec::TQ. + Const = 0x1, Restrict = 0x2, Volatile = 0x4, CVRMask = Const | Volatile | Restrict @@ -182,7 +353,7 @@ public: OCL_Autoreleasing }; - enum { + enum : uint64_t { /// The maximum supported address space number. /// 23 bits should be enough for anyone. MaxAddressSpace = 0x7fffffu, @@ -197,16 +368,25 @@ public: /// Returns the common set of qualifiers while removing them from /// the given sets. static Qualifiers removeCommonQualifiers(Qualifiers &L, Qualifiers &R) { + Qualifiers Q; + PointerAuthQualifier LPtrAuth = L.getPointerAuth(); + if (LPtrAuth.isPresent() && + LPtrAuth.getKey() != PointerAuthQualifier::KeyNoneInternal && + LPtrAuth == R.getPointerAuth()) { + Q.setPointerAuth(LPtrAuth); + PointerAuthQualifier Empty; + L.setPointerAuth(Empty); + R.setPointerAuth(Empty); + } + // If both are only CVR-qualified, bit operations are sufficient. if (!(L.Mask & ~CVRMask) && !(R.Mask & ~CVRMask)) { - Qualifiers Q; Q.Mask = L.Mask & R.Mask; L.Mask &= ~Q.Mask; R.Mask &= ~Q.Mask; return Q; } - Qualifiers Q; unsigned CommonCRV = L.getCVRQualifiers() & R.getCVRQualifiers(); Q.addCVRQualifiers(CommonCRV); L.removeCVRQualifiers(CommonCRV); @@ -251,16 +431,14 @@ public: } // Deserialize qualifiers from an opaque representation. - static Qualifiers fromOpaqueValue(unsigned opaque) { + static Qualifiers fromOpaqueValue(uint64_t opaque) { Qualifiers Qs; Qs.Mask = opaque; return Qs; } // Serialize these qualifiers into an opaque representation. - unsigned getAsOpaqueValue() const { - return Mask; - } + uint64_t getAsOpaqueValue() const { return Mask; } bool hasConst() const { return Mask & Const; } bool hasOnlyConst() const { return Mask == Const; } @@ -407,6 +585,20 @@ public: setAddressSpace(space); } + bool hasPointerAuth() const { return Mask & PtrAuthMask; } + PointerAuthQualifier getPointerAuth() const { + return PointerAuthQualifier::fromOpaqueValue(Mask >> PtrAuthShift); + } + void setPointerAuth(PointerAuthQualifier Q) { + Mask = (Mask & ~PtrAuthMask) | + (uint64_t(Q.getAsOpaqueValue()) << PtrAuthShift); + } + void removePointerAuth() { Mask &= ~PtrAuthMask; } + void addPointerAuth(PointerAuthQualifier Q) { + assert(Q.isPresent()); + setPointerAuth(Q); + } + // Fast qualifiers are those that can be allocated directly // on a QualType object. bool hasFastQualifiers() const { return getFastQualifiers(); } @@ -454,6 +646,8 @@ public: addObjCGCAttr(Q.getObjCGCAttr()); if (Q.hasObjCLifetime()) addObjCLifetime(Q.getObjCLifetime()); + if (Q.hasPointerAuth()) + addPointerAuth(Q.getPointerAuth()); } } @@ -471,6 +665,8 @@ public: removeObjCLifetime(); if (getAddressSpace() == Q.getAddressSpace()) removeAddressSpace(); + if (getPointerAuth() == Q.getPointerAuth()) + removePointerAuth(); } } @@ -483,6 +679,8 @@ public: !hasObjCGCAttr() || !qs.hasObjCGCAttr()); assert(getObjCLifetime() == qs.getObjCLifetime() || !hasObjCLifetime() || !qs.hasObjCLifetime()); + assert(!hasPointerAuth() || !qs.hasPointerAuth() || + getPointerAuth() == qs.getPointerAuth()); Mask |= qs.Mask; } @@ -536,6 +734,8 @@ public: // be changed. (getObjCGCAttr() == other.getObjCGCAttr() || !hasObjCGCAttr() || !other.hasObjCGCAttr()) && + // Pointer-auth qualifiers must match exactly. + getPointerAuth() == other.getPointerAuth() && // ObjC lifetime qualifiers must match exactly. getObjCLifetime() == other.getObjCLifetime() && // CVR qualifiers may subset. @@ -605,24 +805,26 @@ public: void print(raw_ostream &OS, const PrintingPolicy &Policy, bool appendSpaceIfNonEmpty = false) const; - void Profile(llvm::FoldingSetNodeID &ID) const { - ID.AddInteger(Mask); - } + void Profile(llvm::FoldingSetNodeID &ID) const { ID.AddInteger(Mask); } private: - // bits: |0 1 2|3|4 .. 5|6 .. 8|9 ... 31| - // |C R V|U|GCAttr|Lifetime|AddressSpace| - uint32_t Mask = 0; - - static const uint32_t UMask = 0x8; - static const uint32_t UShift = 3; - static const uint32_t GCAttrMask = 0x30; - static const uint32_t GCAttrShift = 4; - static const uint32_t LifetimeMask = 0x1C0; - static const uint32_t LifetimeShift = 6; - static const uint32_t AddressSpaceMask = + // bits: |0 1 2|3|4 .. 5|6 .. 8|9 ... 31|32 ... 63| + // |C R V|U|GCAttr|Lifetime|AddressSpace| PtrAuth | + uint64_t Mask = 0; + static_assert(sizeof(PointerAuthQualifier) == sizeof(uint32_t), + "PointerAuthQualifier must be 32 bits"); + + static constexpr uint64_t UMask = 0x8; + static constexpr uint64_t UShift = 3; + static constexpr uint64_t GCAttrMask = 0x30; + static constexpr uint64_t GCAttrShift = 4; + static constexpr uint64_t LifetimeMask = 0x1C0; + static constexpr uint64_t LifetimeShift = 6; + static constexpr uint64_t AddressSpaceMask = ~(CVRMask | UMask | GCAttrMask | LifetimeMask); - static const uint32_t AddressSpaceShift = 9; + static constexpr uint64_t AddressSpaceShift = 9; + static constexpr uint64_t PtrAuthShift = 32; + static constexpr uint64_t PtrAuthMask = uint64_t(0xffffffff) << PtrAuthShift; }; class QualifiersAndAtomic { @@ -1242,6 +1444,10 @@ public: // true when Type is objc's weak and weak is enabled but ARC isn't. bool isNonWeakInMRRWithObjCWeak(const ASTContext &Context) const; + PointerAuthQualifier getPointerAuth() const { + return getQualifiers().getPointerAuth(); + } + enum PrimitiveDefaultInitializeKind { /// The type does not fall into any of the following categories. Note that /// this case is zero-valued so that values of this enum can be used as a diff --git a/clang/include/clang/Basic/LangOptions.h b/clang/include/clang/Basic/LangOptions.h index ae4715921d16..e2a2aa71b880 100644 --- a/clang/include/clang/Basic/LangOptions.h +++ b/clang/include/clang/Basic/LangOptions.h @@ -57,6 +57,13 @@ enum class ShaderStage { Invalid, }; +enum class PointerAuthenticationMode : unsigned { + None, + Strip, + SignAndStrip, + SignAndAuth +}; + /// Bitfields of LangOptions, split out from LangOptions in order to ensure that /// this large collection of bitfields is a trivial class type. class LangOptionsBase { diff --git a/clang/include/clang/Basic/PointerAuthOptions.h b/clang/include/clang/Basic/PointerAuthOptions.h new file mode 100644 index 000000000000..e5cdcc31ebfb --- /dev/null +++ b/clang/include/clang/Basic/PointerAuthOptions.h @@ -0,0 +1,23 @@ +//===--- PointerAuthOptions.h -----------------------------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// This file defines options for configuring pointer-auth technologies +// like ARMv8.3. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_CLANG_BASIC_POINTERAUTHOPTIONS_H +#define LLVM_CLANG_BASIC_POINTERAUTHOPTIONS_H + +namespace clang { + +constexpr unsigned PointerAuthKeyNone = -1; + +} // end namespace clang + +#endif -- GitLab From 0d288e5b0ccf217e41944ad4fd8772d8ae45daa1 Mon Sep 17 00:00:00 2001 From: Sunho Kim Date: Thu, 25 Apr 2024 22:43:06 -0700 Subject: [PATCH 011/301] [ORC] Implement basic reoptimization. (#67050) --- compiler-rt/lib/orc/common.h | 6 +- compiler-rt/lib/orc/elfnix_platform.cpp | 1 + .../BuildingAJIT/Chapter3/KaleidoscopeJIT.h | 6 +- .../SpeculativeJIT/SpeculativeJIT.cpp | 9 +- .../Orc/CompileOnDemandLayer.h | 36 +-- .../ExecutionEngine/Orc/IRPartitionLayer.h | 85 +++++ .../Orc/JITLinkRedirectableSymbolManager.h | 107 +++++++ llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h | 7 +- .../ExecutionEngine/Orc/ReOptimizeLayer.h | 179 +++++++++++ .../ExecutionEngine/Orc/RedirectionManager.h | 103 ++++++ llvm/lib/ExecutionEngine/Orc/CMakeLists.txt | 4 + .../Orc/CompileOnDemandLayer.cpp | 282 +--------------- .../ExecutionEngine/Orc/IRPartitionLayer.cpp | 303 ++++++++++++++++++ .../Orc/JITLinkRedirectableSymbolManager.cpp | 182 +++++++++++ llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 7 +- .../ExecutionEngine/Orc/ReOptimizeLayer.cpp | 278 ++++++++++++++++ .../Orc/RedirectionManager.cpp | 24 ++ llvm/tools/lli/lli.cpp | 3 +- .../ExecutionEngine/Orc/CMakeLists.txt | 2 + .../Orc/JITLinkRedirectionManagerTest.cpp | 99 ++++++ .../Orc/ReOptimizeLayerTest.cpp | 150 +++++++++ 21 files changed, 1548 insertions(+), 325 deletions(-) create mode 100644 llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h create mode 100644 llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h create mode 100644 llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h create mode 100644 llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h create mode 100644 llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp create mode 100644 llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp create mode 100644 llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp create mode 100644 llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp create mode 100644 llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp create mode 100644 llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp diff --git a/compiler-rt/lib/orc/common.h b/compiler-rt/lib/orc/common.h index 73c5c4a2bd8d..f34229a61534 100644 --- a/compiler-rt/lib/orc/common.h +++ b/compiler-rt/lib/orc/common.h @@ -19,9 +19,9 @@ /// This macro should be used to define tags that will be associated with /// handlers in the JIT process, and call can be used to define tags f -#define ORC_RT_JIT_DISPATCH_TAG(X) \ -extern "C" char X; \ -char X = 0; +#define ORC_RT_JIT_DISPATCH_TAG(X) \ + ORC_RT_INTERFACE char X; \ + char X = 0; /// Opaque struct for external symbols. struct __orc_rt_Opaque {}; diff --git a/compiler-rt/lib/orc/elfnix_platform.cpp b/compiler-rt/lib/orc/elfnix_platform.cpp index c087e71038f9..f76a07024031 100644 --- a/compiler-rt/lib/orc/elfnix_platform.cpp +++ b/compiler-rt/lib/orc/elfnix_platform.cpp @@ -28,6 +28,7 @@ using namespace __orc_rt; using namespace __orc_rt::elfnix; // Declare function tags for functions in the JIT process. +ORC_RT_JIT_DISPATCH_TAG(__orc_rt_reoptimize_tag) ORC_RT_JIT_DISPATCH_TAG(__orc_rt_elfnix_get_initializers_tag) ORC_RT_JIT_DISPATCH_TAG(__orc_rt_elfnix_get_deinitializers_tag) ORC_RT_JIT_DISPATCH_TAG(__orc_rt_elfnix_symbol_lookup_tag) diff --git a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h index fd0e081ff2b4..fee2d26e5d92 100644 --- a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h +++ b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h @@ -21,6 +21,7 @@ #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h" #include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" +#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/IRTransformLayer.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h" @@ -48,6 +49,7 @@ private: RTDyldObjectLinkingLayer ObjectLayer; IRCompileLayer CompileLayer; IRTransformLayer OptimizeLayer; + IRPartitionLayer IPLayer; CompileOnDemandLayer CODLayer; JITDylib &MainJD; @@ -68,8 +70,8 @@ public: CompileLayer(*this->ES, ObjectLayer, std::make_unique(std::move(JTMB))), OptimizeLayer(*this->ES, CompileLayer, optimizeModule), - CODLayer(*this->ES, OptimizeLayer, - this->EPCIU->getLazyCallThroughManager(), + IPLayer(*this->ES, OptimizeLayer), + CODLayer(*this->ES, IPLayer, this->EPCIU->getLazyCallThroughManager(), [this] { return this->EPCIU->createIndirectStubsManager(); }), MainJD(this->ES->createBareJITDylib("
")) { MainJD.addGenerator( diff --git a/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp b/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp index 1659e5c5c8b4..24ae953eca7a 100644 --- a/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp +++ b/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp @@ -3,6 +3,7 @@ #include "llvm/ExecutionEngine/Orc/Core.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" +#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/IndirectionUtils.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h" @@ -109,13 +110,14 @@ private: IndirectStubsManagerBuilderFunction ISMBuilder, std::unique_ptr ProcessSymbolsGenerator) : ES(std::move(ES)), DL(std::move(DL)), - MainJD(this->ES->createBareJITDylib("
")), LCTMgr(std::move(LCTMgr)), + MainJD(this->ES->createBareJITDylib("
")), + LCTMgr(std::move(LCTMgr)), CompileLayer(*this->ES, ObjLayer, std::make_unique(std::move(JTMB))), S(Imps, *this->ES), SpeculateLayer(*this->ES, CompileLayer, S, Mangle, BlockFreqQuery()), - CODLayer(*this->ES, SpeculateLayer, *this->LCTMgr, - std::move(ISMBuilder)) { + IPLayer(*this->ES, SpeculateLayer), + CODLayer(*this->ES, IPLayer, *this->LCTMgr, std::move(ISMBuilder)) { MainJD.addGenerator(std::move(ProcessSymbolsGenerator)); this->CODLayer.setImplMap(&Imps); ExitOnErr(S.addSpeculationRuntime(MainJD, Mangle)); @@ -141,6 +143,7 @@ private: Speculator S; RTDyldObjectLinkingLayer ObjLayer{*ES, createMemMgr}; IRSpeculationLayer SpeculateLayer; + IRPartitionLayer IPLayer; CompileOnDemandLayer CODLayer; }; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h b/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h index 41f2882c576e..d492dfe29fba 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h @@ -53,37 +53,15 @@ namespace llvm { namespace orc { class CompileOnDemandLayer : public IRLayer { - friend class PartitioningIRMaterializationUnit; - public: /// Builder for IndirectStubsManagers. using IndirectStubsManagerBuilder = std::function()>; - using GlobalValueSet = std::set; - - /// Partitioning function. - using PartitionFunction = - std::function(GlobalValueSet Requested)>; - - /// Off-the-shelf partitioning which compiles all requested symbols (usually - /// a single function at a time). - static std::optional - compileRequested(GlobalValueSet Requested); - - /// Off-the-shelf partitioning which compiles whole modules whenever any - /// symbol in them is requested. - static std::optional - compileWholeModule(GlobalValueSet Requested); - /// Construct a CompileOnDemandLayer. CompileOnDemandLayer(ExecutionSession &ES, IRLayer &BaseLayer, - LazyCallThroughManager &LCTMgr, - IndirectStubsManagerBuilder BuildIndirectStubsManager); - - /// Sets the partition function. - void setPartitionFunction(PartitionFunction Partition); - + LazyCallThroughManager &LCTMgr, + IndirectStubsManagerBuilder BuildIndirectStubsManager); /// Sets the ImplSymbolMap void setImplMap(ImplSymbolMap *Imp); @@ -110,22 +88,12 @@ private: PerDylibResources &getPerDylibResources(JITDylib &TargetD); - void cleanUpModule(Module &M); - - void expandPartition(GlobalValueSet &Partition); - - void emitPartition(std::unique_ptr R, - ThreadSafeModule TSM, - IRMaterializationUnit::SymbolNameToDefinitionMap Defs); - mutable std::mutex CODLayerMutex; IRLayer &BaseLayer; LazyCallThroughManager &LCTMgr; IndirectStubsManagerBuilder BuildIndirectStubsManager; PerDylibResourcesMap DylibResources; - PartitionFunction Partition = compileRequested; - SymbolLinkagePromoter PromoteSymbols; ImplSymbolMap *AliaseeImpls = nullptr; }; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h b/llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h new file mode 100644 index 000000000000..a2981fea61d3 --- /dev/null +++ b/llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h @@ -0,0 +1,85 @@ +//===- IRPartitionLayer.h - Partition IR module on lookup -------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// JIT layer for breaking up modules into smaller submodules that only contains +// looked up symbols. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_EXECUTIONENGINE_ORC_IRPARTITIONLAYER_H +#define LLVM_EXECUTIONENGINE_ORC_IRPARTITIONLAYER_H + +#include "llvm/ExecutionEngine/Orc/IndirectionUtils.h" +#include "llvm/ExecutionEngine/Orc/Layer.h" +#include "llvm/IR/Attributes.h" +#include "llvm/IR/Constant.h" +#include "llvm/IR/Constants.h" +#include "llvm/IR/DataLayout.h" +#include "llvm/IR/Function.h" +#include "llvm/IR/GlobalAlias.h" +#include "llvm/IR/GlobalValue.h" +#include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Instruction.h" +#include "llvm/IR/Mangler.h" +#include "llvm/IR/Module.h" +#include "llvm/IR/Type.h" + +namespace llvm { +namespace orc { + +/// A layer that breaks up IR modules into smaller submodules that only contains +/// looked up symbols. +class IRPartitionLayer : public IRLayer { + friend class PartitioningIRMaterializationUnit; + +public: + using GlobalValueSet = std::set; + + /// Partitioning function. + using PartitionFunction = + std::function(GlobalValueSet Requested)>; + + /// Construct a IRPartitionLayer. + IRPartitionLayer(ExecutionSession &ES, IRLayer &BaseLayer); + + /// Off-the-shelf partitioning which compiles all requested symbols (usually + /// a single function at a time). + static std::optional + compileRequested(GlobalValueSet Requested); + + /// Off-the-shelf partitioning which compiles whole modules whenever any + /// symbol in them is requested. + static std::optional + compileWholeModule(GlobalValueSet Requested); + + /// Sets the partition function. + void setPartitionFunction(PartitionFunction Partition); + + /// Emits the given module. This should not be called by clients: it will be + /// called by the JIT when a definition added via the add method is requested. + void emit(std::unique_ptr R, + ThreadSafeModule TSM) override; + +private: + void cleanUpModule(Module &M); + + void expandPartition(GlobalValueSet &Partition); + + void emitPartition(std::unique_ptr R, + ThreadSafeModule TSM, + IRMaterializationUnit::SymbolNameToDefinitionMap Defs); + + IRLayer &BaseLayer; + PartitionFunction Partition = compileRequested; + SymbolLinkagePromoter PromoteSymbols; +}; + +} // namespace orc +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h b/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h new file mode 100644 index 000000000000..52f284c89bda --- /dev/null +++ b/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h @@ -0,0 +1,107 @@ +//===- JITLinkRedirectableSymbolManager.h - JITLink redirection -*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Redirectable Symbol Manager implementation using JITLink +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLEMANAGER_H +#define LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLEMANAGER_H + +#include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" +#include "llvm/ExecutionEngine/Orc/RedirectionManager.h" +#include "llvm/Support/StringSaver.h" + +namespace llvm { +namespace orc { + +class JITLinkRedirectableSymbolManager : public RedirectableSymbolManager, + public ResourceManager { +public: + /// Create redirection manager that uses JITLink based implementaion. + static Expected> + Create(ObjectLinkingLayer &ObjLinkingLayer, JITDylib &JD) { + Error Err = Error::success(); + auto RM = std::unique_ptr( + new JITLinkRedirectableSymbolManager(ObjLinkingLayer, JD, Err)); + if (Err) + return Err; + return std::move(RM); + } + + void emitRedirectableSymbols(std::unique_ptr R, + const SymbolAddrMap &InitialDests) override; + + Error redirect(JITDylib &TargetJD, const SymbolAddrMap &NewDests) override; + + Error handleRemoveResources(JITDylib &TargetJD, ResourceKey K) override; + + void handleTransferResources(JITDylib &TargetJD, ResourceKey DstK, + ResourceKey SrcK) override; + +private: + using StubHandle = unsigned; + constexpr static unsigned StubBlockSize = 256; + constexpr static StringRef JumpStubPrefix = "$__IND_JUMP_STUBS"; + constexpr static StringRef StubPtrPrefix = "$IND_JUMP_PTR_"; + constexpr static StringRef JumpStubTableName = "$IND_JUMP_"; + constexpr static StringRef StubPtrTableName = "$__IND_JUMP_PTRS"; + + JITLinkRedirectableSymbolManager(ObjectLinkingLayer &ObjLinkingLayer, + JITDylib &JD, Error &Err) + : ObjLinkingLayer(ObjLinkingLayer), JD(JD), + AnonymousPtrCreator(jitlink::getAnonymousPointerCreator( + ObjLinkingLayer.getExecutionSession().getTargetTriple())), + PtrJumpStubCreator(jitlink::getPointerJumpStubCreator( + ObjLinkingLayer.getExecutionSession().getTargetTriple())) { + if (!AnonymousPtrCreator || !PtrJumpStubCreator) + Err = make_error("Architecture not supported", + inconvertibleErrorCode()); + if (Err) + return; + ObjLinkingLayer.getExecutionSession().registerResourceManager(*this); + } + + ~JITLinkRedirectableSymbolManager() { + ObjLinkingLayer.getExecutionSession().deregisterResourceManager(*this); + } + + StringRef JumpStubSymbolName(unsigned I) { + return *ObjLinkingLayer.getExecutionSession().intern( + (JumpStubPrefix + Twine(I)).str()); + } + + StringRef StubPtrSymbolName(unsigned I) { + return *ObjLinkingLayer.getExecutionSession().intern( + (StubPtrPrefix + Twine(I)).str()); + } + + unsigned GetNumAvailableStubs() const { return AvailableStubs.size(); } + + Error redirectInner(JITDylib &TargetJD, const SymbolAddrMap &NewDests); + Error grow(unsigned Need); + + ObjectLinkingLayer &ObjLinkingLayer; + JITDylib &JD; + jitlink::AnonymousPointerCreator AnonymousPtrCreator; + jitlink::PointerJumpStubCreator PtrJumpStubCreator; + + std::vector AvailableStubs; + using SymbolToStubMap = DenseMap; + DenseMap SymbolToStubs; + std::vector JumpStubs; + std::vector StubPointers; + DenseMap> TrackedResources; + + std::mutex Mutex; +}; + +} // namespace orc +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h index 3a71ddc88ce9..7d1a5bc9e30d 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h @@ -17,6 +17,7 @@ #include "llvm/ExecutionEngine/Orc/CompileUtils.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" +#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/IRTransformLayer.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/ThreadSafeModule.h" @@ -270,9 +271,8 @@ class LLLazyJIT : public LLJIT { public: /// Sets the partition function. - void - setPartitionFunction(CompileOnDemandLayer::PartitionFunction Partition) { - CODLayer->setPartitionFunction(std::move(Partition)); + void setPartitionFunction(IRPartitionLayer::PartitionFunction Partition) { + IPLayer->setPartitionFunction(std::move(Partition)); } /// Returns a reference to the on-demand layer. @@ -292,6 +292,7 @@ private: LLLazyJIT(LLLazyJITBuilderState &S, Error &Err); std::unique_ptr LCTMgr; + std::unique_ptr IPLayer; std::unique_ptr CODLayer; }; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h b/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h new file mode 100644 index 000000000000..fc27a6b8cb08 --- /dev/null +++ b/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h @@ -0,0 +1,179 @@ +//===- ReOptimizeLayer.h - Re-optimization layer interface ------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Re-optimization layer interface. +// +//===----------------------------------------------------------------------===// +#ifndef LLVM_EXECUTIONENGINE_ORC_REOPTIMIZELAYER_H +#define LLVM_EXECUTIONENGINE_ORC_REOPTIMIZELAYER_H + +#include "llvm/ExecutionEngine/Orc/Core.h" +#include "llvm/ExecutionEngine/Orc/Layer.h" +#include "llvm/ExecutionEngine/Orc/RedirectionManager.h" +#include "llvm/ExecutionEngine/Orc/ThreadSafeModule.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/Transforms/Utils/BasicBlockUtils.h" +#include "llvm/Transforms/Utils/Cloning.h" + +namespace llvm { +namespace orc { + +class ReOptimizeLayer : public IRLayer, public ResourceManager { +public: + using ReOptMaterializationUnitID = uint64_t; + + /// AddProfilerFunc will be called when ReOptimizeLayer emits the first + /// version of a materialization unit in order to inject profiling code and + /// reoptimization request code. + using AddProfilerFunc = unique_function; + + /// ReOptimizeFunc will be called when ReOptimizeLayer reoptimization of a + /// materialization unit was requested in order to reoptimize the IR module + /// based on profile data. OldRT is the ResourceTracker that tracks the old + /// function definitions. The OldRT must be kept alive until it can be + /// guaranteed that every invocation of the old function definitions has been + /// terminated. + using ReOptimizeFunc = unique_function; + + ReOptimizeLayer(ExecutionSession &ES, IRLayer &BaseLayer, + RedirectableSymbolManager &RM) + : IRLayer(ES, BaseLayer.getManglingOptions()), ES(ES), + BaseLayer(BaseLayer), RSManager(RM), ReOptFunc(identity), + ProfilerFunc(reoptimizeIfCallFrequent) {} + + void setReoptimizeFunc(ReOptimizeFunc ReOptFunc) { + this->ReOptFunc = std::move(ReOptFunc); + } + + void setAddProfilerFunc(AddProfilerFunc ProfilerFunc) { + this->ProfilerFunc = std::move(ProfilerFunc); + } + + /// Registers reoptimize runtime dispatch handlers to given PlatformJD. The + /// reoptimization request will not be handled if dispatch handler is not + /// registered by using this function. + Error reigsterRuntimeFunctions(JITDylib &PlatformJD); + + /// Emits the given module. This should not be called by clients: it will be + /// called by the JIT when a definition added via the add method is requested. + void emit(std::unique_ptr R, + ThreadSafeModule TSM) override; + + static const uint64_t CallCountThreshold = 10; + + /// Basic AddProfilerFunc that reoptimizes the function when the call count + /// exceeds CallCountThreshold. + static Error reoptimizeIfCallFrequent(ReOptimizeLayer &Parent, + ReOptMaterializationUnitID MUID, + unsigned CurVersion, + ThreadSafeModule &TSM); + + static Error identity(ReOptimizeLayer &Parent, + ReOptMaterializationUnitID MUID, unsigned CurVersion, + ResourceTrackerSP OldRT, ThreadSafeModule &TSM) { + return Error::success(); + } + + // Create IR reoptimize request fucntion call. + static void createReoptimizeCall(Module &M, Instruction &IP, + GlobalVariable *ArgBuffer); + + Error handleRemoveResources(JITDylib &JD, ResourceKey K) override; + void handleTransferResources(JITDylib &JD, ResourceKey DstK, + ResourceKey SrcK) override; + +private: + class ReOptMaterializationUnitState { + public: + ReOptMaterializationUnitState() = default; + ReOptMaterializationUnitState(ReOptMaterializationUnitID ID, + ThreadSafeModule TSM) + : ID(ID), TSM(std::move(TSM)) {} + ReOptMaterializationUnitState(ReOptMaterializationUnitState &&Other) + : ID(Other.ID), TSM(std::move(Other.TSM)), RT(std::move(Other.RT)), + Reoptimizing(std::move(Other.Reoptimizing)), + CurVersion(Other.CurVersion) {} + + ReOptMaterializationUnitID getID() { return ID; } + + const ThreadSafeModule &getThreadSafeModule() { return TSM; } + + ResourceTrackerSP getResourceTracker() { + std::unique_lock Lock(Mutex); + return RT; + } + + void setResourceTracker(ResourceTrackerSP RT) { + std::unique_lock Lock(Mutex); + this->RT = RT; + } + + uint32_t getCurVersion() { + std::unique_lock Lock(Mutex); + return CurVersion; + } + + bool tryStartReoptimize(); + void reoptimizeSucceeded(); + void reoptimizeFailed(); + + private: + std::mutex Mutex; + ReOptMaterializationUnitID ID; + ThreadSafeModule TSM; + ResourceTrackerSP RT; + bool Reoptimizing = false; + uint32_t CurVersion = 0; + }; + + using SPSReoptimizeArgList = + shared::SPSArgList; + using SendErrorFn = unique_function; + + Expected emitMUImplSymbols(ReOptMaterializationUnitState &MUState, + uint32_t Version, JITDylib &JD, + ThreadSafeModule TSM); + + void rt_reoptimize(SendErrorFn SendResult, ReOptMaterializationUnitID MUID, + uint32_t CurVersion); + + static Expected + createReoptimizeArgBuffer(Module &M, ReOptMaterializationUnitID MUID, + uint32_t CurVersion); + + ReOptMaterializationUnitState & + createMaterializationUnitState(const ThreadSafeModule &TSM); + + void + registerMaterializationUnitResource(ResourceKey Key, + ReOptMaterializationUnitState &State); + + ReOptMaterializationUnitState & + getMaterializationUnitState(ReOptMaterializationUnitID MUID); + + ExecutionSession &ES; + IRLayer &BaseLayer; + RedirectableSymbolManager &RSManager; + + ReOptimizeFunc ReOptFunc; + AddProfilerFunc ProfilerFunc; + + std::mutex Mutex; + std::map MUStates; + DenseMap> MUResources; + ReOptMaterializationUnitID NextID = 1; +}; + +} // namespace orc +} // namespace llvm + +#endif diff --git a/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h b/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h new file mode 100644 index 000000000000..4004c42d9146 --- /dev/null +++ b/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h @@ -0,0 +1,103 @@ +//===- RedirectionManager.h - Redirection manager interface -----*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Redirection manager interface that redirects a call to symbol to another. +// +//===----------------------------------------------------------------------===// + +#ifndef LLVM_EXECUTIONENGINE_ORC_REDIRECTIONMANAGER_H +#define LLVM_EXECUTIONENGINE_ORC_REDIRECTIONMANAGER_H + +#include "llvm/ExecutionEngine/Orc/Core.h" + +namespace llvm { +namespace orc { + +/// Base class for performing redirection of call to symbol to another symbol in +/// runtime. +class RedirectionManager { +public: + /// Symbol name to symbol definition map. + using SymbolAddrMap = DenseMap; + + virtual ~RedirectionManager() = default; + /// Change the redirection destination of given symbols to new destination + /// symbols. + virtual Error redirect(JITDylib &JD, const SymbolAddrMap &NewDests) = 0; + + /// Change the redirection destination of given symbol to new destination + /// symbol. + virtual Error redirect(JITDylib &JD, SymbolStringPtr Symbol, + ExecutorSymbolDef NewDest) { + return redirect(JD, {{Symbol, NewDest}}); + } + +private: + virtual void anchor(); +}; + +/// Base class for managing redirectable symbols in which a call +/// gets redirected to another symbol in runtime. +class RedirectableSymbolManager : public RedirectionManager { +public: + /// Create redirectable symbols with given symbol names and initial + /// desitnation symbol addresses. + Error createRedirectableSymbols(ResourceTrackerSP RT, + const SymbolMap &InitialDests); + + /// Create a single redirectable symbol with given symbol name and initial + /// desitnation symbol address. + Error createRedirectableSymbol(ResourceTrackerSP RT, SymbolStringPtr Symbol, + ExecutorSymbolDef InitialDest) { + return createRedirectableSymbols(RT, {{Symbol, InitialDest}}); + } + + /// Emit redirectable symbol + virtual void + emitRedirectableSymbols(std::unique_ptr MR, + const SymbolMap &InitialDests) = 0; +}; + +/// RedirectableMaterializationUnit materializes redirectable symbol +/// by invoking RedirectableSymbolManager::emitRedirectableSymbols +class RedirectableMaterializationUnit : public MaterializationUnit { +public: + RedirectableMaterializationUnit(RedirectableSymbolManager &RM, + const SymbolMap &InitialDests) + : MaterializationUnit(convertToFlags(InitialDests)), RM(RM), + InitialDests(InitialDests) {} + + StringRef getName() const override { + return "RedirectableSymbolMaterializationUnit"; + } + + void materialize(std::unique_ptr R) override { + RM.emitRedirectableSymbols(std::move(R), std::move(InitialDests)); + } + + void discard(const JITDylib &JD, const SymbolStringPtr &Name) override { + InitialDests.erase(Name); + } + +private: + static MaterializationUnit::Interface + convertToFlags(const SymbolMap &InitialDests) { + SymbolFlagsMap Flags; + for (auto [K, V] : InitialDests) + Flags[K] = V.getFlags(); + return MaterializationUnit::Interface(Flags, {}); + } + + RedirectableSymbolManager &RM; + SymbolMap InitialDests; +}; + +} // namespace orc +} // namespace llvm + +#endif diff --git a/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt b/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt index f36605bbf03b..7ed511969d96 100644 --- a/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt +++ b/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt @@ -26,6 +26,7 @@ add_llvm_component_library(LLVMOrcJIT IndirectionUtils.cpp IRCompileLayer.cpp IRTransformLayer.cpp + IRPartitionLayer.cpp JITTargetMachineBuilder.cpp LazyReexports.cpp Layer.cpp @@ -48,6 +49,9 @@ add_llvm_component_library(LLVMOrcJIT ExecutorProcessControl.cpp TaskDispatch.cpp ThreadSafeModule.cpp + RedirectionManager.cpp + JITLinkRedirectableSymbolManager.cpp + ReOptimizeLayer.cpp ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/ExecutionEngine/Orc diff --git a/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp b/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp index 6448adaa0ceb..9296bc2b389a 100644 --- a/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp @@ -9,6 +9,7 @@ #include "llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h" #include "llvm/ADT/Hashing.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" +#include "llvm/ExecutionEngine/Orc/Layer.h" #include "llvm/IR/Mangler.h" #include "llvm/IR/Module.h" #include "llvm/Support/FormatVariadic.h" @@ -17,101 +18,6 @@ using namespace llvm; using namespace llvm::orc; -static ThreadSafeModule extractSubModule(ThreadSafeModule &TSM, - StringRef Suffix, - GVPredicate ShouldExtract) { - - auto DeleteExtractedDefs = [](GlobalValue &GV) { - // Bump the linkage: this global will be provided by the external module. - GV.setLinkage(GlobalValue::ExternalLinkage); - - // Delete the definition in the source module. - if (isa(GV)) { - auto &F = cast(GV); - F.deleteBody(); - F.setPersonalityFn(nullptr); - } else if (isa(GV)) { - cast(GV).setInitializer(nullptr); - } else if (isa(GV)) { - // We need to turn deleted aliases into function or variable decls based - // on the type of their aliasee. - auto &A = cast(GV); - Constant *Aliasee = A.getAliasee(); - assert(A.hasName() && "Anonymous alias?"); - assert(Aliasee->hasName() && "Anonymous aliasee"); - std::string AliasName = std::string(A.getName()); - - if (isa(Aliasee)) { - auto *F = cloneFunctionDecl(*A.getParent(), *cast(Aliasee)); - A.replaceAllUsesWith(F); - A.eraseFromParent(); - F->setName(AliasName); - } else if (isa(Aliasee)) { - auto *G = cloneGlobalVariableDecl(*A.getParent(), - *cast(Aliasee)); - A.replaceAllUsesWith(G); - A.eraseFromParent(); - G->setName(AliasName); - } else - llvm_unreachable("Alias to unsupported type"); - } else - llvm_unreachable("Unsupported global type"); - }; - - auto NewTSM = cloneToNewContext(TSM, ShouldExtract, DeleteExtractedDefs); - NewTSM.withModuleDo([&](Module &M) { - M.setModuleIdentifier((M.getModuleIdentifier() + Suffix).str()); - }); - - return NewTSM; -} - -namespace llvm { -namespace orc { - -class PartitioningIRMaterializationUnit : public IRMaterializationUnit { -public: - PartitioningIRMaterializationUnit(ExecutionSession &ES, - const IRSymbolMapper::ManglingOptions &MO, - ThreadSafeModule TSM, - CompileOnDemandLayer &Parent) - : IRMaterializationUnit(ES, MO, std::move(TSM)), Parent(Parent) {} - - PartitioningIRMaterializationUnit( - ThreadSafeModule TSM, Interface I, - SymbolNameToDefinitionMap SymbolToDefinition, - CompileOnDemandLayer &Parent) - : IRMaterializationUnit(std::move(TSM), std::move(I), - std::move(SymbolToDefinition)), - Parent(Parent) {} - -private: - void materialize(std::unique_ptr R) override { - Parent.emitPartition(std::move(R), std::move(TSM), - std::move(SymbolToDefinition)); - } - - void discard(const JITDylib &V, const SymbolStringPtr &Name) override { - // All original symbols were materialized by the CODLayer and should be - // final. The function bodies provided by M should never be overridden. - llvm_unreachable("Discard should never be called on an " - "ExtractingIRMaterializationUnit"); - } - - mutable std::mutex SourceModuleMutex; - CompileOnDemandLayer &Parent; -}; - -std::optional -CompileOnDemandLayer::compileRequested(GlobalValueSet Requested) { - return std::move(Requested); -} - -std::optional -CompileOnDemandLayer::compileWholeModule(GlobalValueSet Requested) { - return std::nullopt; -} - CompileOnDemandLayer::CompileOnDemandLayer( ExecutionSession &ES, IRLayer &BaseLayer, LazyCallThroughManager &LCTMgr, IndirectStubsManagerBuilder BuildIndirectStubsManager) @@ -119,13 +25,10 @@ CompileOnDemandLayer::CompileOnDemandLayer( LCTMgr(LCTMgr), BuildIndirectStubsManager(std::move(BuildIndirectStubsManager)) {} -void CompileOnDemandLayer::setPartitionFunction(PartitionFunction Partition) { - this->Partition = std::move(Partition); -} - void CompileOnDemandLayer::setImplMap(ImplSymbolMap *Imp) { this->AliaseeImpls = Imp; } + void CompileOnDemandLayer::emit( std::unique_ptr R, ThreadSafeModule TSM) { assert(TSM && "Null module"); @@ -138,10 +41,6 @@ void CompileOnDemandLayer::emit( SymbolAliasMap NonCallables; SymbolAliasMap Callables; - TSM.withModuleDo([&](Module &M) { - // First, do some cleanup on the module: - cleanUpModule(M); - }); for (auto &KV : R->getSymbols()) { auto &Name = KV.first; @@ -152,11 +51,10 @@ void CompileOnDemandLayer::emit( NonCallables[Name] = SymbolAliasMapEntry(Name, Flags); } - // Create a partitioning materialization unit and lodge it with the - // implementation dylib. + // Lodge symbols with the implementation dylib. if (auto Err = PDR.getImplDylib().define( - std::make_unique( - ES, *getManglingOptions(), std::move(TSM), *this))) { + std::make_unique( + BaseLayer, *getManglingOptions(), std::move(TSM)))) { ES.reportError(std::move(Err)); R->failMaterialization(); return; @@ -210,173 +108,3 @@ CompileOnDemandLayer::getPerDylibResources(JITDylib &TargetD) { return I->second; } - -void CompileOnDemandLayer::cleanUpModule(Module &M) { - for (auto &F : M.functions()) { - if (F.isDeclaration()) - continue; - - if (F.hasAvailableExternallyLinkage()) { - F.deleteBody(); - F.setPersonalityFn(nullptr); - continue; - } - } -} - -void CompileOnDemandLayer::expandPartition(GlobalValueSet &Partition) { - // Expands the partition to ensure the following rules hold: - // (1) If any alias is in the partition, its aliasee is also in the partition. - // (2) If any aliasee is in the partition, its aliases are also in the - // partiton. - // (3) If any global variable is in the partition then all global variables - // are in the partition. - assert(!Partition.empty() && "Unexpected empty partition"); - - const Module &M = *(*Partition.begin())->getParent(); - bool ContainsGlobalVariables = false; - std::vector GVsToAdd; - - for (const auto *GV : Partition) - if (isa(GV)) - GVsToAdd.push_back( - cast(cast(GV)->getAliasee())); - else if (isa(GV)) - ContainsGlobalVariables = true; - - for (auto &A : M.aliases()) - if (Partition.count(cast(A.getAliasee()))) - GVsToAdd.push_back(&A); - - if (ContainsGlobalVariables) - for (auto &G : M.globals()) - GVsToAdd.push_back(&G); - - for (const auto *GV : GVsToAdd) - Partition.insert(GV); -} - -void CompileOnDemandLayer::emitPartition( - std::unique_ptr R, ThreadSafeModule TSM, - IRMaterializationUnit::SymbolNameToDefinitionMap Defs) { - - // FIXME: Need a 'notify lazy-extracting/emitting' callback to tie the - // extracted module key, extracted module, and source module key - // together. This could be used, for example, to provide a specific - // memory manager instance to the linking layer. - - auto &ES = getExecutionSession(); - GlobalValueSet RequestedGVs; - for (auto &Name : R->getRequestedSymbols()) { - if (Name == R->getInitializerSymbol()) - TSM.withModuleDo([&](Module &M) { - for (auto &GV : getStaticInitGVs(M)) - RequestedGVs.insert(&GV); - }); - else { - assert(Defs.count(Name) && "No definition for symbol"); - RequestedGVs.insert(Defs[Name]); - } - } - - /// Perform partitioning with the context lock held, since the partition - /// function is allowed to access the globals to compute the partition. - auto GVsToExtract = - TSM.withModuleDo([&](Module &M) { return Partition(RequestedGVs); }); - - // Take a 'None' partition to mean the whole module (as opposed to an empty - // partition, which means "materialize nothing"). Emit the whole module - // unmodified to the base layer. - if (GVsToExtract == std::nullopt) { - Defs.clear(); - BaseLayer.emit(std::move(R), std::move(TSM)); - return; - } - - // If the partition is empty, return the whole module to the symbol table. - if (GVsToExtract->empty()) { - if (auto Err = - R->replace(std::make_unique( - std::move(TSM), - MaterializationUnit::Interface(R->getSymbols(), - R->getInitializerSymbol()), - std::move(Defs), *this))) { - getExecutionSession().reportError(std::move(Err)); - R->failMaterialization(); - return; - } - return; - } - - // Ok -- we actually need to partition the symbols. Promote the symbol - // linkages/names, expand the partition to include any required symbols - // (i.e. symbols that can't be separated from our partition), and - // then extract the partition. - // - // FIXME: We apply this promotion once per partitioning. It's safe, but - // overkill. - auto ExtractedTSM = - TSM.withModuleDo([&](Module &M) -> Expected { - auto PromotedGlobals = PromoteSymbols(M); - if (!PromotedGlobals.empty()) { - - MangleAndInterner Mangle(ES, M.getDataLayout()); - SymbolFlagsMap SymbolFlags; - IRSymbolMapper::add(ES, *getManglingOptions(), - PromotedGlobals, SymbolFlags); - - if (auto Err = R->defineMaterializing(SymbolFlags)) - return std::move(Err); - } - - expandPartition(*GVsToExtract); - - // Submodule name is given by hashing the names of the globals. - std::string SubModuleName; - { - std::vector HashGVs; - HashGVs.reserve(GVsToExtract->size()); - for (const auto *GV : *GVsToExtract) - HashGVs.push_back(GV); - llvm::sort(HashGVs, [](const GlobalValue *LHS, const GlobalValue *RHS) { - return LHS->getName() < RHS->getName(); - }); - hash_code HC(0); - for (const auto *GV : HashGVs) { - assert(GV->hasName() && "All GVs to extract should be named by now"); - auto GVName = GV->getName(); - HC = hash_combine(HC, hash_combine_range(GVName.begin(), GVName.end())); - } - raw_string_ostream(SubModuleName) - << ".submodule." - << formatv(sizeof(size_t) == 8 ? "{0:x16}" : "{0:x8}", - static_cast(HC)) - << ".ll"; - } - - // Extract the requested partiton (plus any necessary aliases) and - // put the rest back into the impl dylib. - auto ShouldExtract = [&](const GlobalValue &GV) -> bool { - return GVsToExtract->count(&GV); - }; - - return extractSubModule(TSM, SubModuleName , ShouldExtract); - }); - - if (!ExtractedTSM) { - ES.reportError(ExtractedTSM.takeError()); - R->failMaterialization(); - return; - } - - if (auto Err = R->replace(std::make_unique( - ES, *getManglingOptions(), std::move(TSM), *this))) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } - BaseLayer.emit(std::move(R), std::move(*ExtractedTSM)); -} - -} // end namespace orc -} // end namespace llvm diff --git a/llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp b/llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp new file mode 100644 index 000000000000..9ad171beac7f --- /dev/null +++ b/llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp @@ -0,0 +1,303 @@ +//===----- IRPartitionLayer.cpp - Partition IR module into submodules -----===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" +#include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" +#include "llvm/ExecutionEngine/Orc/IndirectionUtils.h" + +using namespace llvm; +using namespace llvm::orc; + +static ThreadSafeModule extractSubModule(ThreadSafeModule &TSM, + StringRef Suffix, + GVPredicate ShouldExtract) { + + auto DeleteExtractedDefs = [](GlobalValue &GV) { + // Bump the linkage: this global will be provided by the external module. + GV.setLinkage(GlobalValue::ExternalLinkage); + + // Delete the definition in the source module. + if (isa(GV)) { + auto &F = cast(GV); + F.deleteBody(); + F.setPersonalityFn(nullptr); + } else if (isa(GV)) { + cast(GV).setInitializer(nullptr); + } else if (isa(GV)) { + // We need to turn deleted aliases into function or variable decls based + // on the type of their aliasee. + auto &A = cast(GV); + Constant *Aliasee = A.getAliasee(); + assert(A.hasName() && "Anonymous alias?"); + assert(Aliasee->hasName() && "Anonymous aliasee"); + std::string AliasName = std::string(A.getName()); + + if (isa(Aliasee)) { + auto *F = cloneFunctionDecl(*A.getParent(), *cast(Aliasee)); + A.replaceAllUsesWith(F); + A.eraseFromParent(); + F->setName(AliasName); + } else if (isa(Aliasee)) { + auto *G = cloneGlobalVariableDecl(*A.getParent(), + *cast(Aliasee)); + A.replaceAllUsesWith(G); + A.eraseFromParent(); + G->setName(AliasName); + } else + llvm_unreachable("Alias to unsupported type"); + } else + llvm_unreachable("Unsupported global type"); + }; + + auto NewTSM = cloneToNewContext(TSM, ShouldExtract, DeleteExtractedDefs); + NewTSM.withModuleDo([&](Module &M) { + M.setModuleIdentifier((M.getModuleIdentifier() + Suffix).str()); + }); + + return NewTSM; +} + +namespace llvm { +namespace orc { + +class PartitioningIRMaterializationUnit : public IRMaterializationUnit { +public: + PartitioningIRMaterializationUnit(ExecutionSession &ES, + const IRSymbolMapper::ManglingOptions &MO, + ThreadSafeModule TSM, + IRPartitionLayer &Parent) + : IRMaterializationUnit(ES, MO, std::move(TSM)), Parent(Parent) {} + + PartitioningIRMaterializationUnit( + ThreadSafeModule TSM, Interface I, + SymbolNameToDefinitionMap SymbolToDefinition, IRPartitionLayer &Parent) + : IRMaterializationUnit(std::move(TSM), std::move(I), + std::move(SymbolToDefinition)), + Parent(Parent) {} + +private: + void materialize(std::unique_ptr R) override { + Parent.emitPartition(std::move(R), std::move(TSM), + std::move(SymbolToDefinition)); + } + + void discard(const JITDylib &V, const SymbolStringPtr &Name) override { + // All original symbols were materialized by the CODLayer and should be + // final. The function bodies provided by M should never be overridden. + llvm_unreachable("Discard should never be called on an " + "ExtractingIRMaterializationUnit"); + } + + IRPartitionLayer &Parent; +}; + +} // namespace orc +} // namespace llvm + +IRPartitionLayer::IRPartitionLayer(ExecutionSession &ES, IRLayer &BaseLayer) + : IRLayer(ES, BaseLayer.getManglingOptions()), BaseLayer(BaseLayer) {} + +void IRPartitionLayer::setPartitionFunction(PartitionFunction Partition) { + this->Partition = Partition; +} + +std::optional +IRPartitionLayer::compileRequested(GlobalValueSet Requested) { + return std::move(Requested); +} + +std::optional +IRPartitionLayer::compileWholeModule(GlobalValueSet Requested) { + return std::nullopt; +} + +void IRPartitionLayer::emit(std::unique_ptr R, + ThreadSafeModule TSM) { + assert(TSM && "Null module"); + + auto &ES = getExecutionSession(); + TSM.withModuleDo([&](Module &M) { + // First, do some cleanup on the module: + cleanUpModule(M); + }); + + // Create a partitioning materialization unit and pass the responsibility. + if (auto Err = R->replace(std::make_unique( + ES, *getManglingOptions(), std::move(TSM), *this))) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } +} + +void IRPartitionLayer::cleanUpModule(Module &M) { + for (auto &F : M.functions()) { + if (F.isDeclaration()) + continue; + + if (F.hasAvailableExternallyLinkage()) { + F.deleteBody(); + F.setPersonalityFn(nullptr); + continue; + } + } +} + +void IRPartitionLayer::expandPartition(GlobalValueSet &Partition) { + // Expands the partition to ensure the following rules hold: + // (1) If any alias is in the partition, its aliasee is also in the partition. + // (2) If any aliasee is in the partition, its aliases are also in the + // partiton. + // (3) If any global variable is in the partition then all global variables + // are in the partition. + assert(!Partition.empty() && "Unexpected empty partition"); + + const Module &M = *(*Partition.begin())->getParent(); + bool ContainsGlobalVariables = false; + std::vector GVsToAdd; + + for (const auto *GV : Partition) + if (isa(GV)) + GVsToAdd.push_back( + cast(cast(GV)->getAliasee())); + else if (isa(GV)) + ContainsGlobalVariables = true; + + for (auto &A : M.aliases()) + if (Partition.count(cast(A.getAliasee()))) + GVsToAdd.push_back(&A); + + if (ContainsGlobalVariables) + for (auto &G : M.globals()) + GVsToAdd.push_back(&G); + + for (const auto *GV : GVsToAdd) + Partition.insert(GV); +} + +void IRPartitionLayer::emitPartition( + std::unique_ptr R, ThreadSafeModule TSM, + IRMaterializationUnit::SymbolNameToDefinitionMap Defs) { + + // FIXME: Need a 'notify lazy-extracting/emitting' callback to tie the + // extracted module key, extracted module, and source module key + // together. This could be used, for example, to provide a specific + // memory manager instance to the linking layer. + + auto &ES = getExecutionSession(); + GlobalValueSet RequestedGVs; + for (auto &Name : R->getRequestedSymbols()) { + if (Name == R->getInitializerSymbol()) + TSM.withModuleDo([&](Module &M) { + for (auto &GV : getStaticInitGVs(M)) + RequestedGVs.insert(&GV); + }); + else { + assert(Defs.count(Name) && "No definition for symbol"); + RequestedGVs.insert(Defs[Name]); + } + } + + /// Perform partitioning with the context lock held, since the partition + /// function is allowed to access the globals to compute the partition. + auto GVsToExtract = + TSM.withModuleDo([&](Module &M) { return Partition(RequestedGVs); }); + + // Take a 'None' partition to mean the whole module (as opposed to an empty + // partition, which means "materialize nothing"). Emit the whole module + // unmodified to the base layer. + if (GVsToExtract == std::nullopt) { + Defs.clear(); + BaseLayer.emit(std::move(R), std::move(TSM)); + return; + } + + // If the partition is empty, return the whole module to the symbol table. + if (GVsToExtract->empty()) { + if (auto Err = + R->replace(std::make_unique( + std::move(TSM), + MaterializationUnit::Interface(R->getSymbols(), + R->getInitializerSymbol()), + std::move(Defs), *this))) { + getExecutionSession().reportError(std::move(Err)); + R->failMaterialization(); + return; + } + return; + } + + // Ok -- we actually need to partition the symbols. Promote the symbol + // linkages/names, expand the partition to include any required symbols + // (i.e. symbols that can't be separated from our partition), and + // then extract the partition. + // + // FIXME: We apply this promotion once per partitioning. It's safe, but + // overkill. + auto ExtractedTSM = TSM.withModuleDo([&](Module &M) + -> Expected { + auto PromotedGlobals = PromoteSymbols(M); + if (!PromotedGlobals.empty()) { + + MangleAndInterner Mangle(ES, M.getDataLayout()); + SymbolFlagsMap SymbolFlags; + IRSymbolMapper::add(ES, *getManglingOptions(), PromotedGlobals, + SymbolFlags); + + if (auto Err = R->defineMaterializing(SymbolFlags)) + return std::move(Err); + } + + expandPartition(*GVsToExtract); + + // Submodule name is given by hashing the names of the globals. + std::string SubModuleName; + { + std::vector HashGVs; + HashGVs.reserve(GVsToExtract->size()); + for (const auto *GV : *GVsToExtract) + HashGVs.push_back(GV); + llvm::sort(HashGVs, [](const GlobalValue *LHS, const GlobalValue *RHS) { + return LHS->getName() < RHS->getName(); + }); + hash_code HC(0); + for (const auto *GV : HashGVs) { + assert(GV->hasName() && "All GVs to extract should be named by now"); + auto GVName = GV->getName(); + HC = hash_combine(HC, hash_combine_range(GVName.begin(), GVName.end())); + } + raw_string_ostream(SubModuleName) + << ".submodule." + << formatv(sizeof(size_t) == 8 ? "{0:x16}" : "{0:x8}", + static_cast(HC)) + << ".ll"; + } + + // Extract the requested partiton (plus any necessary aliases) and + // put the rest back into the impl dylib. + auto ShouldExtract = [&](const GlobalValue &GV) -> bool { + return GVsToExtract->count(&GV); + }; + + return extractSubModule(TSM, SubModuleName, ShouldExtract); + }); + + if (!ExtractedTSM) { + ES.reportError(ExtractedTSM.takeError()); + R->failMaterialization(); + return; + } + + if (auto Err = R->replace(std::make_unique( + ES, *getManglingOptions(), std::move(TSM), *this))) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } + BaseLayer.emit(std::move(R), std::move(*ExtractedTSM)); +} diff --git a/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp b/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp new file mode 100644 index 000000000000..0e123b98201b --- /dev/null +++ b/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp @@ -0,0 +1,182 @@ +//===-- JITLinkRedirectableSymbolManager.cpp - JITLink redirection in Orc -===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h" +#include "llvm/ExecutionEngine/Orc/Core.h" + +#define DEBUG_TYPE "orc" + +using namespace llvm; +using namespace llvm::orc; + +void JITLinkRedirectableSymbolManager::emitRedirectableSymbols( + std::unique_ptr R, + const SymbolAddrMap &InitialDests) { + auto &ES = ObjLinkingLayer.getExecutionSession(); + std::unique_lock Lock(Mutex); + if (GetNumAvailableStubs() < InitialDests.size()) + if (auto Err = grow(InitialDests.size() - GetNumAvailableStubs())) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } + + JITDylib &TargetJD = R->getTargetJITDylib(); + SymbolMap NewSymbolDefs; + std::vector Symbols; + for (auto &[K, V] : InitialDests) { + StubHandle StubID = AvailableStubs.back(); + if (SymbolToStubs[&TargetJD].count(K)) { + ES.reportError(make_error( + "Tried to create duplicate redirectable symbols", + inconvertibleErrorCode())); + R->failMaterialization(); + return; + } + SymbolToStubs[&TargetJD][K] = StubID; + NewSymbolDefs[K] = JumpStubs[StubID]; + NewSymbolDefs[K].setFlags(V.getFlags()); + Symbols.push_back(K); + AvailableStubs.pop_back(); + } + + // FIXME: when this fails we can return stubs to the pool + if (auto Err = redirectInner(TargetJD, InitialDests)) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } + + if (auto Err = R->replace(absoluteSymbols(NewSymbolDefs))) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } + + auto Err = R->withResourceKeyDo([&](ResourceKey Key) { + TrackedResources[Key].insert(TrackedResources[Key].end(), Symbols.begin(), + Symbols.end()); + }); + if (Err) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } +} + +Error JITLinkRedirectableSymbolManager::redirect( + JITDylib &TargetJD, const SymbolAddrMap &NewDests) { + std::unique_lock Lock(Mutex); + return redirectInner(TargetJD, NewDests); +} + +Error JITLinkRedirectableSymbolManager::redirectInner( + JITDylib &TargetJD, const SymbolAddrMap &NewDests) { + std::vector PtrWrites; + for (auto &[K, V] : NewDests) { + if (!SymbolToStubs[&TargetJD].count(K)) + return make_error( + "Tried to redirect non-existent redirectalbe symbol", + inconvertibleErrorCode()); + StubHandle StubID = SymbolToStubs[&TargetJD].at(K); + PtrWrites.push_back({StubPointers[StubID].getAddress(), V.getAddress()}); + } + return ObjLinkingLayer.getExecutionSession() + .getExecutorProcessControl() + .getMemoryAccess() + .writePointers(PtrWrites); +} + +Error JITLinkRedirectableSymbolManager::grow(unsigned Need) { + unsigned OldSize = JumpStubs.size(); + unsigned NumNewStubs = alignTo(Need, StubBlockSize); + unsigned NewSize = OldSize + NumNewStubs; + + JumpStubs.resize(NewSize); + StubPointers.resize(NewSize); + AvailableStubs.reserve(NewSize); + + SymbolLookupSet LookupSymbols; + DenseMap NewDefsMap; + + auto &ES = ObjLinkingLayer.getExecutionSession(); + Triple TT = ES.getTargetTriple(); + auto G = std::make_unique( + "", TT, TT.isArch64Bit() ? 8 : 4, + TT.isLittleEndian() ? support::little : support::big, + jitlink::getGenericEdgeKindName); + auto &PointerSection = + G->createSection(StubPtrTableName, MemProt::Write | MemProt::Read); + auto &StubsSection = + G->createSection(JumpStubTableName, MemProt::Exec | MemProt::Read); + + // FIXME: We can batch the stubs into one block and use address to access them + for (size_t I = OldSize; I < NewSize; I++) { + auto Pointer = AnonymousPtrCreator(*G, PointerSection, nullptr, 0); + if (auto Err = Pointer.takeError()) + return Err; + + StringRef PtrSymName = StubPtrSymbolName(I); + Pointer->setName(PtrSymName); + Pointer->setScope(jitlink::Scope::Default); + LookupSymbols.add(ES.intern(PtrSymName)); + NewDefsMap[ES.intern(PtrSymName)] = &StubPointers[I]; + + auto Stub = PtrJumpStubCreator(*G, StubsSection, *Pointer); + if (auto Err = Stub.takeError()) + return Err; + + StringRef JumpStubSymName = JumpStubSymbolName(I); + Stub->setName(JumpStubSymName); + Stub->setScope(jitlink::Scope::Default); + LookupSymbols.add(ES.intern(JumpStubSymName)); + NewDefsMap[ES.intern(JumpStubSymName)] = &JumpStubs[I]; + } + + if (auto Err = ObjLinkingLayer.add(JD, std::move(G))) + return Err; + + auto LookupResult = ES.lookup(makeJITDylibSearchOrder(&JD), LookupSymbols); + if (auto Err = LookupResult.takeError()) + return Err; + + for (auto &[K, V] : *LookupResult) + *NewDefsMap.at(K) = V; + + for (size_t I = OldSize; I < NewSize; I++) + AvailableStubs.push_back(I); + + return Error::success(); +} + +Error JITLinkRedirectableSymbolManager::handleRemoveResources( + JITDylib &TargetJD, ResourceKey K) { + std::unique_lock Lock(Mutex); + for (auto &Symbol : TrackedResources[K]) { + if (!SymbolToStubs[&TargetJD].count(Symbol)) + return make_error( + "Tried to remove non-existent redirectable symbol", + inconvertibleErrorCode()); + AvailableStubs.push_back(SymbolToStubs[&TargetJD].at(Symbol)); + SymbolToStubs[&TargetJD].erase(Symbol); + if (SymbolToStubs[&TargetJD].empty()) + SymbolToStubs.erase(&TargetJD); + } + TrackedResources.erase(K); + + return Error::success(); +} + +void JITLinkRedirectableSymbolManager::handleTransferResources( + JITDylib &TargetJD, ResourceKey DstK, ResourceKey SrcK) { + std::unique_lock Lock(Mutex); + TrackedResources[DstK].insert(TrackedResources[DstK].end(), + TrackedResources[SrcK].begin(), + TrackedResources[SrcK].end()); + TrackedResources.erase(SrcK); +} diff --git a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp index 568b2ececaa0..ea43dfcf2ec0 100644 --- a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp +++ b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp @@ -1268,9 +1268,12 @@ LLLazyJIT::LLLazyJIT(LLLazyJITBuilderState &S, Error &Err) : LLJIT(S, Err) { return; } + // Create the IP Layer. + IPLayer = std::make_unique(*ES, *InitHelperTransformLayer); + // Create the COD layer. - CODLayer = std::make_unique( - *ES, *InitHelperTransformLayer, *LCTMgr, std::move(ISMBuilder)); + CODLayer = std::make_unique(*ES, *IPLayer, *LCTMgr, + std::move(ISMBuilder)); if (*S.SupportConcurrentCompilation) CODLayer->setCloneToNewContextOnEmit(true); diff --git a/llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp b/llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp new file mode 100644 index 000000000000..2ec82f210e6f --- /dev/null +++ b/llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp @@ -0,0 +1,278 @@ +#include "llvm/ExecutionEngine/Orc/ReOptimizeLayer.h" + +using namespace llvm; +using namespace orc; + +bool ReOptimizeLayer::ReOptMaterializationUnitState::tryStartReoptimize() { + std::unique_lock Lock(Mutex); + if (Reoptimizing) + return false; + + Reoptimizing = true; + return true; +} + +void ReOptimizeLayer::ReOptMaterializationUnitState::reoptimizeSucceeded() { + std::unique_lock Lock(Mutex); + assert(Reoptimizing && "Tried to mark unstarted reoptimization as done"); + Reoptimizing = false; + CurVersion++; +} + +void ReOptimizeLayer::ReOptMaterializationUnitState::reoptimizeFailed() { + std::unique_lock Lock(Mutex); + assert(Reoptimizing && "Tried to mark unstarted reoptimization as done"); + Reoptimizing = false; +} + +Error ReOptimizeLayer::reigsterRuntimeFunctions(JITDylib &PlatformJD) { + ExecutionSession::JITDispatchHandlerAssociationMap WFs; + using ReoptimizeSPSSig = shared::SPSError(uint64_t, uint32_t); + WFs[ES.intern("__orc_rt_reoptimize_tag")] = + ES.wrapAsyncWithSPS(this, + &ReOptimizeLayer::rt_reoptimize); + return ES.registerJITDispatchHandlers(PlatformJD, std::move(WFs)); +} + +void ReOptimizeLayer::emit(std::unique_ptr R, + ThreadSafeModule TSM) { + auto &JD = R->getTargetJITDylib(); + + bool HasNonCallable = false; + for (auto &KV : R->getSymbols()) { + auto &Flags = KV.second; + if (!Flags.isCallable()) + HasNonCallable = true; + } + + if (HasNonCallable) { + BaseLayer.emit(std::move(R), std::move(TSM)); + return; + } + + auto &MUState = createMaterializationUnitState(TSM); + + if (auto Err = R->withResourceKeyDo([&](ResourceKey Key) { + registerMaterializationUnitResource(Key, MUState); + })) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } + + if (auto Err = + ProfilerFunc(*this, MUState.getID(), MUState.getCurVersion(), TSM)) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } + + auto InitialDests = + emitMUImplSymbols(MUState, MUState.getCurVersion(), JD, std::move(TSM)); + if (!InitialDests) { + ES.reportError(InitialDests.takeError()); + R->failMaterialization(); + return; + } + + RSManager.emitRedirectableSymbols(std::move(R), std::move(*InitialDests)); +} + +Error ReOptimizeLayer::reoptimizeIfCallFrequent(ReOptimizeLayer &Parent, + ReOptMaterializationUnitID MUID, + unsigned CurVersion, + ThreadSafeModule &TSM) { + return TSM.withModuleDo([&](Module &M) -> Error { + Type *I64Ty = Type::getInt64Ty(M.getContext()); + GlobalVariable *Counter = new GlobalVariable( + M, I64Ty, false, GlobalValue::InternalLinkage, + Constant::getNullValue(I64Ty), "__orc_reopt_counter"); + auto ArgBufferConst = createReoptimizeArgBuffer(M, MUID, CurVersion); + if (auto Err = ArgBufferConst.takeError()) + return Err; + GlobalVariable *ArgBuffer = + new GlobalVariable(M, (*ArgBufferConst)->getType(), true, + GlobalValue::InternalLinkage, (*ArgBufferConst)); + for (auto &F : M) { + if (F.isDeclaration()) + continue; + auto &BB = F.getEntryBlock(); + auto *IP = &*BB.getFirstInsertionPt(); + IRBuilder<> IRB(IP); + Value *Threshold = ConstantInt::get(I64Ty, CallCountThreshold, true); + Value *Cnt = IRB.CreateLoad(I64Ty, Counter); + // Use EQ to prevent further reoptimize calls. + Value *Cmp = IRB.CreateICmpEQ(Cnt, Threshold); + Value *Added = IRB.CreateAdd(Cnt, ConstantInt::get(I64Ty, 1)); + (void)IRB.CreateStore(Added, Counter); + Instruction *SplitTerminator = SplitBlockAndInsertIfThen(Cmp, IP, false); + createReoptimizeCall(M, *SplitTerminator, ArgBuffer); + } + return Error::success(); + }); +} + +Expected +ReOptimizeLayer::emitMUImplSymbols(ReOptMaterializationUnitState &MUState, + uint32_t Version, JITDylib &JD, + ThreadSafeModule TSM) { + DenseMap RenamedMap; + cantFail(TSM.withModuleDo([&](Module &M) -> Error { + MangleAndInterner Mangle(ES, M.getDataLayout()); + for (auto &F : M) + if (!F.isDeclaration()) { + std::string NewName = + (F.getName() + ".__def__." + Twine(Version)).str(); + RenamedMap[Mangle(F.getName())] = Mangle(NewName); + F.setName(NewName); + } + return Error::success(); + })); + + auto RT = JD.createResourceTracker(); + if (auto Err = + JD.define(std::make_unique( + BaseLayer, *getManglingOptions(), std::move(TSM)), + RT)) + return Err; + MUState.setResourceTracker(RT); + + SymbolLookupSet LookupSymbols; + for (auto [K, V] : RenamedMap) + LookupSymbols.add(V); + + auto ImplSymbols = + ES.lookup({{&JD, JITDylibLookupFlags::MatchAllSymbols}}, LookupSymbols, + LookupKind::Static, SymbolState::Resolved); + if (auto Err = ImplSymbols.takeError()) + return Err; + + SymbolMap Result; + for (auto [K, V] : RenamedMap) + Result[K] = (*ImplSymbols)[V]; + + return Result; +} + +void ReOptimizeLayer::rt_reoptimize(SendErrorFn SendResult, + ReOptMaterializationUnitID MUID, + uint32_t CurVersion) { + auto &MUState = getMaterializationUnitState(MUID); + if (CurVersion < MUState.getCurVersion() || !MUState.tryStartReoptimize()) { + SendResult(Error::success()); + return; + } + + ThreadSafeModule TSM = cloneToNewContext(MUState.getThreadSafeModule()); + auto OldRT = MUState.getResourceTracker(); + auto &JD = OldRT->getJITDylib(); + + if (auto Err = ReOptFunc(*this, MUID, CurVersion + 1, OldRT, TSM)) { + ES.reportError(std::move(Err)); + MUState.reoptimizeFailed(); + SendResult(Error::success()); + return; + } + + auto SymbolDests = + emitMUImplSymbols(MUState, CurVersion + 1, JD, std::move(TSM)); + if (!SymbolDests) { + ES.reportError(SymbolDests.takeError()); + MUState.reoptimizeFailed(); + SendResult(Error::success()); + return; + } + + if (auto Err = RSManager.redirect(JD, std::move(*SymbolDests))) { + ES.reportError(std::move(Err)); + MUState.reoptimizeFailed(); + SendResult(Error::success()); + return; + } + + MUState.reoptimizeSucceeded(); + SendResult(Error::success()); +} + +Expected ReOptimizeLayer::createReoptimizeArgBuffer( + Module &M, ReOptMaterializationUnitID MUID, uint32_t CurVersion) { + size_t ArgBufferSize = SPSReoptimizeArgList::size(MUID, CurVersion); + std::vector ArgBuffer(ArgBufferSize); + shared::SPSOutputBuffer OB(ArgBuffer.data(), ArgBuffer.size()); + if (!SPSReoptimizeArgList::serialize(OB, MUID, CurVersion)) + return make_error("Could not serealize args list", + inconvertibleErrorCode()); + return ConstantDataArray::get(M.getContext(), ArrayRef(ArgBuffer)); +} + +void ReOptimizeLayer::createReoptimizeCall(Module &M, Instruction &IP, + GlobalVariable *ArgBuffer) { + GlobalVariable *DispatchCtx = + M.getGlobalVariable("__orc_rt_jit_dispatch_ctx"); + if (!DispatchCtx) + DispatchCtx = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), + false, GlobalValue::ExternalLinkage, + nullptr, "__orc_rt_jit_dispatch_ctx"); + GlobalVariable *ReoptimizeTag = + M.getGlobalVariable("__orc_rt_reoptimize_tag"); + if (!ReoptimizeTag) + ReoptimizeTag = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), + false, GlobalValue::ExternalLinkage, + nullptr, "__orc_rt_reoptimize_tag"); + Function *DispatchFunc = M.getFunction("__orc_rt_jit_dispatch"); + if (!DispatchFunc) { + std::vector Args = {Type::getInt8PtrTy(M.getContext()), + Type::getInt8PtrTy(M.getContext()), + Type::getInt8PtrTy(M.getContext()), + IntegerType::get(M.getContext(), 64)}; + FunctionType *FuncTy = + FunctionType::get(Type::getVoidTy(M.getContext()), Args, false); + DispatchFunc = Function::Create(FuncTy, GlobalValue::ExternalLinkage, + "__orc_rt_jit_dispatch", &M); + } + size_t ArgBufferSizeConst = + SPSReoptimizeArgList::size(ReOptMaterializationUnitID{}, uint32_t{}); + Constant *ArgBufferSize = ConstantInt::get( + IntegerType::get(M.getContext(), 64), ArgBufferSizeConst, false); + IRBuilder<> IRB(&IP); + (void)IRB.CreateCall(DispatchFunc, + {DispatchCtx, ReoptimizeTag, ArgBuffer, ArgBufferSize}); +} + +ReOptimizeLayer::ReOptMaterializationUnitState & +ReOptimizeLayer::createMaterializationUnitState(const ThreadSafeModule &TSM) { + std::unique_lock Lock(Mutex); + ReOptMaterializationUnitID MUID = NextID; + MUStates.emplace(MUID, + ReOptMaterializationUnitState(MUID, cloneToNewContext(TSM))); + ++NextID; + return MUStates.at(MUID); +} + +ReOptimizeLayer::ReOptMaterializationUnitState & +ReOptimizeLayer::getMaterializationUnitState(ReOptMaterializationUnitID MUID) { + std::unique_lock Lock(Mutex); + return MUStates.at(MUID); +} + +void ReOptimizeLayer::registerMaterializationUnitResource( + ResourceKey Key, ReOptMaterializationUnitState &State) { + std::unique_lock Lock(Mutex); + MUResources[Key].insert(State.getID()); +} + +Error ReOptimizeLayer::handleRemoveResources(JITDylib &JD, ResourceKey K) { + std::unique_lock Lock(Mutex); + for (auto MUID : MUResources[K]) + MUStates.erase(MUID); + + MUResources.erase(K); + return Error::success(); +} + +void ReOptimizeLayer::handleTransferResources(JITDylib &JD, ResourceKey DstK, + ResourceKey SrcK) { + std::unique_lock Lock(Mutex); + MUResources[DstK].insert(MUResources[SrcK].begin(), MUResources[SrcK].end()); + MUResources.erase(SrcK); +} diff --git a/llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp b/llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp new file mode 100644 index 000000000000..cbc77c503430 --- /dev/null +++ b/llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp @@ -0,0 +1,24 @@ +//===---- RedirectionManager.cpp - Redirection manager interface in Orc ---===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "llvm/ExecutionEngine/Orc/RedirectionManager.h" + +#define DEBUG_TYPE "orc" + +using namespace llvm; +using namespace llvm::orc; + +void RedirectionManager::anchor() {} + +Error RedirectableSymbolManager::createRedirectableSymbols( + ResourceTrackerSP RT, const SymbolMap &InitialDests) { + auto &JD = RT->getJITDylib(); + return JD.define( + std::make_unique(*this, InitialDests), + RT); +} diff --git a/llvm/tools/lli/lli.cpp b/llvm/tools/lli/lli.cpp index 25f43a4bb681..5c57b573b234 100644 --- a/llvm/tools/lli/lli.cpp +++ b/llvm/tools/lli/lli.cpp @@ -30,6 +30,7 @@ #include "llvm/ExecutionEngine/Orc/EPCEHFrameRegistrar.h" #include "llvm/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" +#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/LLJIT.h" #include "llvm/ExecutionEngine/Orc/ObjectTransformLayer.h" @@ -1061,7 +1062,7 @@ int runOrcJIT(const char *ProgName) { } if (PerModuleLazy) - J->setPartitionFunction(orc::CompileOnDemandLayer::compileWholeModule); + J->setPartitionFunction(orc::IRPartitionLayer::compileWholeModule); auto IRDump = createIRDebugDumper(); J->getIRTransformLayer().setTransform( diff --git a/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt b/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt index 8a6a26bba63c..cc85f8963628 100644 --- a/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt +++ b/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt @@ -42,6 +42,8 @@ add_llvm_unittest(OrcJITTests TaskDispatchTest.cpp ThreadSafeModuleTest.cpp WrapperFunctionUtilsTest.cpp + JITLinkRedirectionManagerTest.cpp + ReOptimizeLayerTest.cpp ) target_link_libraries(OrcJITTests PRIVATE diff --git a/llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp b/llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp new file mode 100644 index 000000000000..f063111354ac --- /dev/null +++ b/llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp @@ -0,0 +1,99 @@ +#include "OrcTestCommon.h" +#include "llvm/ExecutionEngine/JITLink/JITLinkMemoryManager.h" +#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h" +#include "llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h" +#include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" +#include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" +#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h" +#include "llvm/Testing/Support/Error.h" +#include "gtest/gtest.h" + +using namespace llvm; +using namespace llvm::orc; +using namespace llvm::jitlink; + +static int initialTarget() { return 42; } +static int middleTarget() { return 13; } +static int finalTarget() { return 53; } + +class JITLinkRedirectionManagerTest : public testing::Test { +public: + ~JITLinkRedirectionManagerTest() { + if (ES) + if (auto Err = ES->endSession()) + ES->reportError(std::move(Err)); + } + +protected: + void SetUp() override { + auto JTMB = JITTargetMachineBuilder::detectHost(); + // Bail out if we can not detect the host. + if (!JTMB) { + consumeError(JTMB.takeError()); + GTEST_SKIP(); + } + + ES = std::make_unique( + std::make_unique( + nullptr, nullptr, JTMB->getTargetTriple().getTriple())); + JD = &ES->createBareJITDylib("main"); + ObjLinkingLayer = std::make_unique( + *ES, std::make_unique(4096)); + DL = std::make_unique( + cantFail(JTMB->getDefaultDataLayoutForTarget())); + } + JITDylib *JD{nullptr}; + std::unique_ptr ES; + std::unique_ptr ObjLinkingLayer; + std::unique_ptr DL; +}; + +TEST_F(JITLinkRedirectionManagerTest, BasicRedirectionOperation) { + auto RM = JITLinkRedirectableSymbolManager::Create(*ObjLinkingLayer, *JD); + // Bail out if we can not create + if (!RM) { + consumeError(RM.takeError()); + GTEST_SKIP(); + } + + auto DefineTarget = [&](StringRef TargetName, ExecutorAddr Addr) { + SymbolStringPtr Target = ES->intern(TargetName); + cantFail(JD->define(std::make_unique( + SymbolFlagsMap({{Target, JITSymbolFlags::Exported}}), + [&](std::unique_ptr R) -> void { + // No dependencies registered, can't fail. + cantFail( + R->notifyResolved({{Target, {Addr, JITSymbolFlags::Exported}}})); + cantFail(R->notifyEmitted()); + }))); + return cantFail(ES->lookup({JD}, TargetName)); + }; + + auto InitialTarget = + DefineTarget("InitialTarget", ExecutorAddr::fromPtr(&initialTarget)); + auto MiddleTarget = + DefineTarget("MiddleTarget", ExecutorAddr::fromPtr(&middleTarget)); + auto FinalTarget = + DefineTarget("FinalTarget", ExecutorAddr::fromPtr(&finalTarget)); + + auto RedirectableSymbol = ES->intern("RedirectableTarget"); + EXPECT_THAT_ERROR( + (*RM)->createRedirectableSymbols(JD->getDefaultResourceTracker(), + {{RedirectableSymbol, InitialTarget}}), + Succeeded()); + auto RTDef = cantFail(ES->lookup({JD}, RedirectableSymbol)); + + auto RTPtr = RTDef.getAddress().toPtr(); + auto Result = RTPtr(); + EXPECT_EQ(Result, 42) << "Failed to call initial target"; + + EXPECT_THAT_ERROR((*RM)->redirect(*JD, {{RedirectableSymbol, MiddleTarget}}), + Succeeded()); + Result = RTPtr(); + EXPECT_EQ(Result, 13) << "Failed to call middle redirected target"; + + EXPECT_THAT_ERROR((*RM)->redirect(*JD, {{RedirectableSymbol, FinalTarget}}), + Succeeded()); + Result = RTPtr(); + EXPECT_EQ(Result, 53) << "Failed to call redirected target"; +} diff --git a/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp b/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp new file mode 100644 index 000000000000..1cecdf700976 --- /dev/null +++ b/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp @@ -0,0 +1,150 @@ +#include "llvm/ExecutionEngine/Orc/ReOptimizeLayer.h" +#include "OrcTestCommon.h" +#include "llvm/ExecutionEngine/JITLink/JITLinkMemoryManager.h" +#include "llvm/ExecutionEngine/Orc/CompileUtils.h" +#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h" +#include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" +#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" +#include "llvm/ExecutionEngine/Orc/IRTransformLayer.h" +#include "llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h" +#include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" +#include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" +#include "llvm/ExecutionEngine/Orc/ObjectTransformLayer.h" +#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h" +#include "llvm/IR/IRBuilder.h" +#include "llvm/Support/CodeGen.h" +#include "llvm/TargetParser/Host.h" +#include "llvm/Testing/Support/Error.h" +#include "gtest/gtest.h" + +using namespace llvm; +using namespace llvm::orc; +using namespace llvm::jitlink; + +class ReOptimizeLayerTest : public testing::Test { +public: + ~ReOptimizeLayerTest() { + if (ES) + if (auto Err = ES->endSession()) + ES->reportError(std::move(Err)); + } + +protected: + void SetUp() override { + auto JTMB = JITTargetMachineBuilder::detectHost(); + // Bail out if we can not detect the host. + if (!JTMB) { + consumeError(JTMB.takeError()); + GTEST_SKIP(); + } + + auto EPC = SelfExecutorProcessControl::Create(); + if (!EPC) { + consumeError(EPC.takeError()); + GTEST_SKIP(); + } + ES = std::make_unique(std::move(*EPC)); + JD = &ES->createBareJITDylib("main"); + ObjLinkingLayer = std::make_unique( + *ES, std::make_unique(4096)); + DL = std::make_unique( + cantFail(JTMB->getDefaultDataLayoutForTarget())); + + auto TM = JTMB->createTargetMachine(); + if (!TM) { + consumeError(TM.takeError()); + GTEST_SKIP(); + } + auto CompileFunction = + std::make_unique(std::move(*TM)); + CompileLayer = std::make_unique(*ES, *ObjLinkingLayer, + std::move(CompileFunction)); + } + + Error addIRModule(ResourceTrackerSP RT, ThreadSafeModule TSM) { + assert(TSM && "Can not add null module"); + + TSM.withModuleDo([&](Module &M) { M.setDataLayout(*DL); }); + + return ROLayer->add(std::move(RT), std::move(TSM)); + } + + JITDylib *JD{nullptr}; + std::unique_ptr ES; + std::unique_ptr ObjLinkingLayer; + std::unique_ptr CompileLayer; + std::unique_ptr ROLayer; + std::unique_ptr DL; +}; + +static Function *createRetFunction(Module *M, StringRef Name, + uint32_t ReturnCode) { + Function *Result = Function::Create( + FunctionType::get(Type::getInt32Ty(M->getContext()), {}, false), + GlobalValue::ExternalLinkage, Name, M); + + BasicBlock *BB = BasicBlock::Create(M->getContext(), Name, Result); + IRBuilder<> Builder(M->getContext()); + Builder.SetInsertPoint(BB); + + Value *RetValue = ConstantInt::get(M->getContext(), APInt(32, ReturnCode)); + Builder.CreateRet(RetValue); + return Result; +} + +TEST_F(ReOptimizeLayerTest, BasicReOptimization) { + auto &EPC = ES->getExecutorProcessControl(); + EXPECT_THAT_ERROR(JD->define(absoluteSymbols( + {{ES->intern("__orc_rt_jit_dispatch"), + {EPC.getJITDispatchInfo().JITDispatchFunction, + JITSymbolFlags::Exported}}, + {ES->intern("__orc_rt_jit_dispatch_ctx"), + {EPC.getJITDispatchInfo().JITDispatchContext, + JITSymbolFlags::Exported}}, + {ES->intern("__orc_rt_reoptimize_tag"), + {ExecutorAddr(), JITSymbolFlags::Exported}}})), + Succeeded()); + + auto RM = JITLinkRedirectableSymbolManager::Create(*ObjLinkingLayer, *JD); + EXPECT_THAT_ERROR(RM.takeError(), Succeeded()); + + ROLayer = std::make_unique(*ES, *CompileLayer, **RM); + ROLayer->setReoptimizeFunc( + [&](ReOptimizeLayer &Parent, + ReOptimizeLayer::ReOptMaterializationUnitID MUID, unsigned CurVerison, + ResourceTrackerSP OldRT, ThreadSafeModule &TSM) { + TSM.withModuleDo([&](Module &M) { + for (auto &F : M) { + if (F.isDeclaration()) + continue; + for (auto &B : F) { + for (auto &I : B) { + if (ReturnInst *Ret = dyn_cast(&I)) { + Value *RetValue = + ConstantInt::get(M.getContext(), APInt(32, 53)); + Ret->setOperand(0, RetValue); + } + } + } + } + }); + return Error::success(); + }); + EXPECT_THAT_ERROR(ROLayer->reigsterRuntimeFunctions(*JD), Succeeded()); + + ThreadSafeContext Ctx(std::make_unique()); + auto M = std::make_unique("
", *Ctx.getContext()); + M->setTargetTriple(sys::getProcessTriple()); + + (void)createRetFunction(M.get(), "main", 42); + + EXPECT_THAT_ERROR(addIRModule(JD->getDefaultResourceTracker(), + ThreadSafeModule(std::move(M), std::move(Ctx))), + Succeeded()); + + auto Result = cantFail(ES->lookup({JD}, "main")); + auto FuncPtr = Result.getAddress().toPtr(); + for (size_t I = 0; I <= ReOptimizeLayer::CallCountThreshold; I++) + EXPECT_EQ(FuncPtr(), 42); + EXPECT_EQ(FuncPtr(), 53); +} -- GitLab From 82d87600e5141af85deb8f3c5387513fda50dc43 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 26 Apr 2024 14:44:07 +0900 Subject: [PATCH 012/301] [InstCombine] Add extra tests for mul nuw inference (NFC) --- llvm/test/Transforms/InstCombine/mul.ll | 80 +++++++++++++++++++++---- 1 file changed, 70 insertions(+), 10 deletions(-) diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll index 227ca4a6d5cf..4c1ce10171dd 100644 --- a/llvm/test/Transforms/InstCombine/mul.ll +++ b/llvm/test/Transforms/InstCombine/mul.ll @@ -2061,8 +2061,8 @@ define i32 @mul_sext_icmp_with_zero(i32 %x) { define i32 @test_mul_sext_bool(i1 %x, i32 %y) { ; CHECK-LABEL: @test_mul_sext_bool( -; CHECK-NEXT: [[Y_NEG:%.*]] = sub i32 0, [[Y:%.*]] -; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[Y_NEG]], i32 0 +; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[Y:%.*]] +; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[TMP1]], i32 0 ; CHECK-NEXT: ret i32 [[MUL]] ; %sext = sext i1 %x to i32 @@ -2072,8 +2072,8 @@ define i32 @test_mul_sext_bool(i1 %x, i32 %y) { define i32 @test_mul_sext_bool_nuw(i1 %x, i32 %y) { ; CHECK-LABEL: @test_mul_sext_bool_nuw( -; CHECK-NEXT: [[Y_NEG:%.*]] = sub i32 0, [[Y:%.*]] -; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[Y_NEG]], i32 0 +; CHECK-NEXT: [[TMP1:%.*]] = sub i32 0, [[Y:%.*]] +; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[TMP1]], i32 0 ; CHECK-NEXT: ret i32 [[MUL]] ; %sext = sext i1 %x to i32 @@ -2083,8 +2083,8 @@ define i32 @test_mul_sext_bool_nuw(i1 %x, i32 %y) { define i32 @test_mul_sext_bool_nsw(i1 %x, i32 %y) { ; CHECK-LABEL: @test_mul_sext_bool_nsw( -; CHECK-NEXT: [[Y_NEG:%.*]] = sub nsw i32 0, [[Y:%.*]] -; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[Y_NEG]], i32 0 +; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[Y:%.*]] +; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[TMP1]], i32 0 ; CHECK-NEXT: ret i32 [[MUL]] ; %sext = sext i1 %x to i32 @@ -2094,8 +2094,8 @@ define i32 @test_mul_sext_bool_nsw(i1 %x, i32 %y) { define i32 @test_mul_sext_bool_nuw_nsw(i1 %x, i32 %y) { ; CHECK-LABEL: @test_mul_sext_bool_nuw_nsw( -; CHECK-NEXT: [[Y_NEG:%.*]] = sub nsw i32 0, [[Y:%.*]] -; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[Y_NEG]], i32 0 +; CHECK-NEXT: [[TMP1:%.*]] = sub nsw i32 0, [[Y:%.*]] +; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[TMP1]], i32 0 ; CHECK-NEXT: ret i32 [[MUL]] ; %sext = sext i1 %x to i32 @@ -2106,8 +2106,8 @@ define i32 @test_mul_sext_bool_nuw_nsw(i1 %x, i32 %y) { define i32 @test_mul_sext_bool_commuted(i1 %x, i32 %y) { ; CHECK-LABEL: @test_mul_sext_bool_commuted( ; CHECK-NEXT: [[TMP1:%.*]] = xor i32 [[Y:%.*]], -2 -; CHECK-NEXT: [[YY_NEG1:%.*]] = add i32 [[TMP1]], 1 -; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[YY_NEG1]], i32 0 +; CHECK-NEXT: [[YY_NEG:%.*]] = add i32 [[TMP1]], 1 +; CHECK-NEXT: [[MUL:%.*]] = select i1 [[X:%.*]], i32 [[YY_NEG]], i32 0 ; CHECK-NEXT: ret i32 [[MUL]] ; %yy = xor i32 %y, 1 @@ -2139,3 +2139,63 @@ define i32 @test_mul_sext_multiuse(i1 %x, i32 %y) { %mul = mul i32 %sext, %y ret i32 %mul } + +define i8 @mul_nsw_nonneg(i8 %x, i8 %y) { +; CHECK-LABEL: @mul_nsw_nonneg( +; CHECK-NEXT: [[X_NNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1 +; CHECK-NEXT: call void @llvm.assume(i1 [[X_NNEG]]) +; CHECK-NEXT: [[Y_NNEG:%.*]] = icmp sgt i8 [[Y:%.*]], -1 +; CHECK-NEXT: call void @llvm.assume(i1 [[Y_NNEG]]) +; CHECK-NEXT: [[MUL:%.*]] = mul nsw i8 [[X]], [[Y]] +; CHECK-NEXT: ret i8 [[MUL]] +; + %x.nneg = icmp sge i8 %x, 0 + call void @llvm.assume(i1 %x.nneg) + %y.nneg = icmp sge i8 %y, 0 + call void @llvm.assume(i1 %y.nneg) + %mul = mul nsw i8 %x, %y + ret i8 %mul +} + +define i8 @mul_nsw_not_nonneg1(i8 %x, i8 %y) { +; CHECK-LABEL: @mul_nsw_not_nonneg1( +; CHECK-NEXT: [[Y_NNEG:%.*]] = icmp sgt i8 [[Y:%.*]], -1 +; CHECK-NEXT: call void @llvm.assume(i1 [[Y_NNEG]]) +; CHECK-NEXT: [[MUL:%.*]] = mul nsw i8 [[X:%.*]], [[Y]] +; CHECK-NEXT: ret i8 [[MUL]] +; + %y.nneg = icmp sge i8 %y, 0 + call void @llvm.assume(i1 %y.nneg) + %mul = mul nsw i8 %x, %y + ret i8 %mul +} + +define i8 @mul_nsw_not_nonneg2(i8 %x, i8 %y) { +; CHECK-LABEL: @mul_nsw_not_nonneg2( +; CHECK-NEXT: [[X_NNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1 +; CHECK-NEXT: call void @llvm.assume(i1 [[X_NNEG]]) +; CHECK-NEXT: [[MUL:%.*]] = mul nsw i8 [[X]], [[Y:%.*]] +; CHECK-NEXT: ret i8 [[MUL]] +; + %x.nneg = icmp sge i8 %x, 0 + call void @llvm.assume(i1 %x.nneg) + %mul = mul nsw i8 %x, %y + ret i8 %mul +} + +define i8 @mul_not_nsw_nonneg(i8 %x, i8 %y) { +; CHECK-LABEL: @mul_not_nsw_nonneg( +; CHECK-NEXT: [[X_NNEG:%.*]] = icmp sgt i8 [[X:%.*]], -1 +; CHECK-NEXT: call void @llvm.assume(i1 [[X_NNEG]]) +; CHECK-NEXT: [[Y_NNEG:%.*]] = icmp sgt i8 [[Y:%.*]], -1 +; CHECK-NEXT: call void @llvm.assume(i1 [[Y_NNEG]]) +; CHECK-NEXT: [[MUL:%.*]] = mul i8 [[X]], [[Y]] +; CHECK-NEXT: ret i8 [[MUL]] +; + %x.nneg = icmp sge i8 %x, 0 + call void @llvm.assume(i1 %x.nneg) + %y.nneg = icmp sge i8 %y, 0 + call void @llvm.assume(i1 %y.nneg) + %mul = mul i8 %x, %y + ret i8 %mul +} -- GitLab From 47682e4b4a0c8e7637d65868a7208aa6806a50f4 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Fri, 26 Apr 2024 14:47:15 +0900 Subject: [PATCH 013/301] Revert "[ORC] Implement basic reoptimization. (#67050)" This reverts commit 0d288e5b0ccf217e41944ad4fd8772d8ae45daa1. Breaks the build. --- compiler-rt/lib/orc/common.h | 6 +- compiler-rt/lib/orc/elfnix_platform.cpp | 1 - .../BuildingAJIT/Chapter3/KaleidoscopeJIT.h | 6 +- .../SpeculativeJIT/SpeculativeJIT.cpp | 9 +- .../Orc/CompileOnDemandLayer.h | 36 ++- .../ExecutionEngine/Orc/IRPartitionLayer.h | 85 ----- .../Orc/JITLinkRedirectableSymbolManager.h | 107 ------- llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h | 7 +- .../ExecutionEngine/Orc/ReOptimizeLayer.h | 179 ----------- .../ExecutionEngine/Orc/RedirectionManager.h | 103 ------ llvm/lib/ExecutionEngine/Orc/CMakeLists.txt | 4 - .../Orc/CompileOnDemandLayer.cpp | 282 +++++++++++++++- .../ExecutionEngine/Orc/IRPartitionLayer.cpp | 303 ------------------ .../Orc/JITLinkRedirectableSymbolManager.cpp | 182 ----------- llvm/lib/ExecutionEngine/Orc/LLJIT.cpp | 7 +- .../ExecutionEngine/Orc/ReOptimizeLayer.cpp | 278 ---------------- .../Orc/RedirectionManager.cpp | 24 -- llvm/tools/lli/lli.cpp | 3 +- .../ExecutionEngine/Orc/CMakeLists.txt | 2 - .../Orc/JITLinkRedirectionManagerTest.cpp | 99 ------ .../Orc/ReOptimizeLayerTest.cpp | 150 --------- 21 files changed, 325 insertions(+), 1548 deletions(-) delete mode 100644 llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h delete mode 100644 llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h delete mode 100644 llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h delete mode 100644 llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h delete mode 100644 llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp delete mode 100644 llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp delete mode 100644 llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp delete mode 100644 llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp delete mode 100644 llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp delete mode 100644 llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp diff --git a/compiler-rt/lib/orc/common.h b/compiler-rt/lib/orc/common.h index f34229a61534..73c5c4a2bd8d 100644 --- a/compiler-rt/lib/orc/common.h +++ b/compiler-rt/lib/orc/common.h @@ -19,9 +19,9 @@ /// This macro should be used to define tags that will be associated with /// handlers in the JIT process, and call can be used to define tags f -#define ORC_RT_JIT_DISPATCH_TAG(X) \ - ORC_RT_INTERFACE char X; \ - char X = 0; +#define ORC_RT_JIT_DISPATCH_TAG(X) \ +extern "C" char X; \ +char X = 0; /// Opaque struct for external symbols. struct __orc_rt_Opaque {}; diff --git a/compiler-rt/lib/orc/elfnix_platform.cpp b/compiler-rt/lib/orc/elfnix_platform.cpp index f76a07024031..c087e71038f9 100644 --- a/compiler-rt/lib/orc/elfnix_platform.cpp +++ b/compiler-rt/lib/orc/elfnix_platform.cpp @@ -28,7 +28,6 @@ using namespace __orc_rt; using namespace __orc_rt::elfnix; // Declare function tags for functions in the JIT process. -ORC_RT_JIT_DISPATCH_TAG(__orc_rt_reoptimize_tag) ORC_RT_JIT_DISPATCH_TAG(__orc_rt_elfnix_get_initializers_tag) ORC_RT_JIT_DISPATCH_TAG(__orc_rt_elfnix_get_deinitializers_tag) ORC_RT_JIT_DISPATCH_TAG(__orc_rt_elfnix_symbol_lookup_tag) diff --git a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h index fee2d26e5d92..fd0e081ff2b4 100644 --- a/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h +++ b/llvm/examples/Kaleidoscope/BuildingAJIT/Chapter3/KaleidoscopeJIT.h @@ -21,7 +21,6 @@ #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h" #include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" -#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/IRTransformLayer.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h" @@ -49,7 +48,6 @@ private: RTDyldObjectLinkingLayer ObjectLayer; IRCompileLayer CompileLayer; IRTransformLayer OptimizeLayer; - IRPartitionLayer IPLayer; CompileOnDemandLayer CODLayer; JITDylib &MainJD; @@ -70,8 +68,8 @@ public: CompileLayer(*this->ES, ObjectLayer, std::make_unique(std::move(JTMB))), OptimizeLayer(*this->ES, CompileLayer, optimizeModule), - IPLayer(*this->ES, OptimizeLayer), - CODLayer(*this->ES, IPLayer, this->EPCIU->getLazyCallThroughManager(), + CODLayer(*this->ES, OptimizeLayer, + this->EPCIU->getLazyCallThroughManager(), [this] { return this->EPCIU->createIndirectStubsManager(); }), MainJD(this->ES->createBareJITDylib("
")) { MainJD.addGenerator( diff --git a/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp b/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp index 24ae953eca7a..1659e5c5c8b4 100644 --- a/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp +++ b/llvm/examples/SpeculativeJIT/SpeculativeJIT.cpp @@ -3,7 +3,6 @@ #include "llvm/ExecutionEngine/Orc/Core.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" -#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/IndirectionUtils.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/RTDyldObjectLinkingLayer.h" @@ -110,14 +109,13 @@ private: IndirectStubsManagerBuilderFunction ISMBuilder, std::unique_ptr ProcessSymbolsGenerator) : ES(std::move(ES)), DL(std::move(DL)), - MainJD(this->ES->createBareJITDylib("
")), - LCTMgr(std::move(LCTMgr)), + MainJD(this->ES->createBareJITDylib("
")), LCTMgr(std::move(LCTMgr)), CompileLayer(*this->ES, ObjLayer, std::make_unique(std::move(JTMB))), S(Imps, *this->ES), SpeculateLayer(*this->ES, CompileLayer, S, Mangle, BlockFreqQuery()), - IPLayer(*this->ES, SpeculateLayer), - CODLayer(*this->ES, IPLayer, *this->LCTMgr, std::move(ISMBuilder)) { + CODLayer(*this->ES, SpeculateLayer, *this->LCTMgr, + std::move(ISMBuilder)) { MainJD.addGenerator(std::move(ProcessSymbolsGenerator)); this->CODLayer.setImplMap(&Imps); ExitOnErr(S.addSpeculationRuntime(MainJD, Mangle)); @@ -143,7 +141,6 @@ private: Speculator S; RTDyldObjectLinkingLayer ObjLayer{*ES, createMemMgr}; IRSpeculationLayer SpeculateLayer; - IRPartitionLayer IPLayer; CompileOnDemandLayer CODLayer; }; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h b/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h index d492dfe29fba..41f2882c576e 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h @@ -53,15 +53,37 @@ namespace llvm { namespace orc { class CompileOnDemandLayer : public IRLayer { + friend class PartitioningIRMaterializationUnit; + public: /// Builder for IndirectStubsManagers. using IndirectStubsManagerBuilder = std::function()>; + using GlobalValueSet = std::set; + + /// Partitioning function. + using PartitionFunction = + std::function(GlobalValueSet Requested)>; + + /// Off-the-shelf partitioning which compiles all requested symbols (usually + /// a single function at a time). + static std::optional + compileRequested(GlobalValueSet Requested); + + /// Off-the-shelf partitioning which compiles whole modules whenever any + /// symbol in them is requested. + static std::optional + compileWholeModule(GlobalValueSet Requested); + /// Construct a CompileOnDemandLayer. CompileOnDemandLayer(ExecutionSession &ES, IRLayer &BaseLayer, - LazyCallThroughManager &LCTMgr, - IndirectStubsManagerBuilder BuildIndirectStubsManager); + LazyCallThroughManager &LCTMgr, + IndirectStubsManagerBuilder BuildIndirectStubsManager); + + /// Sets the partition function. + void setPartitionFunction(PartitionFunction Partition); + /// Sets the ImplSymbolMap void setImplMap(ImplSymbolMap *Imp); @@ -88,12 +110,22 @@ private: PerDylibResources &getPerDylibResources(JITDylib &TargetD); + void cleanUpModule(Module &M); + + void expandPartition(GlobalValueSet &Partition); + + void emitPartition(std::unique_ptr R, + ThreadSafeModule TSM, + IRMaterializationUnit::SymbolNameToDefinitionMap Defs); + mutable std::mutex CODLayerMutex; IRLayer &BaseLayer; LazyCallThroughManager &LCTMgr; IndirectStubsManagerBuilder BuildIndirectStubsManager; PerDylibResourcesMap DylibResources; + PartitionFunction Partition = compileRequested; + SymbolLinkagePromoter PromoteSymbols; ImplSymbolMap *AliaseeImpls = nullptr; }; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h b/llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h deleted file mode 100644 index a2981fea61d3..000000000000 --- a/llvm/include/llvm/ExecutionEngine/Orc/IRPartitionLayer.h +++ /dev/null @@ -1,85 +0,0 @@ -//===- IRPartitionLayer.h - Partition IR module on lookup -------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// JIT layer for breaking up modules into smaller submodules that only contains -// looked up symbols. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_EXECUTIONENGINE_ORC_IRPARTITIONLAYER_H -#define LLVM_EXECUTIONENGINE_ORC_IRPARTITIONLAYER_H - -#include "llvm/ExecutionEngine/Orc/IndirectionUtils.h" -#include "llvm/ExecutionEngine/Orc/Layer.h" -#include "llvm/IR/Attributes.h" -#include "llvm/IR/Constant.h" -#include "llvm/IR/Constants.h" -#include "llvm/IR/DataLayout.h" -#include "llvm/IR/Function.h" -#include "llvm/IR/GlobalAlias.h" -#include "llvm/IR/GlobalValue.h" -#include "llvm/IR/GlobalVariable.h" -#include "llvm/IR/Instruction.h" -#include "llvm/IR/Mangler.h" -#include "llvm/IR/Module.h" -#include "llvm/IR/Type.h" - -namespace llvm { -namespace orc { - -/// A layer that breaks up IR modules into smaller submodules that only contains -/// looked up symbols. -class IRPartitionLayer : public IRLayer { - friend class PartitioningIRMaterializationUnit; - -public: - using GlobalValueSet = std::set; - - /// Partitioning function. - using PartitionFunction = - std::function(GlobalValueSet Requested)>; - - /// Construct a IRPartitionLayer. - IRPartitionLayer(ExecutionSession &ES, IRLayer &BaseLayer); - - /// Off-the-shelf partitioning which compiles all requested symbols (usually - /// a single function at a time). - static std::optional - compileRequested(GlobalValueSet Requested); - - /// Off-the-shelf partitioning which compiles whole modules whenever any - /// symbol in them is requested. - static std::optional - compileWholeModule(GlobalValueSet Requested); - - /// Sets the partition function. - void setPartitionFunction(PartitionFunction Partition); - - /// Emits the given module. This should not be called by clients: it will be - /// called by the JIT when a definition added via the add method is requested. - void emit(std::unique_ptr R, - ThreadSafeModule TSM) override; - -private: - void cleanUpModule(Module &M); - - void expandPartition(GlobalValueSet &Partition); - - void emitPartition(std::unique_ptr R, - ThreadSafeModule TSM, - IRMaterializationUnit::SymbolNameToDefinitionMap Defs); - - IRLayer &BaseLayer; - PartitionFunction Partition = compileRequested; - SymbolLinkagePromoter PromoteSymbols; -}; - -} // namespace orc -} // namespace llvm - -#endif diff --git a/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h b/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h deleted file mode 100644 index 52f284c89bda..000000000000 --- a/llvm/include/llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h +++ /dev/null @@ -1,107 +0,0 @@ -//===- JITLinkRedirectableSymbolManager.h - JITLink redirection -*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Redirectable Symbol Manager implementation using JITLink -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLEMANAGER_H -#define LLVM_EXECUTIONENGINE_ORC_JITLINKREDIRECABLEMANAGER_H - -#include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" -#include "llvm/ExecutionEngine/Orc/RedirectionManager.h" -#include "llvm/Support/StringSaver.h" - -namespace llvm { -namespace orc { - -class JITLinkRedirectableSymbolManager : public RedirectableSymbolManager, - public ResourceManager { -public: - /// Create redirection manager that uses JITLink based implementaion. - static Expected> - Create(ObjectLinkingLayer &ObjLinkingLayer, JITDylib &JD) { - Error Err = Error::success(); - auto RM = std::unique_ptr( - new JITLinkRedirectableSymbolManager(ObjLinkingLayer, JD, Err)); - if (Err) - return Err; - return std::move(RM); - } - - void emitRedirectableSymbols(std::unique_ptr R, - const SymbolAddrMap &InitialDests) override; - - Error redirect(JITDylib &TargetJD, const SymbolAddrMap &NewDests) override; - - Error handleRemoveResources(JITDylib &TargetJD, ResourceKey K) override; - - void handleTransferResources(JITDylib &TargetJD, ResourceKey DstK, - ResourceKey SrcK) override; - -private: - using StubHandle = unsigned; - constexpr static unsigned StubBlockSize = 256; - constexpr static StringRef JumpStubPrefix = "$__IND_JUMP_STUBS"; - constexpr static StringRef StubPtrPrefix = "$IND_JUMP_PTR_"; - constexpr static StringRef JumpStubTableName = "$IND_JUMP_"; - constexpr static StringRef StubPtrTableName = "$__IND_JUMP_PTRS"; - - JITLinkRedirectableSymbolManager(ObjectLinkingLayer &ObjLinkingLayer, - JITDylib &JD, Error &Err) - : ObjLinkingLayer(ObjLinkingLayer), JD(JD), - AnonymousPtrCreator(jitlink::getAnonymousPointerCreator( - ObjLinkingLayer.getExecutionSession().getTargetTriple())), - PtrJumpStubCreator(jitlink::getPointerJumpStubCreator( - ObjLinkingLayer.getExecutionSession().getTargetTriple())) { - if (!AnonymousPtrCreator || !PtrJumpStubCreator) - Err = make_error("Architecture not supported", - inconvertibleErrorCode()); - if (Err) - return; - ObjLinkingLayer.getExecutionSession().registerResourceManager(*this); - } - - ~JITLinkRedirectableSymbolManager() { - ObjLinkingLayer.getExecutionSession().deregisterResourceManager(*this); - } - - StringRef JumpStubSymbolName(unsigned I) { - return *ObjLinkingLayer.getExecutionSession().intern( - (JumpStubPrefix + Twine(I)).str()); - } - - StringRef StubPtrSymbolName(unsigned I) { - return *ObjLinkingLayer.getExecutionSession().intern( - (StubPtrPrefix + Twine(I)).str()); - } - - unsigned GetNumAvailableStubs() const { return AvailableStubs.size(); } - - Error redirectInner(JITDylib &TargetJD, const SymbolAddrMap &NewDests); - Error grow(unsigned Need); - - ObjectLinkingLayer &ObjLinkingLayer; - JITDylib &JD; - jitlink::AnonymousPointerCreator AnonymousPtrCreator; - jitlink::PointerJumpStubCreator PtrJumpStubCreator; - - std::vector AvailableStubs; - using SymbolToStubMap = DenseMap; - DenseMap SymbolToStubs; - std::vector JumpStubs; - std::vector StubPointers; - DenseMap> TrackedResources; - - std::mutex Mutex; -}; - -} // namespace orc -} // namespace llvm - -#endif diff --git a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h index 7d1a5bc9e30d..3a71ddc88ce9 100644 --- a/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h +++ b/llvm/include/llvm/ExecutionEngine/Orc/LLJIT.h @@ -17,7 +17,6 @@ #include "llvm/ExecutionEngine/Orc/CompileUtils.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" #include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" -#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/IRTransformLayer.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/ThreadSafeModule.h" @@ -271,8 +270,9 @@ class LLLazyJIT : public LLJIT { public: /// Sets the partition function. - void setPartitionFunction(IRPartitionLayer::PartitionFunction Partition) { - IPLayer->setPartitionFunction(std::move(Partition)); + void + setPartitionFunction(CompileOnDemandLayer::PartitionFunction Partition) { + CODLayer->setPartitionFunction(std::move(Partition)); } /// Returns a reference to the on-demand layer. @@ -292,7 +292,6 @@ private: LLLazyJIT(LLLazyJITBuilderState &S, Error &Err); std::unique_ptr LCTMgr; - std::unique_ptr IPLayer; std::unique_ptr CODLayer; }; diff --git a/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h b/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h deleted file mode 100644 index fc27a6b8cb08..000000000000 --- a/llvm/include/llvm/ExecutionEngine/Orc/ReOptimizeLayer.h +++ /dev/null @@ -1,179 +0,0 @@ -//===- ReOptimizeLayer.h - Re-optimization layer interface ------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Re-optimization layer interface. -// -//===----------------------------------------------------------------------===// -#ifndef LLVM_EXECUTIONENGINE_ORC_REOPTIMIZELAYER_H -#define LLVM_EXECUTIONENGINE_ORC_REOPTIMIZELAYER_H - -#include "llvm/ExecutionEngine/Orc/Core.h" -#include "llvm/ExecutionEngine/Orc/Layer.h" -#include "llvm/ExecutionEngine/Orc/RedirectionManager.h" -#include "llvm/ExecutionEngine/Orc/ThreadSafeModule.h" -#include "llvm/IR/IRBuilder.h" -#include "llvm/Transforms/Utils/BasicBlockUtils.h" -#include "llvm/Transforms/Utils/Cloning.h" - -namespace llvm { -namespace orc { - -class ReOptimizeLayer : public IRLayer, public ResourceManager { -public: - using ReOptMaterializationUnitID = uint64_t; - - /// AddProfilerFunc will be called when ReOptimizeLayer emits the first - /// version of a materialization unit in order to inject profiling code and - /// reoptimization request code. - using AddProfilerFunc = unique_function; - - /// ReOptimizeFunc will be called when ReOptimizeLayer reoptimization of a - /// materialization unit was requested in order to reoptimize the IR module - /// based on profile data. OldRT is the ResourceTracker that tracks the old - /// function definitions. The OldRT must be kept alive until it can be - /// guaranteed that every invocation of the old function definitions has been - /// terminated. - using ReOptimizeFunc = unique_function; - - ReOptimizeLayer(ExecutionSession &ES, IRLayer &BaseLayer, - RedirectableSymbolManager &RM) - : IRLayer(ES, BaseLayer.getManglingOptions()), ES(ES), - BaseLayer(BaseLayer), RSManager(RM), ReOptFunc(identity), - ProfilerFunc(reoptimizeIfCallFrequent) {} - - void setReoptimizeFunc(ReOptimizeFunc ReOptFunc) { - this->ReOptFunc = std::move(ReOptFunc); - } - - void setAddProfilerFunc(AddProfilerFunc ProfilerFunc) { - this->ProfilerFunc = std::move(ProfilerFunc); - } - - /// Registers reoptimize runtime dispatch handlers to given PlatformJD. The - /// reoptimization request will not be handled if dispatch handler is not - /// registered by using this function. - Error reigsterRuntimeFunctions(JITDylib &PlatformJD); - - /// Emits the given module. This should not be called by clients: it will be - /// called by the JIT when a definition added via the add method is requested. - void emit(std::unique_ptr R, - ThreadSafeModule TSM) override; - - static const uint64_t CallCountThreshold = 10; - - /// Basic AddProfilerFunc that reoptimizes the function when the call count - /// exceeds CallCountThreshold. - static Error reoptimizeIfCallFrequent(ReOptimizeLayer &Parent, - ReOptMaterializationUnitID MUID, - unsigned CurVersion, - ThreadSafeModule &TSM); - - static Error identity(ReOptimizeLayer &Parent, - ReOptMaterializationUnitID MUID, unsigned CurVersion, - ResourceTrackerSP OldRT, ThreadSafeModule &TSM) { - return Error::success(); - } - - // Create IR reoptimize request fucntion call. - static void createReoptimizeCall(Module &M, Instruction &IP, - GlobalVariable *ArgBuffer); - - Error handleRemoveResources(JITDylib &JD, ResourceKey K) override; - void handleTransferResources(JITDylib &JD, ResourceKey DstK, - ResourceKey SrcK) override; - -private: - class ReOptMaterializationUnitState { - public: - ReOptMaterializationUnitState() = default; - ReOptMaterializationUnitState(ReOptMaterializationUnitID ID, - ThreadSafeModule TSM) - : ID(ID), TSM(std::move(TSM)) {} - ReOptMaterializationUnitState(ReOptMaterializationUnitState &&Other) - : ID(Other.ID), TSM(std::move(Other.TSM)), RT(std::move(Other.RT)), - Reoptimizing(std::move(Other.Reoptimizing)), - CurVersion(Other.CurVersion) {} - - ReOptMaterializationUnitID getID() { return ID; } - - const ThreadSafeModule &getThreadSafeModule() { return TSM; } - - ResourceTrackerSP getResourceTracker() { - std::unique_lock Lock(Mutex); - return RT; - } - - void setResourceTracker(ResourceTrackerSP RT) { - std::unique_lock Lock(Mutex); - this->RT = RT; - } - - uint32_t getCurVersion() { - std::unique_lock Lock(Mutex); - return CurVersion; - } - - bool tryStartReoptimize(); - void reoptimizeSucceeded(); - void reoptimizeFailed(); - - private: - std::mutex Mutex; - ReOptMaterializationUnitID ID; - ThreadSafeModule TSM; - ResourceTrackerSP RT; - bool Reoptimizing = false; - uint32_t CurVersion = 0; - }; - - using SPSReoptimizeArgList = - shared::SPSArgList; - using SendErrorFn = unique_function; - - Expected emitMUImplSymbols(ReOptMaterializationUnitState &MUState, - uint32_t Version, JITDylib &JD, - ThreadSafeModule TSM); - - void rt_reoptimize(SendErrorFn SendResult, ReOptMaterializationUnitID MUID, - uint32_t CurVersion); - - static Expected - createReoptimizeArgBuffer(Module &M, ReOptMaterializationUnitID MUID, - uint32_t CurVersion); - - ReOptMaterializationUnitState & - createMaterializationUnitState(const ThreadSafeModule &TSM); - - void - registerMaterializationUnitResource(ResourceKey Key, - ReOptMaterializationUnitState &State); - - ReOptMaterializationUnitState & - getMaterializationUnitState(ReOptMaterializationUnitID MUID); - - ExecutionSession &ES; - IRLayer &BaseLayer; - RedirectableSymbolManager &RSManager; - - ReOptimizeFunc ReOptFunc; - AddProfilerFunc ProfilerFunc; - - std::mutex Mutex; - std::map MUStates; - DenseMap> MUResources; - ReOptMaterializationUnitID NextID = 1; -}; - -} // namespace orc -} // namespace llvm - -#endif diff --git a/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h b/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h deleted file mode 100644 index 4004c42d9146..000000000000 --- a/llvm/include/llvm/ExecutionEngine/Orc/RedirectionManager.h +++ /dev/null @@ -1,103 +0,0 @@ -//===- RedirectionManager.h - Redirection manager interface -----*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Redirection manager interface that redirects a call to symbol to another. -// -//===----------------------------------------------------------------------===// - -#ifndef LLVM_EXECUTIONENGINE_ORC_REDIRECTIONMANAGER_H -#define LLVM_EXECUTIONENGINE_ORC_REDIRECTIONMANAGER_H - -#include "llvm/ExecutionEngine/Orc/Core.h" - -namespace llvm { -namespace orc { - -/// Base class for performing redirection of call to symbol to another symbol in -/// runtime. -class RedirectionManager { -public: - /// Symbol name to symbol definition map. - using SymbolAddrMap = DenseMap; - - virtual ~RedirectionManager() = default; - /// Change the redirection destination of given symbols to new destination - /// symbols. - virtual Error redirect(JITDylib &JD, const SymbolAddrMap &NewDests) = 0; - - /// Change the redirection destination of given symbol to new destination - /// symbol. - virtual Error redirect(JITDylib &JD, SymbolStringPtr Symbol, - ExecutorSymbolDef NewDest) { - return redirect(JD, {{Symbol, NewDest}}); - } - -private: - virtual void anchor(); -}; - -/// Base class for managing redirectable symbols in which a call -/// gets redirected to another symbol in runtime. -class RedirectableSymbolManager : public RedirectionManager { -public: - /// Create redirectable symbols with given symbol names and initial - /// desitnation symbol addresses. - Error createRedirectableSymbols(ResourceTrackerSP RT, - const SymbolMap &InitialDests); - - /// Create a single redirectable symbol with given symbol name and initial - /// desitnation symbol address. - Error createRedirectableSymbol(ResourceTrackerSP RT, SymbolStringPtr Symbol, - ExecutorSymbolDef InitialDest) { - return createRedirectableSymbols(RT, {{Symbol, InitialDest}}); - } - - /// Emit redirectable symbol - virtual void - emitRedirectableSymbols(std::unique_ptr MR, - const SymbolMap &InitialDests) = 0; -}; - -/// RedirectableMaterializationUnit materializes redirectable symbol -/// by invoking RedirectableSymbolManager::emitRedirectableSymbols -class RedirectableMaterializationUnit : public MaterializationUnit { -public: - RedirectableMaterializationUnit(RedirectableSymbolManager &RM, - const SymbolMap &InitialDests) - : MaterializationUnit(convertToFlags(InitialDests)), RM(RM), - InitialDests(InitialDests) {} - - StringRef getName() const override { - return "RedirectableSymbolMaterializationUnit"; - } - - void materialize(std::unique_ptr R) override { - RM.emitRedirectableSymbols(std::move(R), std::move(InitialDests)); - } - - void discard(const JITDylib &JD, const SymbolStringPtr &Name) override { - InitialDests.erase(Name); - } - -private: - static MaterializationUnit::Interface - convertToFlags(const SymbolMap &InitialDests) { - SymbolFlagsMap Flags; - for (auto [K, V] : InitialDests) - Flags[K] = V.getFlags(); - return MaterializationUnit::Interface(Flags, {}); - } - - RedirectableSymbolManager &RM; - SymbolMap InitialDests; -}; - -} // namespace orc -} // namespace llvm - -#endif diff --git a/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt b/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt index 7ed511969d96..f36605bbf03b 100644 --- a/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt +++ b/llvm/lib/ExecutionEngine/Orc/CMakeLists.txt @@ -26,7 +26,6 @@ add_llvm_component_library(LLVMOrcJIT IndirectionUtils.cpp IRCompileLayer.cpp IRTransformLayer.cpp - IRPartitionLayer.cpp JITTargetMachineBuilder.cpp LazyReexports.cpp Layer.cpp @@ -49,9 +48,6 @@ add_llvm_component_library(LLVMOrcJIT ExecutorProcessControl.cpp TaskDispatch.cpp ThreadSafeModule.cpp - RedirectionManager.cpp - JITLinkRedirectableSymbolManager.cpp - ReOptimizeLayer.cpp ADDITIONAL_HEADER_DIRS ${LLVM_MAIN_INCLUDE_DIR}/llvm/ExecutionEngine/Orc diff --git a/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp b/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp index 9296bc2b389a..6448adaa0ceb 100644 --- a/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp +++ b/llvm/lib/ExecutionEngine/Orc/CompileOnDemandLayer.cpp @@ -9,7 +9,6 @@ #include "llvm/ExecutionEngine/Orc/CompileOnDemandLayer.h" #include "llvm/ADT/Hashing.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" -#include "llvm/ExecutionEngine/Orc/Layer.h" #include "llvm/IR/Mangler.h" #include "llvm/IR/Module.h" #include "llvm/Support/FormatVariadic.h" @@ -18,6 +17,101 @@ using namespace llvm; using namespace llvm::orc; +static ThreadSafeModule extractSubModule(ThreadSafeModule &TSM, + StringRef Suffix, + GVPredicate ShouldExtract) { + + auto DeleteExtractedDefs = [](GlobalValue &GV) { + // Bump the linkage: this global will be provided by the external module. + GV.setLinkage(GlobalValue::ExternalLinkage); + + // Delete the definition in the source module. + if (isa(GV)) { + auto &F = cast(GV); + F.deleteBody(); + F.setPersonalityFn(nullptr); + } else if (isa(GV)) { + cast(GV).setInitializer(nullptr); + } else if (isa(GV)) { + // We need to turn deleted aliases into function or variable decls based + // on the type of their aliasee. + auto &A = cast(GV); + Constant *Aliasee = A.getAliasee(); + assert(A.hasName() && "Anonymous alias?"); + assert(Aliasee->hasName() && "Anonymous aliasee"); + std::string AliasName = std::string(A.getName()); + + if (isa(Aliasee)) { + auto *F = cloneFunctionDecl(*A.getParent(), *cast(Aliasee)); + A.replaceAllUsesWith(F); + A.eraseFromParent(); + F->setName(AliasName); + } else if (isa(Aliasee)) { + auto *G = cloneGlobalVariableDecl(*A.getParent(), + *cast(Aliasee)); + A.replaceAllUsesWith(G); + A.eraseFromParent(); + G->setName(AliasName); + } else + llvm_unreachable("Alias to unsupported type"); + } else + llvm_unreachable("Unsupported global type"); + }; + + auto NewTSM = cloneToNewContext(TSM, ShouldExtract, DeleteExtractedDefs); + NewTSM.withModuleDo([&](Module &M) { + M.setModuleIdentifier((M.getModuleIdentifier() + Suffix).str()); + }); + + return NewTSM; +} + +namespace llvm { +namespace orc { + +class PartitioningIRMaterializationUnit : public IRMaterializationUnit { +public: + PartitioningIRMaterializationUnit(ExecutionSession &ES, + const IRSymbolMapper::ManglingOptions &MO, + ThreadSafeModule TSM, + CompileOnDemandLayer &Parent) + : IRMaterializationUnit(ES, MO, std::move(TSM)), Parent(Parent) {} + + PartitioningIRMaterializationUnit( + ThreadSafeModule TSM, Interface I, + SymbolNameToDefinitionMap SymbolToDefinition, + CompileOnDemandLayer &Parent) + : IRMaterializationUnit(std::move(TSM), std::move(I), + std::move(SymbolToDefinition)), + Parent(Parent) {} + +private: + void materialize(std::unique_ptr R) override { + Parent.emitPartition(std::move(R), std::move(TSM), + std::move(SymbolToDefinition)); + } + + void discard(const JITDylib &V, const SymbolStringPtr &Name) override { + // All original symbols were materialized by the CODLayer and should be + // final. The function bodies provided by M should never be overridden. + llvm_unreachable("Discard should never be called on an " + "ExtractingIRMaterializationUnit"); + } + + mutable std::mutex SourceModuleMutex; + CompileOnDemandLayer &Parent; +}; + +std::optional +CompileOnDemandLayer::compileRequested(GlobalValueSet Requested) { + return std::move(Requested); +} + +std::optional +CompileOnDemandLayer::compileWholeModule(GlobalValueSet Requested) { + return std::nullopt; +} + CompileOnDemandLayer::CompileOnDemandLayer( ExecutionSession &ES, IRLayer &BaseLayer, LazyCallThroughManager &LCTMgr, IndirectStubsManagerBuilder BuildIndirectStubsManager) @@ -25,10 +119,13 @@ CompileOnDemandLayer::CompileOnDemandLayer( LCTMgr(LCTMgr), BuildIndirectStubsManager(std::move(BuildIndirectStubsManager)) {} +void CompileOnDemandLayer::setPartitionFunction(PartitionFunction Partition) { + this->Partition = std::move(Partition); +} + void CompileOnDemandLayer::setImplMap(ImplSymbolMap *Imp) { this->AliaseeImpls = Imp; } - void CompileOnDemandLayer::emit( std::unique_ptr R, ThreadSafeModule TSM) { assert(TSM && "Null module"); @@ -41,6 +138,10 @@ void CompileOnDemandLayer::emit( SymbolAliasMap NonCallables; SymbolAliasMap Callables; + TSM.withModuleDo([&](Module &M) { + // First, do some cleanup on the module: + cleanUpModule(M); + }); for (auto &KV : R->getSymbols()) { auto &Name = KV.first; @@ -51,10 +152,11 @@ void CompileOnDemandLayer::emit( NonCallables[Name] = SymbolAliasMapEntry(Name, Flags); } - // Lodge symbols with the implementation dylib. + // Create a partitioning materialization unit and lodge it with the + // implementation dylib. if (auto Err = PDR.getImplDylib().define( - std::make_unique( - BaseLayer, *getManglingOptions(), std::move(TSM)))) { + std::make_unique( + ES, *getManglingOptions(), std::move(TSM), *this))) { ES.reportError(std::move(Err)); R->failMaterialization(); return; @@ -108,3 +210,173 @@ CompileOnDemandLayer::getPerDylibResources(JITDylib &TargetD) { return I->second; } + +void CompileOnDemandLayer::cleanUpModule(Module &M) { + for (auto &F : M.functions()) { + if (F.isDeclaration()) + continue; + + if (F.hasAvailableExternallyLinkage()) { + F.deleteBody(); + F.setPersonalityFn(nullptr); + continue; + } + } +} + +void CompileOnDemandLayer::expandPartition(GlobalValueSet &Partition) { + // Expands the partition to ensure the following rules hold: + // (1) If any alias is in the partition, its aliasee is also in the partition. + // (2) If any aliasee is in the partition, its aliases are also in the + // partiton. + // (3) If any global variable is in the partition then all global variables + // are in the partition. + assert(!Partition.empty() && "Unexpected empty partition"); + + const Module &M = *(*Partition.begin())->getParent(); + bool ContainsGlobalVariables = false; + std::vector GVsToAdd; + + for (const auto *GV : Partition) + if (isa(GV)) + GVsToAdd.push_back( + cast(cast(GV)->getAliasee())); + else if (isa(GV)) + ContainsGlobalVariables = true; + + for (auto &A : M.aliases()) + if (Partition.count(cast(A.getAliasee()))) + GVsToAdd.push_back(&A); + + if (ContainsGlobalVariables) + for (auto &G : M.globals()) + GVsToAdd.push_back(&G); + + for (const auto *GV : GVsToAdd) + Partition.insert(GV); +} + +void CompileOnDemandLayer::emitPartition( + std::unique_ptr R, ThreadSafeModule TSM, + IRMaterializationUnit::SymbolNameToDefinitionMap Defs) { + + // FIXME: Need a 'notify lazy-extracting/emitting' callback to tie the + // extracted module key, extracted module, and source module key + // together. This could be used, for example, to provide a specific + // memory manager instance to the linking layer. + + auto &ES = getExecutionSession(); + GlobalValueSet RequestedGVs; + for (auto &Name : R->getRequestedSymbols()) { + if (Name == R->getInitializerSymbol()) + TSM.withModuleDo([&](Module &M) { + for (auto &GV : getStaticInitGVs(M)) + RequestedGVs.insert(&GV); + }); + else { + assert(Defs.count(Name) && "No definition for symbol"); + RequestedGVs.insert(Defs[Name]); + } + } + + /// Perform partitioning with the context lock held, since the partition + /// function is allowed to access the globals to compute the partition. + auto GVsToExtract = + TSM.withModuleDo([&](Module &M) { return Partition(RequestedGVs); }); + + // Take a 'None' partition to mean the whole module (as opposed to an empty + // partition, which means "materialize nothing"). Emit the whole module + // unmodified to the base layer. + if (GVsToExtract == std::nullopt) { + Defs.clear(); + BaseLayer.emit(std::move(R), std::move(TSM)); + return; + } + + // If the partition is empty, return the whole module to the symbol table. + if (GVsToExtract->empty()) { + if (auto Err = + R->replace(std::make_unique( + std::move(TSM), + MaterializationUnit::Interface(R->getSymbols(), + R->getInitializerSymbol()), + std::move(Defs), *this))) { + getExecutionSession().reportError(std::move(Err)); + R->failMaterialization(); + return; + } + return; + } + + // Ok -- we actually need to partition the symbols. Promote the symbol + // linkages/names, expand the partition to include any required symbols + // (i.e. symbols that can't be separated from our partition), and + // then extract the partition. + // + // FIXME: We apply this promotion once per partitioning. It's safe, but + // overkill. + auto ExtractedTSM = + TSM.withModuleDo([&](Module &M) -> Expected { + auto PromotedGlobals = PromoteSymbols(M); + if (!PromotedGlobals.empty()) { + + MangleAndInterner Mangle(ES, M.getDataLayout()); + SymbolFlagsMap SymbolFlags; + IRSymbolMapper::add(ES, *getManglingOptions(), + PromotedGlobals, SymbolFlags); + + if (auto Err = R->defineMaterializing(SymbolFlags)) + return std::move(Err); + } + + expandPartition(*GVsToExtract); + + // Submodule name is given by hashing the names of the globals. + std::string SubModuleName; + { + std::vector HashGVs; + HashGVs.reserve(GVsToExtract->size()); + for (const auto *GV : *GVsToExtract) + HashGVs.push_back(GV); + llvm::sort(HashGVs, [](const GlobalValue *LHS, const GlobalValue *RHS) { + return LHS->getName() < RHS->getName(); + }); + hash_code HC(0); + for (const auto *GV : HashGVs) { + assert(GV->hasName() && "All GVs to extract should be named by now"); + auto GVName = GV->getName(); + HC = hash_combine(HC, hash_combine_range(GVName.begin(), GVName.end())); + } + raw_string_ostream(SubModuleName) + << ".submodule." + << formatv(sizeof(size_t) == 8 ? "{0:x16}" : "{0:x8}", + static_cast(HC)) + << ".ll"; + } + + // Extract the requested partiton (plus any necessary aliases) and + // put the rest back into the impl dylib. + auto ShouldExtract = [&](const GlobalValue &GV) -> bool { + return GVsToExtract->count(&GV); + }; + + return extractSubModule(TSM, SubModuleName , ShouldExtract); + }); + + if (!ExtractedTSM) { + ES.reportError(ExtractedTSM.takeError()); + R->failMaterialization(); + return; + } + + if (auto Err = R->replace(std::make_unique( + ES, *getManglingOptions(), std::move(TSM), *this))) { + ES.reportError(std::move(Err)); + R->failMaterialization(); + return; + } + BaseLayer.emit(std::move(R), std::move(*ExtractedTSM)); +} + +} // end namespace orc +} // end namespace llvm diff --git a/llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp b/llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp deleted file mode 100644 index 9ad171beac7f..000000000000 --- a/llvm/lib/ExecutionEngine/Orc/IRPartitionLayer.cpp +++ /dev/null @@ -1,303 +0,0 @@ -//===----- IRPartitionLayer.cpp - Partition IR module into submodules -----===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" -#include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" -#include "llvm/ExecutionEngine/Orc/IndirectionUtils.h" - -using namespace llvm; -using namespace llvm::orc; - -static ThreadSafeModule extractSubModule(ThreadSafeModule &TSM, - StringRef Suffix, - GVPredicate ShouldExtract) { - - auto DeleteExtractedDefs = [](GlobalValue &GV) { - // Bump the linkage: this global will be provided by the external module. - GV.setLinkage(GlobalValue::ExternalLinkage); - - // Delete the definition in the source module. - if (isa(GV)) { - auto &F = cast(GV); - F.deleteBody(); - F.setPersonalityFn(nullptr); - } else if (isa(GV)) { - cast(GV).setInitializer(nullptr); - } else if (isa(GV)) { - // We need to turn deleted aliases into function or variable decls based - // on the type of their aliasee. - auto &A = cast(GV); - Constant *Aliasee = A.getAliasee(); - assert(A.hasName() && "Anonymous alias?"); - assert(Aliasee->hasName() && "Anonymous aliasee"); - std::string AliasName = std::string(A.getName()); - - if (isa(Aliasee)) { - auto *F = cloneFunctionDecl(*A.getParent(), *cast(Aliasee)); - A.replaceAllUsesWith(F); - A.eraseFromParent(); - F->setName(AliasName); - } else if (isa(Aliasee)) { - auto *G = cloneGlobalVariableDecl(*A.getParent(), - *cast(Aliasee)); - A.replaceAllUsesWith(G); - A.eraseFromParent(); - G->setName(AliasName); - } else - llvm_unreachable("Alias to unsupported type"); - } else - llvm_unreachable("Unsupported global type"); - }; - - auto NewTSM = cloneToNewContext(TSM, ShouldExtract, DeleteExtractedDefs); - NewTSM.withModuleDo([&](Module &M) { - M.setModuleIdentifier((M.getModuleIdentifier() + Suffix).str()); - }); - - return NewTSM; -} - -namespace llvm { -namespace orc { - -class PartitioningIRMaterializationUnit : public IRMaterializationUnit { -public: - PartitioningIRMaterializationUnit(ExecutionSession &ES, - const IRSymbolMapper::ManglingOptions &MO, - ThreadSafeModule TSM, - IRPartitionLayer &Parent) - : IRMaterializationUnit(ES, MO, std::move(TSM)), Parent(Parent) {} - - PartitioningIRMaterializationUnit( - ThreadSafeModule TSM, Interface I, - SymbolNameToDefinitionMap SymbolToDefinition, IRPartitionLayer &Parent) - : IRMaterializationUnit(std::move(TSM), std::move(I), - std::move(SymbolToDefinition)), - Parent(Parent) {} - -private: - void materialize(std::unique_ptr R) override { - Parent.emitPartition(std::move(R), std::move(TSM), - std::move(SymbolToDefinition)); - } - - void discard(const JITDylib &V, const SymbolStringPtr &Name) override { - // All original symbols were materialized by the CODLayer and should be - // final. The function bodies provided by M should never be overridden. - llvm_unreachable("Discard should never be called on an " - "ExtractingIRMaterializationUnit"); - } - - IRPartitionLayer &Parent; -}; - -} // namespace orc -} // namespace llvm - -IRPartitionLayer::IRPartitionLayer(ExecutionSession &ES, IRLayer &BaseLayer) - : IRLayer(ES, BaseLayer.getManglingOptions()), BaseLayer(BaseLayer) {} - -void IRPartitionLayer::setPartitionFunction(PartitionFunction Partition) { - this->Partition = Partition; -} - -std::optional -IRPartitionLayer::compileRequested(GlobalValueSet Requested) { - return std::move(Requested); -} - -std::optional -IRPartitionLayer::compileWholeModule(GlobalValueSet Requested) { - return std::nullopt; -} - -void IRPartitionLayer::emit(std::unique_ptr R, - ThreadSafeModule TSM) { - assert(TSM && "Null module"); - - auto &ES = getExecutionSession(); - TSM.withModuleDo([&](Module &M) { - // First, do some cleanup on the module: - cleanUpModule(M); - }); - - // Create a partitioning materialization unit and pass the responsibility. - if (auto Err = R->replace(std::make_unique( - ES, *getManglingOptions(), std::move(TSM), *this))) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } -} - -void IRPartitionLayer::cleanUpModule(Module &M) { - for (auto &F : M.functions()) { - if (F.isDeclaration()) - continue; - - if (F.hasAvailableExternallyLinkage()) { - F.deleteBody(); - F.setPersonalityFn(nullptr); - continue; - } - } -} - -void IRPartitionLayer::expandPartition(GlobalValueSet &Partition) { - // Expands the partition to ensure the following rules hold: - // (1) If any alias is in the partition, its aliasee is also in the partition. - // (2) If any aliasee is in the partition, its aliases are also in the - // partiton. - // (3) If any global variable is in the partition then all global variables - // are in the partition. - assert(!Partition.empty() && "Unexpected empty partition"); - - const Module &M = *(*Partition.begin())->getParent(); - bool ContainsGlobalVariables = false; - std::vector GVsToAdd; - - for (const auto *GV : Partition) - if (isa(GV)) - GVsToAdd.push_back( - cast(cast(GV)->getAliasee())); - else if (isa(GV)) - ContainsGlobalVariables = true; - - for (auto &A : M.aliases()) - if (Partition.count(cast(A.getAliasee()))) - GVsToAdd.push_back(&A); - - if (ContainsGlobalVariables) - for (auto &G : M.globals()) - GVsToAdd.push_back(&G); - - for (const auto *GV : GVsToAdd) - Partition.insert(GV); -} - -void IRPartitionLayer::emitPartition( - std::unique_ptr R, ThreadSafeModule TSM, - IRMaterializationUnit::SymbolNameToDefinitionMap Defs) { - - // FIXME: Need a 'notify lazy-extracting/emitting' callback to tie the - // extracted module key, extracted module, and source module key - // together. This could be used, for example, to provide a specific - // memory manager instance to the linking layer. - - auto &ES = getExecutionSession(); - GlobalValueSet RequestedGVs; - for (auto &Name : R->getRequestedSymbols()) { - if (Name == R->getInitializerSymbol()) - TSM.withModuleDo([&](Module &M) { - for (auto &GV : getStaticInitGVs(M)) - RequestedGVs.insert(&GV); - }); - else { - assert(Defs.count(Name) && "No definition for symbol"); - RequestedGVs.insert(Defs[Name]); - } - } - - /// Perform partitioning with the context lock held, since the partition - /// function is allowed to access the globals to compute the partition. - auto GVsToExtract = - TSM.withModuleDo([&](Module &M) { return Partition(RequestedGVs); }); - - // Take a 'None' partition to mean the whole module (as opposed to an empty - // partition, which means "materialize nothing"). Emit the whole module - // unmodified to the base layer. - if (GVsToExtract == std::nullopt) { - Defs.clear(); - BaseLayer.emit(std::move(R), std::move(TSM)); - return; - } - - // If the partition is empty, return the whole module to the symbol table. - if (GVsToExtract->empty()) { - if (auto Err = - R->replace(std::make_unique( - std::move(TSM), - MaterializationUnit::Interface(R->getSymbols(), - R->getInitializerSymbol()), - std::move(Defs), *this))) { - getExecutionSession().reportError(std::move(Err)); - R->failMaterialization(); - return; - } - return; - } - - // Ok -- we actually need to partition the symbols. Promote the symbol - // linkages/names, expand the partition to include any required symbols - // (i.e. symbols that can't be separated from our partition), and - // then extract the partition. - // - // FIXME: We apply this promotion once per partitioning. It's safe, but - // overkill. - auto ExtractedTSM = TSM.withModuleDo([&](Module &M) - -> Expected { - auto PromotedGlobals = PromoteSymbols(M); - if (!PromotedGlobals.empty()) { - - MangleAndInterner Mangle(ES, M.getDataLayout()); - SymbolFlagsMap SymbolFlags; - IRSymbolMapper::add(ES, *getManglingOptions(), PromotedGlobals, - SymbolFlags); - - if (auto Err = R->defineMaterializing(SymbolFlags)) - return std::move(Err); - } - - expandPartition(*GVsToExtract); - - // Submodule name is given by hashing the names of the globals. - std::string SubModuleName; - { - std::vector HashGVs; - HashGVs.reserve(GVsToExtract->size()); - for (const auto *GV : *GVsToExtract) - HashGVs.push_back(GV); - llvm::sort(HashGVs, [](const GlobalValue *LHS, const GlobalValue *RHS) { - return LHS->getName() < RHS->getName(); - }); - hash_code HC(0); - for (const auto *GV : HashGVs) { - assert(GV->hasName() && "All GVs to extract should be named by now"); - auto GVName = GV->getName(); - HC = hash_combine(HC, hash_combine_range(GVName.begin(), GVName.end())); - } - raw_string_ostream(SubModuleName) - << ".submodule." - << formatv(sizeof(size_t) == 8 ? "{0:x16}" : "{0:x8}", - static_cast(HC)) - << ".ll"; - } - - // Extract the requested partiton (plus any necessary aliases) and - // put the rest back into the impl dylib. - auto ShouldExtract = [&](const GlobalValue &GV) -> bool { - return GVsToExtract->count(&GV); - }; - - return extractSubModule(TSM, SubModuleName, ShouldExtract); - }); - - if (!ExtractedTSM) { - ES.reportError(ExtractedTSM.takeError()); - R->failMaterialization(); - return; - } - - if (auto Err = R->replace(std::make_unique( - ES, *getManglingOptions(), std::move(TSM), *this))) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } - BaseLayer.emit(std::move(R), std::move(*ExtractedTSM)); -} diff --git a/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp b/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp deleted file mode 100644 index 0e123b98201b..000000000000 --- a/llvm/lib/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.cpp +++ /dev/null @@ -1,182 +0,0 @@ -//===-- JITLinkRedirectableSymbolManager.cpp - JITLink redirection in Orc -===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h" -#include "llvm/ExecutionEngine/Orc/Core.h" - -#define DEBUG_TYPE "orc" - -using namespace llvm; -using namespace llvm::orc; - -void JITLinkRedirectableSymbolManager::emitRedirectableSymbols( - std::unique_ptr R, - const SymbolAddrMap &InitialDests) { - auto &ES = ObjLinkingLayer.getExecutionSession(); - std::unique_lock Lock(Mutex); - if (GetNumAvailableStubs() < InitialDests.size()) - if (auto Err = grow(InitialDests.size() - GetNumAvailableStubs())) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } - - JITDylib &TargetJD = R->getTargetJITDylib(); - SymbolMap NewSymbolDefs; - std::vector Symbols; - for (auto &[K, V] : InitialDests) { - StubHandle StubID = AvailableStubs.back(); - if (SymbolToStubs[&TargetJD].count(K)) { - ES.reportError(make_error( - "Tried to create duplicate redirectable symbols", - inconvertibleErrorCode())); - R->failMaterialization(); - return; - } - SymbolToStubs[&TargetJD][K] = StubID; - NewSymbolDefs[K] = JumpStubs[StubID]; - NewSymbolDefs[K].setFlags(V.getFlags()); - Symbols.push_back(K); - AvailableStubs.pop_back(); - } - - // FIXME: when this fails we can return stubs to the pool - if (auto Err = redirectInner(TargetJD, InitialDests)) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } - - if (auto Err = R->replace(absoluteSymbols(NewSymbolDefs))) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } - - auto Err = R->withResourceKeyDo([&](ResourceKey Key) { - TrackedResources[Key].insert(TrackedResources[Key].end(), Symbols.begin(), - Symbols.end()); - }); - if (Err) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } -} - -Error JITLinkRedirectableSymbolManager::redirect( - JITDylib &TargetJD, const SymbolAddrMap &NewDests) { - std::unique_lock Lock(Mutex); - return redirectInner(TargetJD, NewDests); -} - -Error JITLinkRedirectableSymbolManager::redirectInner( - JITDylib &TargetJD, const SymbolAddrMap &NewDests) { - std::vector PtrWrites; - for (auto &[K, V] : NewDests) { - if (!SymbolToStubs[&TargetJD].count(K)) - return make_error( - "Tried to redirect non-existent redirectalbe symbol", - inconvertibleErrorCode()); - StubHandle StubID = SymbolToStubs[&TargetJD].at(K); - PtrWrites.push_back({StubPointers[StubID].getAddress(), V.getAddress()}); - } - return ObjLinkingLayer.getExecutionSession() - .getExecutorProcessControl() - .getMemoryAccess() - .writePointers(PtrWrites); -} - -Error JITLinkRedirectableSymbolManager::grow(unsigned Need) { - unsigned OldSize = JumpStubs.size(); - unsigned NumNewStubs = alignTo(Need, StubBlockSize); - unsigned NewSize = OldSize + NumNewStubs; - - JumpStubs.resize(NewSize); - StubPointers.resize(NewSize); - AvailableStubs.reserve(NewSize); - - SymbolLookupSet LookupSymbols; - DenseMap NewDefsMap; - - auto &ES = ObjLinkingLayer.getExecutionSession(); - Triple TT = ES.getTargetTriple(); - auto G = std::make_unique( - "", TT, TT.isArch64Bit() ? 8 : 4, - TT.isLittleEndian() ? support::little : support::big, - jitlink::getGenericEdgeKindName); - auto &PointerSection = - G->createSection(StubPtrTableName, MemProt::Write | MemProt::Read); - auto &StubsSection = - G->createSection(JumpStubTableName, MemProt::Exec | MemProt::Read); - - // FIXME: We can batch the stubs into one block and use address to access them - for (size_t I = OldSize; I < NewSize; I++) { - auto Pointer = AnonymousPtrCreator(*G, PointerSection, nullptr, 0); - if (auto Err = Pointer.takeError()) - return Err; - - StringRef PtrSymName = StubPtrSymbolName(I); - Pointer->setName(PtrSymName); - Pointer->setScope(jitlink::Scope::Default); - LookupSymbols.add(ES.intern(PtrSymName)); - NewDefsMap[ES.intern(PtrSymName)] = &StubPointers[I]; - - auto Stub = PtrJumpStubCreator(*G, StubsSection, *Pointer); - if (auto Err = Stub.takeError()) - return Err; - - StringRef JumpStubSymName = JumpStubSymbolName(I); - Stub->setName(JumpStubSymName); - Stub->setScope(jitlink::Scope::Default); - LookupSymbols.add(ES.intern(JumpStubSymName)); - NewDefsMap[ES.intern(JumpStubSymName)] = &JumpStubs[I]; - } - - if (auto Err = ObjLinkingLayer.add(JD, std::move(G))) - return Err; - - auto LookupResult = ES.lookup(makeJITDylibSearchOrder(&JD), LookupSymbols); - if (auto Err = LookupResult.takeError()) - return Err; - - for (auto &[K, V] : *LookupResult) - *NewDefsMap.at(K) = V; - - for (size_t I = OldSize; I < NewSize; I++) - AvailableStubs.push_back(I); - - return Error::success(); -} - -Error JITLinkRedirectableSymbolManager::handleRemoveResources( - JITDylib &TargetJD, ResourceKey K) { - std::unique_lock Lock(Mutex); - for (auto &Symbol : TrackedResources[K]) { - if (!SymbolToStubs[&TargetJD].count(Symbol)) - return make_error( - "Tried to remove non-existent redirectable symbol", - inconvertibleErrorCode()); - AvailableStubs.push_back(SymbolToStubs[&TargetJD].at(Symbol)); - SymbolToStubs[&TargetJD].erase(Symbol); - if (SymbolToStubs[&TargetJD].empty()) - SymbolToStubs.erase(&TargetJD); - } - TrackedResources.erase(K); - - return Error::success(); -} - -void JITLinkRedirectableSymbolManager::handleTransferResources( - JITDylib &TargetJD, ResourceKey DstK, ResourceKey SrcK) { - std::unique_lock Lock(Mutex); - TrackedResources[DstK].insert(TrackedResources[DstK].end(), - TrackedResources[SrcK].begin(), - TrackedResources[SrcK].end()); - TrackedResources.erase(SrcK); -} diff --git a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp index ea43dfcf2ec0..568b2ececaa0 100644 --- a/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp +++ b/llvm/lib/ExecutionEngine/Orc/LLJIT.cpp @@ -1268,12 +1268,9 @@ LLLazyJIT::LLLazyJIT(LLLazyJITBuilderState &S, Error &Err) : LLJIT(S, Err) { return; } - // Create the IP Layer. - IPLayer = std::make_unique(*ES, *InitHelperTransformLayer); - // Create the COD layer. - CODLayer = std::make_unique(*ES, *IPLayer, *LCTMgr, - std::move(ISMBuilder)); + CODLayer = std::make_unique( + *ES, *InitHelperTransformLayer, *LCTMgr, std::move(ISMBuilder)); if (*S.SupportConcurrentCompilation) CODLayer->setCloneToNewContextOnEmit(true); diff --git a/llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp b/llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp deleted file mode 100644 index 2ec82f210e6f..000000000000 --- a/llvm/lib/ExecutionEngine/Orc/ReOptimizeLayer.cpp +++ /dev/null @@ -1,278 +0,0 @@ -#include "llvm/ExecutionEngine/Orc/ReOptimizeLayer.h" - -using namespace llvm; -using namespace orc; - -bool ReOptimizeLayer::ReOptMaterializationUnitState::tryStartReoptimize() { - std::unique_lock Lock(Mutex); - if (Reoptimizing) - return false; - - Reoptimizing = true; - return true; -} - -void ReOptimizeLayer::ReOptMaterializationUnitState::reoptimizeSucceeded() { - std::unique_lock Lock(Mutex); - assert(Reoptimizing && "Tried to mark unstarted reoptimization as done"); - Reoptimizing = false; - CurVersion++; -} - -void ReOptimizeLayer::ReOptMaterializationUnitState::reoptimizeFailed() { - std::unique_lock Lock(Mutex); - assert(Reoptimizing && "Tried to mark unstarted reoptimization as done"); - Reoptimizing = false; -} - -Error ReOptimizeLayer::reigsterRuntimeFunctions(JITDylib &PlatformJD) { - ExecutionSession::JITDispatchHandlerAssociationMap WFs; - using ReoptimizeSPSSig = shared::SPSError(uint64_t, uint32_t); - WFs[ES.intern("__orc_rt_reoptimize_tag")] = - ES.wrapAsyncWithSPS(this, - &ReOptimizeLayer::rt_reoptimize); - return ES.registerJITDispatchHandlers(PlatformJD, std::move(WFs)); -} - -void ReOptimizeLayer::emit(std::unique_ptr R, - ThreadSafeModule TSM) { - auto &JD = R->getTargetJITDylib(); - - bool HasNonCallable = false; - for (auto &KV : R->getSymbols()) { - auto &Flags = KV.second; - if (!Flags.isCallable()) - HasNonCallable = true; - } - - if (HasNonCallable) { - BaseLayer.emit(std::move(R), std::move(TSM)); - return; - } - - auto &MUState = createMaterializationUnitState(TSM); - - if (auto Err = R->withResourceKeyDo([&](ResourceKey Key) { - registerMaterializationUnitResource(Key, MUState); - })) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } - - if (auto Err = - ProfilerFunc(*this, MUState.getID(), MUState.getCurVersion(), TSM)) { - ES.reportError(std::move(Err)); - R->failMaterialization(); - return; - } - - auto InitialDests = - emitMUImplSymbols(MUState, MUState.getCurVersion(), JD, std::move(TSM)); - if (!InitialDests) { - ES.reportError(InitialDests.takeError()); - R->failMaterialization(); - return; - } - - RSManager.emitRedirectableSymbols(std::move(R), std::move(*InitialDests)); -} - -Error ReOptimizeLayer::reoptimizeIfCallFrequent(ReOptimizeLayer &Parent, - ReOptMaterializationUnitID MUID, - unsigned CurVersion, - ThreadSafeModule &TSM) { - return TSM.withModuleDo([&](Module &M) -> Error { - Type *I64Ty = Type::getInt64Ty(M.getContext()); - GlobalVariable *Counter = new GlobalVariable( - M, I64Ty, false, GlobalValue::InternalLinkage, - Constant::getNullValue(I64Ty), "__orc_reopt_counter"); - auto ArgBufferConst = createReoptimizeArgBuffer(M, MUID, CurVersion); - if (auto Err = ArgBufferConst.takeError()) - return Err; - GlobalVariable *ArgBuffer = - new GlobalVariable(M, (*ArgBufferConst)->getType(), true, - GlobalValue::InternalLinkage, (*ArgBufferConst)); - for (auto &F : M) { - if (F.isDeclaration()) - continue; - auto &BB = F.getEntryBlock(); - auto *IP = &*BB.getFirstInsertionPt(); - IRBuilder<> IRB(IP); - Value *Threshold = ConstantInt::get(I64Ty, CallCountThreshold, true); - Value *Cnt = IRB.CreateLoad(I64Ty, Counter); - // Use EQ to prevent further reoptimize calls. - Value *Cmp = IRB.CreateICmpEQ(Cnt, Threshold); - Value *Added = IRB.CreateAdd(Cnt, ConstantInt::get(I64Ty, 1)); - (void)IRB.CreateStore(Added, Counter); - Instruction *SplitTerminator = SplitBlockAndInsertIfThen(Cmp, IP, false); - createReoptimizeCall(M, *SplitTerminator, ArgBuffer); - } - return Error::success(); - }); -} - -Expected -ReOptimizeLayer::emitMUImplSymbols(ReOptMaterializationUnitState &MUState, - uint32_t Version, JITDylib &JD, - ThreadSafeModule TSM) { - DenseMap RenamedMap; - cantFail(TSM.withModuleDo([&](Module &M) -> Error { - MangleAndInterner Mangle(ES, M.getDataLayout()); - for (auto &F : M) - if (!F.isDeclaration()) { - std::string NewName = - (F.getName() + ".__def__." + Twine(Version)).str(); - RenamedMap[Mangle(F.getName())] = Mangle(NewName); - F.setName(NewName); - } - return Error::success(); - })); - - auto RT = JD.createResourceTracker(); - if (auto Err = - JD.define(std::make_unique( - BaseLayer, *getManglingOptions(), std::move(TSM)), - RT)) - return Err; - MUState.setResourceTracker(RT); - - SymbolLookupSet LookupSymbols; - for (auto [K, V] : RenamedMap) - LookupSymbols.add(V); - - auto ImplSymbols = - ES.lookup({{&JD, JITDylibLookupFlags::MatchAllSymbols}}, LookupSymbols, - LookupKind::Static, SymbolState::Resolved); - if (auto Err = ImplSymbols.takeError()) - return Err; - - SymbolMap Result; - for (auto [K, V] : RenamedMap) - Result[K] = (*ImplSymbols)[V]; - - return Result; -} - -void ReOptimizeLayer::rt_reoptimize(SendErrorFn SendResult, - ReOptMaterializationUnitID MUID, - uint32_t CurVersion) { - auto &MUState = getMaterializationUnitState(MUID); - if (CurVersion < MUState.getCurVersion() || !MUState.tryStartReoptimize()) { - SendResult(Error::success()); - return; - } - - ThreadSafeModule TSM = cloneToNewContext(MUState.getThreadSafeModule()); - auto OldRT = MUState.getResourceTracker(); - auto &JD = OldRT->getJITDylib(); - - if (auto Err = ReOptFunc(*this, MUID, CurVersion + 1, OldRT, TSM)) { - ES.reportError(std::move(Err)); - MUState.reoptimizeFailed(); - SendResult(Error::success()); - return; - } - - auto SymbolDests = - emitMUImplSymbols(MUState, CurVersion + 1, JD, std::move(TSM)); - if (!SymbolDests) { - ES.reportError(SymbolDests.takeError()); - MUState.reoptimizeFailed(); - SendResult(Error::success()); - return; - } - - if (auto Err = RSManager.redirect(JD, std::move(*SymbolDests))) { - ES.reportError(std::move(Err)); - MUState.reoptimizeFailed(); - SendResult(Error::success()); - return; - } - - MUState.reoptimizeSucceeded(); - SendResult(Error::success()); -} - -Expected ReOptimizeLayer::createReoptimizeArgBuffer( - Module &M, ReOptMaterializationUnitID MUID, uint32_t CurVersion) { - size_t ArgBufferSize = SPSReoptimizeArgList::size(MUID, CurVersion); - std::vector ArgBuffer(ArgBufferSize); - shared::SPSOutputBuffer OB(ArgBuffer.data(), ArgBuffer.size()); - if (!SPSReoptimizeArgList::serialize(OB, MUID, CurVersion)) - return make_error("Could not serealize args list", - inconvertibleErrorCode()); - return ConstantDataArray::get(M.getContext(), ArrayRef(ArgBuffer)); -} - -void ReOptimizeLayer::createReoptimizeCall(Module &M, Instruction &IP, - GlobalVariable *ArgBuffer) { - GlobalVariable *DispatchCtx = - M.getGlobalVariable("__orc_rt_jit_dispatch_ctx"); - if (!DispatchCtx) - DispatchCtx = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), - false, GlobalValue::ExternalLinkage, - nullptr, "__orc_rt_jit_dispatch_ctx"); - GlobalVariable *ReoptimizeTag = - M.getGlobalVariable("__orc_rt_reoptimize_tag"); - if (!ReoptimizeTag) - ReoptimizeTag = new GlobalVariable(M, Type::getInt8PtrTy(M.getContext()), - false, GlobalValue::ExternalLinkage, - nullptr, "__orc_rt_reoptimize_tag"); - Function *DispatchFunc = M.getFunction("__orc_rt_jit_dispatch"); - if (!DispatchFunc) { - std::vector Args = {Type::getInt8PtrTy(M.getContext()), - Type::getInt8PtrTy(M.getContext()), - Type::getInt8PtrTy(M.getContext()), - IntegerType::get(M.getContext(), 64)}; - FunctionType *FuncTy = - FunctionType::get(Type::getVoidTy(M.getContext()), Args, false); - DispatchFunc = Function::Create(FuncTy, GlobalValue::ExternalLinkage, - "__orc_rt_jit_dispatch", &M); - } - size_t ArgBufferSizeConst = - SPSReoptimizeArgList::size(ReOptMaterializationUnitID{}, uint32_t{}); - Constant *ArgBufferSize = ConstantInt::get( - IntegerType::get(M.getContext(), 64), ArgBufferSizeConst, false); - IRBuilder<> IRB(&IP); - (void)IRB.CreateCall(DispatchFunc, - {DispatchCtx, ReoptimizeTag, ArgBuffer, ArgBufferSize}); -} - -ReOptimizeLayer::ReOptMaterializationUnitState & -ReOptimizeLayer::createMaterializationUnitState(const ThreadSafeModule &TSM) { - std::unique_lock Lock(Mutex); - ReOptMaterializationUnitID MUID = NextID; - MUStates.emplace(MUID, - ReOptMaterializationUnitState(MUID, cloneToNewContext(TSM))); - ++NextID; - return MUStates.at(MUID); -} - -ReOptimizeLayer::ReOptMaterializationUnitState & -ReOptimizeLayer::getMaterializationUnitState(ReOptMaterializationUnitID MUID) { - std::unique_lock Lock(Mutex); - return MUStates.at(MUID); -} - -void ReOptimizeLayer::registerMaterializationUnitResource( - ResourceKey Key, ReOptMaterializationUnitState &State) { - std::unique_lock Lock(Mutex); - MUResources[Key].insert(State.getID()); -} - -Error ReOptimizeLayer::handleRemoveResources(JITDylib &JD, ResourceKey K) { - std::unique_lock Lock(Mutex); - for (auto MUID : MUResources[K]) - MUStates.erase(MUID); - - MUResources.erase(K); - return Error::success(); -} - -void ReOptimizeLayer::handleTransferResources(JITDylib &JD, ResourceKey DstK, - ResourceKey SrcK) { - std::unique_lock Lock(Mutex); - MUResources[DstK].insert(MUResources[SrcK].begin(), MUResources[SrcK].end()); - MUResources.erase(SrcK); -} diff --git a/llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp b/llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp deleted file mode 100644 index cbc77c503430..000000000000 --- a/llvm/lib/ExecutionEngine/Orc/RedirectionManager.cpp +++ /dev/null @@ -1,24 +0,0 @@ -//===---- RedirectionManager.cpp - Redirection manager interface in Orc ---===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "llvm/ExecutionEngine/Orc/RedirectionManager.h" - -#define DEBUG_TYPE "orc" - -using namespace llvm; -using namespace llvm::orc; - -void RedirectionManager::anchor() {} - -Error RedirectableSymbolManager::createRedirectableSymbols( - ResourceTrackerSP RT, const SymbolMap &InitialDests) { - auto &JD = RT->getJITDylib(); - return JD.define( - std::make_unique(*this, InitialDests), - RT); -} diff --git a/llvm/tools/lli/lli.cpp b/llvm/tools/lli/lli.cpp index 5c57b573b234..25f43a4bb681 100644 --- a/llvm/tools/lli/lli.cpp +++ b/llvm/tools/lli/lli.cpp @@ -30,7 +30,6 @@ #include "llvm/ExecutionEngine/Orc/EPCEHFrameRegistrar.h" #include "llvm/ExecutionEngine/Orc/EPCGenericRTDyldMemoryManager.h" #include "llvm/ExecutionEngine/Orc/ExecutionUtils.h" -#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" #include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" #include "llvm/ExecutionEngine/Orc/LLJIT.h" #include "llvm/ExecutionEngine/Orc/ObjectTransformLayer.h" @@ -1062,7 +1061,7 @@ int runOrcJIT(const char *ProgName) { } if (PerModuleLazy) - J->setPartitionFunction(orc::IRPartitionLayer::compileWholeModule); + J->setPartitionFunction(orc::CompileOnDemandLayer::compileWholeModule); auto IRDump = createIRDebugDumper(); J->getIRTransformLayer().setTransform( diff --git a/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt b/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt index cc85f8963628..8a6a26bba63c 100644 --- a/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt +++ b/llvm/unittests/ExecutionEngine/Orc/CMakeLists.txt @@ -42,8 +42,6 @@ add_llvm_unittest(OrcJITTests TaskDispatchTest.cpp ThreadSafeModuleTest.cpp WrapperFunctionUtilsTest.cpp - JITLinkRedirectionManagerTest.cpp - ReOptimizeLayerTest.cpp ) target_link_libraries(OrcJITTests PRIVATE diff --git a/llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp b/llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp deleted file mode 100644 index f063111354ac..000000000000 --- a/llvm/unittests/ExecutionEngine/Orc/JITLinkRedirectionManagerTest.cpp +++ /dev/null @@ -1,99 +0,0 @@ -#include "OrcTestCommon.h" -#include "llvm/ExecutionEngine/JITLink/JITLinkMemoryManager.h" -#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h" -#include "llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h" -#include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" -#include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" -#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h" -#include "llvm/Testing/Support/Error.h" -#include "gtest/gtest.h" - -using namespace llvm; -using namespace llvm::orc; -using namespace llvm::jitlink; - -static int initialTarget() { return 42; } -static int middleTarget() { return 13; } -static int finalTarget() { return 53; } - -class JITLinkRedirectionManagerTest : public testing::Test { -public: - ~JITLinkRedirectionManagerTest() { - if (ES) - if (auto Err = ES->endSession()) - ES->reportError(std::move(Err)); - } - -protected: - void SetUp() override { - auto JTMB = JITTargetMachineBuilder::detectHost(); - // Bail out if we can not detect the host. - if (!JTMB) { - consumeError(JTMB.takeError()); - GTEST_SKIP(); - } - - ES = std::make_unique( - std::make_unique( - nullptr, nullptr, JTMB->getTargetTriple().getTriple())); - JD = &ES->createBareJITDylib("main"); - ObjLinkingLayer = std::make_unique( - *ES, std::make_unique(4096)); - DL = std::make_unique( - cantFail(JTMB->getDefaultDataLayoutForTarget())); - } - JITDylib *JD{nullptr}; - std::unique_ptr ES; - std::unique_ptr ObjLinkingLayer; - std::unique_ptr DL; -}; - -TEST_F(JITLinkRedirectionManagerTest, BasicRedirectionOperation) { - auto RM = JITLinkRedirectableSymbolManager::Create(*ObjLinkingLayer, *JD); - // Bail out if we can not create - if (!RM) { - consumeError(RM.takeError()); - GTEST_SKIP(); - } - - auto DefineTarget = [&](StringRef TargetName, ExecutorAddr Addr) { - SymbolStringPtr Target = ES->intern(TargetName); - cantFail(JD->define(std::make_unique( - SymbolFlagsMap({{Target, JITSymbolFlags::Exported}}), - [&](std::unique_ptr R) -> void { - // No dependencies registered, can't fail. - cantFail( - R->notifyResolved({{Target, {Addr, JITSymbolFlags::Exported}}})); - cantFail(R->notifyEmitted()); - }))); - return cantFail(ES->lookup({JD}, TargetName)); - }; - - auto InitialTarget = - DefineTarget("InitialTarget", ExecutorAddr::fromPtr(&initialTarget)); - auto MiddleTarget = - DefineTarget("MiddleTarget", ExecutorAddr::fromPtr(&middleTarget)); - auto FinalTarget = - DefineTarget("FinalTarget", ExecutorAddr::fromPtr(&finalTarget)); - - auto RedirectableSymbol = ES->intern("RedirectableTarget"); - EXPECT_THAT_ERROR( - (*RM)->createRedirectableSymbols(JD->getDefaultResourceTracker(), - {{RedirectableSymbol, InitialTarget}}), - Succeeded()); - auto RTDef = cantFail(ES->lookup({JD}, RedirectableSymbol)); - - auto RTPtr = RTDef.getAddress().toPtr(); - auto Result = RTPtr(); - EXPECT_EQ(Result, 42) << "Failed to call initial target"; - - EXPECT_THAT_ERROR((*RM)->redirect(*JD, {{RedirectableSymbol, MiddleTarget}}), - Succeeded()); - Result = RTPtr(); - EXPECT_EQ(Result, 13) << "Failed to call middle redirected target"; - - EXPECT_THAT_ERROR((*RM)->redirect(*JD, {{RedirectableSymbol, FinalTarget}}), - Succeeded()); - Result = RTPtr(); - EXPECT_EQ(Result, 53) << "Failed to call redirected target"; -} diff --git a/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp b/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp deleted file mode 100644 index 1cecdf700976..000000000000 --- a/llvm/unittests/ExecutionEngine/Orc/ReOptimizeLayerTest.cpp +++ /dev/null @@ -1,150 +0,0 @@ -#include "llvm/ExecutionEngine/Orc/ReOptimizeLayer.h" -#include "OrcTestCommon.h" -#include "llvm/ExecutionEngine/JITLink/JITLinkMemoryManager.h" -#include "llvm/ExecutionEngine/Orc/CompileUtils.h" -#include "llvm/ExecutionEngine/Orc/ExecutorProcessControl.h" -#include "llvm/ExecutionEngine/Orc/IRCompileLayer.h" -#include "llvm/ExecutionEngine/Orc/IRPartitionLayer.h" -#include "llvm/ExecutionEngine/Orc/IRTransformLayer.h" -#include "llvm/ExecutionEngine/Orc/JITLinkRedirectableSymbolManager.h" -#include "llvm/ExecutionEngine/Orc/JITTargetMachineBuilder.h" -#include "llvm/ExecutionEngine/Orc/ObjectLinkingLayer.h" -#include "llvm/ExecutionEngine/Orc/ObjectTransformLayer.h" -#include "llvm/ExecutionEngine/Orc/Shared/ExecutorAddress.h" -#include "llvm/IR/IRBuilder.h" -#include "llvm/Support/CodeGen.h" -#include "llvm/TargetParser/Host.h" -#include "llvm/Testing/Support/Error.h" -#include "gtest/gtest.h" - -using namespace llvm; -using namespace llvm::orc; -using namespace llvm::jitlink; - -class ReOptimizeLayerTest : public testing::Test { -public: - ~ReOptimizeLayerTest() { - if (ES) - if (auto Err = ES->endSession()) - ES->reportError(std::move(Err)); - } - -protected: - void SetUp() override { - auto JTMB = JITTargetMachineBuilder::detectHost(); - // Bail out if we can not detect the host. - if (!JTMB) { - consumeError(JTMB.takeError()); - GTEST_SKIP(); - } - - auto EPC = SelfExecutorProcessControl::Create(); - if (!EPC) { - consumeError(EPC.takeError()); - GTEST_SKIP(); - } - ES = std::make_unique(std::move(*EPC)); - JD = &ES->createBareJITDylib("main"); - ObjLinkingLayer = std::make_unique( - *ES, std::make_unique(4096)); - DL = std::make_unique( - cantFail(JTMB->getDefaultDataLayoutForTarget())); - - auto TM = JTMB->createTargetMachine(); - if (!TM) { - consumeError(TM.takeError()); - GTEST_SKIP(); - } - auto CompileFunction = - std::make_unique(std::move(*TM)); - CompileLayer = std::make_unique(*ES, *ObjLinkingLayer, - std::move(CompileFunction)); - } - - Error addIRModule(ResourceTrackerSP RT, ThreadSafeModule TSM) { - assert(TSM && "Can not add null module"); - - TSM.withModuleDo([&](Module &M) { M.setDataLayout(*DL); }); - - return ROLayer->add(std::move(RT), std::move(TSM)); - } - - JITDylib *JD{nullptr}; - std::unique_ptr ES; - std::unique_ptr ObjLinkingLayer; - std::unique_ptr CompileLayer; - std::unique_ptr ROLayer; - std::unique_ptr DL; -}; - -static Function *createRetFunction(Module *M, StringRef Name, - uint32_t ReturnCode) { - Function *Result = Function::Create( - FunctionType::get(Type::getInt32Ty(M->getContext()), {}, false), - GlobalValue::ExternalLinkage, Name, M); - - BasicBlock *BB = BasicBlock::Create(M->getContext(), Name, Result); - IRBuilder<> Builder(M->getContext()); - Builder.SetInsertPoint(BB); - - Value *RetValue = ConstantInt::get(M->getContext(), APInt(32, ReturnCode)); - Builder.CreateRet(RetValue); - return Result; -} - -TEST_F(ReOptimizeLayerTest, BasicReOptimization) { - auto &EPC = ES->getExecutorProcessControl(); - EXPECT_THAT_ERROR(JD->define(absoluteSymbols( - {{ES->intern("__orc_rt_jit_dispatch"), - {EPC.getJITDispatchInfo().JITDispatchFunction, - JITSymbolFlags::Exported}}, - {ES->intern("__orc_rt_jit_dispatch_ctx"), - {EPC.getJITDispatchInfo().JITDispatchContext, - JITSymbolFlags::Exported}}, - {ES->intern("__orc_rt_reoptimize_tag"), - {ExecutorAddr(), JITSymbolFlags::Exported}}})), - Succeeded()); - - auto RM = JITLinkRedirectableSymbolManager::Create(*ObjLinkingLayer, *JD); - EXPECT_THAT_ERROR(RM.takeError(), Succeeded()); - - ROLayer = std::make_unique(*ES, *CompileLayer, **RM); - ROLayer->setReoptimizeFunc( - [&](ReOptimizeLayer &Parent, - ReOptimizeLayer::ReOptMaterializationUnitID MUID, unsigned CurVerison, - ResourceTrackerSP OldRT, ThreadSafeModule &TSM) { - TSM.withModuleDo([&](Module &M) { - for (auto &F : M) { - if (F.isDeclaration()) - continue; - for (auto &B : F) { - for (auto &I : B) { - if (ReturnInst *Ret = dyn_cast(&I)) { - Value *RetValue = - ConstantInt::get(M.getContext(), APInt(32, 53)); - Ret->setOperand(0, RetValue); - } - } - } - } - }); - return Error::success(); - }); - EXPECT_THAT_ERROR(ROLayer->reigsterRuntimeFunctions(*JD), Succeeded()); - - ThreadSafeContext Ctx(std::make_unique()); - auto M = std::make_unique("
", *Ctx.getContext()); - M->setTargetTriple(sys::getProcessTriple()); - - (void)createRetFunction(M.get(), "main", 42); - - EXPECT_THAT_ERROR(addIRModule(JD->getDefaultResourceTracker(), - ThreadSafeModule(std::move(M), std::move(Ctx))), - Succeeded()); - - auto Result = cantFail(ES->lookup({JD}, "main")); - auto FuncPtr = Result.getAddress().toPtr(); - for (size_t I = 0; I <= ReOptimizeLayer::CallCountThreshold; I++) - EXPECT_EQ(FuncPtr(), 42); - EXPECT_EQ(FuncPtr(), 53); -} -- GitLab From 0d56d88d9fc48f1b97a641422ee23cc6eabcd6ef Mon Sep 17 00:00:00 2001 From: Pavel Labath Date: Fri, 26 Apr 2024 07:13:33 +0000 Subject: [PATCH 014/301] [lldb] Update eh-frame-dwarf-unwind-abort.test for a change in llvm assembler The jump instruction now gets encoded as a near jump, which changes some offsets. --- lldb/test/Shell/Unwind/eh-frame-dwarf-unwind-abort.test | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/lldb/test/Shell/Unwind/eh-frame-dwarf-unwind-abort.test b/lldb/test/Shell/Unwind/eh-frame-dwarf-unwind-abort.test index 477a656a711f..d5e66ca5e263 100644 --- a/lldb/test/Shell/Unwind/eh-frame-dwarf-unwind-abort.test +++ b/lldb/test/Shell/Unwind/eh-frame-dwarf-unwind-abort.test @@ -9,12 +9,12 @@ process launch # CHECK: stop reason = signal SIGTRAP thread backtrace -# CHECK: frame #0: {{.*}}`asm_main + 23 +# CHECK: frame #0: {{.*}}`asm_main + 19 # CHECK: frame #1: {{.*}}`main + {{.*}} target modules show-unwind -n asm_main # CHECK: eh_frame UnwindPlan: # CHECK: row[0]: 0: CFA=rsp +8 => rip=[CFA-8] -# CHECK: row[1]: 14: CFA=rsp+16 => rbp=[CFA-16] rip=[CFA-8] -# CHECK: row[2]: 17: CFA=rbp+16 => rbp=[CFA-16] rip=[CFA-8] -# CHECK: row[3]: 22: CFA=rsp +8 => rip=[CFA-8] +# CHECK: row[1]: 10: CFA=rsp+16 => rbp=[CFA-16] rip=[CFA-8] +# CHECK: row[2]: 13: CFA=rbp+16 => rbp=[CFA-16] rip=[CFA-8] +# CHECK: row[3]: 18: CFA=rsp +8 => rip=[CFA-8] -- GitLab From 2308d4697e0b3b0cfd905e2b025ea905ee763fbe Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Thu, 25 Apr 2024 07:39:41 +0200 Subject: [PATCH 015/301] [clang][Interp][NFC] Rename locals and add assertions to virtual casts --- clang/lib/AST/Interp/Interp.h | 9 ++++++--- clang/lib/AST/Interp/Opcodes.td | 2 +- 2 files changed, 7 insertions(+), 4 deletions(-) diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 9283f697c007..0e9f287cd221 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1355,12 +1355,14 @@ inline bool VirtBaseHelper(InterpState &S, CodePtr OpPC, const RecordDecl *Decl, while (Base.isBaseClass()) Base = Base.getBase(); - auto *Field = Base.getRecord()->getVirtualBase(Decl); - S.Stk.push(Base.atField(Field->Offset)); + const Record::Base *VirtBase = Base.getRecord()->getVirtualBase(Decl); + S.Stk.push(Base.atField(VirtBase->Offset)); return true; } -inline bool GetPtrVirtBase(InterpState &S, CodePtr OpPC, const RecordDecl *D) { +inline bool GetPtrVirtBasePop(InterpState &S, CodePtr OpPC, + const RecordDecl *D) { + assert(D); const Pointer &Ptr = S.Stk.pop(); if (!CheckNull(S, OpPC, Ptr, CSK_Base)) return false; @@ -1369,6 +1371,7 @@ inline bool GetPtrVirtBase(InterpState &S, CodePtr OpPC, const RecordDecl *D) { inline bool GetPtrThisVirtBase(InterpState &S, CodePtr OpPC, const RecordDecl *D) { + assert(D); if (S.checkingPotentialConstantExpression()) return false; const Pointer &This = S.Current->getThis(); diff --git a/clang/lib/AST/Interp/Opcodes.td b/clang/lib/AST/Interp/Opcodes.td index 742785b28eb4..2a97b978b523 100644 --- a/clang/lib/AST/Interp/Opcodes.td +++ b/clang/lib/AST/Interp/Opcodes.td @@ -336,7 +336,7 @@ def GetPtrDerivedPop : Opcode { } // [Pointer] -> [Pointer] -def GetPtrVirtBase : Opcode { +def GetPtrVirtBasePop : Opcode { // RecordDecl of base class. let Args = [ArgRecordDecl]; } -- GitLab From 8979644bbd82b85ef40c17165b37769980455b75 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Thu, 25 Apr 2024 07:45:16 +0200 Subject: [PATCH 016/301] [clang][Interp][NFC] Add InlineDescriptor::dump() --- clang/lib/AST/Interp/Descriptor.h | 3 +++ clang/lib/AST/Interp/Disasm.cpp | 19 +++++++++++++++++++ 2 files changed, 22 insertions(+) diff --git a/clang/lib/AST/Interp/Descriptor.h b/clang/lib/AST/Interp/Descriptor.h index c386fc8ac7b0..cd20495c259c 100644 --- a/clang/lib/AST/Interp/Descriptor.h +++ b/clang/lib/AST/Interp/Descriptor.h @@ -82,6 +82,9 @@ struct InlineDescriptor { InlineDescriptor(const Descriptor *D) : Offset(sizeof(InlineDescriptor)), IsConst(false), IsInitialized(false), IsBase(false), IsActive(false), IsFieldMutable(false), Desc(D) {} + + void dump() const { dump(llvm::errs()); } + void dump(llvm::raw_ostream &OS) const; }; /// Describes a memory block created by an allocation site. diff --git a/clang/lib/AST/Interp/Disasm.cpp b/clang/lib/AST/Interp/Disasm.cpp index d127f33223e8..e847a237660d 100644 --- a/clang/lib/AST/Interp/Disasm.cpp +++ b/clang/lib/AST/Interp/Disasm.cpp @@ -208,6 +208,25 @@ LLVM_DUMP_METHOD void Descriptor::dump(llvm::raw_ostream &OS) const { OS << " dummy"; } +LLVM_DUMP_METHOD void InlineDescriptor::dump(llvm::raw_ostream &OS) const { + { + ColorScope SC(OS, true, {llvm::raw_ostream::BLUE, true}); + OS << "InlineDescriptor " << (const void *)this << "\n"; + } + OS << "Offset: " << Offset << "\n"; + OS << "IsConst: " << IsConst << "\n"; + OS << "IsInitialized: " << IsInitialized << "\n"; + OS << "IsBase: " << IsBase << "\n"; + OS << "IsActive: " << IsActive << "\n"; + OS << "IsFieldMutable: " << IsFieldMutable << "\n"; + OS << "Desc: "; + if (Desc) + Desc->dump(OS); + else + OS << "nullptr"; + OS << "\n"; +} + LLVM_DUMP_METHOD void InterpFrame::dump(llvm::raw_ostream &OS, unsigned Indent) const { unsigned Spaces = Indent * 2; -- GitLab From c70f05831663915f1c66d3767803ff74c08e79ee Mon Sep 17 00:00:00 2001 From: martinboehme Date: Fri, 26 Apr 2024 09:30:07 +0200 Subject: [PATCH 017/301] [clang][dataflow] Fix crash when `ConstantExpr` is used in conditional operator. (#90112) `ConstantExpr` does not appear as a `CFGStmt` in the CFG, so `StmtToEnvMap::getEnvironment()` was not finding an entry for it in the map, causing a crash when we tried to access the iterator resulting from the map lookup. The fix is to make `ignoreCFGOmittedNodes()` ignore `ConstantExpr`, but in addition, I'm hardening `StmtToEnvMap::getEnvironment()` to make sure release builds don't crash in similar situations in the future. --- clang/lib/Analysis/FlowSensitive/ASTOps.cpp | 16 +++++++--- clang/lib/Analysis/FlowSensitive/Transfer.cpp | 6 +++- .../Analysis/FlowSensitive/TransferTest.cpp | 32 +++++++++++++++++++ 3 files changed, 49 insertions(+), 5 deletions(-) diff --git a/clang/lib/Analysis/FlowSensitive/ASTOps.cpp b/clang/lib/Analysis/FlowSensitive/ASTOps.cpp index 619bf772bba5..bd1676583ecc 100644 --- a/clang/lib/Analysis/FlowSensitive/ASTOps.cpp +++ b/clang/lib/Analysis/FlowSensitive/ASTOps.cpp @@ -33,12 +33,20 @@ namespace clang::dataflow { const Expr &ignoreCFGOmittedNodes(const Expr &E) { const Expr *Current = &E; - if (auto *EWC = dyn_cast(Current)) { - Current = EWC->getSubExpr(); + const Expr *Last = nullptr; + while (Current != Last) { + Last = Current; + if (auto *EWC = dyn_cast(Current)) { + Current = EWC->getSubExpr(); + assert(Current != nullptr); + } + if (auto *CE = dyn_cast(Current)) { + Current = CE->getSubExpr(); + assert(Current != nullptr); + } + Current = Current->IgnoreParens(); assert(Current != nullptr); } - Current = Current->IgnoreParens(); - assert(Current != nullptr); return *Current; } diff --git a/clang/lib/Analysis/FlowSensitive/Transfer.cpp b/clang/lib/Analysis/FlowSensitive/Transfer.cpp index 43fdfa5abcbb..fd224aeb79b1 100644 --- a/clang/lib/Analysis/FlowSensitive/Transfer.cpp +++ b/clang/lib/Analysis/FlowSensitive/Transfer.cpp @@ -41,7 +41,11 @@ namespace dataflow { const Environment *StmtToEnvMap::getEnvironment(const Stmt &S) const { auto BlockIt = ACFG.getStmtToBlock().find(&ignoreCFGOmittedNodes(S)); - assert(BlockIt != ACFG.getStmtToBlock().end()); + if (BlockIt == ACFG.getStmtToBlock().end()) { + assert(false); + // Return null to avoid dereferencing the end iterator in non-assert builds. + return nullptr; + } if (!ACFG.isBlockReachable(*BlockIt->getSecond())) return nullptr; if (BlockIt->getSecond()->getBlockID() == CurBlockID) diff --git a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp index d204700919d3..301bec32c0cf 100644 --- a/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp +++ b/clang/unittests/Analysis/FlowSensitive/TransferTest.cpp @@ -5357,6 +5357,38 @@ TEST(TransferTest, ConditionalOperatorLocation) { }); } +TEST(TransferTest, ConditionalOperatorOnConstantExpr) { + // This is a regression test: We used to crash when a `ConstantExpr` was used + // in the branches of a conditional operator. + std::string Code = R"cc( + consteval bool identity(bool B) { return B; } + void target(bool Cond) { + bool JoinTrueTrue = Cond ? identity(true) : identity(true); + bool JoinTrueFalse = Cond ? identity(true) : identity(false); + // [[p]] + } + )cc"; + runDataflow( + Code, + [](const llvm::StringMap> &Results, + ASTContext &ASTCtx) { + Environment Env = getEnvironmentAtAnnotation(Results, "p").fork(); + + auto &JoinTrueTrue = + getValueForDecl(ASTCtx, Env, "JoinTrueTrue"); + // FIXME: This test documents the current behavior, namely that we + // don't actually use the constant result of the `ConstantExpr` and + // instead treat it like a normal function call. + EXPECT_EQ(JoinTrueTrue.formula().kind(), Formula::Kind::AtomRef); + // EXPECT_TRUE(JoinTrueTrue.formula().literal()); + + auto &JoinTrueFalse = + getValueForDecl(ASTCtx, Env, "JoinTrueFalse"); + EXPECT_EQ(JoinTrueFalse.formula().kind(), Formula::Kind::AtomRef); + }, + LangStandard::lang_cxx20); +} + TEST(TransferTest, IfStmtBranchExtendsFlowCondition) { std::string Code = R"( void target(bool Foo) { -- GitLab From 2b2c66c00f968b439f159bf200f801da9afaf22f Mon Sep 17 00:00:00 2001 From: "long.chen" Date: Fri, 26 Apr 2024 16:44:55 +0900 Subject: [PATCH 018/301] [NFC][llvm] refine generated code format (#90172) --- llvm/utils/TableGen/DAGISelMatcherEmitter.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp index dcecac4380ce..ff508d648733 100644 --- a/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp +++ b/llvm/utils/TableGen/DAGISelMatcherEmitter.cpp @@ -1352,7 +1352,7 @@ void llvm::EmitMatcherTable(Matcher *TheMatcher, const CodeGenDAGPatterns &CGP, MatcherEmitter.EmitHistogram(TheMatcher, OS); OS << " #undef TARGET_VAL\n"; - OS << " SelectCodeCommon(N, MatcherTable,sizeof(MatcherTable));\n"; + OS << " SelectCodeCommon(N, MatcherTable, sizeof(MatcherTable));\n"; OS << "}\n"; EndEmitFunction(OS); -- GitLab From 88a733f8e6ca42de8c7818cc404e38cbc8f497c9 Mon Sep 17 00:00:00 2001 From: bd1976bris Date: Fri, 26 Apr 2024 09:13:17 +0100 Subject: [PATCH 019/301] [llvm-objcopy][docs] Use "Mark" rather than "Make" in the objcopy docs for consistency (#90080) llvm-objcopy --help uses the term "Mark" rather than "Make". e.g. "Mark all symbols local" Change llvm/docs to align. --- llvm/docs/CommandGuide/llvm-objcopy.rst | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/docs/CommandGuide/llvm-objcopy.rst b/llvm/docs/CommandGuide/llvm-objcopy.rst index 57d6280d57c8..a62acfc8fdcd 100644 --- a/llvm/docs/CommandGuide/llvm-objcopy.rst +++ b/llvm/docs/CommandGuide/llvm-objcopy.rst @@ -366,12 +366,12 @@ them. .. option:: --keep-global-symbol , -G - Make all symbols local in the output, except for symbols with the name + Mark all symbols local in the output, except for symbols with the name ````. Can be specified multiple times to ignore multiple symbols. .. option:: --keep-global-symbols - Make all symbols local in the output, except for symbols named in the file + Mark all symbols local in the output, except for symbols named in the file ````. In the file, each line represents a single symbol, with leading and trailing whitespace ignored, as is anything following a '#'. Can be specified multiple times to read names from multiple files. @@ -395,7 +395,7 @@ them. .. option:: --localize-hidden - Make all symbols with hidden or internal visibility local in the output. + Mark all symbols with hidden or internal visibility local in the output. .. option:: --localize-symbol , -L -- GitLab From c2db883ff4340b2f70154eca04e3adbc8e0d082c Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Thu, 25 Apr 2024 07:46:17 +0200 Subject: [PATCH 020/301] [clang][Interp][NFC] Print virtual bases in Record::dump() --- clang/lib/AST/Interp/Disasm.cpp | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/clang/lib/AST/Interp/Disasm.cpp b/clang/lib/AST/Interp/Disasm.cpp index e847a237660d..01cc88ea9a84 100644 --- a/clang/lib/AST/Interp/Disasm.cpp +++ b/clang/lib/AST/Interp/Disasm.cpp @@ -270,8 +270,6 @@ LLVM_DUMP_METHOD void Record::dump(llvm::raw_ostream &OS, unsigned Indentation, ++I; } - // FIXME: Virtual bases. - I = 0; for (const Record::Field &F : fields()) { OS.indent(Indent) << "- Field " << I << ": "; @@ -282,6 +280,14 @@ LLVM_DUMP_METHOD void Record::dump(llvm::raw_ostream &OS, unsigned Indentation, OS << ". Offset " << (Offset + F.Offset) << "\n"; ++I; } + + I = 0; + for (const Record::Base &B : virtual_bases()) { + OS.indent(Indent) << "- Virtual Base " << I << ". Offset " + << (Offset + B.Offset) << "\n"; + B.R->dump(OS, Indentation + 1, Offset + B.Offset); + ++I; + } } LLVM_DUMP_METHOD void Block::dump(llvm::raw_ostream &OS) const { -- GitLab From bc8a4ea11070d06374b403cd09b771a99cc6ba1a Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Thu, 25 Apr 2024 07:49:04 +0200 Subject: [PATCH 021/301] [clang][Interp][NFC] Move collectBaseOffset() to Context We will need this outside of ByteCodeExprGen later. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 46 ++++++++---------------- clang/lib/AST/Interp/ByteCodeExprGen.h | 4 +-- clang/lib/AST/Interp/Context.cpp | 33 +++++++++++++++++ clang/lib/AST/Interp/Context.h | 3 ++ 4 files changed, 52 insertions(+), 34 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 8cd0c198d9a8..bbd2771d3712 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -110,8 +110,8 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { if (!this->visit(SubExpr)) return false; - unsigned DerivedOffset = collectBaseOffset(getRecordTy(CE->getType()), - getRecordTy(SubExpr->getType())); + unsigned DerivedOffset = + collectBaseOffset(CE->getType(), SubExpr->getType()); return this->emitGetPtrBasePop(DerivedOffset, CE); } @@ -120,8 +120,8 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { if (!this->visit(SubExpr)) return false; - unsigned DerivedOffset = collectBaseOffset(getRecordTy(SubExpr->getType()), - getRecordTy(CE->getType())); + unsigned DerivedOffset = + collectBaseOffset(SubExpr->getType(), CE->getType()); return this->emitGetPtrDerivedPop(DerivedOffset, CE); } @@ -3529,35 +3529,17 @@ void ByteCodeExprGen::emitCleanup() { template unsigned -ByteCodeExprGen::collectBaseOffset(const RecordType *BaseType, - const RecordType *DerivedType) { - assert(BaseType); - assert(DerivedType); - const auto *FinalDecl = cast(BaseType->getDecl()); - const RecordDecl *CurDecl = DerivedType->getDecl(); - const Record *CurRecord = getRecord(CurDecl); - assert(CurDecl && FinalDecl); - - unsigned OffsetSum = 0; - for (;;) { - assert(CurRecord->getNumBases() > 0); - // One level up - for (const Record::Base &B : CurRecord->bases()) { - const auto *BaseDecl = cast(B.Decl); - - if (BaseDecl == FinalDecl || BaseDecl->isDerivedFrom(FinalDecl)) { - OffsetSum += B.Offset; - CurRecord = B.R; - CurDecl = BaseDecl; - break; - } - } - if (CurDecl == FinalDecl) - break; - } +ByteCodeExprGen::collectBaseOffset(const QualType BaseType, + const QualType DerivedType) { + const auto extractRecordDecl = [](QualType Ty) -> const CXXRecordDecl * { + if (const auto *PT = dyn_cast(Ty)) + return PT->getPointeeType()->getAsCXXRecordDecl(); + return Ty->getAsCXXRecordDecl(); + }; + const CXXRecordDecl *BaseDecl = extractRecordDecl(BaseType); + const CXXRecordDecl *DerivedDecl = extractRecordDecl(DerivedType); - assert(OffsetSum > 0); - return OffsetSum; + return Ctx.collectBaseOffset(BaseDecl, DerivedDecl); } /// Emit casts from a PrimType to another PrimType. diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.h b/clang/lib/AST/Interp/ByteCodeExprGen.h index 7e9dc8631fc0..4a57f76ae5b3 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.h +++ b/clang/lib/AST/Interp/ByteCodeExprGen.h @@ -283,8 +283,8 @@ private: bool emitRecordDestruction(const Record *R); bool emitDestruction(const Descriptor *Desc); - unsigned collectBaseOffset(const RecordType *BaseType, - const RecordType *DerivedType); + unsigned collectBaseOffset(const QualType BaseType, + const QualType DerivedType); protected: /// Variable to storage mapping. diff --git a/clang/lib/AST/Interp/Context.cpp b/clang/lib/AST/Interp/Context.cpp index 274178837bf0..d51a57e5e92e 100644 --- a/clang/lib/AST/Interp/Context.cpp +++ b/clang/lib/AST/Interp/Context.cpp @@ -262,3 +262,36 @@ const Function *Context::getOrCreateFunction(const FunctionDecl *FD) { return Func; } + +unsigned Context::collectBaseOffset(const RecordDecl *BaseDecl, + const RecordDecl *DerivedDecl) const { + assert(BaseDecl); + assert(DerivedDecl); + const auto *FinalDecl = cast(BaseDecl); + const RecordDecl *CurDecl = DerivedDecl; + const Record *CurRecord = P->getOrCreateRecord(CurDecl); + assert(CurDecl && FinalDecl); + + unsigned OffsetSum = 0; + for (;;) { + assert(CurRecord->getNumBases() > 0); + // One level up + for (const Record::Base &B : CurRecord->bases()) { + const auto *BaseDecl = cast(B.Decl); + + if (BaseDecl == FinalDecl || BaseDecl->isDerivedFrom(FinalDecl)) { + OffsetSum += B.Offset; + CurRecord = B.R; + CurDecl = BaseDecl; + break; + } + } + if (CurDecl == FinalDecl) + break; + + // break; + } + + assert(OffsetSum > 0); + return OffsetSum; +} diff --git a/clang/lib/AST/Interp/Context.h b/clang/lib/AST/Interp/Context.h index 23c439ad8912..360e9499d084 100644 --- a/clang/lib/AST/Interp/Context.h +++ b/clang/lib/AST/Interp/Context.h @@ -104,6 +104,9 @@ public: /// Returns the program. This is only needed for unittests. Program &getProgram() const { return *P.get(); } + unsigned collectBaseOffset(const RecordDecl *BaseDecl, + const RecordDecl *DerivedDecl) const; + private: /// Runs a function. bool Run(State &Parent, const Function *Func, APValue &Result); -- GitLab From 22da5a6e34ed6146752b24d9156a678b50fddaef Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Fri, 26 Apr 2024 16:25:33 +0800 Subject: [PATCH 022/301] [IRCE] Skip icmp ptr in `InductiveRangeCheck::parseRangeCheckICmp` (#89967) Fixes https://github.com/llvm/llvm-project/issues/89959. --- .../Scalar/InductiveRangeCheckElimination.cpp | 3 ++ llvm/test/Transforms/IRCE/pr89959.ll | 33 +++++++++++++++++++ 2 files changed, 36 insertions(+) create mode 100644 llvm/test/Transforms/IRCE/pr89959.ll diff --git a/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp b/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp index 9df28747570c..104e8ceb7967 100644 --- a/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp +++ b/llvm/lib/Transforms/Scalar/InductiveRangeCheckElimination.cpp @@ -279,6 +279,9 @@ bool InductiveRangeCheck::parseRangeCheckICmp(Loop *L, ICmpInst *ICI, Value *LHS = ICI->getOperand(0); Value *RHS = ICI->getOperand(1); + if (!LHS->getType()->isIntegerTy()) + return false; + // Canonicalize to the `Index Pred Invariant` comparison if (IsLoopInvariant(LHS)) { std::swap(LHS, RHS); diff --git a/llvm/test/Transforms/IRCE/pr89959.ll b/llvm/test/Transforms/IRCE/pr89959.ll new file mode 100644 index 000000000000..dc7c0dfbc57a --- /dev/null +++ b/llvm/test/Transforms/IRCE/pr89959.ll @@ -0,0 +1,33 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=irce -S < %s 2>&1 | FileCheck %s + +; Make sure we don't crash. +define void @pr89959() { +; CHECK-LABEL: define void @pr89959() { +; CHECK-NEXT: top: +; CHECK-NEXT: br label [[L3:%.*]] +; CHECK: L3: +; CHECK-NEXT: [[VALUE_PHI:%.*]] = phi ptr [ null, [[TOP:%.*]] ], [ [[TMP0:%.*]], [[L13:%.*]] ] +; CHECK-NEXT: [[TMP0]] = getelementptr i8, ptr [[VALUE_PHI]], i64 8 +; CHECK-NEXT: [[DOTNOT:%.*]] = icmp ule ptr [[VALUE_PHI]], null +; CHECK-NEXT: br i1 [[DOTNOT]], label [[L13]], label [[L15:%.*]] +; CHECK: L13: +; CHECK-NEXT: br label [[L3]] +; CHECK: L15: +; CHECK-NEXT: ret void +; +top: + br label %L3 + +L3: + %value_phi = phi ptr [ null, %top ], [ %0, %L13 ] + %0 = getelementptr i8, ptr %value_phi, i64 8 + %.not = icmp ule ptr %value_phi, null + br i1 %.not, label %L13, label %L15 + +L13: + br label %L3 + +L15: + ret void +} -- GitLab From c4b28bf903644c8c540310594983eba741d45abe Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 26 Apr 2024 09:33:29 +0100 Subject: [PATCH 023/301] [lldb][Docs] Link from platform doc to extensions doc (#90029) So we aren't describing the same packets twice. Basically turning the platform doc into a list of cross links. qLaunchSuccess was missing a description so I added one. --- lldb/docs/resources/lldbgdbremote.md | 227 ++++++++- lldb/docs/resources/lldbplatformpackets.md | 513 ++------------------- 2 files changed, 265 insertions(+), 475 deletions(-) diff --git a/lldb/docs/resources/lldbgdbremote.md b/lldb/docs/resources/lldbgdbremote.md index cbe5c766d61e..9a1032818af0 100644 --- a/lldb/docs/resources/lldbgdbremote.md +++ b/lldb/docs/resources/lldbgdbremote.md @@ -130,6 +130,21 @@ The above packet helps when you have remote debugging abilities where you could launch a process on a remote host, this isn't needed for bare board debugging. +## qLaunchSuccess + +### Brief + +Check whether launching a process with the `A` packet succeeded. + +### Description + +Returns the status of the last attempt to launch a process. +Either `OK` if no error ocurred, or `E` followed by a string +describing the error. + +### Priority To Implement + +High, launching processes is a key part of LLDB's platform mode. ## QEnvironment:NAME=VALUE @@ -263,6 +278,20 @@ QSetWorkingDir: ``` This packet must be sent _prior_ to sending a "A" packet. +## qGetWorkingDir + +### Brief + +Get the current working directory of the platform stub in +ASCII hex encoding. + +### Example + +``` +receive: qGetWorkingDir +send: 2f4170706c65496e7465726e616c2f6c6c64622f73657474696e67732f342f5465737453657474696e67732e746573745f646973617373656d626c65725f73657474696e6773 +``` + ## QSetDisableASLR:\ ### Brief @@ -1029,13 +1058,17 @@ a remote host. Request: `qPlatform_mkdir:,` +The request packet has the fields: + 1. mode bits in base 16 + 2. file path in ascii-hex encoding + Reply: * `F` (mkdir called successfully and returned with the given return code) * `Exx` (An error occurred) -## qPlatform_chmod +## vFile:chmod / qPlatform_chmod ### Brief @@ -1900,6 +1933,43 @@ send packet: $qsProcessInfo#00 read packet: $E04#00 ``` +## qPathComplete (Platform Extension) + +### Brief + +Get a list of matched disk files/directories by passing a boolean flag +and a partial path. + +### Example + +``` +receive: qPathComplete:0,6d61696e +send: M6d61696e2e637070 +receive: qPathComplete:1,746573 +send: M746573742f,74657374732f +``` + +If the first argument is zero, the result should contain all +files (including directories) starting with the given path. If the +argument is one, the result should contain only directories. + +The result should be a comma-separated list of hex-encoded paths. +Paths denoting a directory should end with a directory separator (`/` or `\`. + +## qKillSpawnedProcess (Platform Extension) + +### Brief + +Kill a process running on the target system. + +### Example + +``` +receive: qKillSpawnedProcess:1337 +send: OK +``` +The request packet has the process ID in base 10. + ## qLaunchGDBServer (Platform Extension) ### Brief @@ -2397,3 +2467,158 @@ STUB REPLIES: {"process_state_value":48,"process_state string":"dyld_process_sta Low. This packet is needed to prevent lldb's utility functions for scanning the Objective-C class list from running very early in process startup. + +## vFile Packets + +Though some of these may match the ones described in GDB's protocol +documentation, we include our own expectations here in case of +mismatches or extensions. + +### vFile:size + +#### Brief + +Get the size of a file on the target system, filename in ASCII hex. + +#### Example + +``` +receive: vFile:size:2f746d702f61 +send: Fc008 +``` + +response is `F` followed by the file size in base 16. +`F-1,errno` with the errno if an error occurs, base 16. + +### vFile:mode + +#### Brief + +Get the mode bits of a file on the target system, filename in ASCII hex. + +#### Example + +``` +receive: vFile:mode:2f746d702f61 +send: F1ed +``` + +response is `F` followed by the mode bits in base 16, this `0x1ed` would +correspond to `0755` in octal. +`F-1,errno` with the errno if an error occurs, base 16. + +### vFile:unlink + +#### Brief + +Remove a file on the target system. + +#### Example + +``` +receive: vFile:unlink:2f746d702f61 +send: F0 +``` + +Argument is a file path in ascii-hex encoding. +Response is `F` plus the return value of `unlink()`, base 16 encoding. +Return value may optionally be followed by a comma and the base16 +value of errno if unlink failed. + +### vFile:symlink + +#### Brief + +Create a symbolic link (symlink, soft-link) on the target system. + +#### Example + +``` +receive: vFile:symlink:, +send: F0,0 +``` + +Argument file paths are in ascii-hex encoding. +Response is `F` plus the return value of `symlink()`, base 16 encoding, +optionally followed by the value of errno if it failed, also base 16. + +### vFile:open + +#### Brief + +Open a file on the remote system and return the file descriptor of it. + +#### Example + +``` +receive: vFile:open:2f746d702f61,00000001,00000180 +send: F8 +``` + +request packet has the fields: + 1. ASCII hex encoded filename + 2. Flags passed to the open call, base 16. + Note that these are not the `oflags` that `open(2)` takes, but + are the constant values in `enum OpenOptions` from LLDB's + [`File.h`](https://github.com/llvm/llvm-project/blob/main/lldb/include/lldb/Host/File.h). + 3. Mode bits, base 16 + +response is `F` followed by the opened file descriptor in base 16. +`F-1,errno` with the errno if an error occurs, base 16. + +### vFile:close + +#### Brief + +Close a previously opened file descriptor. + +#### Example + +``` +receive: vFile:close:7 +send: F0 +``` + +File descriptor is in base 16. `F-1,errno` with the errno if an error occurs, +errno is base 16. + +### vFile:pread + +#### Brief + +Read data from an opened file descriptor. + +#### Example + +``` +receive: vFile:pread:7,1024,0 +send: F4;a'b\00 +``` + +Request packet has the fields: + 1. File descriptor, base 16 + 2. Number of bytes to be read, base 16 + 3. Offset into file to start from, base 16 + +Response is `F`, followed by the number of bytes read (base 16), a +semicolon, followed by the data in the binary-escaped-data encoding. + +### vFile:pwrite + +#### Brief + +Write data to a previously opened file descriptor. + +#### Example + +``` +receive: vFile:pwrite:8,0,\cf\fa\ed\fe\0c\00\00 +send: F1024 +``` + +Request packet has the fields: + 1. File descriptor, base 16 + 2. Offset into file to start from, base 16 + 3. binary-escaped-data to be written + +Response is `F`, followed by the number of bytes written (base 16). \ No newline at end of file diff --git a/lldb/docs/resources/lldbplatformpackets.md b/lldb/docs/resources/lldbplatformpackets.md index 326dd5669f79..f7262e193d94 100644 --- a/lldb/docs/resources/lldbplatformpackets.md +++ b/lldb/docs/resources/lldbplatformpackets.md @@ -1,484 +1,49 @@ # LLDB Platform Packets -Here is a brief overview of the packets that an lldb platform server +This is a list of the packets that an lldb platform server needs to implement for the lldb testsuite to be run on a remote target device/system. These are almost all lldb extensions to the gdb-remote serial -protocol. Many of the `vFile:` packets are also described in the "Host +protocol. Many of the `vFile:` packets are also described in the "Host I/O Packets" detailed in the gdb-remote protocol documentation, although the lldb platform extensions include packets that are not defined there (`vFile:size:`, `vFile:mode:`, `vFile:symlink`, `vFile:chmod:`). -Most importantly, the flags that lldb passes to `vFile:open:` are -incompatible with the flags that gdb specifies. - -## QStartNoAckMode - -### Brief - -A request to stop sending ACK packets for each properly formatted packet. - -### Example - -A platform session will typically start like this: -``` -receive: +$QStartNoAckMode#b0 -send: + <-- ACKing the properly formatted QStartNoAckMode packet -send: $OK#9a -receive: + <-- Our OK packet getting ACKed -``` - -ACK mode is now disabled. - -## qHostInfo - -### Brief - -Describe the hardware and OS of the target system - -### Example - -``` -receive: qHostInfo -send: cputype:16777228;cpusubtype:1;ostype:ios;watchpoint_exceptions_received:before;os_version:12.1;vendor:apple;default_packet_timeout:5; -``` - -All numbers are base 10, `os_version` is a string that will be parsed as major.minor.patch. - -## qModuleInfo - -### Brief - -Get information for a module by given module path and architecture. - -The response is: -* `(uuid|md5):...;triple:...;file_offset:...;file_size...;` or -* `EXX` - for any errors - -### Example - -``` -receive: qModuleInfo:2f62696e2f6c73; -``` - -## qGetWorkingDir - -### Brief - -Get the current working directory of the platform stub in -ASCII hex encoding. - -### Example - -``` -receive: qGetWorkingDir -send: 2f4170706c65496e7465726e616c2f6c6c64622f73657474696e67732f342f5465737453657474696e67732e746573745f646973617373656d626c65725f73657474696e6773 -``` - -## QSetWorkingDir - -### Brief - -Set the current working directory of the platform stub in -ASCII hex encoding. - -### Example - -``` -receive: QSetWorkingDir:2f4170706c65496e7465726e616c2f6c6c64622f73657474696e67732f342f5465737453657474696e67732e746573745f646973617373656d626c65725f73657474696e6773 -send: OK -``` - -## qPlatform_mkdir - -### Brief - -Create a directory on the target system. - -### Example - -``` -receive: qPlatform_mkdir:000001fd,2f746d702f6131 -send: F0 -``` - -request packet has the fields: - 1. mode bits in base 16 - 2. file path in ASCII hex encoding - -response is F followed by the return value of the `mkdir()` call, -base 16 encoded. - -## qPlatform_shell - -### Brief - -Run a shell command on the target system, return the output. - -### Example - -``` -receive: qPlatform_shell:6c73202f746d702f,0000000a -send: F,0,0, -``` - -request packet has the fields: - 1. shell command in ASCII hex encoding - 2. timeout - 3. working directory in ASCII hex encoding (optional) - -Response is `F` followed by the return value of the command (base 16), -followed by another number, followed by the output of the command -in binary-escaped-data encoding. - -## qLaunchGDBServer - -### Brief - -Start a gdbserver process (`gdbserver`, `debugserver`, `lldb-server`) -on the target system. - -### Example - -``` -receive: qLaunchGDBServer;host:; -send: pid:1337;port:43001; -``` - -Request packet hostname field is not ASCII hex encoded. Hostnames -do not have `$` or `#` characters in them. - -Response to the packet is the pid of the newly launched gdbserver, -and the port it is listening for a connection on. - -When the testsuite is running, lldb may use the pid to kill off a -debugserver that doesn't seem to be responding, etc. - -## qKillSpawnedProcess - -### Brief - -Kill a process running on the target system. - -### Example - -``` -receive: qKillSpawnedProcess:1337 -send: OK -``` -The request packet has the process ID in base 10. - -## qProcessInfoPID: - -### Brief - -Gather information about a process running on the target. - -### Example - -``` -receive: qProcessInfoPID:71964 -send: pid:71964;name:612e6f7574; -``` - -The request packet has the pid encoded in base 10. - -The reply has semicolon-separated `name:value` fields, two are -shown here. `pid` is base 10 encoded. `name` is ascii hex encoded. -lldb-server can reply with many additional fields, but this is probably -enough for the testsuite. - -## qfProcessInfo - -### Brief - -Search the process table for processes matching criteria, -respond with them in multiple packets. - -### Example - -``` -receive: qfProcessInfo:name_match:equals;name:6e6f70726f6365737365786973747377697468746869736e616d65; -send: pid:3500;name:612e6f7574; -``` - -The request packet has a criteria to search for, followed by -a specific name. - -| Key | Value | Description -| ------------ | --------- | ----------- -| `name` | ascii-hex | An ASCII hex string that contains the name of the process that will be matched. -| `name_match` | enum | One of: `equals`, `starts_with`, `ends_with`, `contains` or `regex` -| `pid` | integer | A string value containing the decimal process ID -| `parent_pid` | integer | A string value containing the decimal parent process ID -| `uid` | integer | A string value containing the decimal user ID -| `gid` | integer | A string value containing the decimal group ID -| `euid` | integer | A string value containing the decimal effective user ID -| `egid` | integer | A string value containing the decimal effective group ID -| `all_users` | bool | A boolean value that specifies if processes should be listed for all users, not just the user that the platform is running as -| `triple` | ascii-hex | An ASCII hex target triple string (`x86_64`, `x86_64-apple-macosx`, `armv7-apple-ios`) - -If no criteria is given, `qfProcessInfo` will request a list of every process. - -The lldb testsuite currently only uses `name_match:equals` and the -no-criteria mode to list every process. - -The response should include any information about the process that -can be retrieved in semicolon-separated `name:value` fields. -In this example, `pid` is base 10, `name` is ASCII hex encoded. -The testsuite seems to only require these two. - -This packet only responds with one process. To get further matches to -the search, `qsProcessInfo` should be sent. - -If no process match is found, `Exx` should be returned. - -Sample packet/response: -``` -send packet: $qfProcessInfo#00 -read packet: $pid:60001;ppid:59948;uid:7746;gid:11;euid:7746;egid:11;name:6c6c6462;triple:7838365f36342d6170706c652d6d61636f7378;#00 -send packet: $qsProcessInfo#00 -read packet: $pid:59992;ppid:192;uid:7746;gid:11;euid:7746;egid:11;name:6d64776f726b6572;triple:7838365f36342d6170706c652d6d61636f7378;#00 -send packet: $qsProcessInfo#00 -read packet: $E04#00 -``` - -## qsProcessInfo - -### Brief - -Return the next process info found by the most recent `qfProcessInfo:` -packet. - -### Example - -Continues to return the results of the `qfProcessInfo`. Once all matches -have been sent, `Exx` is returned to indicate end of matches. - -## qPathComplete - -### Brief - -Get a list of matched disk files/directories by passing a boolean flag -and a partial path. - -### Example - -``` -receive: qPathComplete:0,6d61696e -send: M6d61696e2e637070 -receive: qPathComplete:1,746573 -send: M746573742f,74657374732f -``` - -If the first argument is zero, the result should contain all -files (including directories) starting with the given path. If the -argument is one, the result should contain only directories. - -The result should be a comma-separated list of hex-encoded paths. -Paths denoting a directory should end with a directory separator (`/` or `\`). - -## vFile:size - -### Brief - -Get the size of a file on the target system, filename in ASCII hex encoding. - -### Example - -``` -receive: vFile:size:2f746d702f61 -send: Fc008 -``` - -response is `F` followed by the file size in base 16. -`F-1,errno` with the errno if an error occurs, base 16. - -## vFile:mode - -### Brief - -Get the mode bits of a file on the target system, filename in ASCII hex. - -### Example - -``` -receive: vFile:mode:2f746d702f61 -send: F1ed -``` - -response is `F` followed by the mode bits in base 16, this `0x1ed` would -correspond to `0755` in octal. -`F-1,errno` with the errno if an error occurs, base 16. - -## vFile:unlink - -### Brief - -Remove a file on the target system. - -### Example - -``` -receive: vFile:unlink:2f746d702f61 -send: F0 -``` - -Argument is a file path in ascii-hex encoding. - -Response is `F` plus the return value of `unlink()` in base 16 encoding. -If unlink failed, the return value may be followed by a comma and the value of -errno in base 16 encoding. - -## vFile:symlink - -### Brief - -Create a symbolic link (symlink, soft-link) on the target system. - -### Example - -``` -receive: vFile:symlink:, -send: F0,0 -``` - -Argument file paths are in ascii-hex encoding. -Response is `F` plus the return value of `symlink()`, base 16 encoding, -optionally followed by the value of errno if it failed, also base 16. - -## vFile:chmod / qPlatform_chmod - -### Brief - -Change the permission mode bits on a file on the target - -### Example - -``` -receive: vFile:chmod:180,2f746d702f61 -send: F0 -``` - -Arguments are the mode bits to set, base 16, and a file path in -ascii-hex encoding. -Response is `F` plus the return value of `chmod()`, base 16 encoding. - -These 2 packets do the same thing, it is not known why we ended up with 2. - -## vFile:chmod - -### Brief - -Change the permission mode bits on a file on the target. - -### Example - -``` -receive: vFile:chmod:180,2f746d702f61 -send: F0 -``` - -Arguments are the mode bits to set, base 16, and a file path in -ascii-hex encoding. -Response is `F` plus the return value of `chmod()`, base 10 encoding. - -## vFile:open - -### Brief - -Open a file on the remote system and return the file descriptor of it. - -### Example - -``` -receive: vFile:open:2f746d702f61,00000001,00000180 -send: F8 -``` - -request packet has the fields: - 1. ASCII hex encoded filename - 2. Flags passed to the open call, base 16. - Note that these are not the `oflags` that `open(2)` takes, but - are the constant values in `enum OpenOptions` from LLDB's - [`File.h`](https://github.com/llvm/llvm-project/blob/main/lldb/include/lldb/Host/File.h). - 3. Mode bits, base 16 - -response is `F` followed by the opened file descriptor in base 16. -`F-1,errno` with the errno if an error occurs, base 16. - -## vFile:close - -### Brief - -Close a previously opened file descriptor. - -### Example - -``` -receive: vFile:close:7 -send: F0 -``` - -File descriptor is in base 16. `F-1,errno` with the errno if an error occurs, -errno is base 16. - -## vFile:pread - -### Brief - -Read data from an opened file descriptor. - -### Example - -``` -receive: vFile:pread:7,1024,0 -send: F4;a'b\00 -``` - -Request packet has the fields: - 1. File descriptor, base 16 - 2. Number of bytes to be read, base 16 - 3. Offset into file to start from, base 16 - -Response is `F`, followed by the number of bytes read (base 16 encoded), a -semicolon, followed by the data in the binary-escaped-data encoding. - -## vFile:pwrite - -### Brief - -Write data to a previously opened file descriptor. - -### Example - -``` -receive: vFile:pwrite:8,0,\cf\fa\ed\fe\0c\00\00 -send: F1024 -``` - -Request packet has the fields: - 1. File descriptor, base 16 - 2. Offset into file to start from, base 16 - 3. binary-escaped-data to be written - -Response is `F`, followed by the number of bytes written (base 16 encoded). - -## Launching Processes - -Finally, the platform must be able to launch processes so that debugserver -can attach to them. To do this, the following packets should be handled: -* `QSetDisableASLR` -* `QSetDetachOnError` -* `QSetSTDOUT` -* `QSetSTDERR` -* `QSetSTDIN` -* `QEnvironment` -* `QEnvironmentHexEncoded` -* `A` -* `qLaunchSuccess` -* `qProcessInfo` - -Most of these are documented in the standard gdb-remote protocol -and/or LLDB's [GDB Remote Protocol Extensions](lldbgdbremote). +Most importantly, the flags that LLDB passes to `vFile:open:` are +incompatible with the flags that GDB specifies. + +* [QStartNoAckMode](./lldbgdbremote.md#qstartnoackmode) +* [qHostInfo](./lldbgdbremote.md#qhostinfo) +* [qModuleInfo](./lldbgdbremote.md#qmoduleinfo-module-path-arch-triple) +* [qGetWorkingDir](./lldbgdbremote.md#qgetworkingdir) +* [QSetWorkingDir](./lldbgdbremote.md#qsetworkingdir-ascii-hex-path) +* [qPlatform_mkdir](./lldbgdbremote.md#qplatform-mkdir) +* [qPlatform_shell](./lldbgdbremote.md#qplatform-shell) +* [qLaunchGDBServer](./lldbgdbremote.md#qlaunchgdbserver-platform-extension) +* [qKillSpawnedProcess](./lldbgdbremote.md#qkillspawnedprocess-platform-extension) +* [qProcessInfoPID](./lldbgdbremote.md#qprocessinfopid-pid-platform-extension) + * It is likely that you only need to support the `pid` and `name` fields. +* [qProcessInfo](./lldbgdbremote.md#qprocessinfo) + * The lldb test suite currently only uses `name_match:equals` and the no-criteria mode to list every process. +* [qPathComplete](./lldbgdbremote.md#qpathcomplete-platform-extension) +* [vFile:chmod](./lldbgdbremote.md#vfile-chmod-qplatform-chmod) +* [vFile:size](./lldbgdbremote.md#vfile-size) +* [vFile:mode](./lldbgdbremote.md#vfile-mode) +* [vFile:unlink](./lldbgdbremote.md#vfile-unlink) +* [vFile:symlink](./lldbgdbremote.md#vfile-symlink) +* [vFile:open](./lldbgdbremote.md#vfile-open) +* [vFile:close](./lldbgdbremote.md#vfile-close) +* [vFile:pread](./lldbgdbremote.md#vfile-pread) +* [vFile:pwrite](./lldbgdbremote.md#vfile-pwrite) + +The remote platform must be able to launch processes so that debugserver +can attach to them. This requires the following packets in addition to the +previous list: +* [QSetDisableASLR](./lldbgdbremote.md#qsetdisableaslr-bool) +* [QSetDetatchOnError](./lldbgdbremote.md#qsetdetachonerror) +* [QSetSTDIN / QSetSTDOUT / QSetSTDERR](./lldbgdbremote.md#qsetstdin-ascii-hex-path-qsetstdout-ascii-hex-path-qsetstderr-ascii-hex-path) (all 3) +* [QEnvironment](./lldbgdbremote.md#qenvironment-name-value) +* [QEnvironmentHexEncoded](./lldbgdbremote.md#qenvironmenthexencoded-hex-encoding-name-value) +* [A](./lldbgdbremote.md#a-launch-args-packet) +* [qLaunchSuccess](./lldbgdbremote.md#qlaunchsuccess) -- GitLab From d529e780f3935aadd42688fa8ab45d0350c2f70c Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Fri, 26 Apr 2024 02:37:54 -0600 Subject: [PATCH 024/301] [GVN] Refactor the LeaderTable structure into a properly encapsulated data structure (#88347) Hide the details of the one-off linked list used to implement the leader lists by wrapping them in iterators, and then use that to reimplement a number of traversals using standard algorithms and range-based for-loops. No functional change intended. --- llvm/include/llvm/Transforms/Scalar/GVN.h | 111 ++++++++++-------- llvm/lib/Transforms/Scalar/GVN.cpp | 135 ++++++++++++++-------- 2 files changed, 149 insertions(+), 97 deletions(-) diff --git a/llvm/include/llvm/Transforms/Scalar/GVN.h b/llvm/include/llvm/Transforms/Scalar/GVN.h index 4ba9b74ccb00..debe2ee79917 100644 --- a/llvm/include/llvm/Transforms/Scalar/GVN.h +++ b/llvm/include/llvm/Transforms/Scalar/GVN.h @@ -232,13 +232,67 @@ private: /// A mapping from value numbers to lists of Value*'s that /// have that value number. Use findLeader to query it. - struct LeaderTableEntry { - Value *Val; - const BasicBlock *BB; - LeaderTableEntry *Next; + class LeaderMap { + public: + struct LeaderTableEntry { + Value *Val; + const BasicBlock *BB; + }; + + private: + struct LeaderListNode { + LeaderTableEntry Entry; + LeaderListNode *Next; + }; + DenseMap NumToLeaders; + BumpPtrAllocator TableAllocator; + + public: + class leader_iterator { + const LeaderListNode *Current; + + public: + using iterator_category = std::forward_iterator_tag; + using value_type = const LeaderTableEntry; + using difference_type = std::ptrdiff_t; + using pointer = value_type *; + using reference = value_type &; + + leader_iterator(const LeaderListNode *C) : Current(C) {} + leader_iterator &operator++() { + assert(Current && "Dereferenced end of leader list!"); + Current = Current->Next; + return *this; + } + bool operator==(const leader_iterator &Other) const { + return Current == Other.Current; + } + bool operator!=(const leader_iterator &Other) const { + return Current != Other.Current; + } + reference operator*() const { return Current->Entry; } + }; + + iterator_range getLeaders(uint32_t N) { + auto I = NumToLeaders.find(N); + if (I == NumToLeaders.end()) { + return iterator_range(leader_iterator(nullptr), + leader_iterator(nullptr)); + } + + return iterator_range(leader_iterator(&I->second), + leader_iterator(nullptr)); + } + + void insert(uint32_t N, Value *V, const BasicBlock *BB); + void erase(uint32_t N, Instruction *I, const BasicBlock *BB); + void verifyRemoved(const Value *Inst) const; + void clear() { + NumToLeaders.clear(); + TableAllocator.Reset(); + } }; - DenseMap LeaderTable; - BumpPtrAllocator TableAllocator; + LeaderMap LeaderTable; // Block-local map of equivalent values to their leader, does not // propagate to any successors. Entries added mid-block are applied @@ -264,51 +318,6 @@ private: MemoryDependenceResults *RunMD, LoopInfo &LI, OptimizationRemarkEmitter *ORE, MemorySSA *MSSA = nullptr); - /// Push a new Value to the LeaderTable onto the list for its value number. - void addToLeaderTable(uint32_t N, Value *V, const BasicBlock *BB) { - LeaderTableEntry &Curr = LeaderTable[N]; - if (!Curr.Val) { - Curr.Val = V; - Curr.BB = BB; - return; - } - - LeaderTableEntry *Node = TableAllocator.Allocate(); - Node->Val = V; - Node->BB = BB; - Node->Next = Curr.Next; - Curr.Next = Node; - } - - /// Scan the list of values corresponding to a given - /// value number, and remove the given instruction if encountered. - void removeFromLeaderTable(uint32_t N, Instruction *I, BasicBlock *BB) { - LeaderTableEntry *Prev = nullptr; - LeaderTableEntry *Curr = &LeaderTable[N]; - - while (Curr && (Curr->Val != I || Curr->BB != BB)) { - Prev = Curr; - Curr = Curr->Next; - } - - if (!Curr) - return; - - if (Prev) { - Prev->Next = Curr->Next; - } else { - if (!Curr->Next) { - Curr->Val = nullptr; - Curr->BB = nullptr; - } else { - LeaderTableEntry *Next = Curr->Next; - Curr->Val = Next->Val; - Curr->BB = Next->BB; - Curr->Next = Next->Next; - } - } - } - // List of critical edges to be split between iterations. SmallVector, 4> toSplit; diff --git a/llvm/lib/Transforms/Scalar/GVN.cpp b/llvm/lib/Transforms/Scalar/GVN.cpp index d829e92b2444..b5be8ac24941 100644 --- a/llvm/lib/Transforms/Scalar/GVN.cpp +++ b/llvm/lib/Transforms/Scalar/GVN.cpp @@ -725,6 +725,69 @@ void GVNPass::ValueTable::verifyRemoved(const Value *V) const { "Inst still occurs in value numbering map!"); } +//===----------------------------------------------------------------------===// +// LeaderMap External Functions +//===----------------------------------------------------------------------===// + +/// Push a new Value to the LeaderTable onto the list for its value number. +void GVNPass::LeaderMap::insert(uint32_t N, Value *V, const BasicBlock *BB) { + LeaderListNode &Curr = NumToLeaders[N]; + if (!Curr.Entry.Val) { + Curr.Entry.Val = V; + Curr.Entry.BB = BB; + return; + } + + LeaderListNode *Node = TableAllocator.Allocate(); + Node->Entry.Val = V; + Node->Entry.BB = BB; + Node->Next = Curr.Next; + Curr.Next = Node; +} + +/// Scan the list of values corresponding to a given +/// value number, and remove the given instruction if encountered. +void GVNPass::LeaderMap::erase(uint32_t N, Instruction *I, + const BasicBlock *BB) { + LeaderListNode *Prev = nullptr; + LeaderListNode *Curr = &NumToLeaders[N]; + + while (Curr && (Curr->Entry.Val != I || Curr->Entry.BB != BB)) { + Prev = Curr; + Curr = Curr->Next; + } + + if (!Curr) + return; + + if (Prev) { + Prev->Next = Curr->Next; + } else { + if (!Curr->Next) { + Curr->Entry.Val = nullptr; + Curr->Entry.BB = nullptr; + } else { + LeaderListNode *Next = Curr->Next; + Curr->Entry.Val = Next->Entry.Val; + Curr->Entry.BB = Next->Entry.BB; + Curr->Next = Next->Next; + } + } +} + +void GVNPass::LeaderMap::verifyRemoved(const Value *V) const { + // Walk through the value number scope to make sure the instruction isn't + // ferreted away in it. + for (const auto &I : NumToLeaders) { + (void)I; + assert(I.second.Entry.Val != V && "Inst still in value numbering scope!"); + assert( + std::none_of(leader_iterator(&I.second), leader_iterator(nullptr), + [=](const LeaderTableEntry &E) { return E.Val == V; }) && + "Inst still in value numbering scope!"); + } +} + //===----------------------------------------------------------------------===// // GVN Pass //===----------------------------------------------------------------------===// @@ -1467,7 +1530,7 @@ void GVNPass::eliminatePartiallyRedundantLoad( OldLoad->replaceAllUsesWith(NewLoad); replaceValuesPerBlockEntry(ValuesPerBlock, OldLoad, NewLoad); if (uint32_t ValNo = VN.lookup(OldLoad, false)) - removeFromLeaderTable(ValNo, OldLoad, OldLoad->getParent()); + LeaderTable.erase(ValNo, OldLoad, OldLoad->getParent()); VN.erase(OldLoad); removeInstruction(OldLoad); } @@ -2204,10 +2267,9 @@ GVNPass::ValueTable::assignExpNewValueNum(Expression &Exp) { /// defined in \p BB. bool GVNPass::ValueTable::areAllValsInBB(uint32_t Num, const BasicBlock *BB, GVNPass &Gvn) { - LeaderTableEntry *Vals = &Gvn.LeaderTable[Num]; - while (Vals && Vals->BB == BB) - Vals = Vals->Next; - return !Vals; + return all_of( + Gvn.LeaderTable.getLeaders(Num), + [=](const LeaderMap::LeaderTableEntry &L) { return L.BB == BB; }); } /// Wrap phiTranslateImpl to provide caching functionality. @@ -2229,12 +2291,11 @@ bool GVNPass::ValueTable::areCallValsEqual(uint32_t Num, uint32_t NewNum, const BasicBlock *PhiBlock, GVNPass &Gvn) { CallInst *Call = nullptr; - LeaderTableEntry *Vals = &Gvn.LeaderTable[Num]; - while (Vals) { - Call = dyn_cast(Vals->Val); + auto Leaders = Gvn.LeaderTable.getLeaders(Num); + for (const auto &Entry : Leaders) { + Call = dyn_cast(Entry.Val); if (Call && Call->getParent() == PhiBlock) break; - Vals = Vals->Next; } if (AA->doesNotAccessMemory(Call)) @@ -2327,23 +2388,17 @@ void GVNPass::ValueTable::eraseTranslateCacheEntry( // question. This is fast because dominator tree queries consist of only // a few comparisons of DFS numbers. Value *GVNPass::findLeader(const BasicBlock *BB, uint32_t num) { - LeaderTableEntry Vals = LeaderTable[num]; - if (!Vals.Val) return nullptr; + auto Leaders = LeaderTable.getLeaders(num); + if (Leaders.empty()) + return nullptr; Value *Val = nullptr; - if (DT->dominates(Vals.BB, BB)) { - Val = Vals.Val; - if (isa(Val)) return Val; - } - - LeaderTableEntry* Next = Vals.Next; - while (Next) { - if (DT->dominates(Next->BB, BB)) { - if (isa(Next->Val)) return Next->Val; - if (!Val) Val = Next->Val; + for (const auto &Entry : Leaders) { + if (DT->dominates(Entry.BB, BB)) { + Val = Entry.Val; + if (isa(Val)) + return Val; } - - Next = Next->Next; } return Val; @@ -2452,7 +2507,7 @@ bool GVNPass::propagateEquality(Value *LHS, Value *RHS, // have the simple case where the edge dominates the end. if (RootDominatesEnd && !isa(RHS) && canReplacePointersIfEqual(LHS, RHS, DL)) - addToLeaderTable(LVN, RHS, Root.getEnd()); + LeaderTable.insert(LVN, RHS, Root.getEnd()); // Replace all occurrences of 'LHS' with 'RHS' everywhere in the scope. As // LHS always has at least one use that is not dominated by Root, this will @@ -2546,7 +2601,7 @@ bool GVNPass::propagateEquality(Value *LHS, Value *RHS, // The leader table only tracks basic blocks, not edges. Only add to if we // have the simple case where the edge dominates the end. if (RootDominatesEnd) - addToLeaderTable(Num, NotVal, Root.getEnd()); + LeaderTable.insert(Num, NotVal, Root.getEnd()); continue; } @@ -2596,7 +2651,7 @@ bool GVNPass::processInstruction(Instruction *I) { return true; unsigned Num = VN.lookupOrAdd(Load); - addToLeaderTable(Num, Load, Load->getParent()); + LeaderTable.insert(Num, Load, Load->getParent()); return false; } @@ -2664,7 +2719,7 @@ bool GVNPass::processInstruction(Instruction *I) { // Allocations are always uniquely numbered, so we can save time and memory // by fast failing them. if (isa(I) || I->isTerminator() || isa(I)) { - addToLeaderTable(Num, I, I->getParent()); + LeaderTable.insert(Num, I, I->getParent()); return false; } @@ -2672,7 +2727,7 @@ bool GVNPass::processInstruction(Instruction *I) { // need to do a lookup to see if the number already exists // somewhere in the domtree: it can't! if (Num >= NextNum) { - addToLeaderTable(Num, I, I->getParent()); + LeaderTable.insert(Num, I, I->getParent()); return false; } @@ -2681,7 +2736,7 @@ bool GVNPass::processInstruction(Instruction *I) { Value *Repl = findLeader(I->getParent(), Num); if (!Repl) { // Failure, just remember this instance for future use. - addToLeaderTable(Num, I, I->getParent()); + LeaderTable.insert(Num, I, I->getParent()); return false; } @@ -2876,7 +2931,7 @@ bool GVNPass::performScalarPREInsertion(Instruction *Instr, BasicBlock *Pred, VN.add(Instr, Num); // Update the availability map to include the new instruction. - addToLeaderTable(Num, Instr, Pred); + LeaderTable.insert(Num, Instr, Pred); return true; } @@ -3027,13 +3082,13 @@ bool GVNPass::performScalarPRE(Instruction *CurInst) { // After creating a new PHI for ValNo, the phi translate result for ValNo will // be changed, so erase the related stale entries in phi translate cache. VN.eraseTranslateCacheEntry(ValNo, *CurrentBlock); - addToLeaderTable(ValNo, Phi, CurrentBlock); + LeaderTable.insert(ValNo, Phi, CurrentBlock); Phi->setDebugLoc(CurInst->getDebugLoc()); CurInst->replaceAllUsesWith(Phi); if (MD && Phi->getType()->isPtrOrPtrVectorTy()) MD->invalidateCachedPointerInfo(Phi); VN.erase(CurInst); - removeFromLeaderTable(ValNo, CurInst, CurrentBlock); + LeaderTable.erase(ValNo, CurInst, CurrentBlock); LLVM_DEBUG(dbgs() << "GVN PRE removed: " << *CurInst << '\n'); removeInstruction(CurInst); @@ -3127,7 +3182,6 @@ void GVNPass::cleanupGlobalSets() { VN.clear(); LeaderTable.clear(); BlockRPONumber.clear(); - TableAllocator.Reset(); ICF->clear(); InvalidBlockRPONumbers = true; } @@ -3147,18 +3201,7 @@ void GVNPass::removeInstruction(Instruction *I) { /// internal data structures. void GVNPass::verifyRemoved(const Instruction *Inst) const { VN.verifyRemoved(Inst); - - // Walk through the value number scope to make sure the instruction isn't - // ferreted away in it. - for (const auto &I : LeaderTable) { - const LeaderTableEntry *Node = &I.second; - assert(Node->Val != Inst && "Inst still in value numbering scope!"); - - while (Node->Next) { - Node = Node->Next; - assert(Node->Val != Inst && "Inst still in value numbering scope!"); - } - } + LeaderTable.verifyRemoved(Inst); } /// BB is declared dead, which implied other blocks become dead as well. This @@ -3285,7 +3328,7 @@ void GVNPass::assignValNumForDeadCode() { for (BasicBlock *BB : DeadBlocks) { for (Instruction &Inst : *BB) { unsigned ValNum = VN.lookupOrAdd(&Inst); - addToLeaderTable(ValNum, &Inst, BB); + LeaderTable.insert(ValNum, &Inst, BB); } } } -- GitLab From bd53c7cce418fe7f3e171859d4718df15d03dc2b Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 26 Apr 2024 09:44:41 +0100 Subject: [PATCH 025/301] [lldb][Docs] Document vFile "MD5" and "exists" This is a Markdown version of https://github.com/llvm/llvm-project/pull/89357. --- lldb/docs/resources/lldbgdbremote.md | 44 +++++++++++++++++++++++++++- 1 file changed, 43 insertions(+), 1 deletion(-) diff --git a/lldb/docs/resources/lldbgdbremote.md b/lldb/docs/resources/lldbgdbremote.md index 9a1032818af0..05e4f714f7f7 100644 --- a/lldb/docs/resources/lldbgdbremote.md +++ b/lldb/docs/resources/lldbgdbremote.md @@ -2621,4 +2621,46 @@ Request packet has the fields: 2. Offset into file to start from, base 16 3. binary-escaped-data to be written -Response is `F`, followed by the number of bytes written (base 16). \ No newline at end of file +Response is `F`, followed by the number of bytes written (base 16). + +### vFile:MD5 + +#### Brief + +Generate an MD5 hash of the file at the given path. + +#### Example + +``` +receive: vFile:MD5:2f746d702f61 +send (success): F,00000000000000001111111111111111 +send (failure): F,x +``` + +Request packet contains the ASCII hex encoded filename. + +If the hash succeeded, the response is `F,` followed by the low 64 +bits of the result, and finally the high 64 bits of the result. Both are in +hex format without a prefix. + +The response is `F,`, followed by `x` if the file did not exist +or failed to hash. + +### vFile:exists + +#### Brief + +Check whether the file at the given path exists. + +#### Example + +``` +receive: vFile:exists:2f746d702f61 +send (exists): F,1 +send (does not exist): F,0 +``` + +Request packet contains the ASCII hex encoded filename. + +The response is a return code where 1 means the file exists +and 0 means it does not. \ No newline at end of file -- GitLab From 1a343c9b0ff0b38d841a54bdbef130dbdc624451 Mon Sep 17 00:00:00 2001 From: zxc12523 <76193329+zxc12523@users.noreply.github.com> Date: Fri, 26 Apr 2024 16:46:21 +0800 Subject: [PATCH 026/301] [X86] LowerVectorCTLZInRegLUT - fix: typo "CLTZ"-> "CTLZ" (#90051) --- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index bb43cbe15f52..f0cec6224e84 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -27896,7 +27896,7 @@ static SDValue LowerVectorCTLZInRegLUT(SDValue Op, const SDLoc &DL, SDValue InRegLUT = DAG.getBuildVector(CurrVT, DL, LUTVec); // Begin by bitcasting the input to byte vector, then split those bytes - // into lo/hi nibbles and use the PSHUFB LUT to perform CLTZ on each of them. + // into lo/hi nibbles and use the PSHUFB LUT to perform CTLZ on each of them. // If the hi input nibble is zero then we add both results together, otherwise // we just take the hi result (by masking the lo result to zero before the // add). -- GitLab From cf5a8b489464d09dfdd7a48ce7c8b41d3c9bf819 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Fri, 26 Apr 2024 16:59:12 +0800 Subject: [PATCH 027/301] [clang] Enable sized deallocation by default in C++14 onwards (#83774) Since C++14 has been released for about nine years and most standard libraries have implemented sized deallocation functions, it's time to make this feature default again. This is another try of https://reviews.llvm.org/D112921. Fixes #60061 --- .../clangd/unittests/FindTargetTests.cpp | 4 +- .../checkers/misc/new-delete-overloads.cpp | 10 - clang/docs/ReleaseNotes.rst | 5 + clang/include/clang/Driver/Options.td | 8 +- clang/lib/Driver/ToolChains/Clang.cpp | 13 +- clang/lib/Driver/ToolChains/Darwin.cpp | 58 ++++- clang/lib/Driver/ToolChains/Darwin.h | 4 + clang/lib/Driver/ToolChains/ZOS.cpp | 6 + clang/test/AST/ast-dump-expr-json.cpp | 2 +- clang/test/AST/ast-dump-expr.cpp | 2 +- clang/test/AST/ast-dump-stmt-json.cpp | 244 +++++++++++++++++- clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +- .../basic.stc.dynamic.deallocation/p2.cpp | 2 +- clang/test/CXX/drs/cwg292.cpp | 17 +- .../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +- .../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +- .../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +- .../CodeGenCXX/cxx2a-destroying-delete.cpp | 4 +- clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +- clang/test/CodeGenCXX/delete.cpp | 12 +- clang/test/CodeGenCXX/dllimport.cpp | 4 +- clang/test/CodeGenCXX/new.cpp | 6 +- .../coro-aligned-alloc-2.cpp | 2 - .../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +- clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +- clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +- clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 - clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +- clang/test/CodeGenCoroutines/pr56919.cpp | 9 +- clang/test/Lexer/cxx-features.cpp | 20 +- clang/test/PCH/cxx1z-aligned-alloc.cpp | 10 +- clang/test/SemaCXX/MicrosoftExtensions.cpp | 8 +- .../SemaCXX/builtin-operator-new-delete.cpp | 2 +- .../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +- .../unavailable_aligned_allocation.cpp | 15 +- clang/tools/clang-repl/CMakeLists.txt | 59 +++++ clang/unittests/Interpreter/CMakeLists.txt | 59 +++++ .../StaticAnalyzer/CallEventTest.cpp | 2 +- clang/www/cxx_status.html | 11 +- .../support.dynamic/libcpp_deallocate.sh.cpp | 3 + .../sized_delete_array14.pass.cpp | 8 +- .../new.delete.single/sized_delete14.pass.cpp | 8 +- 42 files changed, 555 insertions(+), 113 deletions(-) diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp index 799a549ff081..88aae2729904 100644 --- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp +++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp @@ -839,7 +839,9 @@ TEST_F(TargetDeclTest, OverloadExpr) { [[delete]] x; } )cpp"; - EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept"); + // Sized deallocation is enabled by default in C++14 onwards. + EXPECT_DECLS("CXXDeleteExpr", + "void operator delete(void *, unsigned long) noexcept"); } TEST_F(TargetDeclTest, DependentExprs) { diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp index 78f021144b2e..f86fe8a4c5b1 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp @@ -12,16 +12,6 @@ struct S { // CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has no matching declaration of 'operator delete' at the same scope void *operator new(size_t size) noexcept(false); -struct T { - // Sized deallocations are not enabled by default, and so this new/delete pair - // does not match. However, we expect only one warning, for the new, because - // the operator delete is a placement delete and we do not warn on mismatching - // placement operations. - // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new' has no matching declaration of 'operator delete' at the same scope - void *operator new(size_t size) noexcept; - void operator delete(void *ptr, size_t) noexcept; // ok only if sized deallocation is enabled -}; - struct U { void *operator new(size_t size) noexcept; void operator delete(void *ptr) noexcept; diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index f5e5d3a2e6ea..1576f681707d 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -90,6 +90,11 @@ C++ Language Changes -------------------- - Implemented ``_BitInt`` literal suffixes ``__wb`` or ``__WB`` as a Clang extension with ``unsigned`` modifiers also allowed. (#GH85223). +C++14 Feature Support +^^^^^^^^^^^^^^^^^^^^^ +- Sized deallocation is enabled by default in C++14 onwards. The user may specify + ``-fno-sized-deallocation`` to disable it if there are some regressions. + C++20 Feature Support ^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 4cb0b840df87..5a6526b0592f 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -603,6 +603,7 @@ class MarshallingInfoVisibility // Key paths that are constant during parsing of options with the same key path prefix. defvar cplusplus = LangOpts<"CPlusPlus">; defvar cpp11 = LangOpts<"CPlusPlus11">; +defvar cpp14 = LangOpts<"CPlusPlus14">; defvar cpp17 = LangOpts<"CPlusPlus17">; defvar cpp20 = LangOpts<"CPlusPlus20">; defvar c99 = LangOpts<"C99">; @@ -3370,10 +3371,9 @@ defm relaxed_template_template_args : BoolFOption<"relaxed-template-template-arg "Enable C++17 relaxed template template argument matching">, NegFlag>; defm sized_deallocation : BoolFOption<"sized-deallocation", - LangOpts<"SizedDeallocation">, DefaultFalse, - PosFlag, - NegFlag>; + LangOpts<"SizedDeallocation">, Default, + PosFlag, + NegFlag, BothFlags<[], [ClangOption, CC1Option]>>; defm aligned_allocation : BoolFOption<"aligned-allocation", LangOpts<"AlignedAllocation">, Default, PosFlag, diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index 651a2b5aac36..f4fe7422cba6 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -7262,10 +7262,15 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args, options::OPT_fno_relaxed_template_template_args); - // -fsized-deallocation is off by default, as it is an ABI-breaking change for - // most platforms. - Args.addOptInFlag(CmdArgs, options::OPT_fsized_deallocation, - options::OPT_fno_sized_deallocation); + // -fsized-deallocation is on by default in C++14 onwards and otherwise off + // by default. + if (Arg *A = Args.getLastArg(options::OPT_fsized_deallocation, + options::OPT_fno_sized_deallocation)) { + if (A->getOption().matches(options::OPT_fno_sized_deallocation)) + CmdArgs.push_back("-fno-sized-deallocation"); + else + CmdArgs.push_back("-fsized-deallocation"); + } // -faligned-allocation is on by default in C++17 onwards and otherwise off // by default. diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index caf6c4a444fd..593b403a1e3f 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -2912,9 +2912,54 @@ static bool sdkSupportsBuiltinModules(const Darwin::DarwinPlatformKind &TargetPl } } -void Darwin::addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, - llvm::opt::ArgStringList &CC1Args, - Action::OffloadKind DeviceOffloadKind) const { +static inline llvm::VersionTuple +sizedDeallocMinVersion(llvm::Triple::OSType OS) { + switch (OS) { + default: + break; + case llvm::Triple::Darwin: + case llvm::Triple::MacOSX: // Earliest supporting version is 10.12. + return llvm::VersionTuple(10U, 12U); + case llvm::Triple::IOS: + case llvm::Triple::TvOS: // Earliest supporting version is 10.0.0. + return llvm::VersionTuple(10U); + case llvm::Triple::WatchOS: // Earliest supporting version is 3.0.0. + return llvm::VersionTuple(3U); + } + + llvm_unreachable("Unexpected OS"); +} + +bool Darwin::isSizedDeallocationUnavailable() const { + llvm::Triple::OSType OS; + + if (isTargetMacCatalyst()) + return TargetVersion < sizedDeallocMinVersion(llvm::Triple::MacOSX); + switch (TargetPlatform) { + case MacOS: // Earlier than 10.12. + OS = llvm::Triple::MacOSX; + break; + case IPhoneOS: + OS = llvm::Triple::IOS; + break; + case TvOS: // Earlier than 10.0. + OS = llvm::Triple::TvOS; + break; + case WatchOS: // Earlier than 3.0. + OS = llvm::Triple::WatchOS; + break; + case DriverKit: + case XROS: + // Always available. + return false; + } + + return TargetVersion < sizedDeallocMinVersion(OS); +} + +void Darwin::addClangTargetOptions( + const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, + Action::OffloadKind DeviceOffloadKind) const { // Pass "-faligned-alloc-unavailable" only when the user hasn't manually // enabled or disabled aligned allocations. if (!DriverArgs.hasArgNoClaim(options::OPT_faligned_allocation, @@ -2922,6 +2967,13 @@ void Darwin::addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, isAlignedAllocationUnavailable()) CC1Args.push_back("-faligned-alloc-unavailable"); + // Pass "-fno-sized-deallocation" only when the user hasn't manually enabled + // or disabled sized deallocations. + if (!DriverArgs.hasArgNoClaim(options::OPT_fsized_deallocation, + options::OPT_fno_sized_deallocation) && + isSizedDeallocationUnavailable()) + CC1Args.push_back("-fno-sized-deallocation"); + addClangCC1ASTargetOptions(DriverArgs, CC1Args); // Enable compatibility mode for NSItemProviderCompletionHandler in diff --git a/clang/lib/Driver/ToolChains/Darwin.h b/clang/lib/Driver/ToolChains/Darwin.h index 10d4b69e5d5f..b45279ecedeb 100644 --- a/clang/lib/Driver/ToolChains/Darwin.h +++ b/clang/lib/Driver/ToolChains/Darwin.h @@ -511,6 +511,10 @@ protected: /// targeting. bool isAlignedAllocationUnavailable() const; + /// Return true if c++14 sized deallocation functions are not implemented in + /// the c++ standard library of the deployment target we are targeting. + bool isSizedDeallocationUnavailable() const; + void addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadKind) const override; diff --git a/clang/lib/Driver/ToolChains/ZOS.cpp b/clang/lib/Driver/ToolChains/ZOS.cpp index d5fc7b8ef562..074e0556ecd2 100644 --- a/clang/lib/Driver/ToolChains/ZOS.cpp +++ b/clang/lib/Driver/ToolChains/ZOS.cpp @@ -36,6 +36,12 @@ void ZOS::addClangTargetOptions(const ArgList &DriverArgs, if (!DriverArgs.hasArgNoClaim(options::OPT_faligned_allocation, options::OPT_fno_aligned_allocation)) CC1Args.push_back("-faligned-alloc-unavailable"); + + // Pass "-fno-sized-deallocation" only when the user hasn't manually enabled + // or disabled sized deallocations. + if (!DriverArgs.hasArgNoClaim(options::OPT_fsized_deallocation, + options::OPT_fno_sized_deallocation)) + CC1Args.push_back("-fno-sized-deallocation"); } void zos::Assembler::ConstructJob(Compilation &C, const JobAction &JA, diff --git a/clang/test/AST/ast-dump-expr-json.cpp b/clang/test/AST/ast-dump-expr-json.cpp index 0fb07b0b434c..bdd5ea19e418 100644 --- a/clang/test/AST/ast-dump-expr-json.cpp +++ b/clang/test/AST/ast-dump-expr-json.cpp @@ -2333,7 +2333,7 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "FunctionDecl", // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *) noexcept" +// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ diff --git a/clang/test/AST/ast-dump-expr.cpp b/clang/test/AST/ast-dump-expr.cpp index 69e65e22d61d..de88f29bc4b0 100644 --- a/clang/test/AST/ast-dump-expr.cpp +++ b/clang/test/AST/ast-dump-expr.cpp @@ -164,7 +164,7 @@ void UnaryExpressions(int *p) { // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue ParmVar 0x{{[^ ]*}} 'p' 'int *' ::delete p; - // CHECK: CXXDeleteExpr 0x{{[^ ]*}} 'void' global Function 0x{{[^ ]*}} 'operator delete' 'void (void *) noexcept' + // CHECK: CXXDeleteExpr 0x{{[^ ]*}} 'void' global Function 0x{{[^ ]*}} 'operator delete' 'void (void *, unsigned long) noexcept' // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue ParmVar 0x{{[^ ]*}} 'p' 'int *' diff --git a/clang/test/AST/ast-dump-stmt-json.cpp b/clang/test/AST/ast-dump-stmt-json.cpp index 667a12a01202..a473d17da942 100644 --- a/clang/test/AST/ast-dump-stmt-json.cpp +++ b/clang/test/AST/ast-dump-stmt-json.cpp @@ -994,7 +994,7 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "FunctionDecl", // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *) noexcept" +// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ @@ -1369,7 +1369,7 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "FunctionDecl", // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *) noexcept" +// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ @@ -1722,7 +1722,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "end": {} // CHECK-NEXT: }, // CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "mangledName": "_ZdlPv", // CHECK-NEXT: "type": { @@ -1810,6 +1809,126 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } +// CHECK-NOT: {{^}}Dumping +// CHECK: "kind": "FunctionDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "isUsed": true, +// CHECK-NEXT: "name": "operator delete", +// CHECK-NEXT: "mangledName": "_ZdlPvm", +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" +// CHECK-NEXT: }, +// CHECK-NEXT: "inner": [ +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void *" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "unsigned long" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "VisibilityAttr", +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "implicit": true, +// CHECK-NEXT: "visibility": "default" +// CHECK-NEXT: } +// CHECK-NEXT: ] +// CHECK-NEXT: } + +// CHECK-NOT: {{^}}Dumping +// CHECK: "kind": "FunctionDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "name": "operator delete", +// CHECK-NEXT: "mangledName": "_ZdlPvmSt11align_val_t", +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void (void *, unsigned long, std::align_val_t) noexcept" +// CHECK-NEXT: }, +// CHECK-NEXT: "inner": [ +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void *" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "unsigned long" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "std::align_val_t" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "VisibilityAttr", +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "implicit": true, +// CHECK-NEXT: "visibility": "default" +// CHECK-NEXT: } +// CHECK-NEXT: ] +// CHECK-NEXT: } + // CHECK-NOT: {{^}}Dumping // CHECK: "kind": "FunctionDecl", // CHECK-NEXT: "loc": {}, @@ -1906,6 +2025,125 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } +// CHECK-NOT: {{^}}Dumping +// CHECK: "kind": "FunctionDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "name": "operator delete[]", +// CHECK-NEXT: "mangledName": "_ZdaPvm", +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" +// CHECK-NEXT: }, +// CHECK-NEXT: "inner": [ +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void *" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "unsigned long" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "VisibilityAttr", +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "implicit": true, +// CHECK-NEXT: "visibility": "default" +// CHECK-NEXT: } +// CHECK-NEXT: ] +// CHECK-NEXT: } + +// CHECK-NOT: {{^}}Dumping +// CHECK: "kind": "FunctionDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "name": "operator delete[]", +// CHECK-NEXT: "mangledName": "_ZdaPvmSt11align_val_t", +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void (void *, unsigned long, std::align_val_t) noexcept" +// CHECK-NEXT: }, +// CHECK-NEXT: "inner": [ +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "void *" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "unsigned long" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "ParmVarDecl", +// CHECK-NEXT: "loc": {}, +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "type": { +// CHECK-NEXT: "qualType": "std::align_val_t" +// CHECK-NEXT: } +// CHECK-NEXT: }, +// CHECK-NEXT: { +// CHECK-NEXT: "id": "0x{{.*}}", +// CHECK-NEXT: "kind": "VisibilityAttr", +// CHECK-NEXT: "range": { +// CHECK-NEXT: "begin": {}, +// CHECK-NEXT: "end": {} +// CHECK-NEXT: }, +// CHECK-NEXT: "implicit": true, +// CHECK-NEXT: "visibility": "default" +// CHECK-NEXT: } +// CHECK-NEXT: ] +// CHECK-NEXT: } + // CHECK-NOT: {{^}}Dumping // CHECK: "kind": "FunctionTemplateDecl", // CHECK-NEXT: "loc": { diff --git a/clang/test/Analysis/cxxnewexpr-callback.cpp b/clang/test/Analysis/cxxnewexpr-callback.cpp index fe7a9fffad93..7df58cfa9ca2 100644 --- a/clang/test/Analysis/cxxnewexpr-callback.cpp +++ b/clang/test/Analysis/cxxnewexpr-callback.cpp @@ -9,7 +9,7 @@ void free(void *); } // namespace std void *operator new(size_t size) { return std::malloc(size); } -void operator delete(void *ptr) { std::free(ptr); } +void operator delete(void *ptr, size_t size) { std::free(ptr); } struct S { S() {} @@ -49,7 +49,7 @@ void test() { // CHECK-NEXT: PostCall (operator delete) } -void operator delete(void *ptr) { +void operator delete(void *ptr, size_t size) { std::free(ptr); // CHECK-NO-INLINE-NEXT: PreCall (std::free) // CHECK-NO-INLINE-NEXT: PostCall (std::free) diff --git a/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp b/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp index 9e3210c6650f..706549f56c52 100644 --- a/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp +++ b/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1z -fsized-deallocation -fexceptions -verify %s +// RUN: %clang_cc1 -std=c++1z -fexceptions -verify %s using size_t = decltype(sizeof(0)); diff --git a/clang/test/CXX/drs/cwg292.cpp b/clang/test/CXX/drs/cwg292.cpp index b05d3b92d627..a7bcbe6f5051 100644 --- a/clang/test/CXX/drs/cwg292.cpp +++ b/clang/test/CXX/drs/cwg292.cpp @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK -// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK -// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK -// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK -// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK -// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK -// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,CXX98-11 +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,CXX98-11 +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 namespace cwg292 { // cwg292: 2.9 @@ -23,7 +23,8 @@ void f() { // CHECK: invoke {{.*}} i32 @cwg292::g()() // CHECK-NEXT: to {{.*}} unwind label %lpad // CHECK-LABEL: lpad: -// CHECK: call void @operator delete(void*)(ptr {{.*}} %[[CALL]]) +// CXX98-11: call void @operator delete(void*)(ptr {{.*}} %[[CALL]]) +// SINCE-CXX14: call void @operator delete(void*, unsigned long)(ptr {{.*}} %[[CALL]], i64 noundef 1) // CHECK-LABEL: eh.resume: // CHECK-LABEL: } diff --git a/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp b/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp index 6537cdcfeafa..d0b24c8fe47b 100644 --- a/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp +++ b/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1z -fsized-deallocation -fexceptions %s -verify +// RUN: %clang_cc1 -std=c++1z -fexceptions %s -verify using size_t = decltype(sizeof(0)); namespace std { enum class align_val_t : size_t {}; } diff --git a/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp b/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp index 4e1565725152..55913aff9c19 100644 --- a/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp +++ b/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp @@ -1,12 +1,12 @@ // Check that delete exprs call the sized deallocation function if -// -fsized-deallocation is passed in both C++11 and C++14. +// -fsized-deallocation is passed in C++11 or std >= C++14. // RUN: %clang_cc1 -std=c++11 -fsized-deallocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++14 -fsized-deallocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s +// RUN: %clang_cc1 -std=c++14 %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// Check that we don't used sized deallocation without -fsized-deallocation and -// C++14. +// Check that we don't used sized deallocation with -fno-sized-deallocation or without C++14. // RUN: %clang_cc1 -std=c++11 %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s --check-prefix=CHECK-UNSIZED -// RUN: %clang_cc1 -std=c++14 %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s --check-prefix=CHECK-UNSIZED +// RUN: %clang_cc1 -std=c++14 %s -emit-llvm -triple x86_64-linux-gnu -fno-sized-deallocation -o - \ +// RUN: | FileCheck %s --check-prefix=CHECK-UNSIZED // CHECK-UNSIZED-NOT: _ZdlPvm // CHECK-UNSIZED-NOT: _ZdaPvm diff --git a/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp b/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp index ab2e4b3cdbbf..8823bc64a436 100644 --- a/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp +++ b/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp @@ -1,10 +1,10 @@ // Check that delete exprs call aligned (de)allocation functions if // -faligned-allocation is passed in both C++11 and C++14. // RUN: %clang_cc1 -std=c++11 -fexceptions -fsized-deallocation -faligned-allocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++14 -fexceptions -fsized-deallocation -faligned-allocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++1z -fexceptions -fsized-deallocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s +// RUN: %clang_cc1 -std=c++14 -fexceptions -faligned-allocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s +// RUN: %clang_cc1 -std=c++1z -fexceptions %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++1z -fexceptions -fsized-deallocation %s -emit-llvm -triple x86_64-windows-msvc -o - | FileCheck %s --check-prefix=CHECK-MS +// RUN: %clang_cc1 -std=c++1z -fexceptions %s -emit-llvm -triple x86_64-windows-msvc -o - | FileCheck %s --check-prefix=CHECK-MS // Check that we don't used aligned (de)allocation without -faligned-allocation or C++1z. // RUN: %clang_cc1 -std=c++14 -DUNALIGNED -fexceptions %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s --check-prefix=CHECK-UNALIGNED diff --git a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp index 20264b67353a..f6f4a2ff735c 100644 --- a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp +++ b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp @@ -108,10 +108,10 @@ struct J { // CHECK-MSABI-LABEL: define {{.*}}@"?j@@ J *j() { // CHECK-ITANIUM: invoke {{.*}}@_ZN1JC1Ev( - // CHECK-ITANIUM: call {{.*}}@_ZdlPv( + // CHECK-ITANIUM: call {{.*}}@_ZdlPvm( // CHECK-NOT: } // CHECK-MSABI: invoke {{.*}}@"??0J@@Q{{AE|EAA}}@XZ"( - // CHECK-MSABI: call {{.*}}@"??3@YAXP{{E?}}AX@Z"( + // CHECK-MSABI: call {{.*}}@"??3@YAXP{{E?}}AX{{I|_K}}@Z"( return new J; // CHECK: } } diff --git a/clang/test/CodeGenCXX/delete-two-arg.cpp b/clang/test/CodeGenCXX/delete-two-arg.cpp index 552634f430a8..a0dcd03bc5a9 100644 --- a/clang/test/CodeGenCXX/delete-two-arg.cpp +++ b/clang/test/CodeGenCXX/delete-two-arg.cpp @@ -43,7 +43,9 @@ namespace test2 { // CHECK-NEXT: br i1 [[T1]], // CHECK: [[T3:%.*]] = getelementptr inbounds i8, ptr [[T0]], i32 -4 // CHECK-NEXT: [[T5:%.*]] = load i32, ptr [[T3]] - // CHECK-NEXT: call void @_ZdaPv(ptr noundef [[T3]]) + // CHECK-NEXT: [[T6:%.*]] = mul i32 4, [[T5]] + // CHECK-NEXT: [[T7:%.*]] = add i32 [[T6]], 4 + // CHECK-NEXT: call void @_ZdaPvj(ptr noundef [[T3]], i32 noundef [[T7]]) // CHECK-NEXT: br label ::delete[] p; } diff --git a/clang/test/CodeGenCXX/delete.cpp b/clang/test/CodeGenCXX/delete.cpp index 1a418f48b659..d5b0dc671291 100644 --- a/clang/test/CodeGenCXX/delete.cpp +++ b/clang/test/CodeGenCXX/delete.cpp @@ -16,7 +16,7 @@ void t3(S *s) { // CHECK: icmp {{.*}} null // CHECK: br i1 - // CHECK: call void @_ZdlPv + // CHECK: call void @_ZdlPvm // Check the delete is inside the 'if !null' check unless we're optimizing // for size. FIXME: We could omit the branch entirely in this case. @@ -35,7 +35,7 @@ struct T { void t4(T *t) { // CHECK: call void @_ZN1TD1Ev // CHECK-SIZE-NEXT: br - // CHECK: call void @_ZdlPv + // CHECK: call void @_ZdlPvm delete t; } @@ -93,14 +93,16 @@ namespace test1 { // CHECK-NEXT: call void @_ZN5test11AD1Ev(ptr {{[^,]*}} [[CUR]]) // CHECK-NEXT: [[ISDONE:%.*]] = icmp eq ptr [[CUR]], [[BEGIN]] // CHECK-NEXT: br i1 [[ISDONE]] - // CHECK: call void @_ZdaPv(ptr noundef [[ALLOC]]) + // CHECK: [[MUL:%.*]] = mul i64 4, [[COUNT]] + // CHECK-NEXT: [[SIZE:%.*]] = add i64 [[MUL]], 8 + // CHECK-NEXT: call void @_ZdaPvm(ptr noundef [[ALLOC]], i64 noundef [[SIZE]]) } } namespace test2 { // CHECK-LABEL: define{{.*}} void @_ZN5test21fEPb void f(bool *b) { - // CHECK: call void @_ZdlPv(ptr + // CHECK: call void @_ZdlPvm(ptr{{.*}}i64 delete b; // CHECK: call void @_ZdaPv(ptr delete [] b; @@ -137,7 +139,7 @@ namespace test4 { // CHECK-NEXT: [[DTOR:%.*]] = load ptr, ptr [[T0]] // CHECK-NEXT: call void [[DTOR]](ptr {{[^,]*}} [[OBJ:%.*]]) // Call the global operator delete. - // CHECK-NEXT: call void @_ZdlPv(ptr noundef [[ALLOCATED]]) [[NUW:#[0-9]+]] + // CHECK-NEXT: call void @_ZdlPvm(ptr noundef [[ALLOCATED]], i64 noundef 8) [[NUW:#[0-9]+]] ::delete xp; } } diff --git a/clang/test/CodeGenCXX/dllimport.cpp b/clang/test/CodeGenCXX/dllimport.cpp index 6fec2f2982d4..484866b45389 100644 --- a/clang/test/CodeGenCXX/dllimport.cpp +++ b/clang/test/CodeGenCXX/dllimport.cpp @@ -205,7 +205,7 @@ USEVAR(VarTmpl) // Functions //===----------------------------------------------------------------------===// -// GNU-DAG: declare dso_local void @_ZdlPv(ptr) +// GNU-DAG: declare dso_local void @_ZdlPv{{j|y}}(ptr, i{{32|64}}) // Import function declaration. // MSC-DAG: declare dllimport void @"?decl@@YAXXZ"() @@ -358,7 +358,7 @@ __declspec(dllimport) void operator delete(void*); __declspec(dllimport) inline int *ReferencingImportedNew() { return new int[2]; } // MO1-DAG: define available_externally dllimport ptr @"?ReferencingImportedNew@@YAPAHXZ" __declspec(dllimport) inline int *ReferencingImportedDelete() { delete (int*)nullptr; } -// MO1-DAG: define available_externally dllimport ptr @"?ReferencingImportedDelete@@YAPAHXZ" +// MO1-DAG: declare dllimport ptr @"?ReferencingImportedDelete@@YAPAHXZ" USE(ReferencingImportedNew) USE(ReferencingImportedDelete) struct ClassWithDtor { ~ClassWithDtor() {} }; diff --git a/clang/test/CodeGenCXX/new.cpp b/clang/test/CodeGenCXX/new.cpp index e278d9acfe9e..af225529c494 100644 --- a/clang/test/CodeGenCXX/new.cpp +++ b/clang/test/CodeGenCXX/new.cpp @@ -15,7 +15,7 @@ void t1() { } // CHECK: declare noundef nonnull ptr @_Znwm(i64 noundef) [[ATTR_NOBUILTIN:#[^ ]*]] -// CHECK: declare void @_ZdlPv(ptr noundef) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] +// CHECK: declare void @_ZdlPvm(ptr noundef, i64 noundef) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] // CHECK: declare noundef nonnull ptr @_Znam(i64 noundef) [[ATTR_NOBUILTIN]] // CHECK: declare void @_ZdaPv(ptr noundef) [[ATTR_NOBUILTIN_NOUNWIND]] @@ -192,7 +192,7 @@ void f() { // CHECK: store i64 200 delete[] new (nothrow) Alloc[10][20]; // CHECK: call noalias noundef nonnull ptr @_Znwm - // CHECK: call void @_ZdlPv(ptr + // CHECK: call void @_ZdlPvm(ptr noundef {{%.*}}, i64 noundef 1) delete new bool; // CHECK: ret void } @@ -317,7 +317,7 @@ namespace N3664 { void f() { // CHECK: call noalias noundef nonnull ptr @_Znwm(i64 noundef 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] int *p = new int; // expected-note {{allocated with 'new' here}} - // CHECK: call void @_ZdlPv({{.*}}) [[ATTR_BUILTIN_DELETE:#[^ ]*]] + // CHECK: call void @_ZdlPvm({{.*}}) [[ATTR_BUILTIN_DELETE:#[^ ]*]] delete p; // CHECK: call noalias noundef nonnull ptr @_Znam(i64 noundef 12) [[ATTR_BUILTIN_NEW]] diff --git a/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp b/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp index a3ee964a22a1..ecf991a2fb49 100644 --- a/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp +++ b/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp @@ -1,9 +1,7 @@ // Tests that the combination of -fcoro-aligned-allocation and -fsized-deallocation works well. // Test the compiler will chose sized deallocation correctly. -// This is only enabled with `-fsized-deallocation` which is off by default. // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -std=c++20 \ // RUN: -fcoro-aligned-allocation -S -emit-llvm %s -o - -disable-llvm-passes \ -// RUN: -fsized-deallocation \ // RUN: | FileCheck %s #include "Inputs/coroutine.h" diff --git a/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp b/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp index d14c3d372ddb..b50d9f8f7674 100644 --- a/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp +++ b/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp @@ -26,8 +26,9 @@ struct task { // CHECK: %[[aligned_new:.+]] = call{{.*}}@_ZnwmSt11align_val_t({{.*}}%[[coro_size]],{{.*}}%[[coro_align]]) // CHECK: coro.free: +// CHECK: %[[coro_size_for_free:.+]] = call{{.*}}@llvm.coro.size // CHECK: %[[coro_align_for_free:.+]] = call{{.*}}@llvm.coro.align -// CHECK: call void @_ZdlPvSt11align_val_t({{.*}}[[coro_align_for_free]] +// CHECK: call void @_ZdlPvmSt11align_val_t({{.*}}%[[coro_size_for_free]],{{.*}}%[[coro_align_for_free]]) task f() { co_return 43; @@ -58,8 +59,9 @@ void *operator new(std::size_t, std::align_val_t, std::nothrow_t) noexcept; // CHECK: %[[aligned_new:.+]] = call{{.*}}@_ZnwmSt11align_val_tSt9nothrow_t({{.*}}%[[coro_size]],{{.*}}%[[coro_align]]) // CHECK: coro.free: +// CHECK: %[[coro_size_for_free:.+]] = call{{.*}}@llvm.coro.size // CHECK: %[[coro_align_for_free:.+]] = call{{.*}}@llvm.coro.align -// CHECK: call void @_ZdlPvSt11align_val_t({{.*}}[[coro_align_for_free]] +// CHECK: call void @_ZdlPvmSt11align_val_t({{.*}}%[[coro_size_for_free]],{{.*}}%[[coro_align_for_free]]) task2 f2() { co_return 43; diff --git a/clang/test/CodeGenCoroutines/coro-alloc.cpp b/clang/test/CodeGenCoroutines/coro-alloc.cpp index d026a0d7df22..7b3be7e0b7f9 100644 --- a/clang/test/CodeGenCoroutines/coro-alloc.cpp +++ b/clang/test/CodeGenCoroutines/coro-alloc.cpp @@ -70,7 +70,8 @@ extern "C" void f0(global_new_delete_tag) { // CHECK: br i1 %[[NeedDealloc]], label %[[FreeBB:.+]], label %[[Afterwards:.+]] // CHECK: [[FreeBB]]: - // CHECK: call void @_ZdlPv(ptr noundef %[[MEM]]) + // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() + // CHECK: call void @_ZdlPvm(ptr noundef %[[MEM]], i64 noundef %[[SIZE]]) // CHECK: br label %[[Afterwards]] // CHECK: [[Afterwards]]: @@ -99,7 +100,8 @@ extern "C" void f1(promise_new_tag ) { // CHECK: %[[FRAME:.+]] = call ptr @llvm.coro.begin( // CHECK: %[[MEM:.+]] = call ptr @llvm.coro.free(token %[[ID]], ptr %[[FRAME]]) - // CHECK: call void @_ZdlPv(ptr noundef %[[MEM]]) + // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() + // CHECK: call void @_ZdlPvm(ptr noundef %[[MEM]], i64 noundef %[[SIZE]]) co_return; } diff --git a/clang/test/CodeGenCoroutines/coro-cleanup.cpp b/clang/test/CodeGenCoroutines/coro-cleanup.cpp index 98f150758e2d..4e77ac25af1b 100644 --- a/clang/test/CodeGenCoroutines/coro-cleanup.cpp +++ b/clang/test/CodeGenCoroutines/coro-cleanup.cpp @@ -84,11 +84,13 @@ void f() { // CHECK: [[Cleanup]]: // CHECK: call void @_ZNSt16coroutine_traitsIJvEE12promise_typeD1Ev( // CHECK: %[[Mem0:.+]] = call ptr @llvm.coro.free( - // CHECK: call void @_ZdlPv(ptr noundef %[[Mem0]] + // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() + // CHECK: call void @_ZdlPvm(ptr noundef %[[Mem0]], i64 noundef %[[SIZE]]) // CHECK: [[Dealloc]]: // THROWEND: %[[Mem:.+]] = call ptr @llvm.coro.free( - // THROWEND: call void @_ZdlPv(ptr noundef %[[Mem]]) + // THROWEND: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() + // THROWEND: call void @_ZdlPvm(ptr noundef %[[Mem]], i64 noundef %[[SIZE]]) co_return; } diff --git a/clang/test/CodeGenCoroutines/coro-dealloc.cpp b/clang/test/CodeGenCoroutines/coro-dealloc.cpp index 1f7d04b3689e..656c9cbd3ef2 100644 --- a/clang/test/CodeGenCoroutines/coro-dealloc.cpp +++ b/clang/test/CodeGenCoroutines/coro-dealloc.cpp @@ -1,6 +1,5 @@ // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -std=c++20 \ // RUN: -S -emit-llvm %s -o - -disable-llvm-passes \ -// RUN: -fsized-deallocation \ // RUN: | FileCheck %s #include "Inputs/coroutine.h" @@ -21,7 +20,6 @@ struct task { }; // Test the compiler will chose sized deallocation correctly. -// This is only enabled with `-fsized-deallocation` which is off by default. void operator delete(void *ptr, std::size_t size) noexcept; // CHECK: define{{.*}}@_Z1fv diff --git a/clang/test/CodeGenCoroutines/coro-gro.cpp b/clang/test/CodeGenCoroutines/coro-gro.cpp index d4c3ff589e34..b62134317cef 100644 --- a/clang/test/CodeGenCoroutines/coro-gro.cpp +++ b/clang/test/CodeGenCoroutines/coro-gro.cpp @@ -51,7 +51,8 @@ int f() { // CHECK: call void @_ZNSt16coroutine_traitsIiJEE12promise_typeD1Ev( // CHECK: %[[Mem:.+]] = call ptr @llvm.coro.free( - // CHECK: call void @_ZdlPv(ptr noundef %[[Mem]]) + // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() + // CHECK: call void @_ZdlPvm(ptr noundef %[[Mem]], i64 noundef %[[SIZE]]) // Initialize retval from Gro and destroy Gro // Note this also tests delaying initialization when Gro and function return diff --git a/clang/test/CodeGenCoroutines/pr56919.cpp b/clang/test/CodeGenCoroutines/pr56919.cpp index c7de08ef72d7..baa8c27ce664 100644 --- a/clang/test/CodeGenCoroutines/pr56919.cpp +++ b/clang/test/CodeGenCoroutines/pr56919.cpp @@ -111,12 +111,15 @@ Task Bar() { co_await Baz(); } // CHECK: _Z3Quxv.destroy:{{.*}} // CHECK-NEXT: # -// CHECK-NEXT: jmp _ZdlPv +// CHECK-NEXT: movl $40, %esi +// CHECK-NEXT: jmp _ZdlPvm@PLT // CHECK: _Z3Bazv.destroy:{{.*}} // CHECK-NEXT: # -// CHECK-NEXT: jmp _ZdlPv +// CHECK-NEXT: movl $80, %esi +// CHECK-NEXT: jmp _ZdlPvm // CHECK: _Z3Barv.destroy:{{.*}} // CHECK-NEXT: # -// CHECK-NEXT: jmp _ZdlPv +// CHECK-NEXT: movl $120, %esi +// CHECK-NEXT: jmp _ZdlPvm diff --git a/clang/test/Lexer/cxx-features.cpp b/clang/test/Lexer/cxx-features.cpp index baaa9d4434e9..738c31966606 100644 --- a/clang/test/Lexer/cxx-features.cpp +++ b/clang/test/Lexer/cxx-features.cpp @@ -1,17 +1,17 @@ // RUN: %clang_cc1 -std=c++98 -fcxx-exceptions -verify %s // RUN: %clang_cc1 -std=c++11 -fcxx-exceptions -verify %s -// RUN: %clang_cc1 -std=c++14 -fcxx-exceptions -fsized-deallocation -verify %s -// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -fsized-deallocation -verify %s -// RUN: %clang_cc1 -std=c++20 -fcxx-exceptions -fsized-deallocation -verify %s -// RUN: %clang_cc1 -std=c++23 -fcxx-exceptions -fsized-deallocation -verify %s -// RUN: %clang_cc1 -std=c++2c -fcxx-exceptions -fsized-deallocation -verify %s +// RUN: %clang_cc1 -std=c++14 -fcxx-exceptions -verify %s +// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -verify %s +// RUN: %clang_cc1 -std=c++20 -fcxx-exceptions -verify %s +// RUN: %clang_cc1 -std=c++23 -fcxx-exceptions -verify %s +// RUN: %clang_cc1 -std=c++2c -fcxx-exceptions -verify %s // -// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -fsized-deallocation -frelaxed-template-template-args -DRELAXED_TEMPLATE_TEMPLATE_ARGS=1 -verify %s -// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -fsized-deallocation -DCONCEPTS_TS=1 -verify %s -// RUN: %clang_cc1 -std=c++14 -fno-rtti -fno-threadsafe-statics -verify %s -DNO_EXCEPTIONS -DNO_RTTI -DNO_THREADSAFE_STATICS -fsized-deallocation -// RUN: %clang_cc1 -std=c++14 -fchar8_t -DNO_EXCEPTIONS -DCHAR8_T -verify -fsized-deallocation %s -// RUN: %clang_cc1 -std=c++2a -fno-char8_t -DNO_EXCEPTIONS -DNO_CHAR8_T -verify -fsized-deallocation %s +// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -frelaxed-template-template-args -DRELAXED_TEMPLATE_TEMPLATE_ARGS=1 -verify %s +// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -DCONCEPTS_TS=1 -verify %s +// RUN: %clang_cc1 -std=c++14 -fno-rtti -fno-threadsafe-statics -verify %s -DNO_EXCEPTIONS -DNO_RTTI -DNO_THREADSAFE_STATICS +// RUN: %clang_cc1 -std=c++14 -fchar8_t -DNO_EXCEPTIONS -DCHAR8_T -verify %s +// RUN: %clang_cc1 -std=c++2a -fno-char8_t -DNO_EXCEPTIONS -DNO_CHAR8_T -verify %s // expected-no-diagnostics diff --git a/clang/test/PCH/cxx1z-aligned-alloc.cpp b/clang/test/PCH/cxx1z-aligned-alloc.cpp index c1becbde3bf2..cccd62859784 100644 --- a/clang/test/PCH/cxx1z-aligned-alloc.cpp +++ b/clang/test/PCH/cxx1z-aligned-alloc.cpp @@ -1,12 +1,12 @@ // No PCH: -// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -include %s -verify %s +// RUN: %clang_cc1 -pedantic -std=c++1z -include %s -verify %s // // With PCH: -// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -emit-pch %s -o %t -// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -include-pch %t -verify %s +// RUN: %clang_cc1 -pedantic -std=c++1z -emit-pch %s -o %t +// RUN: %clang_cc1 -pedantic -std=c++1z -include-pch %t -verify %s -// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -emit-pch -fpch-instantiate-templates %s -o %t -// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -include-pch %t -verify %s +// RUN: %clang_cc1 -pedantic -std=c++1z -emit-pch -fpch-instantiate-templates %s -o %t +// RUN: %clang_cc1 -pedantic -std=c++1z -include-pch %t -verify %s // expected-no-diagnostics diff --git a/clang/test/SemaCXX/MicrosoftExtensions.cpp b/clang/test/SemaCXX/MicrosoftExtensions.cpp index 7286217b1644..98c19975095b 100644 --- a/clang/test/SemaCXX/MicrosoftExtensions.cpp +++ b/clang/test/SemaCXX/MicrosoftExtensions.cpp @@ -571,11 +571,17 @@ class PR34109_class { virtual ~PR34109_class() {} }; +#if !defined(__cpp_sized_deallocation) void operator delete(void *) throw(); // expected-note@-1 {{previous declaration is here}} __declspec(dllexport) void operator delete(void *) throw(); // expected-error@-1 {{redeclaration of 'operator delete' cannot add 'dllexport' attribute}} - +#else +void operator delete(void *, unsigned int) throw(); +// expected-note@-1 {{previous declaration is here}} +__declspec(dllexport) void operator delete(void *, unsigned int) throw(); +// expected-error@-1 {{redeclaration of 'operator delete' cannot add 'dllexport' attribute}} +#endif void PR34109(int* a) { delete a; } diff --git a/clang/test/SemaCXX/builtin-operator-new-delete.cpp b/clang/test/SemaCXX/builtin-operator-new-delete.cpp index 6fcff92dc095..db15616803e3 100644 --- a/clang/test/SemaCXX/builtin-operator-new-delete.cpp +++ b/clang/test/SemaCXX/builtin-operator-new-delete.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1z -fsyntax-only -verify %s +// RUN: %clang_cc1 -std=c++1z -fno-sized-deallocation -fsyntax-only -verify %s // RUN: %clang_cc1 -std=c++03 -fsyntax-only -verify %s // RUN: %clang_cc1 -std=c++03 -faligned-allocation -fsyntax-only -verify %s // RUN: %clang_cc1 -std=c++11 -fsyntax-only -verify %s diff --git a/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp b/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp index 3ec65a6a64d1..462f1725bb1c 100644 --- a/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp +++ b/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1y -verify %s -fsized-deallocation -fexceptions -fcxx-exceptions +// RUN: %clang_cc1 -std=c++1y -verify %s -fexceptions -fcxx-exceptions using size_t = decltype(sizeof(0)); void operator delete(void *, size_t) noexcept; // expected-note {{'operator delete' declared here}} diff --git a/clang/test/SemaCXX/unavailable_aligned_allocation.cpp b/clang/test/SemaCXX/unavailable_aligned_allocation.cpp index be593eafe11d..45fdec606ad1 100644 --- a/clang/test/SemaCXX/unavailable_aligned_allocation.cpp +++ b/clang/test/SemaCXX/unavailable_aligned_allocation.cpp @@ -75,7 +75,7 @@ void testOveraligned() { // expected-error-re@-22 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is {{only|not}} available on}} // expected-note@-23 {{if you supply your own aligned allocation functions}} -// expected-error-re@-24 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is {{only|not}} available on}} +// expected-error-re@-24 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is {{only|not}} available on}} // expected-note@-25 {{if you supply your own aligned allocation functions}} // expected-error-re@-26 {{aligned allocation function of type 'void *(std::size_t, std::align_val_t, const std::nothrow_t &) noexcept' is {{only|not}} available on}} @@ -143,19 +143,19 @@ OveralignedS2::~OveralignedS2() {} // expected-no-diagnostics #else #if defined(IOS) -// expected-error@-6 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on iOS 11 or newer}}} +// expected-error@-6 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on iOS 11 or newer}}} // expected-note@-7 {{if you supply your own aligned allocation functions}} #elif defined(TVOS) -// expected-error@-9 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on tvOS 11 or newer}}} +// expected-error@-9 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on tvOS 11 or newer}}} // expected-note@-10 {{if you supply your own aligned allocation functions}} #elif defined(WATCHOS) -// expected-error@-12 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on watchOS 4 or newer}}} +// expected-error@-12 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on watchOS 4 or newer}}} // expected-note@-13 {{if you supply your own aligned allocation functions}} #elif defined(MACOS) -// expected-error@-15 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on macOS 10.13 or newer}}} +// expected-error@-15 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on macOS 10.13 or newer}}} // expected-note@-16 {{if you supply your own aligned allocation functions}} #elif defined(ZOS) -// expected-error@-18 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is not available on z/OS}}} +// expected-error@-18 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is not available on z/OS}}} // expected-note@-19 {{if you supply your own aligned allocation functions}} #endif #endif @@ -209,6 +209,9 @@ void *operator new(std::size_t __sz, std::align_val_t) { void operator delete(void *p, std::align_val_t) { } +void operator delete(void *p, std::size_t __sz, std::align_val_t) { +} + void testOveraligned2() { auto p = new ((std::align_val_t)8) OveralignedS; delete p; diff --git a/clang/tools/clang-repl/CMakeLists.txt b/clang/tools/clang-repl/CMakeLists.txt index d3dec1984b78..2b7d5f014189 100644 --- a/clang/tools/clang-repl/CMakeLists.txt +++ b/clang/tools/clang-repl/CMakeLists.txt @@ -11,6 +11,65 @@ add_clang_tool(clang-repl ClangRepl.cpp ) +if(MSVC) + set_target_properties(clang-repl PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS 1) + + # RTTI/C++ symbols + set(clang_repl_exports ${clang_repl_exports} ??_7type_info@@6B@ + ?__type_info_root_node@@3U__type_info_node@@A + ?nothrow@std@@3Unothrow_t@1@B + ) + + # Compiler added symbols for static variables. NOT for VStudio < 2015 + set(clang_repl_exports ${clang_repl_exports} _Init_thread_abort _Init_thread_epoch + _Init_thread_footer _Init_thread_header _tls_index + ) + + if(CMAKE_SIZEOF_VOID_P EQUAL 8) + # new/delete variants needed when linking to static msvc runtime (esp. Debug) + set(clang_repl_exports ${clang_repl_exports} + ??2@YAPEAX_K@Z + ??3@YAXPEAX@Z + ??_U@YAPEAX_K@Z + ??_V@YAXPEAX@Z + ??3@YAXPEAX_K@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z + ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z + ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z + ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z + ) + else() + set(clang_repl_exports ${clang_repl_exports} + ??2@YAPAXI@Z + ??3@YAXPAX@Z + ??3@YAXPAXI@Z + ??_U@YAPAXI@Z + ??_V@YAXPAX@Z + ??_V@YAXPAXI@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z + ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z + ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z + ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z + ) + endif() + + # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...' + foreach(sym ${clang_repl_exports}) + set(clang_repl_link_str "${clang_repl_link_str} /EXPORT:${sym}") + endforeach(sym ${clang_repl_exports}) + + set_property(TARGET clang-repl APPEND_STRING PROPERTY LINK_FLAGS ${clang_repl_link_str}) + +endif(MSVC) + clang_target_link_libraries(clang-repl PRIVATE clangAST clangBasic diff --git a/clang/unittests/Interpreter/CMakeLists.txt b/clang/unittests/Interpreter/CMakeLists.txt index e5a77e77de75..bc831d33bf3d 100644 --- a/clang/unittests/Interpreter/CMakeLists.txt +++ b/clang/unittests/Interpreter/CMakeLists.txt @@ -29,3 +29,62 @@ if(NOT WIN32) endif() export_executable_symbols(ClangReplInterpreterTests) + +if(MSVC) + set_target_properties(ClangReplInterpreterTests PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS 1) + + # RTTI/C++ symbols + set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} ??_7type_info@@6B@ + ?__type_info_root_node@@3U__type_info_node@@A + ?nothrow@std@@3Unothrow_t@1@B + ) + + # Compiler added symbols for static variables. NOT for VStudio < 2015 + set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} _Init_thread_abort _Init_thread_epoch + _Init_thread_footer _Init_thread_header _tls_index + ) + + if(CMAKE_SIZEOF_VOID_P EQUAL 8) + # new/delete variants needed when linking to static msvc runtime (esp. Debug) + set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} + ??2@YAPEAX_K@Z + ??3@YAXPEAX@Z + ??_U@YAPEAX_K@Z + ??_V@YAXPEAX@Z + ??3@YAXPEAX_K@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z + ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z + ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z + ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z + ) + else() + set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} + ??2@YAPAXI@Z + ??3@YAXPAX@Z + ??3@YAXPAXI@Z + ??_U@YAPAXI@Z + ??_V@YAXPAX@Z + ??_V@YAXPAXI@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z + ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z + ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z + ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z + ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z + ) + endif() + + # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...' + foreach(sym ${ClangReplInterpreterTests_exports}) + set(ClangReplInterpreterTests_link_str "${ClangReplInterpreterTests_link_str} /EXPORT:${sym}") + endforeach(sym ${ClangReplInterpreterTests_exports}) + + set_property(TARGET ClangReplInterpreterTests APPEND_STRING PROPERTY LINK_FLAGS ${ClangReplInterpreterTests_link_str}) + +endif(MSVC) diff --git a/clang/unittests/StaticAnalyzer/CallEventTest.cpp b/clang/unittests/StaticAnalyzer/CallEventTest.cpp index adbfe02a284d..7c4132788ca7 100644 --- a/clang/unittests/StaticAnalyzer/CallEventTest.cpp +++ b/clang/unittests/StaticAnalyzer/CallEventTest.cpp @@ -76,7 +76,7 @@ TEST(CXXDeallocatorCall, SimpleDestructor) { } )", Diags)); - EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 1\n"); + EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 2\n"); } } // namespace diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index c233171e63c8..96705224ee4a 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -1258,12 +1258,11 @@ code. This issue is expected to be rectified soon.

-(7): In Clang 3.7 and later, sized deallocation is only enabled -if the user passes the -fsized-deallocation flag. The user must -supply definitions of the sized deallocation functions, either by providing them -explicitly or by using a C++ standard library that does. libstdc++ -added these functions in version 5.0, and libc++ added them in -version 3.7. +(7): The user must supply definitions of the sized deallocation + functions, either by providing them explicitly or by using a C++ standard library + that does. libstdc++ added these functions in version 5.0, and + libc++ added them in version 3.7. The user can also use the + -fno-sized-deallocation option to disable sized deallocation.

diff --git a/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp b/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp index f94ceaf57dba..aa3ce210e363 100644 --- a/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp +++ b/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp @@ -21,6 +21,9 @@ // GCC doesn't support the aligned-allocation flags. // XFAIL: gcc +// TODO(mordante) fix this test after updating clang in Docker +// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18, clang-19 + // RUN: %{build} -faligned-allocation -fsized-deallocation // RUN: %{run} // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp index 21663cdf956d..0241e7cefcac 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp @@ -8,11 +8,11 @@ // test sized operator delete[] replacement. +// TODO(mordante) fix this test after updating clang in Docker +// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18, clang-19 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11 - -// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by -// default. It is only enabled when -fsized-deallocation is given. -// XFAIL: clang, apple-clang +// XFAIL: apple-clang +// XFAIL: using-built-library-before-llvm-11 #include #include diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp index a8701ce7a86c..2ab691618ea4 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp @@ -8,11 +8,11 @@ // test sized operator delete replacement. +// TODO(mordante) fix this test after updating clang in Docker +// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18, clang-19 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11 - -// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by -// default. It is only enabled when -fsized-deallocation is given. -// XFAIL: clang, apple-clang +// XFAIL: apple-clang +// XFAIL: using-built-library-before-llvm-11 #include #include -- GitLab From 1c8ba24da884b612125aafed98f67f41883dc24c Mon Sep 17 00:00:00 2001 From: David Spickett Date: Fri, 26 Apr 2024 09:58:36 +0100 Subject: [PATCH 028/301] [flang] Silence warning in release builds /home/david.spickett/llvm-project/flang/include/flang/Runtime/descriptor.h:458:30: warning: variable 'addendum' set but not used [-Wunused-but-set-variable] 458 | if (DescriptorAddendum * addendum{descriptor().Addendum()}) { | The if body is purely asserts. --- flang/include/flang/Runtime/descriptor.h | 1 + 1 file changed, 1 insertion(+) diff --git a/flang/include/flang/Runtime/descriptor.h b/flang/include/flang/Runtime/descriptor.h index 96d56d9b43a6..1b0b7e23ce6c 100644 --- a/flang/include/flang/Runtime/descriptor.h +++ b/flang/include/flang/Runtime/descriptor.h @@ -456,6 +456,7 @@ public: assert(descriptor().rank() <= maxRank); assert(descriptor().SizeInBytes() <= byteSize); if (DescriptorAddendum * addendum{descriptor().Addendum()}) { + (void)addendum; assert(hasAddendum); assert(addendum->LenParameters() <= maxLengthTypeParameters); } else { -- GitLab From e0a51553c40ec9193be30a5ee41d786ef896811b Mon Sep 17 00:00:00 2001 From: WANG Rui Date: Fri, 26 Apr 2024 17:05:03 +0800 Subject: [PATCH 029/301] [LoongArch] Simplify RISCVSubtarget. NFC The flags, initialization of the flags, and the getter methods for features defined in LoongArch.td can be generated by TableGen. --- .../lib/Target/LoongArch/LoongArchSubtarget.h | 38 +++++-------------- 1 file changed, 10 insertions(+), 28 deletions(-) diff --git a/llvm/lib/Target/LoongArch/LoongArchSubtarget.h b/llvm/lib/Target/LoongArch/LoongArchSubtarget.h index cecb4a50aa76..a6e40840517f 100644 --- a/llvm/lib/Target/LoongArch/LoongArchSubtarget.h +++ b/llvm/lib/Target/LoongArch/LoongArchSubtarget.h @@ -31,21 +31,11 @@ class StringRef; class LoongArchSubtarget : public LoongArchGenSubtargetInfo { virtual void anchor(); - bool HasLA32 = false; - bool HasLA64 = false; - bool HasBasicF = false; - bool HasBasicD = false; - bool HasExtLSX = false; - bool HasExtLASX = false; - bool HasExtLVZ = false; - bool HasExtLBT = false; - bool HasLaGlobalWithPcrel = false; - bool HasLaGlobalWithAbs = false; - bool HasLaLocalWithAbs = false; - bool HasUAL = false; - bool HasLinkerRelax = false; - bool HasExpAutoVec = false; - bool HasFrecipe = false; + +#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ + bool ATTRIBUTE = DEFAULT; +#include "LoongArchGenSubtargetInfo.inc" + unsigned GRLen = 32; MVT GRLenVT = MVT::i32; LoongArchABI::ABI TargetABI = LoongArchABI::ABI_Unknown; @@ -92,20 +82,12 @@ public: const SelectionDAGTargetInfo *getSelectionDAGInfo() const override { return &TSInfo; } + +#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \ + bool GETTER() const { return ATTRIBUTE; } +#include "LoongArchGenSubtargetInfo.inc" + bool is64Bit() const { return HasLA64; } - bool hasBasicF() const { return HasBasicF; } - bool hasBasicD() const { return HasBasicD; } - bool hasExtLSX() const { return HasExtLSX; } - bool hasExtLASX() const { return HasExtLASX; } - bool hasExtLVZ() const { return HasExtLVZ; } - bool hasExtLBT() const { return HasExtLBT; } - bool hasLaGlobalWithPcrel() const { return HasLaGlobalWithPcrel; } - bool hasLaGlobalWithAbs() const { return HasLaGlobalWithAbs; } - bool hasLaLocalWithAbs() const { return HasLaLocalWithAbs; } - bool hasUAL() const { return HasUAL; } - bool hasLinkerRelax() const { return HasLinkerRelax; } - bool hasExpAutoVec() const { return HasExpAutoVec; } - bool hasFrecipe() const { return HasFrecipe; } MVT getGRLenVT() const { return GRLenVT; } unsigned getGRLen() const { return GRLen; } LoongArchABI::ABI getTargetABI() const { return TargetABI; } -- GitLab From 15f02723d49be9a828fbf072966a225babd60457 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Thu, 25 Apr 2024 07:50:30 +0200 Subject: [PATCH 030/301] [clang][Interp] Improve support for virtual bases Fix initializing virtual bases. We only consider their base size, not their virtual size because they get flattened into the Record hierarchy when we create them. Fix that and also virtual derived-to-base casts. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 25 +++++++- clang/lib/AST/Interp/ByteCodeStmtGen.cpp | 22 +++++-- clang/lib/AST/Interp/Descriptor.cpp | 74 ++++++++++++++++------ clang/lib/AST/Interp/Interp.h | 3 + clang/test/AST/Interp/cxx23.cpp | 16 +++++ clang/test/AST/Interp/records.cpp | 79 ++++++++++++++++++++++++ 6 files changed, 192 insertions(+), 27 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index bbd2771d3712..588ffa55c11e 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -110,10 +110,29 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { if (!this->visit(SubExpr)) return false; - unsigned DerivedOffset = - collectBaseOffset(CE->getType(), SubExpr->getType()); + const auto extractRecordDecl = [](QualType Ty) -> const CXXRecordDecl * { + if (const auto *PT = dyn_cast(Ty)) + return PT->getPointeeType()->getAsCXXRecordDecl(); + return Ty->getAsCXXRecordDecl(); + }; - return this->emitGetPtrBasePop(DerivedOffset, CE); + // FIXME: We can express a series of non-virtual casts as a single + // GetPtrBasePop op. + QualType CurType = SubExpr->getType(); + for (const CXXBaseSpecifier *B : CE->path()) { + if (B->isVirtual()) { + if (!this->emitGetPtrVirtBasePop(extractRecordDecl(B->getType()), CE)) + return false; + CurType = B->getType(); + } else { + unsigned DerivedOffset = collectBaseOffset(B->getType(), CurType); + if (!this->emitGetPtrBasePop(DerivedOffset, CE)) + return false; + CurType = B->getType(); + } + } + + return true; } case CK_BaseToDerived: { diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp index 36dab6252ece..9b8e64f11385 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp @@ -189,14 +189,24 @@ bool ByteCodeStmtGen::visitFunc(const FunctionDecl *F) { if (!emitFieldInitializer(F, F->Offset, InitExpr)) return false; } else if (const Type *Base = Init->getBaseClass()) { - // Base class initializer. - // Get This Base and call initializer on it. const auto *BaseDecl = Base->getAsCXXRecordDecl(); assert(BaseDecl); - const Record::Base *B = R->getBase(BaseDecl); - assert(B); - if (!this->emitGetPtrThisBase(B->Offset, InitExpr)) - return false; + + if (Init->isBaseVirtual()) { + const Record::Base *B = R->getVirtualBase(BaseDecl); + assert(B); + if (!this->emitGetPtrThisVirtBase(BaseDecl, InitExpr)) + return false; + + } else { + // Base class initializer. + // Get This Base and call initializer on it. + const Record::Base *B = R->getBase(BaseDecl); + assert(B); + if (!this->emitGetPtrThisBase(B->Offset, InitExpr)) + return false; + } + if (!this->visitInitializer(InitExpr)) return false; if (!this->emitFinishInitPop(InitExpr)) diff --git a/clang/lib/AST/Interp/Descriptor.cpp b/clang/lib/AST/Interp/Descriptor.cpp index a4ccc0236d29..954c58c8cb37 100644 --- a/clang/lib/AST/Interp/Descriptor.cpp +++ b/clang/lib/AST/Interp/Descriptor.cpp @@ -136,28 +136,66 @@ static void moveArrayDesc(Block *B, const std::byte *Src, std::byte *Dst, } } +static void initField(Block *B, std::byte *Ptr, bool IsConst, bool IsMutable, + bool IsActive, const Descriptor *D, + unsigned FieldOffset) { + bool IsUnion = false; // FIXME + auto *Desc = reinterpret_cast(Ptr + FieldOffset) - 1; + Desc->Offset = FieldOffset; + Desc->Desc = D; + Desc->IsInitialized = D->IsArray; + Desc->IsBase = false; + Desc->IsActive = IsActive && !IsUnion; + Desc->IsConst = IsConst || D->IsConst; + Desc->IsFieldMutable = IsMutable || D->IsMutable; + + if (auto Fn = D->CtorFn) + Fn(B, Ptr + FieldOffset, Desc->IsConst, Desc->IsFieldMutable, + Desc->IsActive, D); +} + +static void initBase(Block *B, std::byte *Ptr, bool IsConst, bool IsMutable, + bool IsActive, const Descriptor *D, unsigned FieldOffset, + bool IsVirtualBase) { + assert(D); + assert(D->ElemRecord); + + bool IsUnion = D->ElemRecord->isUnion(); + auto *Desc = reinterpret_cast(Ptr + FieldOffset) - 1; + Desc->Offset = FieldOffset; + Desc->Desc = D; + Desc->IsInitialized = D->IsArray; + Desc->IsBase = true; + Desc->IsActive = IsActive && !IsUnion; + Desc->IsConst = IsConst || D->IsConst; + Desc->IsFieldMutable = IsMutable || D->IsMutable; + + for (const auto &V : D->ElemRecord->bases()) + initBase(B, Ptr + FieldOffset, IsConst, IsMutable, IsActive, V.Desc, + V.Offset, false); + for (const auto &F : D->ElemRecord->fields()) + initField(B, Ptr + FieldOffset, IsConst, IsMutable, IsActive, F.Desc, + F.Offset); + + // If this is initializing a virtual base, we do NOT want to consider its + // virtual bases, those are already flattened into the parent record when + // creating it. + if (IsVirtualBase) + return; + + for (const auto &V : D->ElemRecord->virtual_bases()) + initBase(B, Ptr + FieldOffset, IsConst, IsMutable, IsActive, V.Desc, + V.Offset, true); +} + static void ctorRecord(Block *B, std::byte *Ptr, bool IsConst, bool IsMutable, bool IsActive, const Descriptor *D) { - const bool IsUnion = D->ElemRecord->isUnion(); - auto CtorSub = [=](unsigned SubOff, const Descriptor *F, bool IsBase) { - auto *Desc = reinterpret_cast(Ptr + SubOff) - 1; - Desc->Offset = SubOff; - Desc->Desc = F; - Desc->IsInitialized = F->IsArray && !IsBase; - Desc->IsBase = IsBase; - Desc->IsActive = IsActive && !IsUnion; - Desc->IsConst = IsConst || F->IsConst; - Desc->IsFieldMutable = IsMutable || F->IsMutable; - if (auto Fn = F->CtorFn) - Fn(B, Ptr + SubOff, Desc->IsConst, Desc->IsFieldMutable, Desc->IsActive, - F); - }; - for (const auto &B : D->ElemRecord->bases()) - CtorSub(B.Offset, B.Desc, /*isBase=*/true); + for (const auto &V : D->ElemRecord->bases()) + initBase(B, Ptr, IsConst, IsMutable, IsActive, V.Desc, V.Offset, false); for (const auto &F : D->ElemRecord->fields()) - CtorSub(F.Offset, F.Desc, /*isBase=*/false); + initField(B, Ptr, IsConst, IsMutable, IsActive, F.Desc, F.Offset); for (const auto &V : D->ElemRecord->virtual_bases()) - CtorSub(V.Offset, V.Desc, /*isBase=*/true); + initBase(B, Ptr, IsConst, IsMutable, IsActive, V.Desc, V.Offset, true); } static void dtorRecord(Block *B, std::byte *Ptr, const Descriptor *D) { diff --git a/clang/lib/AST/Interp/Interp.h b/clang/lib/AST/Interp/Interp.h index 0e9f287cd221..9da0286deada 100644 --- a/clang/lib/AST/Interp/Interp.h +++ b/clang/lib/AST/Interp/Interp.h @@ -1366,6 +1366,9 @@ inline bool GetPtrVirtBasePop(InterpState &S, CodePtr OpPC, const Pointer &Ptr = S.Stk.pop(); if (!CheckNull(S, OpPC, Ptr, CSK_Base)) return false; + if (Ptr.isDummy()) // FIXME: Once we have type info for dummy pointers, this + // needs to go. + return false; return VirtBaseHelper(S, OpPC, D, Ptr); } diff --git a/clang/test/AST/Interp/cxx23.cpp b/clang/test/AST/Interp/cxx23.cpp index f0325eef6d87..13cc9f43febc 100644 --- a/clang/test/AST/Interp/cxx23.cpp +++ b/clang/test/AST/Interp/cxx23.cpp @@ -141,3 +141,19 @@ struct check_ice { }; }; static_assert(check_ice<42>::x == 42); + + +namespace VirtualBases { + namespace One { + struct U { int n; }; + struct V : U { int n; }; + struct A : virtual V { int n; }; + struct Aa { int n; }; + struct B : virtual A, Aa {}; + struct C : virtual A, Aa {}; + struct D : B, C {}; + + /// Calls the constructor of D. + D d; + } +} diff --git a/clang/test/AST/Interp/records.cpp b/clang/test/AST/Interp/records.cpp index 3e52354a4a10..9307b9c090c5 100644 --- a/clang/test/AST/Interp/records.cpp +++ b/clang/test/AST/Interp/records.cpp @@ -1330,3 +1330,82 @@ namespace UnnamedBitFields { static_assert(a.f == 1.0, ""); static_assert(a.c == 'a', ""); } + +/// FIXME: This still doesn't work in the new interpreter because +/// we lack type information for dummy pointers. +namespace VirtualBases { + /// This used to crash. + namespace One { + class A { + protected: + int x; + }; + class B : public virtual A { + public: + int getX() { return x; } // ref-note {{declared here}} + }; + + class DV : virtual public B{}; + + void foo() { + DV b; + int a[b.getX()]; // both-warning {{variable length arrays}} \ + // ref-note {{non-constexpr function 'getX' cannot be used}} + } + } + + namespace Two { + struct U { int n; }; + struct A : virtual U { int n; }; + struct B : A {}; + B a; + static_assert((U*)(A*)(&a) == (U*)(&a), ""); + + struct C : virtual A {}; + struct D : B, C {}; + D d; + constexpr B *p = &d; + constexpr C *q = &d; + static_assert((A*)p == (A*)q, ""); // both-error {{failed}} + } + + namespace Three { + struct U { int n; }; + struct V : U { int n; }; + struct A : virtual V { int n; }; + struct Aa { int n; }; + struct B : virtual A, Aa {}; + + struct C : virtual A, Aa {}; + + struct D : B, C {}; + + D d; + + constexpr B *p = &d; + constexpr C *q = &d; + + static_assert((void*)p != (void*)q, ""); + static_assert((A*)p == (A*)q, ""); + static_assert((Aa*)p != (Aa*)q, ""); + + constexpr V *v = p; + constexpr V *w = q; + constexpr V *x = (A*)p; + static_assert(v == w, ""); + static_assert(v == x, ""); + + static_assert((U*)&d == p, ""); + static_assert((U*)&d == q, ""); + static_assert((U*)&d == v, ""); + static_assert((U*)&d == w, ""); + static_assert((U*)&d == x, ""); + + struct X {}; + struct Y1 : virtual X {}; + struct Y2 : X {}; + struct Z : Y1, Y2 {}; + Z z; + static_assert((X*)(Y1*)&z != (X*)(Y2*)&z, ""); + } +} -- GitLab From 6578356a4e3e6acd7983c74feab43ac96925894c Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 26 Apr 2024 10:28:52 +0100 Subject: [PATCH 031/301] [TableGen] Ignore inaccessible memory when checking pattern flags (#90061) In the AMDGPU backend we have some cases where we'd like to mark an intrinsic as IntrInaccessibleMemOnly to model dependencies, but the corresponding MachineInstrs use uses/defs of a special physical register to express the same thing. In this case TableGen would complain: Pattern doesn't match mayLoad/mayStore = 0 but the error is not useful. --- llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp index 88d353e89a46..e0e31739e262 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp @@ -3616,7 +3616,15 @@ public: hasChain = true; if (const CodeGenIntrinsic *IntInfo = N.getIntrinsicInfo(CDP)) { - ModRefInfo MR = IntInfo->ME.getModRef(); + // Ignore reads/writes to inaccessible memory. These should not imply + // mayLoad/mayStore on the instruction because they are often used to + // model dependencies that Machine IR expresses as uses/defs of a + // special physical register. + ModRefInfo MR = ModRefInfo::NoModRef; + for (MemoryEffects::Location Loc : MemoryEffects::locations()) { + if (Loc != MemoryEffects::Location::InaccessibleMem) + MR |= IntInfo->ME.getModRef(); + } // If this is an intrinsic, analyze it. if (isRefSet(MR)) mayLoad = true; // These may load memory. -- GitLab From 23b6709c72357c8b8f0ffa6cdbd860977441982b Mon Sep 17 00:00:00 2001 From: Antonio Frighetto Date: Thu, 25 Apr 2024 09:49:24 +0200 Subject: [PATCH 032/301] [AArch64] Drop poison-generating flags in `genSubAdd2SubSub` combiner A miscompilation issue has been addressed with improved handling. Fixes: https://github.com/llvm/llvm-project/issues/88950. --- llvm/lib/Target/AArch64/AArch64InstrInfo.cpp | 15 ++++++++--- .../AArch64/machine-combiner-subadd2.mir | 27 +++++++++++++++++++ 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp index 7bf06e71a030..55fecc4b4845 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.cpp @@ -6924,19 +6924,26 @@ genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI, assert((Opcode == AArch64::SUBWrr || Opcode == AArch64::SUBXrr) && "Unexpected instruction opcode."); + uint32_t Flags = Root.mergeFlagsWith(*AddMI); + Flags &= ~MachineInstr::NoSWrap; + Flags &= ~MachineInstr::NoUWrap; + MachineInstrBuilder MIB1 = BuildMI(MF, MIMetadata(Root), TII->get(Opcode), NewVR) .addReg(RegA, getKillRegState(RegAIsKill)) - .addReg(RegB, getKillRegState(RegBIsKill)); + .addReg(RegB, getKillRegState(RegBIsKill)) + .setMIFlags(Flags); MachineInstrBuilder MIB2 = BuildMI(MF, MIMetadata(Root), TII->get(Opcode), ResultReg) .addReg(NewVR, getKillRegState(true)) - .addReg(RegC, getKillRegState(RegCIsKill)); + .addReg(RegC, getKillRegState(RegCIsKill)) + .setMIFlags(Flags); InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0)); InsInstrs.push_back(MIB1); InsInstrs.push_back(MIB2); DelInstrs.push_back(AddMI); + DelInstrs.push_back(&Root); } /// When getMachineCombinerPatterns() finds potential patterns, @@ -6966,13 +6973,13 @@ void AArch64InstrInfo::genAlternativeCodeSequence( // ==> (A - B) - C genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 1, InstrIdxForVirtReg); - break; + return; case AArch64MachineCombinerPattern::SUBADD_OP2: // A - (B + C) // ==> (A - C) - B genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 2, InstrIdxForVirtReg); - break; + return; case AArch64MachineCombinerPattern::MULADDW_OP1: case AArch64MachineCombinerPattern::MULADDX_OP1: // MUL I=A,B,0 diff --git a/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir b/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir index d1770bb25fae..0b09e8a4b5cd 100644 --- a/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir +++ b/llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir @@ -237,3 +237,30 @@ body: | RET_ReallyLR implicit $w0 ... +--- +# Drop nowrap flags in SUB + +# CHECK-LABEL: name: test8 +# CHECK: %7:gpr64 = SUBXrr %1, %0 +# CHECK-NEXT: %4:gpr64common = SUBXrr killed %7, killed %2 + +name: test8 +registers: + - { id: 0, class: gpr64 } + - { id: 1, class: gpr64 } + - { id: 2, class: gpr64common } + - { id: 3, class: gpr64 } + - { id: 4, class: gpr64common } + - { id: 5, class: gpr64 } +body: | + bb.0: + %1:gpr64 = COPY $x1 + %0:gpr64 = COPY $x0 + %2:gpr64common = ORRXri %0:gpr64, 4096 + %3:gpr64 = ADDXrr killed %2:gpr64common, %0:gpr64 + %4:gpr64common = nsw SUBSXrr %1:gpr64, killed %3:gpr64, implicit-def dead $nzcv + %5:gpr64 = SUBSXri %4:gpr64common, 0, 0, implicit-def $nzcv + $x0 = COPY %5:gpr64 + RET_ReallyLR implicit $x0 + +... -- GitLab From 74a5e7784b32aba5670ff427b158d1e6e38012f1 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Fri, 26 Apr 2024 02:41:21 -0700 Subject: [PATCH 033/301] [llvm-exegesis] Close file descriptors after use (#86584) There are several insstances in the subprocess executor in llvm-exegesis where we fail to close file descriptors after using them. This leaves them open, which can cause issues later on if a third-party binary is using the exegesis libraries and executing many blocks before exiting. Leaving the descriptors open until process exit is also bad practice. This patch fixes that by explicitly calling close() when we are done with a specific file descriptor. This patch fixes #86583. --- llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp | 2 ++ llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp index 498308e2edbe..ed53f8fabb17 100644 --- a/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp +++ b/llvm/tools/llvm-exegesis/lib/BenchmarkRunner.cpp @@ -18,6 +18,7 @@ #include "PerfHelper.h" #include "SubprocessMemory.h" #include "Target.h" +#include "llvm/ADT/ScopeExit.h" #include "llvm/ADT/StringExtras.h" #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Twine.h" @@ -283,6 +284,7 @@ private: SmallVectorImpl &CounterValues, ArrayRef ValidationCounters, SmallVectorImpl &ValidationCounterValues) const { + auto WriteFDClose = make_scope_exit([WriteFD]() { close(WriteFD); }); const ExegesisTarget &ET = State.getExegesisTarget(); auto CounterOrError = ET.createCounter(CounterName, State, ValidationCounters, ChildPID); diff --git a/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp b/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp index 1d44e09ad61e..cda044050502 100644 --- a/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp +++ b/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp @@ -8,6 +8,7 @@ #include "SubprocessMemory.h" #include "Error.h" +#include "llvm/ADT/ScopeExit.h" #include "llvm/Support/Error.h" #include "llvm/Support/FormatVariadic.h" #include @@ -56,6 +57,8 @@ Error SubprocessMemory::initializeSubprocessMemory(pid_t ProcessID) { return make_error( "Failed to create shared memory object for auxiliary memory: " + Twine(strerror(errno))); + auto AuxiliaryMemoryFDClose = + make_scope_exit([AuxiliaryMemoryFD]() { close(AuxiliaryMemoryFD); }); if (ftruncate(AuxiliaryMemoryFD, AuxiliaryMemorySize) != 0) { return make_error("Truncating the auxiliary memory failed: " + Twine(strerror(errno))); @@ -78,6 +81,8 @@ Error SubprocessMemory::addMemoryDefinition( return make_error( "Failed to create shared memory object for memory definition: " + Twine(strerror(errno))); + auto SharedMemoryFDClose = + make_scope_exit([SharedMemoryFD]() { close(SharedMemoryFD); }); if (ftruncate(SharedMemoryFD, MemVal.SizeBytes) != 0) { return make_error("Truncating a memory definiton failed: " + Twine(strerror(errno))); -- GitLab From 24c6409d56e43a7af3f6be6dd3e7267e243fb162 Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Fri, 26 Apr 2024 17:53:31 +0800 Subject: [PATCH 034/301] [clang] Fix -Wunused-variable in ByteCodeStmtGen.cpp (NFC) llvm-project/clang/lib/AST/Interp/ByteCodeStmtGen.cpp:196:31: error: unused variable 'B' [-Werror,-Wunused-variable] const Record::Base *B = R->getVirtualBase(BaseDecl); ^ 1 error generated. --- clang/lib/AST/Interp/ByteCodeStmtGen.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp index 9b8e64f11385..ec2fe39a8aea 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp @@ -193,8 +193,7 @@ bool ByteCodeStmtGen::visitFunc(const FunctionDecl *F) { assert(BaseDecl); if (Init->isBaseVirtual()) { - const Record::Base *B = R->getVirtualBase(BaseDecl); - assert(B); + assert(R->getVirtualBase(BaseDecl)); if (!this->emitGetPtrThisVirtBase(BaseDecl, InitExpr)) return false; -- GitLab From 08dc03c57078ab806dbf015554b9faf38ccc4d4d Mon Sep 17 00:00:00 2001 From: Tom Eccles Date: Fri, 26 Apr 2024 10:54:46 +0100 Subject: [PATCH 035/301] [flang][NFC] Use tablegen to create LoopVersioning constructor (#90037) The pass is currently defined as only considering function arguments as candidates for the optimization. I would prefer to generalise the pass for other top level operations only when there is a concrete use case before making too many assumptions about the current set of top level operations. Therefore I have not adapted this pass to run on all top level operations. --- flang/include/flang/Optimizer/Transforms/Passes.h | 2 +- flang/include/flang/Optimizer/Transforms/Passes.td | 1 - flang/include/flang/Tools/CLOptions.inc | 2 +- flang/lib/Optimizer/Transforms/LoopVersioning.cpp | 4 ---- 4 files changed, 2 insertions(+), 7 deletions(-) diff --git a/flang/include/flang/Optimizer/Transforms/Passes.h b/flang/include/flang/Optimizer/Transforms/Passes.h index fd7a4a3883c9..613e60695465 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.h +++ b/flang/include/flang/Optimizer/Transforms/Passes.h @@ -47,6 +47,7 @@ namespace fir { #define GEN_PASS_DECL_POLYMORPHICOPCONVERSION #define GEN_PASS_DECL_OPENACCDATAOPERANDCONVERSION #define GEN_PASS_DECL_ADDDEBUGINFO +#define GEN_PASS_DECL_LOOPVERSIONING #include "flang/Optimizer/Transforms/Passes.h.inc" std::unique_ptr createAffineDemotionPass(); @@ -62,7 +63,6 @@ std::unique_ptr createStackArraysPass(); std::unique_ptr createAliasTagsPass(); std::unique_ptr createAddDebugInfoPass(fir::AddDebugInfoOptions options = {}); -std::unique_ptr createLoopVersioningPass(); std::unique_ptr createMemoryAllocationPass(bool dynOnHeap, std::size_t maxStackSize); diff --git a/flang/include/flang/Optimizer/Transforms/Passes.td b/flang/include/flang/Optimizer/Transforms/Passes.td index c3d5c336af40..383b1628b715 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.td +++ b/flang/include/flang/Optimizer/Transforms/Passes.td @@ -321,7 +321,6 @@ def LoopVersioning : Pass<"loop-versioning", "mlir::func::FuncOp"> { an array has element sized stride. The element sizes stride allows some loops to be vectorized as well as other loop optimizations. }]; - let constructor = "::fir::createLoopVersioningPass()"; let dependentDialects = [ "fir::FIROpsDialect" ]; } diff --git a/flang/include/flang/Tools/CLOptions.inc b/flang/include/flang/Tools/CLOptions.inc index f24716333d9a..0b031abe0e60 100644 --- a/flang/include/flang/Tools/CLOptions.inc +++ b/flang/include/flang/Tools/CLOptions.inc @@ -253,7 +253,7 @@ inline void createDefaultFIROptimizerPassPipeline( } if (pc.LoopVersioning) - pm.addPass(fir::createLoopVersioningPass()); + pm.addPass(fir::createLoopVersioning()); pm.addPass(mlir::createCSEPass()); diff --git a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp index 7cbd2dd1f897..0afc9c24b45b 100644 --- a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp +++ b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp @@ -556,7 +556,3 @@ void LoopVersioningPass::runOnOperation() { LLVM_DEBUG(llvm::dbgs() << "=== End " DEBUG_TYPE " ===\n"); } - -std::unique_ptr fir::createLoopVersioningPass() { - return std::make_unique(); -} -- GitLab From 46b66dfd31ed0206b4444b77612df42193fe5b42 Mon Sep 17 00:00:00 2001 From: Tom Eccles Date: Fri, 26 Apr 2024 10:55:56 +0100 Subject: [PATCH 036/301] [flang][NFC] use tablegen to create StackArrays constructor (#90038) Stack arrays needs to stay running only on func.func because it needs to know which block terminators can end the function (rather than just branch between unstructured control flow). A similar concept does not exist at the more abstract level of "any top level mlir operation". For example, it currently looks for func::ReturnOp and fir::UnreachableOp as points when execution can end. If this were to be run on omp.declare_reduction, it would also need to understand omp.YieldOp (perhaps only when omp.declare_reduction is the parent). There isn't a generic concept in MLIR for this. --- flang/include/flang/Optimizer/Transforms/Passes.h | 2 +- flang/include/flang/Optimizer/Transforms/Passes.td | 1 - flang/include/flang/Tools/CLOptions.inc | 2 +- flang/lib/Optimizer/Transforms/StackArrays.cpp | 4 ---- 4 files changed, 2 insertions(+), 7 deletions(-) diff --git a/flang/include/flang/Optimizer/Transforms/Passes.h b/flang/include/flang/Optimizer/Transforms/Passes.h index 613e60695465..5532271bad70 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.h +++ b/flang/include/flang/Optimizer/Transforms/Passes.h @@ -47,6 +47,7 @@ namespace fir { #define GEN_PASS_DECL_POLYMORPHICOPCONVERSION #define GEN_PASS_DECL_OPENACCDATAOPERANDCONVERSION #define GEN_PASS_DECL_ADDDEBUGINFO +#define GEN_PASS_DECL_STACKARRAYS #define GEN_PASS_DECL_LOOPVERSIONING #include "flang/Optimizer/Transforms/Passes.h.inc" @@ -59,7 +60,6 @@ createExternalNameConversionPass(bool appendUnderscore); std::unique_ptr createMemDataFlowOptPass(); std::unique_ptr createPromoteToAffinePass(); std::unique_ptr createMemoryAllocationPass(); -std::unique_ptr createStackArraysPass(); std::unique_ptr createAliasTagsPass(); std::unique_ptr createAddDebugInfoPass(fir::AddDebugInfoOptions options = {}); diff --git a/flang/include/flang/Optimizer/Transforms/Passes.td b/flang/include/flang/Optimizer/Transforms/Passes.td index 383b1628b715..6b490569e01d 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.td +++ b/flang/include/flang/Optimizer/Transforms/Passes.td @@ -257,7 +257,6 @@ def StackArrays : Pass<"stack-arrays", "mlir::ModuleOp"> { allocations. }]; let dependentDialects = [ "fir::FIROpsDialect" ]; - let constructor = "::fir::createStackArraysPass()"; } def AddAliasTags : Pass<"fir-add-alias-tags", "mlir::ModuleOp"> { diff --git a/flang/include/flang/Tools/CLOptions.inc b/flang/include/flang/Tools/CLOptions.inc index 0b031abe0e60..4fab9ef423bc 100644 --- a/flang/include/flang/Tools/CLOptions.inc +++ b/flang/include/flang/Tools/CLOptions.inc @@ -258,7 +258,7 @@ inline void createDefaultFIROptimizerPassPipeline( pm.addPass(mlir::createCSEPass()); if (pc.StackArrays) - pm.addPass(fir::createStackArraysPass()); + pm.addPass(fir::createStackArrays()); else fir::addMemoryAllocationOpt(pm); diff --git a/flang/lib/Optimizer/Transforms/StackArrays.cpp b/flang/lib/Optimizer/Transforms/StackArrays.cpp index 1c213abefe6f..c81524dd16a7 100644 --- a/flang/lib/Optimizer/Transforms/StackArrays.cpp +++ b/flang/lib/Optimizer/Transforms/StackArrays.cpp @@ -776,7 +776,3 @@ void StackArraysPass::runOnFunc(mlir::Operation *func) { signalPassFailure(); } } - -std::unique_ptr fir::createStackArraysPass() { - return std::make_unique(); -} -- GitLab From 213ab9610ced9152f70f5b9777347c28e777a0ff Mon Sep 17 00:00:00 2001 From: Tom Eccles Date: Fri, 26 Apr 2024 10:56:56 +0100 Subject: [PATCH 037/301] [flang][NFC] Use tablegen to reduce MemoryAllocationOpt boilerplate (#90062) This is another one that runs on functions but isn't appropriate to also run on other top level operations. It needs to find all paths that return from the function to free heap allocated memory. There isn't a generic concept for general top level operations which is equivalent to looking for function returns. I removed the manual definition of the options structure because there is already an identical definition in tablegen and the options are documented in Passes.td. --- .../flang/Optimizer/Transforms/Passes.h | 3 -- .../flang/Optimizer/Transforms/Passes.td | 1 - flang/include/flang/Tools/CLOptions.inc | 4 +-- .../Optimizer/Transforms/MemoryAllocation.cpp | 30 +++++-------------- 4 files changed, 9 insertions(+), 29 deletions(-) diff --git a/flang/include/flang/Optimizer/Transforms/Passes.h b/flang/include/flang/Optimizer/Transforms/Passes.h index 5532271bad70..547fe742967a 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.h +++ b/flang/include/flang/Optimizer/Transforms/Passes.h @@ -59,13 +59,10 @@ std::unique_ptr createExternalNameConversionPass(bool appendUnderscore); std::unique_ptr createMemDataFlowOptPass(); std::unique_ptr createPromoteToAffinePass(); -std::unique_ptr createMemoryAllocationPass(); std::unique_ptr createAliasTagsPass(); std::unique_ptr createAddDebugInfoPass(fir::AddDebugInfoOptions options = {}); -std::unique_ptr -createMemoryAllocationPass(bool dynOnHeap, std::size_t maxStackSize); std::unique_ptr createAnnotateConstantOperandsPass(); std::unique_ptr createAlgebraicSimplificationPass(); std::unique_ptr diff --git a/flang/include/flang/Optimizer/Transforms/Passes.td b/flang/include/flang/Optimizer/Transforms/Passes.td index 6b490569e01d..020b8a6b64a9 100644 --- a/flang/include/flang/Optimizer/Transforms/Passes.td +++ b/flang/include/flang/Optimizer/Transforms/Passes.td @@ -247,7 +247,6 @@ def MemoryAllocationOpt : Pass<"memory-allocation-opt", "mlir::func::FuncOp"> { "std::size_t", /*default=*/"~static_cast(0)", "Set maximum number of elements of an array allocated on the stack."> ]; - let constructor = "::fir::createMemoryAllocationPass()"; } def StackArrays : Pass<"stack-arrays", "mlir::ModuleOp"> { diff --git a/flang/include/flang/Tools/CLOptions.inc b/flang/include/flang/Tools/CLOptions.inc index 4fab9ef423bc..8f197038f2ba 100644 --- a/flang/include/flang/Tools/CLOptions.inc +++ b/flang/include/flang/Tools/CLOptions.inc @@ -163,8 +163,8 @@ inline void addAVC( inline void addMemoryAllocationOpt(mlir::PassManager &pm) { addNestedPassConditionally(pm, disableFirMao, [&]() { - return fir::createMemoryAllocationPass( - dynamicArrayStackToHeapAllocation, arrayStackAllocationThreshold); + return fir::createMemoryAllocationOpt( + {dynamicArrayStackToHeapAllocation, arrayStackAllocationThreshold}); }); } diff --git a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp index 166a6b10def2..40b452a6202b 100644 --- a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp +++ b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp @@ -28,17 +28,6 @@ namespace fir { static constexpr std::size_t unlimitedArraySize = ~static_cast(0); namespace { -struct MemoryAllocationOptions { - // Always move dynamic array allocations to the heap. This may result in more - // heap fragmentation, so may impact performance negatively. - bool dynamicArrayOnHeap = false; - - // Number of elements in array threshold for moving to heap. In environments - // with limited stack size, moving large arrays to the heap can avoid running - // out of stack space. - std::size_t maxStackArraySize = unlimitedArraySize; -}; - class ReturnAnalysis { public: MLIR_DEFINE_EXPLICIT_INTERNAL_INLINE_TYPE_ID(ReturnAnalysis) @@ -68,8 +57,9 @@ private: /// Return `true` if this allocation is to remain on the stack (`fir.alloca`). /// Otherwise the allocation should be moved to the heap (`fir.allocmem`). -static inline bool keepStackAllocation(fir::AllocaOp alloca, mlir::Block *entry, - const MemoryAllocationOptions &options) { +static inline bool +keepStackAllocation(fir::AllocaOp alloca, mlir::Block *entry, + const fir::MemoryAllocationOptOptions &options) { // Limitation: only arrays allocated on the stack in the entry block are // considered for now. // TODO: Generalize the algorithm and placement of the freemem nodes. @@ -168,6 +158,9 @@ public: options = {dynOnHeap, maxStackSize}; } + MemoryAllocationOpt(const fir::MemoryAllocationOptOptions &options) + : options{options} {} + /// Override `options` if command-line options have been set. inline void useCommandLineOptions() { if (dynamicArrayOnHeap) @@ -211,15 +204,6 @@ public: } private: - MemoryAllocationOptions options; + fir::MemoryAllocationOptOptions options; }; } // namespace - -std::unique_ptr fir::createMemoryAllocationPass() { - return std::make_unique(); -} - -std::unique_ptr -fir::createMemoryAllocationPass(bool dynOnHeap, std::size_t maxStackSize) { - return std::make_unique(dynOnHeap, maxStackSize); -} -- GitLab From 2e3e0868748635b779ba89a772eae3664bd822e4 Mon Sep 17 00:00:00 2001 From: CL <48561979+coderchenlin@users.noreply.github.com> Date: Fri, 26 Apr 2024 17:57:37 +0800 Subject: [PATCH 038/301] [BasicBlockUtils] Remove redundant llvm.dbg instructions after blocks to reduce compile time (#89069) this patch is to fix the compile time for some cases, before this change, some targets (riscv-64, ve) will spend much more compile time on this case (https://godbolt.org/z/rrov17cTo). With this change, the compile time was reduced a lot. Fixes https://github.com/llvm/llvm-project/issues/89073 PR: https://github.com/llvm/llvm-project/pull/89069 --- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 4 ++ .../LoopUnroll/unroll-remove-redundant-dbg.ll | 45 +++++++++++++++++++ .../SimplifyCFG/hoist-dbgvalue-inlined.ll | 1 - .../Transforms/SimplifyCFG/hoist-dbgvalue.ll | 1 - 4 files changed, 49 insertions(+), 2 deletions(-) create mode 100644 llvm/test/Transforms/LoopUnroll/unroll-remove-redundant-dbg.ll diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp index 5396038d8b92..4941f92b94f0 100644 --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -333,6 +333,10 @@ bool llvm::MergeBlockIntoPredecessor(BasicBlock *BB, DomTreeUpdater *DTU, // Finally, erase the old block and update dominator info. DeleteDeadBlock(BB, DTU); + // Remove redundant "llvm.dbg" instrunctions after blocks have been merged. + if (PredBB->getParent()->getSubprogram()) + RemoveRedundantDbgInstrs(PredBB); + return true; } diff --git a/llvm/test/Transforms/LoopUnroll/unroll-remove-redundant-dbg.ll b/llvm/test/Transforms/LoopUnroll/unroll-remove-redundant-dbg.ll new file mode 100644 index 000000000000..66cd4d454443 --- /dev/null +++ b/llvm/test/Transforms/LoopUnroll/unroll-remove-redundant-dbg.ll @@ -0,0 +1,45 @@ +; RUN: opt < %s -S -passes=loop-unroll | FileCheck %s + +define i64 @d(i1 %tobool.not, i32 %add, i64 %conv23) !dbg !14{ +entry: + br label %for.body + +for.body: ; preds = %for.body, %entry + ; There should be only one "llvm.dbg.vale" after loop unrolling + ; CHECK: call void @llvm.dbg.value + ; CHECK-NOT: call void @llvm.dbg.value + + %k.045 = phi i64 [ 0, %entry ], [ %k.046, %for.body ] + tail call void @llvm.dbg.value(metadata i32 0, metadata !13, metadata !DIExpression()), !dbg !17 + %k.046 = add nuw nsw i64 %k.045, 1 + %exitcond = icmp ne i64 %k.046, 5 + br i1 %exitcond, label %for.body, label %for.end22 + +for.end22: ; preds = %for.body + ret i64 %k.046 +} + +; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none) +declare void @llvm.dbg.value(metadata, metadata, metadata) + +!llvm.dbg.cu = !{!0} +!llvm.module.flags = !{!12} + +!0 = distinct !DICompileUnit(language: DW_LANG_C89, file: !1, producer: "clang version 19.0.0git (https://github.com/llvm/llvm-project.git ec062f5b33ed22c61742e3c1486f6cba915801e0)", isOptimized: true, runtimeVersion: 0, emissionKind: FullDebug, globals: !2, splitDebugInlining: false, nameTableKind: None) +!1 = !DIFile(filename: "unroll-remove-redundant-dbg.c", directory: "", checksumkind: CSK_MD5, checksum: "aa30a1d8c04deb9b0f3885c258d2b674") +!2 = !{!3, !8, !10} +!3 = !DIGlobalVariableExpression(var: !4, expr: !DIExpression()) +!4 = distinct !DIGlobalVariable(name: "a", scope: !0, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true) +!5 = !DIDerivedType(tag: DW_TAG_typedef, name: "uint32_t", file: !6, line: 198, baseType: !7) +!6 = !DIFile(filename: "/usr/include/stdint.h", directory: "", checksumkind: CSK_MD5, checksum: "da031bcff2d0c1d65aa92e7e68a44ef3") +!7 = !DIBasicType(name: "unsigned int", size: 32, encoding: DW_ATE_unsigned) +!8 = !DIGlobalVariableExpression(var: !9, expr: !DIExpression()) +!9 = distinct !DIGlobalVariable(name: "c", scope: !0, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true) +!10 = !DIGlobalVariableExpression(var: !11, expr: !DIExpression()) +!11 = distinct !DIGlobalVariable(name: "b", scope: !0, file: !1, line: 2, type: !5, isLocal: false, isDefinition: true) +!12 = !{i32 2, !"Debug Info Version", i32 3} +!13 = !DILocalVariable(name: "f", scope: !14, file: !1, line: 4, type: !5) +!14 = distinct !DISubprogram(name: "d", scope: !1, file: !1, line: 3, type: !15, scopeLine: 3, flags: DIFlagAllCallsDescribed, spFlags: DISPFlagDefinition | DISPFlagOptimized, unit: !0, retainedNodes: !16) +!15 = !DISubroutineType(types: !16) +!16 = !{} +!17 = !DILocation(line: 0, scope: !14) diff --git a/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll b/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll index e00d1daf71de..5af73e789f11 100644 --- a/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll +++ b/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue-inlined.ll @@ -9,7 +9,6 @@ init: ; CHECK: %vala = load i64, ptr %ptr ; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 %vala, metadata [[MD:![0-9]*]] -; CHECK-NEXT: call void @llvm.dbg.value(metadata i64 %vala, metadata [[MD]] ; CHECK-NEXT: %valbmasked = and i64 %vala, 1 a: ; preds = %init diff --git a/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll b/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll index af7da45ec089..c5d723c4e3dd 100644 --- a/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll +++ b/llvm/test/Transforms/SimplifyCFG/hoist-dbgvalue.ll @@ -47,7 +47,6 @@ define i1 @hoist_with_debug2(i32 %x) !dbg !22 { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[TOBOOL_NOT:%.*]] = icmp ugt i32 [[X:%.*]], 2 ; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[X]], metadata [[META21:![0-9]+]], metadata !DIExpression()), !dbg [[DBG23:![0-9]+]] -; CHECK-NEXT: call void @llvm.dbg.value(metadata i32 [[X]], metadata [[META21]], metadata !DIExpression()), !dbg [[DBG23]] ; CHECK-NEXT: [[DOT:%.*]] = select i1 [[TOBOOL_NOT]], i1 false, i1 true ; CHECK-NEXT: ret i1 [[DOT]] ; -- GitLab From 1ed1ec9a99bf543b0a926434beca53a42d2de94d Mon Sep 17 00:00:00 2001 From: Vyacheslav Levytskyy Date: Fri, 26 Apr 2024 12:17:47 +0200 Subject: [PATCH 039/301] [SPIRV] Improve builtins matching and type inference in SPIR-V Backend, fix target ext type constants (#89948) This PR is to improve builtins matching and type inference in SPIR-V Backend. The model test case is printf call from OpenCL.std that has several features allowing for a wider look at builtins support/type inference: (1) call in a "spirv-friendly" style (prefixed by __spirv_ocl_) (2) restricted type of the 1st argument Attached test cases checks several possible inputs. Support of the extension SPV_EXT_relaxed_printf_string_address_space is to do (see: https://github.com/KhronosGroup/SPIRV-Registry/blob/main/extensions/EXT/SPV_EXT_relaxed_printf_string_address_space.asciidoc). This PR also fixes target ext type constants and OpGroupAsyncCopy/OpGroupWaitEvents generation. A new test case is attached. --- llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp | 13 ++- llvm/lib/Target/SPIRV/SPIRVBuiltins.td | 4 +- llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp | 97 ++++++++++++++----- llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp | 10 ++ llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp | 40 +++++--- llvm/test/CodeGen/SPIRV/printf.ll | 40 ++++++++ .../SPIRV/transcoding/spirv-event-null.ll | 33 +++++++ 7 files changed, 196 insertions(+), 41 deletions(-) create mode 100644 llvm/test/CodeGen/SPIRV/printf.ll create mode 100644 llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp index 4b07d7e61fa1..7439d0fefa98 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.cpp @@ -189,6 +189,10 @@ lookupBuiltin(StringRef DemangledCall, std::string BuiltinName = DemangledCall.substr(0, DemangledCall.find('(')).str(); + // Account for possible "__spirv_ocl_" prefix in SPIR-V friendly LLVM IR + if (BuiltinName.rfind("__spirv_ocl_", 0) == 0) + BuiltinName = BuiltinName.substr(12); + // Check if the extracted name contains type information between angle // brackets. If so, the builtin is an instantiated template - needs to have // the information after angle brackets and return type removed. @@ -2008,6 +2012,13 @@ static bool generateAsyncCopy(const SPIRV::IncomingCall *Call, const SPIRV::DemangledBuiltin *Builtin = Call->Builtin; unsigned Opcode = SPIRV::lookupNativeBuiltin(Builtin->Name, Builtin->Set)->Opcode; + + bool IsSet = Opcode == SPIRV::OpGroupAsyncCopy; + Register TypeReg = GR->getSPIRVTypeID(Call->ReturnType); + if (Call->isSpirvOp()) + return buildOpFromWrapper(MIRBuilder, Opcode, Call, + IsSet ? TypeReg : Register(0)); + auto Scope = buildConstantIntReg(SPIRV::Scope::Workgroup, MIRBuilder, GR); switch (Opcode) { @@ -2306,7 +2317,7 @@ Type *parseBuiltinCallArgumentBaseType(const StringRef DemangledCall, // parseBuiltinCallArgumentBaseType(...) as this function only retrieves the // base types. if (TypeStr.ends_with("*")) - TypeStr = TypeStr.slice(0, TypeStr.find_first_of(" ")); + TypeStr = TypeStr.slice(0, TypeStr.find_first_of(" *")); return parseBuiltinTypeNameToTargetExtType("opencl." + TypeStr.str() + "_t", Ctx); diff --git a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td index 660000fb548d..564028547821 100644 --- a/llvm/lib/Target/SPIRV/SPIRVBuiltins.td +++ b/llvm/lib/Target/SPIRV/SPIRVBuiltins.td @@ -585,9 +585,9 @@ defm : DemangledNativeBuiltin<"__spirv_SpecConstantComposite", OpenCL_std, SpecC // Async Copy and Prefetch builtin records: defm : DemangledNativeBuiltin<"async_work_group_copy", OpenCL_std, AsyncCopy, 4, 4, OpGroupAsyncCopy>; -defm : DemangledNativeBuiltin<"__spirv_GroupAsyncCopy", OpenCL_std, AsyncCopy, 4, 4, OpGroupAsyncCopy>; +defm : DemangledNativeBuiltin<"__spirv_GroupAsyncCopy", OpenCL_std, AsyncCopy, 6, 6, OpGroupAsyncCopy>; defm : DemangledNativeBuiltin<"wait_group_events", OpenCL_std, AsyncCopy, 2, 2, OpGroupWaitEvents>; -defm : DemangledNativeBuiltin<"__spirv_GroupWaitEvents", OpenCL_std, AsyncCopy, 2, 2, OpGroupWaitEvents>; +defm : DemangledNativeBuiltin<"__spirv_GroupWaitEvents", OpenCL_std, AsyncCopy, 3, 3, OpGroupWaitEvents>; // Load and store builtin records: defm : DemangledNativeBuiltin<"__spirv_Load", OpenCL_std, LoadStore, 1, 3, OpLoad>; diff --git a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp index 472bc8638c9a..0d539b1ed9a8 100644 --- a/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVEmitIntrinsics.cpp @@ -98,6 +98,8 @@ class SPIRVEmitIntrinsics return B.CreateIntrinsic(IntrID, {Types}, Args); } + void buildAssignPtr(IRBuilder<> &B, Type *ElemTy, Value *Arg); + void replaceMemInstrUses(Instruction *Old, Instruction *New, IRBuilder<> &B); void processInstrAfterVisit(Instruction *I, IRBuilder<> &B); void insertAssignPtrTypeIntrs(Instruction *I, IRBuilder<> &B); @@ -111,6 +113,7 @@ class SPIRVEmitIntrinsics void insertPtrCastOrAssignTypeInstr(Instruction *I, IRBuilder<> &B); void processGlobalValue(GlobalVariable &GV, IRBuilder<> &B); void processParamTypes(Function *F, IRBuilder<> &B); + void processParamTypesByFunHeader(Function *F, IRBuilder<> &B); Type *deduceFunParamElementType(Function *F, unsigned OpIdx); Type *deduceFunParamElementType(Function *F, unsigned OpIdx, std::unordered_set &FVisited); @@ -194,6 +197,17 @@ static inline void reportFatalOnTokenType(const Instruction *I) { false); } +void SPIRVEmitIntrinsics::buildAssignPtr(IRBuilder<> &B, Type *ElemTy, + Value *Arg) { + CallInst *AssignPtrTyCI = + buildIntrWithMD(Intrinsic::spv_assign_ptr_type, {Arg->getType()}, + Constant::getNullValue(ElemTy), Arg, + {B.getInt32(getPointerAddressSpace(Arg->getType()))}, B); + GR->addDeducedElementType(AssignPtrTyCI, ElemTy); + GR->addDeducedElementType(Arg, ElemTy); + AssignPtrTypeInstr[Arg] = AssignPtrTyCI; +} + // Set element pointer type to the given value of ValueTy and tries to // specify this type further (recursively) by Operand value, if needed. Type *SPIRVEmitIntrinsics::deduceElementTypeByValueDeep( @@ -232,6 +246,19 @@ Type *SPIRVEmitIntrinsics::deduceElementTypeByUsersDeep( return nullptr; } +// Implements what we know in advance about intrinsics and builtin calls +// TODO: consider feasibility of this particular case to be generalized by +// encoding knowledge about intrinsics and builtin calls by corresponding +// specification rules +static Type *getPointeeTypeByCallInst(StringRef DemangledName, + Function *CalledF, unsigned OpIdx) { + if ((DemangledName.starts_with("__spirv_ocl_printf(") || + DemangledName.starts_with("printf(")) && + OpIdx == 0) + return IntegerType::getInt8Ty(CalledF->getContext()); + return nullptr; +} + // Deduce and return a successfully deduced Type of the Instruction, // or nullptr otherwise. Type *SPIRVEmitIntrinsics::deduceElementTypeHelper(Value *I) { @@ -795,6 +822,8 @@ void SPIRVEmitIntrinsics::insertPtrCastOrAssignTypeInstr(Instruction *I, return; // collect information about formal parameter types + std::string DemangledName = + getOclOrSpirvBuiltinDemangledName(CI->getCalledFunction()->getName()); Function *CalledF = CI->getCalledFunction(); SmallVector CalledArgTys; bool HaveTypes = false; @@ -811,10 +840,15 @@ void SPIRVEmitIntrinsics::insertPtrCastOrAssignTypeInstr(Instruction *I, if (!ElemTy && hasPointeeTypeAttr(CalledArg)) ElemTy = getPointeeTypeByAttr(CalledArg); if (!ElemTy) { - for (User *U : CalledArg->users()) { - if (Instruction *Inst = dyn_cast(U)) { - if ((ElemTy = deduceElementTypeHelper(Inst)) != nullptr) - break; + ElemTy = getPointeeTypeByCallInst(DemangledName, CalledF, OpIdx); + if (ElemTy) { + GR->addDeducedElementType(CalledArg, ElemTy); + } else { + for (User *U : CalledArg->users()) { + if (Instruction *Inst = dyn_cast(U)) { + if ((ElemTy = deduceElementTypeHelper(Inst)) != nullptr) + break; + } } } } @@ -823,8 +857,6 @@ void SPIRVEmitIntrinsics::insertPtrCastOrAssignTypeInstr(Instruction *I, } } - std::string DemangledName = - getOclOrSpirvBuiltinDemangledName(CI->getCalledFunction()->getName()); if (DemangledName.empty() && !HaveTypes) return; @@ -835,8 +867,14 @@ void SPIRVEmitIntrinsics::insertPtrCastOrAssignTypeInstr(Instruction *I, continue; // Constants (nulls/undefs) are handled in insertAssignPtrTypeIntrs() - if (!isa(ArgOperand) && !isa(ArgOperand)) - continue; + if (!isa(ArgOperand) && !isa(ArgOperand)) { + // However, we may have assumptions about the formal argument's type and + // may have a need to insert a ptr cast for the actual parameter of this + // call. + Argument *CalledArg = CalledF->getArg(OpIdx); + if (!GR->findDeducedElementType(CalledArg)) + continue; + } Type *ExpectedType = OpIdx < CalledArgTys.size() ? CalledArgTys[OpIdx] : nullptr; @@ -1102,9 +1140,13 @@ void SPIRVEmitIntrinsics::processInstrAfterVisit(Instruction *I, (II->paramHasAttr(OpNo, Attribute::ImmArg)))) continue; B.SetInsertPoint(I); - auto *NewOp = - buildIntrWithMD(Intrinsic::spv_track_constant, - {Op->getType(), Op->getType()}, Op, Op, {}, B); + Value *OpTyVal = Op; + if (Op->getType()->isTargetExtTy()) + OpTyVal = Constant::getNullValue( + IntegerType::get(I->getContext(), GR->getPointerSize())); + auto *NewOp = buildIntrWithMD(Intrinsic::spv_track_constant, + {Op->getType(), OpTyVal->getType()}, Op, + OpTyVal, {}, B); I->setOperand(OpNo, NewOp); } } @@ -1179,28 +1221,29 @@ Type *SPIRVEmitIntrinsics::deduceFunParamElementType( return nullptr; } -void SPIRVEmitIntrinsics::processParamTypes(Function *F, IRBuilder<> &B) { +void SPIRVEmitIntrinsics::processParamTypesByFunHeader(Function *F, + IRBuilder<> &B) { B.SetInsertPointPastAllocas(F); for (unsigned OpIdx = 0; OpIdx < F->arg_size(); ++OpIdx) { Argument *Arg = F->getArg(OpIdx); if (!isUntypedPointerTy(Arg->getType())) continue; + Type *ElemTy = GR->findDeducedElementType(Arg); + if (!ElemTy && hasPointeeTypeAttr(Arg) && + (ElemTy = getPointeeTypeByAttr(Arg)) != nullptr) + buildAssignPtr(B, ElemTy, Arg); + } +} +void SPIRVEmitIntrinsics::processParamTypes(Function *F, IRBuilder<> &B) { + B.SetInsertPointPastAllocas(F); + for (unsigned OpIdx = 0; OpIdx < F->arg_size(); ++OpIdx) { + Argument *Arg = F->getArg(OpIdx); + if (!isUntypedPointerTy(Arg->getType())) + continue; Type *ElemTy = GR->findDeducedElementType(Arg); - if (!ElemTy) { - if (hasPointeeTypeAttr(Arg) && - (ElemTy = getPointeeTypeByAttr(Arg)) != nullptr) { - GR->addDeducedElementType(Arg, ElemTy); - } else if ((ElemTy = deduceFunParamElementType(F, OpIdx)) != nullptr) { - CallInst *AssignPtrTyCI = buildIntrWithMD( - Intrinsic::spv_assign_ptr_type, {Arg->getType()}, - Constant::getNullValue(ElemTy), Arg, - {B.getInt32(getPointerAddressSpace(Arg->getType()))}, B); - GR->addDeducedElementType(AssignPtrTyCI, ElemTy); - GR->addDeducedElementType(Arg, ElemTy); - AssignPtrTypeInstr[Arg] = AssignPtrTyCI; - } - } + if (!ElemTy && (ElemTy = deduceFunParamElementType(F, OpIdx)) != nullptr) + buildAssignPtr(B, ElemTy, Arg); } } @@ -1217,6 +1260,8 @@ bool SPIRVEmitIntrinsics::runOnFunction(Function &Func) { AggrConstTypes.clear(); AggrStores.clear(); + processParamTypesByFunHeader(F, B); + // StoreInst's operand type can be changed during the next transformations, // so we need to store it in the set. Also store already transformed types. for (auto &I : instructions(Func)) { diff --git a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp index b8296c3f6eea..96b4a570a26b 100644 --- a/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVISelLowering.cpp @@ -314,6 +314,16 @@ void SPIRVTargetLowering::finalizeLowering(MachineFunction &MF) const { SPIRV::OpTypeBool)) MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpLogicalNotEqual)); break; + case SPIRV::OpConstantI: { + SPIRVType *Type = GR.getSPIRVTypeForVReg(MI.getOperand(1).getReg()); + if (Type->getOpcode() != SPIRV::OpTypeInt && MI.getOperand(2).isImm() && + MI.getOperand(2).getImm() == 0) { + // Validate the null constant of a target extension type + MI.setDesc(STI.getInstrInfo()->get(SPIRV::OpConstantNull)); + for (unsigned i = MI.getNumOperands() - 1; i > 1; --i) + MI.removeOperand(i); + } + } break; } } } diff --git a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp index 9ee0b38d2233..84508fb5fe09 100644 --- a/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp +++ b/llvm/lib/Target/SPIRV/SPIRVPreLegalizer.cpp @@ -38,7 +38,9 @@ public: }; } // namespace -static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR) { +static void +addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR, + DenseMap &TargetExtConstTypes) { MachineRegisterInfo &MRI = MF.getRegInfo(); DenseMap RegsAlreadyAddedToDT; SmallVector ToErase, ToEraseComposites; @@ -47,6 +49,7 @@ static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR) { if (!isSpvIntrinsic(MI, Intrinsic::spv_track_constant)) continue; ToErase.push_back(&MI); + Register SrcReg = MI.getOperand(2).getReg(); auto *Const = cast(cast( MI.getOperand(3).getMetadata()->getOperand(0)) @@ -54,14 +57,14 @@ static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR) { if (auto *GV = dyn_cast(Const)) { Register Reg = GR->find(GV, &MF); if (!Reg.isValid()) - GR->add(GV, &MF, MI.getOperand(2).getReg()); + GR->add(GV, &MF, SrcReg); else RegsAlreadyAddedToDT[&MI] = Reg; } else { Register Reg = GR->find(Const, &MF); if (!Reg.isValid()) { if (auto *ConstVec = dyn_cast(Const)) { - auto *BuildVec = MRI.getVRegDef(MI.getOperand(2).getReg()); + auto *BuildVec = MRI.getVRegDef(SrcReg); assert(BuildVec && BuildVec->getOpcode() == TargetOpcode::G_BUILD_VECTOR); for (unsigned i = 0; i < ConstVec->getNumElements(); ++i) { @@ -75,7 +78,13 @@ static void addConstantsToTrack(MachineFunction &MF, SPIRVGlobalRegistry *GR) { BuildVec->getOperand(1 + i).setReg(ElemReg); } } - GR->add(Const, &MF, MI.getOperand(2).getReg()); + GR->add(Const, &MF, SrcReg); + if (Const->getType()->isTargetExtTy()) { + // remember association so that we can restore it when assign types + MachineInstr *SrcMI = MRI.getVRegDef(SrcReg); + if (SrcMI && SrcMI->getOpcode() == TargetOpcode::G_CONSTANT) + TargetExtConstTypes[SrcMI] = Const->getType(); + } } else { RegsAlreadyAddedToDT[&MI] = Reg; // This MI is unused and will be removed. If the MI uses @@ -364,8 +373,10 @@ void processInstr(MachineInstr &MI, MachineIRBuilder &MIB, } } // namespace llvm -static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, - MachineIRBuilder MIB) { +static void +generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, + MachineIRBuilder MIB, + DenseMap &TargetExtConstTypes) { // Get access to information about available extensions const SPIRVSubtarget *ST = static_cast(&MIB.getMF().getSubtarget()); @@ -422,11 +433,14 @@ static void generateAssignInstrs(MachineFunction &MF, SPIRVGlobalRegistry *GR, continue; } Type *Ty = nullptr; - if (MI.getOpcode() == TargetOpcode::G_CONSTANT) - Ty = MI.getOperand(1).getCImm()->getType(); - else if (MI.getOpcode() == TargetOpcode::G_FCONSTANT) + if (MI.getOpcode() == TargetOpcode::G_CONSTANT) { + auto TargetExtIt = TargetExtConstTypes.find(&MI); + Ty = TargetExtIt == TargetExtConstTypes.end() + ? MI.getOperand(1).getCImm()->getType() + : TargetExtIt->second; + } else if (MI.getOpcode() == TargetOpcode::G_FCONSTANT) { Ty = MI.getOperand(1).getFPImm()->getType(); - else { + } else { assert(MI.getOpcode() == TargetOpcode::G_BUILD_VECTOR); Type *ElemTy = nullptr; MachineInstr *ElemMI = MRI.getVRegDef(MI.getOperand(1).getReg()); @@ -616,10 +630,12 @@ bool SPIRVPreLegalizer::runOnMachineFunction(MachineFunction &MF) { SPIRVGlobalRegistry *GR = ST.getSPIRVGlobalRegistry(); GR->setCurrentFunc(MF); MachineIRBuilder MIB(MF); - addConstantsToTrack(MF, GR); + // a registry of target extension constants + DenseMap TargetExtConstTypes; + addConstantsToTrack(MF, GR, TargetExtConstTypes); foldConstantsIntoIntrinsics(MF); insertBitcasts(MF, GR, MIB); - generateAssignInstrs(MF, GR, MIB); + generateAssignInstrs(MF, GR, MIB, TargetExtConstTypes); processSwitches(MF, GR, MIB); processInstrsWithTypeFolding(MF, GR, MIB); removeImplicitFallthroughs(MF, MIB); diff --git a/llvm/test/CodeGen/SPIRV/printf.ll b/llvm/test/CodeGen/SPIRV/printf.ll new file mode 100644 index 000000000000..483fc1f244e5 --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/printf.ll @@ -0,0 +1,40 @@ +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK: %[[#ExtImport:]] = OpExtInstImport "OpenCL.std" +; CHECK: %[[#Char:]] = OpTypeInt 8 0 +; CHECK: %[[#CharPtr:]] = OpTypePointer UniformConstant %[[#Char]] +; CHECK: %[[#GV:]] = OpVariable %[[#]] UniformConstant %[[#]] +; CHECK: OpFunction +; CHECK: %[[#Arg1:]] = OpFunctionParameter +; CHECK: %[[#Arg2:]] = OpFunctionParameter +; CHECK: %[[#CastedGV:]] = OpBitcast %[[#CharPtr]] %[[#GV]] +; CHECK-NEXT: OpExtInst %[[#]] %[[#ExtImport]] printf %[[#CastedGV]] %[[#ArgConst:]] +; CHECK-NEXT: OpExtInst %[[#]] %[[#ExtImport]] printf %[[#CastedGV]] %[[#ArgConst]] +; CHECK-NEXT: OpExtInst %[[#]] %[[#ExtImport]] printf %[[#Arg1]] %[[#ArgConst:]] +; CHECK-NEXT: OpExtInst %[[#]] %[[#ExtImport]] printf %[[#Arg1]] %[[#ArgConst]] +; CHECK-NEXT: %[[#CastedArg2:]] = OpBitcast %[[#CharPtr]] %[[#Arg2]] +; CHECK-NEXT: OpExtInst %[[#]] %[[#ExtImport]] printf %[[#CastedArg2]] %[[#ArgConst]] +; CHECK-NEXT: OpExtInst %[[#]] %[[#ExtImport]] printf %[[#CastedArg2]] %[[#ArgConst]] +; CHECK: OpFunctionEnd + +%struct = type { [6 x i8] } + +@FmtStr = internal addrspace(2) constant [6 x i8] c"c=%c\0A\00", align 1 + +define spir_kernel void @foo(ptr addrspace(2) %_arg_fmt1, ptr addrspace(2) byval(%struct) %_arg_fmt2) { +entry: + %r1 = tail call spir_func i32 (ptr addrspace(2), ...) @_Z6printfPU3AS2Kcz(ptr addrspace(2) @FmtStr, i8 signext 97) + %r2 = tail call spir_func i32 (ptr addrspace(2), ...) @_Z18__spirv_ocl_printfPU3AS2Kcz(ptr addrspace(2) @FmtStr, i8 signext 97) + %r3 = tail call spir_func i32 (ptr addrspace(2), ...) @_Z6printfPU3AS2Kcz(ptr addrspace(2) %_arg_fmt1, i8 signext 97) + %r4 = tail call spir_func i32 (ptr addrspace(2), ...) @_Z18__spirv_ocl_printfPU3AS2Kcz(ptr addrspace(2) %_arg_fmt1, i8 signext 97) + %r5 = tail call spir_func i32 (ptr addrspace(2), ...) @_Z6printfPU3AS2Kcz(ptr addrspace(2) %_arg_fmt2, i8 signext 97) + %r6 = tail call spir_func i32 (ptr addrspace(2), ...) @_Z18__spirv_ocl_printfPU3AS2Kcz(ptr addrspace(2) %_arg_fmt2, i8 signext 97) + ret void +} + +declare dso_local spir_func i32 @_Z6printfPU3AS2Kcz(ptr addrspace(2), ...) +declare dso_local spir_func i32 @_Z18__spirv_ocl_printfPU3AS2Kcz(ptr addrspace(2), ...) diff --git a/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll new file mode 100644 index 000000000000..fe0d96f2773e --- /dev/null +++ b/llvm/test/CodeGen/SPIRV/transcoding/spirv-event-null.ll @@ -0,0 +1,33 @@ +; RUN: llc -O0 -mtriple=spirv32-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv32-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; RUN: llc -O0 -mtriple=spirv64-unknown-unknown %s -o - | FileCheck %s +; RUN: %if spirv-tools %{ llc -O0 -mtriple=spirv64-unknown-unknown %s -o - -filetype=obj | spirv-val %} + +; CHECK-DAG: %[[#TyEvent:]] = OpTypeEvent +; CHECK-DAG: %[[#TyStruct:]] = OpTypeStruct %[[#TyEvent]] +; CHECK-DAG: %[[#ConstEvent:]] = OpConstantNull %[[#TyEvent]] +; CHECK-DAG: %[[#TyEventPtr:]] = OpTypePointer Function %[[#TyEvent]] +; CHECK-DAG: %[[#TyStructPtr:]] = OpTypePointer Function %[[#TyStruct]] +; CHECK: OpFunction +; CHECK: OpFunctionParameter +; CHECK: %[[#Src:]] = OpFunctionParameter +; CHECK: OpVariable %[[#TyStructPtr]] Function +; CHECK: %[[#EventVar:]] = OpVariable %[[#TyEventPtr]] Function +; CHECK: %[[#Dest:]] = OpInBoundsPtrAccessChain +; CHECK: %[[#CopyRes:]] = OpGroupAsyncCopy %[[#TyEvent]] %[[#]] %[[#Dest]] %[[#Src]] %[[#]] %[[#]] %[[#ConstEvent]] +; CHECK: OpStore %[[#EventVar]] %[[#CopyRes]] + +%"class.sycl::_V1::device_event" = type { target("spirv.Event") } + +define spir_kernel void @foo(ptr addrspace(1) %_arg_out_ptr, ptr addrspace(3) noundef %_arg_local_acc) { +entry: + %var = alloca %"class.sycl::_V1::device_event" + %dev_event.i.sroa.0 = alloca target("spirv.Event") + %add.ptr.i26 = getelementptr inbounds i32, ptr addrspace(1) %_arg_out_ptr, i64 0 + %call3.i = tail call spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kimm9ocl_event(i32 2, ptr addrspace(1) %add.ptr.i26, ptr addrspace(3) %_arg_local_acc, i64 16, i64 10, target("spirv.Event") zeroinitializer) + store target("spirv.Event") %call3.i, ptr %dev_event.i.sroa.0 + ret void +} + +declare dso_local spir_func target("spirv.Event") @_Z22__spirv_GroupAsyncCopyjPU3AS1iPU3AS3Kimm9ocl_event(i32, ptr addrspace(1), ptr addrspace(3), i64, i64, target("spirv.Event")) -- GitLab From f1112ebe074ea098d83dd100e67c218e1a20adf9 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 26 Apr 2024 12:20:40 +0200 Subject: [PATCH 040/301] AMDGPU: Do not bitcast atomic load in IR (#90060) These hooks should be removed. This is a trivial legalization transform the legalizer needs to support. The IR just complicates things, and it was losing metadata. Implement the DAG promotion support, and switch AMDGPU over to using it. Really we'd be a lot better off merging ATOMIC_LOAD and LOAD like GlobalISel does. --- llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 15 ++++++ .../SelectionDAG/LegalizeFloatTypes.cpp | 39 ++++++++++++++ llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h | 2 + llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 13 +++++ llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h | 6 +++ .../AMDGPU/no-expand-atomic-load.ll | 54 +++++++------------ 6 files changed, 95 insertions(+), 34 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index 8413cd60135f..c381870ae5f4 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -5575,6 +5575,21 @@ void SelectionDAGLegalize::PromoteNode(SDNode *Node) { Results.push_back(NewAtomic.getValue(1)); break; } + case ISD::ATOMIC_LOAD: { + AtomicSDNode *AM = cast(Node); + SDLoc SL(Node); + assert(NVT.getSizeInBits() == OVT.getSizeInBits() && + "unexpected promotion type"); + assert(AM->getMemoryVT().getSizeInBits() == NVT.getSizeInBits() && + "unexpected atomic_load with illegal type"); + + SDValue NewAtomic = + DAG.getAtomic(ISD::ATOMIC_LOAD, SL, NVT, DAG.getVTList(NVT, MVT::Other), + {AM->getChain(), AM->getBasePtr()}, AM->getMemOperand()); + Results.push_back(DAG.getNode(ISD::BITCAST, SL, OVT, NewAtomic)); + Results.push_back(NewAtomic.getValue(1)); + break; + } case ISD::SPLAT_VECTOR: { SDValue Scalar = Node->getOperand(0); MVT ScalarType = Scalar.getSimpleValueType(); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index 7685bc73cf96..abe5be763825 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -2449,6 +2449,9 @@ void DAGTypeLegalizer::PromoteFloatResult(SDNode *N, unsigned ResNo) { R = PromoteFloatRes_STRICT_FP_ROUND(N); break; case ISD::LOAD: R = PromoteFloatRes_LOAD(N); break; + case ISD::ATOMIC_LOAD: + R = PromoteFloatRes_ATOMIC_LOAD(N); + break; case ISD::SELECT: R = PromoteFloatRes_SELECT(N); break; case ISD::SELECT_CC: R = PromoteFloatRes_SELECT_CC(N); break; @@ -2695,6 +2698,25 @@ SDValue DAGTypeLegalizer::PromoteFloatRes_LOAD(SDNode *N) { return DAG.getNode(GetPromotionOpcode(VT, NVT), SDLoc(N), NVT, newL); } +SDValue DAGTypeLegalizer::PromoteFloatRes_ATOMIC_LOAD(SDNode *N) { + AtomicSDNode *AM = cast(N); + EVT VT = AM->getValueType(0); + + // Load the value as an integer value with the same number of bits. + EVT IVT = EVT::getIntegerVT(*DAG.getContext(), VT.getSizeInBits()); + SDValue newL = DAG.getAtomic( + ISD::ATOMIC_LOAD, SDLoc(N), IVT, DAG.getVTList(IVT, MVT::Other), + {AM->getChain(), AM->getBasePtr()}, AM->getMemOperand()); + + // Legalize the chain result by replacing uses of the old value chain with the + // new one + ReplaceValueWith(SDValue(N, 1), newL.getValue(1)); + + // Convert the integer value to the desired FP type + EVT NVT = TLI.getTypeToTransformTo(*DAG.getContext(), VT); + return DAG.getNode(GetPromotionOpcode(VT, IVT), SDLoc(N), NVT, newL); +} + // Construct a new SELECT node with the promoted true- and false- values. SDValue DAGTypeLegalizer::PromoteFloatRes_SELECT(SDNode *N) { SDValue TrueVal = GetPromotedFloat(N->getOperand(1)); @@ -2855,6 +2877,9 @@ void DAGTypeLegalizer::SoftPromoteHalfResult(SDNode *N, unsigned ResNo) { case ISD::FFREXP: R = SoftPromoteHalfRes_FFREXP(N); break; case ISD::LOAD: R = SoftPromoteHalfRes_LOAD(N); break; + case ISD::ATOMIC_LOAD: + R = SoftPromoteHalfRes_ATOMIC_LOAD(N); + break; case ISD::SELECT: R = SoftPromoteHalfRes_SELECT(N); break; case ISD::SELECT_CC: R = SoftPromoteHalfRes_SELECT_CC(N); break; case ISD::SINT_TO_FP: @@ -3039,6 +3064,20 @@ SDValue DAGTypeLegalizer::SoftPromoteHalfRes_LOAD(SDNode *N) { return NewL; } +SDValue DAGTypeLegalizer::SoftPromoteHalfRes_ATOMIC_LOAD(SDNode *N) { + AtomicSDNode *AM = cast(N); + + // Load the value as an integer value with the same number of bits. + SDValue NewL = DAG.getAtomic( + ISD::ATOMIC_LOAD, SDLoc(N), MVT::i16, DAG.getVTList(MVT::i16, MVT::Other), + {AM->getChain(), AM->getBasePtr()}, AM->getMemOperand()); + + // Legalize the chain result by replacing uses of the old value chain with the + // new one + ReplaceValueWith(SDValue(N, 1), NewL.getValue(1)); + return NewL; +} + SDValue DAGTypeLegalizer::SoftPromoteHalfRes_SELECT(SDNode *N) { SDValue Op1 = GetSoftPromotedHalf(N->getOperand(1)); SDValue Op2 = GetSoftPromotedHalf(N->getOperand(2)); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h index 9c855e558553..4a2c7b355eb5 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h @@ -691,6 +691,7 @@ private: SDValue PromoteFloatRes_FP_ROUND(SDNode *N); SDValue PromoteFloatRes_STRICT_FP_ROUND(SDNode *N); SDValue PromoteFloatRes_LOAD(SDNode *N); + SDValue PromoteFloatRes_ATOMIC_LOAD(SDNode *N); SDValue PromoteFloatRes_SELECT(SDNode *N); SDValue PromoteFloatRes_SELECT_CC(SDNode *N); SDValue PromoteFloatRes_UnaryOp(SDNode *N); @@ -734,6 +735,7 @@ private: SDValue SoftPromoteHalfRes_FFREXP(SDNode *N); SDValue SoftPromoteHalfRes_FP_ROUND(SDNode *N); SDValue SoftPromoteHalfRes_LOAD(SDNode *N); + SDValue SoftPromoteHalfRes_ATOMIC_LOAD(SDNode *N); SDValue SoftPromoteHalfRes_SELECT(SDNode *N); SDValue SoftPromoteHalfRes_SELECT_CC(SDNode *N); SDValue SoftPromoteHalfRes_UnaryOp(SDNode *N); diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index f4a747784d1f..7993b6312111 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -148,6 +148,19 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, setOperationAction(ISD::LOAD, MVT::i128, Promote); AddPromotedToType(ISD::LOAD, MVT::i128, MVT::v4i32); + // TODO: Would be better to consume as directly legal + setOperationAction(ISD::ATOMIC_LOAD, MVT::f32, Promote); + AddPromotedToType(ISD::ATOMIC_LOAD, MVT::f32, MVT::i32); + + setOperationAction(ISD::ATOMIC_LOAD, MVT::f64, Promote); + AddPromotedToType(ISD::ATOMIC_LOAD, MVT::f64, MVT::i64); + + setOperationAction(ISD::ATOMIC_LOAD, MVT::f16, Promote); + AddPromotedToType(ISD::ATOMIC_LOAD, MVT::f16, MVT::i16); + + setOperationAction(ISD::ATOMIC_LOAD, MVT::bf16, Promote); + AddPromotedToType(ISD::ATOMIC_LOAD, MVT::bf16, MVT::i16); + // There are no 64-bit extloads. These should be done as a 32-bit extload and // an extension to 64-bit. for (MVT VT : MVT::integer_valuetypes()) diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h index 72661a8d29f8..269c414521db 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.h @@ -230,6 +230,12 @@ public: bool isCheapToSpeculateCtlz(Type *Ty) const override; bool isSDNodeAlwaysUniform(const SDNode *N) const override; + + // FIXME: This hook should not exist + AtomicExpansionKind shouldCastAtomicLoadInIR(LoadInst *LI) const override { + return AtomicExpansionKind::None; + } + static CCAssignFn *CCAssignFnForCall(CallingConv::ID CC, bool IsVarArg); static CCAssignFn *CCAssignFnForReturn(CallingConv::ID CC, bool IsVarArg); diff --git a/llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-load.ll b/llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-load.ll index fd5a2044db48..b1497aefe9b9 100644 --- a/llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-load.ll +++ b/llvm/test/Transforms/AtomicExpand/AMDGPU/no-expand-atomic-load.ll @@ -6,8 +6,7 @@ define float @load_atomic_f32_global_system(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define float @load_atomic_f32_global_system( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr addrspace(1) [[PTR]] seq_cst, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float +; CHECK-NEXT: [[TMP2:%.*]] = load atomic float, ptr addrspace(1) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0:![0-9]+]] ; CHECK-NEXT: ret float [[TMP2]] ; %ld = load atomic float, ptr addrspace(1) %ptr seq_cst, align 4, !some.unknown.md !0 @@ -17,8 +16,7 @@ define float @load_atomic_f32_global_system(ptr addrspace(1) %ptr) { define float @load_atomic_f32_global_agent(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define float @load_atomic_f32_global_agent( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float +; CHECK-NEXT: [[TMP2:%.*]] = load atomic float, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4, !some.unknown.md [[META0]] ; CHECK-NEXT: ret float [[TMP2]] ; %ld = load atomic float, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 4, !some.unknown.md !0 @@ -28,8 +26,7 @@ define float @load_atomic_f32_global_agent(ptr addrspace(1) %ptr) { define float @load_atomic_f32_local(ptr addrspace(3) %ptr) { ; CHECK-LABEL: define float @load_atomic_f32_local( ; CHECK-SAME: ptr addrspace(3) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr addrspace(3) [[PTR]] seq_cst, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float +; CHECK-NEXT: [[TMP2:%.*]] = load atomic float, ptr addrspace(3) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]] ; CHECK-NEXT: ret float [[TMP2]] ; %ld = load atomic float, ptr addrspace(3) %ptr seq_cst, align 4, !some.unknown.md !0 @@ -39,8 +36,7 @@ define float @load_atomic_f32_local(ptr addrspace(3) %ptr) { define float @load_atomic_f32_flat_system(ptr %ptr) { ; CHECK-LABEL: define float @load_atomic_f32_flat_system( ; CHECK-SAME: ptr [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[PTR]] seq_cst, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float +; CHECK-NEXT: [[TMP2:%.*]] = load atomic float, ptr [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]] ; CHECK-NEXT: ret float [[TMP2]] ; %ld = load atomic float, ptr %ptr seq_cst, align 4, !some.unknown.md !0 @@ -50,8 +46,7 @@ define float @load_atomic_f32_flat_system(ptr %ptr) { define float @load_atomic_f32_flat_agent(ptr %ptr) { ; CHECK-LABEL: define float @load_atomic_f32_flat_agent( ; CHECK-SAME: ptr [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i32, ptr [[PTR]] syncscope("agent") seq_cst, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i32 [[TMP1]] to float +; CHECK-NEXT: [[TMP2:%.*]] = load atomic float, ptr [[PTR]] syncscope("agent") seq_cst, align 4, !some.unknown.md [[META0]] ; CHECK-NEXT: ret float [[TMP2]] ; %ld = load atomic float, ptr %ptr syncscope("agent") seq_cst, align 4, !some.unknown.md !0 @@ -61,8 +56,7 @@ define float @load_atomic_f32_flat_agent(ptr %ptr) { define half @load_atomic_f16_global_system(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define half @load_atomic_f16_global_system( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i16, ptr addrspace(1) [[PTR]] seq_cst, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16 [[TMP1]] to half +; CHECK-NEXT: [[TMP2:%.*]] = load atomic half, ptr addrspace(1) [[PTR]] seq_cst, align 4, !some.unknown.md [[META0]] ; CHECK-NEXT: ret half [[TMP2]] ; %ld = load atomic half, ptr addrspace(1) %ptr seq_cst, align 4, !some.unknown.md !0 @@ -72,8 +66,7 @@ define half @load_atomic_f16_global_system(ptr addrspace(1) %ptr) { define half @load_atomic_f16_global_agent(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define half @load_atomic_f16_global_agent( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i16, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16 [[TMP1]] to half +; CHECK-NEXT: [[TMP2:%.*]] = load atomic half, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 4, !some.unknown.md [[META0]] ; CHECK-NEXT: ret half [[TMP2]] ; %ld = load atomic half, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 4, !some.unknown.md !0 @@ -83,8 +76,7 @@ define half @load_atomic_f16_global_agent(ptr addrspace(1) %ptr) { define half @load_atomic_f16_local(ptr addrspace(3) %ptr) { ; CHECK-LABEL: define half @load_atomic_f16_local( ; CHECK-SAME: ptr addrspace(3) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i16, ptr addrspace(3) [[PTR]] seq_cst, align 2 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16 [[TMP1]] to half +; CHECK-NEXT: [[TMP2:%.*]] = load atomic half, ptr addrspace(3) [[PTR]] seq_cst, align 2, !some.unknown.md [[META0]] ; CHECK-NEXT: ret half [[TMP2]] ; %ld = load atomic half, ptr addrspace(3) %ptr seq_cst, align 2, !some.unknown.md !0 @@ -94,8 +86,7 @@ define half @load_atomic_f16_local(ptr addrspace(3) %ptr) { define bfloat @load_atomic_bf16_global_system(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define bfloat @load_atomic_bf16_global_system( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i16, ptr addrspace(1) [[PTR]] seq_cst, align 2 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16 [[TMP1]] to bfloat +; CHECK-NEXT: [[TMP2:%.*]] = load atomic bfloat, ptr addrspace(1) [[PTR]] seq_cst, align 2, !some.unknown.md [[META0]] ; CHECK-NEXT: ret bfloat [[TMP2]] ; %ld = load atomic bfloat, ptr addrspace(1) %ptr seq_cst, align 2, !some.unknown.md !0 @@ -105,8 +96,7 @@ define bfloat @load_atomic_bf16_global_system(ptr addrspace(1) %ptr) { define bfloat @load_atomic_bf16_global_agent(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define bfloat @load_atomic_bf16_global_agent( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i16, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 2 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16 [[TMP1]] to bfloat +; CHECK-NEXT: [[TMP2:%.*]] = load atomic bfloat, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 2, !some.unknown.md [[META0]] ; CHECK-NEXT: ret bfloat [[TMP2]] ; %ld = load atomic bfloat, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 2, !some.unknown.md !0 @@ -116,8 +106,7 @@ define bfloat @load_atomic_bf16_global_agent(ptr addrspace(1) %ptr) { define bfloat @load_atomic_bf16_local(ptr addrspace(3) %ptr) { ; CHECK-LABEL: define bfloat @load_atomic_bf16_local( ; CHECK-SAME: ptr addrspace(3) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i16, ptr addrspace(3) [[PTR]] seq_cst, align 2 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16 [[TMP1]] to bfloat +; CHECK-NEXT: [[TMP2:%.*]] = load atomic bfloat, ptr addrspace(3) [[PTR]] seq_cst, align 2, !some.unknown.md [[META0]] ; CHECK-NEXT: ret bfloat [[TMP2]] ; %ld = load atomic bfloat, ptr addrspace(3) %ptr seq_cst, align 2, !some.unknown.md !0 @@ -127,8 +116,7 @@ define bfloat @load_atomic_bf16_local(ptr addrspace(3) %ptr) { define bfloat @load_atomic_bf16_flat(ptr %ptr) { ; CHECK-LABEL: define bfloat @load_atomic_bf16_flat( ; CHECK-SAME: ptr [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i16, ptr [[PTR]] seq_cst, align 2 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i16 [[TMP1]] to bfloat +; CHECK-NEXT: [[TMP2:%.*]] = load atomic bfloat, ptr [[PTR]] seq_cst, align 2, !some.unknown.md [[META0]] ; CHECK-NEXT: ret bfloat [[TMP2]] ; %ld = load atomic bfloat, ptr %ptr seq_cst, align 2, !some.unknown.md !0 @@ -138,8 +126,7 @@ define bfloat @load_atomic_bf16_flat(ptr %ptr) { define double @load_atomic_f64_global_system(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define double @load_atomic_f64_global_system( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i64, ptr addrspace(1) [[PTR]] seq_cst, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to double +; CHECK-NEXT: [[TMP2:%.*]] = load atomic double, ptr addrspace(1) [[PTR]] seq_cst, align 8, !some.unknown.md [[META0]] ; CHECK-NEXT: ret double [[TMP2]] ; %ld = load atomic double, ptr addrspace(1) %ptr seq_cst, align 8, !some.unknown.md !0 @@ -149,8 +136,7 @@ define double @load_atomic_f64_global_system(ptr addrspace(1) %ptr) { define double @load_atomic_f64_global_agent(ptr addrspace(1) %ptr) { ; CHECK-LABEL: define double @load_atomic_f64_global_agent( ; CHECK-SAME: ptr addrspace(1) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i64, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to double +; CHECK-NEXT: [[TMP2:%.*]] = load atomic double, ptr addrspace(1) [[PTR]] syncscope("agent") seq_cst, align 8, !some.unknown.md [[META0]] ; CHECK-NEXT: ret double [[TMP2]] ; %ld = load atomic double, ptr addrspace(1) %ptr syncscope("agent") seq_cst, align 8, !some.unknown.md !0 @@ -160,8 +146,7 @@ define double @load_atomic_f64_global_agent(ptr addrspace(1) %ptr) { define double @load_atomic_f64_local(ptr addrspace(3) %ptr) { ; CHECK-LABEL: define double @load_atomic_f64_local( ; CHECK-SAME: ptr addrspace(3) [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i64, ptr addrspace(3) [[PTR]] seq_cst, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to double +; CHECK-NEXT: [[TMP2:%.*]] = load atomic double, ptr addrspace(3) [[PTR]] seq_cst, align 8, !some.unknown.md [[META0]] ; CHECK-NEXT: ret double [[TMP2]] ; %ld = load atomic double, ptr addrspace(3) %ptr seq_cst, align 8, !some.unknown.md !0 @@ -171,8 +156,7 @@ define double @load_atomic_f64_local(ptr addrspace(3) %ptr) { define double @load_atomic_f64_flat_system(ptr %ptr) { ; CHECK-LABEL: define double @load_atomic_f64_flat_system( ; CHECK-SAME: ptr [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i64, ptr [[PTR]] seq_cst, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to double +; CHECK-NEXT: [[TMP2:%.*]] = load atomic double, ptr [[PTR]] seq_cst, align 8, !some.unknown.md [[META0]] ; CHECK-NEXT: ret double [[TMP2]] ; %ld = load atomic double, ptr %ptr seq_cst, align 8, !some.unknown.md !0 @@ -182,8 +166,7 @@ define double @load_atomic_f64_flat_system(ptr %ptr) { define double @load_atomic_f64_flat_agent(ptr %ptr) { ; CHECK-LABEL: define double @load_atomic_f64_flat_agent( ; CHECK-SAME: ptr [[PTR:%.*]]) { -; CHECK-NEXT: [[TMP1:%.*]] = load atomic i64, ptr [[PTR]] syncscope("agent") seq_cst, align 8 -; CHECK-NEXT: [[TMP2:%.*]] = bitcast i64 [[TMP1]] to double +; CHECK-NEXT: [[TMP2:%.*]] = load atomic double, ptr [[PTR]] syncscope("agent") seq_cst, align 8, !some.unknown.md [[META0]] ; CHECK-NEXT: ret double [[TMP2]] ; %ld = load atomic double, ptr %ptr syncscope("agent") seq_cst, align 8, !some.unknown.md !0 @@ -193,3 +176,6 @@ define double @load_atomic_f64_flat_agent(ptr %ptr) { !0 = !{} +;. +; CHECK: [[META0]] = !{} +;. -- GitLab From 5c969af66ac1ea58425101772ad099698f49a20d Mon Sep 17 00:00:00 2001 From: Kiran Chandramohan Date: Fri, 26 Apr 2024 11:21:34 +0100 Subject: [PATCH 041/301] [Flang][OpenMP] Skip default privatization of implied do indices (#89915) The scope of these indices is limited to the implied-do and is mapped to SSA values or registers and hence need not be privatized. Fixes #87216 --- flang/lib/Lower/OpenMP/DataSharingProcessor.cpp | 1 + .../Lower/OpenMP/default-clause-implied-do-fix.f90 | 11 +++++++++++ 2 files changed, 12 insertions(+) create mode 100644 flang/test/Lower/OpenMP/default-clause-implied-do-fix.f90 diff --git a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp index b419686e8ce4..d94c32375c0d 100644 --- a/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp +++ b/flang/lib/Lower/OpenMP/DataSharingProcessor.cpp @@ -339,6 +339,7 @@ void DataSharingProcessor::defaultPrivatize( if (!Fortran::semantics::IsProcedure(*sym) && !sym->GetUltimate().has() && !sym->GetUltimate().has() && + !Fortran::semantics::IsImpliedDoIndex(sym->GetUltimate()) && !symbolsInNestedRegions.contains(sym) && !symbolsInParentRegions.contains(sym) && !privatizedSymbols.contains(sym)) diff --git a/flang/test/Lower/OpenMP/default-clause-implied-do-fix.f90 b/flang/test/Lower/OpenMP/default-clause-implied-do-fix.f90 new file mode 100644 index 000000000000..25579272a6e0 --- /dev/null +++ b/flang/test/Lower/OpenMP/default-clause-implied-do-fix.f90 @@ -0,0 +1,11 @@ +!RUN: %flang_fc1 -emit-hlfir -fopenmp %s -o - | FileCheck %s + +!CHECK: @_QPsb +subroutine sb(a) + integer :: a(:) +!CHECK: omp.parallel + !$omp parallel default(private) +!CHECK: hlfir.elemental + if (any(a/=(/(100,i=1,5)/))) print *, "OK" + !$omp end parallel +end subroutine -- GitLab From 0fa1f1f2d117564d86a0df8383e84341ba85c531 Mon Sep 17 00:00:00 2001 From: Paul Walker Date: Fri, 26 Apr 2024 11:25:55 +0100 Subject: [PATCH 042/301] [LLVM][SVE] Seperate the int and floating-point variants of addqv. (#89762) We only use common intrinsics for operations that treat their element type as a container of bits. --- clang/include/clang/Basic/arm_sve.td | 27 ++++++++++--------- .../acle_sve2p1_fp_reduce.c | 12 ++++----- llvm/include/llvm/IR/IntrinsicsAArch64.td | 10 ++++--- llvm/lib/IR/AutoUpgrade.cpp | 12 +++++++++ .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 +- 5 files changed, 39 insertions(+), 24 deletions(-) diff --git a/clang/include/clang/Basic/arm_sve.td b/clang/include/clang/Basic/arm_sve.td index 6cc249837d3f..15340ebb62b3 100644 --- a/clang/include/clang/Basic/arm_sve.td +++ b/clang/include/clang/Basic/arm_sve.td @@ -1961,19 +1961,20 @@ def SVPSEL_D : SInst<"svpsel_lane_b64", "PPPm", "Pl", MergeNone, "", [IsStreamin // Standalone sve2.1 builtins let TargetGuard = "sve2p1" in { -def SVORQV : SInst<"svorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_orqv", [IsReductionQV]>; -def SVEORQV : SInst<"sveorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_eorqv", [IsReductionQV]>; -def SVADDQV : SInst<"svaddqv[_{d}]", "{Pd", "hfdcsilUcUsUiUl", MergeNone, "aarch64_sve_addqv", [IsReductionQV]>; -def SVANDQV : SInst<"svandqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_andqv", [IsReductionQV]>; -def SVSMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_smaxqv", [IsReductionQV]>; -def SVUMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_umaxqv", [IsReductionQV]>; -def SVSMINQV : SInst<"svminqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_sminqv", [IsReductionQV]>; -def SVUMINQV : SInst<"svminqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_uminqv", [IsReductionQV]>; - -def SVFMAXNMQV: SInst<"svmaxnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxnmqv", [IsReductionQV]>; -def SVFMINNMQV: SInst<"svminnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminnmqv", [IsReductionQV]>; -def SVFMAXQV: SInst<"svmaxqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxqv", [IsReductionQV]>; -def SVFMINQV: SInst<"svminqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminqv", [IsReductionQV]>; +def SVORQV : SInst<"svorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_orqv", [IsReductionQV]>; +def SVEORQV : SInst<"sveorqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_eorqv", [IsReductionQV]>; +def SVADDQV : SInst<"svaddqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_addqv", [IsReductionQV]>; +def SVANDQV : SInst<"svandqv[_{d}]", "{Pd", "csilUcUsUiUl", MergeNone, "aarch64_sve_andqv", [IsReductionQV]>; +def SVSMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_smaxqv", [IsReductionQV]>; +def SVUMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_umaxqv", [IsReductionQV]>; +def SVSMINQV : SInst<"svminqv[_{d}]", "{Pd", "csil", MergeNone, "aarch64_sve_sminqv", [IsReductionQV]>; +def SVUMINQV : SInst<"svminqv[_{d}]", "{Pd", "UcUsUiUl", MergeNone, "aarch64_sve_uminqv", [IsReductionQV]>; + +def SVFADDQV : SInst<"svaddqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_faddqv", [IsReductionQV]>; +def SVFMAXNMQV : SInst<"svmaxnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxnmqv", [IsReductionQV]>; +def SVFMINNMQV : SInst<"svminnmqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminnmqv", [IsReductionQV]>; +def SVFMAXQV : SInst<"svmaxqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fmaxqv", [IsReductionQV]>; +def SVFMINQV : SInst<"svminqv[_{d}]", "{Pd", "hfd", MergeNone, "aarch64_sve_fminqv", [IsReductionQV]>; } let TargetGuard = "sve2p1|sme2" in { diff --git a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c index e58cf4e49a37..9d5ffdafe866 100644 --- a/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c +++ b/clang/test/CodeGen/aarch64-sve2p1-intrinsics/acle_sve2p1_fp_reduce.c @@ -20,13 +20,13 @@ // CHECK-LABEL: @test_svaddqv_f16( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16( [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.faddqv.v8f16.nxv8f16( [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret <8 x half> [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svaddqv_f16u10__SVBool_tu13__SVFloat16_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv8i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.addqv.v8f16.nxv8f16( [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <8 x half> @llvm.aarch64.sve.faddqv.v8f16.nxv8f16( [[TMP0]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret <8 x half> [[TMP1]] // float16x8_t test_svaddqv_f16(svbool_t pg, svfloat16_t op) @@ -37,13 +37,13 @@ float16x8_t test_svaddqv_f16(svbool_t pg, svfloat16_t op) // CHECK-LABEL: @test_svaddqv_f32( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32( [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.faddqv.v4f32.nxv4f32( [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret <4 x float> [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svaddqv_f32u10__SVBool_tu13__SVFloat32_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv4i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.addqv.v4f32.nxv4f32( [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <4 x float> @llvm.aarch64.sve.faddqv.v4f32.nxv4f32( [[TMP0]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret <4 x float> [[TMP1]] // float32x4_t test_svaddqv_f32(svbool_t pg, svfloat32_t op) @@ -54,13 +54,13 @@ float32x4_t test_svaddqv_f32(svbool_t pg, svfloat32_t op) // CHECK-LABEL: @test_svaddqv_f64( // CHECK-NEXT: entry: // CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64( [[TMP0]], [[OP:%.*]]) +// CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.faddqv.v2f64.nxv2f64( [[TMP0]], [[OP:%.*]]) // CHECK-NEXT: ret <2 x double> [[TMP1]] // // CPP-CHECK-LABEL: @_Z16test_svaddqv_f64u10__SVBool_tu13__SVFloat64_t( // CPP-CHECK-NEXT: entry: // CPP-CHECK-NEXT: [[TMP0:%.*]] = tail call @llvm.aarch64.sve.convert.from.svbool.nxv2i1( [[PG:%.*]]) -// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.addqv.v2f64.nxv2f64( [[TMP0]], [[OP:%.*]]) +// CPP-CHECK-NEXT: [[TMP1:%.*]] = tail call <2 x double> @llvm.aarch64.sve.faddqv.v2f64.nxv2f64( [[TMP0]], [[OP:%.*]]) // CPP-CHECK-NEXT: ret <2 x double> [[TMP1]] // float64x2_t test_svaddqv_f64(svbool_t pg, svfloat64_t op) diff --git a/llvm/include/llvm/IR/IntrinsicsAArch64.td b/llvm/include/llvm/IR/IntrinsicsAArch64.td index bcaa37de74b6..e31e00a9c76f 100644 --- a/llvm/include/llvm/IR/IntrinsicsAArch64.td +++ b/llvm/include/llvm/IR/IntrinsicsAArch64.td @@ -1762,6 +1762,7 @@ def int_aarch64_sve_uqsub_x : AdvSIMD_2VectorArg_Intrinsic; def int_aarch64_sve_orqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; def int_aarch64_sve_eorqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; def int_aarch64_sve_andqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_addqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; def int_aarch64_sve_smaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; def int_aarch64_sve_umaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; def int_aarch64_sve_sminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; @@ -2079,11 +2080,12 @@ def int_aarch64_sve_fmaxv : AdvSIMD_SVE_Reduce_Intrinsic; def int_aarch64_sve_fmaxnmv : AdvSIMD_SVE_Reduce_Intrinsic; def int_aarch64_sve_fminv : AdvSIMD_SVE_Reduce_Intrinsic; def int_aarch64_sve_fminnmv : AdvSIMD_SVE_Reduce_Intrinsic; -def int_aarch64_sve_addqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; + +def int_aarch64_sve_faddqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; def int_aarch64_sve_fmaxnmqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; def int_aarch64_sve_fminnmqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; -def int_aarch64_sve_fmaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; -def int_aarch64_sve_fminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_fmaxqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; +def int_aarch64_sve_fminqv : AdvSIMD_SVE_V128_Reduce_Intrinsic; // // Floating-point conversions @@ -3646,4 +3648,4 @@ def int_aarch64_sve_pmov_to_pred_lane_zero : SVE2_1VectorArg_Pred_Intrinsic; def int_aarch64_sve_pmov_to_vector_lane_merging : SVE2_Pred_1VectorArgIndexed_Intrinsic; -def int_aarch64_sve_pmov_to_vector_lane_zeroing : SVE2_Pred_1VectorArg_Intrinsic; \ No newline at end of file +def int_aarch64_sve_pmov_to_vector_lane_zeroing : SVE2_Pred_1VectorArg_Intrinsic; diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 634b2dd5119e..6dc5b9aae769 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -846,6 +846,18 @@ static bool upgradeArmOrAarch64IntrinsicFunction(bool IsArm, Function *F, return false; // No other 'aarch64.sve.bf*'. } + if (Name.consume_front("addqv")) { + // 'aarch64.sve.addqv'. + if (!F->getReturnType()->isFPOrFPVectorTy()) + return false; + + auto Args = F->getFunctionType()->params(); + Type *Tys[] = {F->getReturnType(), Args[1]}; + NewFn = Intrinsic::getDeclaration(F->getParent(), + Intrinsic::aarch64_sve_faddqv, Tys); + return true; + } + if (Name.consume_front("ld")) { // 'aarch64.sve.ld*'. static const Regex LdRegex("^[234](.nxv[a-z0-9]+|$)"); diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 525ae79da996..3331ba7f99a1 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -4119,7 +4119,7 @@ defm BFCLAMP_ZZZ : sve2p1_bfclamp<"bfclamp", AArch64fclamp>; // SME2.1 or SVE2.1 instructions //===----------------------------------------------------------------------===// let Predicates = [HasSVE2p1_or_HasSME2p1] in { -defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv", int_aarch64_sve_addqv>; +defm FADDQV : sve2p1_fp_reduction_q<0b000, "faddqv", int_aarch64_sve_faddqv>; defm FMAXNMQV : sve2p1_fp_reduction_q<0b100, "fmaxnmqv", int_aarch64_sve_fmaxnmqv>; defm FMINNMQV : sve2p1_fp_reduction_q<0b101, "fminnmqv", int_aarch64_sve_fminnmqv>; defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv", int_aarch64_sve_fmaxqv>; -- GitLab From 12adaac7edf47f50bed536dd5e6eb1fd1caeef9f Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 26 Apr 2024 10:16:47 +0100 Subject: [PATCH 043/301] [X86] Split off or + blend/shuffle combine tests from combine-or.ll Add additional cpu test coverage --- llvm/test/CodeGen/X86/combine-or-shuffle.ll | 862 ++++++++++++++++++++ llvm/test/CodeGen/X86/combine-or.ll | 505 +----------- 2 files changed, 900 insertions(+), 467 deletions(-) create mode 100644 llvm/test/CodeGen/X86/combine-or-shuffle.ll diff --git a/llvm/test/CodeGen/X86/combine-or-shuffle.ll b/llvm/test/CodeGen/X86/combine-or-shuffle.ll new file mode 100644 index 000000000000..175d21a4f706 --- /dev/null +++ b/llvm/test/CodeGen/X86/combine-or-shuffle.ll @@ -0,0 +1,862 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse | FileCheck %s -check-prefixes=SSE,SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.1 | FileCheck %s -check-prefixes=SSE,SSE4 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s -check-prefixes=AVX,AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s -check-prefixes=AVX,AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 | FileCheck %s -check-prefixes=AVX,AVX512 + +; Verify that each of the following test cases is folded into a single +; instruction which performs a blend operation. + +define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: test1: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test1: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test1: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> + %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> + %or = or <2 x i64> %shuf1, %shuf2 + ret <2 x i64> %or +} + + +define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test2: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test2: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test2: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: test3: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test3: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test3: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> + %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> + %or = or <2 x i64> %shuf1, %shuf2 + ret <2 x i64> %or +} + + +define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test4: +; SSE2: # %bb.0: +; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE4-LABEL: test4: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test4: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test5: +; SSE2: # %bb.0: +; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test5: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test5: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test6: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test6: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test6: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test7: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test7: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test7: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX-NEXT: retq + %and1 = and <4 x i32> %a, + %and2 = and <4 x i32> %b, + %or = or <4 x i32> %and1, %and2 + ret <4 x i32> %or +} + + +define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: test8: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test8: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test8: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; AVX-NEXT: retq + %and1 = and <2 x i64> %a, + %and2 = and <2 x i64> %b, + %or = or <2 x i64> %and1, %and2 + ret <2 x i64> %or +} + + +define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test9: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test9: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test9: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %and1 = and <4 x i32> %a, + %and2 = and <4 x i32> %b, + %or = or <4 x i32> %and1, %and2 + ret <4 x i32> %or +} + + +define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) { +; SSE2-LABEL: test10: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test10: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test10: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %and1 = and <2 x i64> %a, + %and2 = and <2 x i64> %b, + %or = or <2 x i64> %and1, %and2 + ret <2 x i64> %or +} + + +define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test11: +; SSE2: # %bb.0: +; SSE2-NEXT: movss {{.*#+}} xmm1 = xmm0[0],xmm1[1,2,3] +; SSE2-NEXT: movaps %xmm1, %xmm0 +; SSE2-NEXT: retq +; +; SSE4-LABEL: test11: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test11: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] +; AVX-NEXT: retq + %and1 = and <4 x i32> %a, + %and2 = and <4 x i32> %b, + %or = or <4 x i32> %and1, %and2 + ret <4 x i32> %or +} + + +define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test12: +; SSE2: # %bb.0: +; SSE2-NEXT: movss {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test12: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test12: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; AVX-NEXT: retq + %and1 = and <4 x i32> %a, + %and2 = and <4 x i32> %b, + %or = or <4 x i32> %and1, %and2 + ret <4 x i32> %or +} + + +; Verify that the following test cases are folded into single shuffles. + +define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) { +; SSE-LABEL: test13: +; SSE: # %bb.0: +; SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3] +; SSE-NEXT: retq +; +; AVX-LABEL: test13: +; AVX: # %bb.0: +; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) { +; SSE-LABEL: test14: +; SSE: # %bb.0: +; SSE-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; SSE-NEXT: retq +; +; AVX-LABEL: test14: +; AVX: # %bb.0: +; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] +; AVX-NEXT: retq + %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> + %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> + %or = or <2 x i64> %shuf1, %shuf2 + ret <2 x i64> %or +} + + +define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) { +; SSE-LABEL: test15: +; SSE: # %bb.0: +; SSE-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,1],xmm0[2,1] +; SSE-NEXT: movaps %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: test15: +; AVX: # %bb.0: +; AVX-NEXT: vshufps {{.*#+}} xmm0 = xmm1[2,1],xmm0[2,1] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) { +; SSE-LABEL: test16: +; SSE: # %bb.0: +; SSE-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] +; SSE-NEXT: movaps %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: test16: +; AVX: # %bb.0: +; AVX-NEXT: vmovlhps {{.*#+}} xmm0 = xmm1[0],xmm0[0] +; AVX-NEXT: retq + %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> + %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> + %or = or <2 x i64> %shuf1, %shuf2 + ret <2 x i64> %or +} + + +; Verify that the dag-combiner does not fold a OR of two shuffles into a single +; shuffle instruction when the shuffle indexes are not compatible. + +define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) { +; SSE-LABEL: test17: +; SSE: # %bb.0: +; SSE-NEXT: psllq $32, %xmm0 +; SSE-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero +; SSE-NEXT: por %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: test17: +; AVX: # %bb.0: +; AVX-NEXT: vpsllq $32, %xmm0, %xmm0 +; AVX-NEXT: vmovq {{.*#+}} xmm1 = xmm1[0],zero +; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test18: +; SSE2: # %bb.0: +; SSE2-NEXT: xorps %xmm2, %xmm2 +; SSE2-NEXT: xorps %xmm3, %xmm3 +; SSE2-NEXT: movss {{.*#+}} xmm3 = xmm0[0],xmm3[1,2,3] +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm3[1,0,1,1] +; SSE2-NEXT: movss {{.*#+}} xmm2 = xmm1[0],xmm2[1,2,3] +; SSE2-NEXT: orps %xmm0, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE4-LABEL: test18: +; SSE4: # %bb.0: +; SSE4-NEXT: pxor %xmm2, %xmm2 +; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7] +; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1] +; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; SSE4-NEXT: por %xmm0, %xmm2 +; SSE4-NEXT: movdqa %xmm2, %xmm0 +; SSE4-NEXT: retq +; +; AVX1-LABEL: test18: +; AVX1: # %bb.0: +; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3] +; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,1,1] +; AVX1-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3] +; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: test18: +; AVX2: # %bb.0: +; AVX2-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm0[0],xmm2[1,2,3] +; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[1,0,1,1] +; AVX2-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1,2,3] +; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test18: +; AVX512: # %bb.0: +; AVX512-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3],zero,zero,zero,zero,zero,zero,zero,zero +; AVX512-NEXT: vpxor %xmm2, %xmm2, %xmm2 +; AVX512-NEXT: vpblendw {{.*#+}} xmm1 = xmm1[0,1],xmm2[2,3,4,5,6,7] +; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test19: +; SSE2: # %bb.0: +; SSE2-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,3,2,3] +; SSE2-NEXT: pxor %xmm2, %xmm2 +; SSE2-NEXT: punpckldq {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1] +; SSE2-NEXT: movdqa %xmm1, %xmm0 +; SSE2-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0],xmm1[2,2] +; SSE2-NEXT: orps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE4-LABEL: test19: +; SSE4: # %bb.0: +; SSE4-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,3] +; SSE4-NEXT: pxor %xmm3, %xmm3 +; SSE4-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] +; SSE4-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2] +; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5,6,7] +; SSE4-NEXT: por %xmm2, %xmm0 +; SSE4-NEXT: retq +; +; AVX1-LABEL: test19: +; AVX1: # %bb.0: +; AVX1-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,3] +; AVX1-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; AVX1-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3] +; AVX1-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,1,2,2] +; AVX1-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3] +; AVX1-NEXT: vorps %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: test19: +; AVX2: # %bb.0: +; AVX2-NEXT: vshufps {{.*#+}} xmm0 = xmm0[0,0,2,3] +; AVX2-NEXT: vxorps %xmm2, %xmm2, %xmm2 +; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm2[0],xmm0[1],xmm2[2],xmm0[3] +; AVX2-NEXT: vshufps {{.*#+}} xmm1 = xmm1[0,1,2,2] +; AVX2-NEXT: vblendps {{.*#+}} xmm1 = xmm1[0],xmm2[1],xmm1[2,3] +; AVX2-NEXT: vorps %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: test19: +; AVX512: # %bb.0: +; AVX512-NEXT: vpshufb {{.*#+}} xmm0 = zero,zero,zero,zero,xmm0[0,1,2,3],zero,zero,zero,zero,xmm0[12,13,14,15] +; AVX512-NEXT: vpshufb {{.*#+}} xmm1 = xmm1[0,1,2,3],zero,zero,zero,zero,xmm1[8,9,10,11,8,9,10,11] +; AVX512-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) { +; SSE-LABEL: test20: +; SSE: # %bb.0: +; SSE-NEXT: por %xmm1, %xmm0 +; SSE-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero +; SSE-NEXT: retq +; +; AVX-LABEL: test20: +; AVX: # %bb.0: +; AVX-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX-NEXT: vmovq {{.*#+}} xmm0 = xmm0[0],zero +; AVX-NEXT: retq + %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> + %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> + %or = or <2 x i64> %shuf1, %shuf2 + ret <2 x i64> %or +} + + +define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) { +; SSE-LABEL: test21: +; SSE: # %bb.0: +; SSE-NEXT: por %xmm1, %xmm0 +; SSE-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] +; SSE-NEXT: retq +; +; AVX1-LABEL: test21: +; AVX1: # %bb.0: +; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] +; AVX1-NEXT: retq +; +; AVX2-LABEL: test21: +; AVX2: # %bb.0: +; AVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] +; AVX2-NEXT: retq +; +; AVX512-LABEL: test21: +; AVX512: # %bb.0: +; AVX512-NEXT: vorpd %xmm1, %xmm0, %xmm0 +; AVX512-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] +; AVX512-NEXT: retq + %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> + %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> + %or = or <2 x i64> %shuf1, %shuf2 + ret <2 x i64> %or +} + + +; Verify that the dag-combiner keeps the correct domain for float/double vectors +; bitcast to use the mask-or blend combine. + +define <2 x double> @test22(<2 x double> %a0, <2 x double> %a1) { +; SSE2-LABEL: test22: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test22: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test22: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %bc1 = bitcast <2 x double> %a0 to <2 x i64> + %bc2 = bitcast <2 x double> %a1 to <2 x i64> + %and1 = and <2 x i64> %bc1, + %and2 = and <2 x i64> %bc2, + %or = or <2 x i64> %and1, %and2 + %bc3 = bitcast <2 x i64> %or to <2 x double> + ret <2 x double> %bc3 +} + + +define <4 x float> @test23(<4 x float> %a0, <4 x float> %a1) { +; SSE2-LABEL: test23: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,2],xmm1[0,3] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0,1,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test23: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test23: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] +; AVX-NEXT: retq + %bc1 = bitcast <4 x float> %a0 to <4 x i32> + %bc2 = bitcast <4 x float> %a1 to <4 x i32> + %and1 = and <4 x i32> %bc1, + %and2 = and <4 x i32> %bc2, + %or = or <4 x i32> %and1, %and2 + %bc3 = bitcast <4 x i32> %or to <4 x float> + ret <4 x float> %bc3 +} + + +define <4 x float> @test24(<4 x float> %a0, <4 x float> %a1) { +; SSE2-LABEL: test24: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test24: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test24: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %bc1 = bitcast <4 x float> %a0 to <2 x i64> + %bc2 = bitcast <4 x float> %a1 to <2 x i64> + %and1 = and <2 x i64> %bc1, + %and2 = and <2 x i64> %bc2, + %or = or <2 x i64> %and1, %and2 + %bc3 = bitcast <2 x i64> %or to <4 x float> + ret <4 x float> %bc3 +} + + +define <4 x float> @test25(<4 x float> %a0) { +; SSE2-LABEL: test25: +; SSE2: # %bb.0: +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,2],mem[0,3] +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,0,1,3] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test25: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = mem[0],xmm0[1,2],mem[3] +; SSE4-NEXT: retq +; +; AVX1-LABEL: test25: +; AVX1: # %bb.0: +; AVX1-NEXT: vblendps {{.*#+}} xmm0 = mem[0],xmm0[1,2],mem[3] +; AVX1-NEXT: retq +; +; AVX2-LABEL: test25: +; AVX2: # %bb.0: +; AVX2-NEXT: vbroadcastss {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX2-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] +; AVX2-NEXT: retq +; +; AVX512-LABEL: test25: +; AVX512: # %bb.0: +; AVX512-NEXT: vbroadcastss {{.*#+}} xmm1 = [1.0E+0,1.0E+0,1.0E+0,1.0E+0] +; AVX512-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] +; AVX512-NEXT: retq + %bc1 = bitcast <4 x float> %a0 to <4 x i32> + %bc2 = bitcast <4 x float> to <4 x i32> + %and1 = and <4 x i32> %bc1, + %and2 = and <4 x i32> %bc2, + %or = or <4 x i32> %and1, %and2 + %bc3 = bitcast <4 x i32> %or to <4 x float> + ret <4 x float> %bc3 +} + + +; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle +; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to +; handle legal vector value types. +define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) { +; SSE2-LABEL: test_crash: +; SSE2: # %bb.0: +; SSE2-NEXT: movaps {{.*#+}} xmm2 = [65535,0,65535,65535,65535,65535,65535,65535] +; SSE2-NEXT: andps %xmm2, %xmm1 +; SSE2-NEXT: andnps %xmm0, %xmm2 +; SSE2-NEXT: orps %xmm1, %xmm2 +; SSE2-NEXT: movaps %xmm2, %xmm0 +; SSE2-NEXT: retq +; +; SSE4-LABEL: test_crash: +; SSE4: # %bb.0: +; SSE4-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3,4,5,6,7] +; SSE4-NEXT: retq +; +; AVX-LABEL: test_crash: +; AVX: # %bb.0: +; AVX-NEXT: vpblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3,4,5,6,7] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32> + %or = or <4 x i8> %shuf1, %shuf2 + ret <4 x i8> %or +} + +; Verify that we can fold regardless of which operand is the zeroinitializer + +define <4 x i32> @test2b(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test2b: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test2b: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test2b: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + +define <4 x i32> @test2c(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test2c: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test2c: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test2c: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> + %shuf2 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %b, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + + +define <4 x i32> @test2d(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test2d: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test2d: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test2d: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> + %shuf2 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %b, <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + +; Make sure we can have an undef where an index pointing to the zero vector should be + +define <4 x i32> @test2e(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test2e: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test2e: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test2e: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> , <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> , <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + +define <4 x i32> @test2f(<4 x i32> %a, <4 x i32> %b) { +; SSE2-LABEL: test2f: +; SSE2: # %bb.0: +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: retq +; +; SSE4-LABEL: test2f: +; SSE4: # %bb.0: +; SSE4-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; SSE4-NEXT: retq +; +; AVX-LABEL: test2f: +; AVX: # %bb.0: +; AVX-NEXT: vblendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] +; AVX-NEXT: retq + %shuf1 = shufflevector <4 x i32> %a, <4 x i32> , <4 x i32> + %shuf2 = shufflevector <4 x i32> %b, <4 x i32> , <4 x i32> + %or = or <4 x i32> %shuf1, %shuf2 + ret <4 x i32> %or +} + +; (or (and X, c1), c2) -> (and (or X, c2), c1|c2) iff (c1 & c2) != 0 + +define <2 x i64> @or_and_v2i64(<2 x i64> %a0) { +; SSE-LABEL: or_and_v2i64: +; SSE: # %bb.0: +; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: or_and_v2i64: +; AVX1: # %bb.0: +; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: or_and_v2i64: +; AVX2: # %bb.0: +; AVX2-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: or_and_v2i64: +; AVX512: # %bb.0: +; AVX512-NEXT: vpbroadcastq {{.*#+}} xmm1 = [7,7] +; AVX512-NEXT: vpternlogq $200, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to2}, %xmm1, %xmm0 +; AVX512-NEXT: retq + %1 = and <2 x i64> %a0, + %2 = or <2 x i64> %1, + ret <2 x i64> %2 +} + +define <4 x i32> @or_and_v4i32(<4 x i32> %a0) { +; SSE-LABEL: or_and_v4i32: +; SSE: # %bb.0: +; SSE-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE-NEXT: retq +; +; AVX1-LABEL: or_and_v4i32: +; AVX1: # %bb.0: +; AVX1-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX1-NEXT: retq +; +; AVX2-LABEL: or_and_v4i32: +; AVX2: # %bb.0: +; AVX2-NEXT: vorps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: retq +; +; AVX512-LABEL: or_and_v4i32: +; AVX512: # %bb.0: +; AVX512-NEXT: vpmovsxbd {{.*#+}} xmm1 = [3,3,15,7] +; AVX512-NEXT: vpternlogd $200, {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm0 +; AVX512-NEXT: retq + %1 = and <4 x i32> %a0, + %2 = or <4 x i32> %1, + ret <4 x i32> %2 +} + +; If all masked bits are going to be set, that's a constant fold. + +define <4 x i32> @or_and_v4i32_fold(<4 x i32> %a0) { +; SSE-LABEL: or_and_v4i32_fold: +; SSE: # %bb.0: +; SSE-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3] +; SSE-NEXT: retq +; +; AVX-LABEL: or_and_v4i32_fold: +; AVX: # %bb.0: +; AVX-NEXT: vbroadcastss {{.*#+}} xmm0 = [3,3,3,3] +; AVX-NEXT: retq + %1 = and <4 x i32> %a0, + %2 = or <4 x i32> %1, + ret <4 x i32> %2 +} diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll index 5188de543f72..57679f7e8f1f 100644 --- a/llvm/test/CodeGen/X86/combine-or.ll +++ b/llvm/test/CodeGen/X86/combine-or.ll @@ -1,6 +1,8 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s -check-prefixes=CHECK,CHECK-LV -; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -early-live-intervals | FileCheck %s -check-prefixes=CHECK,CHECK-LIS +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 | FileCheck %s -check-prefixes=CHECK,SSE +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7 -early-live-intervals | FileCheck %s -check-prefixes=CHECK,SSE +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=corei7-avx | FileCheck %s -check-prefixes=CHECK,AVX,AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v3 | FileCheck %s -check-prefixes=CHECK,AVX,AVX2 define i32 @or_self(i32 %x) { ; CHECK-LABEL: or_self: @@ -19,472 +21,34 @@ define <4 x i32> @or_self_vec(<4 x i32> %x) { ret <4 x i32> %or } -; Verify that each of the following test cases is folded into a single -; instruction which performs a blend operation. - -define <2 x i64> @test1(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test1: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> - %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> - %or = or <2 x i64> %shuf1, %shuf2 - ret <2 x i64> %or -} - - -define <4 x i32> @test2(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test2: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <2 x i64> @test3(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test3: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> - %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> - %or = or <2 x i64> %shuf1, %shuf2 - ret <2 x i64> %or -} - - -define <4 x i32> @test4(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test4: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <4 x i32> @test5(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test5: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <4 x i32> @test6(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test6: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <4 x i32> @test7(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test7: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; CHECK-NEXT: retq - %and1 = and <4 x i32> %a, - %and2 = and <4 x i32> %b, - %or = or <4 x i32> %and1, %and2 - ret <4 x i32> %or -} - - -define <2 x i64> @test8(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test8: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] -; CHECK-NEXT: retq - %and1 = and <2 x i64> %a, - %and2 = and <2 x i64> %b, - %or = or <2 x i64> %and1, %and2 - ret <2 x i64> %or -} - - -define <4 x i32> @test9(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test9: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %and1 = and <4 x i32> %a, - %and2 = and <4 x i32> %b, - %or = or <4 x i32> %and1, %and2 - ret <4 x i32> %or -} - - -define <2 x i64> @test10(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test10: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %and1 = and <2 x i64> %a, - %and2 = and <2 x i64> %b, - %or = or <2 x i64> %and1, %and2 - ret <2 x i64> %or -} - - -define <4 x i32> @test11(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test11: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm0[0],xmm1[1,2,3] -; CHECK-NEXT: retq - %and1 = and <4 x i32> %a, - %and2 = and <4 x i32> %b, - %or = or <4 x i32> %and1, %and2 - ret <4 x i32> %or -} - - -define <4 x i32> @test12(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test12: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] -; CHECK-NEXT: retq - %and1 = and <4 x i32> %a, - %and2 = and <4 x i32> %b, - %or = or <4 x i32> %and1, %and2 - ret <4 x i32> %or -} - - -; Verify that the following test cases are folded into single shuffles. - -define <4 x i32> @test13(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test13: -; CHECK: # %bb.0: -; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[1,1],xmm1[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <2 x i64> @test14(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test14: -; CHECK: # %bb.0: -; CHECK-NEXT: movlhps {{.*#+}} xmm0 = xmm0[0],xmm1[0] -; CHECK-NEXT: retq - %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> - %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> - %or = or <2 x i64> %shuf1, %shuf2 - ret <2 x i64> %or -} - - -define <4 x i32> @test15(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test15: -; CHECK: # %bb.0: -; CHECK-NEXT: shufps {{.*#+}} xmm1 = xmm1[2,1],xmm0[2,1] -; CHECK-NEXT: movaps %xmm1, %xmm0 -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <2 x i64> @test16(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test16: -; CHECK: # %bb.0: -; CHECK-NEXT: movlhps {{.*#+}} xmm1 = xmm1[0],xmm0[0] -; CHECK-NEXT: movaps %xmm1, %xmm0 -; CHECK-NEXT: retq - %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> - %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> - %or = or <2 x i64> %shuf1, %shuf2 - ret <2 x i64> %or -} - - -; Verify that the dag-combiner does not fold a OR of two shuffles into a single -; shuffle instruction when the shuffle indexes are not compatible. - -define <4 x i32> @test17(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test17: -; CHECK: # %bb.0: -; CHECK-NEXT: psllq $32, %xmm0 -; CHECK-NEXT: movq {{.*#+}} xmm1 = xmm1[0],zero -; CHECK-NEXT: por %xmm1, %xmm0 -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <4 x i32> @test18(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test18: -; CHECK: # %bb.0: -; CHECK-NEXT: pxor %xmm2, %xmm2 -; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm2[2,3,4,5,6,7] -; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,1] -; CHECK-NEXT: pblendw {{.*#+}} xmm2 = xmm1[0,1],xmm2[2,3,4,5,6,7] -; CHECK-NEXT: por %xmm0, %xmm2 -; CHECK-NEXT: movdqa %xmm2, %xmm0 -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <4 x i32> @test19(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test19: -; CHECK: # %bb.0: -; CHECK-NEXT: pshufd {{.*#+}} xmm2 = xmm0[0,0,2,3] -; CHECK-NEXT: pxor %xmm3, %xmm3 -; CHECK-NEXT: pblendw {{.*#+}} xmm2 = xmm3[0,1],xmm2[2,3],xmm3[4,5],xmm2[6,7] -; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm1[0,1,2,2] -; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1],xmm3[2,3],xmm0[4,5,6,7] -; CHECK-NEXT: por %xmm2, %xmm0 -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <2 x i64> @test20(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test20: -; CHECK: # %bb.0: -; CHECK-NEXT: por %xmm1, %xmm0 -; CHECK-NEXT: movq {{.*#+}} xmm0 = xmm0[0],zero -; CHECK-NEXT: retq - %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> - %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> - %or = or <2 x i64> %shuf1, %shuf2 - ret <2 x i64> %or -} - - -define <2 x i64> @test21(<2 x i64> %a, <2 x i64> %b) { -; CHECK-LABEL: test21: -; CHECK: # %bb.0: -; CHECK-NEXT: por %xmm1, %xmm0 -; CHECK-NEXT: pslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3,4,5,6,7] -; CHECK-NEXT: retq - %shuf1 = shufflevector <2 x i64> %a, <2 x i64> zeroinitializer, <2 x i32> - %shuf2 = shufflevector <2 x i64> %b, <2 x i64> zeroinitializer, <2 x i32> - %or = or <2 x i64> %shuf1, %shuf2 - ret <2 x i64> %or -} - - -; Verify that the dag-combiner keeps the correct domain for float/double vectors -; bitcast to use the mask-or blend combine. - -define <2 x double> @test22(<2 x double> %a0, <2 x double> %a1) { -; CHECK-LABEL: test22: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %bc1 = bitcast <2 x double> %a0 to <2 x i64> - %bc2 = bitcast <2 x double> %a1 to <2 x i64> - %and1 = and <2 x i64> %bc1, - %and2 = and <2 x i64> %bc2, - %or = or <2 x i64> %and1, %and2 - %bc3 = bitcast <2 x i64> %or to <2 x double> - ret <2 x double> %bc3 -} - - -define <4 x float> @test23(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: test23: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0],xmm0[1,2],xmm1[3] -; CHECK-NEXT: retq - %bc1 = bitcast <4 x float> %a0 to <4 x i32> - %bc2 = bitcast <4 x float> %a1 to <4 x i32> - %and1 = and <4 x i32> %bc1, - %and2 = and <4 x i32> %bc2, - %or = or <4 x i32> %and1, %and2 - %bc3 = bitcast <4 x i32> %or to <4 x float> - ret <4 x float> %bc3 -} - - -define <4 x float> @test24(<4 x float> %a0, <4 x float> %a1) { -; CHECK-LABEL: test24: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %bc1 = bitcast <4 x float> %a0 to <2 x i64> - %bc2 = bitcast <4 x float> %a1 to <2 x i64> - %and1 = and <2 x i64> %bc1, - %and2 = and <2 x i64> %bc2, - %or = or <2 x i64> %and1, %and2 - %bc3 = bitcast <2 x i64> %or to <4 x float> - ret <4 x float> %bc3 -} - - -define <4 x float> @test25(<4 x float> %a0) { -; CHECK-LABEL: test25: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = mem[0],xmm0[1,2],mem[3] -; CHECK-NEXT: retq - %bc1 = bitcast <4 x float> %a0 to <4 x i32> - %bc2 = bitcast <4 x float> to <4 x i32> - %and1 = and <4 x i32> %bc1, - %and2 = and <4 x i32> %bc2, - %or = or <4 x i32> %and1, %and2 - %bc3 = bitcast <4 x i32> %or to <4 x float> - ret <4 x float> %bc3 -} - - -; Verify that the DAGCombiner doesn't crash in the attempt to check if a shuffle -; with illegal type has a legal mask. Method 'isShuffleMaskLegal' only knows how to -; handle legal vector value types. -define <4 x i8> @test_crash(<4 x i8> %a, <4 x i8> %b) { -; CHECK-LABEL: test_crash: -; CHECK: # %bb.0: -; CHECK-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0],xmm0[1],xmm1[2,3,4,5,6,7] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i8> %a, <4 x i8> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i8> %b, <4 x i8> zeroinitializer, <4 x i32> - %or = or <4 x i8> %shuf1, %shuf2 - ret <4 x i8> %or -} - -; Verify that we can fold regardless of which operand is the zeroinitializer - -define <4 x i32> @test2b(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test2b: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> zeroinitializer, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - -define <4 x i32> @test2c(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test2c: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %a, <4 x i32> - %shuf2 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %b, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - - -define <4 x i32> @test2d(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test2d: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> zeroinitializer, <4 x i32> - %shuf2 = shufflevector <4 x i32> zeroinitializer, <4 x i32> %b, <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - -; Make sure we can have an undef where an index pointing to the zero vector should be - -define <4 x i32> @test2e(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test2e: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> , <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> , <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - -define <4 x i32> @test2f(<4 x i32> %a, <4 x i32> %b) { -; CHECK-LABEL: test2f: -; CHECK: # %bb.0: -; CHECK-NEXT: blendps {{.*#+}} xmm0 = xmm1[0,1],xmm0[2,3] -; CHECK-NEXT: retq - %shuf1 = shufflevector <4 x i32> %a, <4 x i32> , <4 x i32> - %shuf2 = shufflevector <4 x i32> %b, <4 x i32> , <4 x i32> - %or = or <4 x i32> %shuf1, %shuf2 - ret <4 x i32> %or -} - -; (or (and X, c1), c2) -> (and (or X, c2), c1|c2) iff (c1 & c2) != 0 - -define <2 x i64> @or_and_v2i64(<2 x i64> %a0) { -; CHECK-LABEL: or_and_v2i64: -; CHECK: # %bb.0: -; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; CHECK-NEXT: retq - %1 = and <2 x i64> %a0, - %2 = or <2 x i64> %1, - ret <2 x i64> %2 -} - -define <4 x i32> @or_and_v4i32(<4 x i32> %a0) { -; CHECK-LABEL: or_and_v4i32: -; CHECK: # %bb.0: -; CHECK-NEXT: orps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; CHECK-NEXT: retq - %1 = and <4 x i32> %a0, - %2 = or <4 x i32> %1, - ret <4 x i32> %2 -} - -; If all masked bits are going to be set, that's a constant fold. - -define <4 x i32> @or_and_v4i32_fold(<4 x i32> %a0) { -; CHECK-LABEL: or_and_v4i32_fold: -; CHECK: # %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm0 = [3,3,3,3] -; CHECK-NEXT: retq - %1 = and <4 x i32> %a0, - %2 = or <4 x i32> %1, - ret <4 x i32> %2 -} - ; fold (or x, c) -> c iff (x & ~c) == 0 define <2 x i64> @or_zext_v2i32(<2 x i32> %a0) { -; CHECK-LABEL: or_zext_v2i32: -; CHECK: # %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295] -; CHECK-NEXT: retq +; SSE-LABEL: or_zext_v2i32: +; SSE: # %bb.0: +; SSE-NEXT: movaps {{.*#+}} xmm0 = [4294967295,4294967295] +; SSE-NEXT: retq +; +; AVX-LABEL: or_zext_v2i32: +; AVX: # %bb.0: +; AVX-NEXT: vmovddup {{.*#+}} xmm0 = [4294967295,4294967295] +; AVX-NEXT: # xmm0 = mem[0,0] +; AVX-NEXT: retq %1 = zext <2 x i32> %a0 to <2 x i64> %2 = or <2 x i64> %1, ret <2 x i64> %2 } define <4 x i32> @or_zext_v4i16(<4 x i16> %a0) { -; CHECK-LABEL: or_zext_v4i16: -; CHECK: # %bb.0: -; CHECK-NEXT: movaps {{.*#+}} xmm0 = [65535,65535,65535,65535] -; CHECK-NEXT: retq +; SSE-LABEL: or_zext_v4i16: +; SSE: # %bb.0: +; SSE-NEXT: movaps {{.*#+}} xmm0 = [65535,65535,65535,65535] +; SSE-NEXT: retq +; +; AVX-LABEL: or_zext_v4i16: +; AVX: # %bb.0: +; AVX-NEXT: vbroadcastss {{.*#+}} xmm0 = [65535,65535,65535,65535] +; AVX-NEXT: retq %1 = zext <4 x i16> %a0 to <4 x i32> %2 = or <4 x i32> %1, ret <4 x i32> %2 @@ -522,12 +86,19 @@ define i64 @or_and_and_commute_i64(i64 %x, i64 %y) { } define <4 x i32> @or_and_and_v4i32(<4 x i32> %x, <4 x i32> %y) { -; CHECK-LABEL: or_and_and_v4i32: -; CHECK: # %bb.0: -; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; CHECK-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; CHECK-NEXT: orps %xmm1, %xmm0 -; CHECK-NEXT: retq +; SSE-LABEL: or_and_and_v4i32: +; SSE: # %bb.0: +; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE-NEXT: andps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE-NEXT: orps %xmm1, %xmm0 +; SSE-NEXT: retq +; +; AVX-LABEL: or_and_and_v4i32: +; AVX: # %bb.0: +; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 +; AVX-NEXT: vandps {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX-NEXT: vorps %xmm1, %xmm0, %xmm0 +; AVX-NEXT: retq %xy = or <4 x i32> %x, %y %mx = and <4 x i32> %x, %mxy = and <4 x i32> %xy, @@ -613,5 +184,5 @@ define i32 @or_and_multiuse_and_multiuse_i32(i32 %x, i32 %y) nounwind { declare void @use_i32(i32) ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; CHECK-LIS: {{.*}} -; CHECK-LV: {{.*}} +; AVX1: {{.*}} +; AVX2: {{.*}} -- GitLab From 28675109ccb69fbb6de93167a66a93663ceed65e Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 26 Apr 2024 11:24:08 +0100 Subject: [PATCH 044/301] [X86] Add test coverage for #89533 --- llvm/test/CodeGen/X86/combine-or.ll | 107 +++++++++++++++++++++++++++- 1 file changed, 104 insertions(+), 3 deletions(-) diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll index 57679f7e8f1f..8419001de236 100644 --- a/llvm/test/CodeGen/X86/combine-or.ll +++ b/llvm/test/CodeGen/X86/combine-or.ll @@ -182,7 +182,108 @@ define i32 @or_and_multiuse_and_multiuse_i32(i32 %x, i32 %y) nounwind { ret i32 %r } +define i64 @or_build_pair_not(i32 %a0, i32 %a1) { +; CHECK-LABEL: or_build_pair_not: +; CHECK: # %bb.0: +; CHECK-NEXT: # kill: def $esi killed $esi def $rsi +; CHECK-NEXT: # kill: def $edi killed $edi def $rdi +; CHECK-NEXT: notl %edi +; CHECK-NEXT: notl %esi +; CHECK-NEXT: shlq $32, %rsi +; CHECK-NEXT: leaq (%rsi,%rdi), %rax +; CHECK-NEXT: retq + %n0 = xor i32 %a0, -1 + %n1 = xor i32 %a1, -1 + %x0 = zext i32 %n0 to i64 + %x1 = zext i32 %n1 to i64 + %hi = shl i64 %x1, 32 + %r = or i64 %hi, %x0 + ret i64 %r +} + +define i64 @PR89533(<64 x i8> %a0) { +; SSE-LABEL: PR89533: +; SSE: # %bb.0: +; SSE-NEXT: movdqa {{.*#+}} xmm4 = [95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95] +; SSE-NEXT: pcmpeqb %xmm4, %xmm0 +; SSE-NEXT: pmovmskb %xmm0, %eax +; SSE-NEXT: xorl $65535, %eax # imm = 0xFFFF +; SSE-NEXT: pcmpeqb %xmm4, %xmm1 +; SSE-NEXT: pmovmskb %xmm1, %ecx +; SSE-NEXT: notl %ecx +; SSE-NEXT: shll $16, %ecx +; SSE-NEXT: orl %eax, %ecx +; SSE-NEXT: pcmpeqb %xmm4, %xmm2 +; SSE-NEXT: pmovmskb %xmm2, %edx +; SSE-NEXT: xorl $65535, %edx # imm = 0xFFFF +; SSE-NEXT: pcmpeqb %xmm4, %xmm3 +; SSE-NEXT: pmovmskb %xmm3, %eax +; SSE-NEXT: notl %eax +; SSE-NEXT: shll $16, %eax +; SSE-NEXT: orl %edx, %eax +; SSE-NEXT: shlq $32, %rax +; SSE-NEXT: orq %rcx, %rax +; SSE-NEXT: je .LBB11_2 +; SSE-NEXT: # %bb.1: # %cond.false +; SSE-NEXT: rep bsfq %rax, %rax +; SSE-NEXT: retq +; SSE-NEXT: .LBB11_2: # %cond.end +; SSE-NEXT: movl $64, %eax +; SSE-NEXT: retq +; +; AVX1-LABEL: PR89533: +; AVX1: # %bb.0: +; AVX1-NEXT: vbroadcastss {{.*#+}} xmm2 = [95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95] +; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm3 +; AVX1-NEXT: vpmovmskb %xmm3, %eax +; AVX1-NEXT: xorl $65535, %eax # imm = 0xFFFF +; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm0 +; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpmovmskb %xmm0, %ecx +; AVX1-NEXT: notl %ecx +; AVX1-NEXT: shll $16, %ecx +; AVX1-NEXT: orl %eax, %ecx +; AVX1-NEXT: vpcmpeqb %xmm2, %xmm1, %xmm0 +; AVX1-NEXT: vpmovmskb %xmm0, %edx +; AVX1-NEXT: xorl $65535, %edx # imm = 0xFFFF +; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm0 +; AVX1-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm0 +; AVX1-NEXT: vpmovmskb %xmm0, %eax +; AVX1-NEXT: notl %eax +; AVX1-NEXT: shll $16, %eax +; AVX1-NEXT: orl %edx, %eax +; AVX1-NEXT: shlq $32, %rax +; AVX1-NEXT: orq %rcx, %rax +; AVX1-NEXT: je .LBB11_2 +; AVX1-NEXT: # %bb.1: # %cond.false +; AVX1-NEXT: rep bsfq %rax, %rax +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; AVX1-NEXT: .LBB11_2: # %cond.end +; AVX1-NEXT: movl $64, %eax +; AVX1-NEXT: vzeroupper +; AVX1-NEXT: retq +; +; AVX2-LABEL: PR89533: +; AVX2: # %bb.0: +; AVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95] +; AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0 +; AVX2-NEXT: vpmovmskb %ymm0, %eax +; AVX2-NEXT: notl %eax +; AVX2-NEXT: vpcmpeqb %ymm2, %ymm1, %ymm0 +; AVX2-NEXT: vpmovmskb %ymm0, %ecx +; AVX2-NEXT: notl %ecx +; AVX2-NEXT: shlq $32, %rcx +; AVX2-NEXT: orq %rax, %rcx +; AVX2-NEXT: xorl %eax, %eax +; AVX2-NEXT: tzcntq %rcx, %rax +; AVX2-NEXT: vzeroupper +; AVX2-NEXT: retq + %cmp = icmp ne <64 x i8> %a0, + %mask = bitcast <64 x i1> %cmp to i64 + %tz = tail call i64 @llvm.cttz.i64(i64 %mask, i1 false) + ret i64 %tz +} + declare void @use_i32(i32) -;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: -; AVX1: {{.*}} -; AVX2: {{.*}} + -- GitLab From 1b2f970e9f40eb2a3bd082b6a660d4f58ba4f59b Mon Sep 17 00:00:00 2001 From: CarolineConcatto Date: Fri, 26 Apr 2024 11:32:21 +0100 Subject: [PATCH 045/301] [LLVM][AARCH64]Replace +sme2p1+smef16f16 by +smef16f16 (#88860) According to the latest ISA Spec release[1] all instructions under: HasSME2p1 and HasSMEF16F16 should now only require: HasSMEF16F16 [1]https://developer.arm.com --- .../llvm/TargetParser/AArch64TargetParser.h | 4 +- llvm/lib/Target/AArch64/AArch64.td | 2 +- llvm/lib/Target/AArch64/AArch64Features.td | 6 +- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 6 + .../lib/Target/AArch64/AArch64SMEInstrInfo.td | 4 +- .../test/MC/AArch64/SME2p1/fadd-diagnostics.s | 2 +- llvm/test/MC/AArch64/SME2p1/fadd.s | 110 +++---- llvm/test/MC/AArch64/SME2p1/fcvt.s | 20 +- .../MC/AArch64/SME2p1/fcvtl-diagnostics.s | 2 +- llvm/test/MC/AArch64/SME2p1/fcvtl.s | 20 +- .../test/MC/AArch64/SME2p1/fmla-diagnostics.s | 2 +- llvm/test/MC/AArch64/SME2p1/fmla.s | 300 +++++++++--------- .../test/MC/AArch64/SME2p1/fmls-diagnostics.s | 2 +- llvm/test/MC/AArch64/SME2p1/fmls.s | 300 +++++++++--------- .../MC/AArch64/SME2p1/fmopa-diagnostics.s | 2 +- llvm/test/MC/AArch64/SME2p1/fmopa.s | 36 +-- .../MC/AArch64/SME2p1/fmops-diagnostics.s | 2 +- llvm/test/MC/AArch64/SME2p1/fmops.s | 36 +-- .../test/MC/AArch64/SME2p1/fsub-diagnostics.s | 3 +- llvm/test/MC/AArch64/SME2p1/fsub.s | 108 +++---- 20 files changed, 489 insertions(+), 478 deletions(-) diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 805b963a7a13..44aa886b61b6 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -268,7 +268,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"sha3", AArch64::AEK_SHA3, "+sha3", "-sha3", FEAT_SHA3, "+sha3,+sha2,+fp-armv8,+neon", 140}, {"simd", AArch64::AEK_SIMD, "+neon", "-neon", FEAT_SIMD, "+fp-armv8,+neon", 100}, {"sm4", AArch64::AEK_SM4, "+sm4", "-sm4", FEAT_SM4, "+sm4,+fp-armv8,+neon", 106}, - {"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_INIT, "", 0}, + {"sme-f16f16", AArch64::AEK_SMEF16F16, "+sme-f16f16", "-sme-f16f16", FEAT_INIT, "+sme2,+sme-f16f16", 0}, {"sme-f64f64", AArch64::AEK_SMEF64F64, "+sme-f64f64", "-sme-f64f64", FEAT_SME_F64, "+sme,+sme-f64f64,+bf16", 560}, {"sme-i16i64", AArch64::AEK_SMEI16I64, "+sme-i16i64", "-sme-i16i64", FEAT_SME_I64, "+sme,+sme-i16i64,+bf16", 570}, {"sme", AArch64::AEK_SME, "+sme", "-sme", FEAT_SME, "+sme,+bf16", 430}, @@ -302,7 +302,7 @@ inline constexpr ExtensionInfo Extensions[] = { {"ssve-fp8dot4", AArch64::AEK_SSVE_FP8DOT4, "+ssve-fp8dot4", "-ssve-fp8dot4", FEAT_INIT, "+sme2", 0}, {"lut", AArch64::AEK_LUT, "+lut", "-lut", FEAT_INIT, "", 0}, {"sme-lutv2", AArch64::AEK_SME_LUTv2, "+sme-lutv2", "-sme-lutv2", FEAT_INIT, "", 0}, - {"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+sme2,+fp8", 0}, + {"sme-f8f16", AArch64::AEK_SMEF8F16, "+sme-f8f16", "-sme-f8f16", FEAT_INIT, "+fp8,+sme2", 0}, {"sme-f8f32", AArch64::AEK_SMEF8F32, "+sme-f8f32", "-sme-f8f32", FEAT_INIT, "+sme2,+fp8", 0}, {"sme-fa64", AArch64::AEK_SMEFA64, "+sme-fa64", "-sme-fa64", FEAT_INIT, "", 0}, {"cpa", AArch64::AEK_CPA, "+cpa", "-cpa", FEAT_INIT, "", 0}, diff --git a/llvm/lib/Target/AArch64/AArch64.td b/llvm/lib/Target/AArch64/AArch64.td index f2f1c93ea225..4b2ce0d73949 100644 --- a/llvm/lib/Target/AArch64/AArch64.td +++ b/llvm/lib/Target/AArch64/AArch64.td @@ -76,7 +76,7 @@ def SME2p1Unsupported : AArch64Unsupported; def SME2Unsupported : AArch64Unsupported { let F = !listconcat([HasSME2, HasSVE2orSME2, HasSVE2p1_or_HasSME2, HasSSVE_FP8FMA, - HasSMEF8F16, HasSMEF8F32], + HasSMEF8F16, HasSMEF8F32, HasSMEF16F16orSMEF8F16], SME2p1Unsupported.F); } diff --git a/llvm/lib/Target/AArch64/AArch64Features.td b/llvm/lib/Target/AArch64/AArch64Features.td index efda45a72ef4..3a3751a85afd 100644 --- a/llvm/lib/Target/AArch64/AArch64Features.td +++ b/llvm/lib/Target/AArch64/AArch64Features.td @@ -505,15 +505,15 @@ def FeatureSMEF64F64 : SubtargetFeature<"sme-f64f64", "HasSMEF64F64", "true", def FeatureSMEI16I64 : SubtargetFeature<"sme-i16i64", "HasSMEI16I64", "true", "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>; -def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", - "Enable SME2.1 non-widening Float16 instructions (FEAT_SME_F16F16)", []>; - def FeatureSMEFA64 : SubtargetFeature<"sme-fa64", "HasSMEFA64", "true", "Enable the full A64 instruction set in streaming SVE mode (FEAT_SME_FA64)", [FeatureSME, FeatureSVE2]>; def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true", "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>; +def FeatureSMEF16F16 : SubtargetFeature<"sme-f16f16", "HasSMEF16F16", "true", + "Enable SME non-widening Float16 instructions (FEAT_SME_F16F16)", [FeatureSME2]>; + def FeatureSME2p1 : SubtargetFeature<"sme2p1", "HasSME2p1", "true", "Enable Scalable Matrix Extension 2.1 (FEAT_SME2p1) instructions", [FeatureSME2]>; diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index a7abb58064a5..17d96370c04a 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -230,6 +230,12 @@ def HasSVE2p1_or_HasSME2 def HasSVE2p1_or_HasSME2p1 : Predicate<"Subtarget->hasSVE2p1() || Subtarget->hasSME2p1()">, AssemblerPredicateWithAll<(any_of FeatureSME2p1, FeatureSVE2p1), "sme2p1 or sve2p1">; + +def HasSMEF16F16orSMEF8F16 + : Predicate<"Subtarget->hasSMEF16F16() || Subtarget->hasSMEF8F16()">, + AssemblerPredicateWithAll<(any_of FeatureSMEF16F16, FeatureSMEF8F16), + "sme-f16f16 or sme-f8f16">; + // A subset of NEON instructions are legal in Streaming SVE execution mode, // they should be enabled if either has been specified. def HasNEONorSME diff --git a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td index 2db0fa253434..574178c8d524 100644 --- a/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td @@ -792,12 +792,14 @@ defm LUTI4_S_2ZTZI : sme2p1_luti4_vector_vg2_index<"luti4">; defm LUTI4_S_4ZTZI : sme2p1_luti4_vector_vg4_index<"luti4">; } -let Predicates = [HasSME2p1, HasSMEF16F16] in { +let Predicates = [HasSMEF16F16orSMEF8F16] in { defm FADD_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fadd", 0b0100, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; defm FADD_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fadd", 0b0100, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; defm FSUB_VG2_M2Z_H : sme2_multivec_accum_add_sub_vg2<"fsub", 0b0101, MatrixOp16, ZZ_h_mul_r, nxv8f16, null_frag>; defm FSUB_VG4_M4Z_H : sme2_multivec_accum_add_sub_vg4<"fsub", 0b0101, MatrixOp16, ZZZZ_h_mul_r, nxv8f16, null_frag>; +} +let Predicates = [HasSMEF16F16] in { defm FMLA_VG2_M2ZZI_H : sme2p1_multi_vec_array_vg2_index_16b<"fmla", 0b00, 0b100, ZZ_h_mul_r, ZPR4b16>; defm FMLA_VG4_M4ZZI_H : sme2p1_multi_vec_array_vg4_index_16b<"fmla", 0b000, ZZZZ_h_mul_r, ZPR4b16>; defm FMLA_VG2_M2ZZ_H : sme2_dot_mla_add_sub_array_vg24_single<"fmla", 0b0011100, MatrixOp16, ZZ_h, ZPR4b16>; diff --git a/llvm/test/MC/AArch64/SME2p1/fadd-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/fadd-diagnostics.s index c13a1be05b1c..a18989880a34 100644 --- a/llvm/test/MC/AArch64/SME2p1/fadd-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2p1/fadd-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Out of range index offset diff --git a/llvm/test/MC/AArch64/SME2p1/fadd.s b/llvm/test/MC/AArch64/SME2p1/fadd.s index a8e64a63dbdb..bdb769093c83 100644 --- a/llvm/test/MC/AArch64/SME2p1/fadd.s +++ b/llvm/test/MC/AArch64/SME2p1/fadd.s @@ -1,300 +1,302 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fadd za.h[w8, 0, vgx2], {z0.h, z1.h} // 11000001-10100100-00011100-00000000 // CHECK-INST: fadd za.h[w8, 0, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x00,0x1c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41c00 fadd za.h[w8, 0], {z0.h - z1.h} // 11000001-10100100-00011100-00000000 // CHECK-INST: fadd za.h[w8, 0, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x00,0x1c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41c00 fadd za.h[w10, 5, vgx2], {z10.h, z11.h} // 11000001-10100100-01011101-01000101 // CHECK-INST: fadd za.h[w10, 5, vgx2], { z10.h, z11.h } // CHECK-ENCODING: [0x45,0x5d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45d45 fadd za.h[w10, 5], {z10.h - z11.h} // 11000001-10100100-01011101-01000101 // CHECK-INST: fadd za.h[w10, 5, vgx2], { z10.h, z11.h } // CHECK-ENCODING: [0x45,0x5d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45d45 fadd za.h[w11, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-01111101-10000111 // CHECK-INST: fadd za.h[w11, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x87,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d87 fadd za.h[w11, 7], {z12.h - z13.h} // 11000001-10100100-01111101-10000111 // CHECK-INST: fadd za.h[w11, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x87,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d87 fadd za.h[w11, 7, vgx2], {z30.h, z31.h} // 11000001-10100100-01111111-11000111 // CHECK-INST: fadd za.h[w11, 7, vgx2], { z30.h, z31.h } // CHECK-ENCODING: [0xc7,0x7f,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47fc7 fadd za.h[w11, 7], {z30.h - z31.h} // 11000001-10100100-01111111-11000111 // CHECK-INST: fadd za.h[w11, 7, vgx2], { z30.h, z31.h } // CHECK-ENCODING: [0xc7,0x7f,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47fc7 fadd za.h[w8, 5, vgx2], {z16.h, z17.h} // 11000001-10100100-00011110-00000101 // CHECK-INST: fadd za.h[w8, 5, vgx2], { z16.h, z17.h } // CHECK-ENCODING: [0x05,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41e05 fadd za.h[w8, 5], {z16.h - z17.h} // 11000001-10100100-00011110-00000101 // CHECK-INST: fadd za.h[w8, 5, vgx2], { z16.h, z17.h } // CHECK-ENCODING: [0x05,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41e05 fadd za.h[w8, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-00011100-00000001 // CHECK-INST: fadd za.h[w8, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x01,0x1c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41c01 fadd za.h[w8, 1], {z0.h - z1.h} // 11000001-10100100-00011100-00000001 // CHECK-INST: fadd za.h[w8, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x01,0x1c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41c01 fadd za.h[w10, 0, vgx2], {z18.h, z19.h} // 11000001-10100100-01011110, 01000000 // CHECK-INST: fadd za.h[w10, 0, vgx2], { z18.h, z19.h } // CHECK-ENCODING: [0x40,0x5e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45e40 fadd za.h[w10, 0], {z18.h - z19.h} // 11000001-10100100-01011110-01000000 // CHECK-INST: fadd za.h[w10, 0, vgx2], { z18.h, z19.h } // CHECK-ENCODING: [0x40,0x5e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45e40 fadd za.h[w8, 0, vgx2], {z12.h, z13.h} // 11000001-10100100-00011101-10000000 // CHECK-INST: fadd za.h[w8, 0, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x80,0x1d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41d80 fadd za.h[w8, 0], {z12.h - z13.h} // 11000001-10100100-00011101-10000000 // CHECK-INST: fadd za.h[w8, 0, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x80,0x1d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41d80 fadd za.h[w10, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-01011100-00000001 // CHECK-INST: fadd za.h[w10, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x01,0x5c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45c01 fadd za.h[w10, 1], {z0.h - z1.h} // 11000001-10100100-01011100-00000001 // CHECK-INST: fadd za.h[w10, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x01,0x5c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45c01 fadd za.h[w8, 5, vgx2], {z22.h, z23.h} // 11000001-10100100-00011110, 11000101 // CHECK-INST: fadd za.h[w8, 5, vgx2], { z22.h, z23.h } // CHECK-ENCODING: [0xc5,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41ec5 fadd za.h[w8, 5], {z22.h - z23.h} // 11000001-10100100-00011110-11000101 // CHECK-INST: fadd za.h[w8, 5, vgx2], { z22.h, z23.h } // CHECK-ENCODING: [0xc5,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41ec5 fadd za.h[w11, 2, vgx2], {z8.h, z9.h} // 11000001-10100100-01111101-00000010 // CHECK-INST: fadd za.h[w11, 2, vgx2], { z8.h, z9.h } // CHECK-ENCODING: [0x02,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d02 fadd za.h[w11, 2], {z8.h - z9.h} // 11000001-10100100-01111101-00000010 // CHECK-INST: fadd za.h[w11, 2, vgx2], { z8.h, z9.h } // CHECK-ENCODING: [0x02,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d02 fadd za.h[w9, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-00111101-10000111 // CHECK-INST: fadd za.h[w9, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x87,0x3d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a43d87 fadd za.h[w9, 7], {z12.h - z13.h} // 11000001-10100100-00111101-10000111 // CHECK-INST: fadd za.h[w9, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x87,0x3d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a43d87 fadd za.h[w8, 0, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00000000 // CHECK-INST: fadd za.h[w8, 0, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x00,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c00 fadd za.h[w8, 0], {z0.h - z3.h} // 11000001-10100101-00011100-00000000 // CHECK-INST: fadd za.h[w8, 0, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x00,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c00 fadd za.h[w10, 5, vgx4], {z8.h - z11.h} // 11000001-10100101-01011101-00000101 // CHECK-INST: fadd za.h[w10, 5, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x05,0x5d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55d05 fadd za.h[w10, 5], {z8.h - z11.h} // 11000001-10100101-01011101-00000101 // CHECK-INST: fadd za.h[w10, 5, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x05,0x5d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55d05 fadd za.h[w11, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-01111101-10000111 // CHECK-INST: fadd za.h[w11, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x87,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d87 fadd za.h[w11, 7], {z12.h - z15.h} // 11000001-10100101-01111101-10000111 // CHECK-INST: fadd za.h[w11, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x87,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d87 fadd za.h[w11, 7, vgx4], {z28.h - z31.h} // 11000001-10100101-01111111-10000111 // CHECK-INST: fadd za.h[w11, 7, vgx4], { z28.h - z31.h } // CHECK-ENCODING: [0x87,0x7f,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57f87 fadd za.h[w11, 7], {z28.h - z31.h} // 11000001-10100101-01111111-10000111 // CHECK-INST: fadd za.h[w11, 7, vgx4], { z28.h - z31.h } // CHECK-ENCODING: [0x87,0x7f,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57f87 fadd za.h[w8, 5, vgx4], {z16.h - z19.h} // 11000001-10100101-00011110-00000101 // CHECK-INST: fadd za.h[w8, 5, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x05,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e05 fadd za.h[w8, 5], {z16.h - z19.h} // 11000001-10100101-00011110-00000101 // CHECK-INST: fadd za.h[w8, 5, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x05,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e05 fadd za.h[w8, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00000001 // CHECK-INST: fadd za.h[w8, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x01,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c01 fadd za.h[w8, 1], {z0.h - z3.h} // 11000001-10100101-00011100-00000001 // CHECK-INST: fadd za.h[w8, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x01,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c01 fadd za.h[w10, 0, vgx4], {z16.h - z19.h} // 11000001-10100101-01011110-00000000 // CHECK-INST: fadd za.h[w10, 0, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x00,0x5e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55e00 fadd za.h[w10, 0], {z16.h - z19.h} // 11000001-10100101-01011110-00000000 // CHECK-INST: fadd za.h[w10, 0, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x00,0x5e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55e00 fadd za.h[w8, 0, vgx4], {z12.h - z15.h} // 11000001-10100101-00011101-10000000 // CHECK-INST: fadd za.h[w8, 0, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x80,0x1d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51d80 fadd za.h[w8, 0], {z12.h - z15.h} // 11000001-10100101-00011101-10000000 // CHECK-INST: fadd za.h[w8, 0, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x80,0x1d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51d80 fadd za.h[w10, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-01011100-00000001 // CHECK-INST: fadd za.h[w10, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x01,0x5c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55c01 fadd za.h[w10, 1], {z0.h - z3.h} // 11000001-10100101-01011100-00000001 // CHECK-INST: fadd za.h[w10, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x01,0x5c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55c01 fadd za.h[w8, 5, vgx4], {z20.h - z23.h} // 11000001-10100101-00011110-10000101 // CHECK-INST: fadd za.h[w8, 5, vgx4], { z20.h - z23.h } // CHECK-ENCODING: [0x85,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e85 fadd za.h[w8, 5], {z20.h - z23.h} // 11000001-10100101-00011110-10000101 // CHECK-INST: fadd za.h[w8, 5, vgx4], { z20.h - z23.h } // CHECK-ENCODING: [0x85,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e85 fadd za.h[w11, 2, vgx4], {z8.h - z11.h} // 11000001-10100101-01111101-00000010 // CHECK-INST: fadd za.h[w11, 2, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x02,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d02 fadd za.h[w11, 2], {z8.h - z11.h} // 11000001-10100101-01111101-00000010 // CHECK-INST: fadd za.h[w11, 2, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x02,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d02 fadd za.h[w9, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-00111101-10000111 // CHECK-INST: fadd za.h[w9, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x87,0x3d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a53d87 fadd za.h[w9, 7], {z12.h - z15.h} // 11000001-10100101-00111101-10000111 // CHECK-INST: fadd za.h[w9, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x87,0x3d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a53d87 diff --git a/llvm/test/MC/AArch64/SME2p1/fcvt.s b/llvm/test/MC/AArch64/SME2p1/fcvt.s index b5707bad0a24..2731055dedec 100644 --- a/llvm/test/MC/AArch64/SME2p1/fcvt.s +++ b/llvm/test/MC/AArch64/SME2p1/fcvt.s @@ -1,36 +1,36 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fcvt {z0.s, z1.s}, z0.h // 11000001-10100000-11100000-00000000 // CHECK-INST: fcvt { z0.s, z1.s }, z0.h // CHECK-ENCODING: [0x00,0xe0,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e000 fcvt {z20.s, z21.s}, z10.h // 11000001-10100000-11100001-01010100 // CHECK-INST: fcvt { z20.s, z21.s }, z10.h // CHECK-ENCODING: [0x54,0xe1,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e154 fcvt {z22.s, z23.s}, z13.h // 11000001-10100000-11100001-10110110 // CHECK-INST: fcvt { z22.s, z23.s }, z13.h // CHECK-ENCODING: [0xb6,0xe1,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e1b6 fcvt {z30.s, z31.s}, z31.h // 11000001-10100000-11100011-11111110 // CHECK-INST: fcvt { z30.s, z31.s }, z31.h // CHECK-ENCODING: [0xfe,0xe3,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e3fe diff --git a/llvm/test/MC/AArch64/SME2p1/fcvtl-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/fcvtl-diagnostics.s index a723d2fc6f3a..ad3eaba7bdc2 100644 --- a/llvm/test/MC/AArch64/SME2p1/fcvtl-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2p1/fcvtl-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Invalid vector list diff --git a/llvm/test/MC/AArch64/SME2p1/fcvtl.s b/llvm/test/MC/AArch64/SME2p1/fcvtl.s index 31cf90d03796..6284915e4983 100644 --- a/llvm/test/MC/AArch64/SME2p1/fcvtl.s +++ b/llvm/test/MC/AArch64/SME2p1/fcvtl.s @@ -1,36 +1,36 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fcvtl {z0.s, z1.s}, z0.h // 11000001-10100000-11100000-00000001 // CHECK-INST: fcvtl { z0.s, z1.s }, z0.h // CHECK-ENCODING: [0x01,0xe0,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e001 fcvtl {z20.s, z21.s}, z10.h // 11000001-10100000-11100001-01010101 // CHECK-INST: fcvtl { z20.s, z21.s }, z10.h // CHECK-ENCODING: [0x55,0xe1,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e155 fcvtl {z22.s, z23.s}, z13.h // 11000001-10100000-11100001-10110111 // CHECK-INST: fcvtl { z22.s, z23.s }, z13.h // CHECK-ENCODING: [0xb7,0xe1,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e1b7 fcvtl {z30.s, z31.s}, z31.h // 11000001-10100000-11100011-11111111 // CHECK-INST: fcvtl { z30.s, z31.s }, z31.h // CHECK-ENCODING: [0xff,0xe3,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0e3ff diff --git a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s index d32f795728a2..2f0dccb57c90 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2p1/fmla-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Invalid vector list diff --git a/llvm/test/MC/AArch64/SME2p1/fmla.s b/llvm/test/MC/AArch64/SME2p1/fmla.s index 10529d81eed6..df9ac8076e56 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmla.s +++ b/llvm/test/MC/AArch64/SME2p1/fmla.s @@ -1,877 +1,877 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fmla za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h // 11000001-00100000-00011100-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h // CHECK-ENCODING: [0x00,0x1c,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201c00 fmla za.h[w8, 0], {z0.h - z1.h}, z0.h // 11000001-00100000-00011100-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h // CHECK-ENCODING: [0x00,0x1c,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201c00 fmla za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h // 11000001-00100101-01011101-01000101 // CHECK-INST: fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h // CHECK-ENCODING: [0x45,0x5d,0x25,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1255d45 fmla za.h[w10, 5], {z10.h - z11.h}, z5.h // 11000001-00100101-01011101-01000101 // CHECK-INST: fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h // CHECK-ENCODING: [0x45,0x5d,0x25,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1255d45 fmla za.h[w11, 7, vgx2], {z13.h, z14.h}, z8.h // 11000001-00101000-01111101-10100111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h // CHECK-ENCODING: [0xa7,0x7d,0x28,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1287da7 fmla za.h[w11, 7], {z13.h - z14.h}, z8.h // 11000001-00101000-01111101-10100111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h // CHECK-ENCODING: [0xa7,0x7d,0x28,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1287da7 fmla za.h[w11, 7, vgx2], {z31.h, z0.h}, z15.h // 11000001-00101111-01111111-11100111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h // CHECK-ENCODING: [0xe7,0x7f,0x2f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12f7fe7 fmla za.h[w11, 7], {z31.h - z0.h}, z15.h // 11000001-00101111-01111111-11100111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h // CHECK-ENCODING: [0xe7,0x7f,0x2f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12f7fe7 fmla za.h[w8, 5, vgx2], {z17.h, z18.h}, z0.h // 11000001-00100000-00011110-00100101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h // CHECK-ENCODING: [0x25,0x1e,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201e25 fmla za.h[w8, 5], {z17.h - z18.h}, z0.h // 11000001-00100000-00011110-00100101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h // CHECK-ENCODING: [0x25,0x1e,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201e25 fmla za.h[w8, 1, vgx2], {z1.h, z2.h}, z14.h // 11000001-00101110-00011100-00100001 // CHECK-INST: fmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h // CHECK-ENCODING: [0x21,0x1c,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1c21 fmla za.h[w8, 1], {z1.h - z2.h}, z14.h // 11000001-00101110-00011100-00100001 // CHECK-INST: fmla za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h // CHECK-ENCODING: [0x21,0x1c,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1c21 fmla za.h[w10, 0, vgx2], {z19.h, z20.h}, z4.h // 11000001-00100100-01011110-01100000 // CHECK-INST: fmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h // CHECK-ENCODING: [0x60,0x5e,0x24,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1245e60 fmla za.h[w10, 0], {z19.h - z20.h}, z4.h // 11000001-00100100-01011110-01100000 // CHECK-INST: fmla za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h // CHECK-ENCODING: [0x60,0x5e,0x24,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1245e60 fmla za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h // 11000001-00100010-00011101-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h // CHECK-ENCODING: [0x80,0x1d,0x22,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1221d80 fmla za.h[w8, 0], {z12.h - z13.h}, z2.h // 11000001-00100010-00011101-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h // CHECK-ENCODING: [0x80,0x1d,0x22,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1221d80 fmla za.h[w10, 1, vgx2], {z1.h, z2.h}, z10.h // 11000001-00101010-01011100-00100001 // CHECK-INST: fmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h // CHECK-ENCODING: [0x21,0x5c,0x2a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12a5c21 fmla za.h[w10, 1], {z1.h - z2.h}, z10.h // 11000001-00101010-01011100-00100001 // CHECK-INST: fmla za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h // CHECK-ENCODING: [0x21,0x5c,0x2a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12a5c21 fmla za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h // 11000001-00101110-00011110-11000101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h // CHECK-ENCODING: [0xc5,0x1e,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1ec5 fmla za.h[w8, 5], {z22.h - z23.h}, z14.h // 11000001-00101110-00011110-11000101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h // CHECK-ENCODING: [0xc5,0x1e,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1ec5 fmla za.h[w11, 2, vgx2], {z9.h, z10.h}, z1.h // 11000001-00100001-01111101-00100010 // CHECK-INST: fmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h // CHECK-ENCODING: [0x22,0x7d,0x21,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1217d22 fmla za.h[w11, 2], {z9.h - z10.h}, z1.h // 11000001-00100001-01111101-00100010 // CHECK-INST: fmla za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h // CHECK-ENCODING: [0x22,0x7d,0x21,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1217d22 fmla za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h // 11000001-00101011-00111101-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h // CHECK-ENCODING: [0x87,0x3d,0x2b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12b3d87 fmla za.h[w9, 7], {z12.h - z13.h}, z11.h // 11000001-00101011-00111101-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h // CHECK-ENCODING: [0x87,0x3d,0x2b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12b3d87 fmla za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-00010000-00010000-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] // CHECK-ENCODING: [0x00,0x10,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101000 fmla za.h[w8, 0], {z0.h - z1.h}, z0.h[0] // 11000001-00010000-00010000-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] // CHECK-ENCODING: [0x00,0x10,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101000 fmla za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h[2] // 11000001-00010101-01010101-01000101 // CHECK-INST: fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] // CHECK-ENCODING: [0x45,0x55,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1155545 fmla za.h[w10, 5], {z10.h - z11.h}, z5.h[2] // 11000001-00010101-01010101-01000101 // CHECK-INST: fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] // CHECK-ENCODING: [0x45,0x55,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1155545 fmla za.h[w11, 7, vgx2], {z12.h, z13.h}, z8.h[6] // 11000001-00011000-01111101-10000111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] // CHECK-ENCODING: [0x87,0x7d,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1187d87 fmla za.h[w11, 7], {z12.h - z13.h}, z8.h[6] // 11000001-00011000-01111101-10000111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] // CHECK-ENCODING: [0x87,0x7d,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1187d87 fmla za.h[w11, 7, vgx2], {z30.h, z31.h}, z15.h[7] // 11000001-00011111-01111111-11001111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] // CHECK-ENCODING: [0xcf,0x7f,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11f7fcf fmla za.h[w11, 7], {z30.h - z31.h}, z15.h[7] // 11000001-00011111-01111111-11001111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] // CHECK-ENCODING: [0xcf,0x7f,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11f7fcf fmla za.h[w8, 5, vgx2], {z16.h, z17.h}, z0.h[6] // 11000001-00010000-00011110-00000101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] // CHECK-ENCODING: [0x05,0x1e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101e05 fmla za.h[w8, 5], {z16.h - z17.h}, z0.h[6] // 11000001-00010000-00011110-00000101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] // CHECK-ENCODING: [0x05,0x1e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101e05 fmla za.h[w8, 1, vgx2], {z0.h, z1.h}, z14.h[2] // 11000001-00011110-00010100-00000001 // CHECK-INST: fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] // CHECK-ENCODING: [0x01,0x14,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1401 fmla za.h[w8, 1], {z0.h - z1.h}, z14.h[2] // 11000001-00011110-00010100-00000001 // CHECK-INST: fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] // CHECK-ENCODING: [0x01,0x14,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1401 fmla za.h[w10, 0, vgx2], {z18.h, z19.h}, z4.h[3] // 11000001-00010100-01010110-01001000 // CHECK-INST: fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] // CHECK-ENCODING: [0x48,0x56,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1145648 fmla za.h[w10, 0], {z18.h - z19.h}, z4.h[3] // 11000001-00010100-01010110-01001000 // CHECK-INST: fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] // CHECK-ENCODING: [0x48,0x56,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1145648 fmla za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h[4] // 11000001-00010010-00011001-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] // CHECK-ENCODING: [0x80,0x19,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1121980 fmla za.h[w8, 0], {z12.h - z13.h}, z2.h[4] // 11000001-00010010-00011001-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] // CHECK-ENCODING: [0x80,0x19,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1121980 fmla za.h[w10, 1, vgx2], {z0.h, z1.h}, z10.h[4] // 11000001-00011010-01011000-00000001 // CHECK-INST: fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] // CHECK-ENCODING: [0x01,0x58,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11a5801 fmla za.h[w10, 1], {z0.h - z1.h}, z10.h[4] // 11000001-00011010-01011000-00000001 // CHECK-INST: fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] // CHECK-ENCODING: [0x01,0x58,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11a5801 fmla za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h[5] // 11000001-00011110-00011010-11001101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] // CHECK-ENCODING: [0xcd,0x1a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1acd fmla za.h[w8, 5], {z22.h - z23.h}, z14.h[5] // 11000001-00011110-00011010-11001101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] // CHECK-ENCODING: [0xcd,0x1a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1acd fmla za.h[w11, 2, vgx2], {z8.h, z9.h}, z1.h[2] // 11000001-00010001-01110101-00000010 // CHECK-INST: fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] // CHECK-ENCODING: [0x02,0x75,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1117502 fmla za.h[w11, 2], {z8.h - z9.h}, z1.h[2] // 11000001-00010001-01110101-00000010 // CHECK-INST: fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] // CHECK-ENCODING: [0x02,0x75,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1117502 fmla za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h[4] // 11000001-00011011-00111001-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] // CHECK-ENCODING: [0x87,0x39,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11b3987 fmla za.h[w9, 7], {z12.h - z13.h}, z11.h[4] // 11000001-00011011-00111001-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] // CHECK-ENCODING: [0x87,0x39,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11b3987 fmla za.h[w8, 0, vgx2], {z0.h, z1.h}, {z0.h, z1.h} // 11000001-10100000-00010000-00001000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x08,0x10,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a01008 fmla za.h[w8, 0], {z0.h - z1.h}, {z0.h - z1.h} // 11000001-10100000-00010000-00001000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x08,0x10,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a01008 fmla za.h[w10, 5, vgx2], {z10.h, z11.h}, {z20.h, z21.h} // 11000001-10110100-01010001-01001101 // CHECK-INST: fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x4d,0x51,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b4514d fmla za.h[w10, 5], {z10.h - z11.h}, {z20.h - z21.h} // 11000001-10110100-01010001-01001101 // CHECK-INST: fmla za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x4d,0x51,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b4514d fmla za.h[w11, 7, vgx2], {z12.h, z13.h}, {z8.h, z9.h} // 11000001-10101000-01110001-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } // CHECK-ENCODING: [0x8f,0x71,0xa8,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a8718f fmla za.h[w11, 7], {z12.h - z13.h}, {z8.h - z9.h} // 11000001-10101000-01110001-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } // CHECK-ENCODING: [0x8f,0x71,0xa8,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a8718f fmla za.h[w11, 7, vgx2], {z30.h, z31.h}, {z30.h, z31.h} // 11000001-10111110-01110011-11001111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xcf,0x73,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be73cf fmla za.h[w11, 7], {z30.h - z31.h}, {z30.h - z31.h} // 11000001-10111110-01110011-11001111 // CHECK-INST: fmla za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xcf,0x73,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be73cf fmla za.h[w8, 5, vgx2], {z16.h, z17.h}, {z16.h, z17.h} // 11000001-10110000-00010010-00001101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } // CHECK-ENCODING: [0x0d,0x12,0xb0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b0120d fmla za.h[w8, 5], {z16.h - z17.h}, {z16.h - z17.h} // 11000001-10110000-00010010-00001101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } // CHECK-ENCODING: [0x0d,0x12,0xb0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b0120d fmla za.h[w8, 1, vgx2], {z0.h, z1.h}, {z30.h, z31.h} // 11000001-10111110-00010000-00001001 // CHECK-INST: fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } // CHECK-ENCODING: [0x09,0x10,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be1009 fmla za.h[w8, 1], {z0.h - z1.h}, {z30.h - z31.h} // 11000001-10111110-00010000-00001001 // CHECK-INST: fmla za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } // CHECK-ENCODING: [0x09,0x10,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be1009 fmla za.h[w10, 0, vgx2], {z18.h, z19.h}, {z20.h, z21.h} // 11000001-10110100-01010010-01001000 // CHECK-INST: fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x48,0x52,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b45248 fmla za.h[w10, 0], {z18.h - z19.h}, {z20.h - z21.h} // 11000001-10110100-01010010-01001000 // CHECK-INST: fmla za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x48,0x52,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b45248 fmla za.h[w8, 0, vgx2], {z12.h, z13.h}, {z2.h, z3.h} // 11000001-10100010-00010001-10001000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } // CHECK-ENCODING: [0x88,0x11,0xa2,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a21188 fmla za.h[w8, 0], {z12.h - z13.h}, {z2.h - z3.h} // 11000001-10100010-00010001-10001000 // CHECK-INST: fmla za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } // CHECK-ENCODING: [0x88,0x11,0xa2,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a21188 fmla za.h[w10, 1, vgx2], {z0.h, z1.h}, {z26.h, z27.h} // 11000001-10111010-01010000-00001001 // CHECK-INST: fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } // CHECK-ENCODING: [0x09,0x50,0xba,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1ba5009 fmla za.h[w10, 1], {z0.h - z1.h}, {z26.h - z27.h} // 11000001-10111010-01010000-00001001 // CHECK-INST: fmla za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } // CHECK-ENCODING: [0x09,0x50,0xba,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1ba5009 fmla za.h[w8, 5, vgx2], {z22.h, z23.h}, {z30.h, z31.h} // 11000001-10111110-00010010-11001101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xcd,0x12,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be12cd fmla za.h[w8, 5], {z22.h - z23.h}, {z30.h - z31.h} // 11000001-10111110-00010010-11001101 // CHECK-INST: fmla za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xcd,0x12,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be12cd fmla za.h[w11, 2, vgx2], {z8.h, z9.h}, {z0.h, z1.h} // 11000001-10100000-01110001-00001010 // CHECK-INST: fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x0a,0x71,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0710a fmla za.h[w11, 2], {z8.h - z9.h}, {z0.h - z1.h} // 11000001-10100000-01110001-00001010 // CHECK-INST: fmla za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x0a,0x71,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0710a fmla za.h[w9, 7, vgx2], {z12.h, z13.h}, {z10.h, z11.h} // 11000001-10101010-00110001-10001111 // CHECK-INST: fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } // CHECK-ENCODING: [0x8f,0x31,0xaa,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1aa318f fmla za.h[w9, 7], {z12.h - z13.h}, {z10.h - z11.h} // 11000001-10101010-00110001-10001111 // CHECK-INST: fmla za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } // CHECK-ENCODING: [0x8f,0x31,0xaa,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1aa318f fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h // 11000001-00110000-00011100-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h // CHECK-ENCODING: [0x00,0x1c,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301c00 fmla za.h[w8, 0], {z0.h - z3.h}, z0.h // 11000001-00110000-00011100-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h // CHECK-ENCODING: [0x00,0x1c,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301c00 fmla za.h[w10, 5, vgx4], {z10.h - z13.h}, z5.h // 11000001-00110101-01011101-01000101 // CHECK-INST: fmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h // CHECK-ENCODING: [0x45,0x5d,0x35,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1355d45 fmla za.h[w10, 5], {z10.h - z13.h}, z5.h // 11000001-00110101-01011101-01000101 // CHECK-INST: fmla za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h // CHECK-ENCODING: [0x45,0x5d,0x35,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1355d45 fmla za.h[w11, 7, vgx4], {z13.h - z16.h}, z8.h // 11000001-00111000-01111101-10100111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h // CHECK-ENCODING: [0xa7,0x7d,0x38,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1387da7 fmla za.h[w11, 7], {z13.h - z16.h}, z8.h // 11000001-00111000-01111101-10100111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h // CHECK-ENCODING: [0xa7,0x7d,0x38,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1387da7 fmla za.h[w11, 7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-00111111-01111111-11100111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h // CHECK-ENCODING: [0xe7,0x7f,0x3f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13f7fe7 fmla za.h[w11, 7], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-00111111-01111111-11100111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h // CHECK-ENCODING: [0xe7,0x7f,0x3f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13f7fe7 fmla za.h[w8, 5, vgx4], {z17.h - z20.h}, z0.h // 11000001-00110000-00011110-00100101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h // CHECK-ENCODING: [0x25,0x1e,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301e25 fmla za.h[w8, 5], {z17.h - z20.h}, z0.h // 11000001-00110000-00011110-00100101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h // CHECK-ENCODING: [0x25,0x1e,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301e25 fmla za.h[w8, 1, vgx4], {z1.h - z4.h}, z14.h // 11000001-00111110-00011100-00100001 // CHECK-INST: fmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h // CHECK-ENCODING: [0x21,0x1c,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1c21 fmla za.h[w8, 1], {z1.h - z4.h}, z14.h // 11000001-00111110-00011100-00100001 // CHECK-INST: fmla za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h // CHECK-ENCODING: [0x21,0x1c,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1c21 fmla za.h[w10, 0, vgx4], {z19.h - z22.h}, z4.h // 11000001-00110100-01011110-01100000 // CHECK-INST: fmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h // CHECK-ENCODING: [0x60,0x5e,0x34,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1345e60 fmla za.h[w10, 0], {z19.h - z22.h}, z4.h // 11000001-00110100-01011110-01100000 // CHECK-INST: fmla za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h // CHECK-ENCODING: [0x60,0x5e,0x34,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1345e60 fmla za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h // 11000001-00110010-00011101-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h // CHECK-ENCODING: [0x80,0x1d,0x32,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1321d80 fmla za.h[w8, 0], {z12.h - z15.h}, z2.h // 11000001-00110010-00011101-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h // CHECK-ENCODING: [0x80,0x1d,0x32,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1321d80 fmla za.h[w10, 1, vgx4], {z1.h - z4.h}, z10.h // 11000001-00111010-01011100-00100001 // CHECK-INST: fmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h // CHECK-ENCODING: [0x21,0x5c,0x3a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13a5c21 fmla za.h[w10, 1], {z1.h - z4.h}, z10.h // 11000001-00111010-01011100-00100001 // CHECK-INST: fmla za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h // CHECK-ENCODING: [0x21,0x5c,0x3a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13a5c21 fmla za.h[w8, 5, vgx4], {z22.h - z25.h}, z14.h // 11000001-00111110-00011110-11000101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h // CHECK-ENCODING: [0xc5,0x1e,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1ec5 fmla za.h[w8, 5], {z22.h - z25.h}, z14.h // 11000001-00111110-00011110-11000101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h // CHECK-ENCODING: [0xc5,0x1e,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1ec5 fmla za.h[w11, 2, vgx4], {z9.h - z12.h}, z1.h // 11000001-00110001-01111101-00100010 // CHECK-INST: fmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h // CHECK-ENCODING: [0x22,0x7d,0x31,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1317d22 fmla za.h[w11, 2], {z9.h - z12.h}, z1.h // 11000001-00110001-01111101-00100010 // CHECK-INST: fmla za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h // CHECK-ENCODING: [0x22,0x7d,0x31,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1317d22 fmla za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h // 11000001-00111011-00111101-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h // CHECK-ENCODING: [0x87,0x3d,0x3b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13b3d87 fmla za.h[w9, 7], {z12.h - z15.h}, z11.h // 11000001-00111011-00111101-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h // CHECK-ENCODING: [0x87,0x3d,0x3b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13b3d87 fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] // CHECK-ENCODING: [0x00,0x90,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109000 fmla za.h[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] // CHECK-ENCODING: [0x00,0x90,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109000 fmla za.h[w10, 5, vgx4], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00000101 // CHECK-INST: fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] // CHECK-ENCODING: [0x05,0xd5,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c115d505 fmla za.h[w10, 5], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00000101 // CHECK-INST: fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] // CHECK-ENCODING: [0x05,0xd5,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c115d505 fmla za.h[w11, 7, vgx4], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10000111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] // CHECK-ENCODING: [0x87,0xfd,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c118fd87 fmla za.h[w11, 7], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10000111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] // CHECK-ENCODING: [0x87,0xfd,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c118fd87 fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] // CHECK-ENCODING: [0x8f,0xff,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11fff8f fmla za.h[w11, 7], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] // CHECK-ENCODING: [0x8f,0xff,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11fff8f fmla za.h[w8, 5, vgx4], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00000101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] // CHECK-ENCODING: [0x05,0x9e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109e05 fmla za.h[w8, 5], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00000101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] // CHECK-ENCODING: [0x05,0x9e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109e05 fmla za.h[w8, 1, vgx4], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00000001 // CHECK-INST: fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] // CHECK-ENCODING: [0x01,0x94,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9401 fmla za.h[w8, 1], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00000001 // CHECK-INST: fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] // CHECK-ENCODING: [0x01,0x94,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9401 fmla za.h[w10, 0, vgx4], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00001000 // CHECK-INST: fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] // CHECK-ENCODING: [0x08,0xd6,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c114d608 fmla za.h[w10, 0], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00001000 // CHECK-INST: fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] // CHECK-ENCODING: [0x08,0xd6,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c114d608 fmla za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] // CHECK-ENCODING: [0x80,0x99,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1129980 fmla za.h[w8, 0], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10000000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] // CHECK-ENCODING: [0x80,0x99,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1129980 fmla za.h[w10, 1, vgx4], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00000001 // CHECK-INST: fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] // CHECK-ENCODING: [0x01,0xd8,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11ad801 fmla za.h[w10, 1], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00000001 // CHECK-INST: fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] // CHECK-ENCODING: [0x01,0xd8,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11ad801 fmla za.h[w8, 5, vgx4], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10001101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] // CHECK-ENCODING: [0x8d,0x9a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9a8d fmla za.h[w8, 5], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10001101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] // CHECK-ENCODING: [0x8d,0x9a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9a8d fmla za.h[w11, 2, vgx4], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00000010 // CHECK-INST: fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] // CHECK-ENCODING: [0x02,0xf5,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c111f502 fmla za.h[w11, 2], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00000010 // CHECK-INST: fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] // CHECK-ENCODING: [0x02,0xf5,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c111f502 fmla za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] // CHECK-ENCODING: [0x87,0xb9,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11bb987 fmla za.h[w9, 7], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10000111 // CHECK-INST: fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] // CHECK-ENCODING: [0x87,0xb9,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11bb987 fmla za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-10100001-00010000-00001000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x08,0x10,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11008 fmla za.h[w8, 0], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-10100001-00010000-00001000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x08,0x10,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11008 fmla za.h[w10, 5, vgx4], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-10110101-01010001-00001101 // CHECK-INST: fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x0d,0x51,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b5510d fmla za.h[w10, 5], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-10110101-01010001-00001101 // CHECK-INST: fmla za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x0d,0x51,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b5510d fmla za.h[w11, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-01110001-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x8f,0x71,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9718f fmla za.h[w11, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-01110001-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x8f,0x71,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9718f fmla za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-10111101-01110011-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x8f,0x73,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd738f fmla za.h[w11, 7], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-10111101-01110011-10001111 // CHECK-INST: fmla za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x8f,0x73,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd738f fmla za.h[w8, 5, vgx4], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-10110001-00010010-00001101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } // CHECK-ENCODING: [0x0d,0x12,0xb1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b1120d fmla za.h[w8, 5], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-10110001-00010010-00001101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } // CHECK-ENCODING: [0x0d,0x12,0xb1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b1120d fmla za.h[w8, 1, vgx4], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-10111101-00010000-00001001 // CHECK-INST: fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x09,0x10,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd1009 fmla za.h[w8, 1], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-10111101-00010000-00001001 // CHECK-INST: fmla za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x09,0x10,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd1009 fmla za.h[w10, 0, vgx4], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-10110101-01010010-00001000 // CHECK-INST: fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x08,0x52,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b55208 fmla za.h[w10, 0], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-10110101-01010010-00001000 // CHECK-INST: fmla za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x08,0x52,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b55208 fmla za.h[w8, 0, vgx4], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-10100001-00010001-10001000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x88,0x11,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11188 fmla za.h[w8, 0], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-10100001-00010001-10001000 // CHECK-INST: fmla za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x88,0x11,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11188 fmla za.h[w10, 1, vgx4], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-10111001-01010000-00001001 // CHECK-INST: fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } // CHECK-ENCODING: [0x09,0x50,0xb9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b95009 fmla za.h[w10, 1], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-10111001-01010000-00001001 // CHECK-INST: fmla za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } // CHECK-ENCODING: [0x09,0x50,0xb9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b95009 fmla za.h[w8, 5, vgx4], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-10111101-00010010-10001101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x8d,0x12,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd128d fmla za.h[w8, 5], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-10111101-00010010-10001101 // CHECK-INST: fmla za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x8d,0x12,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd128d fmla za.h[w11, 2, vgx4], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-10100001-01110001-00001010 // CHECK-INST: fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x0a,0x71,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a1710a fmla za.h[w11, 2], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-10100001-01110001-00001010 // CHECK-INST: fmla za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x0a,0x71,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a1710a fmla za.h[w9, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-00110001-10001111 // CHECK-INST: fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x8f,0x31,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9318f fmla za.h[w9, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-00110001-10001111 // CHECK-INST: fmla za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x8f,0x31,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9318f diff --git a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s index 2174e4202ba0..3ff09321e343 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2p1/fmls-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Invalid vector list diff --git a/llvm/test/MC/AArch64/SME2p1/fmls.s b/llvm/test/MC/AArch64/SME2p1/fmls.s index 9bbb21869e37..67b1430240e8 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmls.s +++ b/llvm/test/MC/AArch64/SME2p1/fmls.s @@ -1,878 +1,878 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fmls za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h // 11000001-00100000-00011100-00001000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h // CHECK-ENCODING: [0x08,0x1c,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201c08 fmls za.h[w8, 0], {z0.h - z1.h}, z0.h // 11000001-00100000-00011100-00001000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h // CHECK-ENCODING: [0x08,0x1c,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201c08 fmls za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h // 11000001-00100101-01011101-01001101 // CHECK-INST: fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h // CHECK-ENCODING: [0x4d,0x5d,0x25,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1255d4d fmls za.h[w10, 5], {z10.h - z11.h}, z5.h // 11000001-00100101-01011101-01001101 // CHECK-INST: fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h // CHECK-ENCODING: [0x4d,0x5d,0x25,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1255d4d fmls za.h[w11, 7, vgx2], {z13.h, z14.h}, z8.h // 11000001-00101000-01111101-10101111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h // CHECK-ENCODING: [0xaf,0x7d,0x28,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1287daf fmls za.h[w11, 7], {z13.h - z14.h}, z8.h // 11000001-00101000-01111101-10101111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z13.h, z14.h }, z8.h // CHECK-ENCODING: [0xaf,0x7d,0x28,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1287daf fmls za.h[w11, 7, vgx2], {z31.h, z0.h}, z15.h // 11000001-00101111-01111111-11101111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h // CHECK-ENCODING: [0xef,0x7f,0x2f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12f7fef fmls za.h[w11, 7], {z31.h - z0.h}, z15.h // 11000001-00101111-01111111-11101111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z31.h, z0.h }, z15.h // CHECK-ENCODING: [0xef,0x7f,0x2f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12f7fef fmls za.h[w8, 5, vgx2], {z17.h, z18.h}, z0.h // 11000001-00100000-00011110-00101101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h // CHECK-ENCODING: [0x2d,0x1e,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201e2d fmls za.h[w8, 5], {z17.h - z18.h}, z0.h // 11000001-00100000-00011110-00101101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z17.h, z18.h }, z0.h // CHECK-ENCODING: [0x2d,0x1e,0x20,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1201e2d fmls za.h[w8, 1, vgx2], {z1.h, z2.h}, z14.h // 11000001-00101110-00011100-00101001 // CHECK-INST: fmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h // CHECK-ENCODING: [0x29,0x1c,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1c29 fmls za.h[w8, 1], {z1.h - z2.h}, z14.h // 11000001-00101110-00011100-00101001 // CHECK-INST: fmls za.h[w8, 1, vgx2], { z1.h, z2.h }, z14.h // CHECK-ENCODING: [0x29,0x1c,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1c29 fmls za.h[w10, 0, vgx2], {z19.h, z20.h}, z4.h // 11000001-00100100-01011110-01101000 // CHECK-INST: fmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h // CHECK-ENCODING: [0x68,0x5e,0x24,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1245e68 fmls za.h[w10, 0], {z19.h - z20.h}, z4.h // 11000001-00100100-01011110-01101000 // CHECK-INST: fmls za.h[w10, 0, vgx2], { z19.h, z20.h }, z4.h // CHECK-ENCODING: [0x68,0x5e,0x24,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1245e68 fmls za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h // 11000001-00100010-00011101-10001000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h // CHECK-ENCODING: [0x88,0x1d,0x22,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1221d88 fmls za.h[w8, 0], {z12.h - z13.h}, z2.h // 11000001-00100010-00011101-10001000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h // CHECK-ENCODING: [0x88,0x1d,0x22,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1221d88 fmls za.h[w10, 1, vgx2], {z1.h, z2.h}, z10.h // 11000001-00101010-01011100-00101001 // CHECK-INST: fmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h // CHECK-ENCODING: [0x29,0x5c,0x2a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12a5c29 fmls za.h[w10, 1], {z1.h - z2.h}, z10.h // 11000001-00101010-01011100-00101001 // CHECK-INST: fmls za.h[w10, 1, vgx2], { z1.h, z2.h }, z10.h // CHECK-ENCODING: [0x29,0x5c,0x2a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12a5c29 fmls za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h // 11000001-00101110-00011110-11001101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h // CHECK-ENCODING: [0xcd,0x1e,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1ecd fmls za.h[w8, 5], {z22.h - z23.h}, z14.h // 11000001-00101110-00011110-11001101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h // CHECK-ENCODING: [0xcd,0x1e,0x2e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12e1ecd fmls za.h[w11, 2, vgx2], {z9.h, z10.h}, z1.h // 11000001-00100001-01111101-00101010 // CHECK-INST: fmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h // CHECK-ENCODING: [0x2a,0x7d,0x21,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1217d2a fmls za.h[w11, 2], {z9.h - z10.h}, z1.h // 11000001-00100001-01111101-00101010 // CHECK-INST: fmls za.h[w11, 2, vgx2], { z9.h, z10.h }, z1.h // CHECK-ENCODING: [0x2a,0x7d,0x21,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1217d2a fmls za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h // 11000001-00101011-00111101-10001111 // CHECK-INST: fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h // CHECK-ENCODING: [0x8f,0x3d,0x2b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12b3d8f fmls za.h[w9, 7], {z12.h - z13.h}, z11.h // 11000001-00101011-00111101-10001111 // CHECK-INST: fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h // CHECK-ENCODING: [0x8f,0x3d,0x2b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c12b3d8f fmls za.h[w8, 0, vgx2], {z0.h, z1.h}, z0.h[0] // 11000001-00010000-00010000-00010000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] // CHECK-ENCODING: [0x10,0x10,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101010 fmls za.h[w8, 0], {z0.h - z1.h}, z0.h[0] // 11000001-00010000-00010000-00010000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, z0.h[0] // CHECK-ENCODING: [0x10,0x10,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101010 fmls za.h[w10, 5, vgx2], {z10.h, z11.h}, z5.h[2] // 11000001-00010101-01010101-01010101 // CHECK-INST: fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] // CHECK-ENCODING: [0x55,0x55,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1155555 fmls za.h[w10, 5], {z10.h - z11.h}, z5.h[2] // 11000001-00010101-01010101-01010101 // CHECK-INST: fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, z5.h[2] // CHECK-ENCODING: [0x55,0x55,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1155555 fmls za.h[w11, 7, vgx2], {z12.h, z13.h}, z8.h[6] // 11000001-00011000-01111101-10010111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] // CHECK-ENCODING: [0x97,0x7d,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1187d97 fmls za.h[w11, 7], {z12.h - z13.h}, z8.h[6] // 11000001-00011000-01111101-10010111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, z8.h[6] // CHECK-ENCODING: [0x97,0x7d,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1187d97 fmls za.h[w11, 7, vgx2], {z30.h, z31.h}, z15.h[7] // 11000001-00011111-01111111-11011111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] // CHECK-ENCODING: [0xdf,0x7f,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11f7fdf fmls za.h[w11, 7], {z30.h - z31.h}, z15.h[7] // 11000001-00011111-01111111-11011111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, z15.h[7] // CHECK-ENCODING: [0xdf,0x7f,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11f7fdf fmls za.h[w8, 5, vgx2], {z16.h, z17.h}, z0.h[6] // 11000001-00010000-00011110-00010101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] // CHECK-ENCODING: [0x15,0x1e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101e15 fmls za.h[w8, 5], {z16.h - z17.h}, z0.h[6] // 11000001-00010000-00011110-00010101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, z0.h[6] // CHECK-ENCODING: [0x15,0x1e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1101e15 fmls za.h[w8, 1, vgx2], {z0.h, z1.h}, z14.h[2] // 11000001-00011110-00010100-00010001 // CHECK-INST: fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] // CHECK-ENCODING: [0x11,0x14,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1411 fmls za.h[w8, 1], {z0.h - z1.h}, z14.h[2] // 11000001-00011110-00010100-00010001 // CHECK-INST: fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, z14.h[2] // CHECK-ENCODING: [0x11,0x14,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1411 fmls za.h[w10, 0, vgx2], {z18.h, z19.h}, z4.h[3] // 11000001-00010100-01010110-01011000 // CHECK-INST: fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] // CHECK-ENCODING: [0x58,0x56,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1145658 fmls za.h[w10, 0], {z18.h - z19.h}, z4.h[3] // 11000001-00010100-01010110-01011000 // CHECK-INST: fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, z4.h[3] // CHECK-ENCODING: [0x58,0x56,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1145658 fmls za.h[w8, 0, vgx2], {z12.h, z13.h}, z2.h[4] // 11000001-00010010-00011001-10010000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] // CHECK-ENCODING: [0x90,0x19,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1121990 fmls za.h[w8, 0], {z12.h - z13.h}, z2.h[4] // 11000001-00010010-00011001-10010000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, z2.h[4] // CHECK-ENCODING: [0x90,0x19,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1121990 fmls za.h[w10, 1, vgx2], {z0.h, z1.h}, z10.h[4] // 11000001-00011010-01011000-00010001 // CHECK-INST: fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] // CHECK-ENCODING: [0x11,0x58,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11a5811 fmls za.h[w10, 1], {z0.h - z1.h}, z10.h[4] // 11000001-00011010-01011000-00010001 // CHECK-INST: fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, z10.h[4] // CHECK-ENCODING: [0x11,0x58,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11a5811 fmls za.h[w8, 5, vgx2], {z22.h, z23.h}, z14.h[5] // 11000001-00011110-00011010-11011101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] // CHECK-ENCODING: [0xdd,0x1a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1add fmls za.h[w8, 5], {z22.h - z23.h}, z14.h[5] // 11000001-00011110-00011010-11011101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, z14.h[5] // CHECK-ENCODING: [0xdd,0x1a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e1add fmls za.h[w11, 2, vgx2], {z8.h, z9.h}, z1.h[2] // 11000001-00010001-01110101-00010010 // CHECK-INST: fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] // CHECK-ENCODING: [0x12,0x75,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1117512 fmls za.h[w11, 2], {z8.h - z9.h}, z1.h[2] // 11000001-00010001-01110101-00010010 // CHECK-INST: fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, z1.h[2] // CHECK-ENCODING: [0x12,0x75,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1117512 fmls za.h[w9, 7, vgx2], {z12.h, z13.h}, z11.h[4] // 11000001-00011011-00111001-10010111 // CHECK-INST: fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] // CHECK-ENCODING: [0x97,0x39,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11b3997 fmls za.h[w9, 7], {z12.h - z13.h}, z11.h[4] // 11000001-00011011-00111001-10010111 // CHECK-INST: fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, z11.h[4] // CHECK-ENCODING: [0x97,0x39,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11b3997 fmls za.h[w8, 0, vgx2], {z0.h, z1.h}, {z0.h, z1.h} // 11000001-10100000-00010000-00011000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x18,0x10,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a01018 fmls za.h[w8, 0], {z0.h - z1.h}, {z0.h - z1.h} // 11000001-10100000-00010000-00011000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z0.h, z1.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x18,0x10,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a01018 fmls za.h[w10, 5, vgx2], {z10.h, z11.h}, {z20.h, z21.h} // 11000001-10110100-01010001-01011101 // CHECK-INST: fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x5d,0x51,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b4515d fmls za.h[w10, 5], {z10.h - z11.h}, {z20.h - z21.h} // 11000001-10110100-01010001-01011101 // CHECK-INST: fmls za.h[w10, 5, vgx2], { z10.h, z11.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x5d,0x51,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b4515d fmls za.h[w11, 7, vgx2], {z12.h, z13.h}, {z8.h, z9.h} // 11000001-10101000-01110001-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } // CHECK-ENCODING: [0x9f,0x71,0xa8,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a8719f fmls za.h[w11, 7], {z12.h - z13.h}, {z8.h - z9.h} // 11000001-10101000-01110001-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z12.h, z13.h }, { z8.h, z9.h } // CHECK-ENCODING: [0x9f,0x71,0xa8,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a8719f fmls za.h[w11, 7, vgx2], {z30.h, z31.h}, {z30.h, z31.h} // 11000001-10111110-01110011-11011111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xdf,0x73,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be73df fmls za.h[w11, 7], {z30.h - z31.h}, {z30.h - z31.h} // 11000001-10111110-01110011-11011111 // CHECK-INST: fmls za.h[w11, 7, vgx2], { z30.h, z31.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xdf,0x73,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be73df fmls za.h[w8, 5, vgx2], {z16.h, z17.h}, {z16.h, z17.h} // 11000001-10110000-00010010-00011101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } // CHECK-ENCODING: [0x1d,0x12,0xb0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b0121d fmls za.h[w8, 5], {z16.h - z17.h}, {z16.h - z17.h} // 11000001-10110000-00010010-00011101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z16.h, z17.h }, { z16.h, z17.h } // CHECK-ENCODING: [0x1d,0x12,0xb0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b0121d fmls za.h[w8, 1, vgx2], {z0.h, z1.h}, {z30.h, z31.h} // 11000001-10111110-00010000-00011001 // CHECK-INST: fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } // CHECK-ENCODING: [0x19,0x10,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be1019 fmls za.h[w8, 1], {z0.h - z1.h}, {z30.h - z31.h} // 11000001-10111110-00010000-00011001 // CHECK-INST: fmls za.h[w8, 1, vgx2], { z0.h, z1.h }, { z30.h, z31.h } // CHECK-ENCODING: [0x19,0x10,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be1019 fmls za.h[w10, 0, vgx2], {z18.h, z19.h}, {z20.h, z21.h} // 11000001-10110100-01010010-01011000 // CHECK-INST: fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x58,0x52,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b45258 fmls za.h[w10, 0], {z18.h - z19.h}, {z20.h - z21.h} // 11000001-10110100-01010010-01011000 // CHECK-INST: fmls za.h[w10, 0, vgx2], { z18.h, z19.h }, { z20.h, z21.h } // CHECK-ENCODING: [0x58,0x52,0xb4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b45258 fmls za.h[w8, 0, vgx2], {z12.h, z13.h}, {z2.h, z3.h} // 11000001-10100010-00010001-10011000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } // CHECK-ENCODING: [0x98,0x11,0xa2,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a21198 fmls za.h[w8, 0], {z12.h - z13.h}, {z2.h - z3.h} // 11000001-10100010-00010001-10011000 // CHECK-INST: fmls za.h[w8, 0, vgx2], { z12.h, z13.h }, { z2.h, z3.h } // CHECK-ENCODING: [0x98,0x11,0xa2,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a21198 fmls za.h[w10, 1, vgx2], {z0.h, z1.h}, {z26.h, z27.h} // 11000001-10111010-01010000-00011001 // CHECK-INST: fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } // CHECK-ENCODING: [0x19,0x50,0xba,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1ba5019 fmls za.h[w10, 1], {z0.h - z1.h}, {z26.h - z27.h} // 11000001-10111010-01010000-00011001 // CHECK-INST: fmls za.h[w10, 1, vgx2], { z0.h, z1.h }, { z26.h, z27.h } // CHECK-ENCODING: [0x19,0x50,0xba,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1ba5019 fmls za.h[w8, 5, vgx2], {z22.h, z23.h}, {z30.h, z31.h} // 11000001-10111110-00010010-11011101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xdd,0x12,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be12dd fmls za.h[w8, 5], {z22.h - z23.h}, {z30.h - z31.h} // 11000001-10111110-00010010-11011101 // CHECK-INST: fmls za.h[w8, 5, vgx2], { z22.h, z23.h }, { z30.h, z31.h } // CHECK-ENCODING: [0xdd,0x12,0xbe,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1be12dd fmls za.h[w11, 2, vgx2], {z8.h, z9.h}, {z0.h, z1.h} // 11000001-10100000-01110001-00011010 // CHECK-INST: fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x1a,0x71,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0711a fmls za.h[w11, 2], {z8.h - z9.h}, {z0.h - z1.h} // 11000001-10100000-01110001-00011010 // CHECK-INST: fmls za.h[w11, 2, vgx2], { z8.h, z9.h }, { z0.h, z1.h } // CHECK-ENCODING: [0x1a,0x71,0xa0,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a0711a fmls za.h[w9, 7, vgx2], {z12.h, z13.h}, {z10.h, z11.h} // 11000001-10101010-00110001-10011111 // CHECK-INST: fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } // CHECK-ENCODING: [0x9f,0x31,0xaa,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1aa319f fmls za.h[w9, 7], {z12.h - z13.h}, {z10.h - z11.h} // 11000001-10101010-00110001-10011111 // CHECK-INST: fmls za.h[w9, 7, vgx2], { z12.h, z13.h }, { z10.h, z11.h } // CHECK-ENCODING: [0x9f,0x31,0xaa,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1aa319f fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h // 11000001-00110000-00011100-00001000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h // CHECK-ENCODING: [0x08,0x1c,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301c08 fmls za.h[w8, 0], {z0.h - z3.h}, z0.h // 11000001-00110000-00011100-00001000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h // CHECK-ENCODING: [0x08,0x1c,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301c08 fmls za.h[w10, 5, vgx4], {z10.h - z13.h}, z5.h // 11000001-00110101-01011101-01001101 // CHECK-INST: fmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h // CHECK-ENCODING: [0x4d,0x5d,0x35,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1355d4d fmls za.h[w10, 5], {z10.h - z13.h}, z5.h // 11000001-00110101-01011101-01001101 // CHECK-INST: fmls za.h[w10, 5, vgx4], { z10.h - z13.h }, z5.h // CHECK-ENCODING: [0x4d,0x5d,0x35,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1355d4d fmls za.h[w11, 7, vgx4], {z13.h - z16.h}, z8.h // 11000001-00111000-01111101-10101111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h // CHECK-ENCODING: [0xaf,0x7d,0x38,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1387daf fmls za.h[w11, 7], {z13.h - z16.h}, z8.h // 11000001-00111000-01111101-10101111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z13.h - z16.h }, z8.h // CHECK-ENCODING: [0xaf,0x7d,0x38,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1387daf fmls za.h[w11, 7, vgx4], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-00111111-01111111-11101111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h // CHECK-ENCODING: [0xef,0x7f,0x3f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13f7fef fmls za.h[w11, 7], {z31.h, z0.h, z1.h, z2.h}, z15.h // 11000001-00111111-01111111-11101111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z31.h, z0.h, z1.h, z2.h }, z15.h // CHECK-ENCODING: [0xef,0x7f,0x3f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13f7fef fmls za.h[w8, 5, vgx4], {z17.h - z20.h}, z0.h // 11000001-00110000-00011110-00101101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h // CHECK-ENCODING: [0x2d,0x1e,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301e2d fmls za.h[w8, 5], {z17.h - z20.h}, z0.h // 11000001-00110000-00011110-00101101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z17.h - z20.h }, z0.h // CHECK-ENCODING: [0x2d,0x1e,0x30,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1301e2d fmls za.h[w8, 1, vgx4], {z1.h - z4.h}, z14.h // 11000001-00111110-00011100-00101001 // CHECK-INST: fmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h // CHECK-ENCODING: [0x29,0x1c,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1c29 fmls za.h[w8, 1], {z1.h - z4.h}, z14.h // 11000001-00111110-00011100-00101001 // CHECK-INST: fmls za.h[w8, 1, vgx4], { z1.h - z4.h }, z14.h // CHECK-ENCODING: [0x29,0x1c,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1c29 fmls za.h[w10, 0, vgx4], {z19.h - z22.h}, z4.h // 11000001-00110100-01011110-01101000 // CHECK-INST: fmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h // CHECK-ENCODING: [0x68,0x5e,0x34,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1345e68 fmls za.h[w10, 0], {z19.h - z22.h}, z4.h // 11000001-00110100-01011110-01101000 // CHECK-INST: fmls za.h[w10, 0, vgx4], { z19.h - z22.h }, z4.h // CHECK-ENCODING: [0x68,0x5e,0x34,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1345e68 fmls za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h // 11000001-00110010-00011101-10001000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h // CHECK-ENCODING: [0x88,0x1d,0x32,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1321d88 fmls za.h[w8, 0], {z12.h - z15.h}, z2.h // 11000001-00110010-00011101-10001000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h // CHECK-ENCODING: [0x88,0x1d,0x32,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1321d88 fmls za.h[w10, 1, vgx4], {z1.h - z4.h}, z10.h // 11000001-00111010-01011100-00101001 // CHECK-INST: fmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h // CHECK-ENCODING: [0x29,0x5c,0x3a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13a5c29 fmls za.h[w10, 1], {z1.h - z4.h}, z10.h // 11000001-00111010-01011100-00101001 // CHECK-INST: fmls za.h[w10, 1, vgx4], { z1.h - z4.h }, z10.h // CHECK-ENCODING: [0x29,0x5c,0x3a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13a5c29 fmls za.h[w8, 5, vgx4], {z22.h - z25.h}, z14.h // 11000001-00111110-00011110-11001101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h // CHECK-ENCODING: [0xcd,0x1e,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1ecd fmls za.h[w8, 5], {z22.h - z25.h}, z14.h // 11000001-00111110-00011110-11001101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z22.h - z25.h }, z14.h // CHECK-ENCODING: [0xcd,0x1e,0x3e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13e1ecd fmls za.h[w11, 2, vgx4], {z9.h - z12.h}, z1.h // 11000001-00110001-01111101-00101010 // CHECK-INST: fmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h // CHECK-ENCODING: [0x2a,0x7d,0x31,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1317d2a fmls za.h[w11, 2], {z9.h - z12.h}, z1.h // 11000001-00110001-01111101-00101010 // CHECK-INST: fmls za.h[w11, 2, vgx4], { z9.h - z12.h }, z1.h // CHECK-ENCODING: [0x2a,0x7d,0x31,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1317d2a fmls za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h // 11000001-00111011-00111101-10001111 // CHECK-INST: fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h // CHECK-ENCODING: [0x8f,0x3d,0x3b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13b3d8f fmls za.h[w9, 7], {z12.h - z15.h}, z11.h // 11000001-00111011-00111101-10001111 // CHECK-INST: fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h // CHECK-ENCODING: [0x8f,0x3d,0x3b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c13b3d8f fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00010000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] // CHECK-ENCODING: [0x10,0x90,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109010 fmls za.h[w8, 0], {z0.h - z3.h}, z0.h[0] // 11000001-00010000-10010000-00010000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, z0.h[0] // CHECK-ENCODING: [0x10,0x90,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109010 fmls za.h[w10, 5, vgx4], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00010101 // CHECK-INST: fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] // CHECK-ENCODING: [0x15,0xd5,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c115d515 fmls za.h[w10, 5], {z8.h - z11.h}, z5.h[2] // 11000001-00010101-11010101-00010101 // CHECK-INST: fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, z5.h[2] // CHECK-ENCODING: [0x15,0xd5,0x15,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c115d515 fmls za.h[w11, 7, vgx4], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10010111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] // CHECK-ENCODING: [0x97,0xfd,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c118fd97 fmls za.h[w11, 7], {z12.h - z15.h}, z8.h[6] // 11000001-00011000-11111101-10010111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, z8.h[6] // CHECK-ENCODING: [0x97,0xfd,0x18,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c118fd97 fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] // CHECK-ENCODING: [0x9f,0xff,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11fff9f fmls za.h[w11, 7], {z28.h - z31.h}, z15.h[7] // 11000001-00011111-11111111-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, z15.h[7] // CHECK-ENCODING: [0x9f,0xff,0x1f,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11fff9f fmls za.h[w8, 5, vgx4], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00010101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] // CHECK-ENCODING: [0x15,0x9e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109e15 fmls za.h[w8, 5], {z16.h - z19.h}, z0.h[6] // 11000001-00010000-10011110-00010101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, z0.h[6] // CHECK-ENCODING: [0x15,0x9e,0x10,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1109e15 fmls za.h[w8, 1, vgx4], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00010001 // CHECK-INST: fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] // CHECK-ENCODING: [0x11,0x94,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9411 fmls za.h[w8, 1], {z0.h - z3.h}, z14.h[2] // 11000001-00011110-10010100-00010001 // CHECK-INST: fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, z14.h[2] // CHECK-ENCODING: [0x11,0x94,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9411 fmls za.h[w10, 0, vgx4], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00011000 // CHECK-INST: fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] // CHECK-ENCODING: [0x18,0xd6,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c114d618 fmls za.h[w10, 0], {z16.h - z19.h}, z4.h[3] // 11000001-00010100-11010110-00011000 // CHECK-INST: fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, z4.h[3] // CHECK-ENCODING: [0x18,0xd6,0x14,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c114d618 fmls za.h[w8, 0, vgx4], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10010000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] // CHECK-ENCODING: [0x90,0x99,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1129990 fmls za.h[w8, 0], {z12.h - z15.h}, z2.h[4] // 11000001-00010010-10011001-10010000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, z2.h[4] // CHECK-ENCODING: [0x90,0x99,0x12,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1129990 fmls za.h[w10, 1, vgx4], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00010001 // CHECK-INST: fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] // CHECK-ENCODING: [0x11,0xd8,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11ad811 fmls za.h[w10, 1], {z0.h - z3.h}, z10.h[4] // 11000001-00011010-11011000-00010001 // CHECK-INST: fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, z10.h[4] // CHECK-ENCODING: [0x11,0xd8,0x1a,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11ad811 fmls za.h[w8, 5, vgx4], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10011101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] // CHECK-ENCODING: [0x9d,0x9a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9a9d fmls za.h[w8, 5], {z20.h - z23.h}, z14.h[5] // 11000001-00011110-10011010-10011101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, z14.h[5] // CHECK-ENCODING: [0x9d,0x9a,0x1e,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11e9a9d fmls za.h[w11, 2, vgx4], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00010010 // CHECK-INST: fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] // CHECK-ENCODING: [0x12,0xf5,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c111f512 fmls za.h[w11, 2], {z8.h - z11.h}, z1.h[2] // 11000001-00010001-11110101-00010010 // CHECK-INST: fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, z1.h[2] // CHECK-ENCODING: [0x12,0xf5,0x11,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c111f512 fmls za.h[w9, 7, vgx4], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10010111 // CHECK-INST: fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] // CHECK-ENCODING: [0x97,0xb9,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11bb997 fmls za.h[w9, 7], {z12.h - z15.h}, z11.h[4] // 11000001-00011011-10111001-10010111 // CHECK-INST: fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, z11.h[4] // CHECK-ENCODING: [0x97,0xb9,0x1b,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c11bb997 fmls za.h[w8, 0, vgx4], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-10100001-00010000-00011000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x18,0x10,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11018 fmls za.h[w8, 0], {z0.h - z3.h}, {z0.h - z3.h} // 11000001-10100001-00010000-00011000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z0.h - z3.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x18,0x10,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11018 fmls za.h[w10, 5, vgx4], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-10110101-01010001-00011101 // CHECK-INST: fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x1d,0x51,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b5511d fmls za.h[w10, 5], {z8.h - z11.h}, {z20.h - z23.h} // 11000001-10110101-01010001-00011101 // CHECK-INST: fmls za.h[w10, 5, vgx4], { z8.h - z11.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x1d,0x51,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b5511d fmls za.h[w11, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-01110001-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x9f,0x71,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9719f fmls za.h[w11, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-01110001-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x9f,0x71,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9719f fmls za.h[w11, 7, vgx4], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-10111101-01110011-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x9f,0x73,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd739f fmls za.h[w11, 7], {z28.h - z31.h}, {z28.h - z31.h} // 11000001-10111101-01110011-10011111 // CHECK-INST: fmls za.h[w11, 7, vgx4], { z28.h - z31.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x9f,0x73,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd739f fmls za.h[w8, 5, vgx4], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-10110001-00010010-00011101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } // CHECK-ENCODING: [0x1d,0x12,0xb1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b1121d fmls za.h[w8, 5], {z16.h - z19.h}, {z16.h - z19.h} // 11000001-10110001-00010010-00011101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z16.h - z19.h }, { z16.h - z19.h } // CHECK-ENCODING: [0x1d,0x12,0xb1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b1121d fmls za.h[w8, 1, vgx4], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-10111101-00010000-00011001 // CHECK-INST: fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x19,0x10,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd1019 fmls za.h[w8, 1], {z0.h - z3.h}, {z28.h - z31.h} // 11000001-10111101-00010000-00011001 // CHECK-INST: fmls za.h[w8, 1, vgx4], { z0.h - z3.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x19,0x10,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd1019 fmls za.h[w10, 0, vgx4], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-10110101-01010010-00011000 // CHECK-INST: fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x18,0x52,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b55218 fmls za.h[w10, 0], {z16.h - z19.h}, {z20.h - z23.h} // 11000001-10110101-01010010-00011000 // CHECK-INST: fmls za.h[w10, 0, vgx4], { z16.h - z19.h }, { z20.h - z23.h } // CHECK-ENCODING: [0x18,0x52,0xb5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b55218 fmls za.h[w8, 0, vgx4], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-10100001-00010001-10011000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x98,0x11,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11198 fmls za.h[w8, 0], {z12.h - z15.h}, {z0.h - z3.h} // 11000001-10100001-00010001-10011000 // CHECK-INST: fmls za.h[w8, 0, vgx4], { z12.h - z15.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x98,0x11,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a11198 fmls za.h[w10, 1, vgx4], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-10111001-01010000-00011001 // CHECK-INST: fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } // CHECK-ENCODING: [0x19,0x50,0xb9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b95019 fmls za.h[w10, 1], {z0.h - z3.h}, {z24.h - z27.h} // 11000001-10111001-01010000-00011001 // CHECK-INST: fmls za.h[w10, 1, vgx4], { z0.h - z3.h }, { z24.h - z27.h } // CHECK-ENCODING: [0x19,0x50,0xb9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1b95019 fmls za.h[w8, 5, vgx4], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-10111101-00010010-10011101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x9d,0x12,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd129d fmls za.h[w8, 5], {z20.h - z23.h}, {z28.h - z31.h} // 11000001-10111101-00010010-10011101 // CHECK-INST: fmls za.h[w8, 5, vgx4], { z20.h - z23.h }, { z28.h - z31.h } // CHECK-ENCODING: [0x9d,0x12,0xbd,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1bd129d fmls za.h[w11, 2, vgx4], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-10100001-01110001-00011010 // CHECK-INST: fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x1a,0x71,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a1711a fmls za.h[w11, 2], {z8.h - z11.h}, {z0.h - z3.h} // 11000001-10100001-01110001-00011010 // CHECK-INST: fmls za.h[w11, 2, vgx4], { z8.h - z11.h }, { z0.h - z3.h } // CHECK-ENCODING: [0x1a,0x71,0xa1,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a1711a fmls za.h[w9, 7, vgx4], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-00110001-10011111 // CHECK-INST: fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x9f,0x31,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9319f fmls za.h[w9, 7], {z12.h - z15.h}, {z8.h - z11.h} // 11000001-10101001-00110001-10011111 // CHECK-INST: fmls za.h[w9, 7, vgx4], { z12.h - z15.h }, { z8.h - z11.h } // CHECK-ENCODING: [0x9f,0x31,0xa9,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: c1a9319f diff --git a/llvm/test/MC/AArch64/SME2p1/fmopa-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/fmopa-diagnostics.s index def19a316c2a..1c561959c25e 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmopa-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2p1/fmopa-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Invalid predicate register diff --git a/llvm/test/MC/AArch64/SME2p1/fmopa.s b/llvm/test/MC/AArch64/SME2p1/fmopa.s index e53d21244fde..0a586d3acc42 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmopa.s +++ b/llvm/test/MC/AArch64/SME2p1/fmopa.s @@ -1,85 +1,85 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fmopa za0.h, p0/m, p0/m, z0.h, z0.h // 10000001-10000000-00000000-00001000 // CHECK-INST: fmopa za0.h, p0/m, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x08,0x00,0x80,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81800008 fmopa za1.h, p5/m, p2/m, z10.h, z21.h // 10000001-10010101-01010101-01001001 // CHECK-INST: fmopa za1.h, p5/m, p2/m, z10.h, z21.h // CHECK-ENCODING: [0x49,0x55,0x95,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81955549 fmopa za1.h, p3/m, p7/m, z13.h, z8.h // 10000001-10001000-11101101-10101001 // CHECK-INST: fmopa za1.h, p3/m, p7/m, z13.h, z8.h // CHECK-ENCODING: [0xa9,0xed,0x88,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 8188eda9 fmopa za1.h, p7/m, p7/m, z31.h, z31.h // 10000001-10011111-11111111-11101001 // CHECK-INST: fmopa za1.h, p7/m, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xe9,0xff,0x9f,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819fffe9 fmopa za1.h, p3/m, p0/m, z17.h, z16.h // 10000001-10010000-00001110-00101001 // CHECK-INST: fmopa za1.h, p3/m, p0/m, z17.h, z16.h // CHECK-ENCODING: [0x29,0x0e,0x90,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81900e29 fmopa za1.h, p1/m, p4/m, z1.h, z30.h // 10000001-10011110-10000100-00101001 // CHECK-INST: fmopa za1.h, p1/m, p4/m, z1.h, z30.h // CHECK-ENCODING: [0x29,0x84,0x9e,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819e8429 fmopa za0.h, p5/m, p2/m, z19.h, z20.h // 10000001-10010100-01010110-01101000 // CHECK-INST: fmopa za0.h, p5/m, p2/m, z19.h, z20.h // CHECK-ENCODING: [0x68,0x56,0x94,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81945668 fmopa za0.h, p6/m, p0/m, z12.h, z2.h // 10000001-10000010-00011001-10001000 // CHECK-INST: fmopa za0.h, p6/m, p0/m, z12.h, z2.h // CHECK-ENCODING: [0x88,0x19,0x82,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81821988 fmopa za1.h, p2/m, p6/m, z1.h, z26.h // 10000001-10011010-11001000-00101001 // CHECK-INST: fmopa za1.h, p2/m, p6/m, z1.h, z26.h // CHECK-ENCODING: [0x29,0xc8,0x9a,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819ac829 fmopa za1.h, p2/m, p0/m, z22.h, z30.h // 10000001-10011110-00001010-11001001 // CHECK-INST: fmopa za1.h, p2/m, p0/m, z22.h, z30.h // CHECK-ENCODING: [0xc9,0x0a,0x9e,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819e0ac9 fmopa za0.h, p5/m, p7/m, z9.h, z1.h // 10000001-10000001-11110101-00101000 // CHECK-INST: fmopa za0.h, p5/m, p7/m, z9.h, z1.h // CHECK-ENCODING: [0x28,0xf5,0x81,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 8181f528 fmopa za1.h, p2/m, p5/m, z12.h, z11.h // 10000001-10001011-10101001-10001001 // CHECK-INST: fmopa za1.h, p2/m, p5/m, z12.h, z11.h // CHECK-ENCODING: [0x89,0xa9,0x8b,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 818ba989 diff --git a/llvm/test/MC/AArch64/SME2p1/fmops-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/fmops-diagnostics.s index 75eea8113262..0ec227ae0e68 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmops-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2p1/fmops-diagnostics.s @@ -1,4 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Invalid predicate register diff --git a/llvm/test/MC/AArch64/SME2p1/fmops.s b/llvm/test/MC/AArch64/SME2p1/fmops.s index 325d4c125b60..597665d59150 100644 --- a/llvm/test/MC/AArch64/SME2p1/fmops.s +++ b/llvm/test/MC/AArch64/SME2p1/fmops.s @@ -1,84 +1,84 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fmops za0.h, p0/m, p0/m, z0.h, z0.h // 10000001-10000000-00000000-00011000 // CHECK-INST: fmops za0.h, p0/m, p0/m, z0.h, z0.h // CHECK-ENCODING: [0x18,0x00,0x80,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81800018 fmops za1.h, p5/m, p2/m, z10.h, z21.h // 10000001-10010101-01010101-01011001 // CHECK-INST: fmops za1.h, p5/m, p2/m, z10.h, z21.h // CHECK-ENCODING: [0x59,0x55,0x95,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81955559 fmops za1.h, p3/m, p7/m, z13.h, z8.h // 10000001-10001000-11101101-10111001 // CHECK-INST: fmops za1.h, p3/m, p7/m, z13.h, z8.h // CHECK-ENCODING: [0xb9,0xed,0x88,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 8188edb9 fmops za1.h, p7/m, p7/m, z31.h, z31.h // 10000001-10011111-11111111-11111001 // CHECK-INST: fmops za1.h, p7/m, p7/m, z31.h, z31.h // CHECK-ENCODING: [0xf9,0xff,0x9f,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819ffff9 fmops za1.h, p3/m, p0/m, z17.h, z16.h // 10000001-10010000-00001110-00111001 // CHECK-INST: fmops za1.h, p3/m, p0/m, z17.h, z16.h // CHECK-ENCODING: [0x39,0x0e,0x90,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81900e39 fmops za1.h, p1/m, p4/m, z1.h, z30.h // 10000001-10011110-10000100-00111001 // CHECK-INST: fmops za1.h, p1/m, p4/m, z1.h, z30.h // CHECK-ENCODING: [0x39,0x84,0x9e,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819e8439 fmops za0.h, p5/m, p2/m, z19.h, z20.h // 10000001-10010100-01010110-01111000 // CHECK-INST: fmops za0.h, p5/m, p2/m, z19.h, z20.h // CHECK-ENCODING: [0x78,0x56,0x94,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81945678 fmops za0.h, p6/m, p0/m, z12.h, z2.h // 10000001-10000010-00011001-10011000 // CHECK-INST: fmops za0.h, p6/m, p0/m, z12.h, z2.h // CHECK-ENCODING: [0x98,0x19,0x82,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 81821998 fmops za1.h, p2/m, p6/m, z1.h, z26.h // 10000001-10011010-11001000-00111001 // CHECK-INST: fmops za1.h, p2/m, p6/m, z1.h, z26.h // CHECK-ENCODING: [0x39,0xc8,0x9a,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819ac839 fmops za1.h, p2/m, p0/m, z22.h, z30.h // 10000001-10011110-00001010-11011001 // CHECK-INST: fmops za1.h, p2/m, p0/m, z22.h, z30.h // CHECK-ENCODING: [0xd9,0x0a,0x9e,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 819e0ad9 fmops za0.h, p5/m, p7/m, z9.h, z1.h // 10000001-10000001-11110101-00111000 // CHECK-INST: fmops za0.h, p5/m, p7/m, z9.h, z1.h // CHECK-ENCODING: [0x38,0xf5,0x81,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 8181f538 fmops za1.h, p2/m, p5/m, z12.h, z11.h // 10000001-10001011-10101001-10011001 // CHECK-INST: fmops za1.h, p2/m, p5/m, z12.h, z11.h // CHECK-ENCODING: [0x99,0xa9,0x8b,0x81] -// CHECK-ERROR: instruction requires: sme2p1 sme-f16f16 +// CHECK-ERROR: instruction requires: sme-f16f16 // CHECK-UNKNOWN: 818ba999 diff --git a/llvm/test/MC/AArch64/SME2p1/fsub-diagnostics.s b/llvm/test/MC/AArch64/SME2p1/fsub-diagnostics.s index 716427a2f725..60cef4260be9 100644 --- a/llvm/test/MC/AArch64/SME2p1/fsub-diagnostics.s +++ b/llvm/test/MC/AArch64/SME2p1/fsub-diagnostics.s @@ -1,5 +1,4 @@ -// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 2>&1 < %s | FileCheck %s - +// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 2>&1 < %s | FileCheck %s // --------------------------------------------------------------------------// // Out of range index offset diff --git a/llvm/test/MC/AArch64/SME2p1/fsub.s b/llvm/test/MC/AArch64/SME2p1/fsub.s index b3735d554765..66410008eb11 100644 --- a/llvm/test/MC/AArch64/SME2p1/fsub.s +++ b/llvm/test/MC/AArch64/SME2p1/fsub.s @@ -1,296 +1,298 @@ -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ +// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f8f16 < %s \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \ // RUN: | FileCheck %s --check-prefix=CHECK-ERROR -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ -// RUN: | llvm-objdump -d --mattr=+sme2p1,+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST -// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ +// RUN: | llvm-objdump -d --mattr=+sme-f16f16 - | FileCheck %s --check-prefix=CHECK-INST +// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme-f16f16 < %s \ // RUN: | llvm-objdump -d --mattr=-sme2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN -// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1,+sme-f16f16 < %s \ +// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme-f16f16 < %s \ // RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \ -// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1,+sme-f16f16 -disassemble -show-encoding \ +// RUN: | llvm-mc -triple=aarch64 -mattr=+sme-f16f16 -disassemble -show-encoding \ // RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST fsub za.h[w8, 0], {z0.h - z1.h} // 11000001-10100100-00011100-00001000 // CHECK-INST: fsub za.h[w8, 0, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x08,0x1c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41c08 fsub za.h[w10, 5, vgx2], {z10.h, z11.h} // 11000001-10100100-01011101-01001101 // CHECK-INST: fsub za.h[w10, 5, vgx2], { z10.h, z11.h } // CHECK-ENCODING: [0x4d,0x5d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45d4d fsub za.h[w10, 5], {z10.h - z11.h} // 11000001-10100100-01011101-01001101 // CHECK-INST: fsub za.h[w10, 5, vgx2], { z10.h, z11.h } // CHECK-ENCODING: [0x4d,0x5d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45d4d fsub za.h[w11, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-01111101-10001111 // CHECK-INST: fsub za.h[w11, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x8f,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d8f fsub za.h[w11, 7], {z12.h - z13.h} // 11000001-10100100-01111101-10001111 // CHECK-INST: fsub za.h[w11, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x8f,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d8f fsub za.h[w11, 7, vgx2], {z30.h, z31.h} // 11000001-10100100-01111111-11001111 // CHECK-INST: fsub za.h[w11, 7, vgx2], { z30.h, z31.h } // CHECK-ENCODING: [0xcf,0x7f,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47fcf fsub za.h[w11, 7], {z30.h - z31.h} // 11000001-10100100-01111111-11001111 // CHECK-INST: fsub za.h[w11, 7, vgx2], { z30.h, z31.h } // CHECK-ENCODING: [0xcf,0x7f,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47fcf fsub za.h[w8, 5, vgx2], {z16.h, z17.h} // 11000001-10100100-00011110-00001101 // CHECK-INST: fsub za.h[w8, 5, vgx2], { z16.h, z17.h } // CHECK-ENCODING: [0x0d,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41e0d fsub za.h[w8, 5], {z16.h - z17.h} // 11000001-10100100-00011110-00001101 // CHECK-INST: fsub za.h[w8, 5, vgx2], { z16.h, z17.h } // CHECK-ENCODING: [0x0d,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41e0d fsub za.h[w8, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-00011100-00001001 // CHECK-INST: fsub za.h[w8, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x09,0x1c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41c09 fsub za.h[w8, 1], {z0.h - z1.h} // 11000001-10100100-00011100-00001001 // CHECK-INST: fsub za.h[w8, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x09,0x1c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41c09 fsub za.h[w10, 0, vgx2], {z18.h, z19.h} // 11000001-10100100-01011110, 01001000 // CHECK-INST: fsub za.h[w10, 0, vgx2], { z18.h, z19.h } // CHECK-ENCODING: [0x48,0x5e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45e48 fsub za.h[w10, 0], {z18.h - z19.h} // 11000001-10100100-01011110-01001000 // CHECK-INST: fsub za.h[w10, 0, vgx2], { z18.h, z19.h } // CHECK-ENCODING: [0x48,0x5e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45e48 fsub za.h[w8, 0, vgx2], {z12.h, z13.h} // 11000001-10100100-00011101-10001000 // CHECK-INST: fsub za.h[w8, 0, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x88,0x1d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41d88 fsub za.h[w8, 0], {z12.h - z13.h} // 11000001-10100100-00011101-10001000 // CHECK-INST: fsub za.h[w8, 0, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x88,0x1d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41d88 fsub za.h[w10, 1, vgx2], {z0.h, z1.h} // 11000001-10100100-01011100-00001001 // CHECK-INST: fsub za.h[w10, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x09,0x5c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45c09 fsub za.h[w10, 1], {z0.h - z1.h} // 11000001-10100100-01011100-00001001 // CHECK-INST: fsub za.h[w10, 1, vgx2], { z0.h, z1.h } // CHECK-ENCODING: [0x09,0x5c,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a45c09 fsub za.h[w8, 5, vgx2], {z22.h, z23.h} // 11000001-10100100-00011110, 11001101 // CHECK-INST: fsub za.h[w8, 5, vgx2], { z22.h, z23.h } // CHECK-ENCODING: [0xcd,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41ecd fsub za.h[w8, 5], {z22.h - z23.h} // 11000001-10100100-00011110-11001101 // CHECK-INST: fsub za.h[w8, 5, vgx2], { z22.h, z23.h } // CHECK-ENCODING: [0xcd,0x1e,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a41ecd fsub za.h[w11, 2, vgx2], {z8.h, z9.h} // 11000001-10100100-01111101-00001010 // CHECK-INST: fsub za.h[w11, 2, vgx2], { z8.h, z9.h } // CHECK-ENCODING: [0x0a,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d0a fsub za.h[w11, 2], {z8.h - z9.h} // 11000001-10100100-01111101-00001010 // CHECK-INST: fsub za.h[w11, 2, vgx2], { z8.h, z9.h } // CHECK-ENCODING: [0x0a,0x7d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a47d0a fsub za.h[w9, 7, vgx2], {z12.h, z13.h} // 11000001-10100100-00111101-10001111 // CHECK-INST: fsub za.h[w9, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x8f,0x3d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a43d8f fsub za.h[w9, 7], {z12.h - z13.h} // 11000001-10100100-00111101-10001111 // CHECK-INST: fsub za.h[w9, 7, vgx2], { z12.h, z13.h } // CHECK-ENCODING: [0x8f,0x3d,0xa4,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a43d8f fsub za.h[w8, 0, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00001000 // CHECK-INST: fsub za.h[w8, 0, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x08,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c08 fsub za.h[w8, 0], {z0.h - z3.h} // 11000001-10100101-00011100-00001000 // CHECK-INST: fsub za.h[w8, 0, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x08,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c08 fsub za.h[w10, 5, vgx4], {z8.h - z11.h} // 11000001-10100101-01011101-00001101 // CHECK-INST: fsub za.h[w10, 5, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x0d,0x5d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55d0d fsub za.h[w10, 5], {z8.h - z11.h} // 11000001-10100101-01011101-00001101 // CHECK-INST: fsub za.h[w10, 5, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x0d,0x5d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55d0d fsub za.h[w11, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-01111101-10001111 // CHECK-INST: fsub za.h[w11, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x8f,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d8f fsub za.h[w11, 7], {z12.h - z15.h} // 11000001-10100101-01111101-10001111 // CHECK-INST: fsub za.h[w11, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x8f,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d8f fsub za.h[w11, 7, vgx4], {z28.h - z31.h} // 11000001-10100101-01111111-10001111 // CHECK-INST: fsub za.h[w11, 7, vgx4], { z28.h - z31.h } // CHECK-ENCODING: [0x8f,0x7f,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57f8f fsub za.h[w11, 7], {z28.h - z31.h} // 11000001-10100101-01111111-10001111 // CHECK-INST: fsub za.h[w11, 7, vgx4], { z28.h - z31.h } // CHECK-ENCODING: [0x8f,0x7f,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57f8f fsub za.h[w8, 5, vgx4], {z16.h - z19.h} // 11000001-10100101-00011110-00001101 // CHECK-INST: fsub za.h[w8, 5, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x0d,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e0d fsub za.h[w8, 5], {z16.h - z19.h} // 11000001-10100101-00011110-00001101 // CHECK-INST: fsub za.h[w8, 5, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x0d,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e0d fsub za.h[w8, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-00011100-00001001 // CHECK-INST: fsub za.h[w8, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x09,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c09 fsub za.h[w8, 1], {z0.h - z3.h} // 11000001-10100101-00011100-00001001 // CHECK-INST: fsub za.h[w8, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x09,0x1c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51c09 fsub za.h[w10, 0, vgx4], {z16.h - z19.h} // 11000001-10100101-01011110-00001000 // CHECK-INST: fsub za.h[w10, 0, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x08,0x5e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55e08 fsub za.h[w10, 0], {z16.h - z19.h} // 11000001-10100101-01011110-00001000 // CHECK-INST: fsub za.h[w10, 0, vgx4], { z16.h - z19.h } // CHECK-ENCODING: [0x08,0x5e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55e08 fsub za.h[w8, 0, vgx4], {z12.h - z15.h} // 11000001-10100101-00011101-10001000 // CHECK-INST: fsub za.h[w8, 0, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x88,0x1d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51d88 fsub za.h[w8, 0], {z12.h - z15.h} // 11000001-10100101-00011101-10001000 // CHECK-INST: fsub za.h[w8, 0, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x88,0x1d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51d88 fsub za.h[w10, 1, vgx4], {z0.h - z3.h} // 11000001-10100101-01011100-00001001 // CHECK-INST: fsub za.h[w10, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x09,0x5c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55c09 fsub za.h[w10, 1], {z0.h - z3.h} // 11000001-10100101-01011100-00001001 // CHECK-INST: fsub za.h[w10, 1, vgx4], { z0.h - z3.h } // CHECK-ENCODING: [0x09,0x5c,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a55c09 fsub za.h[w8, 5, vgx4], {z20.h - z23.h} // 11000001-10100101-00011110-10001101 // CHECK-INST: fsub za.h[w8, 5, vgx4], { z20.h - z23.h } // CHECK-ENCODING: [0x8d,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e8d fsub za.h[w8, 5], {z20.h - z23.h} // 11000001-10100101-00011110-10001101 // CHECK-INST: fsub za.h[w8, 5, vgx4], { z20.h - z23.h } // CHECK-ENCODING: [0x8d,0x1e,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a51e8d fsub za.h[w11, 2, vgx4], {z8.h - z11.h} // 11000001-10100101-01111101-00001010 // CHECK-INST: fsub za.h[w11, 2, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x0a,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d0a fsub za.h[w11, 2], {z8.h - z11.h} // 11000001-10100101-01111101-00001010 // CHECK-INST: fsub za.h[w11, 2, vgx4], { z8.h - z11.h } // CHECK-ENCODING: [0x0a,0x7d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a57d0a fsub za.h[w9, 7, vgx4], {z12.h - z15.h} // 11000001-10100101-00111101-10001111 // CHECK-INST: fsub za.h[w9, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x8f,0x3d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a53d8f fsub za.h[w9, 7], {z12.h - z15.h} // 11000001-10100101-00111101-10001111 // CHECK-INST: fsub za.h[w9, 7, vgx4], { z12.h - z15.h } // CHECK-ENCODING: [0x8f,0x3d,0xa5,0xc1] -// CHECK-ERROR: instruction requires: sme2p1 +// CHECK-ERROR: instruction requires: sme-f16f16 or sme-f8f16 // CHECK-UNKNOWN: c1a53d8f -- GitLab From 468fecfc39a7ad4a88ac9f8b8acb5ea76cbb1fc7 Mon Sep 17 00:00:00 2001 From: Troy Butler <118708570+Troy-Butler@users.noreply.github.com> Date: Fri, 26 Apr 2024 07:00:31 -0400 Subject: [PATCH 046/301] Fix mismatches between function parameter definitions and declarations (#89512) Addresses issue #88716. Some function parameter names in the affected header files did not match the parameter names in the definitions, or were listed in a different order. --------- Signed-off-by: Troy-Butler --- .../StaticAnalyzer/Core/PathSensitive/Store.h | 14 +++++-------- .../InstCombine/InstCombineAndOrXor.cpp | 20 +++++++++---------- llvm/lib/Transforms/Vectorize/VPlan.h | 4 ++-- .../Transforms/Utils/SparseTensorIterator.h | 7 ++++--- 4 files changed, 21 insertions(+), 24 deletions(-) diff --git a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h index fac0c04ae2ca..ef23b160a3c0 100644 --- a/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h +++ b/clang/include/clang/StaticAnalyzer/Core/PathSensitive/Store.h @@ -225,15 +225,11 @@ public: /// invalidated. This should include any regions explicitly invalidated /// even if they do not currently have bindings. Pass \c NULL if this /// information will not be used. - virtual StoreRef invalidateRegions(Store store, - ArrayRef Values, - const Expr *E, unsigned Count, - const LocationContext *LCtx, - const CallEvent *Call, - InvalidatedSymbols &IS, - RegionAndSymbolInvalidationTraits &ITraits, - InvalidatedRegions *InvalidatedTopLevel, - InvalidatedRegions *Invalidated) = 0; + virtual StoreRef invalidateRegions( + Store store, ArrayRef Values, const Expr *Ex, unsigned Count, + const LocationContext *LCtx, const CallEvent *Call, + InvalidatedSymbols &IS, RegionAndSymbolInvalidationTraits &ITraits, + InvalidatedRegions *TopLevelRegions, InvalidatedRegions *Invalidated) = 0; /// enterStackFrame - Let the StoreManager to do something when execution /// engine is about to execute into a callee. diff --git a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp index 8ec1ed7529c1..ed9a89b14efc 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineAndOrXor.cpp @@ -3141,20 +3141,20 @@ Value *InstCombinerImpl::getSelectCondition(Value *A, Value *B, return nullptr; } -/// We have an expression of the form (A & C) | (B & D). Try to simplify this -/// to "A' ? C : D", where A' is a boolean or vector of booleans. +/// We have an expression of the form (A & B) | (C & D). Try to simplify this +/// to "A' ? B : D", where A' is a boolean or vector of booleans. /// When InvertFalseVal is set to true, we try to match the pattern -/// where we have peeked through a 'not' op and A and B are the same: -/// (A & C) | ~(A | D) --> (A & C) | (~A & ~D) --> A' ? C : ~D -Value *InstCombinerImpl::matchSelectFromAndOr(Value *A, Value *C, Value *B, +/// where we have peeked through a 'not' op and A and C are the same: +/// (A & B) | ~(A | D) --> (A & B) | (~A & ~D) --> A' ? B : ~D +Value *InstCombinerImpl::matchSelectFromAndOr(Value *A, Value *B, Value *C, Value *D, bool InvertFalseVal) { // The potential condition of the select may be bitcasted. In that case, look // through its bitcast and the corresponding bitcast of the 'not' condition. Type *OrigType = A->getType(); A = peekThroughBitcast(A, true); - B = peekThroughBitcast(B, true); - if (Value *Cond = getSelectCondition(A, B, InvertFalseVal)) { - // ((bc Cond) & C) | ((bc ~Cond) & D) --> bc (select Cond, (bc C), (bc D)) + C = peekThroughBitcast(C, true); + if (Value *Cond = getSelectCondition(A, C, InvertFalseVal)) { + // ((bc Cond) & B) | ((bc ~Cond) & D) --> bc (select Cond, (bc B), (bc D)) // If this is a vector, we may need to cast to match the condition's length. // The bitcasts will either all exist or all not exist. The builder will // not create unnecessary casts if the types already match. @@ -3168,11 +3168,11 @@ Value *InstCombinerImpl::matchSelectFromAndOr(Value *A, Value *C, Value *B, Type *EltTy = Builder.getIntNTy(SelEltSize / Elts); SelTy = VectorType::get(EltTy, VecTy->getElementCount()); } - Value *BitcastC = Builder.CreateBitCast(C, SelTy); + Value *BitcastB = Builder.CreateBitCast(B, SelTy); if (InvertFalseVal) D = Builder.CreateNot(D); Value *BitcastD = Builder.CreateBitCast(D, SelTy); - Value *Select = Builder.CreateSelect(Cond, BitcastC, BitcastD); + Value *Select = Builder.CreateSelect(Cond, BitcastB, BitcastD); return Builder.CreateBitCast(Select, OrigType); } diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index c74329a0bcc4..21b088cd2386 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -3278,8 +3278,8 @@ public: private: /// Add to the given dominator tree the header block and every new basic block /// that was created between it and the latch block, inclusive. - static void updateDominatorTree(DominatorTree *DT, BasicBlock *LoopLatchBB, - BasicBlock *LoopPreHeaderBB, + static void updateDominatorTree(DominatorTree *DT, BasicBlock *LoopHeaderBB, + BasicBlock *LoopLatchBB, BasicBlock *LoopExitBB); }; diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.h b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.h index 9d69a2335559..46b923250dd8 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.h +++ b/mlir/lib/Dialect/SparseTensor/Transforms/Utils/SparseTensorIterator.h @@ -284,9 +284,10 @@ private: }; /// Helper function to create a TensorLevel object from given `tensor`. -std::unique_ptr makeSparseTensorLevel(OpBuilder &builder, - Location loc, Value t, - unsigned tid, Level l); +std::unique_ptr makeSparseTensorLevel(OpBuilder &b, + Location l, Value t, + unsigned tid, + Level lvl); /// Helper function to create a simple SparseIterator object that iterate over /// the SparseTensorLevel. -- GitLab From 357530f11351687aaec2f19ef7e19c82d5317210 Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 26 Apr 2024 12:01:00 +0100 Subject: [PATCH 047/301] Revert "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" This reverts commit 733b271db793ce30c504a1b5c4ae7a8775b0a6a2. Reverting in order to revert the companion patch adding the atomics ABI ELF attributes due to the reported incompatibility with GNU ld. https://github.com/llvm/llvm-project/pull/84597#issuecomment-2079128332 --- llvm/docs/ReleaseNotes.rst | 5 ----- .../RISCV/MCTargetDesc/RISCVTargetStreamer.cpp | 6 +++--- llvm/lib/Target/RISCV/RISCVFeatures.td | 8 ++++---- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 2 +- llvm/test/CodeGen/RISCV/atomic-load-store.ll | 16 ++++++++-------- llvm/test/CodeGen/RISCV/attributes.ll | 4 ++-- llvm/test/CodeGen/RISCV/forced-atomics.ll | 12 ++++++------ 7 files changed, 24 insertions(+), 29 deletions(-) diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 1be8db602a15..6ef6ec20da67 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -112,11 +112,6 @@ Changes to the RISC-V Backend * The experimental Ssqosid extension is supported. * Zacas is no longer experimental. * Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension. -* The default atomics mapping was changed to emit an additional trailing fence - for sequentially consistent stores, offering compatibility with a future - mapping using load-acquire and store-release instructions while remaining - fully compatible with objects produced prior to this change. The mapping - (ABI) used is recorded as an ELF attribute. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index adb17cec28c2..6f5f12cc7286 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -77,9 +77,9 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, } if (STI.hasFeature(RISCV::FeatureStdExtA)) { - unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureNoTrailingSeqCstFence) - ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C - : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S; + unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureTrailingSeqCstFence) + ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S + : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C; emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag); } } diff --git a/llvm/lib/Target/RISCV/RISCVFeatures.td b/llvm/lib/Target/RISCV/RISCVFeatures.td index deb983528f32..c3dc4ea53697 100644 --- a/llvm/lib/Target/RISCV/RISCVFeatures.td +++ b/llvm/lib/Target/RISCV/RISCVFeatures.td @@ -1216,10 +1216,10 @@ foreach i = {1-31} in def FeatureSaveRestore : SubtargetFeature<"save-restore", "EnableSaveRestore", "true", "Enable save/restore.">; -def FeatureNoTrailingSeqCstFence : SubtargetFeature<"no-trailing-seq-cst-fence", - "EnableTrailingSeqCstFence", - "false", - "Disable trailing fence for seq-cst store.">; +def FeatureTrailingSeqCstFence : SubtargetFeature<"seq-cst-trailing-fence", + "EnableSeqCstTrailingFence", + "true", + "Enable trailing fence for seq-cst store.">; def FeatureUnalignedScalarMem : SubtargetFeature<"unaligned-scalar-mem", "EnableUnalignedScalarMem", diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 769c465d56f9..539aa3525545 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -20192,7 +20192,7 @@ Instruction *RISCVTargetLowering::emitTrailingFence(IRBuilderBase &Builder, if (isa(Inst) && isAcquireOrStronger(Ord)) return Builder.CreateFence(AtomicOrdering::Acquire); - if (Subtarget.enableTrailingSeqCstFence() && isa(Inst) && + if (Subtarget.enableSeqCstTrailingFence() && isa(Inst) && Ord == AtomicOrdering::SequentiallyConsistent) return Builder.CreateFence(AtomicOrdering::SequentiallyConsistent); return nullptr; diff --git a/llvm/test/CodeGen/RISCV/atomic-load-store.ll b/llvm/test/CodeGen/RISCV/atomic-load-store.ll index 1586a133568b..2d1fc21cda89 100644 --- a/llvm/test/CodeGen/RISCV/atomic-load-store.ll +++ b/llvm/test/CodeGen/RISCV/atomic-load-store.ll @@ -1,26 +1,26 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV32I %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO %s ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefix=RV64I %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+no-trailing-seq-cst-fence -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO %s -; RUN: llc -mtriple=riscv32 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-WMO-TRAILING-FENCE %s -; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv32 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV32IA,RV32IA-TSO-TRAILING-FENCE %s -; RUN: llc -mtriple=riscv64 -mattr=+a -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-WMO-TRAILING-FENCE %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso -verify-machineinstrs < %s \ +; RUN: llc -mtriple=riscv64 -mattr=+a,+experimental-ztso,+seq-cst-trailing-fence -verify-machineinstrs < %s \ ; RUN: | FileCheck -check-prefixes=RV64IA,RV64IA-TSO-TRAILING-FENCE %s diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 61b5e50c6d52..1aff3e8b83f4 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -129,8 +129,8 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s -; RUN: llc -mtriple=riscv64 -mattr=+a,no-trailing-seq-cst-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s -; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s +; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s +; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll index 44db3c49db8c..c303690aadff 100644 --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -1,12 +1,12 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc -mtriple=riscv32 -mattr=+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC +; RUN: llc -mtriple=riscv32 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC ; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=RV32,RV32-NO-ATOMIC -; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC -; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING -; RUN: llc -mtriple=riscv64 -mattr=+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC +; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC +; RUN: llc -mtriple=riscv32 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV32,RV32-ATOMIC-TRAILING ; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC -; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+no-trailing-seq-cst-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC -; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING +; RUN: llc -mtriple=riscv64 -mattr=+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-NO-ATOMIC +; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC +; RUN: llc -mtriple=riscv64 -mattr=+forced-atomics,+seq-cst-trailing-fence < %s | FileCheck %s --check-prefixes=RV64,RV64-ATOMIC-TRAILING define i8 @load8(ptr %p) nounwind { ; RV32-NO-ATOMIC-LABEL: load8: -- GitLab From 431be8626696da6059eee26b9a14e1dc9fc0c37f Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 26 Apr 2024 12:02:01 +0100 Subject: [PATCH 048/301] Revert "[RISCV] Support RISCV Atomics ABI attributes (#84597)" This reverts commit 9221f3af8f832d990be986c05d964ad37e5a2356. As reported and confirmed by me locally, adding these attributes causes current GNU ld to segfault when processing the input. Reverted so we can discuss the best next step. --- lld/ELF/Arch/RISCV.cpp | 63 ------ lld/test/ELF/riscv-attributes.s | 202 ------------------ .../llvm/Support/RISCVAttributeParser.h | 1 - llvm/include/llvm/Support/RISCVAttributes.h | 13 -- llvm/lib/Support/RISCVAttributeParser.cpp | 13 +- llvm/lib/Support/RISCVAttributes.cpp | 1 - .../MCTargetDesc/RISCVTargetStreamer.cpp | 7 - llvm/test/CodeGen/RISCV/attributes.ll | 10 +- llvm/test/MC/RISCV/attribute.s | 3 - llvm/test/MC/RISCV/invalid-attribute.s | 3 - 10 files changed, 2 insertions(+), 314 deletions(-) diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 7b9c9c6c6c38..20088d92bafa 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -1084,62 +1084,10 @@ static void mergeArch(RISCVISAInfo::OrderedExtensionMap &mergedExts, } } -static void mergeAtomic(DenseMap::iterator it, - const InputSectionBase *oldSection, - const InputSectionBase *newSection, unsigned int oldTag, - unsigned int newTag) { - using RISCVAttrs::RISCVAtomicAbiTag::AtomicABI; - // Same tags stay the same, and UNKNOWN is compatible with anything - if (oldTag == newTag || newTag == AtomicABI::UNKNOWN) - return; - - switch (oldTag) { - case AtomicABI::UNKNOWN: - it->getSecond() = newTag; - return; - case AtomicABI::A6C: - switch (newTag) { - case AtomicABI::A6S: - it->getSecond() = AtomicABI::A6C; - return; - case AtomicABI::A7: - error(toString(oldSection) + " has atomic_abi=" + Twine(oldTag) + - " but " + toString(newSection) + - " has atomic_abi=" + Twine(newTag)); - return; - }; - - case AtomicABI::A6S: - switch (newTag) { - case AtomicABI::A6C: - it->getSecond() = AtomicABI::A6C; - return; - case AtomicABI::A7: - it->getSecond() = AtomicABI::A7; - return; - }; - - case AtomicABI::A7: - switch (newTag) { - case AtomicABI::A6S: - it->getSecond() = AtomicABI::A7; - return; - case AtomicABI::A6C: - error(toString(oldSection) + " has atomic_abi=" + Twine(oldTag) + - " but " + toString(newSection) + - " has atomic_abi=" + Twine(newTag)); - return; - }; - default: - llvm_unreachable("unknown AtomicABI"); - }; -} - static RISCVAttributesSection * mergeAttributesSection(const SmallVector §ions) { RISCVISAInfo::OrderedExtensionMap exts; const InputSectionBase *firstStackAlign = nullptr; - const InputSectionBase *firstAtomicAbi = nullptr; unsigned firstStackAlignValue = 0, xlen = 0; bool hasArch = false; @@ -1186,17 +1134,6 @@ mergeAttributesSection(const SmallVector §ions) { case RISCVAttrs::PRIV_SPEC_MINOR: case RISCVAttrs::PRIV_SPEC_REVISION: break; - - case llvm::RISCVAttrs::AttrType::ATOMIC_ABI: - if (auto i = parser.getAttributeValue(tag.attr)) { - auto r = merged.intAttr.try_emplace(tag.attr, *i); - if (r.second) { - firstAtomicAbi = sec; - } else { - mergeAtomic(r.first, firstAtomicAbi, sec, r.first->getSecond(), *i); - } - } - continue; } // Fallback for deprecated priv_spec* and other unknown attributes: retain diff --git a/lld/test/ELF/riscv-attributes.s b/lld/test/ELF/riscv-attributes.s index 77c2c3cb263f..d0ce0941269e 100644 --- a/lld/test/ELF/riscv-attributes.s +++ b/lld/test/ELF/riscv-attributes.s @@ -44,39 +44,6 @@ # RUN: not ld.lld a.o b.o c.o diff_stack_align.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=STACK_ALIGN --implicit-check-not=error: # STACK_ALIGN: error: diff_stack_align.o:(.riscv.attributes) has stack_align=32 but a.o:(.riscv.attributes) has stack_align=16 -## merging atomic_abi values for A6C and A7 lead to an error. -# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_A6C.s -o atomic_abi_A6C.o -# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_A7.s -o atomic_abi_A7.o -# RUN: not ld.lld atomic_abi_A6C.o atomic_abi_A7.o -o /dev/null 2>&1 | FileCheck %s --check-prefix=ATOMIC_ABI_ERROR --implicit-check-not=error: -# ATOMIC_ABI_ERROR: error: atomic_abi_A6C.o:(.riscv.attributes) has atomic_abi=1 but atomic_abi_A7.o:(.riscv.attributes) has atomic_abi=3 - - -# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_A6S.s -o atomic_abi_A6S.o -# RUN: ld.lld atomic_abi_A6S.o atomic_abi_A6C.o -o atomic_abi_A6C_A6S -# RUN: llvm-readobj -A atomic_abi_A6C_A6S | FileCheck %s --check-prefix=A6C_A6S - -# RUN: ld.lld atomic_abi_A6S.o atomic_abi_A7.o -o atomic_abi_A6S_A7 -# RUN: llvm-readobj -A atomic_abi_A6S_A7 | FileCheck %s --check-prefix=A6S_A7 - -# RUN: llvm-mc -filetype=obj -triple=riscv64 atomic_abi_unknown.s -o atomic_abi_unknown.o -# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A6C.o -o atomic_abi_A6C_unknown -# RUN: llvm-readobj -A atomic_abi_A6C_unknown | FileCheck %s --check-prefixes=UNKNOWN_A6C - -# RUN: ld.lld atomic_abi_unknown.o diff_stack_align.o -o atomic_abi_none_unknown -# RUN: llvm-readobj -A atomic_abi_none_unknown | FileCheck %s --check-prefixes=UNKNOWN_NONE - -# RUN: ld.lld diff_stack_align.o atomic_abi_A6C.o -o atomic_abi_A6C_none -# RUN: llvm-readobj -A atomic_abi_A6C_none | FileCheck %s --check-prefixes=NONE_A6C - -# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A6S.o -o atomic_abi_A6S_unknown -# RUN: llvm-readobj -A atomic_abi_A6S_unknown | FileCheck %s --check-prefix=UNKNOWN_A6S - -# RUN: ld.lld atomic_abi_unknown.o atomic_abi_A7.o -o atomic_abi_A7_unknown -# RUN: llvm-readobj -A atomic_abi_A7_unknown | FileCheck %s --check-prefix=UNKNOWN_A7 - -# RUN: ld.lld diff_stack_align.o atomic_abi_A7.o -o atomic_abi_A7_none -# RUN: llvm-readobj -A atomic_abi_A7_none | FileCheck %s --check-prefix=NONE_A7 - ## The deprecated priv_spec is not handled as GNU ld does. ## Differing priv_spec attributes lead to an absent attribute. # RUN: llvm-mc -filetype=obj -triple=riscv64 diff_priv_spec.s -o diff_priv_spec.o @@ -319,175 +286,6 @@ .attribute priv_spec, 3 .attribute priv_spec_minor, 3 -#--- atomic_abi_unknown.s -.attribute atomic_abi, 0 - -#--- atomic_abi_A6C.s -.attribute atomic_abi, 1 - -#--- atomic_abi_A6S.s -.attribute atomic_abi, 2 - -#--- atomic_abi_A7.s -.attribute atomic_abi, 3 - -# UNKNOWN_NONE: BuildAttributes { -# UNKNOWN_NONE-NEXT: FormatVersion: 0x41 -# UNKNOWN_NONE-NEXT: Section 1 { -# UNKNOWN_NONE-NEXT: SectionLength: 17 -# UNKNOWN_NONE-NEXT: Vendor: riscv -# UNKNOWN_NONE-NEXT: Tag: Tag_File (0x1) -# UNKNOWN_NONE-NEXT: Size: 7 -# UNKNOWN_NONE-NEXT: FileAttributes { -# UNKNOWN_NONE-NEXT: Attribute { -# UNKNOWN_NONE-NEXT: Tag: 4 -# UNKNOWN_NONE-NEXT: Value: 32 -# UNKNOWN_NONE-NEXT: TagName: stack_align -# UNKNOWN_NONE-NEXT: Description: Stack alignment is 32-bytes -# UNKNOWN_NONE-NEXT: } -# UNKNOWN_NONE-NEXT: } -# UNKNOWN_NONE-NEXT: } -# UNKNOWN_NONE-NEXT: } - -# NONE_A6C: BuildAttributes { -# NONE_A6C-NEXT: FormatVersion: 0x41 -# NONE_A6C-NEXT: Section 1 { -# NONE_A6C-NEXT: SectionLength: 19 -# NONE_A6C-NEXT: Vendor: riscv -# NONE_A6C-NEXT: Tag: Tag_File (0x1) -# NONE_A6C-NEXT: Size: 9 -# NONE_A6C-NEXT: FileAttributes { -# NONE_A6C-NEXT: Attribute { -# NONE_A6C-NEXT: Tag: 14 -# NONE_A6C-NEXT: Value: 1 -# NONE_A6C-NEXT: TagName: atomic_abi -# NONE_A6C-NEXT: Description: Atomic ABI is 1 -# NONE_A6C-NEXT: } -# NONE_A6C-NEXT: Attribute { -# NONE_A6C-NEXT: Tag: 4 -# NONE_A6C-NEXT: Value: 32 -# NONE_A6C-NEXT: TagName: stack_align -# NONE_A6C-NEXT: Description: Stack alignment is 32-bytes -# NONE_A6C-NEXT: } -# NONE_A6C-NEXT: } -# NONE_A6C-NEXT: } -# NONE_A6C-NEXT: } - -# UNKNOWN_A6C: BuildAttributes { -# UNKNOWN_A6C-NEXT: FormatVersion: 0x41 -# UNKNOWN_A6C-NEXT: Section 1 { -# UNKNOWN_A6C-NEXT: SectionLength: 17 -# UNKNOWN_A6C-NEXT: Vendor: riscv -# UNKNOWN_A6C-NEXT: Tag: Tag_File (0x1) -# UNKNOWN_A6C-NEXT: Size: 7 -# UNKNOWN_A6C-NEXT: FileAttributes { -# UNKNOWN_A6C-NEXT: Attribute { -# UNKNOWN_A6C-NEXT: Tag: 14 -# UNKNOWN_A6C-NEXT: Value: 1 -# UNKNOWN_A6C-NEXT: TagName: atomic_abi -# UNKNOWN_A6C-NEXT: Description: Atomic ABI is 1 -# UNKNOWN_A6C-NEXT: } -# UNKNOWN_A6C-NEXT: } -# UNKNOWN_A6C-NEXT: } -# UNKNOWN_A6C-NEXT: } - -# UNKNOWN_A6S: BuildAttributes { -# UNKNOWN_A6S-NEXT: FormatVersion: 0x41 -# UNKNOWN_A6S-NEXT: Section 1 { -# UNKNOWN_A6S-NEXT: SectionLength: -# UNKNOWN_A6S-NEXT: Vendor: riscv -# UNKNOWN_A6S-NEXT: Tag: Tag_File (0x1) -# UNKNOWN_A6S-NEXT: Size: 7 -# UNKNOWN_A6S-NEXT: FileAttributes { -# UNKNOWN_A6S-NEXT: Attribute { -# UNKNOWN_A6S-NEXT: Tag: 14 -# UNKNOWN_A6S-NEXT: Value: 2 -# UNKNOWN_A6S-NEXT: TagName: atomic_abi -# UNKNOWN_A6S-NEXT: Description: Atomic ABI is 2 -# UNKNOWN_A6S-NEXT: } -# UNKNOWN_A6S-NEXT: } -# UNKNOWN_A6S-NEXT: } -# UNKNOWN_A6S-NEXT: } - -# NONE_A7: BuildAttributes { -# NONE_A7-NEXT: FormatVersion: 0x41 -# NONE_A7-NEXT: Section 1 { -# NONE_A7-NEXT: SectionLength: 19 -# NONE_A7-NEXT: Vendor: riscv -# NONE_A7-NEXT: Tag: Tag_File (0x1) -# NONE_A7-NEXT: Size: 9 -# NONE_A7-NEXT: FileAttributes { -# NONE_A7-NEXT: Attribute { -# NONE_A7-NEXT: Tag: 14 -# NONE_A7-NEXT: Value: 3 -# NONE_A7-NEXT: TagName: atomic_abi -# NONE_A7-NEXT: Description: Atomic ABI is 3 -# NONE_A7-NEXT: } -# NONE_A7-NEXT: Attribute { -# NONE_A7-NEXT: Tag: 4 -# NONE_A7-NEXT: Value: 32 -# NONE_A7-NEXT: TagName: stack_align -# NONE_A7-NEXT: Description: Stack alignment is 32-bytes -# NONE_A7-NEXT: } -# NONE_A7-NEXT: } -# NONE_A7-NEXT: } -# NONE_A7-NEXT: } - - -# UNKNOWN_A7: BuildAttributes { -# UNKNOWN_A7-NEXT: FormatVersion: 0x41 -# UNKNOWN_A7-NEXT: Section 1 { -# UNKNOWN_A7-NEXT: SectionLength: 17 -# UNKNOWN_A7-NEXT: Vendor: riscv -# UNKNOWN_A7-NEXT: Tag: Tag_File (0x1) -# UNKNOWN_A7-NEXT: Size: 7 -# UNKNOWN_A7-NEXT: FileAttributes { -# UNKNOWN_A7-NEXT: Attribute { -# UNKNOWN_A7-NEXT: Tag: 14 -# UNKNOWN_A7-NEXT: Value: 3 -# UNKNOWN_A7-NEXT: TagName: atomic_abi -# UNKNOWN_A7-NEXT: Description: Atomic ABI is 3 -# UNKNOWN_A7-NEXT: } -# UNKNOWN_A7-NEXT: } -# UNKNOWN_A7-NEXT: } -# UNKNOWN_A7-NEXT: } - -# A6C_A6S: BuildAttributes { -# A6C_A6S-NEXT: FormatVersion: 0x41 -# A6C_A6S-NEXT: Section 1 { -# A6C_A6S-NEXT: SectionLength: 17 -# A6C_A6S-NEXT: Vendor: riscv -# A6C_A6S-NEXT: Tag: Tag_File (0x1) -# A6C_A6S-NEXT: Size: 7 -# A6C_A6S-NEXT: FileAttributes { -# A6C_A6S-NEXT: Attribute { -# A6C_A6S-NEXT: Tag: 14 -# A6C_A6S-NEXT: Value: 1 -# A6C_A6S-NEXT: TagName: atomic_abi -# A6C_A6S-NEXT: Description: Atomic ABI is 1 -# A6C_A6S-NEXT: } -# A6C_A6S-NEXT: } -# A6C_A6S-NEXT: } -# A6C_A6S-NEXT: } - -# A6S_A7: BuildAttributes { -# A6S_A7-NEXT: FormatVersion: 0x41 -# A6S_A7-NEXT: Section 1 { -# A6S_A7-NEXT: SectionLength: 17 -# A6S_A7-NEXT: Vendor: riscv -# A6S_A7-NEXT: Tag: Tag_File (0x1) -# A6S_A7-NEXT: Size: 7 -# A6S_A7-NEXT: FileAttributes { -# A6S_A7-NEXT: Attribute { -# A6S_A7-NEXT: Tag: 14 -# A6S_A7-NEXT: Value: 3 -# A6S_A7-NEXT: TagName: atomic_abi -# A6S_A7-NEXT: Description: Atomic ABI is 3 -# A6S_A7-NEXT: } -# A6S_A7-NEXT: } -# A6S_A7-NEXT: } -# A6S_A7-NEXT: } - #--- unknown13.s .attribute 13, "0" #--- unknown13a.s diff --git a/llvm/include/llvm/Support/RISCVAttributeParser.h b/llvm/include/llvm/Support/RISCVAttributeParser.h index 9f295504de95..305adffbe851 100644 --- a/llvm/include/llvm/Support/RISCVAttributeParser.h +++ b/llvm/include/llvm/Support/RISCVAttributeParser.h @@ -24,7 +24,6 @@ class RISCVAttributeParser : public ELFAttributeParser { Error unalignedAccess(unsigned tag); Error stackAlign(unsigned tag); - Error atomicAbi(unsigned tag); public: RISCVAttributeParser(ScopedPrinter *sw) diff --git a/llvm/include/llvm/Support/RISCVAttributes.h b/llvm/include/llvm/Support/RISCVAttributes.h index 5def890a7273..18f5a84d21f2 100644 --- a/llvm/include/llvm/Support/RISCVAttributes.h +++ b/llvm/include/llvm/Support/RISCVAttributes.h @@ -32,21 +32,8 @@ enum AttrType : unsigned { PRIV_SPEC = 8, PRIV_SPEC_MINOR = 10, PRIV_SPEC_REVISION = 12, - ATOMIC_ABI = 14, }; -namespace RISCVAtomicAbiTag { -enum AtomicABI : unsigned { - // Values for Tag_RISCV_atomic_abi - // Defined at - // https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version - UNKNOWN = 0, - A6C = 1, - A6S = 2, - A7 = 3, -}; -} // namespace RISCVAtomicAbiTag - enum { NOT_ALLOWED = 0, ALLOWED = 1 }; } // namespace RISCVAttrs diff --git a/llvm/lib/Support/RISCVAttributeParser.cpp b/llvm/lib/Support/RISCVAttributeParser.cpp index 19c5a0e06903..7ce4b6ab161c 100644 --- a/llvm/lib/Support/RISCVAttributeParser.cpp +++ b/llvm/lib/Support/RISCVAttributeParser.cpp @@ -36,18 +36,7 @@ const RISCVAttributeParser::DisplayHandler { RISCVAttrs::UNALIGNED_ACCESS, &RISCVAttributeParser::unalignedAccess, - }, - { - RISCVAttrs::ATOMIC_ABI, - &RISCVAttributeParser::atomicAbi, - }, -}; - -Error RISCVAttributeParser::atomicAbi(unsigned Tag) { - uint64_t Value = de.getULEB128(cursor); - printAttribute(Tag, Value, "Atomic ABI is " + utostr(Value)); - return Error::success(); -} + }}; Error RISCVAttributeParser::unalignedAccess(unsigned tag) { static const char *strings[] = {"No unaligned access", "Unaligned access"}; diff --git a/llvm/lib/Support/RISCVAttributes.cpp b/llvm/lib/Support/RISCVAttributes.cpp index dc70d65acba0..9e629760d3d8 100644 --- a/llvm/lib/Support/RISCVAttributes.cpp +++ b/llvm/lib/Support/RISCVAttributes.cpp @@ -18,7 +18,6 @@ static constexpr TagNameItem tagData[] = { {PRIV_SPEC, "Tag_priv_spec"}, {PRIV_SPEC_MINOR, "Tag_priv_spec_minor"}, {PRIV_SPEC_REVISION, "Tag_priv_spec_revision"}, - {ATOMIC_ABI, "Tag_atomic_abi"}, }; constexpr TagNameMap RISCVAttributeTags{tagData}; diff --git a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp index 6f5f12cc7286..0f92e9ed6a64 100644 --- a/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp +++ b/llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp @@ -75,13 +75,6 @@ void RISCVTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI, auto &ISAInfo = *ParseResult; emitTextAttribute(RISCVAttrs::ARCH, ISAInfo->toString()); } - - if (STI.hasFeature(RISCV::FeatureStdExtA)) { - unsigned AtomicABITag = STI.hasFeature(RISCV::FeatureTrailingSeqCstFence) - ? RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6S - : RISCVAttrs::RISCVAtomicAbiTag::AtomicABI::A6C; - emitAttribute(RISCVAttrs::ATOMIC_ABI, AtomicABITag); - } } // This part is for ascii assembly output diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 1aff3e8b83f4..141d5ea41828 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -129,8 +129,7 @@ ; RUN: llc -mtriple=riscv64 -mattr=+m %s -o - | FileCheck --check-prefixes=CHECK,RV64M %s ; RUN: llc -mtriple=riscv64 -mattr=+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64ZMMUL %s ; RUN: llc -mtriple=riscv64 -mattr=+m,+zmmul %s -o - | FileCheck --check-prefixes=CHECK,RV64MZMMUL %s -; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6C %s -; RUN: llc -mtriple=riscv64 -mattr=+a,+seq-cst-trailing-fence %s -o - | FileCheck --check-prefixes=CHECK,RV64A,A6S %s +; RUN: llc -mtriple=riscv64 -mattr=+a %s -o - | FileCheck --check-prefixes=CHECK,RV64A %s ; RUN: llc -mtriple=riscv64 -mattr=+f %s -o - | FileCheck --check-prefixes=CHECK,RV64F %s ; RUN: llc -mtriple=riscv64 -mattr=+d %s -o - | FileCheck --check-prefixes=CHECK,RV64D %s ; RUN: llc -mtriple=riscv64 -mattr=+c %s -o - | FileCheck --check-prefixes=CHECK,RV64C %s @@ -517,10 +516,3 @@ define i32 @addi(i32 %a) { %1 = add i32 %a, 1 ret i32 %1 } - -define i8 @atomic_load_i8_seq_cst(ptr %a) nounwind { - %1 = load atomic i8, ptr %a seq_cst, align 1 - ret i8 %1 -; A6S: .attribute 14, 2 -; A6C: .attribute 14, 1 -} diff --git a/llvm/test/MC/RISCV/attribute.s b/llvm/test/MC/RISCV/attribute.s index 75b9c65ed1cc..56f0cb1daf17 100644 --- a/llvm/test/MC/RISCV/attribute.s +++ b/llvm/test/MC/RISCV/attribute.s @@ -24,6 +24,3 @@ .attribute priv_spec_revision, 0 # CHECK: attribute 12, 0 - -.attribute atomic_abi, 0 -# CHECK: attribute 14, 0 diff --git a/llvm/test/MC/RISCV/invalid-attribute.s b/llvm/test/MC/RISCV/invalid-attribute.s index 2ebf7ddc9aff..1d732af83cda 100644 --- a/llvm/test/MC/RISCV/invalid-attribute.s +++ b/llvm/test/MC/RISCV/invalid-attribute.s @@ -33,6 +33,3 @@ .attribute arch, 30 # CHECK: [[@LINE-1]]:18: error: expected string constant - -.attribute atomic_abi, "16" -# CHECK: [[@LINE-1]]:24: error: expected numeric constant -- GitLab From 73472c5996716cda0dbb3ddb788304e0e7e6a323 Mon Sep 17 00:00:00 2001 From: Bjorn Pettersson Date: Wed, 13 Mar 2024 13:15:09 +0100 Subject: [PATCH 049/301] [SelectionDAG] Treat CopyFromReg as freezing the value (#85932) The description of CopyFromReg in ISDOpcodes.h says that the input valus is defined outside the scope of the current SelectionDAG. I think that means that we basically can treat it as a FREEZE in the sense that it can be seen as neither being undef nor poison. Being able to fold freeze(CopyFromReg) into CopyFromReg seems useful to avoid regressions if we start to introduce freeze instruction in DAGCombiner/foldBoolSelectToLogic, e.g. to solve https://github.com/llvm/llvm-project/issues/84653 Things _not_ dealt with in this patch: - Depending on calling convention an input argument can be passed also on the stack and not in a register. If it is allowed to treat an argument received in a register as not being poison, then I think we want to treat arguments received on the stack the same way. But then we need to attribute load instructions, or add explicit FREEZE when lowering formal arguments. - A common pattern is that there is an AssertZext or AssertSext just after CopyFromReg. I think that if we treat CopyFromReg as never being poison, then it should be allowed to fold (freeze(AssertZext(CopyFromReg))) -> AssertZext(CopyFromReg)) --- llvm/include/llvm/CodeGen/ISDOpcodes.h | 1 + .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 1 + llvm/test/CodeGen/AArch64/combine-mul.ll | 7 +- .../lasx/ir-instruction/insertelement.ll | 42 +- .../lsx/ir-instruction/insertelement.ll | 42 +- llvm/test/CodeGen/RISCV/alu64.ll | 2 +- .../CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll | 16 +- llvm/test/CodeGen/RISCV/bfloat-convert.ll | 108 ++- llvm/test/CodeGen/RISCV/double-convert.ll | 111 ++-- .../CodeGen/RISCV/double-round-conv-sat.ll | 138 ++-- llvm/test/CodeGen/RISCV/float-convert.ll | 158 ++--- .../CodeGen/RISCV/float-round-conv-sat.ll | 288 ++++---- llvm/test/CodeGen/RISCV/forced-atomics.ll | 4 +- llvm/test/CodeGen/RISCV/fpclamptosat.ll | 4 +- llvm/test/CodeGen/RISCV/half-convert.ll | 268 ++++---- .../test/CodeGen/RISCV/half-round-conv-sat.ll | 624 +++++++++--------- llvm/test/CodeGen/RISCV/iabs.ll | 4 +- .../CodeGen/RISCV/rvv/fpclamptosat_vec.ll | 521 +++++++-------- llvm/test/CodeGen/X86/abdu-vector-128.ll | 54 +- .../CodeGen/X86/apx/kmov-postrapseudos.ll | 10 +- .../CodeGen/X86/avx512-broadcast-arith.ll | 10 +- llvm/test/CodeGen/X86/combine-mul.ll | 8 +- .../X86/div-rem-pair-recomposition-signed.ll | 337 +++++----- llvm/test/CodeGen/X86/fold-masked-merge.ll | 4 +- llvm/test/CodeGen/X86/freeze-binary.ll | 56 +- llvm/test/CodeGen/X86/freeze-combine.ll | 16 +- llvm/test/CodeGen/X86/gfni-funnel-shifts.ll | 4 +- llvm/test/CodeGen/X86/gfni-rotates.ll | 14 +- llvm/test/CodeGen/X86/known-never-zero.ll | 30 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 94 ++- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 32 +- llvm/test/CodeGen/X86/pr38539.ll | 202 +++--- llvm/test/CodeGen/X86/pr62286.ll | 31 +- .../CodeGen/X86/scheduler-backtracking.ll | 2 +- llvm/test/CodeGen/X86/sdiv_fix_sat.ll | 250 +++---- .../test/CodeGen/X86/setcc-non-simple-type.ll | 78 ++- llvm/test/CodeGen/X86/vec_saddo.ll | 14 +- llvm/test/CodeGen/X86/vec_ssubo.ll | 14 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 14 +- llvm/test/CodeGen/X86/vec_usubo.ll | 14 +- llvm/test/CodeGen/X86/vector-bo-select.ll | 10 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 86 +-- llvm/test/CodeGen/X86/vector-fshr-256.ll | 28 +- llvm/test/CodeGen/X86/vector-fshr-sub128.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 12 +- 45 files changed, 1856 insertions(+), 1919 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index 078a936b061a..6429947958ee 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -205,6 +205,7 @@ enum NodeType { /// CopyFromReg - This node indicates that the input value is a virtual or /// physical register that is defined outside of the scope of this /// SelectionDAG. The register is available from the RegisterSDNode object. + /// Note that CopyFromReg is considered as also freezing the value. CopyFromReg, /// UNDEF - An undefined node. diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 224c0c5ee970..dde10fd4b8c8 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5063,6 +5063,7 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::VALUETYPE: case ISD::FrameIndex: case ISD::TargetFrameIndex: + case ISD::CopyFromReg: return true; case ISD::UNDEF: diff --git a/llvm/test/CodeGen/AArch64/combine-mul.ll b/llvm/test/CodeGen/AArch64/combine-mul.ll index a2b042530809..c49e5ae6620a 100644 --- a/llvm/test/CodeGen/AArch64/combine-mul.ll +++ b/llvm/test/CodeGen/AArch64/combine-mul.ll @@ -44,8 +44,7 @@ define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) { define i64 @combine_mul_self_demandedbits(i64 %x) { ; CHECK-LABEL: combine_mul_self_demandedbits: ; CHECK: // %bb.0: -; CHECK-NEXT: mul x8, x0, x0 -; CHECK-NEXT: and x0, x8, #0xfffffffffffffffd +; CHECK-NEXT: mul x0, x0, x0 ; CHECK-NEXT: ret %1 = mul i64 %x, %x %2 = and i64 %1, -3 @@ -77,7 +76,7 @@ define i8 @one_demanded_bit(i8 %x) { define <2 x i64> @one_demanded_bit_splat(<2 x i64> %x) { ; CHECK-LABEL: one_demanded_bit_splat: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #32 +; CHECK-NEXT: mov w8, #32 // =0x20 ; CHECK-NEXT: shl v0.2d, v0.2d, #5 ; CHECK-NEXT: dup v1.2d, x8 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b @@ -131,7 +130,7 @@ define i32 @squared_demanded_2_low_bits(i32 %x) { define <2 x i64> @squared_demanded_2_low_bits_splat(<2 x i64> %x) { ; CHECK-LABEL: squared_demanded_2_low_bits_splat: ; CHECK: // %bb.0: -; CHECK-NEXT: mov x8, #-2 +; CHECK-NEXT: mov x8, #-2 // =0xfffffffffffffffe ; CHECK-NEXT: dup v1.2d, x8 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll index 6629d3440549..25106b456d2f 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll @@ -123,10 +123,9 @@ define void @insert_32xi8_idx(ptr %src, ptr %dst, i8 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 0 -; CHECK-NEXT: st.b $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 0 +; CHECK-NEXT: st.b $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -150,10 +149,9 @@ define void @insert_16xi16_idx(ptr %src, ptr %dst, i16 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 1 -; CHECK-NEXT: st.h $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 1 +; CHECK-NEXT: st.h $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -177,10 +175,9 @@ define void @insert_8xi32_idx(ptr %src, ptr %dst, i32 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 2 -; CHECK-NEXT: st.w $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 2 +; CHECK-NEXT: st.w $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -204,10 +201,9 @@ define void @insert_4xi64_idx(ptr %src, ptr %dst, i64 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 3 -; CHECK-NEXT: st.d $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 3 +; CHECK-NEXT: st.d $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -231,10 +227,9 @@ define void @insert_8xfloat_idx(ptr %src, ptr %dst, float %in, i32 %idx) nounwin ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr1, $a0, 0 ; CHECK-NEXT: xvst $xr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 4, 2 -; CHECK-NEXT: fst.s $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 4, 2 +; CHECK-NEXT: fst.s $fa0, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -258,10 +253,9 @@ define void @insert_4xdouble_idx(ptr %src, ptr %dst, double %in, i32 %idx) nounw ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr1, $a0, 0 ; CHECK-NEXT: xvst $xr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 4, 3 -; CHECK-NEXT: fst.d $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 4, 3 +; CHECK-NEXT: fst.d $fa0, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll index 19171b7d8ed7..7f232073ae12 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll @@ -87,10 +87,9 @@ define void @insert_16xi8_idx(ptr %src, ptr %dst, i8 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 0 -; CHECK-NEXT: st.b $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 0 +; CHECK-NEXT: st.b $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -107,10 +106,9 @@ define void @insert_8xi16_idx(ptr %src, ptr %dst, i16 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 1 -; CHECK-NEXT: st.h $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 1 +; CHECK-NEXT: st.h $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -127,10 +125,9 @@ define void @insert_4xi32_idx(ptr %src, ptr %dst, i32 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 2 -; CHECK-NEXT: st.w $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 2 +; CHECK-NEXT: st.w $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -147,10 +144,9 @@ define void @insert_2xi64_idx(ptr %src, ptr %dst, i64 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 3 -; CHECK-NEXT: st.d $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 3 +; CHECK-NEXT: st.d $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -167,10 +163,9 @@ define void @insert_4xfloat_idx(ptr %src, ptr %dst, float %ins, i32 %idx) nounwi ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr1, $a0, 0 ; CHECK-NEXT: vst $vr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 3, 2 -; CHECK-NEXT: fst.s $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 3, 2 +; CHECK-NEXT: fst.s $fa0, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -187,10 +182,9 @@ define void @insert_2xdouble_idx(ptr %src, ptr %dst, double %ins, i32 %idx) noun ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr1, $a0, 0 ; CHECK-NEXT: vst $vr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 3, 3 -; CHECK-NEXT: fst.d $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 3, 3 +; CHECK-NEXT: fst.d $fa0, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll index d2ee80e6aa95..f032756e007b 100644 --- a/llvm/test/CodeGen/RISCV/alu64.ll +++ b/llvm/test/CodeGen/RISCV/alu64.ll @@ -57,8 +57,8 @@ define i64 @sltiu(i64 %a) nounwind { ; ; RV32I-LABEL: sltiu: ; RV32I: # %bb.0: -; RV32I-NEXT: seqz a1, a1 ; RV32I-NEXT: sltiu a0, a0, 3 +; RV32I-NEXT: seqz a1, a1 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll index f96e1bad2e38..a5a2ae79966c 100644 --- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll @@ -372,10 +372,10 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; RV32IA-NEXT: # =>This Loop Header: Depth=1 ; RV32IA-NEXT: # Child Loop BB2_3 Depth 2 ; RV32IA-NEXT: mv a3, a2 -; RV32IA-NEXT: addi a4, a2, 1 -; RV32IA-NEXT: sltu a2, a2, a1 -; RV32IA-NEXT: neg a2, a2 -; RV32IA-NEXT: and a4, a2, a4 +; RV32IA-NEXT: addi a2, a2, 1 +; RV32IA-NEXT: sltu a4, a3, a1 +; RV32IA-NEXT: neg a4, a4 +; RV32IA-NEXT: and a4, a4, a2 ; RV32IA-NEXT: .LBB2_3: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 @@ -607,10 +607,10 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; RV64IA-NEXT: # =>This Loop Header: Depth=1 ; RV64IA-NEXT: # Child Loop BB3_3 Depth 2 ; RV64IA-NEXT: mv a3, a2 -; RV64IA-NEXT: addi a4, a2, 1 -; RV64IA-NEXT: sltu a2, a2, a1 -; RV64IA-NEXT: neg a2, a2 -; RV64IA-NEXT: and a4, a2, a4 +; RV64IA-NEXT: addi a2, a2, 1 +; RV64IA-NEXT: sltu a4, a3, a1 +; RV64IA-NEXT: neg a4, a4 +; RV64IA-NEXT: and a4, a4, a2 ; RV64IA-NEXT: .LBB3_3: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll index 9e2b0b5c3cbb..770dcccee882 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-convert.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-convert.ll @@ -456,92 +456,80 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind { define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind { ; RV32IZFBFMIN-LABEL: fcvt_l_bf16_sat: ; RV32IZFBFMIN: # %bb.0: # %start -; RV32IZFBFMIN-NEXT: addi sp, sp, -32 -; RV32IZFBFMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) +; RV32IZFBFMIN-NEXT: addi sp, sp, -16 +; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0 -; RV32IZFBFMIN-NEXT: flt.s s0, fa5, fs0 -; RV32IZFBFMIN-NEXT: neg s1, s0 ; RV32IZFBFMIN-NEXT: lui a0, 913408 ; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFBFMIN-NEXT: fle.s s2, fa5, fs0 -; RV32IZFBFMIN-NEXT: neg s3, s2 +; RV32IZFBFMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFBFMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFBFMIN-NEXT: call __fixsfdi -; RV32IZFBFMIN-NEXT: and a0, s3, a0 -; RV32IZFBFMIN-NEXT: or a0, s1, a0 -; RV32IZFBFMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFBFMIN-NEXT: neg a2, a2 ; RV32IZFBFMIN-NEXT: lui a4, 524288 -; RV32IZFBFMIN-NEXT: lui a3, 524288 -; RV32IZFBFMIN-NEXT: beqz s2, .LBB10_2 +; RV32IZFBFMIN-NEXT: lui a2, 524288 +; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_2 ; RV32IZFBFMIN-NEXT: # %bb.1: # %start -; RV32IZFBFMIN-NEXT: mv a3, a1 +; RV32IZFBFMIN-NEXT: mv a2, a1 ; RV32IZFBFMIN-NEXT: .LBB10_2: # %start -; RV32IZFBFMIN-NEXT: and a0, a2, a0 -; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_4 +; RV32IZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IZFBFMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFBFMIN-NEXT: beqz a3, .LBB10_4 ; RV32IZFBFMIN-NEXT: # %bb.3: -; RV32IZFBFMIN-NEXT: addi a3, a4, -1 +; RV32IZFBFMIN-NEXT: addi a2, a4, -1 ; RV32IZFBFMIN-NEXT: .LBB10_4: # %start -; RV32IZFBFMIN-NEXT: and a1, a2, a3 -; RV32IZFBFMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: addi sp, sp, 32 +; RV32IZFBFMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFBFMIN-NEXT: neg a4, a1 +; RV32IZFBFMIN-NEXT: and a1, a4, a2 +; RV32IZFBFMIN-NEXT: neg a2, a3 +; RV32IZFBFMIN-NEXT: neg a3, s0 +; RV32IZFBFMIN-NEXT: and a0, a3, a0 +; RV32IZFBFMIN-NEXT: or a0, a2, a0 +; RV32IZFBFMIN-NEXT: and a0, a4, a0 +; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: addi sp, sp, 16 ; RV32IZFBFMIN-NEXT: ret ; ; R32IDZFBFMIN-LABEL: fcvt_l_bf16_sat: ; R32IDZFBFMIN: # %bb.0: # %start -; R32IDZFBFMIN-NEXT: addi sp, sp, -32 -; R32IDZFBFMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: addi sp, sp, -16 +; R32IDZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; R32IDZFBFMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; R32IDZFBFMIN-NEXT: lui a0, %hi(.LCPI10_0) -; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0 -; R32IDZFBFMIN-NEXT: flt.s s0, fa5, fs0 -; R32IDZFBFMIN-NEXT: neg s1, s0 ; R32IDZFBFMIN-NEXT: lui a0, 913408 ; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a0 -; R32IDZFBFMIN-NEXT: fle.s s2, fa5, fs0 -; R32IDZFBFMIN-NEXT: neg s3, s2 +; R32IDZFBFMIN-NEXT: fle.s s0, fa5, fs0 ; R32IDZFBFMIN-NEXT: fmv.s fa0, fs0 ; R32IDZFBFMIN-NEXT: call __fixsfdi -; R32IDZFBFMIN-NEXT: and a0, s3, a0 -; R32IDZFBFMIN-NEXT: or a0, s1, a0 -; R32IDZFBFMIN-NEXT: feq.s a2, fs0, fs0 -; R32IDZFBFMIN-NEXT: neg a2, a2 ; R32IDZFBFMIN-NEXT: lui a4, 524288 -; R32IDZFBFMIN-NEXT: lui a3, 524288 -; R32IDZFBFMIN-NEXT: beqz s2, .LBB10_2 +; R32IDZFBFMIN-NEXT: lui a2, 524288 +; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_2 ; R32IDZFBFMIN-NEXT: # %bb.1: # %start -; R32IDZFBFMIN-NEXT: mv a3, a1 +; R32IDZFBFMIN-NEXT: mv a2, a1 ; R32IDZFBFMIN-NEXT: .LBB10_2: # %start -; R32IDZFBFMIN-NEXT: and a0, a2, a0 -; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_4 +; R32IDZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0) +; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; R32IDZFBFMIN-NEXT: flt.s a3, fa5, fs0 +; R32IDZFBFMIN-NEXT: beqz a3, .LBB10_4 ; R32IDZFBFMIN-NEXT: # %bb.3: -; R32IDZFBFMIN-NEXT: addi a3, a4, -1 +; R32IDZFBFMIN-NEXT: addi a2, a4, -1 ; R32IDZFBFMIN-NEXT: .LBB10_4: # %start -; R32IDZFBFMIN-NEXT: and a1, a2, a3 -; R32IDZFBFMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: feq.s a1, fs0, fs0 +; R32IDZFBFMIN-NEXT: neg a4, a1 +; R32IDZFBFMIN-NEXT: and a1, a4, a2 +; R32IDZFBFMIN-NEXT: neg a2, a3 +; R32IDZFBFMIN-NEXT: neg a3, s0 +; R32IDZFBFMIN-NEXT: and a0, a3, a0 +; R32IDZFBFMIN-NEXT: or a0, a2, a0 +; R32IDZFBFMIN-NEXT: and a0, a4, a0 +; R32IDZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; R32IDZFBFMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; R32IDZFBFMIN-NEXT: addi sp, sp, 32 +; R32IDZFBFMIN-NEXT: addi sp, sp, 16 ; R32IDZFBFMIN-NEXT: ret ; ; RV32ID-LABEL: fcvt_l_bf16_sat: diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll index c147d6ec6d9b..6024a29da33d 100644 --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -692,28 +692,27 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB12_2 +; RV32IFD-NEXT: beqz s0, .LBB12_2 ; RV32IFD-NEXT: # %bb.1: # %start ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB12_2: # %start ; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB12_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB12_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB12_4: # %start ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -790,33 +789,32 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lui a3, 278016 +; RV32I-NEXT: addi a3, a3, -1 +; RV32I-NEXT: li a2, -1 +; RV32I-NEXT: call __gtdf2 +; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 802304 +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: mv s2, a0 +; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: call __fixdfdi -; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: mv s4, a1 -; RV32I-NEXT: lui s6, 524288 -; RV32I-NEXT: bgez s2, .LBB12_2 +; RV32I-NEXT: mv s4, a0 +; RV32I-NEXT: mv s5, a1 +; RV32I-NEXT: lui a0, 524288 +; RV32I-NEXT: bgez s3, .LBB12_2 ; RV32I-NEXT: # %bb.1: # %start -; RV32I-NEXT: lui s4, 524288 +; RV32I-NEXT: lui s5, 524288 ; RV32I-NEXT: .LBB12_2: # %start -; RV32I-NEXT: lui a3, 278016 -; RV32I-NEXT: addi a3, a3, -1 -; RV32I-NEXT: li a2, -1 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __gtdf2 -; RV32I-NEXT: mv s5, a0 -; RV32I-NEXT: blez a0, .LBB12_4 +; RV32I-NEXT: blez s2, .LBB12_4 ; RV32I-NEXT: # %bb.3: # %start -; RV32I-NEXT: addi s4, s6, -1 +; RV32I-NEXT: addi s5, a0, -1 ; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 @@ -825,11 +823,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 -; RV32I-NEXT: and a1, a0, s4 -; RV32I-NEXT: slti a2, s2, 0 +; RV32I-NEXT: and a1, a0, s5 +; RV32I-NEXT: slti a2, s3, 0 ; RV32I-NEXT: addi a2, a2, -1 -; RV32I-NEXT: and a2, a2, s3 -; RV32I-NEXT: sgtz a3, s5 +; RV32I-NEXT: and a2, a2, s4 +; RV32I-NEXT: sgtz a3, s2 ; RV32I-NEXT: neg a3, a3 ; RV32I-NEXT: or a2, a3, a2 ; RV32I-NEXT: and a0, a0, a2 @@ -840,7 +838,6 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; @@ -949,22 +946,23 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: lui a0, %hi(.LCPI14_0) -; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a0) -; RV32IFD-NEXT: flt.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s0, a0 +; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill +; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s1, a0 +; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: call __fixunsdfdi -; RV32IFD-NEXT: and a0, s1, a0 -; RV32IFD-NEXT: or a0, s0, a0 -; RV32IFD-NEXT: and a1, s1, a1 -; RV32IFD-NEXT: or a1, s0, a1 +; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0) +; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2) +; RV32IFD-NEXT: and a0, s0, a0 +; RV32IFD-NEXT: flt.d a2, fa5, fs0 +; RV32IFD-NEXT: neg a2, a2 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a1, s0, a1 +; RV32IFD-NEXT: or a1, a2, a1 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; @@ -983,27 +981,24 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: mv s0, a0 -; RV32IZFINXZDINX-NEXT: fle.d a0, a2, s0 -; RV32IZFINXZDINX-NEXT: neg s2, a0 -; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI14_0) -; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI14_0+4)(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI14_0)(a2) -; RV32IZFINXZDINX-NEXT: and a0, s2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero +; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0) +; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a4) +; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, s2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a2, a1 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: neg a3, a3 +; RV32IZFINXZDINX-NEXT: or a0, a3, a0 +; RV32IZFINXZDINX-NEXT: and a1, a2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a3, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll index f1c56b320b76..927eee2e9e54 100644 --- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll @@ -53,28 +53,27 @@ define i64 @test_floor_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB1_2 +; RV32IFD-NEXT: beqz s0, .LBB1_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB1_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI1_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB1_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB1_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB1_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -299,28 +298,27 @@ define i64 @test_ceil_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB5_2 +; RV32IFD-NEXT: beqz s0, .LBB5_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB5_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI5_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB5_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB5_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB5_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -545,28 +543,27 @@ define i64 @test_trunc_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB9_2 +; RV32IFD-NEXT: beqz s0, .LBB9_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB9_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI9_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB9_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB9_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB9_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -791,28 +788,27 @@ define i64 @test_round_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB13_2 +; RV32IFD-NEXT: beqz s0, .LBB13_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB13_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI13_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB13_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB13_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB13_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -1037,28 +1033,27 @@ define i64 @test_roundeven_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB17_2 +; RV32IFD-NEXT: beqz s0, .LBB17_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB17_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI17_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB17_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB17_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB17_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -1283,28 +1278,27 @@ define i64 @test_rint_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB21_2 +; RV32IFD-NEXT: beqz s0, .LBB21_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB21_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI21_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI21_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB21_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB21_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB21_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll index 653b64ec7304..7eabd3f5f227 100644 --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -275,26 +275,24 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a1, 325632 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi -; RV32I-NEXT: and a0, s2, a0 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: and s1, s1, a0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg a0, a0 +; RV32I-NEXT: or a0, a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; @@ -618,38 +616,36 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fa0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI12_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB12_2 ; RV32IF-NEXT: # %bb.1: # %start -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB12_2: # %start -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI12_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB12_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB12_4: # %start -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -867,22 +863,23 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: lui a0, %hi(.LCPI14_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a0) -; RV32IF-NEXT: flt.s a0, fa5, fa0 -; RV32IF-NEXT: neg s0, a0 +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: fle.s a0, fa5, fa0 -; RV32IF-NEXT: neg s1, a0 +; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: call __fixunssfdi -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: or a0, s0, a0 -; RV32IF-NEXT: and a1, s1, a1 -; RV32IF-NEXT: or a1, s0, a1 +; RV32IF-NEXT: lui a2, %hi(.LCPI14_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2) +; RV32IF-NEXT: and a0, s0, a0 +; RV32IF-NEXT: flt.s a2, fa5, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a1, s0, a1 +; RV32IF-NEXT: or a1, a2, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -901,17 +898,19 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: lui a1, %hi(.LCPI14_0) -; RV32IZFINX-NEXT: lw a1, %lo(.LCPI14_0)(a1) -; RV32IZFINX-NEXT: flt.s a1, a1, a0 -; RV32IZFINX-NEXT: neg s0, a1 -; RV32IZFINX-NEXT: fle.s a1, zero, a0 -; RV32IZFINX-NEXT: neg s1, a1 +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s a0, zero, a0 +; RV32IZFINX-NEXT: neg s1, a0 +; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi +; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0) +; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 -; RV32IZFINX-NEXT: or a0, s0, a0 +; RV32IZFINX-NEXT: flt.s a2, a2, s0 +; RV32IZFINX-NEXT: neg a2, a2 +; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: and a1, s1, a1 -; RV32IZFINX-NEXT: or a1, s0, a1 +; RV32IZFINX-NEXT: or a1, a2, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -929,33 +928,36 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; ; RV32I-LABEL: fcvt_lu_s_sat: ; RV32I: # %bb.0: # %start -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi sp, sp, -32 +; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a1, 391168 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfdi -; RV32I-NEXT: and a0, s2, a0 -; RV32I-NEXT: or a0, s1, a0 -; RV32I-NEXT: and a1, s2, a1 -; RV32I-NEXT: or a1, s1, a1 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: and s3, s2, a0 +; RV32I-NEXT: lui a1, 391168 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: or a0, a1, s3 +; RV32I-NEXT: and a2, s2, s1 +; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fcvt_lu_s_sat: @@ -2089,26 +2091,24 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a1, 325632 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi -; RV32I-NEXT: and a0, s2, a0 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: and s1, s1, a0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg a0, a0 +; RV32I-NEXT: or a0, a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll index 4f747c278da0..5e99c7eb9056 100644 --- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll @@ -37,8 +37,7 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -53,33 +52,32 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB1_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB1_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI1_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB1_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB1_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -117,23 +115,23 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB1_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB1_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB1_6 +; RV32IZFINX-NEXT: beqz a4, .LBB1_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB1_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -299,8 +297,7 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -315,33 +312,32 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI5_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB5_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB5_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI5_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB5_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB5_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -379,23 +375,23 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB5_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB5_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB5_6 +; RV32IZFINX-NEXT: beqz a4, .LBB5_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB5_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -561,8 +557,7 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -577,33 +572,32 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI9_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB9_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB9_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI9_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB9_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB9_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -641,23 +635,23 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB9_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB9_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB9_6 +; RV32IZFINX-NEXT: beqz a4, .LBB9_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB9_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -823,8 +817,7 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -839,33 +832,32 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI13_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB13_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB13_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI13_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB13_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB13_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -903,23 +895,23 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB13_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB13_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB13_6 +; RV32IZFINX-NEXT: beqz a4, .LBB13_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB13_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1085,8 +1077,7 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -1101,33 +1092,32 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI17_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB17_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB17_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI17_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB17_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB17_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1165,23 +1155,23 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB17_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB17_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB17_6 +; RV32IZFINX-NEXT: beqz a4, .LBB17_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB17_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1347,8 +1337,7 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -1363,33 +1352,32 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI21_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI21_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB21_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB21_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI21_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI21_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB21_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB21_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1427,23 +1415,23 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB21_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB21_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB21_6 +; RV32IZFINX-NEXT: beqz a4, .LBB21_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB21_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll index c303690aadff..f6a53a9d76dd 100644 --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -3567,8 +3567,8 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV32-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32-NEXT: neg a3, a0 ; RV32-NEXT: and a3, a3, a1 -; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: sw a4, 0(sp) +; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 @@ -3659,8 +3659,8 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind { ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32-NEXT: neg a3, a0 ; RV32-NEXT: and a3, a3, a1 -; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: sw a4, 0(sp) +; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll index 06ab813faf02..deb5a6d4013d 100644 --- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll +++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll @@ -114,8 +114,8 @@ define i32 @utest_f64i32(double %x) { ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 ; RV32IF-NEXT: call __fixunsdfdi -; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: sltiu a2, a0, -1 +; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: and a1, a1, a2 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: or a0, a1, a0 @@ -429,8 +429,8 @@ define i32 @utesth_f16i32(half %x) { ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: call __fixunssfdi -; RV32-NEXT: seqz a1, a1 ; RV32-NEXT: sltiu a2, a0, -1 +; RV32-NEXT: seqz a1, a1 ; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: or a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index 277749c75bbb..31fb6e2ee9c8 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -2145,47 +2145,41 @@ define i64 @fcvt_l_h(half %a) nounwind { define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IZFH-LABEL: fcvt_l_h_sat: ; RV32IZFH: # %bb.0: # %start -; RV32IZFH-NEXT: addi sp, sp, -32 -; RV32IZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a0) +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IZFH-NEXT: flt.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s2, fa5, fs0 -; RV32IZFH-NEXT: neg s3, s2 +; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: and a0, s3, a0 -; RV32IZFH-NEXT: or a0, s1, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a3, 524288 -; RV32IZFH-NEXT: beqz s2, .LBB10_2 +; RV32IZFH-NEXT: lui a2, 524288 +; RV32IZFH-NEXT: beqz s0, .LBB10_2 ; RV32IZFH-NEXT: # %bb.1: # %start -; RV32IZFH-NEXT: mv a3, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB10_2: # %start -; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: beqz s0, .LBB10_4 +; RV32IZFH-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB10_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: addi a3, a4, -1 +; RV32IZFH-NEXT: addi a2, a4, -1 ; RV32IZFH-NEXT: .LBB10_4: # %start -; RV32IZFH-NEXT: and a1, a2, a3 -; RV32IZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 32 +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: neg a3, s0 +; RV32IZFH-NEXT: and a0, a3, a0 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_l_h_sat: @@ -2199,47 +2193,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IDZFH-LABEL: fcvt_l_h_sat: ; RV32IDZFH: # %bb.0: # %start -; RV32IDZFH-NEXT: addi sp, sp, -32 -; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: addi sp, sp, -16 +; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IDZFH-NEXT: flt.s s0, fa5, fs0 -; RV32IDZFH-NEXT: neg s1, s0 ; RV32IDZFH-NEXT: lui a0, 913408 ; RV32IDZFH-NEXT: fmv.w.x fa5, a0 -; RV32IDZFH-NEXT: fle.s s2, fa5, fs0 -; RV32IDZFH-NEXT: neg s3, s2 +; RV32IDZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: call __fixsfdi -; RV32IDZFH-NEXT: and a0, s3, a0 -; RV32IDZFH-NEXT: or a0, s1, a0 -; RV32IDZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IDZFH-NEXT: neg a2, a2 ; RV32IDZFH-NEXT: lui a4, 524288 -; RV32IDZFH-NEXT: lui a3, 524288 -; RV32IDZFH-NEXT: beqz s2, .LBB10_2 +; RV32IDZFH-NEXT: lui a2, 524288 +; RV32IDZFH-NEXT: beqz s0, .LBB10_2 ; RV32IDZFH-NEXT: # %bb.1: # %start -; RV32IDZFH-NEXT: mv a3, a1 +; RV32IDZFH-NEXT: mv a2, a1 ; RV32IDZFH-NEXT: .LBB10_2: # %start -; RV32IDZFH-NEXT: and a0, a2, a0 -; RV32IDZFH-NEXT: beqz s0, .LBB10_4 +; RV32IDZFH-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IDZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IDZFH-NEXT: beqz a3, .LBB10_4 ; RV32IDZFH-NEXT: # %bb.3: -; RV32IDZFH-NEXT: addi a3, a4, -1 +; RV32IDZFH-NEXT: addi a2, a4, -1 ; RV32IDZFH-NEXT: .LBB10_4: # %start -; RV32IDZFH-NEXT: and a1, a2, a3 -; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IDZFH-NEXT: neg a4, a1 +; RV32IDZFH-NEXT: and a1, a4, a2 +; RV32IDZFH-NEXT: neg a2, a3 +; RV32IDZFH-NEXT: neg a3, s0 +; RV32IDZFH-NEXT: and a0, a3, a0 +; RV32IDZFH-NEXT: or a0, a2, a0 +; RV32IDZFH-NEXT: and a0, a4, a0 +; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 32 +; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_l_h_sat: @@ -2515,47 +2503,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32ID-LABEL: fcvt_l_h_sat: ; RV32ID: # %bb.0: # %start -; RV32ID-NEXT: addi sp, sp, -32 -; RV32ID-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32ID-NEXT: addi sp, sp, -16 +; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32ID-NEXT: call __extendhfsf2 -; RV32ID-NEXT: lui a0, %hi(.LCPI10_0) -; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32ID-NEXT: fmv.s fs0, fa0 -; RV32ID-NEXT: flt.s s0, fa5, fa0 -; RV32ID-NEXT: neg s1, s0 ; RV32ID-NEXT: lui a0, 913408 ; RV32ID-NEXT: fmv.w.x fa5, a0 -; RV32ID-NEXT: fle.s s2, fa5, fa0 -; RV32ID-NEXT: neg s3, s2 +; RV32ID-NEXT: fle.s s0, fa5, fa0 ; RV32ID-NEXT: call __fixsfdi -; RV32ID-NEXT: and a0, s3, a0 -; RV32ID-NEXT: or a0, s1, a0 -; RV32ID-NEXT: feq.s a2, fs0, fs0 -; RV32ID-NEXT: neg a2, a2 ; RV32ID-NEXT: lui a4, 524288 -; RV32ID-NEXT: lui a3, 524288 -; RV32ID-NEXT: beqz s2, .LBB10_2 +; RV32ID-NEXT: lui a2, 524288 +; RV32ID-NEXT: beqz s0, .LBB10_2 ; RV32ID-NEXT: # %bb.1: # %start -; RV32ID-NEXT: mv a3, a1 +; RV32ID-NEXT: mv a2, a1 ; RV32ID-NEXT: .LBB10_2: # %start -; RV32ID-NEXT: and a0, a2, a0 -; RV32ID-NEXT: beqz s0, .LBB10_4 +; RV32ID-NEXT: lui a1, %hi(.LCPI10_0) +; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32ID-NEXT: flt.s a3, fa5, fs0 +; RV32ID-NEXT: beqz a3, .LBB10_4 ; RV32ID-NEXT: # %bb.3: -; RV32ID-NEXT: addi a3, a4, -1 +; RV32ID-NEXT: addi a2, a4, -1 ; RV32ID-NEXT: .LBB10_4: # %start -; RV32ID-NEXT: and a1, a2, a3 -; RV32ID-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32ID-NEXT: feq.s a1, fs0, fs0 +; RV32ID-NEXT: neg a4, a1 +; RV32ID-NEXT: and a1, a4, a2 +; RV32ID-NEXT: neg a2, s0 +; RV32ID-NEXT: and a0, a2, a0 +; RV32ID-NEXT: neg a2, a3 +; RV32ID-NEXT: or a0, a2, a0 +; RV32ID-NEXT: and a0, a4, a0 +; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32ID-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32ID-NEXT: addi sp, sp, 32 +; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: ret ; ; RV64ID-LABEL: fcvt_l_h_sat: @@ -2574,47 +2556,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IFZFHMIN-LABEL: fcvt_l_h_sat: ; RV32IFZFHMIN: # %bb.0: # %start -; RV32IFZFHMIN-NEXT: addi sp, sp, -32 -; RV32IFZFHMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) +; RV32IFZFHMIN-NEXT: addi sp, sp, -16 +; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0 -; RV32IFZFHMIN-NEXT: flt.s s0, fa5, fs0 -; RV32IFZFHMIN-NEXT: neg s1, s0 ; RV32IFZFHMIN-NEXT: lui a0, 913408 ; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IFZFHMIN-NEXT: fle.s s2, fa5, fs0 -; RV32IFZFHMIN-NEXT: neg s3, s2 +; RV32IFZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IFZFHMIN-NEXT: call __fixsfdi -; RV32IFZFHMIN-NEXT: and a0, s3, a0 -; RV32IFZFHMIN-NEXT: or a0, s1, a0 -; RV32IFZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IFZFHMIN-NEXT: neg a2, a2 ; RV32IFZFHMIN-NEXT: lui a4, 524288 -; RV32IFZFHMIN-NEXT: lui a3, 524288 -; RV32IFZFHMIN-NEXT: beqz s2, .LBB10_2 +; RV32IFZFHMIN-NEXT: lui a2, 524288 +; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_2 ; RV32IFZFHMIN-NEXT: # %bb.1: # %start -; RV32IFZFHMIN-NEXT: mv a3, a1 +; RV32IFZFHMIN-NEXT: mv a2, a1 ; RV32IFZFHMIN-NEXT: .LBB10_2: # %start -; RV32IFZFHMIN-NEXT: and a0, a2, a0 -; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_4 +; RV32IFZFHMIN-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IFZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IFZFHMIN-NEXT: beqz a3, .LBB10_4 ; RV32IFZFHMIN-NEXT: # %bb.3: -; RV32IFZFHMIN-NEXT: addi a3, a4, -1 +; RV32IFZFHMIN-NEXT: addi a2, a4, -1 ; RV32IFZFHMIN-NEXT: .LBB10_4: # %start -; RV32IFZFHMIN-NEXT: and a1, a2, a3 -; RV32IFZFHMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: addi sp, sp, 32 +; RV32IFZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IFZFHMIN-NEXT: neg a4, a1 +; RV32IFZFHMIN-NEXT: and a1, a4, a2 +; RV32IFZFHMIN-NEXT: neg a2, a3 +; RV32IFZFHMIN-NEXT: neg a3, s0 +; RV32IFZFHMIN-NEXT: and a0, a3, a0 +; RV32IFZFHMIN-NEXT: or a0, a2, a0 +; RV32IFZFHMIN-NEXT: and a0, a4, a0 +; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFZFHMIN-NEXT: ret ; ; CHECK64-IZFHMIN-LABEL: fcvt_l_h_sat: @@ -2629,47 +2605,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IDZFHMIN-LABEL: fcvt_l_h_sat: ; RV32IDZFHMIN: # %bb.0: # %start -; RV32IDZFHMIN-NEXT: addi sp, sp, -32 -; RV32IDZFHMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: addi sp, sp, -16 +; RV32IDZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFHMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IDZFHMIN-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0 -; RV32IDZFHMIN-NEXT: flt.s s0, fa5, fs0 -; RV32IDZFHMIN-NEXT: neg s1, s0 ; RV32IDZFHMIN-NEXT: lui a0, 913408 ; RV32IDZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IDZFHMIN-NEXT: fle.s s2, fa5, fs0 -; RV32IDZFHMIN-NEXT: neg s3, s2 +; RV32IDZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IDZFHMIN-NEXT: call __fixsfdi -; RV32IDZFHMIN-NEXT: and a0, s3, a0 -; RV32IDZFHMIN-NEXT: or a0, s1, a0 -; RV32IDZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IDZFHMIN-NEXT: neg a2, a2 ; RV32IDZFHMIN-NEXT: lui a4, 524288 -; RV32IDZFHMIN-NEXT: lui a3, 524288 -; RV32IDZFHMIN-NEXT: beqz s2, .LBB10_2 +; RV32IDZFHMIN-NEXT: lui a2, 524288 +; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_2 ; RV32IDZFHMIN-NEXT: # %bb.1: # %start -; RV32IDZFHMIN-NEXT: mv a3, a1 +; RV32IDZFHMIN-NEXT: mv a2, a1 ; RV32IDZFHMIN-NEXT: .LBB10_2: # %start -; RV32IDZFHMIN-NEXT: and a0, a2, a0 -; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_4 +; RV32IDZFHMIN-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IDZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IDZFHMIN-NEXT: beqz a3, .LBB10_4 ; RV32IDZFHMIN-NEXT: # %bb.3: -; RV32IDZFHMIN-NEXT: addi a3, a4, -1 +; RV32IDZFHMIN-NEXT: addi a2, a4, -1 ; RV32IDZFHMIN-NEXT: .LBB10_4: # %start -; RV32IDZFHMIN-NEXT: and a1, a2, a3 -; RV32IDZFHMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IDZFHMIN-NEXT: neg a4, a1 +; RV32IDZFHMIN-NEXT: and a1, a4, a2 +; RV32IDZFHMIN-NEXT: neg a2, a3 +; RV32IDZFHMIN-NEXT: neg a3, s0 +; RV32IDZFHMIN-NEXT: and a0, a3, a0 +; RV32IDZFHMIN-NEXT: or a0, a2, a0 +; RV32IDZFHMIN-NEXT: and a0, a4, a0 +; RV32IDZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IDZFHMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32IDZFHMIN-NEXT: addi sp, sp, 32 +; RV32IDZFHMIN-NEXT: addi sp, sp, 16 ; RV32IDZFHMIN-NEXT: ret ; ; CHECK32-IZHINXMIN-LABEL: fcvt_l_h_sat: diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll index 9c95210bfa7c..04a8a66f4459 100644 --- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll @@ -108,40 +108,38 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI1_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB1_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB1_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI1_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB1_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB1_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB1_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB1_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_floor_si64: @@ -179,16 +177,16 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB1_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB1_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -196,11 +194,11 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB1_6 +; RV32IZHINX-NEXT: beqz a4, .LBB1_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB1_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_floor_si64: @@ -238,41 +236,39 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB1_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI1_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB1_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB1_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_floor_si64: @@ -324,16 +320,16 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB1_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB1_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -341,11 +337,11 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB1_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB1_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB1_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_floor_si64: @@ -824,40 +820,38 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI5_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB5_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB5_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI5_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB5_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB5_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB5_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB5_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_ceil_si64: @@ -895,16 +889,16 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI5_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI5_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB5_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB5_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -912,11 +906,11 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB5_6 +; RV32IZHINX-NEXT: beqz a4, .LBB5_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB5_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_ceil_si64: @@ -954,41 +948,39 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI5_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB5_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI5_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB5_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB5_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_ceil_si64: @@ -1040,16 +1032,16 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB5_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB5_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1057,11 +1049,11 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB5_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB5_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB5_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_ceil_si64: @@ -1540,40 +1532,38 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI9_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB9_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB9_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI9_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB9_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB9_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB9_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB9_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_trunc_si64: @@ -1611,16 +1601,16 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI9_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI9_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB9_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB9_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1628,11 +1618,11 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB9_6 +; RV32IZHINX-NEXT: beqz a4, .LBB9_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB9_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_trunc_si64: @@ -1670,41 +1660,39 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI9_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB9_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI9_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB9_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB9_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_trunc_si64: @@ -1756,16 +1744,16 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB9_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB9_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1773,11 +1761,11 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB9_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB9_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB9_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_trunc_si64: @@ -2256,40 +2244,38 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI13_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB13_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB13_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI13_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB13_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB13_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB13_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB13_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_round_si64: @@ -2327,16 +2313,16 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI13_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI13_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB13_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB13_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2344,11 +2330,11 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB13_6 +; RV32IZHINX-NEXT: beqz a4, .LBB13_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB13_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_round_si64: @@ -2386,41 +2372,39 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI13_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB13_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI13_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB13_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB13_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_round_si64: @@ -2472,16 +2456,16 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB13_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB13_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2489,11 +2473,11 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB13_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB13_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB13_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_round_si64: @@ -2972,40 +2956,38 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI17_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB17_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB17_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI17_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB17_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB17_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB17_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB17_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_roundeven_si64: @@ -3043,16 +3025,16 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI17_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI17_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB17_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB17_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3060,11 +3042,11 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB17_6 +; RV32IZHINX-NEXT: beqz a4, .LBB17_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB17_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_roundeven_si64: @@ -3102,41 +3084,39 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI17_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB17_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI17_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB17_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB17_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_roundeven_si64: @@ -3188,16 +3168,16 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB17_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB17_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3205,11 +3185,11 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB17_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB17_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB17_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_roundeven_si64: @@ -3688,40 +3668,38 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI21_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB21_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB21_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI21_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB21_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB21_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB21_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB21_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_rint_si64: @@ -3759,16 +3737,16 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI21_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI21_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB21_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB21_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3776,11 +3754,11 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB21_6 +; RV32IZHINX-NEXT: beqz a4, .LBB21_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB21_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_rint_si64: @@ -3818,41 +3796,39 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI21_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB21_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB21_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI21_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB21_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB21_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB21_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB21_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_rint_si64: @@ -3904,16 +3880,16 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB21_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB21_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3921,11 +3897,11 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB21_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB21_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB21_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_rint_si64: diff --git a/llvm/test/CodeGen/RISCV/iabs.ll b/llvm/test/CodeGen/RISCV/iabs.ll index 98c886333d69..a0c85ab4dca7 100644 --- a/llvm/test/CodeGen/RISCV/iabs.ll +++ b/llvm/test/CodeGen/RISCV/iabs.ll @@ -630,8 +630,8 @@ define void @zext16_abs8(i8 %x, ptr %p) { ; RV32I-LABEL: zext16_abs8: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a2, a0, 31 +; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: xor a0, a0, a2 ; RV32I-NEXT: sub a0, a0, a2 ; RV32I-NEXT: sh a0, 0(a1) @@ -648,8 +648,8 @@ define void @zext16_abs8(i8 %x, ptr %p) { ; RV64I-LABEL: zext16_abs8: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 56 -; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a2, a0, 63 +; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: xor a0, a0, a2 ; RV64I-NEXT: subw a0, a0, a2 ; RV64I-NEXT: sh a0, 0(a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll index b3bda5973eb8..a6b2d3141f22 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll @@ -2190,65 +2190,66 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.d fs0, fa0 -; CHECK-NOV-NEXT: fmv.d fa0, fa1 +; CHECK-NOV-NEXT: fmv.d fs0, fa1 ; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixdfti -; CHECK-NOV-NEXT: li a2, -1 -; CHECK-NOV-NEXT: srli a3, a2, 1 -; CHECK-NOV-NEXT: beqz s1, .LBB18_3 +; CHECK-NOV-NEXT: mv a2, a0 +; CHECK-NOV-NEXT: li a0, -1 +; CHECK-NOV-NEXT: srli a3, a0, 1 +; CHECK-NOV-NEXT: beqz a1, .LBB18_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 0 -; CHECK-NOV-NEXT: bnez a1, .LBB18_4 +; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: bnez s1, .LBB18_4 ; CHECK-NOV-NEXT: .LBB18_2: -; CHECK-NOV-NEXT: sltu a5, a0, a3 +; CHECK-NOV-NEXT: sltu a5, s0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB18_5 ; CHECK-NOV-NEXT: j .LBB18_6 ; CHECK-NOV-NEXT: .LBB18_3: -; CHECK-NOV-NEXT: sltu a4, s0, a3 -; CHECK-NOV-NEXT: beqz a1, .LBB18_2 +; CHECK-NOV-NEXT: sltu a4, a2, a3 +; CHECK-NOV-NEXT: beqz s1, .LBB18_2 ; CHECK-NOV-NEXT: .LBB18_4: # %entry -; CHECK-NOV-NEXT: slti a5, a1, 0 +; CHECK-NOV-NEXT: slti a5, s1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB18_6 ; CHECK-NOV-NEXT: .LBB18_5: # %entry -; CHECK-NOV-NEXT: mv a0, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB18_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, s1 +; CHECK-NOV-NEXT: and a5, a5, a1 ; CHECK-NOV-NEXT: bnez a4, .LBB18_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a2, a3 ; CHECK-NOV-NEXT: .LBB18_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, a1 -; CHECK-NOV-NEXT: slli a1, a2, 63 -; CHECK-NOV-NEXT: beq a5, a2, .LBB18_11 +; CHECK-NOV-NEXT: and a4, a6, s1 +; CHECK-NOV-NEXT: slli a1, a0, 63 +; CHECK-NOV-NEXT: beq a5, a0, .LBB18_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a2, .LBB18_12 +; CHECK-NOV-NEXT: bne a4, a0, .LBB18_12 ; CHECK-NOV-NEXT: .LBB18_10: -; CHECK-NOV-NEXT: sltu a2, a1, a0 -; CHECK-NOV-NEXT: beqz a2, .LBB18_13 +; CHECK-NOV-NEXT: sltu a0, a1, s0 +; CHECK-NOV-NEXT: beqz a0, .LBB18_13 ; CHECK-NOV-NEXT: j .LBB18_14 ; CHECK-NOV-NEXT: .LBB18_11: -; CHECK-NOV-NEXT: sltu a3, a1, s0 -; CHECK-NOV-NEXT: beq a4, a2, .LBB18_10 +; CHECK-NOV-NEXT: sltu a3, a1, a2 +; CHECK-NOV-NEXT: beq a4, a0, .LBB18_10 ; CHECK-NOV-NEXT: .LBB18_12: # %entry -; CHECK-NOV-NEXT: slti a2, a4, 0 -; CHECK-NOV-NEXT: xori a2, a2, 1 -; CHECK-NOV-NEXT: bnez a2, .LBB18_14 +; CHECK-NOV-NEXT: slti a0, a4, 0 +; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: bnez a0, .LBB18_14 ; CHECK-NOV-NEXT: .LBB18_13: # %entry -; CHECK-NOV-NEXT: mv a0, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB18_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB18_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: .LBB18_16: # %entry -; CHECK-NOV-NEXT: mv a1, s0 +; CHECK-NOV-NEXT: mv a0, s0 +; CHECK-NOV-NEXT: mv a1, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2273,43 +2274,43 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz s1, .LBB18_3 +; CHECK-V-NEXT: beqz a1, .LBB18_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, s1, 0 -; CHECK-V-NEXT: bnez a1, .LBB18_4 +; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: bnez s1, .LBB18_4 ; CHECK-V-NEXT: .LBB18_2: -; CHECK-V-NEXT: sltu a5, a0, a3 +; CHECK-V-NEXT: sltu a5, s0, a3 ; CHECK-V-NEXT: beqz a5, .LBB18_5 ; CHECK-V-NEXT: j .LBB18_6 ; CHECK-V-NEXT: .LBB18_3: -; CHECK-V-NEXT: sltu a4, s0, a3 -; CHECK-V-NEXT: beqz a1, .LBB18_2 +; CHECK-V-NEXT: sltu a4, a0, a3 +; CHECK-V-NEXT: beqz s1, .LBB18_2 ; CHECK-V-NEXT: .LBB18_4: # %entry -; CHECK-V-NEXT: slti a5, a1, 0 +; CHECK-V-NEXT: slti a5, s1, 0 ; CHECK-V-NEXT: bnez a5, .LBB18_6 ; CHECK-V-NEXT: .LBB18_5: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB18_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, s1 +; CHECK-V-NEXT: and a5, a5, a1 ; CHECK-V-NEXT: bnez a4, .LBB18_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB18_8: # %entry -; CHECK-V-NEXT: and a4, a6, a1 +; CHECK-V-NEXT: and a4, a6, s1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB18_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -2317,26 +2318,26 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB18_12 ; CHECK-V-NEXT: .LBB18_10: -; CHECK-V-NEXT: sltu a2, a1, a0 +; CHECK-V-NEXT: sltu a2, a1, s0 ; CHECK-V-NEXT: beqz a2, .LBB18_13 ; CHECK-V-NEXT: j .LBB18_14 ; CHECK-V-NEXT: .LBB18_11: -; CHECK-V-NEXT: sltu a3, a1, s0 +; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB18_10 ; CHECK-V-NEXT: .LBB18_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB18_14 ; CHECK-V-NEXT: .LBB18_13: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB18_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB18_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB18_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, s0 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, s0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2369,19 +2370,19 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.d fs0, fa0 -; CHECK-NOV-NEXT: fmv.d fa0, fa1 +; CHECK-NOV-NEXT: fmv.d fs0, fa1 ; CHECK-NOV-NEXT: call __fixunsdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixunsdfti -; CHECK-NOV-NEXT: snez a2, s1 ; CHECK-NOV-NEXT: snez a1, a1 +; CHECK-NOV-NEXT: snez a2, s1 +; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a2, a2, s0 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a0, a1, a0 -; CHECK-NOV-NEXT: addi a1, a2, -1 -; CHECK-NOV-NEXT: and a1, a1, s0 +; CHECK-NOV-NEXT: and a1, a1, a0 +; CHECK-NOV-NEXT: mv a0, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2406,25 +2407,25 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixunsdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunsdfti -; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: snez a1, a1 -; CHECK-V-NEXT: addi a1, a1, -1 -; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s0 +; CHECK-V-NEXT: addi a1, a1, -1 +; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a2 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2466,32 +2467,32 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB20_2: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: slti a3, a1, 1 +; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB20_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB20_4: # %entry +; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB20_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB20_8 ; CHECK-NOV-NEXT: .LBB20_6: -; CHECK-NOV-NEXT: snez a2, a0 +; CHECK-NOV-NEXT: snez a0, a4 ; CHECK-NOV-NEXT: j .LBB20_9 ; CHECK-NOV-NEXT: .LBB20_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB20_6 ; CHECK-NOV-NEXT: .LBB20_8: # %entry -; CHECK-NOV-NEXT: sgtz a2, a2 +; CHECK-NOV-NEXT: sgtz a0, a2 ; CHECK-NOV-NEXT: .LBB20_9: # %entry -; CHECK-NOV-NEXT: neg a2, a2 -; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: neg a0, a0 +; CHECK-NOV-NEXT: and a0, a0, a4 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -2533,15 +2534,15 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB20_2: # %entry -; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: slti a4, a1, 1 +; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: blez a1, .LBB20_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB20_4: # %entry +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB20_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -2596,65 +2597,66 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.s fs0, fa0 -; CHECK-NOV-NEXT: fmv.s fa0, fa1 +; CHECK-NOV-NEXT: fmv.s fs0, fa1 ; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: li a2, -1 -; CHECK-NOV-NEXT: srli a3, a2, 1 -; CHECK-NOV-NEXT: beqz s1, .LBB21_3 +; CHECK-NOV-NEXT: mv a2, a0 +; CHECK-NOV-NEXT: li a0, -1 +; CHECK-NOV-NEXT: srli a3, a0, 1 +; CHECK-NOV-NEXT: beqz a1, .LBB21_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 0 -; CHECK-NOV-NEXT: bnez a1, .LBB21_4 +; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: bnez s1, .LBB21_4 ; CHECK-NOV-NEXT: .LBB21_2: -; CHECK-NOV-NEXT: sltu a5, a0, a3 +; CHECK-NOV-NEXT: sltu a5, s0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB21_5 ; CHECK-NOV-NEXT: j .LBB21_6 ; CHECK-NOV-NEXT: .LBB21_3: -; CHECK-NOV-NEXT: sltu a4, s0, a3 -; CHECK-NOV-NEXT: beqz a1, .LBB21_2 +; CHECK-NOV-NEXT: sltu a4, a2, a3 +; CHECK-NOV-NEXT: beqz s1, .LBB21_2 ; CHECK-NOV-NEXT: .LBB21_4: # %entry -; CHECK-NOV-NEXT: slti a5, a1, 0 +; CHECK-NOV-NEXT: slti a5, s1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB21_6 ; CHECK-NOV-NEXT: .LBB21_5: # %entry -; CHECK-NOV-NEXT: mv a0, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB21_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, s1 +; CHECK-NOV-NEXT: and a5, a5, a1 ; CHECK-NOV-NEXT: bnez a4, .LBB21_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a2, a3 ; CHECK-NOV-NEXT: .LBB21_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, a1 -; CHECK-NOV-NEXT: slli a1, a2, 63 -; CHECK-NOV-NEXT: beq a5, a2, .LBB21_11 +; CHECK-NOV-NEXT: and a4, a6, s1 +; CHECK-NOV-NEXT: slli a1, a0, 63 +; CHECK-NOV-NEXT: beq a5, a0, .LBB21_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a2, .LBB21_12 +; CHECK-NOV-NEXT: bne a4, a0, .LBB21_12 ; CHECK-NOV-NEXT: .LBB21_10: -; CHECK-NOV-NEXT: sltu a2, a1, a0 -; CHECK-NOV-NEXT: beqz a2, .LBB21_13 +; CHECK-NOV-NEXT: sltu a0, a1, s0 +; CHECK-NOV-NEXT: beqz a0, .LBB21_13 ; CHECK-NOV-NEXT: j .LBB21_14 ; CHECK-NOV-NEXT: .LBB21_11: -; CHECK-NOV-NEXT: sltu a3, a1, s0 -; CHECK-NOV-NEXT: beq a4, a2, .LBB21_10 +; CHECK-NOV-NEXT: sltu a3, a1, a2 +; CHECK-NOV-NEXT: beq a4, a0, .LBB21_10 ; CHECK-NOV-NEXT: .LBB21_12: # %entry -; CHECK-NOV-NEXT: slti a2, a4, 0 -; CHECK-NOV-NEXT: xori a2, a2, 1 -; CHECK-NOV-NEXT: bnez a2, .LBB21_14 +; CHECK-NOV-NEXT: slti a0, a4, 0 +; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: bnez a0, .LBB21_14 ; CHECK-NOV-NEXT: .LBB21_13: # %entry -; CHECK-NOV-NEXT: mv a0, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB21_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB21_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: .LBB21_16: # %entry -; CHECK-NOV-NEXT: mv a1, s0 +; CHECK-NOV-NEXT: mv a0, s0 +; CHECK-NOV-NEXT: mv a1, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2679,43 +2681,43 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz s1, .LBB21_3 +; CHECK-V-NEXT: beqz a1, .LBB21_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, s1, 0 -; CHECK-V-NEXT: bnez a1, .LBB21_4 +; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: bnez s1, .LBB21_4 ; CHECK-V-NEXT: .LBB21_2: -; CHECK-V-NEXT: sltu a5, a0, a3 +; CHECK-V-NEXT: sltu a5, s0, a3 ; CHECK-V-NEXT: beqz a5, .LBB21_5 ; CHECK-V-NEXT: j .LBB21_6 ; CHECK-V-NEXT: .LBB21_3: -; CHECK-V-NEXT: sltu a4, s0, a3 -; CHECK-V-NEXT: beqz a1, .LBB21_2 +; CHECK-V-NEXT: sltu a4, a0, a3 +; CHECK-V-NEXT: beqz s1, .LBB21_2 ; CHECK-V-NEXT: .LBB21_4: # %entry -; CHECK-V-NEXT: slti a5, a1, 0 +; CHECK-V-NEXT: slti a5, s1, 0 ; CHECK-V-NEXT: bnez a5, .LBB21_6 ; CHECK-V-NEXT: .LBB21_5: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB21_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, s1 +; CHECK-V-NEXT: and a5, a5, a1 ; CHECK-V-NEXT: bnez a4, .LBB21_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB21_8: # %entry -; CHECK-V-NEXT: and a4, a6, a1 +; CHECK-V-NEXT: and a4, a6, s1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB21_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -2723,26 +2725,26 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB21_12 ; CHECK-V-NEXT: .LBB21_10: -; CHECK-V-NEXT: sltu a2, a1, a0 +; CHECK-V-NEXT: sltu a2, a1, s0 ; CHECK-V-NEXT: beqz a2, .LBB21_13 ; CHECK-V-NEXT: j .LBB21_14 ; CHECK-V-NEXT: .LBB21_11: -; CHECK-V-NEXT: sltu a3, a1, s0 +; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB21_10 ; CHECK-V-NEXT: .LBB21_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB21_14 ; CHECK-V-NEXT: .LBB21_13: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB21_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB21_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB21_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, s0 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, s0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2775,19 +2777,19 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.s fs0, fa0 -; CHECK-NOV-NEXT: fmv.s fa0, fa1 +; CHECK-NOV-NEXT: fmv.s fs0, fa1 ; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixunssfti -; CHECK-NOV-NEXT: snez a2, s1 ; CHECK-NOV-NEXT: snez a1, a1 +; CHECK-NOV-NEXT: snez a2, s1 +; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a2, a2, s0 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a0, a1, a0 -; CHECK-NOV-NEXT: addi a1, a2, -1 -; CHECK-NOV-NEXT: and a1, a1, s0 +; CHECK-NOV-NEXT: and a1, a1, a0 +; CHECK-NOV-NEXT: mv a0, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2812,25 +2814,25 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunssfti -; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: snez a1, a1 -; CHECK-V-NEXT: addi a1, a1, -1 -; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s0 +; CHECK-V-NEXT: addi a1, a1, -1 +; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a2 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2872,32 +2874,32 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB23_2: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: slti a3, a1, 1 +; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB23_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB23_4: # %entry +; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB23_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB23_8 ; CHECK-NOV-NEXT: .LBB23_6: -; CHECK-NOV-NEXT: snez a2, a0 +; CHECK-NOV-NEXT: snez a0, a4 ; CHECK-NOV-NEXT: j .LBB23_9 ; CHECK-NOV-NEXT: .LBB23_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB23_6 ; CHECK-NOV-NEXT: .LBB23_8: # %entry -; CHECK-NOV-NEXT: sgtz a2, a2 +; CHECK-NOV-NEXT: sgtz a0, a2 ; CHECK-NOV-NEXT: .LBB23_9: # %entry -; CHECK-NOV-NEXT: neg a2, a2 -; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: neg a0, a0 +; CHECK-NOV-NEXT: and a0, a0, a4 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -2939,15 +2941,15 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB23_2: # %entry -; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: slti a4, a1, 1 +; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: blez a1, .LBB23_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB23_4: # %entry +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB23_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -3002,8 +3004,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset s2, -32 -; CHECK-NOV-NEXT: mv s2, a0 -; CHECK-NOV-NEXT: fmv.w.x fa0, a1 +; CHECK-NOV-NEXT: mv s2, a1 +; CHECK-NOV-NEXT: fmv.w.x fa0, a0 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 @@ -3011,58 +3013,60 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: li a2, -1 -; CHECK-NOV-NEXT: srli a3, a2, 1 -; CHECK-NOV-NEXT: beqz s1, .LBB24_3 +; CHECK-NOV-NEXT: mv a2, a0 +; CHECK-NOV-NEXT: li a0, -1 +; CHECK-NOV-NEXT: srli a3, a0, 1 +; CHECK-NOV-NEXT: beqz a1, .LBB24_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 0 -; CHECK-NOV-NEXT: bnez a1, .LBB24_4 +; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: bnez s1, .LBB24_4 ; CHECK-NOV-NEXT: .LBB24_2: -; CHECK-NOV-NEXT: sltu a5, a0, a3 +; CHECK-NOV-NEXT: sltu a5, s0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB24_5 ; CHECK-NOV-NEXT: j .LBB24_6 ; CHECK-NOV-NEXT: .LBB24_3: -; CHECK-NOV-NEXT: sltu a4, s0, a3 -; CHECK-NOV-NEXT: beqz a1, .LBB24_2 +; CHECK-NOV-NEXT: sltu a4, a2, a3 +; CHECK-NOV-NEXT: beqz s1, .LBB24_2 ; CHECK-NOV-NEXT: .LBB24_4: # %entry -; CHECK-NOV-NEXT: slti a5, a1, 0 +; CHECK-NOV-NEXT: slti a5, s1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB24_6 ; CHECK-NOV-NEXT: .LBB24_5: # %entry -; CHECK-NOV-NEXT: mv a0, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB24_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, s1 +; CHECK-NOV-NEXT: and a5, a5, a1 ; CHECK-NOV-NEXT: bnez a4, .LBB24_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a2, a3 ; CHECK-NOV-NEXT: .LBB24_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, a1 -; CHECK-NOV-NEXT: slli a1, a2, 63 -; CHECK-NOV-NEXT: beq a5, a2, .LBB24_11 +; CHECK-NOV-NEXT: and a4, a6, s1 +; CHECK-NOV-NEXT: slli a1, a0, 63 +; CHECK-NOV-NEXT: beq a5, a0, .LBB24_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a2, .LBB24_12 +; CHECK-NOV-NEXT: bne a4, a0, .LBB24_12 ; CHECK-NOV-NEXT: .LBB24_10: -; CHECK-NOV-NEXT: sltu a2, a1, a0 -; CHECK-NOV-NEXT: beqz a2, .LBB24_13 +; CHECK-NOV-NEXT: sltu a0, a1, s0 +; CHECK-NOV-NEXT: beqz a0, .LBB24_13 ; CHECK-NOV-NEXT: j .LBB24_14 ; CHECK-NOV-NEXT: .LBB24_11: -; CHECK-NOV-NEXT: sltu a3, a1, s0 -; CHECK-NOV-NEXT: beq a4, a2, .LBB24_10 +; CHECK-NOV-NEXT: sltu a3, a1, a2 +; CHECK-NOV-NEXT: beq a4, a0, .LBB24_10 ; CHECK-NOV-NEXT: .LBB24_12: # %entry -; CHECK-NOV-NEXT: slti a2, a4, 0 -; CHECK-NOV-NEXT: xori a2, a2, 1 -; CHECK-NOV-NEXT: bnez a2, .LBB24_14 +; CHECK-NOV-NEXT: slti a0, a4, 0 +; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: bnez a0, .LBB24_14 ; CHECK-NOV-NEXT: .LBB24_13: # %entry -; CHECK-NOV-NEXT: mv a0, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB24_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB24_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: .LBB24_16: # %entry -; CHECK-NOV-NEXT: mv a1, s0 +; CHECK-NOV-NEXT: mv a0, s0 +; CHECK-NOV-NEXT: mv a1, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -3082,8 +3086,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s2, -32 -; CHECK-V-NEXT: mv s2, a0 -; CHECK-V-NEXT: fmv.w.x fa0, a1 +; CHECK-V-NEXT: mv s2, a1 +; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 @@ -3093,31 +3097,31 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz s1, .LBB24_3 +; CHECK-V-NEXT: beqz a1, .LBB24_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, s1, 0 -; CHECK-V-NEXT: bnez a1, .LBB24_4 +; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: bnez s1, .LBB24_4 ; CHECK-V-NEXT: .LBB24_2: -; CHECK-V-NEXT: sltu a5, a0, a3 +; CHECK-V-NEXT: sltu a5, s0, a3 ; CHECK-V-NEXT: beqz a5, .LBB24_5 ; CHECK-V-NEXT: j .LBB24_6 ; CHECK-V-NEXT: .LBB24_3: -; CHECK-V-NEXT: sltu a4, s0, a3 -; CHECK-V-NEXT: beqz a1, .LBB24_2 +; CHECK-V-NEXT: sltu a4, a0, a3 +; CHECK-V-NEXT: beqz s1, .LBB24_2 ; CHECK-V-NEXT: .LBB24_4: # %entry -; CHECK-V-NEXT: slti a5, a1, 0 +; CHECK-V-NEXT: slti a5, s1, 0 ; CHECK-V-NEXT: bnez a5, .LBB24_6 ; CHECK-V-NEXT: .LBB24_5: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB24_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, s1 +; CHECK-V-NEXT: and a5, a5, a1 ; CHECK-V-NEXT: bnez a4, .LBB24_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB24_8: # %entry -; CHECK-V-NEXT: and a4, a6, a1 +; CHECK-V-NEXT: and a4, a6, s1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB24_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -3125,26 +3129,26 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB24_12 ; CHECK-V-NEXT: .LBB24_10: -; CHECK-V-NEXT: sltu a2, a1, a0 +; CHECK-V-NEXT: sltu a2, a1, s0 ; CHECK-V-NEXT: beqz a2, .LBB24_13 ; CHECK-V-NEXT: j .LBB24_14 ; CHECK-V-NEXT: .LBB24_11: -; CHECK-V-NEXT: sltu a3, a1, s0 +; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB24_10 ; CHECK-V-NEXT: .LBB24_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB24_14 ; CHECK-V-NEXT: .LBB24_13: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB24_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB24_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB24_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v9, s0 -; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, s0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -3175,8 +3179,8 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset s2, -32 -; CHECK-NOV-NEXT: mv s0, a0 -; CHECK-NOV-NEXT: fmv.w.x fa0, a1 +; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: fmv.w.x fa0, a0 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s1, a0 @@ -3184,12 +3188,13 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s0 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixunssfti -; CHECK-NOV-NEXT: snez a2, s2 ; CHECK-NOV-NEXT: snez a1, a1 +; CHECK-NOV-NEXT: snez a2, s2 +; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a2, a2, s1 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a0, a1, a0 -; CHECK-NOV-NEXT: addi a1, a2, -1 -; CHECK-NOV-NEXT: and a1, a1, s1 +; CHECK-NOV-NEXT: and a1, a1, a0 +; CHECK-NOV-NEXT: mv a0, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -3209,8 +3214,8 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s2, -32 -; CHECK-V-NEXT: mv s0, a0 -; CHECK-V-NEXT: fmv.w.x fa0, a1 +; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s1, a0 @@ -3218,15 +3223,15 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixunssfti -; CHECK-V-NEXT: snez a2, s2 ; CHECK-V-NEXT: snez a1, a1 -; CHECK-V-NEXT: addi a1, a1, -1 -; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: snez a2, s2 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s1 +; CHECK-V-NEXT: addi a1, a1, -1 +; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v9, a2 -; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a2 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -3269,32 +3274,32 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB26_2: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: slti a3, a1, 1 +; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB26_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB26_4: # %entry +; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB26_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB26_8 ; CHECK-NOV-NEXT: .LBB26_6: -; CHECK-NOV-NEXT: snez a2, a0 +; CHECK-NOV-NEXT: snez a0, a4 ; CHECK-NOV-NEXT: j .LBB26_9 ; CHECK-NOV-NEXT: .LBB26_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB26_6 ; CHECK-NOV-NEXT: .LBB26_8: # %entry -; CHECK-NOV-NEXT: sgtz a2, a2 +; CHECK-NOV-NEXT: sgtz a0, a2 ; CHECK-NOV-NEXT: .LBB26_9: # %entry -; CHECK-NOV-NEXT: neg a2, a2 -; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: neg a0, a0 +; CHECK-NOV-NEXT: and a0, a0, a4 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -3330,15 +3335,15 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB26_2: # %entry -; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: slti a4, a1, 1 +; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: blez a1, .LBB26_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB26_4: # %entry +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB26_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -5811,15 +5816,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixdfti -; CHECK-NOV-NEXT: mv a2, s1 -; CHECK-NOV-NEXT: mv a3, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB47_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB47_2: # %entry -; CHECK-NOV-NEXT: blez a2, .LBB47_4 +; CHECK-NOV-NEXT: mv a3, s1 +; CHECK-NOV-NEXT: blez s1, .LBB47_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB47_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -5827,11 +5832,11 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: slti a3, a3, 0 +; CHECK-NOV-NEXT: addi a3, a3, -1 +; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a0, a2, a0 -; CHECK-NOV-NEXT: slti a2, a3, 0 -; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -5867,15 +5872,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixdfti -; CHECK-V-NEXT: mv a2, s1 -; CHECK-V-NEXT: mv a3, a1 +; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB47_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB47_2: # %entry -; CHECK-V-NEXT: blez a2, .LBB47_4 +; CHECK-V-NEXT: mv a3, s1 +; CHECK-V-NEXT: blez s1, .LBB47_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB47_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -5883,11 +5888,11 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 +; CHECK-V-NEXT: slti a3, a3, 0 +; CHECK-V-NEXT: addi a3, a3, -1 +; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a1, a2, a1 -; CHECK-V-NEXT: slti a2, a3, 0 -; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -6197,15 +6202,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, s1 -; CHECK-NOV-NEXT: mv a3, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB50_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB50_2: # %entry -; CHECK-NOV-NEXT: blez a2, .LBB50_4 +; CHECK-NOV-NEXT: mv a3, s1 +; CHECK-NOV-NEXT: blez s1, .LBB50_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB50_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -6213,11 +6218,11 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: slti a3, a3, 0 +; CHECK-NOV-NEXT: addi a3, a3, -1 +; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a0, a2, a0 -; CHECK-NOV-NEXT: slti a2, a3, 0 -; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -6253,15 +6258,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixsfti -; CHECK-V-NEXT: mv a2, s1 -; CHECK-V-NEXT: mv a3, a1 +; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB50_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB50_2: # %entry -; CHECK-V-NEXT: blez a2, .LBB50_4 +; CHECK-V-NEXT: mv a3, s1 +; CHECK-V-NEXT: blez s1, .LBB50_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB50_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -6269,11 +6274,11 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 +; CHECK-V-NEXT: slti a3, a3, 0 +; CHECK-V-NEXT: addi a3, a3, -1 +; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a1, a2, a1 -; CHECK-V-NEXT: slti a2, a3, 0 -; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -6575,15 +6580,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, s1 -; CHECK-NOV-NEXT: mv a3, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB53_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB53_2: # %entry -; CHECK-NOV-NEXT: blez a2, .LBB53_4 +; CHECK-NOV-NEXT: mv a3, s1 +; CHECK-NOV-NEXT: blez s1, .LBB53_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB53_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -6591,11 +6596,11 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: slti a3, a3, 0 +; CHECK-NOV-NEXT: addi a3, a3, -1 +; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a0, a2, a0 -; CHECK-NOV-NEXT: slti a2, a3, 0 -; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -6625,15 +6630,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixsfti -; CHECK-V-NEXT: mv a2, s1 -; CHECK-V-NEXT: mv a3, a1 +; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB53_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB53_2: # %entry -; CHECK-V-NEXT: blez a2, .LBB53_4 +; CHECK-V-NEXT: mv a3, s1 +; CHECK-V-NEXT: blez s1, .LBB53_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB53_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -6641,11 +6646,11 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 +; CHECK-V-NEXT: slti a3, a3, 0 +; CHECK-V-NEXT: addi a3, a3, -1 +; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a1, a2, a1 -; CHECK-V-NEXT: slti a2, a3, 0 -; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v9, a0 diff --git a/llvm/test/CodeGen/X86/abdu-vector-128.ll b/llvm/test/CodeGen/X86/abdu-vector-128.ll index dd180b67e492..0c33e8973c2d 100644 --- a/llvm/test/CodeGen/X86/abdu-vector-128.ll +++ b/llvm/test/CodeGen/X86/abdu-vector-128.ll @@ -715,43 +715,41 @@ define <2 x i64> @abd_cmp_v2i64_multiuse_cmp(<2 x i64> %a, <2 x i64> %b) nounwin ; ; SSE42-LABEL: abd_cmp_v2i64_multiuse_cmp: ; SSE42: # %bb.0: -; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: psubq %xmm1, %xmm2 ; SSE42-NEXT: movdqa %xmm1, %xmm3 -; SSE42-NEXT: pxor %xmm2, %xmm3 -; SSE42-NEXT: pxor %xmm0, %xmm2 -; SSE42-NEXT: pcmpgtq %xmm3, %xmm2 -; SSE42-NEXT: movdqa %xmm0, %xmm3 -; SSE42-NEXT: psubq %xmm1, %xmm3 -; SSE42-NEXT: psubq %xmm0, %xmm1 -; SSE42-NEXT: movdqa %xmm2, %xmm0 -; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm1 -; SSE42-NEXT: paddq %xmm1, %xmm2 -; SSE42-NEXT: movdqa %xmm2, %xmm0 +; SSE42-NEXT: psubq %xmm0, %xmm3 +; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: pxor %xmm4, %xmm1 +; SSE42-NEXT: pxor %xmm4, %xmm0 +; SSE42-NEXT: pcmpgtq %xmm1, %xmm0 +; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm3 +; SSE42-NEXT: paddq %xmm3, %xmm0 ; SSE42-NEXT: retq ; ; AVX1-LABEL: abd_cmp_v2i64_multiuse_cmp: ; AVX1: # %bb.0: -; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] -; AVX1-NEXT: # xmm2 = mem[0,0] -; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 -; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2 -; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm3 -; AVX1-NEXT: vpsubq %xmm0, %xmm1, %xmm0 -; AVX1-NEXT: vblendvpd %xmm2, %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpaddq %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vpsubq %xmm0, %xmm1, %xmm3 +; AVX1-NEXT: vmovddup {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] +; AVX1-NEXT: # xmm4 = mem[0,0] +; AVX1-NEXT: vpxor %xmm4, %xmm1, %xmm1 +; AVX1-NEXT: vpxor %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm1 +; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: abd_cmp_v2i64_multiuse_cmp: ; AVX2: # %bb.0: -; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] -; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 -; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2 -; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 -; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm3 -; AVX2-NEXT: vpsubq %xmm0, %xmm1, %xmm0 -; AVX2-NEXT: vblendvpd %xmm2, %xmm3, %xmm0, %xmm0 -; AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0 +; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpsubq %xmm0, %xmm1, %xmm3 +; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] +; AVX2-NEXT: vpxor %xmm4, %xmm1, %xmm1 +; AVX2-NEXT: vpxor %xmm4, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm1 +; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: abd_cmp_v2i64_multiuse_cmp: diff --git a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll index 017024c173c3..b2cb2c3e04b3 100644 --- a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll +++ b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll @@ -52,10 +52,7 @@ alloca_21: define i32 @kmovrk_1(<4 x ptr> %arg) { ; AVX512-LABEL: kmovrk_1: ; AVX512: # %bb.0: # %bb -; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512-NEXT: vptestmq %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc0] -; AVX512-NEXT: kmovw %k0, %eax # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x93,0xc0] -; AVX512-NEXT: testb $15, %al # encoding: [0xa8,0x0f] +; AVX512-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] ; AVX512-NEXT: jne .LBB2_1 # encoding: [0x75,A] ; AVX512-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 ; AVX512-NEXT: # %bb.2: # %bb3 @@ -66,10 +63,7 @@ define i32 @kmovrk_1(<4 x ptr> %arg) { ; ; AVX512BW-LABEL: kmovrk_1: ; AVX512BW: # %bb.0: # %bb -; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc0] -; AVX512BW-NEXT: kmovd %k0, %eax # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x93,0xc0] -; AVX512BW-NEXT: testb $15, %al # encoding: [0xa8,0x0f] +; AVX512BW-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] ; AVX512BW-NEXT: jne .LBB2_1 # encoding: [0x75,A] ; AVX512BW-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 ; AVX512BW-NEXT: # %bb.2: # %bb3 diff --git a/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll b/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll index 13d1265a249d..7e48b3719cf0 100644 --- a/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll +++ b/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll @@ -30,13 +30,13 @@ define <64 x i8> @add_v64i8_broadcasts(<64 x i8> %a0, i64 %a1, i8 %a2) { ; AVX512F-NEXT: vinserti128 $1, %xmm4, %ymm3, %ymm3 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-NEXT: vpternlogq $216, %zmm2, %zmm1, %zmm0 -; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm3 -; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3 +; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0 -; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm4 +; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm4 +; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0 -; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm1 -; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 ; AVX512F-NEXT: vpternlogq $226, %zmm4, %zmm2, %zmm0 ; AVX512F-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/combine-mul.ll b/llvm/test/CodeGen/X86/combine-mul.ll index 8d2bb77a9e1a..5d7bf4a2c978 100644 --- a/llvm/test/CodeGen/X86/combine-mul.ll +++ b/llvm/test/CodeGen/X86/combine-mul.ll @@ -80,13 +80,13 @@ define <4 x i32> @combine_vec_mul_pow2b(<4 x i32> %x) { define <4 x i64> @combine_vec_mul_pow2c(<4 x i64> %x) { ; SSE-LABEL: combine_vec_mul_pow2c: ; SSE: # %bb.0: +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: paddq %xmm0, %xmm2 +; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: psllq $4, %xmm2 ; SSE-NEXT: psllq $2, %xmm1 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: paddq %xmm0, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_mul_pow2c: @@ -399,14 +399,12 @@ define i64 @combine_mul_self_demandedbits(i64 %x) { ; SSE: # %bb.0: ; SSE-NEXT: movq %rdi, %rax ; SSE-NEXT: imulq %rdi, %rax -; SSE-NEXT: andq $-3, %rax ; SSE-NEXT: retq ; ; AVX-LABEL: combine_mul_self_demandedbits: ; AVX: # %bb.0: ; AVX-NEXT: movq %rdi, %rax ; AVX-NEXT: imulq %rdi, %rax -; AVX-NEXT: andq $-3, %rax ; AVX-NEXT: retq %1 = mul i64 %x, %x %2 = and i64 %1, -3 diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll index e12ca56023a7..bf7c1c00c71d 100644 --- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll +++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll @@ -178,15 +178,15 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: pushl %edi ; X86-NEXT: pushl %esi ; X86-NEXT: subl $152, %esp -; X86-NEXT: movl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: sarl $31, %eax -; X86-NEXT: movl %edx, %edi -; X86-NEXT: sarl $31, %edi +; X86-NEXT: movl %ebp, %edx +; X86-NEXT: sarl $31, %edx ; X86-NEXT: movl %eax, %esi ; X86-NEXT: xorl %ecx, %esi -; X86-NEXT: movl %esi, %ebp +; X86-NEXT: movl %esi, %edi ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %ecx, %ebx @@ -195,67 +195,66 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl %eax, %esi ; X86-NEXT: xorl {{[0-9]+}}(%esp), %esi ; X86-NEXT: subl %eax, %esi -; X86-NEXT: movl %esi, (%esp) # 4-byte Spill +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %eax, %ebp -; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, %esi -; X86-NEXT: xorl %edx, %esi -; X86-NEXT: movl %edi, %edx -; X86-NEXT: xorl {{[0-9]+}}(%esp), %edx -; X86-NEXT: movl %edi, %ebx +; X86-NEXT: movl %ebx, (%esp) # 4-byte Spill +; X86-NEXT: sbbl %eax, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edx, %edi +; X86-NEXT: xorl %ebp, %edi +; X86-NEXT: movl %edx, %ebx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebx -; X86-NEXT: movl %edi, %ebp +; X86-NEXT: movl %edx, %esi +; X86-NEXT: xorl {{[0-9]+}}(%esp), %esi +; X86-NEXT: movl %edx, %ebp ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: subl %edi, %ebp -; X86-NEXT: sbbl %edi, %ebx -; X86-NEXT: sbbl %edi, %edx -; X86-NEXT: sbbl %edi, %esi -; X86-NEXT: xorl %eax, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, %eax -; X86-NEXT: orl %esi, %eax +; X86-NEXT: subl %edx, %ebp +; X86-NEXT: sbbl %edx, %esi +; X86-NEXT: sbbl %edx, %ebx +; X86-NEXT: sbbl %edx, %edi +; X86-NEXT: xorl %eax, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %esi, %eax +; X86-NEXT: orl %edi, %eax ; X86-NEXT: movl %ebp, %ecx -; X86-NEXT: orl %edx, %ecx -; X86-NEXT: movl %edx, %edi +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: orl %eax, %ecx ; X86-NEXT: sete %cl ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: movl (%esp), %edx # 4-byte Reload -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: orl (%esp), %edx # 4-byte Folded Reload ; X86-NEXT: orl %eax, %edx ; X86-NEXT: sete %al ; X86-NEXT: orb %cl, %al ; X86-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill -; X86-NEXT: bsrl %esi, %edx +; X86-NEXT: bsrl %edi, %edx ; X86-NEXT: xorl $31, %edx -; X86-NEXT: bsrl %edi, %ecx +; X86-NEXT: bsrl %ebx, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx -; X86-NEXT: testl %esi, %esi +; X86-NEXT: testl %edi, %edi ; X86-NEXT: cmovnel %edx, %ecx -; X86-NEXT: bsrl %ebx, %edx +; X86-NEXT: bsrl %esi, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: bsrl %ebp, %ebp ; X86-NEXT: xorl $31, %ebp ; X86-NEXT: addl $32, %ebp -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: testl %ebx, %ebx +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: testl %esi, %esi ; X86-NEXT: cmovnel %edx, %ebp ; X86-NEXT: addl $64, %ebp +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %edi +; X86-NEXT: orl %edi, %ebx ; X86-NEXT: cmovnel %ecx, %ebp ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; X86-NEXT: bsrl %edi, %edx ; X86-NEXT: xorl $31, %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NEXT: bsrl %eax, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx @@ -264,7 +263,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: bsrl %ebx, %esi ; X86-NEXT: xorl $31, %esi -; X86-NEXT: bsrl (%esp), %edx # 4-byte Folded Reload +; X86-NEXT: bsrl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: xorl $31, %edx ; X86-NEXT: addl $32, %edx ; X86-NEXT: testl %ebx, %ebx @@ -272,52 +271,56 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: addl $64, %edx ; X86-NEXT: movl %eax, %esi ; X86-NEXT: orl %edi, %esi +; X86-NEXT: movl %edi, %ebx ; X86-NEXT: cmovnel %ecx, %edx ; X86-NEXT: xorl %esi, %esi ; X86-NEXT: subl %edx, %ebp -; X86-NEXT: movl $0, %ebx -; X86-NEXT: sbbl %ebx, %ebx ; X86-NEXT: movl $0, %edx ; X86-NEXT: sbbl %edx, %edx ; X86-NEXT: movl $0, %eax ; X86-NEXT: sbbl %eax, %eax +; X86-NEXT: movl $0, %edi +; X86-NEXT: sbbl %edi, %edi ; X86-NEXT: movl $127, %ecx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: cmpl %ebp, %ecx ; X86-NEXT: movl $0, %ecx -; X86-NEXT: sbbl %ebx, %ecx -; X86-NEXT: movl $0, %ecx ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %edx, %ecx ; X86-NEXT: movl $0, %ecx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx +; X86-NEXT: movl $0, %ecx +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %edi, %ecx ; X86-NEXT: setb %cl ; X86-NEXT: orb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Folded Reload +; X86-NEXT: movl %ebx, %edi ; X86-NEXT: cmovnel %esi, %edi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: movl (%esp), %edx # 4-byte Reload ; X86-NEXT: cmovnel %esi, %edx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: cmovnel %esi, %eax -; X86-NEXT: cmovel (%esp), %esi # 4-byte Folded Reload +; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: jne .LBB4_8 -; X86-NEXT: # %bb.1: # %_udiv-special-cases -; X86-NEXT: movl %ebx, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: xorl $127, %ebx -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: jne .LBB4_1 +; X86-NEXT: # %bb.8: # %_udiv-special-cases +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload +; X86-NEXT: xorl $127, %ebp +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: orl %ebx, %ecx -; X86-NEXT: je .LBB4_8 -; X86-NEXT: # %bb.2: # %udiv-bb1 -; X86-NEXT: movl (%esp), %eax # 4-byte Reload -; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: orl %ebp, %ecx +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: je .LBB4_9 +; X86-NEXT: # %bb.5: # %udiv-bb1 ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl (%esp), %eax # 4-byte Reload +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -332,78 +335,82 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: shrb $3, %al ; X86-NEXT: andb $15, %al ; X86-NEXT: negb %al -; X86-NEXT: movsbl %al, %ebx -; X86-NEXT: movl 144(%esp,%ebx), %edx -; X86-NEXT: movl 148(%esp,%ebx), %edi +; X86-NEXT: movsbl %al, %edi +; X86-NEXT: movl 144(%esp,%edi), %edx +; X86-NEXT: movl 148(%esp,%edi), %esi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %edx, %edi +; X86-NEXT: shldl %cl, %edx, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: shll %cl, %edx ; X86-NEXT: notb %cl -; X86-NEXT: movl 140(%esp,%ebx), %eax +; X86-NEXT: movl 140(%esp,%edi), %eax ; X86-NEXT: movl %eax, %esi ; X86-NEXT: shrl %esi ; X86-NEXT: shrl %cl, %esi ; X86-NEXT: orl %edx, %esi ; X86-NEXT: movl %esi, %edx -; X86-NEXT: movl 136(%esp,%ebx), %esi +; X86-NEXT: movl 136(%esp,%edi), %esi ; X86-NEXT: movb %ch, %cl ; X86-NEXT: shldl %cl, %esi, %eax ; X86-NEXT: shll %cl, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: addl $1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: adcl $0, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: adcl $0, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: adcl $0, %edi ; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: jae .LBB4_3 +; X86-NEXT: jae .LBB4_2 ; X86-NEXT: # %bb.6: -; X86-NEXT: xorl %ebx, %ebx -; X86-NEXT: xorl %esi, %esi +; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: jmp .LBB4_7 -; X86-NEXT: .LBB4_3: # %udiv-preheader -; X86-NEXT: movl (%esp), %esi # 4-byte Reload -; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) +; X86-NEXT: .LBB4_1: +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: jmp .LBB4_9 +; X86-NEXT: .LBB4_2: # %udiv-preheader +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) +; X86-NEXT: movl (%esp), %ebx # 4-byte Reload +; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movb %bl, %ch ; X86-NEXT: andb $7, %ch ; X86-NEXT: movb %bl, %cl ; X86-NEXT: shrb $3, %cl ; X86-NEXT: andb $15, %cl -; X86-NEXT: movzbl %cl, %ebp -; X86-NEXT: movl 100(%esp,%ebp), %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl 96(%esp,%ebp), %ebx -; X86-NEXT: movl %ebp, %eax +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movzbl %cl, %ebx +; X86-NEXT: movl 100(%esp,%ebx), %ebp +; X86-NEXT: movl %ebp, (%esp) # 4-byte Spill +; X86-NEXT: movl 96(%esp,%ebx), %edi ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, %edx +; X86-NEXT: movl %edi, %edx ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrdl %cl, %esi, %edx -; X86-NEXT: movl 88(%esp,%ebp), %ebp -; X86-NEXT: movl 92(%esp,%eax), %esi -; X86-NEXT: movl %esi, %eax +; X86-NEXT: shrdl %cl, %ebp, %edx +; X86-NEXT: movl %edx, %ebp +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 88(%esp,%ebx), %edx +; X86-NEXT: movl 92(%esp,%ebx), %ebx +; X86-NEXT: movl %ebx, %eax ; X86-NEXT: shrl %cl, %eax ; X86-NEXT: notb %cl -; X86-NEXT: addl %ebx, %ebx -; X86-NEXT: shll %cl, %ebx -; X86-NEXT: orl %eax, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: addl %edi, %edi +; X86-NEXT: shll %cl, %edi +; X86-NEXT: orl %eax, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrl %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: shrdl %cl, %esi, %ebp +; X86-NEXT: shrl %cl, (%esp) # 4-byte Folded Spill +; X86-NEXT: shrdl %cl, %ebx, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: addl $-1, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill @@ -413,113 +420,109 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: adcl $-1, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: movl %ecx, %eax +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: adcl $-1, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: xorl %esi, %esi ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: .p2align 4, 0x90 -; X86-NEXT: .LBB4_4: # %udiv-do-while +; X86-NEXT: .LBB4_3: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: shldl $1, %edx, %ebx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: shldl $1, %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: movl %ebp, %edx +; X86-NEXT: shldl $1, %ebp, (%esp) # 4-byte Folded Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload ; X86-NEXT: shldl $1, %ebp, %edx -; X86-NEXT: shldl $1, %edi, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: shldl $1, %eax, %edi -; X86-NEXT: orl %esi, %edi -; X86-NEXT: movl %edi, (%esp) # 4-byte Spill -; X86-NEXT: movl %ecx, %edi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: shldl $1, %ebx, %ebp +; X86-NEXT: shldl $1, %edi, %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: shldl $1, %ecx, %eax -; X86-NEXT: orl %esi, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $1, %ecx, %edi ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: shldl $1, %eax, %ecx -; X86-NEXT: orl %esi, %ecx +; X86-NEXT: orl %eax, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: shldl $1, %edi, %ecx +; X86-NEXT: orl %eax, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: addl %eax, %eax -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: cmpl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload +; X86-NEXT: shldl $1, %esi, %edi +; X86-NEXT: orl %eax, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: addl %esi, %esi +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: cmpl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl %edx, %ecx +; X86-NEXT: sbbl %ebp, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: sbbl %edx, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl %ebx, %ecx +; X86-NEXT: sbbl (%esp), %ecx # 4-byte Folded Reload ; X86-NEXT: sarl $31, %ecx -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: andl $1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %ecx, %esi -; X86-NEXT: andl %edi, %esi +; X86-NEXT: andl $1, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; X86-NEXT: movl %ecx, %edi ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: subl %ecx, %ebp -; X86-NEXT: sbbl %eax, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: sbbl %edi, %edx -; X86-NEXT: movl (%esp), %edi # 4-byte Reload -; X86-NEXT: sbbl %esi, %ebx +; X86-NEXT: subl %ecx, %ebx ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: sbbl %eax, %ebp +; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %edi, %edx +; X86-NEXT: movl %edx, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: sbbl %esi, (%esp) # 4-byte Folded Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: addl $-1, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: adcl $-1, %esi -; X86-NEXT: adcl $-1, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: adcl $-1, %edi +; X86-NEXT: adcl $-1, %edx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %ebx, %eax +; X86-NEXT: orl %edx, %eax ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %edi, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; X86-NEXT: orl %eax, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: jne .LBB4_4 -; X86-NEXT: # %bb.5: +; X86-NEXT: jne .LBB4_3 +; X86-NEXT: # %bb.4: +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: .LBB4_7: # %udiv-loop-exit +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; X86-NEXT: shldl $1, %edx, %edi -; X86-NEXT: orl %esi, %edi +; X86-NEXT: orl %ecx, %edi ; X86-NEXT: shldl $1, %eax, %edx -; X86-NEXT: orl %esi, %edx -; X86-NEXT: movl %esi, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: orl %ecx, %edx ; X86-NEXT: shldl $1, %esi, %eax ; X86-NEXT: orl %ecx, %eax ; X86-NEXT: addl %esi, %esi -; X86-NEXT: orl %ebx, %esi -; X86-NEXT: .LBB4_8: # %udiv-end -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: xorl %ecx, %edi -; X86-NEXT: xorl %ecx, %edx -; X86-NEXT: xorl %ecx, %eax -; X86-NEXT: xorl %ecx, %esi -; X86-NEXT: subl %ecx, %esi +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload +; X86-NEXT: .LBB4_9: # %udiv-end +; X86-NEXT: xorl %ebx, %edi +; X86-NEXT: xorl %ebx, %edx +; X86-NEXT: xorl %ebx, %eax +; X86-NEXT: xorl %ebx, %esi +; X86-NEXT: subl %ebx, %esi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %ecx, %eax +; X86-NEXT: sbbl %ebx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %ecx, %edx -; X86-NEXT: sbbl %ecx, %edi -; X86-NEXT: movl %edi, (%esp) # 4-byte Spill +; X86-NEXT: sbbl %ebx, %edx +; X86-NEXT: sbbl %ebx, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, (%ebp) ; X86-NEXT: movl %eax, 4(%ebp) ; X86-NEXT: movl %edx, 8(%ebp) @@ -532,7 +535,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, %eax ; X86-NEXT: mull %edi -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %eax, (%esp) # 4-byte Spill ; X86-NEXT: movl %edx, %edi ; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload ; X86-NEXT: adcl $0, %ecx @@ -553,10 +556,10 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: adcl %eax, %edx ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: movl (%esp), %ecx # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: imull %eax, %ecx ; X86-NEXT: mull %ebx -; X86-NEXT: movl %eax, (%esp) # 4-byte Spill +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: imull {{[0-9]+}}(%esp), %ebx ; X86-NEXT: addl %edx, %ebx ; X86-NEXT: addl %ecx, %ebx @@ -568,12 +571,12 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: mull %edx ; X86-NEXT: addl %edx, %ebp ; X86-NEXT: addl %ecx, %ebp -; X86-NEXT: addl (%esp), %eax # 4-byte Folded Reload +; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: adcl %ebx, %ebp ; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: subl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: subl (%esp), %edx # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi diff --git a/llvm/test/CodeGen/X86/fold-masked-merge.ll b/llvm/test/CodeGen/X86/fold-masked-merge.ll index 135494ac25f8..b2614c5fe049 100644 --- a/llvm/test/CodeGen/X86/fold-masked-merge.ll +++ b/llvm/test/CodeGen/X86/fold-masked-merge.ll @@ -56,9 +56,7 @@ define i8 @masked_merge2(i8 %a0, i8 %a1, i8 %a2) { ; NOBMI-LABEL: masked_merge2: ; NOBMI: # %bb.0: ; NOBMI-NEXT: movl %esi, %eax -; NOBMI-NEXT: xorb %sil, %al -; NOBMI-NEXT: andb %dil, %al -; NOBMI-NEXT: xorb %sil, %al +; NOBMI-NEXT: # kill: def $al killed $al killed $eax ; NOBMI-NEXT: retq ; ; BMI-LABEL: masked_merge2: diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll index b212e9438e1b..d75fc5318bd8 100644 --- a/llvm/test/CodeGen/X86/freeze-binary.ll +++ b/llvm/test/CodeGen/X86/freeze-binary.ll @@ -202,13 +202,27 @@ define <4 x i32> @freeze_add_vec(<4 x i32> %a0) nounwind { define <4 x i32> @freeze_add_vec_undef(<4 x i32> %a0) nounwind { ; X86-LABEL: freeze_add_vec_undef: ; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-16, %esp +; X86-NEXT: subl $32, %esp +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl $3, {{[0-9]+}}(%esp) +; X86-NEXT: movl $2, {{[0-9]+}}(%esp) +; X86-NEXT: movl $1, (%esp) +; X86-NEXT: paddd (%esp), %xmm0 ; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp ; X86-NEXT: retl ; ; X64-LABEL: freeze_add_vec_undef: ; X64: # %bb.0: -; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; X64-NEXT: movabsq $8589934593, %rax # imm = 0x200000001 +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) +; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; X64-NEXT: movl $3, -{{[0-9]+}}(%rsp) +; X64-NEXT: vpaddd -{{[0-9]+}}(%rsp), %xmm0, %xmm0 ; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: retq %x = add <4 x i32> %a0, @@ -273,13 +287,27 @@ define <4 x i32> @freeze_sub_vec(<4 x i32> %a0) nounwind { define <4 x i32> @freeze_sub_vec_undef(<4 x i32> %a0) nounwind { ; X86-LABEL: freeze_sub_vec_undef: ; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-16, %esp +; X86-NEXT: subl $32, %esp +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl $3, {{[0-9]+}}(%esp) +; X86-NEXT: movl $2, {{[0-9]+}}(%esp) +; X86-NEXT: movl $1, (%esp) +; X86-NEXT: psubd (%esp), %xmm0 ; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp ; X86-NEXT: retl ; ; X64-LABEL: freeze_sub_vec_undef: ; X64: # %bb.0: -; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; X64-NEXT: movabsq $8589934593, %rax # imm = 0x200000001 +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) +; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp) +; X64-NEXT: movl $3, -{{[0-9]+}}(%rsp) +; X64-NEXT: vpsubd -{{[0-9]+}}(%rsp), %xmm0, %xmm0 ; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: retq %x = sub <4 x i32> %a0, @@ -345,13 +373,29 @@ define <8 x i16> @freeze_mul_vec(<8 x i16> %a0) nounwind { define <8 x i16> @freeze_mul_vec_undef(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_mul_vec_undef: ; X86: # %bb.0: +; X86-NEXT: pushl %ebp +; X86-NEXT: movl %esp, %ebp +; X86-NEXT: andl $-16, %esp +; X86-NEXT: subl $32, %esp +; X86-NEXT: movw %ax, {{[0-9]+}}(%esp) +; X86-NEXT: movw $1, {{[0-9]+}}(%esp) +; X86-NEXT: movl $196612, {{[0-9]+}}(%esp) # imm = 0x30004 +; X86-NEXT: movl $262147, {{[0-9]+}}(%esp) # imm = 0x40003 +; X86-NEXT: movl $131073, (%esp) # imm = 0x20001 +; X86-NEXT: pmullw (%esp), %xmm0 ; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 +; X86-NEXT: movl %ebp, %esp +; X86-NEXT: popl %ebp ; X86-NEXT: retl ; ; X64-LABEL: freeze_mul_vec_undef: ; X64: # %bb.0: -; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; X64-NEXT: movabsq $1125912791875585, %rax # imm = 0x4000300020001 +; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) +; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp) +; X64-NEXT: movw $1, -{{[0-9]+}}(%rsp) +; X64-NEXT: movl $196612, -{{[0-9]+}}(%rsp) # imm = 0x30004 +; X64-NEXT: vpmullw -{{[0-9]+}}(%rsp), %xmm0, %xmm0 ; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: retq %x = mul <8 x i16> %a0, diff --git a/llvm/test/CodeGen/X86/freeze-combine.ll b/llvm/test/CodeGen/X86/freeze-combine.ll index b037a6d9a1b9..1cfb8627a4dd 100644 --- a/llvm/test/CodeGen/X86/freeze-combine.ll +++ b/llvm/test/CodeGen/X86/freeze-combine.ll @@ -3,9 +3,9 @@ define i32 @const() { ; CHECK-LABEL: name: const ; CHECK: bb.0 (%ir-block.0): - ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 - ; CHECK: $eax = COPY [[MOV32ri]] - ; CHECK: RET 0, $eax + ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 + ; CHECK-NEXT: $eax = COPY [[MOV32ri]] + ; CHECK-NEXT: RET 0, $eax %y = freeze i32 1 ret i32 %y } @@ -13,11 +13,11 @@ define i32 @const() { define i32 @fold(i32 %x) { ; CHECK-LABEL: name: fold ; CHECK: bb.0 (%ir-block.0): - ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]] - ; CHECK: $eax = COPY [[COPY1]] - ; CHECK: RET 0, $eax + ; CHECK-NEXT: liveins: $edi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: $eax = COPY [[COPY]] + ; CHECK-NEXT: RET 0, $eax %y = freeze i32 %x %z = freeze i32 %y ret i32 %z diff --git a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll index 0c341dc63a9e..afe0ebb9dcb4 100644 --- a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll +++ b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll @@ -522,17 +522,17 @@ declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) define <16 x i8> @splatconstant_fshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind { ; GFNISSE-LABEL: splatconstant_fshr_v16i8: ; GFNISSE: # %bb.0: +; GFNISSE-NEXT: paddb %xmm0, %xmm0 ; GFNISSE-NEXT: psrlw $7, %xmm1 ; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; GFNISSE-NEXT: paddb %xmm0, %xmm0 ; GFNISSE-NEXT: por %xmm1, %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: splatconstant_fshr_v16i8: ; GFNIAVX1OR2: # %bb.0: +; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm1, %xmm1 ; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/gfni-rotates.ll b/llvm/test/CodeGen/X86/gfni-rotates.ll index 7ab8300b269a..96aff5b2af31 100644 --- a/llvm/test/CodeGen/X86/gfni-rotates.ll +++ b/llvm/test/CodeGen/X86/gfni-rotates.ll @@ -421,18 +421,18 @@ define <16 x i8> @splatconstant_rotr_v16i8(<16 x i8> %a) nounwind { ; GFNISSE-LABEL: splatconstant_rotr_v16i8: ; GFNISSE: # %bb.0: ; GFNISSE-NEXT: movdqa %xmm0, %xmm1 -; GFNISSE-NEXT: psrlw $7, %xmm1 -; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; GFNISSE-NEXT: paddb %xmm0, %xmm0 +; GFNISSE-NEXT: paddb %xmm0, %xmm1 +; GFNISSE-NEXT: psrlw $7, %xmm0 +; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; GFNISSE-NEXT: por %xmm1, %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: splatconstant_rotr_v16i8: ; GFNIAVX1OR2: # %bb.0: -; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm1 -; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm1 +; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpor %xmm0, %xmm1, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; ; GFNIAVX512-LABEL: splatconstant_rotr_v16i8: diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll index 39d02f9112f4..2f780e3c6fe1 100644 --- a/llvm/test/CodeGen/X86/known-never-zero.ll +++ b/llvm/test/CodeGen/X86/known-never-zero.ll @@ -676,12 +676,13 @@ define i32 @rotr_known_nonzero(i32 %xx, i32 %y) { ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx ; X64-NEXT: orl $256, %edi # imm = 0x100 +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %edi +; X64-NEXT: rorl %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB22_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB22_1: ; X64-NEXT: movl $32, %eax @@ -713,12 +714,13 @@ define i32 @rotr_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotr_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %edi +; X64-NEXT: rorl %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB23_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB23_1: ; X64-NEXT: movl $32, %eax @@ -773,12 +775,13 @@ define i32 @rotr_with_fshr_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotr_with_fshr_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %edi +; X64-NEXT: rorl %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB25_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB25_1: ; X64-NEXT: movl $32, %eax @@ -808,12 +811,13 @@ define i32 @rotl_known_nonzero(i32 %xx, i32 %y) { ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx ; X64-NEXT: orl $256, %edi # imm = 0x100 +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %edi +; X64-NEXT: roll %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB26_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB26_1: ; X64-NEXT: movl $32, %eax @@ -845,12 +849,13 @@ define i32 @rotl_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotl_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %edi +; X64-NEXT: roll %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB27_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB27_1: ; X64-NEXT: movl $32, %eax @@ -905,12 +910,13 @@ define i32 @rotl_with_fshl_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotl_with_fshl_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %edi +; X64-NEXT: roll %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB29_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB29_1: ; X64-NEXT: movl $32, %eax diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll index d3cced3233ea..5a6375e08bca 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll @@ -893,27 +893,26 @@ define <2 x i64> @vec128_i64_signed_reg_reg(<2 x i64> %a1, <2 x i64> %a2) nounwi ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm5, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3] -; SSE41-NEXT: por %xmm3, %xmm6 -; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 -; SSE41-NEXT: pand %xmm5, %xmm0 -; SSE41-NEXT: por %xmm4, %xmm0 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psubq %xmm1, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] +; SSE41-NEXT: por %xmm3, %xmm0 +; SSE41-NEXT: pmovsxbq {{.*#+}} xmm3 = [1,1] +; SSE41-NEXT: por %xmm0, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psubq %xmm1, %xmm4 ; SSE41-NEXT: psubq %xmm2, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 +; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 ; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: psrlq $1, %xmm0 ; SSE41-NEXT: psrlq $33, %xmm1 -; SSE41-NEXT: pmuludq %xmm6, %xmm1 -; SSE41-NEXT: movdqa %xmm6, %xmm3 -; SSE41-NEXT: psrlq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm0, %xmm3 -; SSE41-NEXT: paddq %xmm1, %xmm3 -; SSE41-NEXT: psllq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm6, %xmm0 +; SSE41-NEXT: pmuludq %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psrlq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm0, %xmm4 +; SSE41-NEXT: paddq %xmm1, %xmm4 +; SSE41-NEXT: psllq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm3, %xmm0 ; SSE41-NEXT: paddq %xmm2, %xmm0 -; SSE41-NEXT: paddq %xmm3, %xmm0 +; SSE41-NEXT: paddq %xmm4, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: vec128_i64_signed_reg_reg: @@ -1077,27 +1076,26 @@ define <2 x i64> @vec128_i64_unsigned_reg_reg(<2 x i64> %a1, <2 x i64> %a2) noun ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm5, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3] -; SSE41-NEXT: por %xmm3, %xmm6 -; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 -; SSE41-NEXT: pand %xmm5, %xmm0 -; SSE41-NEXT: por %xmm4, %xmm0 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psubq %xmm1, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] +; SSE41-NEXT: por %xmm3, %xmm0 +; SSE41-NEXT: pmovsxbq {{.*#+}} xmm3 = [1,1] +; SSE41-NEXT: por %xmm0, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psubq %xmm1, %xmm4 ; SSE41-NEXT: psubq %xmm2, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 +; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 ; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: psrlq $1, %xmm0 ; SSE41-NEXT: psrlq $33, %xmm1 -; SSE41-NEXT: pmuludq %xmm6, %xmm1 -; SSE41-NEXT: movdqa %xmm6, %xmm3 -; SSE41-NEXT: psrlq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm0, %xmm3 -; SSE41-NEXT: paddq %xmm1, %xmm3 -; SSE41-NEXT: psllq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm6, %xmm0 +; SSE41-NEXT: pmuludq %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psrlq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm0, %xmm4 +; SSE41-NEXT: paddq %xmm1, %xmm4 +; SSE41-NEXT: psllq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm3, %xmm0 ; SSE41-NEXT: paddq %xmm2, %xmm0 -; SSE41-NEXT: paddq %xmm3, %xmm0 +; SSE41-NEXT: paddq %xmm4, %xmm0 ; SSE41-NEXT: retq ; ; AVX1-LABEL: vec128_i64_unsigned_reg_reg: @@ -1993,14 +1991,14 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun ; ; AVX512VL-FALLBACK-LABEL: vec128_i16_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminuw %xmm1, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm2, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm2, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpminuw %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %xmm1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsubw %xmm1, %xmm2, %xmm1 ; AVX512VL-FALLBACK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; AVX512VL-FALLBACK-NEXT: retq ; @@ -2786,14 +2784,14 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw ; ; AVX512VL-FALLBACK-LABEL: vec128_i8_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm2, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %xmm1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %xmm1, %xmm2, %xmm1 ; AVX512VL-FALLBACK-NEXT: vpaddb %xmm0, %xmm1, %xmm0 ; AVX512VL-FALLBACK-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll index cc08396ae8c7..e880a1acc9e8 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll @@ -1445,14 +1445,14 @@ define <16 x i16> @vec256_i16_unsigned_reg_reg(<16 x i16> %a1, <16 x i16> %a2) n ; ; AVX512VL-FALLBACK-LABEL: vec256_i16_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm2, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpxor %ymm2, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpxor %ymm1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm2, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpaddw %ymm0, %ymm1, %ymm0 ; AVX512VL-FALLBACK-NEXT: retq ; @@ -2210,14 +2210,14 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw ; ; AVX512VL-FALLBACK-LABEL: vec256_i8_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm2, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm2, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512VL-FALLBACK-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/pr38539.ll b/llvm/test/CodeGen/X86/pr38539.ll index 04aff9b7d2e5..ace78b38d53e 100644 --- a/llvm/test/CodeGen/X86/pr38539.ll +++ b/llvm/test/CodeGen/X86/pr38539.ll @@ -22,7 +22,7 @@ define void @f() nounwind { ; X86-NEXT: pushl %edi ; X86-NEXT: pushl %esi ; X86-NEXT: andl $-16, %esp -; X86-NEXT: subl $176, %esp +; X86-NEXT: subl $160, %esp ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi @@ -47,55 +47,54 @@ define void @f() nounwind { ; X86-NEXT: testl %edi, %edi ; X86-NEXT: jne .LBB0_1 ; X86-NEXT: # %bb.2: # %BB_udiv-special-cases -; X86-NEXT: bsrl %esi, %ecx -; X86-NEXT: xorl $31, %ecx -; X86-NEXT: addl $32, %ecx +; X86-NEXT: bsrl %esi, %eax +; X86-NEXT: xorl $31, %eax +; X86-NEXT: addl $32, %eax ; X86-NEXT: jmp .LBB0_3 ; X86-NEXT: .LBB0_1: -; X86-NEXT: bsrl %edi, %ecx -; X86-NEXT: xorl $31, %ecx +; X86-NEXT: bsrl %edi, %eax +; X86-NEXT: xorl $31, %eax ; X86-NEXT: .LBB0_3: # %BB_udiv-special-cases -; X86-NEXT: xorl %eax, %eax +; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: jne .LBB0_4 ; X86-NEXT: # %bb.5: # %BB_udiv-special-cases -; X86-NEXT: addl $64, %ecx +; X86-NEXT: addl $64, %eax ; X86-NEXT: jmp .LBB0_6 ; X86-NEXT: .LBB0_4: -; X86-NEXT: bsrl %edx, %ecx -; X86-NEXT: xorl $31, %ecx -; X86-NEXT: addl $32, %ecx +; X86-NEXT: bsrl %edx, %eax +; X86-NEXT: xorl $31, %eax +; X86-NEXT: addl $32, %eax ; X86-NEXT: .LBB0_6: # %BB_udiv-special-cases -; X86-NEXT: subl $62, %ecx +; X86-NEXT: subl $62, %eax ; X86-NEXT: movl $0, %ebx ; X86-NEXT: sbbl %ebx, %ebx -; X86-NEXT: sbbl %eax, %eax -; X86-NEXT: addl $-66, %ecx +; X86-NEXT: sbbl %ecx, %ecx +; X86-NEXT: addl $-66, %eax ; X86-NEXT: adcl $-1, %ebx -; X86-NEXT: adcl $3, %eax -; X86-NEXT: movl %eax, %edi -; X86-NEXT: movb $1, %al -; X86-NEXT: testb %al, %al +; X86-NEXT: adcl $3, %ecx +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: movb $1, %cl +; X86-NEXT: testb %cl, %cl ; X86-NEXT: jne .LBB0_11 ; X86-NEXT: # %bb.7: # %BB_udiv-special-cases -; X86-NEXT: andl $3, %edi -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: xorl $65, %eax -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %edi, %eax -; X86-NEXT: orl %ebx, %eax +; X86-NEXT: andl $3, %esi +; X86-NEXT: movl %eax, %ecx +; X86-NEXT: xorl $65, %ecx +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %esi, %ecx +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: je .LBB0_11 ; X86-NEXT: # %bb.8: # %udiv-bb1 -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ecx, %eax +; X86-NEXT: movl %eax, %ecx ; X86-NEXT: addl $1, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: adcl $0, %ebx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: adcl $0, %esi -; X86-NEXT: andl $3, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: adcl $0, %ebx +; X86-NEXT: andl $3, %ebx ; X86-NEXT: movb $65, %cl ; X86-NEXT: subb %al, %cl ; X86-NEXT: movb %cl, %ch @@ -112,29 +111,31 @@ define void @f() nounwind { ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl 136(%esp,%eax), %edx +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 120(%esp,%eax), %edi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shll %cl, %edx +; X86-NEXT: shll %cl, %edi ; X86-NEXT: notb %cl -; X86-NEXT: movl 128(%esp,%eax), %edi -; X86-NEXT: movl 132(%esp,%eax), %esi -; X86-NEXT: movl %esi, %eax +; X86-NEXT: movl 112(%esp,%eax), %esi +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 116(%esp,%eax), %edx +; X86-NEXT: movl %edx, %eax ; X86-NEXT: shrl %eax ; X86-NEXT: shrl %cl, %eax ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %edi, %esi +; X86-NEXT: shldl %cl, %esi, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shll %cl, %esi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: shll %cl, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: orl %ebx, %ecx +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: je .LBB0_11 ; X86-NEXT: # %bb.9: # %udiv-preheader -; X86-NEXT: orl %eax, %edx -; X86-NEXT: andl $3, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %eax, %edi +; X86-NEXT: andl $3, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -149,20 +150,20 @@ define void @f() nounwind { ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: shrb $3, %al ; X86-NEXT: andb $15, %al -; X86-NEXT: movzbl %al, %esi -; X86-NEXT: movl 80(%esp,%esi), %edx -; X86-NEXT: movl 84(%esp,%esi), %eax -; X86-NEXT: movl %eax, %edi +; X86-NEXT: movzbl %al, %eax +; X86-NEXT: movl 64(%esp,%eax), %edi +; X86-NEXT: movl 68(%esp,%eax), %edx +; X86-NEXT: movl %edx, %esi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrl %cl, %edi +; X86-NEXT: shrl %cl, %esi ; X86-NEXT: notb %cl -; X86-NEXT: movl 88(%esp,%esi), %esi -; X86-NEXT: addl %esi, %esi -; X86-NEXT: shll %cl, %esi -; X86-NEXT: orl %edi, %esi +; X86-NEXT: movl 72(%esp,%eax), %ebx +; X86-NEXT: addl %ebx, %ebx +; X86-NEXT: shll %cl, %ebx +; X86-NEXT: orl %esi, %ebx ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrdl %cl, %eax, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shrdl %cl, %edx, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: addl $-1, %eax @@ -179,63 +180,62 @@ define void @f() nounwind { ; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .LBB0_10: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: shldl $1, %esi, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: shldl $1, %edx, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: shldl $1, %ebx, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: movl %ebx, %eax -; X86-NEXT: andl $2, %eax -; X86-NEXT: shrl %eax -; X86-NEXT: leal (%eax,%edx,2), %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: shldl $1, %edi, %ebx +; X86-NEXT: shldl $1, %ebx, %edi ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: orl %esi, %ebx +; X86-NEXT: movl %esi, %edx +; X86-NEXT: andl $2, %edx +; X86-NEXT: shrl %edx +; X86-NEXT: leal (%edx,%ebx,2), %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: shldl $1, %edx, %esi +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: shldl $1, %eax, %edi -; X86-NEXT: orl %esi, %edi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $1, %eax, %edx +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: addl %eax, %eax ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: andl $3, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: sbbl %esi, %eax -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: sbbl %ecx, %ebx -; X86-NEXT: shll $30, %ebx -; X86-NEXT: movl %ebx, %eax -; X86-NEXT: sarl $30, %eax -; X86-NEXT: sarl $31, %ebx -; X86-NEXT: shrdl $1, %ebx, %eax -; X86-NEXT: movl %eax, %edi -; X86-NEXT: andl $1, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: andl $3, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: cmpl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: sbbl %edi, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: sbbl %ecx, %esi +; X86-NEXT: shll $30, %esi +; X86-NEXT: movl %esi, %edx +; X86-NEXT: sarl $30, %edx +; X86-NEXT: sarl $31, %esi +; X86-NEXT: shrdl $1, %esi, %edx +; X86-NEXT: movl %edx, %eax +; X86-NEXT: andl $1, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: movl %esi, %eax ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: movl %ebx, %edi -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload -; X86-NEXT: subl %eax, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %ebx, %esi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: sbbl %edi, %ecx +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload +; X86-NEXT: subl %edx, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %esi, %edi +; X86-NEXT: movl %edi, %ebx +; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: andl $3, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: addl $-1, %eax -; X86-NEXT: adcl $-1, %ebx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: adcl $3, %edi -; X86-NEXT: andl $3, %edi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: adcl $-1, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: adcl $3, %esi +; X86-NEXT: andl $3, %esi ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %edi, %eax -; X86-NEXT: orl %ebx, %eax +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %esi, %eax +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %edx, %eax ; X86-NEXT: jne .LBB0_10 ; X86-NEXT: .LBB0_11: # %udiv-end ; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload diff --git a/llvm/test/CodeGen/X86/pr62286.ll b/llvm/test/CodeGen/X86/pr62286.ll index 782c84408f25..1b13cee628df 100644 --- a/llvm/test/CodeGen/X86/pr62286.ll +++ b/llvm/test/CodeGen/X86/pr62286.ll @@ -8,21 +8,20 @@ define i64 @PR62286(i32 %a) { ; SSE-LABEL: PR62286: ; SSE: # %bb.0: ; SSE-NEXT: movd %edi, %xmm0 -; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,0] -; SSE-NEXT: paddd %xmm1, %xmm1 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,1,0] +; SSE-NEXT: paddd %xmm0, %xmm0 ; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; SSE-NEXT: pxor %xmm3, %xmm3 -; SSE-NEXT: pcmpgtd %xmm1, %xmm3 -; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] -; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,0] -; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE-NEXT: pcmpgtd %xmm0, %xmm2 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] -; SSE-NEXT: paddq %xmm1, %xmm0 -; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; SSE-NEXT: pxor %xmm3, %xmm3 +; SSE-NEXT: pcmpgtd %xmm0, %xmm3 +; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] +; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE-NEXT: pcmpgtd %xmm1, %xmm2 +; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE-NEXT: paddq %xmm0, %xmm1 -; SSE-NEXT: movq %xmm1, %rax +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] +; SSE-NEXT: paddq %xmm1, %xmm0 +; SSE-NEXT: movq %xmm0, %rax ; SSE-NEXT: retq ; ; AVX1-LABEL: PR62286: @@ -47,10 +46,10 @@ define i64 @PR62286(i32 %a) { ; AVX2-LABEL: PR62286: ; AVX2: # %bb.0: ; AVX2-NEXT: vmovd %edi, %xmm0 -; AVX2-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] -; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm1 +; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 diff --git a/llvm/test/CodeGen/X86/scheduler-backtracking.ll b/llvm/test/CodeGen/X86/scheduler-backtracking.ll index a9f3e8b22fb6..785b97d8c240 100644 --- a/llvm/test/CodeGen/X86/scheduler-backtracking.ll +++ b/llvm/test/CodeGen/X86/scheduler-backtracking.ll @@ -14,7 +14,6 @@ define i256 @test1(i256 %a) nounwind { ; ILP: # %bb.0: ; ILP-NEXT: movq %rdi, %rax ; ILP-NEXT: leal (%rsi,%rsi), %ecx -; ILP-NEXT: addb $3, %cl ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) @@ -23,6 +22,7 @@ define i256 @test1(i256 %a) nounwind { ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) +; ILP-NEXT: addb $3, %cl ; ILP-NEXT: movl %ecx, %edx ; ILP-NEXT: shrb $3, %dl ; ILP-NEXT: andb $7, %cl diff --git a/llvm/test/CodeGen/X86/sdiv_fix_sat.ll b/llvm/test/CodeGen/X86/sdiv_fix_sat.ll index 31297a06f809..a1cabb433d87 100644 --- a/llvm/test/CodeGen/X86/sdiv_fix_sat.ll +++ b/llvm/test/CodeGen/X86/sdiv_fix_sat.ll @@ -563,18 +563,20 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: subq $120, %rsp ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] -; X64-NEXT: psllq $32, %xmm3 +; X64-NEXT: pxor %xmm3, %xmm3 +; X64-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm0[2],xmm3[3],xmm0[3] ; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; X64-NEXT: psrad $31, %xmm2 ; X64-NEXT: psrlq $31, %xmm3 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; X64-NEXT: pxor %xmm0, %xmm0 ; X64-NEXT: pcmpgtd %xmm1, %xmm0 @@ -582,113 +584,113 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movq %xmm1, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: movl $4294967295, %edx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rdx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rdx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax -; X64-NEXT: cmovgeq %rcx, %r14 -; X64-NEXT: cmovgeq %rdx, %rbp +; X64-NEXT: cmovgeq %rdx, %r13 +; X64-NEXT: cmovgeq %rcx, %r12 ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rcx +; X64-NEXT: cmpq %r13, %rcx ; X64-NEXT: movq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r14, %rax -; X64-NEXT: cmovgeq %rcx, %rbp -; X64-NEXT: movq %rbp, %xmm0 +; X64-NEXT: sbbq %r12, %rax +; X64-NEXT: cmovgeq %rcx, %r13 +; X64-NEXT: movq %r13, %xmm0 ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rcx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax +; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r14 -; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: cmovgeq %rax, %r12 ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rcx +; X64-NEXT: cmpq %r13, %rcx ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r14, %rax -; X64-NEXT: cmovgeq %rcx, %rbp -; X64-NEXT: movq %rbp, %xmm0 +; X64-NEXT: sbbq %r12, %rax +; X64-NEXT: cmovgeq %rcx, %r13 +; X64-NEXT: movq %r13, %xmm0 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; X64-NEXT: psrlq $1, %xmm1 ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: pshufd $212, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload -; X64-NEXT: # xmm0 = mem[0,1,1,3] -; X64-NEXT: psllq $32, %xmm0 +; X64-NEXT: pxor %xmm0, %xmm0 +; X64-NEXT: punpckldq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload +; X64-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3] ; X64-NEXT: psrad $31, %xmm1 ; X64-NEXT: psrlq $31, %xmm0 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; X64-NEXT: pxor %xmm1, %xmm1 ; X64-NEXT: pcmpgtd %xmm0, %xmm1 @@ -696,94 +698,92 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rcx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax +; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r14 -; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: cmovgeq %rax, %r12 ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rcx +; X64-NEXT: cmpq %r13, %rcx ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r14, %rax -; X64-NEXT: cmovgeq %rcx, %rbp -; X64-NEXT: movq %rbp, %xmm0 +; X64-NEXT: sbbq %r12, %rax +; X64-NEXT: cmovgeq %rcx, %r13 +; X64-NEXT: movq %r13, %xmm0 ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rcx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax +; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r14 -; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: cmovgeq %rax, %r12 ; X64-NEXT: movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rax -; X64-NEXT: sbbq %r14, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill -; X64-NEXT: cmovgeq %rax, %rbp -; X64-NEXT: movq %rbp, %xmm1 +; X64-NEXT: cmpq %r13, %rax +; X64-NEXT: sbbq %r12, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill +; X64-NEXT: cmovgeq %rax, %r13 +; X64-NEXT: movq %r13, %xmm1 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X64-NEXT: psrlq $1, %xmm0 diff --git a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll index 97c3c2040b29..a80d8d8cd01b 100644 --- a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll +++ b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll @@ -46,7 +46,6 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: movq 24(%rsi), %rcx ; CHECK-NEXT: movq 32(%rsi), %rdx ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0] -; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [1,1] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2,2] ; CHECK-NEXT: .p2align 4, 0x90 @@ -54,39 +53,45 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-NEXT: xorpd %xmm3, %xmm3 -; CHECK-NEXT: movq $-1024, %rdi # imm = 0xFC00 +; CHECK-NEXT: movq $-1024, %rsi # imm = 0xFC00 ; CHECK-NEXT: movdqa %xmm0, %xmm4 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_2: # %vector.body ; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-NEXT: cmpq 1024(%rdx,%rdi), %rsi -; CHECK-NEXT: movq %rcx, %r8 -; CHECK-NEXT: sbbq 1032(%rdx,%rdi), %r8 -; CHECK-NEXT: setge %r8b -; CHECK-NEXT: movzbl %r8b, %r8d -; CHECK-NEXT: andl $1, %r8d +; CHECK-NEXT: movdqu 1024(%rdx,%rsi), %xmm5 +; CHECK-NEXT: movdqu 1040(%rdx,%rsi), %xmm6 +; CHECK-NEXT: movq %xmm5, %rdi +; CHECK-NEXT: movq %xmm6, %r8 +; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3] +; CHECK-NEXT: movq %xmm5, %r9 +; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[2,3,2,3] +; CHECK-NEXT: movq %xmm5, %r10 ; CHECK-NEXT: negq %r8 -; CHECK-NEXT: movq %r8, %xmm5 -; CHECK-NEXT: cmpq 1040(%rdx,%rdi), %rsi ; CHECK-NEXT: movq %rcx, %r8 -; CHECK-NEXT: sbbq 1048(%rdx,%rdi), %r8 +; CHECK-NEXT: sbbq %r10, %r8 ; CHECK-NEXT: setge %r8b ; CHECK-NEXT: movzbl %r8b, %r8d -; CHECK-NEXT: andl $1, %r8d ; CHECK-NEXT: negq %r8 -; CHECK-NEXT: movq %r8, %xmm6 -; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0] -; CHECK-NEXT: movdqa %xmm1, %xmm6 -; CHECK-NEXT: psllq %xmm4, %xmm6 +; CHECK-NEXT: movq %r8, %xmm5 +; CHECK-NEXT: negq %rdi +; CHECK-NEXT: movq %rcx, %rdi +; CHECK-NEXT: sbbq %r9, %rdi +; CHECK-NEXT: setge %dil +; CHECK-NEXT: movzbl %dil, %edi +; CHECK-NEXT: negq %rdi +; CHECK-NEXT: movq %rdi, %xmm6 +; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm5[0] +; CHECK-NEXT: movdqa %xmm1, %xmm5 +; CHECK-NEXT: psllq %xmm4, %xmm5 ; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[2,3,2,3] ; CHECK-NEXT: movdqa %xmm1, %xmm8 ; CHECK-NEXT: psllq %xmm7, %xmm8 -; CHECK-NEXT: movsd {{.*#+}} xmm8 = xmm6[0],xmm8[1] -; CHECK-NEXT: andpd %xmm5, %xmm8 +; CHECK-NEXT: movsd {{.*#+}} xmm8 = xmm5[0],xmm8[1] +; CHECK-NEXT: andpd %xmm6, %xmm8 ; CHECK-NEXT: orpd %xmm8, %xmm3 ; CHECK-NEXT: paddq %xmm2, %xmm4 -; CHECK-NEXT: addq $32, %rdi +; CHECK-NEXT: addq $32, %rsi ; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: # %bb.3: # %middle.block ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 @@ -101,7 +106,6 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-AVX2-NEXT: movq 24(%rsi), %rcx ; CHECK-AVX2-NEXT: movq 32(%rsi), %rdx ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,1] -; CHECK-AVX2-NEXT: xorl %esi, %esi ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm1 = [1,1] ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm2 = [2,2] ; CHECK-AVX2-NEXT: .p2align 4, 0x90 @@ -109,34 +113,40 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-AVX2-NEXT: # =>This Loop Header: Depth=1 ; CHECK-AVX2-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; CHECK-AVX2-NEXT: movq $-1024, %rdi # imm = 0xFC00 +; CHECK-AVX2-NEXT: movq $-1024, %rsi # imm = 0xFC00 ; CHECK-AVX2-NEXT: vmovdqa %xmm0, %xmm4 ; CHECK-AVX2-NEXT: .p2align 4, 0x90 ; CHECK-AVX2-NEXT: .LBB0_2: # %vector.body ; CHECK-AVX2-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-AVX2-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-AVX2-NEXT: cmpq 1024(%rdx,%rdi), %rsi -; CHECK-AVX2-NEXT: movq %rcx, %r8 -; CHECK-AVX2-NEXT: sbbq 1032(%rdx,%rdi), %r8 +; CHECK-AVX2-NEXT: vmovdqu 1024(%rdx,%rsi), %xmm5 +; CHECK-AVX2-NEXT: vmovdqu 1040(%rdx,%rsi), %xmm6 +; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm5[0],xmm6[0] +; CHECK-AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm5 = xmm5[1],xmm6[1] +; CHECK-AVX2-NEXT: vmovq %xmm5, %rdi +; CHECK-AVX2-NEXT: vpextrq $1, %xmm5, %r8 +; CHECK-AVX2-NEXT: vmovq %xmm7, %r9 +; CHECK-AVX2-NEXT: vpextrq $1, %xmm7, %r10 +; CHECK-AVX2-NEXT: negq %r10 +; CHECK-AVX2-NEXT: movq %rcx, %r10 +; CHECK-AVX2-NEXT: sbbq %r8, %r10 ; CHECK-AVX2-NEXT: setge %r8b ; CHECK-AVX2-NEXT: movzbl %r8b, %r8d -; CHECK-AVX2-NEXT: andl $1, %r8d ; CHECK-AVX2-NEXT: negq %r8 ; CHECK-AVX2-NEXT: vmovq %r8, %xmm5 -; CHECK-AVX2-NEXT: cmpq 1040(%rdx,%rdi), %rsi +; CHECK-AVX2-NEXT: negq %r9 ; CHECK-AVX2-NEXT: movq %rcx, %r8 -; CHECK-AVX2-NEXT: sbbq 1048(%rdx,%rdi), %r8 -; CHECK-AVX2-NEXT: setge %r8b -; CHECK-AVX2-NEXT: movzbl %r8b, %r8d -; CHECK-AVX2-NEXT: andl $1, %r8d -; CHECK-AVX2-NEXT: negq %r8 -; CHECK-AVX2-NEXT: vmovq %r8, %xmm6 -; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0] +; CHECK-AVX2-NEXT: sbbq %rdi, %r8 +; CHECK-AVX2-NEXT: setge %dil +; CHECK-AVX2-NEXT: movzbl %dil, %edi +; CHECK-AVX2-NEXT: negq %rdi +; CHECK-AVX2-NEXT: vmovq %rdi, %xmm6 +; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0] ; CHECK-AVX2-NEXT: vpsllvq %xmm4, %xmm1, %xmm6 ; CHECK-AVX2-NEXT: vpand %xmm6, %xmm5, %xmm5 ; CHECK-AVX2-NEXT: vpor %xmm3, %xmm5, %xmm3 ; CHECK-AVX2-NEXT: vpaddq %xmm2, %xmm4, %xmm4 -; CHECK-AVX2-NEXT: addq $32, %rdi +; CHECK-AVX2-NEXT: addq $32, %rsi ; CHECK-AVX2-NEXT: jne .LBB0_2 ; CHECK-AVX2-NEXT: # %bb.3: # %middle.block ; CHECK-AVX2-NEXT: # in Loop: Header=BB0_1 Depth=1 diff --git a/llvm/test/CodeGen/X86/vec_saddo.ll b/llvm/test/CodeGen/X86/vec_saddo.ll index cee30f5fe5da..460c5fe11f82 100644 --- a/llvm/test/CodeGen/X86/vec_saddo.ll +++ b/llvm/test/CodeGen/X86/vec_saddo.ll @@ -1045,16 +1045,12 @@ define <4 x i32> @saddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: saddo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k2 -; AVX512-NEXT: kandw %k1, %k0, %k1 -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k2, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_ssubo.ll b/llvm/test/CodeGen/X86/vec_ssubo.ll index 64ed08104885..d06993da6365 100644 --- a/llvm/test/CodeGen/X86/vec_ssubo.ll +++ b/llvm/test/CodeGen/X86/vec_ssubo.ll @@ -1062,16 +1062,12 @@ define <4 x i32> @ssubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: ssubo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm1 -; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k0 -; AVX512-NEXT: vptestnmd %xmm0, %xmm0, %k1 {%k1} -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k0, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_uaddo.ll b/llvm/test/CodeGen/X86/vec_uaddo.ll index 950e943bd902..bac118095331 100644 --- a/llvm/test/CodeGen/X86/vec_uaddo.ll +++ b/llvm/test/CodeGen/X86/vec_uaddo.ll @@ -1098,16 +1098,12 @@ define <4 x i32> @uaddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: uaddo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k2 -; AVX512-NEXT: kandw %k1, %k0, %k1 -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k2, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_usubo.ll b/llvm/test/CodeGen/X86/vec_usubo.ll index 7de972770d8d..ab75ada72f25 100644 --- a/llvm/test/CodeGen/X86/vec_usubo.ll +++ b/llvm/test/CodeGen/X86/vec_usubo.ll @@ -1145,16 +1145,12 @@ define <4 x i32> @usubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: usubo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm1 -; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k0 -; AVX512-NEXT: vptestnmd %xmm0, %xmm0, %k1 {%k1} -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k0, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll index 78797b9acc2e..27aaad6353ed 100644 --- a/llvm/test/CodeGen/X86/vector-bo-select.ll +++ b/llvm/test/CodeGen/X86/vector-bo-select.ll @@ -3137,11 +3137,11 @@ define <8 x i64> @mul_v8i64_cast_cond(i8 noundef zeroext %pb, <8 x i64> noundef ; AVX512-LABEL: mul_v8i64_cast_cond: ; AVX512: # %bb.0: ; AVX512-NEXT: kmovw %edi, %k1 -; AVX512-NEXT: vpsrlq $32, %zmm1, %zmm2 -; AVX512-NEXT: vpmuludq %zmm2, %zmm0, %zmm2 -; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm3 -; AVX512-NEXT: vpmuludq %zmm1, %zmm3, %zmm3 -; AVX512-NEXT: vpaddq %zmm3, %zmm2, %zmm2 +; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm2 +; AVX512-NEXT: vpmuludq %zmm1, %zmm2, %zmm2 +; AVX512-NEXT: vpsrlq $32, %zmm1, %zmm3 +; AVX512-NEXT: vpmuludq %zmm3, %zmm0, %zmm3 +; AVX512-NEXT: vpaddq %zmm2, %zmm3, %zmm2 ; AVX512-NEXT: vpsllq $32, %zmm2, %zmm2 ; AVX512-NEXT: vpmuludq %zmm1, %zmm0, %zmm1 ; AVX512-NEXT: vpaddq %zmm2, %zmm1, %zmm0 {%k1} diff --git a/llvm/test/CodeGen/X86/vector-fshr-128.ll b/llvm/test/CodeGen/X86/vector-fshr-128.ll index b839452725a9..3aaa9268a8d8 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-128.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-128.ll @@ -58,12 +58,12 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; SSE41-NEXT: psrlq %xmm4, %xmm1 ; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pandn %xmm3, %xmm2 -; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3] ; SSE41-NEXT: paddq %xmm0, %xmm0 -; SSE41-NEXT: movdqa %xmm0, %xmm3 -; SSE41-NEXT: psllq %xmm1, %xmm3 +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psllq %xmm2, %xmm1 +; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] ; SSE41-NEXT: psllq %xmm2, %xmm0 -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7] +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] ; SSE41-NEXT: por %xmm5, %xmm0 ; SSE41-NEXT: retq ; @@ -76,11 +76,11 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; AVX1-NEXT: vpsrlq %xmm4, %xmm1, %xmm1 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0,1,2,3],xmm1[4,5,6,7] ; AVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,3,2,3] ; AVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 -; AVX1-NEXT: vpsllq %xmm3, %xmm0, %xmm3 +; AVX1-NEXT: vpsllq %xmm2, %xmm0, %xmm3 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] ; AVX1-NEXT: vpsllq %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7] ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: retq ; @@ -158,13 +158,13 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; XOPAVX1-LABEL: var_funnnel_v2i64: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpmovsxbq {{.*#+}} xmm3 = [63,63] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubq %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshlq %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlq %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshlq %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshlq %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; @@ -366,13 +366,13 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %amt) ; XOPAVX1-LABEL: var_funnnel_v4i32: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [31,31,31,31] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubd %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshld %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshld %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshld %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshld %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; @@ -646,26 +646,26 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt) ; XOPAVX1-LABEL: var_funnnel_v8i16: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubw %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshlw %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddw %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlw %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshlw %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubw %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshlw %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_funnnel_v8i16: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastw {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15] -; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX2-NEXT: vpsubw %xmm4, %xmm5, %xmm4 -; XOPAVX2-NEXT: vpshlw %xmm4, %xmm1, %xmm1 -; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX2-NEXT: vpaddw %xmm0, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpshlw %xmm2, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpshlw %xmm4, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX2-NEXT: vpsubw %xmm2, %xmm3, %xmm2 +; XOPAVX2-NEXT: vpshlw %xmm2, %xmm1, %xmm1 ; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: retq ; @@ -995,26 +995,26 @@ define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) ; XOPAVX1-LABEL: var_funnnel_v16i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubb %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshlb %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlb %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshlb %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshlb %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_funnnel_v16i8: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastb {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] -; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX2-NEXT: vpsubb %xmm4, %xmm5, %xmm4 -; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1 -; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpshlb %xmm4, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX2-NEXT: vpsubb %xmm2, %xmm3, %xmm2 +; XOPAVX2-NEXT: vpshlb %xmm2, %xmm1, %xmm1 ; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll index 7b6b0ea83c7e..fc65f759f5fb 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-256.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll @@ -486,22 +486,22 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> % ; XOPAVX2-LABEL: var_funnnel_v16i16: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastw {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; XOPAVX2-NEXT: vpand %ymm3, %ymm2, %ymm4 +; XOPAVX2-NEXT: vpandn %ymm3, %ymm2, %ymm4 ; XOPAVX2-NEXT: vextracti128 $1, %ymm4, %xmm5 -; XOPAVX2-NEXT: vpxor %xmm6, %xmm6, %xmm6 -; XOPAVX2-NEXT: vpsubw %xmm5, %xmm6, %xmm5 -; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm7 -; XOPAVX2-NEXT: vpshlw %xmm5, %xmm7, %xmm5 -; XOPAVX2-NEXT: vpsubw %xmm4, %xmm6, %xmm4 -; XOPAVX2-NEXT: vpshlw %xmm4, %xmm1, %xmm1 -; XOPAVX2-NEXT: vinserti128 $1, %xmm5, %ymm1, %ymm1 -; XOPAVX2-NEXT: vpandn %ymm3, %ymm2, %ymm2 -; XOPAVX2-NEXT: vextracti128 $1, %ymm2, %xmm3 ; XOPAVX2-NEXT: vpaddw %ymm0, %ymm0, %ymm0 -; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm4 -; XOPAVX2-NEXT: vpshlw %xmm3, %xmm4, %xmm3 -; XOPAVX2-NEXT: vpshlw %xmm2, %xmm0, %xmm0 -; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0 +; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm6 +; XOPAVX2-NEXT: vpshlw %xmm5, %xmm6, %xmm5 +; XOPAVX2-NEXT: vpshlw %xmm4, %xmm0, %xmm0 +; XOPAVX2-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm0 +; XOPAVX2-NEXT: vpand %ymm3, %ymm2, %ymm2 +; XOPAVX2-NEXT: vextracti128 $1, %ymm2, %xmm3 +; XOPAVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; XOPAVX2-NEXT: vpsubw %xmm3, %xmm4, %xmm3 +; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm5 +; XOPAVX2-NEXT: vpshlw %xmm3, %xmm5, %xmm3 +; XOPAVX2-NEXT: vpsubw %xmm2, %xmm4, %xmm2 +; XOPAVX2-NEXT: vpshlw %xmm2, %xmm1, %xmm1 +; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1 ; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq %res = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %amt) diff --git a/llvm/test/CodeGen/X86/vector-fshr-sub128.ll b/llvm/test/CodeGen/X86/vector-fshr-sub128.ll index 0426c48aecfc..a6067a960fc0 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-sub128.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-sub128.ll @@ -185,13 +185,13 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %amt) ; XOPAVX1-LABEL: var_funnnel_v2i32: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [31,31,31,31] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubd %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshld %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshld %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshld %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshld %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll index c54da38ef10c..75baba5f35f7 100644 --- a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll +++ b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll @@ -927,9 +927,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; SSE2-LABEL: constant_shift_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psllq $7, %xmm1 -; SSE2-NEXT: paddq %xmm0, %xmm0 -; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE2-NEXT: paddq %xmm0, %xmm1 +; SSE2-NEXT: psllq $7, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSE41-LABEL: constant_shift_v2i64: @@ -975,9 +975,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; X86-SSE-LABEL: constant_shift_v2i64: ; X86-SSE: # %bb.0: ; X86-SSE-NEXT: movdqa %xmm0, %xmm1 -; X86-SSE-NEXT: psllq $7, %xmm1 -; X86-SSE-NEXT: paddq %xmm0, %xmm0 -; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; X86-SSE-NEXT: paddq %xmm0, %xmm1 +; X86-SSE-NEXT: psllq $7, %xmm0 +; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X86-SSE-NEXT: retl %shift = shl <2 x i64> %a, ret <2 x i64> %shift -- GitLab From 8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 Mon Sep 17 00:00:00 2001 From: Bjorn Pettersson Date: Tue, 16 Apr 2024 18:53:19 +0200 Subject: [PATCH 050/301] [DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932) Avoid turning a BUILD_VECTOR that can be recognized as "all zeros", "all ones" or "constant" into something that depends on freeze(undef), as that would destroy those properties. Instead we replace undef by 0/-1 in such vectors, making it possible to fold away the freeze. We typically use -1 if the BUILD_VECTOR would identify as "all ones", and otherwise we use the value 0. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 20 +++++++ llvm/test/CodeGen/X86/freeze-binary.ll | 56 ++----------------- 2 files changed, 26 insertions(+), 50 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index aa746f1c7b7b..f984d4b39596 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15452,6 +15452,26 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { N0.getOpcode() == ISD::BUILD_PAIR || N0.getOpcode() == ISD::CONCAT_VECTORS; + // Avoid turning a BUILD_VECTOR that can be recognized as "all zeros", "all + // ones" or "constant" into something that depends on FrozenUndef. We can + // instead pick undef values to keep those properties, while at the same time + // folding away the freeze. + // If we implement a more general solution for folding away freeze(undef) in + // the future, then this special handling can be removed. + if (N0.getOpcode() == ISD::BUILD_VECTOR) { + SDLoc DL(N0); + MVT VT = N0.getSimpleValueType(); + if (llvm::ISD::isBuildVectorAllOnes(N0.getNode())) + return DAG.getAllOnesConstant(DL, VT); + if (llvm::ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { + SmallVector NewVecC; + for (const SDValue &Op : N0->op_values()) + NewVecC.push_back( + Op.isUndef() ? DAG.getConstant(0, DL, Op.getValueType()) : Op); + return DAG.getBuildVector(VT, DL, NewVecC); + } + } + SmallSetVector MaybePoisonOperands; for (SDValue Op : N0->ops()) { if (DAG.isGuaranteedNotToBeUndefOrPoison(Op, /*PoisonOnly*/ false, diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll index d75fc5318bd8..b212e9438e1b 100644 --- a/llvm/test/CodeGen/X86/freeze-binary.ll +++ b/llvm/test/CodeGen/X86/freeze-binary.ll @@ -202,27 +202,13 @@ define <4 x i32> @freeze_add_vec(<4 x i32> %a0) nounwind { define <4 x i32> @freeze_add_vec_undef(<4 x i32> %a0) nounwind { ; X86-LABEL: freeze_add_vec_undef: ; X86: # %bb.0: -; X86-NEXT: pushl %ebp -; X86-NEXT: movl %esp, %ebp -; X86-NEXT: andl $-16, %esp -; X86-NEXT: subl $32, %esp -; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) -; X86-NEXT: movl $3, {{[0-9]+}}(%esp) -; X86-NEXT: movl $2, {{[0-9]+}}(%esp) -; X86-NEXT: movl $1, (%esp) -; X86-NEXT: paddd (%esp), %xmm0 ; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: movl %ebp, %esp -; X86-NEXT: popl %ebp +; X86-NEXT: paddd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_add_vec_undef: ; X64: # %bb.0: -; X64-NEXT: movabsq $8589934593, %rax # imm = 0x200000001 -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) -; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp) -; X64-NEXT: movl $3, -{{[0-9]+}}(%rsp) -; X64-NEXT: vpaddd -{{[0-9]+}}(%rsp), %xmm0, %xmm0 +; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpaddd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: retq %x = add <4 x i32> %a0, @@ -287,27 +273,13 @@ define <4 x i32> @freeze_sub_vec(<4 x i32> %a0) nounwind { define <4 x i32> @freeze_sub_vec_undef(<4 x i32> %a0) nounwind { ; X86-LABEL: freeze_sub_vec_undef: ; X86: # %bb.0: -; X86-NEXT: pushl %ebp -; X86-NEXT: movl %esp, %ebp -; X86-NEXT: andl $-16, %esp -; X86-NEXT: subl $32, %esp -; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) -; X86-NEXT: movl $3, {{[0-9]+}}(%esp) -; X86-NEXT: movl $2, {{[0-9]+}}(%esp) -; X86-NEXT: movl $1, (%esp) -; X86-NEXT: psubd (%esp), %xmm0 ; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: movl %ebp, %esp -; X86-NEXT: popl %ebp +; X86-NEXT: psubd {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_sub_vec_undef: ; X64: # %bb.0: -; X64-NEXT: movabsq $8589934593, %rax # imm = 0x200000001 -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) -; X64-NEXT: movl %eax, -{{[0-9]+}}(%rsp) -; X64-NEXT: movl $3, -{{[0-9]+}}(%rsp) -; X64-NEXT: vpsubd -{{[0-9]+}}(%rsp), %xmm0, %xmm0 +; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpsubd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: retq %x = sub <4 x i32> %a0, @@ -373,29 +345,13 @@ define <8 x i16> @freeze_mul_vec(<8 x i16> %a0) nounwind { define <8 x i16> @freeze_mul_vec_undef(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_mul_vec_undef: ; X86: # %bb.0: -; X86-NEXT: pushl %ebp -; X86-NEXT: movl %esp, %ebp -; X86-NEXT: andl $-16, %esp -; X86-NEXT: subl $32, %esp -; X86-NEXT: movw %ax, {{[0-9]+}}(%esp) -; X86-NEXT: movw $1, {{[0-9]+}}(%esp) -; X86-NEXT: movl $196612, {{[0-9]+}}(%esp) # imm = 0x30004 -; X86-NEXT: movl $262147, {{[0-9]+}}(%esp) # imm = 0x40003 -; X86-NEXT: movl $131073, (%esp) # imm = 0x20001 -; X86-NEXT: pmullw (%esp), %xmm0 ; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 -; X86-NEXT: movl %ebp, %esp -; X86-NEXT: popl %ebp +; X86-NEXT: pmullw {{\.?LCPI[0-9]+_[0-9]+}}, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_mul_vec_undef: ; X64: # %bb.0: -; X64-NEXT: movabsq $1125912791875585, %rax # imm = 0x4000300020001 -; X64-NEXT: movq %rax, -{{[0-9]+}}(%rsp) -; X64-NEXT: movw %ax, -{{[0-9]+}}(%rsp) -; X64-NEXT: movw $1, -{{[0-9]+}}(%rsp) -; X64-NEXT: movl $196612, -{{[0-9]+}}(%rsp) # imm = 0x30004 -; X64-NEXT: vpmullw -{{[0-9]+}}(%rsp), %xmm0, %xmm0 +; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: vpmullw {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 ; X64-NEXT: retq %x = mul <8 x i16> %a0, -- GitLab From a670cdadca54910a8e65d5521f2119337fb0bd03 Mon Sep 17 00:00:00 2001 From: Jonathan Thackray Date: Fri, 26 Apr 2024 13:04:35 +0100 Subject: [PATCH 051/301] [AArch64] Add support for Neoverse-N3, Neoverse-V3 and Neoverse-V3AE (#90143) Neoverse-N3, Neoverse-V3 and Neoverse-V3AE are Armv9.2 AArch64 CPUs. Technical Reference Manual for Neoverse-N3: https://developer.arm.com/documentation/107997/latest/ Technical Reference Manual for Neoverse-V3: https://developer.arm.com/documentation/107734/latest/ Technical Reference Manual for Neoverse-V3AE: https://developer.arm.com/documentation/101595/latest/ --- clang/docs/ReleaseNotes.rst | 3 + clang/test/Driver/aarch64-mcpu.c | 6 ++ clang/test/Misc/target-invalid-cpu-note.c | 4 +- llvm/docs/ReleaseNotes.rst | 3 +- .../llvm/TargetParser/AArch64TargetParser.h | 21 +++++++ llvm/lib/Target/AArch64/AArch64Processors.td | 45 ++++++++++++++ llvm/lib/Target/AArch64/AArch64Subtarget.cpp | 2 + llvm/lib/TargetParser/Host.cpp | 3 + .../TargetParser/TargetParserTest.cpp | 58 ++++++++++++++++++- 9 files changed, 141 insertions(+), 4 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 1576f681707d..92563262cc67 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -633,6 +633,9 @@ Arm and AArch64 Support * Arm Cortex-A78AE (cortex-a78ae). * Arm Cortex-A520AE (cortex-a520ae). * Arm Cortex-A720AE (cortex-a720ae). + * Arm Neoverse-N3 (neoverse-n3). + * Arm Neoverse-V3 (neoverse-v3). + * Arm Neoverse-V3AE (neoverse-v3ae). Android Support ^^^^^^^^^^^^^^^ diff --git a/clang/test/Driver/aarch64-mcpu.c b/clang/test/Driver/aarch64-mcpu.c index 77ba43122b24..ad4a5f9ac6fb 100644 --- a/clang/test/Driver/aarch64-mcpu.c +++ b/clang/test/Driver/aarch64-mcpu.c @@ -64,10 +64,16 @@ // NEOVERSE-V1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v1" // RUN: %clang --target=aarch64 -mcpu=neoverse-v2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V2 %s // NEOVERSE-V2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v2" +// RUN: %clang --target=aarch64 -mcpu=neoverse-v3 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V3 %s +// NEOVERSE-V3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v3" +// RUN: %clang --target=aarch64 -mcpu=neoverse-v3ae -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-V3AE %s +// NEOVERSE-V3AE: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-v3ae" // RUN: %clang --target=aarch64 -mcpu=neoverse-n1 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N1 %s // NEOVERSE-N1: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n1" // RUN: %clang --target=aarch64 -mcpu=neoverse-n2 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N2 %s // NEOVERSE-N2: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n2" +// RUN: %clang --target=aarch64 -mcpu=neoverse-n3 -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-N3 %s +// NEOVERSE-N3: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-n3" // RUN: %clang --target=aarch64 -mcpu=neoverse-512tvb -### -c %s 2>&1 | FileCheck -check-prefix=NEOVERSE-512TVB %s // NEOVERSE-512TVB: "-cc1"{{.*}} "-triple" "aarch64{{.*}}" "-target-cpu" "neoverse-512tvb" // RUN: %clang --target=aarch64 -mcpu=cortex-a520 -### -c %s 2>&1 | FileCheck -check-prefix=CORTEX-A520 %s diff --git a/clang/test/Misc/target-invalid-cpu-note.c b/clang/test/Misc/target-invalid-cpu-note.c index 9c91c4157cd6..21d80b713450 100644 --- a/clang/test/Misc/target-invalid-cpu-note.c +++ b/clang/test/Misc/target-invalid-cpu-note.c @@ -5,11 +5,11 @@ // RUN: not %clang_cc1 -triple arm64--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix AARCH64 // AARCH64: error: unknown target CPU 'not-a-cpu' -// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple arm64--- -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE_AARCH64 // TUNE_AARCH64: error: unknown target CPU 'not-a-cpu' -// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-512tvb, neoverse-v1, neoverse-v2, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} +// TUNE_AARCH64-NEXT: note: valid target CPU values are: cortex-a34, cortex-a35, cortex-a53, cortex-a55, cortex-a510, cortex-a520, cortex-a520ae, cortex-a57, cortex-a65, cortex-a65ae, cortex-a72, cortex-a73, cortex-a75, cortex-a76, cortex-a76ae, cortex-a77, cortex-a78, cortex-a78ae, cortex-a78c, cortex-a710, cortex-a715, cortex-a720, cortex-a720ae, cortex-r82, cortex-x1, cortex-x1c, cortex-x2, cortex-x3, cortex-x4, neoverse-e1, neoverse-n1, neoverse-n2, neoverse-n3, neoverse-512tvb, neoverse-v1, neoverse-v2, neoverse-v3, neoverse-v3ae, cyclone, apple-a7, apple-a8, apple-a9, apple-a10, apple-a11, apple-a12, apple-a13, apple-a14, apple-a15, apple-a16, apple-a17, apple-m1, apple-m2, apple-m3, apple-s4, apple-s5, exynos-m3, exynos-m4, exynos-m5, falkor, saphira, kryo, thunderx2t99, thunderx3t110, thunderx, thunderxt88, thunderxt81, thunderxt83, tsv110, a64fx, carmel, ampere1, ampere1a, ampere1b, cobalt-100, grace{{$}} // RUN: not %clang_cc1 -triple i386--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix X86 // X86: error: unknown target CPU 'not-a-cpu' diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 6ef6ec20da67..a83b8bb79a1c 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -69,7 +69,8 @@ Changes to Interprocedural Optimizations Changes to the AArch64 Backend ------------------------------ -* Added support for Cortex-A78AE, Cortex-A520AE and Cortex-A720AE CPUs. +* Added support for Cortex-A78AE, Cortex-A520AE, Cortex-A720AE, + Neoverse-N3, Neoverse-V3 and Neoverse-V3AE CPUs. Changes to the AMDGPU Backend ----------------------------- diff --git a/llvm/include/llvm/TargetParser/AArch64TargetParser.h b/llvm/include/llvm/TargetParser/AArch64TargetParser.h index 44aa886b61b6..0d1cfd152151 100644 --- a/llvm/include/llvm/TargetParser/AArch64TargetParser.h +++ b/llvm/include/llvm/TargetParser/AArch64TargetParser.h @@ -677,6 +677,13 @@ inline constexpr CpuInfo CpuInfos[] = { AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE, AArch64::AEK_SB, AArch64::AEK_SSBS, AArch64::AEK_SVE, AArch64::AEK_SVE2, AArch64::AEK_SVE2BITPERM})}, + {"neoverse-n3", ARMV9_2A, + AArch64::ExtensionBitset({AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_FP16FML, AArch64::AEK_PAUTH, + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, + AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_PROFILE, AArch64::AEK_PERFMON})}, {"neoverse-512tvb", ARMV8_4A, AArch64::ExtensionBitset( {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_SHA3, @@ -697,6 +704,20 @@ inline constexpr CpuInfo CpuInfos[] = { AArch64::AEK_FP16, AArch64::AEK_BF16, AArch64::AEK_RAND, AArch64::AEK_DOTPROD, AArch64::AEK_PROFILE, AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, AArch64::AEK_I8MM, AArch64::AEK_MTE})}, + {"neoverse-v3", ARMV9_2A, + AArch64::ExtensionBitset( + {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64, + AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_FP16FML})}, + {"neoverse-v3ae", ARMV9_2A, + (AArch64::ExtensionBitset( + {AArch64::AEK_PROFILE, AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, AArch64::AEK_LS64, + AArch64::AEK_BRBE, AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_FP16FML}))}, {"cyclone", ARMV8A, AArch64::ExtensionBitset( {AArch64::AEK_AES, AArch64::AEK_SHA2, AArch64::AEK_NONE})}, diff --git a/llvm/lib/Target/AArch64/AArch64Processors.td b/llvm/lib/Target/AArch64/AArch64Processors.td index c50a8200dd89..8772e51bf0ab 100644 --- a/llvm/lib/Target/AArch64/AArch64Processors.td +++ b/llvm/lib/Target/AArch64/AArch64Processors.td @@ -447,6 +447,15 @@ def TuneNeoverseN2 : SubtargetFeature<"neoversen2", "ARMProcFamily", "NeoverseN2 FeatureEnableSelectOptimize, FeaturePredictableSelectIsExpensive]>; +def TuneNeoverseN3 : SubtargetFeature<"neoversen3", "ARMProcFamily", "NeoverseN3", + "Neoverse N3 ARM processors", [ + FeatureFuseAES, + FeaturePostRAScheduler, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + def TuneNeoverse512TVB : SubtargetFeature<"neoverse512tvb", "ARMProcFamily", "Neoverse512TVB", "Neoverse 512-TVB ARM processors", [ FeatureFuseAES, @@ -476,6 +485,24 @@ def TuneNeoverseV2 : SubtargetFeature<"neoversev2", "ARMProcFamily", "NeoverseV2 FeatureEnableSelectOptimize, FeaturePredictableSelectIsExpensive]>; +def TuneNeoverseV3 : SubtargetFeature<"neoversev3", "ARMProcFamily", "NeoverseV3", + "Neoverse V3 ARM processors", [ + FeatureFuseAES, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + +def TuneNeoverseV3AE : SubtargetFeature<"neoversev3AE", "ARMProcFamily", "NeoverseV3", + "Neoverse V3AE ARM processors", [ + FeatureFuseAES, + FeatureALULSLFast, + FeatureFuseAdrpAdd, + FeaturePostRAScheduler, + FeatureEnableSelectOptimize, + FeaturePredictableSelectIsExpensive]>; + def TuneSaphira : SubtargetFeature<"saphira", "ARMProcFamily", "Saphira", "Qualcomm Saphira processors", [ FeaturePostRAScheduler, @@ -715,6 +742,10 @@ def ProcessorFeatures { FeatureMatMulInt8, FeatureMTE, FeatureSVE2, FeatureSVE2BitPerm, FeatureTRBE, FeaturePerfMon]; + list NeoverseN3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML, + FeatureFullFP16, FeatureMTE, FeaturePerfMon, + FeatureRandGen, FeatureSPE, FeatureSPE_EEF, + FeatureSVE2BitPerm]; list Neoverse512TVB = [HasV8_4aOps, FeatureBF16, FeatureCacheDeepPersist, FeatureCrypto, FeatureFPARMv8, FeatureFP16FML, FeatureFullFP16, FeatureMatMulInt8, FeatureNEON, @@ -729,6 +760,14 @@ def ProcessorFeatures { FeaturePerfMon, FeatureETE, FeatureMatMulInt8, FeatureNEON, FeatureSVE2BitPerm, FeatureFP16FML, FeatureMTE, FeatureRandGen]; + list NeoverseV3 = [HasV9_2aOps, FeatureETE, FeatureFP16FML, + FeatureFullFP16, FeatureLS64, FeatureMTE, + FeaturePerfMon, FeatureRandGen, FeatureSPE, + FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE]; + list NeoverseV3AE = [HasV9_2aOps, FeatureETE, FeatureFP16FML, + FeatureFullFP16, FeatureLS64, FeatureMTE, + FeaturePerfMon, FeatureRandGen, FeatureSPE, + FeatureSPE_EEF, FeatureSVE2BitPerm, FeatureBRBE]; list Saphira = [HasV8_4aOps, FeatureCrypto, FeatureFPARMv8, FeatureNEON, FeatureSPE, FeaturePerfMon]; list ThunderX = [HasV8_0aOps, FeatureCRC, FeatureCrypto, @@ -831,12 +870,18 @@ def : ProcessorModel<"neoverse-n1", NeoverseN1Model, ProcessorFeatures.NeoverseN1, [TuneNeoverseN1]>; def : ProcessorModel<"neoverse-n2", NeoverseN2Model, ProcessorFeatures.NeoverseN2, [TuneNeoverseN2]>; +def : ProcessorModel<"neoverse-n3", NeoverseN2Model, + ProcessorFeatures.NeoverseN3, [TuneNeoverseN3]>; def : ProcessorModel<"neoverse-512tvb", NeoverseV1Model, ProcessorFeatures.Neoverse512TVB, [TuneNeoverse512TVB]>; def : ProcessorModel<"neoverse-v1", NeoverseV1Model, ProcessorFeatures.NeoverseV1, [TuneNeoverseV1]>; def : ProcessorModel<"neoverse-v2", NeoverseV2Model, ProcessorFeatures.NeoverseV2, [TuneNeoverseV2]>; +def : ProcessorModel<"neoverse-v3", NeoverseV2Model, + ProcessorFeatures.NeoverseV3, [TuneNeoverseV3]>; +def : ProcessorModel<"neoverse-v3ae", NeoverseV2Model, + ProcessorFeatures.NeoverseV3AE, [TuneNeoverseV3AE]>; def : ProcessorModel<"exynos-m3", ExynosM3Model, ProcessorFeatures.ExynosM3, [TuneExynosM3]>; def : ProcessorModel<"exynos-m4", ExynosM4Model, ProcessorFeatures.ExynosM4, diff --git a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp index ef09a3cde495..7d34dd1c7768 100644 --- a/llvm/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/llvm/lib/Target/AArch64/AArch64Subtarget.cpp @@ -234,7 +234,9 @@ void AArch64Subtarget::initializeProperties(bool HasMinSize) { MaxBytesForLoopAlignment = 16; break; case NeoverseN2: + case NeoverseN3: case NeoverseV2: + case NeoverseV3: PrefFunctionAlignment = Align(16); PrefLoopAlignment = Align(32); MaxBytesForLoopAlignment = 16; diff --git a/llvm/lib/TargetParser/Host.cpp b/llvm/lib/TargetParser/Host.cpp index d2c9bae97364..0a93b06f40c2 100644 --- a/llvm/lib/TargetParser/Host.cpp +++ b/llvm/lib/TargetParser/Host.cpp @@ -245,8 +245,11 @@ StringRef sys::detail::getHostCPUNameForARM(StringRef ProcCpuinfoContent) { .Case("0xd4a", "neoverse-e1") .Case("0xd0c", "neoverse-n1") .Case("0xd49", "neoverse-n2") + .Case("0xd8e", "neoverse-n3") .Case("0xd40", "neoverse-v1") .Case("0xd4f", "neoverse-v2") + .Case("0xd84", "neoverse-v3") + .Case("0xd83", "neoverse-v3ae") .Default("generic"); } diff --git a/llvm/unittests/TargetParser/TargetParserTest.cpp b/llvm/unittests/TargetParser/TargetParserTest.cpp index 2c72a7229b52..75e235008b4f 100644 --- a/llvm/unittests/TargetParser/TargetParserTest.cpp +++ b/llvm/unittests/TargetParser/TargetParserTest.cpp @@ -1345,6 +1345,44 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_JSCVT, AArch64::AEK_FCMA, AArch64::AEK_PAUTH}), "9-A"), + ARMCPUTestParams( + "neoverse-v3", "armv9.2-a", "neon-fp-armv8", + AArch64::ExtensionBitset( + {AArch64::AEK_BF16, AArch64::AEK_I8MM, + AArch64::AEK_SVE, AArch64::AEK_SVE2, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RCPC, + AArch64::AEK_RAS, AArch64::AEK_CRC, + AArch64::AEK_FP, AArch64::AEK_PROFILE, + AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_LS64, AArch64::AEK_BRBE, + AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, + AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, + AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, + AArch64::AEK_FCMA}), + "9.2-A"), + ARMCPUTestParams( + "neoverse-v3ae", "armv9.2-a", "neon-fp-armv8", + AArch64::ExtensionBitset( + {AArch64::AEK_BF16, AArch64::AEK_I8MM, + AArch64::AEK_SVE, AArch64::AEK_SVE2, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RCPC, + AArch64::AEK_RAS, AArch64::AEK_CRC, + AArch64::AEK_FP, AArch64::AEK_PROFILE, + AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_LS64, AArch64::AEK_BRBE, + AArch64::AEK_PAUTH, AArch64::AEK_FLAGM, + AArch64::AEK_PERFMON, AArch64::AEK_RAND, + AArch64::AEK_SVE2BITPERM, AArch64::AEK_FP16FML, + AArch64::AEK_PROFILE, AArch64::AEK_JSCVT, + AArch64::AEK_FCMA}), + "9.2-A"), ARMCPUTestParams( "cortex-r82", "armv8-r", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( @@ -1636,6 +1674,24 @@ INSTANTIATE_TEST_SUITE_P( AArch64::AEK_FCMA, AArch64::AEK_PAUTH, AArch64::AEK_FP16FML}), "9-A"), + ARMCPUTestParams( + "neoverse-n3", "armv9.2-a", "neon-fp-armv8", + AArch64::ExtensionBitset( + {AArch64::AEK_BF16, AArch64::AEK_I8MM, + AArch64::AEK_SVE, AArch64::AEK_SVE2, + AArch64::AEK_FP16, AArch64::AEK_DOTPROD, + AArch64::AEK_LSE, AArch64::AEK_RDM, + AArch64::AEK_SIMD, AArch64::AEK_RCPC, + AArch64::AEK_RAS, AArch64::AEK_CRC, + AArch64::AEK_FP, AArch64::AEK_PROFILE, + AArch64::AEK_MTE, AArch64::AEK_SSBS, + AArch64::AEK_SB, AArch64::AEK_PREDRES, + AArch64::AEK_FCMA, AArch64::AEK_PAUTH, + AArch64::AEK_FLAGM, AArch64::AEK_PERFMON, + AArch64::AEK_RAND, AArch64::AEK_SVE2BITPERM, + AArch64::AEK_FP16FML, AArch64::AEK_PROFILE, + AArch64::AEK_JSCVT}), + "9.2-A"), ARMCPUTestParams( "ampere1", "armv8.6-a", "crypto-neon-fp-armv8", AArch64::ExtensionBitset( @@ -1750,7 +1806,7 @@ INSTANTIATE_TEST_SUITE_P( ARMCPUTestParams::PrintToStringParamName); // Note: number of CPUs includes aliases. -static constexpr unsigned NumAArch64CPUArchs = 72; +static constexpr unsigned NumAArch64CPUArchs = 75; TEST(TargetParserTest, testAArch64CPUArchList) { SmallVector List; -- GitLab From 134e645645832af6fe9c15d121551de989aa81cf Mon Sep 17 00:00:00 2001 From: Dan Klishch <30951924+DanShaders@users.noreply.github.com> Date: Fri, 26 Apr 2024 08:14:47 -0400 Subject: [PATCH 052/301] [clang][X86] Fix -Wundef warning in cpuid.h (#89842) Caught by compiling a project (SerenityOS) that uses compiler-rt and not silencing warnings from system headers. --- clang/lib/Headers/cpuid.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/clang/lib/Headers/cpuid.h b/clang/lib/Headers/cpuid.h index 0bb9912b465f..bb7692efb78f 100644 --- a/clang/lib/Headers/cpuid.h +++ b/clang/lib/Headers/cpuid.h @@ -10,7 +10,7 @@ #ifndef __CPUID_H #define __CPUID_H -#if !(__x86_64__ || __i386__) +#if !defined(__x86_64__) && !defined(__i386__) #error this header is for x86 only #endif @@ -256,7 +256,7 @@ #define bit_AVX10_256 0x00020000 #define bit_AVX10_512 0x00040000 -#if __i386__ +#ifdef __i386__ #define __cpuid(__leaf, __eax, __ebx, __ecx, __edx) \ __asm("cpuid" : "=a"(__eax), "=b" (__ebx), "=c"(__ecx), "=d"(__edx) \ : "0"(__leaf)) @@ -285,7 +285,7 @@ static __inline unsigned int __get_cpuid_max (unsigned int __leaf, unsigned int *__sig) { unsigned int __eax, __ebx, __ecx, __edx; -#if __i386__ +#ifdef __i386__ int __cpuid_supported; __asm(" pushfl\n" -- GitLab From 39f1b2de6f6d45de226292fd24e2a2ceaab6c82f Mon Sep 17 00:00:00 2001 From: Bjorn Pettersson Date: Fri, 15 Mar 2024 14:20:26 +0100 Subject: [PATCH 053/301] Add test cases for SELECT->AND miscompiles in DAGCombiner Adding reproducers for github issues #84653 and #85190. --- llvm/test/CodeGen/RISCV/pr84653_pr85190.ll | 95 ++++++++++++++++++++++ 1 file changed, 95 insertions(+) create mode 100644 llvm/test/CodeGen/RISCV/pr84653_pr85190.ll diff --git a/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll b/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll new file mode 100644 index 000000000000..3fa494e1a57d --- /dev/null +++ b/llvm/test/CodeGen/RISCV/pr84653_pr85190.ll @@ -0,0 +1,95 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=riscv64 | FileCheck %s --check-prefixes=CHECK-NOZBB +; RUN: llc < %s -mtriple=riscv64 -mattr=+zbb | FileCheck %s --check-prefixes=CHECK-ZBB + +; This test case miscompiled for ZBB (DAGCombiner turned a SELECT into a more +; poisonous AND operation). +define i1 @pr84653(i32 %x) { +; CHECK-NOZBB-LABEL: pr84653: +; CHECK-NOZBB: # %bb.0: +; CHECK-NOZBB-NEXT: sext.w a1, a0 +; CHECK-NOZBB-NEXT: sgtz a2, a1 +; CHECK-NOZBB-NEXT: lui a3, 524288 +; CHECK-NOZBB-NEXT: addi a3, a3, -1 +; CHECK-NOZBB-NEXT: xor a0, a0, a3 +; CHECK-NOZBB-NEXT: sext.w a0, a0 +; CHECK-NOZBB-NEXT: slt a0, a0, a1 +; CHECK-NOZBB-NEXT: and a0, a2, a0 +; CHECK-NOZBB-NEXT: ret +; +; CHECK-ZBB-LABEL: pr84653: +; CHECK-ZBB: # %bb.0: +; CHECK-ZBB-NEXT: sext.w a1, a0 +; CHECK-ZBB-NEXT: lui a2, 524288 +; CHECK-ZBB-NEXT: addi a2, a2, -1 +; CHECK-ZBB-NEXT: xor a0, a0, a2 +; CHECK-ZBB-NEXT: sext.w a0, a0 +; CHECK-ZBB-NEXT: max a0, a0, zero +; CHECK-ZBB-NEXT: slt a0, a0, a1 +; CHECK-ZBB-NEXT: ret + %cmp1 = icmp sgt i32 %x, 0 + %sub = sub nsw i32 2147483647, %x ; 0x7fffffff + %cmp2 = icmp sgt i32 %x, %sub + %r = select i1 %cmp1, i1 %cmp2, i1 false + ret i1 %r +} + +; This test case miscompiled for ZBB (DAGCombiner turned a SELECT into a more +; poisonous AND operation). +define i1 @pr85190(i64 %a) { +; CHECK-NOZBB-LABEL: pr85190: +; CHECK-NOZBB: # %bb.0: +; CHECK-NOZBB-NEXT: ori a1, a0, 7 +; CHECK-NOZBB-NEXT: slti a2, a0, 0 +; CHECK-NOZBB-NEXT: li a3, -1 +; CHECK-NOZBB-NEXT: slli a3, a3, 63 +; CHECK-NOZBB-NEXT: sub a3, a3, a1 +; CHECK-NOZBB-NEXT: slt a0, a0, a3 +; CHECK-NOZBB-NEXT: and a0, a2, a0 +; CHECK-NOZBB-NEXT: ret +; +; CHECK-ZBB-LABEL: pr85190: +; CHECK-ZBB: # %bb.0: +; CHECK-ZBB-NEXT: ori a1, a0, 7 +; CHECK-ZBB-NEXT: li a2, -1 +; CHECK-ZBB-NEXT: slli a2, a2, 63 +; CHECK-ZBB-NEXT: sub a2, a2, a1 +; CHECK-ZBB-NEXT: slt a0, a0, a2 +; CHECK-ZBB-NEXT: ret + %or = or i64 %a, 7 + %cmp1 = icmp slt i64 %a, 0 + %sub = sub nsw i64 -9223372036854775808, %or ; 0x8000000000000000 + %cmp2 = icmp sgt i64 %sub, %a + %res = select i1 %cmp1, i1 %cmp2, i1 false + ret i1 %res +} + +define i1 @select_to_or(i32 %x) { +; CHECK-NOZBB-LABEL: select_to_or: +; CHECK-NOZBB: # %bb.0: +; CHECK-NOZBB-NEXT: sext.w a1, a0 +; CHECK-NOZBB-NEXT: sgtz a2, a1 +; CHECK-NOZBB-NEXT: lui a3, 524288 +; CHECK-NOZBB-NEXT: addi a3, a3, -1 +; CHECK-NOZBB-NEXT: xor a0, a0, a3 +; CHECK-NOZBB-NEXT: sext.w a0, a0 +; CHECK-NOZBB-NEXT: slt a0, a0, a1 +; CHECK-NOZBB-NEXT: or a0, a2, a0 +; CHECK-NOZBB-NEXT: ret +; +; CHECK-ZBB-LABEL: select_to_or: +; CHECK-ZBB: # %bb.0: +; CHECK-ZBB-NEXT: sext.w a1, a0 +; CHECK-ZBB-NEXT: lui a2, 524288 +; CHECK-ZBB-NEXT: addi a2, a2, -1 +; CHECK-ZBB-NEXT: xor a0, a0, a2 +; CHECK-ZBB-NEXT: sext.w a0, a0 +; CHECK-ZBB-NEXT: min a0, a0, zero +; CHECK-ZBB-NEXT: slt a0, a0, a1 +; CHECK-ZBB-NEXT: ret + %cmp1 = icmp sgt i32 %x, 0 + %sub = sub nsw i32 2147483647, %x ; 0x7fffffff + %cmp2 = icmp sgt i32 %x, %sub + %r = select i1 %cmp1, i1 true, i1 %cmp2 + ret i1 %r +} -- GitLab From c4c9d4f306732c854fa88d2f30c1a22bb025d0c9 Mon Sep 17 00:00:00 2001 From: Peter Lafreniere Date: Fri, 26 Apr 2024 08:34:21 -0400 Subject: [PATCH 054/301] [M68k] Add support for MOVEQ instruction (#88542) Add support for the moveq instruction, which is both faster and smaller (1/2 to 1/3 the size) than a move with immediate to register. This change introduces the instruction, along with a set of pseudoinstructions to handle immediate moves to a register that is lowered post-RA. Pseudos are used as moveq can only write to the full register, which makes matching i8 and i16 immediate loads difficult in tablegen. Furthermore, selecting moveq before RA constrains that immediate to be moved into a data register, which may not be optimal. The bulk of this change are fixes to existing tests, which cover the new functionality sufficiently. --- llvm/lib/Target/M68k/M68kExpandPseudo.cpp | 7 ++++ llvm/lib/Target/M68k/M68kInstrData.td | 41 +++++++++++++++++-- llvm/lib/Target/M68k/M68kInstrInfo.cpp | 34 +++++++++++++++ llvm/lib/Target/M68k/M68kInstrInfo.h | 3 ++ .../CodeGen/M68k/Arith/add-with-overflow.ll | 2 +- llvm/test/CodeGen/M68k/Arith/add.ll | 4 +- llvm/test/CodeGen/M68k/Arith/bitwise.ll | 6 +-- .../CodeGen/M68k/Arith/divide-by-constant.ll | 14 +++---- llvm/test/CodeGen/M68k/Arith/imul.ll | 16 ++++---- .../CodeGen/M68k/Arith/smul-with-overflow.ll | 12 +++--- .../CodeGen/M68k/Arith/sub-with-overflow.ll | 10 ++--- llvm/test/CodeGen/M68k/Arith/sub.ll | 2 +- .../CodeGen/M68k/Arith/umul-with-overflow.ll | 6 +-- llvm/test/CodeGen/M68k/CConv/c-call.ll | 6 +-- llvm/test/CodeGen/M68k/CConv/fastcc-call.ll | 12 +++--- .../CodeModel/medium-pie-global-access.ll | 4 +- .../M68k/CodeModel/small-pie-global-access.ll | 4 +- llvm/test/CodeGen/M68k/Control/cmp.ll | 26 ++++++------ llvm/test/CodeGen/M68k/Control/long-setcc.ll | 4 +- llvm/test/CodeGen/M68k/Control/setcc.ll | 6 +-- llvm/test/CodeGen/M68k/PR57660.ll | 2 +- llvm/test/CodeGen/M68k/gcc_except_table.ll | 2 +- llvm/test/CodeGen/M68k/link-unlnk.ll | 4 +- llvm/test/MC/Disassembler/M68k/data.txt | 6 +++ llvm/test/MC/M68k/Data/Classes/MxMove_RI.s | 3 ++ 25 files changed, 162 insertions(+), 74 deletions(-) diff --git a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp index 7fcc65beaa65..c7fdd7d7c350 100644 --- a/llvm/lib/Target/M68k/M68kExpandPseudo.cpp +++ b/llvm/lib/Target/M68k/M68kExpandPseudo.cpp @@ -80,6 +80,13 @@ bool M68kExpandPseudo::ExpandMI(MachineBasicBlock &MBB, default: return false; + case M68k::MOVI8di: + return TII->ExpandMOVI(MIB, MVT::i8); + case M68k::MOVI16ri: + return TII->ExpandMOVI(MIB, MVT::i16); + case M68k::MOVI32ri: + return TII->ExpandMOVI(MIB, MVT::i32); + case M68k::MOVXd16d8: return TII->ExpandMOVX_RR(MIB, MVT::i16, MVT::i8); case M68k::MOVXd32d8: diff --git a/llvm/lib/Target/M68k/M68kInstrData.td b/llvm/lib/Target/M68k/M68kInstrData.td index fa7e7aa0ed46..dc777a933e27 100644 --- a/llvm/lib/Target/M68k/M68kInstrData.td +++ b/llvm/lib/Target/M68k/M68kInstrData.td @@ -19,7 +19,7 @@ /// /// Pseudo: /// -/// MOVSX [x] MOVZX [x] MOVX [x] +/// MOVI [x] MOVSX [x] MOVZX [x] MOVX [x] /// /// Map: /// @@ -165,11 +165,12 @@ foreach AM = MxMoveSupportedAMs in { } // foreach AM // R <- I +// No pattern, as all immediate -> register moves are matched to the MOVI pseudo class MxMove_RI("MxOp"#TYPE.Size#"AddrMode_i"), MxOpBundle DST = !cast("MxOp"#TYPE.Size#"AddrMode_"#DST_REG)> : MxMove; + [(null_frag)], ENC>; foreach REG = ["r", "a", "d"] in { foreach TYPE = !if(!eq(REG, "d"), [MxType8, MxType16, MxType32], [MxType16, MxType32]) in @@ -242,6 +243,24 @@ def : Pat<(store MxType32.BPat :$src, MxType32.BPat :$dst), def : Pat<(store MxType32.BPat :$src, MxType32.JPat :$dst), (MOV32ji MxType32.JOp :$dst, MxType32.IOp :$src)>; +//===----------------------------------------------------------------------===// +// MOVEQ +//===----------------------------------------------------------------------===// + +/// ------------+---------+---+----------------------- +/// F E D C | B A 9 | 8 | 7 6 5 4 3 2 1 0 +/// ------------+---------+---+----------------------- +/// 0 1 1 1 | REG | 0 | DATA +/// ------------+---------+---+----------------------- + +// No pattern, as all immediate -> register moves are matched to the MOVI pseudo +let Defs = [CCR] in +def MOVQ : MxInst<(outs MxDRD32:$dst), (ins Mxi8imm:$imm), + "moveq\t$imm, $dst", + [(null_frag)]> { + let Inst = (descend 0b0111, (operand "$dst", 3), 0b0, (operand "$imm", 8)); +} + //===----------------------------------------------------------------------===// // MOVEM // @@ -496,7 +515,23 @@ class MxPseudoMove_RR PAT = []> class MxPseudoMove_RM PAT = []> : MxPseudo<(outs DST.ROp:$dst), (ins SRCOpd:$src), PAT>; -} + + +// These Pseudos handle loading immediates to registers. +// They are expanded post-RA into either move or moveq instructions, +// depending on size, destination register class, and immediate value. +// This is done with pseudoinstructions in order to not constrain RA to +// data registers if moveq matches. +class MxPseudoMove_DI + : MxPseudo<(outs TYPE.ROp:$dst), (ins TYPE.IOp:$src), + [(set TYPE.ROp:$dst, imm:$src)]>; + +// i8 imm -> reg can always be converted to moveq, +// but we still emit a pseudo for consistency. +def MOVI8di : MxPseudoMove_DI; +def MOVI16ri : MxPseudoMove_DI; +def MOVI32ri : MxPseudoMove_DI; +} // let Defs = [CCR] /// This group of Pseudos is analogues to the real x86 extending moves, but /// since M68k does not have those we need to emulate. These instructions diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.cpp b/llvm/lib/Target/M68k/M68kInstrInfo.cpp index d56fef9e9029..338db45782c9 100644 --- a/llvm/lib/Target/M68k/M68kInstrInfo.cpp +++ b/llvm/lib/Target/M68k/M68kInstrInfo.cpp @@ -346,6 +346,40 @@ void M68kInstrInfo::AddZExt(MachineBasicBlock &MBB, BuildMI(MBB, I, DL, get(And), Reg).addReg(Reg).addImm(Mask); } +// Convert MOVI to MOVQ if the target is a data register and the immediate +// fits in a sign-extended i8, otherwise emit a plain MOV. +bool M68kInstrInfo::ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const { + Register Reg = MIB->getOperand(0).getReg(); + int64_t Imm = MIB->getOperand(1).getImm(); + bool IsAddressReg = false; + + const auto *DR32 = RI.getRegClass(M68k::DR32RegClassID); + const auto *AR32 = RI.getRegClass(M68k::AR32RegClassID); + const auto *AR16 = RI.getRegClass(M68k::AR16RegClassID); + + if (AR16->contains(Reg) || AR32->contains(Reg)) + IsAddressReg = true; + + LLVM_DEBUG(dbgs() << "Expand " << *MIB.getInstr() << " to "); + + if (MVTSize == MVT::i8 || (!IsAddressReg && Imm >= -128 && Imm <= 127)) { + LLVM_DEBUG(dbgs() << "MOVEQ\n"); + + // We need to assign to the full register to make IV happy + Register SReg = + MVTSize == MVT::i32 ? Reg : Register(RI.getMatchingMegaReg(Reg, DR32)); + assert(SReg && "No viable MEGA register available"); + + MIB->setDesc(get(M68k::MOVQ)); + MIB->getOperand(0).setReg(SReg); + } else { + LLVM_DEBUG(dbgs() << "MOVE\n"); + MIB->setDesc(get(MVTSize == MVT::i16 ? M68k::MOV16ri : M68k::MOV32ri)); + } + + return true; +} + bool M68kInstrInfo::ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const { unsigned Move = MVTDst == MVT::i16 ? M68k::MOV16rr : M68k::MOV32rr; diff --git a/llvm/lib/Target/M68k/M68kInstrInfo.h b/llvm/lib/Target/M68k/M68kInstrInfo.h index 577967f2fdfc..d1e1e1cd9998 100644 --- a/llvm/lib/Target/M68k/M68kInstrInfo.h +++ b/llvm/lib/Target/M68k/M68kInstrInfo.h @@ -302,6 +302,9 @@ public: void AddZExt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, DebugLoc DL, unsigned Reg, MVT From, MVT To) const; + /// Move immediate to register + bool ExpandMOVI(MachineInstrBuilder &MIB, MVT MVTSize) const; + /// Move across register classes without extension bool ExpandMOVX_RR(MachineInstrBuilder &MIB, MVT MVTDst, MVT MVTSrc) const; diff --git a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll index bd5e593edb33..70479b0b3ec6 100644 --- a/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/add-with-overflow.ll @@ -35,7 +35,7 @@ define fastcc i1 @test6(i32 %v1, i32 %v2, ptr %X) nounwind { ; CHECK-NEXT: ; %bb.1: ; %normal ; CHECK-NEXT: move.l #0, (%a0) ; CHECK-NEXT: .LBB1_2: ; %carry -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts entry: %t = call {i32, i1} @llvm.uadd.with.overflow.i32(i32 %v1, i32 %v2) diff --git a/llvm/test/CodeGen/M68k/Arith/add.ll b/llvm/test/CodeGen/M68k/Arith/add.ll index 281751e3e183..a9eb0bb815b0 100644 --- a/llvm/test/CodeGen/M68k/Arith/add.ll +++ b/llvm/test/CodeGen/M68k/Arith/add.ll @@ -43,7 +43,7 @@ define fastcc void @test3(ptr inreg %a) nounwind { ; CHECK-NEXT: suba.l #4, %sp ; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill ; CHECK-NEXT: move.l (%a0), %d0 -; CHECK-NEXT: move.l #0, %d1 +; CHECK-NEXT: moveq #0, %d1 ; CHECK-NEXT: move.l #-2147483648, %d2 ; CHECK-NEXT: add.l (4,%a0), %d2 ; CHECK-NEXT: addx.l %d0, %d1 @@ -64,7 +64,7 @@ define fastcc void @test4(ptr inreg %a) nounwind { ; CHECK-NEXT: suba.l #4, %sp ; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill ; CHECK-NEXT: move.l (%a0), %d0 -; CHECK-NEXT: move.l #0, %d1 +; CHECK-NEXT: moveq #0, %d1 ; CHECK-NEXT: move.l #128, %d2 ; CHECK-NEXT: add.l (4,%a0), %d2 ; CHECK-NEXT: addx.l %d0, %d1 diff --git a/llvm/test/CodeGen/M68k/Arith/bitwise.ll b/llvm/test/CodeGen/M68k/Arith/bitwise.ll index 70e4dd42bfb6..74fc543a5fb8 100644 --- a/llvm/test/CodeGen/M68k/Arith/bitwise.ll +++ b/llvm/test/CodeGen/M68k/Arith/bitwise.ll @@ -242,7 +242,7 @@ define i64 @lshr64(i64 %a, i64 %b) nounwind { ; CHECK-NEXT: add.l #-32, %d1 ; CHECK-NEXT: bmi .LBB18_1 ; CHECK-NEXT: ; %bb.2: -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: bra .LBB18_3 ; CHECK-NEXT: .LBB18_1: ; CHECK-NEXT: move.l %d2, %d0 @@ -301,7 +301,7 @@ define i64 @ashr64(i64 %a, i64 %b) nounwind { ; CHECK-NEXT: add.l #-32, %d3 ; CHECK-NEXT: bmi .LBB19_5 ; CHECK-NEXT: ; %bb.4: -; CHECK-NEXT: move.l #31, %d2 +; CHECK-NEXT: moveq #31, %d2 ; CHECK-NEXT: .LBB19_5: ; CHECK-NEXT: asr.l %d2, %d0 ; CHECK-NEXT: movem.l (0,%sp), %d2-%d3 ; 12-byte Folded Reload @@ -322,7 +322,7 @@ define i64 @shl64(i64 %a, i64 %b) nounwind { ; CHECK-NEXT: add.l #-32, %d0 ; CHECK-NEXT: bmi .LBB20_1 ; CHECK-NEXT: ; %bb.2: -; CHECK-NEXT: move.l #0, %d1 +; CHECK-NEXT: moveq #0, %d1 ; CHECK-NEXT: bra .LBB20_3 ; CHECK-NEXT: .LBB20_1: ; CHECK-NEXT: move.l %d2, %d1 diff --git a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll index 834dfe1c26f0..fcc8dd3e7662 100644 --- a/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll +++ b/llvm/test/CodeGen/M68k/Arith/divide-by-constant.ll @@ -40,7 +40,7 @@ define zeroext i8 @test3(i8 zeroext %x, i8 zeroext %c) { ; CHECK-NEXT: move.b (11,%sp), %d0 ; CHECK-NEXT: and.l #255, %d0 ; CHECK-NEXT: muls #171, %d0 -; CHECK-NEXT: move.w #9, %d1 +; CHECK-NEXT: moveq #9, %d1 ; CHECK-NEXT: lsr.w %d1, %d0 ; CHECK-NEXT: and.l #65535, %d0 ; CHECK-NEXT: rts @@ -58,7 +58,7 @@ define signext i16 @test4(i16 signext %x) nounwind { ; CHECK-NEXT: muls #1986, %d0 ; CHECK-NEXT: asr.l #8, %d0 ; CHECK-NEXT: asr.l #8, %d0 -; CHECK-NEXT: move.w #15, %d1 +; CHECK-NEXT: moveq #15, %d1 ; CHECK-NEXT: move.w %d0, %d2 ; CHECK-NEXT: lsr.w %d1, %d2 ; CHECK-NEXT: add.w %d2, %d0 @@ -94,7 +94,7 @@ define signext i16 @test6(i16 signext %x) nounwind { ; CHECK-NEXT: muls #26215, %d0 ; CHECK-NEXT: asr.l #8, %d0 ; CHECK-NEXT: asr.l #8, %d0 -; CHECK-NEXT: move.w #15, %d1 +; CHECK-NEXT: moveq #15, %d1 ; CHECK-NEXT: move.w %d0, %d2 ; CHECK-NEXT: lsr.w %d1, %d2 ; CHECK-NEXT: asr.w #2, %d0 @@ -128,7 +128,7 @@ define i8 @test8(i8 %x) nounwind { ; CHECK-NEXT: lsr.b #1, %d0 ; CHECK-NEXT: and.l #255, %d0 ; CHECK-NEXT: muls #211, %d0 -; CHECK-NEXT: move.w #13, %d1 +; CHECK-NEXT: moveq #13, %d1 ; CHECK-NEXT: lsr.w %d1, %d0 ; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0 ; CHECK-NEXT: rts @@ -143,7 +143,7 @@ define i8 @test9(i8 %x) nounwind { ; CHECK-NEXT: lsr.b #2, %d0 ; CHECK-NEXT: and.l #255, %d0 ; CHECK-NEXT: muls #71, %d0 -; CHECK-NEXT: move.w #11, %d1 +; CHECK-NEXT: moveq #11, %d1 ; CHECK-NEXT: lsr.w %d1, %d0 ; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0 ; CHECK-NEXT: rts @@ -156,11 +156,11 @@ define i32 @testsize1(i32 %x) minsize nounwind { ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: suba.l #4, %sp ; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill -; CHECK-NEXT: move.l #31, %d1 +; CHECK-NEXT: moveq #31, %d1 ; CHECK-NEXT: move.l (8,%sp), %d0 ; CHECK-NEXT: move.l %d0, %d2 ; CHECK-NEXT: asr.l %d1, %d2 -; CHECK-NEXT: move.l #27, %d1 +; CHECK-NEXT: moveq #27, %d1 ; CHECK-NEXT: lsr.l %d1, %d2 ; CHECK-NEXT: add.l %d2, %d0 ; CHECK-NEXT: asr.l #5, %d0 diff --git a/llvm/test/CodeGen/M68k/Arith/imul.ll b/llvm/test/CodeGen/M68k/Arith/imul.ll index f53568395c29..a1846e4d51bd 100644 --- a/llvm/test/CodeGen/M68k/Arith/imul.ll +++ b/llvm/test/CodeGen/M68k/Arith/imul.ll @@ -19,7 +19,7 @@ define i64 @mul4_64(i64 %A) { ; CHECK-NEXT: suba.l #4, %sp ; CHECK-NEXT: .cfi_def_cfa_offset -8 ; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill -; CHECK-NEXT: move.l #30, %d0 +; CHECK-NEXT: moveq #30, %d0 ; CHECK-NEXT: move.l (12,%sp), %d1 ; CHECK-NEXT: move.l %d1, %d2 ; CHECK-NEXT: lsr.l %d0, %d2 @@ -38,7 +38,7 @@ define i32 @mul4096_32(i32 %A) { ; CHECK-LABEL: mul4096_32: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: -; CHECK-NEXT: move.l #12, %d1 +; CHECK-NEXT: moveq #12, %d1 ; CHECK-NEXT: move.l (4,%sp), %d0 ; CHECK-NEXT: lsl.l %d1, %d0 ; CHECK-NEXT: rts @@ -53,11 +53,11 @@ define i64 @mul4096_64(i64 %A) { ; CHECK-NEXT: suba.l #8, %sp ; CHECK-NEXT: .cfi_def_cfa_offset -12 ; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill -; CHECK-NEXT: move.l #20, %d0 +; CHECK-NEXT: moveq #20, %d0 ; CHECK-NEXT: move.l (16,%sp), %d1 ; CHECK-NEXT: move.l %d1, %d2 ; CHECK-NEXT: lsr.l %d0, %d2 -; CHECK-NEXT: move.l #12, %d3 +; CHECK-NEXT: moveq #12, %d3 ; CHECK-NEXT: move.l (12,%sp), %d0 ; CHECK-NEXT: lsl.l %d3, %d0 ; CHECK-NEXT: or.l %d2, %d0 @@ -73,7 +73,7 @@ define i32 @mulmin4096_32(i32 %A) { ; CHECK-LABEL: mulmin4096_32: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: -; CHECK-NEXT: move.l #12, %d1 +; CHECK-NEXT: moveq #12, %d1 ; CHECK-NEXT: move.l (4,%sp), %d0 ; CHECK-NEXT: lsl.l %d1, %d0 ; CHECK-NEXT: neg.l %d0 @@ -89,11 +89,11 @@ define i64 @mulmin4096_64(i64 %A) { ; CHECK-NEXT: suba.l #8, %sp ; CHECK-NEXT: .cfi_def_cfa_offset -12 ; CHECK-NEXT: movem.l %d2-%d3, (0,%sp) ; 12-byte Folded Spill -; CHECK-NEXT: move.l #20, %d0 +; CHECK-NEXT: moveq #20, %d0 ; CHECK-NEXT: move.l (16,%sp), %d1 ; CHECK-NEXT: move.l %d1, %d2 ; CHECK-NEXT: lsr.l %d0, %d2 -; CHECK-NEXT: move.l #12, %d3 +; CHECK-NEXT: moveq #12, %d3 ; CHECK-NEXT: move.l (12,%sp), %d0 ; CHECK-NEXT: lsl.l %d3, %d0 ; CHECK-NEXT: or.l %d2, %d0 @@ -258,7 +258,7 @@ define i32 @mul0_32(i32 %A) { ; CHECK-LABEL: mul0_32: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts %mul = mul i32 %A, 0 ret i32 %mul diff --git a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll index 5bd4d5d48bc8..10a797f13441 100644 --- a/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/smul-with-overflow.ll @@ -24,7 +24,7 @@ entry: define zeroext i8 @smul_i8_no_ovf(i8 signext %a, i8 signext %b) nounwind ssp { ; CHECK-LABEL: smul_i8_no_ovf: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: move.l #42, %d0 +; CHECK-NEXT: moveq #42, %d0 ; CHECK-NEXT: rts entry: %smul = tail call { i8, i1 } @llvm.smul.with.overflow.i8(i8 %a, i8 %b) @@ -70,7 +70,7 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (no,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB3_1: ; %normal @@ -78,7 +78,7 @@ define fastcc i1 @test1(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (ok,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts entry: @@ -108,7 +108,7 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (no,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB4_2: ; %normal @@ -116,7 +116,7 @@ define fastcc i1 @test2(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (ok,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts entry: @@ -155,7 +155,7 @@ define i32 @test4(i32 %a, i32 %b) nounwind readnone { ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (8,%sp), %d0 ; CHECK-NEXT: add.l (4,%sp), %d0 -; CHECK-NEXT: move.l #4, %d1 +; CHECK-NEXT: moveq #4, %d1 ; CHECK-NEXT: muls.l %d1, %d0 ; CHECK-NEXT: rts entry: diff --git a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll index 8d47c7ebf7e5..be3223156986 100644 --- a/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/sub-with-overflow.ll @@ -19,7 +19,7 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (no,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB0_1: ; %normal @@ -27,7 +27,7 @@ define i1 @func1(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (ok,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts entry: @@ -56,7 +56,7 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (no,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB1_1: ; %normal @@ -64,7 +64,7 @@ define i1 @func2(i32 %v1, i32 %v2) nounwind { ; CHECK-NEXT: lea (ok,%pc), %a0 ; CHECK-NEXT: move.l %a0, (%sp) ; CHECK-NEXT: jsr printf@PLT -; CHECK-NEXT: move.b #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts entry: @@ -85,7 +85,7 @@ carry: define i1 @func3(i32 %x) nounwind { ; CHECK-LABEL: func3: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: move.l #-1, %d0 +; CHECK-NEXT: moveq #-1, %d0 ; CHECK-NEXT: add.l (4,%sp), %d0 ; CHECK-NEXT: svs %d0 ; CHECK-NEXT: rts diff --git a/llvm/test/CodeGen/M68k/Arith/sub.ll b/llvm/test/CodeGen/M68k/Arith/sub.ll index fff3601000df..16d0498b3dbb 100644 --- a/llvm/test/CodeGen/M68k/Arith/sub.ll +++ b/llvm/test/CodeGen/M68k/Arith/sub.ll @@ -7,7 +7,7 @@ define i32 @test1(i32 %x) { ; CHECK-NEXT: ; %bb.0: ; CHECK-NEXT: move.l (4,%sp), %d1 ; CHECK-NEXT: eori.l #31, %d1 -; CHECK-NEXT: move.l #32, %d0 +; CHECK-NEXT: moveq #32, %d0 ; CHECK-NEXT: sub.l %d1, %d0 ; CHECK-NEXT: rts %xor = xor i32 %x, 31 diff --git a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll index fd128a3e52bd..3314e65399c4 100644 --- a/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll +++ b/llvm/test/CodeGen/M68k/Arith/umul-with-overflow.ll @@ -24,7 +24,7 @@ entry: define zeroext i8 @umul_i8_no_ovf(i8 signext %a, i8 signext %b) nounwind ssp { ; CHECK-LABEL: umul_i8_no_ovf: ; CHECK: ; %bb.0: ; %entry -; CHECK-NEXT: move.l #42, %d0 +; CHECK-NEXT: moveq #42, %d0 ; CHECK-NEXT: rts entry: %umul = tail call { i8, i1 } @llvm.umul.with.overflow.i8(i8 %a, i8 %b) @@ -59,7 +59,7 @@ declare {i32, i1} @llvm.umul.with.overflow.i32(i32 %a, i32 %b) define i1 @a(i32 %x) nounwind { ; CHECK-LABEL: a: ; CHECK: ; %bb.0: -; CHECK-NEXT: move.l #3, %d0 +; CHECK-NEXT: moveq #3, %d0 ; CHECK-NEXT: move.l (4,%sp), %d1 ; CHECK-NEXT: mulu.l %d0, %d1 ; CHECK-NEXT: svs %d0 @@ -90,7 +90,7 @@ define i32 @test3(i32 %a, i32 %b) nounwind readnone { ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (8,%sp), %d0 ; CHECK-NEXT: add.l (4,%sp), %d0 -; CHECK-NEXT: move.l #4, %d1 +; CHECK-NEXT: moveq #4, %d1 ; CHECK-NEXT: mulu.l %d1, %d0 ; CHECK-NEXT: rts entry: diff --git a/llvm/test/CodeGen/M68k/CConv/c-call.ll b/llvm/test/CodeGen/M68k/CConv/c-call.ll index a9638eec6a31..badd4e31f37d 100644 --- a/llvm/test/CodeGen/M68k/CConv/c-call.ll +++ b/llvm/test/CodeGen/M68k/CConv/c-call.ll @@ -14,7 +14,7 @@ define i32 @test1() nounwind { ; CHECK-NEXT: move.l #2, (4,%sp) ; CHECK-NEXT: move.l #1, (%sp) ; CHECK-NEXT: jsr (test1_callee@PLT,%pc) -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #20, %sp ; CHECK-NEXT: rts entry: @@ -34,7 +34,7 @@ define i16 @test2() nounwind { ; CHECK-NEXT: move.l #2, (4,%sp) ; CHECK-NEXT: move.l #1, (%sp) ; CHECK-NEXT: jsr (test2_callee@PLT,%pc) -; CHECK-NEXT: move.w #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #20, %sp ; CHECK-NEXT: rts entry: @@ -54,7 +54,7 @@ define i8 @test3() nounwind { ; CHECK-NEXT: move.l #2, (4,%sp) ; CHECK-NEXT: move.l #1, (%sp) ; CHECK-NEXT: jsr (test3_callee@PLT,%pc) -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #20, %sp ; CHECK-NEXT: rts entry: diff --git a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll index 4b0f8ed254a5..8d40ebd5228f 100644 --- a/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll +++ b/llvm/test/CodeGen/M68k/CConv/fastcc-call.ll @@ -11,12 +11,12 @@ define i32 @foo1() nounwind uwtable { ; CHECK-NEXT: suba.l #4, %sp ; CHECK-NEXT: .cfi_def_cfa_offset -8 ; CHECK-NEXT: move.l #5, (%sp) -; CHECK-NEXT: move.l #1, %d0 -; CHECK-NEXT: move.l #2, %d1 +; CHECK-NEXT: moveq #1, %d0 +; CHECK-NEXT: moveq #2, %d1 ; CHECK-NEXT: move.l #3, %a0 ; CHECK-NEXT: move.l #4, %a1 ; CHECK-NEXT: jsr (bar1@PLT,%pc) -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts entry: @@ -34,11 +34,11 @@ define i32 @foo2() nounwind uwtable { ; CHECK-NEXT: suba.l #12, %sp ; CHECK-NEXT: .cfi_def_cfa_offset -16 ; CHECK-NEXT: lea (8,%sp), %a0 -; CHECK-NEXT: move.l #2, %d0 +; CHECK-NEXT: moveq #2, %d0 ; CHECK-NEXT: lea (4,%sp), %a1 -; CHECK-NEXT: move.l #4, %d1 +; CHECK-NEXT: moveq #4, %d1 ; CHECK-NEXT: jsr (bar2@PLT,%pc) -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #12, %sp ; CHECK-NEXT: rts entry: diff --git a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll index ce8f2d0a6ba7..3d398afe7dc4 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/medium-pie-global-access.ll @@ -71,7 +71,7 @@ define i32 @my_access_global_store_d() #0 { ; CHECK-NEXT: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (d@GOTPCREL,%pc), %a0 ; CHECK-NEXT: move.l #2, (%a0) -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts entry: store i32 2, ptr @d, align 4 @@ -105,7 +105,7 @@ define linkonce_odr i32 @bar() comdat { ; CHECK-LABEL: bar: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: ; %entry -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts entry: ret i32 0 diff --git a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll index 668f8a96ac6f..030f72bb3753 100644 --- a/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll +++ b/llvm/test/CodeGen/M68k/CodeModel/small-pie-global-access.ll @@ -69,7 +69,7 @@ define i32 @my_access_global_store_d() #0 { ; CHECK-NEXT: ; %bb.0: ; %entry ; CHECK-NEXT: move.l (d@GOTPCREL,%pc), %a0 ; CHECK-NEXT: move.l #2, (%a0) -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts entry: store i32 2, ptr @d, align 4 @@ -103,7 +103,7 @@ define linkonce_odr i32 @bar() comdat { ; CHECK-LABEL: bar: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: ; %entry -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts entry: ret i32 0 diff --git a/llvm/test/CodeGen/M68k/Control/cmp.ll b/llvm/test/CodeGen/M68k/Control/cmp.ll index 634c08760a4e..d3a8bbb0b0c8 100644 --- a/llvm/test/CodeGen/M68k/Control/cmp.ll +++ b/llvm/test/CodeGen/M68k/Control/cmp.ll @@ -8,10 +8,10 @@ define i32 @test1(ptr %y) nounwind { ; CHECK-NEXT: cmpi.l #0, (%a0) ; CHECK-NEXT: beq .LBB0_2 ; CHECK-NEXT: ; %bb.1: ; %cond_false -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB0_2: ; %cond_true -; CHECK-NEXT: move.l #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: rts %tmp = load i32, ptr %y ; [#uses=1] %tmp.upgrd.1 = icmp eq i32 %tmp, 0 ; [#uses=1] @@ -33,10 +33,10 @@ define i32 @test2(ptr %y) nounwind { ; CHECK-NEXT: cmpi.l #0, %d0 ; CHECK-NEXT: beq .LBB1_2 ; CHECK-NEXT: ; %bb.1: ; %cond_false -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB1_2: ; %cond_true -; CHECK-NEXT: move.l #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: rts %tmp = load i32, ptr %y ; [#uses=1] %tmp1 = shl i32 %tmp, 3 ; [#uses=1] @@ -59,10 +59,10 @@ define i8 @test2b(ptr %y) nounwind { ; CHECK-NEXT: cmpi.b #0, %d0 ; CHECK-NEXT: beq .LBB2_2 ; CHECK-NEXT: ; %bb.1: ; %cond_false -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB2_2: ; %cond_true -; CHECK-NEXT: move.b #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: rts %tmp = load i8, ptr %y ; [#uses=1] %tmp1 = shl i8 %tmp, 3 ; [#uses=1] @@ -84,7 +84,7 @@ define i64 @test3(i64 %x) nounwind { ; CHECK-NEXT: seq %d0 ; CHECK-NEXT: move.l %d0, %d1 ; CHECK-NEXT: and.l #255, %d1 -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts %t = icmp eq i64 %x, 0 %r = zext i1 %t to i64 @@ -97,7 +97,7 @@ define i64 @test4(i64 %x) nounwind { ; CHECK-NEXT: suba.l #4, %sp ; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill ; CHECK-NEXT: move.l (8,%sp), %d1 -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: move.l (12,%sp), %d2 ; CHECK-NEXT: sub.l #1, %d2 ; CHECK-NEXT: subx.l %d0, %d1 @@ -119,11 +119,11 @@ define i32 @test6() nounwind align 2 { ; CHECK-NEXT: or.l (8,%sp), %d0 ; CHECK-NEXT: beq .LBB5_1 ; CHECK-NEXT: ; %bb.2: ; %F -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #20, %sp ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB5_1: ; %T -; CHECK-NEXT: move.l #1, %d0 +; CHECK-NEXT: moveq #1, %d0 ; CHECK-NEXT: adda.l #20, %sp ; CHECK-NEXT: rts %A = alloca {i64, i64}, align 8 @@ -229,7 +229,7 @@ define zeroext i1 @test15(i32 %bf.load, i32 %n) { ; CHECK-LABEL: test15: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: -; CHECK-NEXT: move.l #16, %d0 +; CHECK-NEXT: moveq #16, %d0 ; CHECK-NEXT: move.l (4,%sp), %d1 ; CHECK-NEXT: lsr.l %d0, %d1 ; CHECK-NEXT: move.l %d1, %d0 @@ -252,7 +252,7 @@ define i8 @test16(i16 signext %L) { ; CHECK-LABEL: test16: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: -; CHECK-NEXT: move.w #15, %d1 +; CHECK-NEXT: moveq #15, %d1 ; CHECK-NEXT: move.w (6,%sp), %d0 ; CHECK-NEXT: lsr.w %d1, %d0 ; CHECK-NEXT: eori.b #1, %d0 @@ -268,7 +268,7 @@ define i8 @test18(i64 %L) { ; CHECK-LABEL: test18: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: -; CHECK-NEXT: move.l #31, %d1 +; CHECK-NEXT: moveq #31, %d1 ; CHECK-NEXT: move.l (4,%sp), %d0 ; CHECK-NEXT: lsr.l %d1, %d0 ; CHECK-NEXT: eori.b #1, %d0 diff --git a/llvm/test/CodeGen/M68k/Control/long-setcc.ll b/llvm/test/CodeGen/M68k/Control/long-setcc.ll index b089af5f2ae8..45a617599c1e 100644 --- a/llvm/test/CodeGen/M68k/Control/long-setcc.ll +++ b/llvm/test/CodeGen/M68k/Control/long-setcc.ll @@ -4,7 +4,7 @@ define i1 @t1(i64 %x) nounwind { ; CHECK-LABEL: t1: ; CHECK: ; %bb.0: -; CHECK-NEXT: move.l #31, %d1 +; CHECK-NEXT: moveq #31, %d1 ; CHECK-NEXT: move.l (4,%sp), %d0 ; CHECK-NEXT: lsr.l %d1, %d0 ; CHECK-NEXT: ; kill: def $bd0 killed $bd0 killed $d0 @@ -26,7 +26,7 @@ define i1 @t2(i64 %x) nounwind { define i1 @t3(i32 %x) nounwind { ; CHECK-LABEL: t3: ; CHECK: ; %bb.0: -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: rts %tmp = icmp ugt i32 %x, -1 ret i1 %tmp diff --git a/llvm/test/CodeGen/M68k/Control/setcc.ll b/llvm/test/CodeGen/M68k/Control/setcc.ll index 63856e278c9e..9e03f9b90842 100644 --- a/llvm/test/CodeGen/M68k/Control/setcc.ll +++ b/llvm/test/CodeGen/M68k/Control/setcc.ll @@ -40,7 +40,7 @@ define fastcc i64 @t3(i64 %x) nounwind readnone ssp { ; CHECK: ; %bb.0: ; %entry ; CHECK-NEXT: suba.l #4, %sp ; CHECK-NEXT: movem.l %d2, (0,%sp) ; 8-byte Folded Spill -; CHECK-NEXT: move.l #0, %d2 +; CHECK-NEXT: moveq #0, %d2 ; CHECK-NEXT: sub.l #18, %d1 ; CHECK-NEXT: subx.l %d2, %d0 ; CHECK-NEXT: scs %d0 @@ -61,7 +61,7 @@ define i8 @t5(i32 %a) { ; CHECK-LABEL: t5: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: ; %entry -; CHECK-NEXT: move.l #31, %d1 +; CHECK-NEXT: moveq #31, %d1 ; CHECK-NEXT: move.l (4,%sp), %d0 ; CHECK-NEXT: lsr.l %d1, %d0 ; CHECK-NEXT: eori.b #1, %d0 @@ -86,7 +86,7 @@ define zeroext i1 @t6(i32 %a) { ; CHECK-LABEL: t6: ; CHECK: .cfi_startproc ; CHECK-NEXT: ; %bb.0: ; %entry -; CHECK-NEXT: move.l #31, %d0 +; CHECK-NEXT: moveq #31, %d0 ; CHECK-NEXT: move.l (4,%sp), %d1 ; CHECK-NEXT: lsr.l %d0, %d1 ; CHECK-NEXT: eori.b #1, %d1 diff --git a/llvm/test/CodeGen/M68k/PR57660.ll b/llvm/test/CodeGen/M68k/PR57660.ll index 184c30a33d79..bad949b08caf 100644 --- a/llvm/test/CodeGen/M68k/PR57660.ll +++ b/llvm/test/CodeGen/M68k/PR57660.ll @@ -7,7 +7,7 @@ define dso_local void @foo1() { ; CHECK-NEXT: ; %bb.0: ; %entry ; CHECK-NEXT: suba.l #2, %sp ; CHECK-NEXT: .cfi_def_cfa_offset -6 -; CHECK-NEXT: move.b #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: move.b %d0, (0,%sp) ; 1-byte Folded Spill ; CHECK-NEXT: .LBB0_1: ; %do.body ; CHECK-NEXT: ; =>This Inner Loop Header: Depth=1 diff --git a/llvm/test/CodeGen/M68k/gcc_except_table.ll b/llvm/test/CodeGen/M68k/gcc_except_table.ll index a7d2a6662724..fe0ed7861dfe 100644 --- a/llvm/test/CodeGen/M68k/gcc_except_table.ll +++ b/llvm/test/CodeGen/M68k/gcc_except_table.ll @@ -19,7 +19,7 @@ define i32 @foo() uwtable ssp personality ptr @__gxx_personality_v0 { ; CHECK-NEXT: jsr _Z1fv@PLT ; CHECK-NEXT: .Ltmp1: ; CHECK-NEXT: ; %bb.1: ; %try.cont -; CHECK-NEXT: move.l #0, %d0 +; CHECK-NEXT: moveq #0, %d0 ; CHECK-NEXT: adda.l #4, %sp ; CHECK-NEXT: rts ; CHECK-NEXT: .LBB0_2: ; %lpad diff --git a/llvm/test/CodeGen/M68k/link-unlnk.ll b/llvm/test/CodeGen/M68k/link-unlnk.ll index dfdd80e66ade..fe39a9a13494 100644 --- a/llvm/test/CodeGen/M68k/link-unlnk.ll +++ b/llvm/test/CodeGen/M68k/link-unlnk.ll @@ -105,7 +105,7 @@ define i32 @test_gep() { ; FP-NEXT: .cfi_def_cfa_register %a6 ; FP-NEXT: move.l #21, (-4,%a6) ; FP-NEXT: move.l #12, (-256,%a6) -; FP-NEXT: move.l #0, %d0 +; FP-NEXT: moveq #0, %d0 ; FP-NEXT: unlk %a6 ; FP-NEXT: rts ; @@ -116,7 +116,7 @@ define i32 @test_gep() { ; NO-FP-NEXT: .cfi_def_cfa_offset -260 ; NO-FP-NEXT: move.l #21, (252,%sp) ; NO-FP-NEXT: move.l #12, (0,%sp) -; NO-FP-NEXT: move.l #0, %d0 +; NO-FP-NEXT: moveq #0, %d0 ; NO-FP-NEXT: adda.l #256, %sp ; NO-FP-NEXT: rts entry: diff --git a/llvm/test/MC/Disassembler/M68k/data.txt b/llvm/test/MC/Disassembler/M68k/data.txt index 8e2fb3f13560..3951ea677f11 100644 --- a/llvm/test/MC/Disassembler/M68k/data.txt +++ b/llvm/test/MC/Disassembler/M68k/data.txt @@ -36,6 +36,12 @@ # CHECK: move.l (64,%sp,%a0), %d0 0x20 0x37 0x88 0x40 +# CHECK: move.b #234, %d2 +0x14 0x3c 0x00 0xea + +# CHECK: moveq #100, %d2 +0x74 0x64 + # CHECK: move.l $f0000000, %a5 0x2a 0x79 0xf0 0x00 0x00 0x00 diff --git a/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s b/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s index 091367a68256..2081924d7b17 100644 --- a/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s +++ b/llvm/test/MC/M68k/Data/Classes/MxMove_RI.s @@ -9,3 +9,6 @@ move.l #42, %a1 ; CHECK: move.l #-1, %a1 ; CHECK-SAME: encoding: [0x22,0x7c,0xff,0xff,0xff,0xff] move.l #-1, %a1 +; CHECK: moveq #-17, %d3 +; CHECK-SAME: encoding: [0x76,0xef] +moveq #-17, %d3 -- GitLab From 7696d36b4ed595bf9681fd379d1dcbaf30c1ef0a Mon Sep 17 00:00:00 2001 From: Carlos Alberto Enciso Date: Fri, 26 Apr 2024 13:35:09 +0100 Subject: [PATCH 055/301] [Transforms] Debug values are not remapped when cloning. (#87747) When cloning instructions from one basic block to another, the debug values are not remapped, in the same was as the normal instructions. --- llvm/include/llvm/IR/IntrinsicInst.h | 3 +- .../llvm/Transforms/Scalar/JumpThreading.h | 10 ++--- llvm/include/llvm/Transforms/Utils/Local.h | 5 +++ llvm/lib/IR/IntrinsicInst.cpp | 5 ++- llvm/lib/Transforms/Scalar/JumpThreading.cpp | 41 +++++++++++-------- llvm/lib/Transforms/Utils/CloneFunction.cpp | 3 ++ llvm/lib/Transforms/Utils/Local.cpp | 24 +++++++++++ .../CallSiteSplitting/callsite-split-debug.ll | 36 +++++++++++++++- 8 files changed, 101 insertions(+), 26 deletions(-) diff --git a/llvm/include/llvm/IR/IntrinsicInst.h b/llvm/include/llvm/IR/IntrinsicInst.h index 081e72cc82b2..2e99c9e2ee3e 100644 --- a/llvm/include/llvm/IR/IntrinsicInst.h +++ b/llvm/include/llvm/IR/IntrinsicInst.h @@ -311,7 +311,8 @@ public: Value *getVariableLocationOp(unsigned OpIdx) const; - void replaceVariableLocationOp(Value *OldValue, Value *NewValue); + void replaceVariableLocationOp(Value *OldValue, Value *NewValue, + bool AllowEmpty = false); void replaceVariableLocationOp(unsigned OpIdx, Value *NewValue); /// Adding a new location operand will always result in this intrinsic using /// an ArgList, and must always be accompanied by a new expression that uses diff --git a/llvm/include/llvm/Transforms/Scalar/JumpThreading.h b/llvm/include/llvm/Transforms/Scalar/JumpThreading.h index 3364d7eaee42..f7358ac9b1ee 100644 --- a/llvm/include/llvm/Transforms/Scalar/JumpThreading.h +++ b/llvm/include/llvm/Transforms/Scalar/JumpThreading.h @@ -22,6 +22,7 @@ #include "llvm/Analysis/BranchProbabilityInfo.h" #include "llvm/Analysis/DomTreeUpdater.h" #include "llvm/IR/ValueHandle.h" +#include "llvm/Transforms/Utils/ValueMapper.h" #include #include @@ -114,11 +115,10 @@ public: bool processBlock(BasicBlock *BB); bool maybeMergeBasicBlockIntoOnlyPred(BasicBlock *BB); void updateSSA(BasicBlock *BB, BasicBlock *NewBB, - DenseMap &ValueMapping); - DenseMap cloneInstructions(BasicBlock::iterator BI, - BasicBlock::iterator BE, - BasicBlock *NewBB, - BasicBlock *PredBB); + ValueToValueMapTy &ValueMapping); + void cloneInstructions(ValueToValueMapTy &ValueMapping, + BasicBlock::iterator BI, BasicBlock::iterator BE, + BasicBlock *NewBB, BasicBlock *PredBB); bool tryThreadEdge(BasicBlock *BB, const SmallVectorImpl &PredBBs, BasicBlock *SuccBB); diff --git a/llvm/include/llvm/Transforms/Utils/Local.h b/llvm/include/llvm/Transforms/Utils/Local.h index e2143b5bfbe2..6937ec8dfd21 100644 --- a/llvm/include/llvm/Transforms/Utils/Local.h +++ b/llvm/include/llvm/Transforms/Utils/Local.h @@ -18,6 +18,7 @@ #include "llvm/IR/Dominators.h" #include "llvm/Support/CommandLine.h" #include "llvm/Transforms/Utils/SimplifyCFGOptions.h" +#include "llvm/Transforms/Utils/ValueMapper.h" #include namespace llvm { @@ -490,6 +491,10 @@ void hoistAllInstructionsInto(BasicBlock *DomBlock, Instruction *InsertPt, DIExpression *getExpressionForConstant(DIBuilder &DIB, const Constant &C, Type &Ty); +/// Remap the operands of the debug records attached to \p Inst, and the +/// operands of \p Inst itself if it's a debug intrinsic. +void remapDebugVariable(ValueToValueMapTy &Mapping, Instruction *Inst); + //===----------------------------------------------------------------------===// // Intrinsic pattern matching // diff --git a/llvm/lib/IR/IntrinsicInst.cpp b/llvm/lib/IR/IntrinsicInst.cpp index 8faeb4e9951f..6b6420ae41c9 100644 --- a/llvm/lib/IR/IntrinsicInst.cpp +++ b/llvm/lib/IR/IntrinsicInst.cpp @@ -119,7 +119,8 @@ static ValueAsMetadata *getAsMetadata(Value *V) { } void DbgVariableIntrinsic::replaceVariableLocationOp(Value *OldValue, - Value *NewValue) { + Value *NewValue, + bool AllowEmpty) { // If OldValue is used as the address part of a dbg.assign intrinsic replace // it with NewValue and return true. auto ReplaceDbgAssignAddress = [this, OldValue, NewValue]() -> bool { @@ -136,6 +137,8 @@ void DbgVariableIntrinsic::replaceVariableLocationOp(Value *OldValue, auto Locations = location_ops(); auto OldIt = find(Locations, OldValue); if (OldIt == Locations.end()) { + if (AllowEmpty || DbgAssignAddrReplaced) + return; assert(DbgAssignAddrReplaced && "OldValue must be dbg.assign addr if unused in DIArgList"); return; diff --git a/llvm/lib/Transforms/Scalar/JumpThreading.cpp b/llvm/lib/Transforms/Scalar/JumpThreading.cpp index ffcb511e6a83..08d82fa66da3 100644 --- a/llvm/lib/Transforms/Scalar/JumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/JumpThreading.cpp @@ -1876,7 +1876,7 @@ bool JumpThreadingPass::processBranchOnXOR(BinaryOperator *BO) { static void addPHINodeEntriesForMappedBlock(BasicBlock *PHIBB, BasicBlock *OldPred, BasicBlock *NewPred, - DenseMap &ValueMap) { + ValueToValueMapTy &ValueMap) { for (PHINode &PN : PHIBB->phis()) { // Ok, we have a PHI node. Figure out what the incoming value was for the // DestBlock. @@ -1884,7 +1884,7 @@ static void addPHINodeEntriesForMappedBlock(BasicBlock *PHIBB, // Remap the value if necessary. if (Instruction *Inst = dyn_cast(IV)) { - DenseMap::iterator I = ValueMap.find(Inst); + ValueToValueMapTy::iterator I = ValueMap.find(Inst); if (I != ValueMap.end()) IV = I->second; } @@ -1945,9 +1945,8 @@ bool JumpThreadingPass::maybeMergeBasicBlockIntoOnlyPred(BasicBlock *BB) { /// Update the SSA form. NewBB contains instructions that are copied from BB. /// ValueMapping maps old values in BB to new ones in NewBB. -void JumpThreadingPass::updateSSA( - BasicBlock *BB, BasicBlock *NewBB, - DenseMap &ValueMapping) { +void JumpThreadingPass::updateSSA(BasicBlock *BB, BasicBlock *NewBB, + ValueToValueMapTy &ValueMapping) { // If there were values defined in BB that are used outside the block, then we // now have to update all uses of the value to use either the original value, // the cloned value, or some PHI derived value. This can require arbitrary @@ -2008,14 +2007,15 @@ void JumpThreadingPass::updateSSA( /// Clone instructions in range [BI, BE) to NewBB. For PHI nodes, we only clone /// arguments that come from PredBB. Return the map from the variables in the /// source basic block to the variables in the newly created basic block. -DenseMap -JumpThreadingPass::cloneInstructions(BasicBlock::iterator BI, - BasicBlock::iterator BE, BasicBlock *NewBB, - BasicBlock *PredBB) { + +void JumpThreadingPass::cloneInstructions(ValueToValueMapTy &ValueMapping, + BasicBlock::iterator BI, + BasicBlock::iterator BE, + BasicBlock *NewBB, + BasicBlock *PredBB) { // We are going to have to map operands from the source basic block to the new // copy of the block 'NewBB'. If there are PHI nodes in the source basic // block, evaluate them to account for entry from PredBB. - DenseMap ValueMapping; // Retargets llvm.dbg.value to any renamed variables. auto RetargetDbgValueIfPossible = [&](Instruction *NewInst) -> bool { @@ -2103,7 +2103,7 @@ JumpThreadingPass::cloneInstructions(BasicBlock::iterator BI, // Remap operands to patch up intra-block references. for (unsigned i = 0, e = New->getNumOperands(); i != e; ++i) if (Instruction *Inst = dyn_cast(New->getOperand(i))) { - DenseMap::iterator I = ValueMapping.find(Inst); + ValueToValueMapTy::iterator I = ValueMapping.find(Inst); if (I != ValueMapping.end()) New->setOperand(i, I->second); } @@ -2120,7 +2120,7 @@ JumpThreadingPass::cloneInstructions(BasicBlock::iterator BI, RetargetDbgVariableRecordIfPossible(&DVR); } - return ValueMapping; + return; } /// Attempt to thread through two successive basic blocks. @@ -2295,8 +2295,9 @@ void JumpThreadingPass::threadThroughTwoBasicBlocks(BasicBlock *PredPredBB, // We are going to have to map operands from the original BB block to the new // copy of the block 'NewBB'. If there are PHI nodes in PredBB, evaluate them // to account for entry from PredPredBB. - DenseMap ValueMapping = - cloneInstructions(PredBB->begin(), PredBB->end(), NewBB, PredPredBB); + ValueToValueMapTy ValueMapping; + cloneInstructions(ValueMapping, PredBB->begin(), PredBB->end(), NewBB, + PredPredBB); // Copy the edge probabilities from PredBB to NewBB. if (BPI) @@ -2419,8 +2420,9 @@ void JumpThreadingPass::threadEdge(BasicBlock *BB, } // Copy all the instructions from BB to NewBB except the terminator. - DenseMap ValueMapping = - cloneInstructions(BB->begin(), std::prev(BB->end()), NewBB, PredBB); + ValueToValueMapTy ValueMapping; + cloneInstructions(ValueMapping, BB->begin(), std::prev(BB->end()), NewBB, + PredBB); // We didn't copy the terminator from BB over to NewBB, because there is now // an unconditional jump to SuccBB. Insert the unconditional jump. @@ -2675,7 +2677,7 @@ bool JumpThreadingPass::duplicateCondBranchOnPHIIntoPred( // We are going to have to map operands from the original BB block into the // PredBB block. Evaluate PHI nodes in BB. - DenseMap ValueMapping; + ValueToValueMapTy ValueMapping; BasicBlock::iterator BI = BB->begin(); for (; PHINode *PN = dyn_cast(BI); ++BI) @@ -2689,11 +2691,14 @@ bool JumpThreadingPass::duplicateCondBranchOnPHIIntoPred( // Remap operands to patch up intra-block references. for (unsigned i = 0, e = New->getNumOperands(); i != e; ++i) if (Instruction *Inst = dyn_cast(New->getOperand(i))) { - DenseMap::iterator I = ValueMapping.find(Inst); + ValueToValueMapTy::iterator I = ValueMapping.find(Inst); if (I != ValueMapping.end()) New->setOperand(i, I->second); } + // Remap debug variable operands. + remapDebugVariable(ValueMapping, New); + // If this instruction can be simplified after the operands are updated, // just use the simplified value instead. This frequently happens due to // phi translation. diff --git a/llvm/lib/Transforms/Utils/CloneFunction.cpp b/llvm/lib/Transforms/Utils/CloneFunction.cpp index 3eac726994ae..303a09805a9d 100644 --- a/llvm/lib/Transforms/Utils/CloneFunction.cpp +++ b/llvm/lib/Transforms/Utils/CloneFunction.cpp @@ -1131,6 +1131,9 @@ BasicBlock *llvm::DuplicateInstructionsInSplitBetween( if (I != ValueMapping.end()) New->setOperand(i, I->second); } + + // Remap debug variable operands. + remapDebugVariable(ValueMapping, New); } return NewBB; diff --git a/llvm/lib/Transforms/Utils/Local.cpp b/llvm/lib/Transforms/Utils/Local.cpp index 5f456092bf4e..f3cd3104c312 100644 --- a/llvm/lib/Transforms/Utils/Local.cpp +++ b/llvm/lib/Transforms/Utils/Local.cpp @@ -3685,6 +3685,30 @@ DIExpression *llvm::getExpressionForConstant(DIBuilder &DIB, const Constant &C, return nullptr; } +void llvm::remapDebugVariable(ValueToValueMapTy &Mapping, Instruction *Inst) { + auto RemapDebugOperands = [&Mapping](auto *DV, auto Set) { + for (auto *Op : Set) { + auto I = Mapping.find(Op); + if (I != Mapping.end()) + DV->replaceVariableLocationOp(Op, I->second, /*AllowEmpty=*/true); + } + }; + auto RemapAssignAddress = [&Mapping](auto *DA) { + auto I = Mapping.find(DA->getAddress()); + if (I != Mapping.end()) + DA->setAddress(I->second); + }; + if (auto DVI = dyn_cast(Inst)) + RemapDebugOperands(DVI, DVI->location_ops()); + if (auto DAI = dyn_cast(Inst)) + RemapAssignAddress(DAI); + for (DbgVariableRecord &DVR : filterDbgVars(Inst->getDbgRecordRange())) { + RemapDebugOperands(&DVR, DVR.location_ops()); + if (DVR.isDbgAssign()) + RemapAssignAddress(&DVR); + } +} + namespace { /// A potential constituent of a bitreverse or bswap expression. See diff --git a/llvm/test/Transforms/CallSiteSplitting/callsite-split-debug.ll b/llvm/test/Transforms/CallSiteSplitting/callsite-split-debug.ll index 8f10dcb30d7b..68c906d616c9 100644 --- a/llvm/test/Transforms/CallSiteSplitting/callsite-split-debug.ll +++ b/llvm/test/Transforms/CallSiteSplitting/callsite-split-debug.ll @@ -1,4 +1,4 @@ -; RUN: opt -S -passes=callsite-splitting -o - < %s | FileCheck %s +; RUN: opt -S -passes=callsite-splitting -o - < %s | FileCheck %s --check-prefixes=CHECK,CHECK-DEBUG ; RUN: opt -S -strip-debug -passes=callsite-splitting -o - < %s | FileCheck %s define internal i16 @bar(i16 %p1, i16 %p2) { @@ -8,6 +8,9 @@ define internal i16 @bar(i16 %p1, i16 %p2) { define i16 @foo(i16 %in) { bb0: + %a = alloca i16, align 4, !DIAssignID !12 + call void @llvm.dbg.assign(metadata i1 undef, metadata !11, metadata !DIExpression(), metadata !12, metadata ptr %a, metadata !DIExpression()), !dbg !8 + store i16 7, ptr %a, align 4, !DIAssignID !13 br label %bb1 bb1: @@ -20,13 +23,21 @@ bb2: CallsiteBB: %1 = phi i16 [ 0, %bb1 ], [ 1, %bb2 ] %c = phi i16 [ 2, %bb1 ], [ 3, %bb2 ] + %p = phi ptr [ %a, %bb1 ], [ %a, %bb2 ] + call void @llvm.dbg.value(metadata i16 %1, metadata !7, metadata !DIExpression()), !dbg !8 call void @llvm.dbg.value(metadata i16 %c, metadata !7, metadata !DIExpression()), !dbg !8 + call void @llvm.dbg.value(metadata !DIArgList(i16 %1, i16 %c), metadata !7, metadata !DIExpression()), !dbg !8 + call void @llvm.dbg.value(metadata !DIArgList(i16 %c, i16 %c), metadata !7, metadata !DIExpression()), !dbg !8 + call void @llvm.dbg.assign(metadata i16 %1, metadata !11, metadata !DIExpression(), metadata !13, metadata ptr %a, metadata !DIExpression()), !dbg !8 + call void @llvm.dbg.assign(metadata i16 %c, metadata !11, metadata !DIExpression(), metadata !13, metadata ptr %a, metadata !DIExpression()), !dbg !8 + call void @llvm.dbg.assign(metadata i16 %1, metadata !11, metadata !DIExpression(), metadata !13, metadata ptr %p, metadata !DIExpression()), !dbg !8 %2 = call i16 @bar(i16 %1, i16 5) ret i16 %2 } ; Function Attrs: nounwind readnone speculatable declare void @llvm.dbg.value(metadata, metadata, metadata) #0 +declare void @llvm.dbg.assign(metadata, metadata, metadata, metadata, metadata, metadata) attributes #0 = { nounwind readnone speculatable } @@ -43,14 +54,37 @@ attributes #0 = { nounwind readnone speculatable } !6 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 4, unit: !0) !7 = !DILocalVariable(name: "c", scope: !6, line: 5, type: !5) !8 = !DILocation(line: 5, column: 7, scope: !6) +!11 = !DILocalVariable(name: "a", scope: !6, line: 6, type: !5) +!12 = distinct !DIAssignID() +!13 = distinct !DIAssignID() ; The optimization should trigger even in the presence of the dbg.value in ; CallSiteBB. ; CHECK-LABEL: @foo ; CHECK-LABEL: bb1.split: +; CHECK-DEBUG: call void @llvm.dbg.value(metadata i16 0, metadata ![[DBG_1:[0-9]+]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.value(metadata i16 2, metadata ![[DBG_1]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.value(metadata !DIArgList(i16 0, i16 2), {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.value(metadata !DIArgList(i16 2, i16 2), {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.assign(metadata i16 0, metadata ![[DBG_2:[0-9]+]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.assign(metadata i16 2, metadata ![[DBG_2]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.assign(metadata i16 0, metadata ![[DBG_2]], metadata !DIExpression(), metadata ![[ID_1:[0-9]+]], metadata ptr %a, {{.*}} ; CHECK: [[TMP1:%[0-9]+]] = call i16 @bar(i16 0, i16 5) + ; CHECK-LABEL: bb2.split: +; CHECK-DEBUG: call void @llvm.dbg.value(metadata i16 1, metadata ![[DBG_1]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.value(metadata i16 3, metadata ![[DBG_1]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.value(metadata !DIArgList(i16 1, i16 3), {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.value(metadata !DIArgList(i16 3, i16 3), {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.assign(metadata i16 1, metadata ![[DBG_2]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.assign(metadata i16 3, metadata ![[DBG_2]], {{.*}} +; CHECK-DEBUG: call void @llvm.dbg.assign(metadata i16 1, metadata ![[DBG_2]], metadata !DIExpression(), metadata ![[ID_1:[0-9]+]], metadata ptr %a, {{.*}} ; CHECK: [[TMP2:%[0-9]+]] = call i16 @bar(i16 1, i16 5) + ; CHECK-LABEL: CallsiteBB ; CHECK: %phi.call = phi i16 [ [[TMP2]], %bb2.split ], [ [[TMP1]], %bb1.split + +; CHECK-DEBUG-DAG: ![[DBG_1]] = !DILocalVariable(name: "c"{{.*}}) +; CHECK-DEBUG-DAG: ![[DBG_2]] = !DILocalVariable(name: "a"{{.*}}) +; CHECK-DEBUG-DAG: ![[ID_1]] = distinct !DIAssignID() -- GitLab From c379a5b69e7e1917589a1d0b6993d74e6697490e Mon Sep 17 00:00:00 2001 From: Alex Bradbury Date: Fri, 26 Apr 2024 13:49:27 +0100 Subject: [PATCH 056/301] [RISCV][NFC] Future-proof reference to ISA manual in RISCVInstrInfoC.td The reference to a particular page number is long since out of date. Instead, let's name the section title which at least has remained stable so far. --- llvm/lib/Target/RISCV/RISCVInstrInfoC.td | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td index 18d38348f721..f4e50d7aa45c 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoC.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoC.td @@ -841,7 +841,7 @@ def : InstAlias<".insn_cj $opcode, $funct3, $imm11", //===----------------------------------------------------------------------===// // Patterns are defined in the same order the compressed instructions appear -// on page 82 of the ISA manual. +// under the "RVC Instruction Set Listings" section of the ISA manual. // Quadrant 0 let Predicates = [HasStdExtCOrZca] in { -- GitLab From 55d85c84ac01fda633c82e7ba821f6e62352a5c3 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 26 Apr 2024 14:11:03 +0100 Subject: [PATCH 057/301] [DAG] visitORCommutative - fold build_pair(not(x),not(y)) -> not(build_pair(x,y)) style patterns (#90050) (Sorry, not an actual build_pair node just a similar pattern). For cases where we're concatenating 2 integers into a double width integer, see if both integer sources are NOT patterns. We could take this further and handle all logic ops with a constant operands, but I just wanted to handle the case reported on #89533 initially. Fixes #89533 --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 21 +++++++ llvm/test/CodeGen/X86/combine-or.ll | 10 ++-- .../subvectorwise-store-of-vector-splat.ll | 56 +++---------------- 3 files changed, 33 insertions(+), 54 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f984d4b39596..062a9743b8cc 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -7620,6 +7620,7 @@ SDValue DAGCombiner::visitORLike(SDValue N0, SDValue N1, const SDLoc &DL) { static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1, SDNode *N) { EVT VT = N0.getValueType(); + unsigned BW = VT.getScalarSizeInBits(); SDLoc DL(N); auto peekThroughResize = [](SDValue V) { @@ -7689,6 +7690,26 @@ static SDValue visitORCommutative(SelectionDAG &DAG, SDValue N0, SDValue N1, peekThroughZext(N0.getOperand(2)) == peekThroughZext(N1.getOperand(1))) return N0; + // Attempt to match a legalized build_pair-esque pattern: + // or(shl(aext(Hi),BW/2),zext(Lo)) + SDValue Lo, Hi; + if (sd_match(N0, + m_OneUse(m_Shl(m_AnyExt(m_Value(Hi)), m_SpecificInt(BW / 2)))) && + sd_match(N1, m_ZExt(m_Value(Lo))) && + Lo.getScalarValueSizeInBits() == (BW / 2) && + Lo.getValueType() == Hi.getValueType()) { + // Fold build_pair(not(Lo),not(Hi)) -> not(build_pair(Lo,Hi)). + SDValue NotLo, NotHi; + if (sd_match(Lo, m_OneUse(m_Not(m_Value(NotLo)))) && + sd_match(Hi, m_OneUse(m_Not(m_Value(NotHi))))) { + Lo = DAG.getNode(ISD::ZERO_EXTEND, DL, VT, NotLo); + Hi = DAG.getNode(ISD::ANY_EXTEND, DL, VT, NotHi); + Hi = DAG.getNode(ISD::SHL, DL, VT, Hi, + DAG.getShiftAmountConstant(BW / 2, VT, DL)); + return DAG.getNOT(DL, DAG.getNode(ISD::OR, DL, VT, Lo, Hi), VT); + } + } + return SDValue(); } diff --git a/llvm/test/CodeGen/X86/combine-or.ll b/llvm/test/CodeGen/X86/combine-or.ll index 8419001de236..3b2102f46a29 100644 --- a/llvm/test/CodeGen/X86/combine-or.ll +++ b/llvm/test/CodeGen/X86/combine-or.ll @@ -186,11 +186,10 @@ define i64 @or_build_pair_not(i32 %a0, i32 %a1) { ; CHECK-LABEL: or_build_pair_not: ; CHECK: # %bb.0: ; CHECK-NEXT: # kill: def $esi killed $esi def $rsi -; CHECK-NEXT: # kill: def $edi killed $edi def $rdi -; CHECK-NEXT: notl %edi -; CHECK-NEXT: notl %esi ; CHECK-NEXT: shlq $32, %rsi -; CHECK-NEXT: leaq (%rsi,%rdi), %rax +; CHECK-NEXT: movl %edi, %eax +; CHECK-NEXT: orq %rsi, %rax +; CHECK-NEXT: notq %rax ; CHECK-NEXT: retq %n0 = xor i32 %a0, -1 %n1 = xor i32 %a1, -1 @@ -269,12 +268,11 @@ define i64 @PR89533(<64 x i8> %a0) { ; AVX2-NEXT: vpbroadcastb {{.*#+}} ymm2 = [95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95,95] ; AVX2-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm0 ; AVX2-NEXT: vpmovmskb %ymm0, %eax -; AVX2-NEXT: notl %eax ; AVX2-NEXT: vpcmpeqb %ymm2, %ymm1, %ymm0 ; AVX2-NEXT: vpmovmskb %ymm0, %ecx -; AVX2-NEXT: notl %ecx ; AVX2-NEXT: shlq $32, %rcx ; AVX2-NEXT: orq %rax, %rcx +; AVX2-NEXT: notq %rcx ; AVX2-NEXT: xorl %eax, %eax ; AVX2-NEXT: tzcntq %rcx, %rax ; AVX2-NEXT: vzeroupper diff --git a/llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll b/llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll index e0f438eb7cc8..ae66c5420638 100644 --- a/llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll +++ b/llvm/test/CodeGen/X86/subvectorwise-store-of-vector-splat.ll @@ -3060,12 +3060,7 @@ define void @vec384_v3i32(ptr %in.subvec.ptr, ptr %out.subvec.ptr, ptr %out.vec. ; SCALAR: # %bb.0: ; SCALAR-NEXT: movl 8(%rdi), %eax ; SCALAR-NEXT: movq (%rdi), %rcx -; SCALAR-NEXT: movq %rcx, %rdi -; SCALAR-NEXT: shrq $32, %rdi -; SCALAR-NEXT: notl %edi -; SCALAR-NEXT: shlq $32, %rdi -; SCALAR-NEXT: notl %ecx -; SCALAR-NEXT: orq %rdi, %rcx +; SCALAR-NEXT: notq %rcx ; SCALAR-NEXT: notl %eax ; SCALAR-NEXT: movl %eax, 8(%rsi) ; SCALAR-NEXT: movq %rcx, (%rsi) @@ -3196,12 +3191,7 @@ define void @vec384_v3f32(ptr %in.subvec.ptr, ptr %out.subvec.ptr, ptr %out.vec. ; SCALAR: # %bb.0: ; SCALAR-NEXT: movl 8(%rdi), %eax ; SCALAR-NEXT: movq (%rdi), %rcx -; SCALAR-NEXT: movq %rcx, %rdi -; SCALAR-NEXT: shrq $32, %rdi -; SCALAR-NEXT: notl %edi -; SCALAR-NEXT: shlq $32, %rdi -; SCALAR-NEXT: notl %ecx -; SCALAR-NEXT: orq %rdi, %rcx +; SCALAR-NEXT: notq %rcx ; SCALAR-NEXT: notl %eax ; SCALAR-NEXT: movl %eax, 8(%rsi) ; SCALAR-NEXT: movq %rcx, (%rsi) @@ -4216,25 +4206,10 @@ define void @vec384_v6i32(ptr %in.subvec.ptr, ptr %out.subvec.ptr, ptr %out.vec. ; SCALAR: # %bb.0: ; SCALAR-NEXT: movq (%rdi), %rax ; SCALAR-NEXT: movq 8(%rdi), %rcx -; SCALAR-NEXT: movq %rax, %r8 -; SCALAR-NEXT: shrq $32, %r8 -; SCALAR-NEXT: movq %rcx, %r9 -; SCALAR-NEXT: shrq $32, %r9 ; SCALAR-NEXT: movq 16(%rdi), %rdi -; SCALAR-NEXT: movq %rdi, %r10 -; SCALAR-NEXT: shrq $32, %r10 -; SCALAR-NEXT: notl %r10d -; SCALAR-NEXT: shlq $32, %r10 -; SCALAR-NEXT: notl %edi -; SCALAR-NEXT: orq %r10, %rdi -; SCALAR-NEXT: notl %r9d -; SCALAR-NEXT: shlq $32, %r9 -; SCALAR-NEXT: notl %ecx -; SCALAR-NEXT: orq %r9, %rcx -; SCALAR-NEXT: notl %r8d -; SCALAR-NEXT: shlq $32, %r8 -; SCALAR-NEXT: notl %eax -; SCALAR-NEXT: orq %r8, %rax +; SCALAR-NEXT: notq %rdi +; SCALAR-NEXT: notq %rcx +; SCALAR-NEXT: notq %rax ; SCALAR-NEXT: movq %rax, (%rsi) ; SCALAR-NEXT: movq %rcx, 8(%rsi) ; SCALAR-NEXT: movq %rdi, 16(%rsi) @@ -4303,25 +4278,10 @@ define void @vec384_v6f32(ptr %in.subvec.ptr, ptr %out.subvec.ptr, ptr %out.vec. ; SCALAR: # %bb.0: ; SCALAR-NEXT: movq (%rdi), %rax ; SCALAR-NEXT: movq 8(%rdi), %rcx -; SCALAR-NEXT: movq %rax, %r8 -; SCALAR-NEXT: shrq $32, %r8 -; SCALAR-NEXT: movq %rcx, %r9 -; SCALAR-NEXT: shrq $32, %r9 ; SCALAR-NEXT: movq 16(%rdi), %rdi -; SCALAR-NEXT: movq %rdi, %r10 -; SCALAR-NEXT: shrq $32, %r10 -; SCALAR-NEXT: notl %r10d -; SCALAR-NEXT: shlq $32, %r10 -; SCALAR-NEXT: notl %edi -; SCALAR-NEXT: orq %r10, %rdi -; SCALAR-NEXT: notl %r9d -; SCALAR-NEXT: shlq $32, %r9 -; SCALAR-NEXT: notl %ecx -; SCALAR-NEXT: orq %r9, %rcx -; SCALAR-NEXT: notl %r8d -; SCALAR-NEXT: shlq $32, %r8 -; SCALAR-NEXT: notl %eax -; SCALAR-NEXT: orq %r8, %rax +; SCALAR-NEXT: notq %rdi +; SCALAR-NEXT: notq %rcx +; SCALAR-NEXT: notq %rax ; SCALAR-NEXT: movq %rax, (%rsi) ; SCALAR-NEXT: movq %rcx, 8(%rsi) ; SCALAR-NEXT: movq %rdi, 16(%rsi) -- GitLab From bb1a8bbbf06f4cbe66b685b068add5ae63c21697 Mon Sep 17 00:00:00 2001 From: erichkeane Date: Fri, 26 Apr 2024 06:17:05 -0700 Subject: [PATCH 058/301] [NFC][OpenACC] Remove stale FIXME comment in a test A recent patch changed the array sections to work differently for OpenACC, including for the diagnostic, so the FIXME is now irrelevant. --- clang/test/ParserOpenACC/parse-cache-construct.cpp | 2 -- 1 file changed, 2 deletions(-) diff --git a/clang/test/ParserOpenACC/parse-cache-construct.cpp b/clang/test/ParserOpenACC/parse-cache-construct.cpp index 1ab2153a68be..f1c71e8b5847 100644 --- a/clang/test/ParserOpenACC/parse-cache-construct.cpp +++ b/clang/test/ParserOpenACC/parse-cache-construct.cpp @@ -72,8 +72,6 @@ void use() { #pragma acc cache(Arrs.MemArr[3].array[1:4]) } for (int i = 0; i < 10; ++i) { - // FIXME: Once we have a new array-section type to represent OpenACC as - // well, change this error message. // expected-error@+2{{OpenACC sub-array is not allowed here}} // expected-warning@+1{{OpenACC construct 'cache' not yet implemented, pragma ignored}} #pragma acc cache(Arrs.MemArr[3:4].array[1:4]) -- GitLab From 405c018c71fb685425df4fe173e54f5edc5d6979 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Fri, 26 Apr 2024 15:21:44 +0200 Subject: [PATCH 059/301] DAG: Simplify demanded bits for truncating atomic_store (#90113) It's really unfortunate that STORE and ATOMIC_STORE are separate opcodes. This duplicates a basic simplify demanded for the truncating case. This avoids some AMDGPU lit regressions in a future patch. I'm not sure how to craft a test that exposes this without first introducing the regressions by promoting half to i16. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 20 +++++++++++++++++++ 1 file changed, 20 insertions(+) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 062a9743b8cc..b6d5b309ceb9 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -530,6 +530,7 @@ namespace { bool refineExtractVectorEltIntoMultipleNarrowExtractVectorElts(SDNode *N); SDValue visitSTORE(SDNode *N); + SDValue visitATOMIC_STORE(SDNode *N); SDValue visitLIFETIME_END(SDNode *N); SDValue visitINSERT_VECTOR_ELT(SDNode *N); SDValue visitEXTRACT_VECTOR_ELT(SDNode *N); @@ -1909,6 +1910,7 @@ SDValue DAGCombiner::visit(SDNode *N) { case ISD::BR_CC: return visitBR_CC(N); case ISD::LOAD: return visitLOAD(N); case ISD::STORE: return visitSTORE(N); + case ISD::ATOMIC_STORE: return visitATOMIC_STORE(N); case ISD::INSERT_VECTOR_ELT: return visitINSERT_VECTOR_ELT(N); case ISD::EXTRACT_VECTOR_ELT: return visitEXTRACT_VECTOR_ELT(N); case ISD::BUILD_VECTOR: return visitBUILD_VECTOR(N); @@ -21137,6 +21139,24 @@ SDValue DAGCombiner::replaceStoreOfInsertLoad(StoreSDNode *ST) { ST->getMemOperand()->getFlags()); } +SDValue DAGCombiner::visitATOMIC_STORE(SDNode *N) { + AtomicSDNode *ST = cast(N); + SDValue Val = ST->getVal(); + EVT VT = Val.getValueType(); + EVT MemVT = ST->getMemoryVT(); + + if (MemVT.bitsLT(VT)) { // Is truncating store + APInt TruncDemandedBits = APInt::getLowBitsSet(VT.getScalarSizeInBits(), + MemVT.getScalarSizeInBits()); + // See if we can simplify the operation with SimplifyDemandedBits, which + // only works if the value has a single use. + if (SimplifyDemandedBits(Val, TruncDemandedBits)) + return SDValue(N, 0); + } + + return SDValue(); +} + SDValue DAGCombiner::visitSTORE(SDNode *N) { StoreSDNode *ST = cast(N); SDValue Chain = ST->getChain(); -- GitLab From 904b1a850536d273b0e11bd17a7ea642ba3b5bc4 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Fri, 26 Apr 2024 08:28:10 -0500 Subject: [PATCH 060/301] [Offload] Remove remaining `__tgt_register_requires` references (#90198) Summary: This call was removed a few months ago to allow the runtime to actually init / deinit in a correct order. However that patch forgot to remove a few leftover uses. --- llvm/include/llvm/Frontend/OpenMP/OMPKinds.def | 3 --- llvm/test/Transforms/OpenMP/add_attributes.ll | 11 ----------- offload/test/unified_shared_memory/api.c | 9 --------- offload/test/unified_shared_memory/close_manual.c | 6 ------ offload/test/unified_shared_memory/shared_update.c | 9 --------- 5 files changed, 38 deletions(-) diff --git a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def index d22d2a8e948b..fe09bb8177c2 100644 --- a/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def +++ b/llvm/include/llvm/Frontend/OpenMP/OMPKinds.def @@ -436,7 +436,6 @@ __OMP_RTL(__tgt_target_kernel, false, Int32, IdentPtr, Int64, Int32, Int32, VoidPtr, KernelArgsPtr) __OMP_RTL(__tgt_target_kernel_nowait, false, Int32, IdentPtr, Int64, Int32, Int32, VoidPtr, KernelArgsPtr, Int32, VoidPtr, Int32, VoidPtr) -__OMP_RTL(__tgt_register_requires, false, Void, Int64) __OMP_RTL(__tgt_target_data_begin_mapper, false, Void, IdentPtr, Int64, Int32, VoidPtrPtr, VoidPtrPtr, Int64Ptr, Int64Ptr, VoidPtrPtr, VoidPtrPtr) __OMP_RTL(__tgt_target_data_begin_nowait_mapper, false, Void, IdentPtr, Int64, Int32, @@ -1025,8 +1024,6 @@ __OMP_RTL_ATTRS(__tgt_target_kernel_nowait, ForkAttrs, SExt, ParamAttrs(AttributeSet(), AttributeSet(), SExt, SExt, AttributeSet(), AttributeSet(), SExt, AttributeSet(), SExt)) -__OMP_RTL_ATTRS(__tgt_register_requires, ForkAttrs, AttributeSet(), - ParamAttrs()) __OMP_RTL_ATTRS(__tgt_target_data_begin_mapper, ForkAttrs, AttributeSet(), ParamAttrs(AttributeSet(), AttributeSet(), SExt)) __OMP_RTL_ATTRS(__tgt_target_data_begin_nowait_mapper, ForkAttrs, AttributeSet(), diff --git a/llvm/test/Transforms/OpenMP/add_attributes.ll b/llvm/test/Transforms/OpenMP/add_attributes.ll index 47ff5cad4e7e..ebcca3067f04 100644 --- a/llvm/test/Transforms/OpenMP/add_attributes.ll +++ b/llvm/test/Transforms/OpenMP/add_attributes.ll @@ -641,8 +641,6 @@ declare i32 @__tgt_target_teams_mapper(ptr, i64, ptr, i32, ptr, ptr, ptr, ptr, p declare i32 @__tgt_target_teams_nowait_mapper(ptr, i64, ptr, i32, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, i32, ptr) -declare void @__tgt_register_requires(i64) - declare void @__tgt_target_data_begin_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) declare void @__tgt_target_data_begin_nowait_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) @@ -1248,9 +1246,6 @@ declare i32 @__tgt_target_kernel_nowait(ptr, i64, i32, i32, ptr, ptr, i32, ptr, ; CHECK: ; Function Attrs: nounwind ; CHECK-NEXT: declare i32 @__tgt_target_teams_nowait_mapper(ptr, i64, ptr, i32, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, i32, ptr) -; CHECK: ; Function Attrs: nounwind -; CHECK-NEXT: declare void @__tgt_register_requires(i64) - ; CHECK: ; Function Attrs: nounwind ; CHECK-NEXT: declare void @__tgt_target_data_begin_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) @@ -1893,9 +1888,6 @@ declare i32 @__tgt_target_kernel_nowait(ptr, i64, i32, i32, ptr, ptr, i32, ptr, ; OPTIMISTIC: ; Function Attrs: nounwind ; OPTIMISTIC-NEXT: declare i32 @__tgt_target_teams_nowait_mapper(ptr, i64, ptr, i32, ptr, ptr, ptr, ptr, ptr, ptr, i32, i32, i32, ptr, i32, ptr) -; OPTIMISTIC: ; Function Attrs: nounwind -; OPTIMISTIC-NEXT: declare void @__tgt_register_requires(i64) - ; OPTIMISTIC: ; Function Attrs: nounwind ; OPTIMISTIC-NEXT: declare void @__tgt_target_data_begin_mapper(ptr, i64, i32, ptr, ptr, ptr, ptr, ptr, ptr) @@ -2551,9 +2543,6 @@ declare i32 @__tgt_target_kernel_nowait(ptr, i64, i32, i32, ptr, ptr, i32, ptr, ; EXT: ; Function Attrs: nounwind ; EXT-NEXT: declare signext i32 @__tgt_target_teams_nowait_mapper(ptr, i64, ptr, i32 signext, ptr, ptr, ptr, ptr, ptr, ptr, i32 signext, i32 signext, i32 signext, ptr, i32 signext, ptr) -; EXT: ; Function Attrs: nounwind -; EXT-NEXT: declare void @__tgt_register_requires(i64) - ; EXT: ; Function Attrs: nounwind ; EXT-NEXT: declare void @__tgt_target_data_begin_mapper(ptr, i64, i32 signext, ptr, ptr, ptr, ptr, ptr, ptr) diff --git a/offload/test/unified_shared_memory/api.c b/offload/test/unified_shared_memory/api.c index c7ab055abb51..b938971b4b03 100644 --- a/offload/test/unified_shared_memory/api.c +++ b/offload/test/unified_shared_memory/api.c @@ -9,11 +9,6 @@ #include #include -// --------------------------------------------------------------------------- -// Various definitions copied from OpenMP RTL - -extern void __tgt_register_requires(int64_t); - // End of definitions copied from OpenMP RTL. // --------------------------------------------------------------------------- @@ -32,10 +27,6 @@ void init(int A[], int B[], int C[]) { int main(int argc, char *argv[]) { const int device = omp_get_default_device(); - // Manual registration of requires flags for Clang versions - // that do not support requires. - __tgt_register_requires(8); - // CHECK: Initial device: [[INITIAL_DEVICE:[0-9]+]] printf("Initial device: %d\n", omp_get_initial_device()); // CHECK: Num devices: [[INITIAL_DEVICE]] diff --git a/offload/test/unified_shared_memory/close_manual.c b/offload/test/unified_shared_memory/close_manual.c index 9985e822c05d..c588cb1c403a 100644 --- a/offload/test/unified_shared_memory/close_manual.c +++ b/offload/test/unified_shared_memory/close_manual.c @@ -8,8 +8,6 @@ // --------------------------------------------------------------------------- // Various definitions copied from OpenMP RTL -extern void __tgt_register_requires(int64_t); - extern void __tgt_target_data_begin(int64_t device_id, int32_t arg_num, void **args_base, void **args, int64_t *arg_sizes, int64_t *arg_types); @@ -30,10 +28,6 @@ int main(int argc, char *argv[]) { void *host_alloc = 0, *device_alloc = 0; int *a = (int *)malloc(N * sizeof(int)); - // Manual registration of requires flags for Clang versions - // that do not support requires. - __tgt_register_requires(8); - // Init for (int i = 0; i < N; ++i) { a[i] = 10; diff --git a/offload/test/unified_shared_memory/shared_update.c b/offload/test/unified_shared_memory/shared_update.c index 65db9e4f6bdc..f8eb11d56a6c 100644 --- a/offload/test/unified_shared_memory/shared_update.c +++ b/offload/test/unified_shared_memory/shared_update.c @@ -11,11 +11,6 @@ #include #include -// --------------------------------------------------------------------------- -// Various definitions copied from OpenMP RTL - -extern void __tgt_register_requires(int64_t); - // End of definitions copied from OpenMP RTL. // --------------------------------------------------------------------------- @@ -30,10 +25,6 @@ int main(int argc, char *argv[]) { int *alloc = (int *)malloc(N * sizeof(int)); int data[N]; - // Manual registration of requires flags for Clang versions - // that do not support requires. - __tgt_register_requires(8); - for (int i = 0; i < N; ++i) { alloc[i] = 10; data[i] = 1; -- GitLab From ace3bd0580d47fa044014eedd1e42ab6ab4d1e11 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Fri, 26 Apr 2024 14:48:34 +0100 Subject: [PATCH 061/301] Revert "[TableGen] Ignore inaccessible memory when checking pattern flags (#90061)" This reverts commit 6578356a4e3e6acd7983c74feab43ac96925894c. The patch had no effect due to a silly mistake and fixing the mistake causes other problems. --- llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp | 10 +--------- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp index e0e31739e262..88d353e89a46 100644 --- a/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp +++ b/llvm/utils/TableGen/Common/CodeGenDAGPatterns.cpp @@ -3616,15 +3616,7 @@ public: hasChain = true; if (const CodeGenIntrinsic *IntInfo = N.getIntrinsicInfo(CDP)) { - // Ignore reads/writes to inaccessible memory. These should not imply - // mayLoad/mayStore on the instruction because they are often used to - // model dependencies that Machine IR expresses as uses/defs of a - // special physical register. - ModRefInfo MR = ModRefInfo::NoModRef; - for (MemoryEffects::Location Loc : MemoryEffects::locations()) { - if (Loc != MemoryEffects::Location::InaccessibleMem) - MR |= IntInfo->ME.getModRef(); - } + ModRefInfo MR = IntInfo->ME.getModRef(); // If this is an intrinsic, analyze it. if (isRefSet(MR)) mayLoad = true; // These may load memory. -- GitLab From d74e42acd2479eb9f3bd8077fd3be2f3395aa638 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Tue, 16 Apr 2024 14:55:41 -0400 Subject: [PATCH 062/301] [SLP]Attempt to vectorize long stores, if short one failed. We can try to vectorize long store sequences, if short ones were unsuccessful because of the non-profitable vectorization. It should not increase compile time significantly (stores are sorted already, complexity is n x log n), but vectorize extra code. Metric: size..text Program size..text results results0 diff test-suite :: External/SPEC/CINT2006/400.perlbench/400.perlbench.test 1088012.00 1088236.00 0.0% test-suite :: SingleSource/UnitTests/matrix-types-spec.test 480396.00 480476.00 0.0% test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 664613.00 664661.00 0.0% test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 664613.00 664661.00 0.0% test-suite :: External/SPEC/CFP2017rate/510.parest_r/510.parest_r.test 2041105.00 2040961.00 -0.0% test-suite :: MultiSource/Applications/JM/lencod/lencod.test 836563.00 836387.00 -0.0% test-suite :: MultiSource/Benchmarks/7zip/7zip-benchmark.test 1035100.00 1032140.00 -0.3% In all benchmarks extra code gets vectorized Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/88563 --- .../llvm/Transforms/Vectorize/SLPVectorizer.h | 13 +- .../Transforms/Vectorize/SLPVectorizer.cpp | 340 +++++++++++++++--- .../AArch64/vec3-reorder-reshuffle.ll | 30 +- .../Transforms/SLPVectorizer/X86/pr46983.ll | 75 +--- 4 files changed, 327 insertions(+), 131 deletions(-) diff --git a/llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h b/llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h index 326006fbb880..4f99d171469e 100644 --- a/llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h +++ b/llvm/include/llvm/Transforms/Vectorize/SLPVectorizer.h @@ -153,10 +153,15 @@ private: /// a vectorization chain. bool vectorizeChainsInBlock(BasicBlock *BB, slpvectorizer::BoUpSLP &R); - bool vectorizeStoreChain(ArrayRef Chain, slpvectorizer::BoUpSLP &R, - unsigned Idx, unsigned MinVF); - - bool vectorizeStores(ArrayRef Stores, slpvectorizer::BoUpSLP &R); + std::optional vectorizeStoreChain(ArrayRef Chain, + slpvectorizer::BoUpSLP &R, + unsigned Idx, unsigned MinVF, + unsigned &Size); + + bool vectorizeStores( + ArrayRef Stores, slpvectorizer::BoUpSLP &R, + DenseSet> + &Visited); /// The store instructions in a basic block organized by base pointer. StoreListMap Stores; diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 0cd7bd777222..fbece8c0109c 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -1135,6 +1135,7 @@ public: ScalarToTreeEntry.clear(); MultiNodeScalars.clear(); MustGather.clear(); + NonScheduledFirst.clear(); EntryToLastInstruction.clear(); ExternalUses.clear(); ExternalUsesAsGEPs.clear(); @@ -1252,7 +1253,7 @@ public: /// effectively impossible for the backend to undo. /// TODO: If load combining is allowed in the IR optimizer, this analysis /// may not be necessary. - bool isLoadCombineCandidate() const; + bool isLoadCombineCandidate(ArrayRef Stores) const; /// Checks if the given array of loads can be represented as a vectorized, /// scatter or just simple gather. @@ -2356,6 +2357,14 @@ public: bool isAnyGathered(const SmallDenseSet &Vals) const { return any_of(MustGather, [&](Value *V) { return Vals.contains(V); }); } + /// Checks if the given value is gathered in one of the nodes. + bool isGathered(const Value *V) const { + return MustGather.contains(V); + } + /// Checks if the specified value was not schedule. + bool isNotScheduled(const Value *V) const { + return NonScheduledFirst.contains(V); + } /// Check if the value is vectorized in the tree. bool isVectorized(Value *V) const { return getTreeEntry(V); } @@ -3071,6 +3080,9 @@ private: /// A list of scalars that we found that we need to keep as scalars. ValueSet MustGather; + /// A set of first non-schedulable values. + ValueSet NonScheduledFirst; + /// A map between the vectorized entries and the last instructions in the /// bundles. The bundles are built in use order, not in the def order of the /// instructions. So, we cannot rely directly on the last instruction in the @@ -6646,6 +6658,7 @@ void BoUpSLP::buildTree_rec(ArrayRef VL, unsigned Depth, "tryScheduleBundle should cancelScheduling on failure"); newTreeEntry(VL, std::nullopt /*not vectorized*/, S, UserTreeIdx, ReuseShuffleIndicies); + NonScheduledFirst.insert(VL.front()); return; } LLVM_DEBUG(dbgs() << "SLP: We are able to schedule this bundle.\n"); @@ -9587,11 +9600,11 @@ bool BoUpSLP::isLoadCombineReductionCandidate(RecurKind RdxKind) const { /* MatchOr */ false); } -bool BoUpSLP::isLoadCombineCandidate() const { +bool BoUpSLP::isLoadCombineCandidate(ArrayRef Stores) const { // Peek through a final sequence of stores and check if all operations are // likely to be load-combined. - unsigned NumElts = VectorizableTree[0]->Scalars.size(); - for (Value *Scalar : VectorizableTree[0]->Scalars) { + unsigned NumElts = Stores.size(); + for (Value *Scalar : Stores) { Value *X; if (!match(Scalar, m_Store(m_Value(X), m_Value())) || !isLoadCombineCandidateImpl(X, NumElts, TTI, /* MatchOr */ true)) @@ -15210,8 +15223,11 @@ bool SLPVectorizerPass::runImpl(Function &F, ScalarEvolution *SE_, return Changed; } -bool SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R, - unsigned Idx, unsigned MinVF) { +std::optional +SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R, + unsigned Idx, unsigned MinVF, + unsigned &Size) { + Size = 0; LLVM_DEBUG(dbgs() << "SLP: Analyzing a store chain of length " << Chain.size() << "\n"); const unsigned Sz = R.getVectorElementSize(Chain[0]); @@ -15228,11 +15244,42 @@ bool SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R, LLVM_DEBUG(dbgs() << "SLP: Analyzing " << VF << " stores at offset " << Idx << "\n"); + SetVector ValOps; + for (Value *V : Chain) + ValOps.insert(cast(V)->getValueOperand()); + // Operands are not same/alt opcodes or non-power-of-2 uniques - exit. + InstructionsState S = getSameOpcode(ValOps.getArrayRef(), *TLI); + if (all_of(ValOps, IsaPred) && ValOps.size() > 1) { + DenseSet Stores(Chain.begin(), Chain.end()); + bool IsPowerOf2 = + isPowerOf2_32(ValOps.size()) || + (VectorizeNonPowerOf2 && isPowerOf2_32(ValOps.size() + 1)); + if ((!IsPowerOf2 && S.getOpcode() && S.getOpcode() != Instruction::Load && + (!S.MainOp->isSafeToRemove() || + any_of(ValOps.getArrayRef(), + [&](Value *V) { + return !isa(V) && + (V->getNumUses() > Chain.size() || + any_of(V->users(), [&](User *U) { + return !Stores.contains(U); + })); + }))) || + (ValOps.size() > Chain.size() / 2 && !S.getOpcode())) { + Size = (!IsPowerOf2 && S.getOpcode()) ? 1 : 2; + return false; + } + } + if (R.isLoadCombineCandidate(Chain)) + return true; R.buildTree(Chain); - if (R.isTreeTinyAndNotFullyVectorizable()) - return false; - if (R.isLoadCombineCandidate()) + // Check if tree tiny and store itself or its value is not vectorized. + if (R.isTreeTinyAndNotFullyVectorizable()) { + if (R.isGathered(Chain.front()) || + R.isNotScheduled(cast(Chain.front())->getValueOperand())) + return std::nullopt; + Size = R.getTreeSize(); return false; + } R.reorderTopToBottom(); R.reorderBottomToTop(); R.buildExternalUses(); @@ -15240,6 +15287,9 @@ bool SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R, R.computeMinimumValueSizes(); R.transformNodes(); + Size = R.getTreeSize(); + if (S.getOpcode() == Instruction::Load) + Size = 2; // cut off masked gather small trees InstructionCost Cost = R.getTreeCost(); LLVM_DEBUG(dbgs() << "SLP: Found cost = " << Cost << " for VF=" << VF << "\n"); @@ -15261,17 +15311,45 @@ bool SLPVectorizerPass::vectorizeStoreChain(ArrayRef Chain, BoUpSLP &R, return false; } -bool SLPVectorizerPass::vectorizeStores(ArrayRef Stores, - BoUpSLP &R) { +/// Checks if the quadratic mean deviation is less than 90% of the mean size. +static bool checkTreeSizes(ArrayRef> Sizes, + bool First) { + unsigned Num = 0; + uint64_t Sum = std::accumulate( + Sizes.begin(), Sizes.end(), static_cast(0), + [&](uint64_t V, const std::pair &Val) { + unsigned Size = First ? Val.first : Val.second; + if (Size == 1) + return V; + ++Num; + return V + Size; + }); + if (Num == 0) + return true; + uint64_t Mean = Sum / Num; + if (Mean == 0) + return true; + uint64_t Dev = std::accumulate( + Sizes.begin(), Sizes.end(), static_cast(0), + [&](uint64_t V, const std::pair &Val) { + unsigned P = First ? Val.first : Val.second; + if (P == 1) + return V; + return V + (P - Mean) * (P - Mean); + }) / + Num; + return Dev * 81 / (Mean * Mean) == 0; +} + +bool SLPVectorizerPass::vectorizeStores( + ArrayRef Stores, BoUpSLP &R, + DenseSet> + &Visited) { // We may run into multiple chains that merge into a single chain. We mark the // stores that we vectorized so that we don't visit the same store twice. BoUpSLP::ValueSet VectorizedStores; bool Changed = false; - // Stores the pair of stores (first_store, last_store) in a range, that were - // already tried to be vectorized. Allows to skip the store ranges that were - // already tried to be vectorized but the attempts were unsuccessful. - DenseSet> TriedSequences; struct StoreDistCompare { bool operator()(const std::pair &Op1, const std::pair &Op2) const { @@ -15299,7 +15377,14 @@ bool SLPVectorizerPass::vectorizeStores(ArrayRef Stores, PrevDist = DataVar.second; }); - if (Operands.size() <= 1) + if (Operands.size() <= 1 || + !Visited + .insert({Operands.front(), + cast(Operands.front())->getValueOperand(), + Operands.back(), + cast(Operands.back())->getValueOperand(), + Operands.size()}) + .second) continue; unsigned MaxVecRegSize = R.getMaxVecRegSize(); @@ -15308,13 +15393,19 @@ bool SLPVectorizerPass::vectorizeStores(ArrayRef Stores, unsigned MaxVF = std::min(R.getMaximumVF(EltSize, Instruction::Store), MaxElts); + unsigned MaxRegVF = MaxVF; auto *Store = cast(Operands[0]); Type *StoreTy = Store->getValueOperand()->getType(); Type *ValueTy = StoreTy; if (auto *Trunc = dyn_cast(Store->getValueOperand())) ValueTy = Trunc->getSrcTy(); - unsigned MinVF = PowerOf2Ceil(TTI->getStoreMinimumVF( - R.getMinVF(DL->getTypeStoreSizeInBits(StoreTy)), StoreTy, ValueTy)); + if (ValueTy == StoreTy && + R.getVectorElementSize(Store->getValueOperand()) <= EltSize) + MaxVF = std::min(MaxVF, bit_floor(Operands.size())); + unsigned MinVF = std::max( + 2, PowerOf2Ceil(TTI->getStoreMinimumVF( + R.getMinVF(DL->getTypeStoreSizeInBits(StoreTy)), StoreTy, + ValueTy))); if (MaxVF < MinVF) { LLVM_DEBUG(dbgs() << "SLP: Vectorization infeasible as MaxVF (" << MaxVF @@ -15329,7 +15420,7 @@ bool SLPVectorizerPass::vectorizeStores(ArrayRef Stores, // consider cases where VF + 1 is a power-of-2, i.e. almost all vector // lanes are used. unsigned CandVF = Operands.size(); - if (isPowerOf2_32(CandVF + 1) && CandVF <= MaxVF) + if (isPowerOf2_32(CandVF + 1) && CandVF <= MaxRegVF) NonPowerOf2VF = CandVF; } @@ -15340,40 +15431,184 @@ bool SLPVectorizerPass::vectorizeStores(ArrayRef Stores, VF = Size > MaxVF ? NonPowerOf2VF : Size; Size *= 2; }); - unsigned StartIdx = 0; - for (unsigned Size : CandidateVFs) { - for (unsigned Cnt = StartIdx, E = Operands.size(); Cnt + Size <= E;) { - ArrayRef Slice = ArrayRef(Operands).slice(Cnt, Size); - assert( - all_of( - Slice, - [&](Value *V) { - return cast(V)->getValueOperand()->getType() == - cast(Slice.front()) - ->getValueOperand() - ->getType(); - }) && - "Expected all operands of same type."); - if (!VectorizedStores.count(Slice.front()) && - !VectorizedStores.count(Slice.back()) && - TriedSequences.insert(std::make_pair(Slice.front(), Slice.back())) - .second && - vectorizeStoreChain(Slice, R, Cnt, MinVF)) { - // Mark the vectorized stores so that we don't vectorize them again. - VectorizedStores.insert(Slice.begin(), Slice.end()); - Changed = true; - // If we vectorized initial block, no need to try to vectorize it - // again. - if (Cnt == StartIdx) - StartIdx += Size; - Cnt += Size; - continue; + unsigned End = Operands.size(); + unsigned Repeat = 0; + constexpr unsigned MaxAttempts = 4; + OwningArrayRef> RangeSizes(Operands.size()); + for_each(RangeSizes, [](std::pair &P) { + P.first = P.second = 1; + }); + DenseMap> NonSchedulable; + auto IsNotVectorized = [](bool First, + const std::pair &P) { + return First ? P.first > 0 : P.second > 0; + }; + auto IsVectorized = [](bool First, + const std::pair &P) { + return First ? P.first == 0 : P.second == 0; + }; + auto VFIsProfitable = [](bool First, unsigned Size, + const std::pair &P) { + return First ? Size >= P.first : Size >= P.second; + }; + auto FirstSizeSame = [](unsigned Size, + const std::pair &P) { + return Size == P.first; + }; + while (true) { + ++Repeat; + bool RepeatChanged = false; + bool AnyProfitableGraph; + for (unsigned Size : CandidateVFs) { + AnyProfitableGraph = false; + unsigned StartIdx = std::distance( + RangeSizes.begin(), + find_if(RangeSizes, std::bind(IsNotVectorized, Size >= MaxRegVF, + std::placeholders::_1))); + while (StartIdx < End) { + unsigned EndIdx = + std::distance(RangeSizes.begin(), + find_if(RangeSizes.drop_front(StartIdx), + std::bind(IsVectorized, Size >= MaxRegVF, + std::placeholders::_1))); + unsigned Sz = EndIdx >= End ? End : EndIdx; + for (unsigned Cnt = StartIdx; Cnt + Size <= Sz;) { + if (!checkTreeSizes(RangeSizes.slice(Cnt, Size), + Size >= MaxRegVF)) { + ++Cnt; + continue; + } + ArrayRef Slice = ArrayRef(Operands).slice(Cnt, Size); + assert(all_of(Slice, + [&](Value *V) { + return cast(V) + ->getValueOperand() + ->getType() == + cast(Slice.front()) + ->getValueOperand() + ->getType(); + }) && + "Expected all operands of same type."); + if (!NonSchedulable.empty()) { + auto [NonSchedSizeMax, NonSchedSizeMin] = + NonSchedulable.lookup(Slice.front()); + if (NonSchedSizeMax > 0 && NonSchedSizeMin <= Size) { + Cnt += NonSchedSizeMax; + continue; + } + } + unsigned TreeSize; + std::optional Res = + vectorizeStoreChain(Slice, R, Cnt, MinVF, TreeSize); + if (!Res) { + NonSchedulable + .try_emplace(Slice.front(), std::make_pair(Size, Size)) + .first->getSecond() + .second = Size; + } else if (*Res) { + // Mark the vectorized stores so that we don't vectorize them + // again. + VectorizedStores.insert(Slice.begin(), Slice.end()); + // Mark the vectorized stores so that we don't vectorize them + // again. + AnyProfitableGraph = RepeatChanged = Changed = true; + // If we vectorized initial block, no need to try to vectorize + // it again. + for_each(RangeSizes.slice(Cnt, Size), + [](std::pair &P) { + P.first = P.second = 0; + }); + if (Cnt < StartIdx + MinVF) { + for_each(RangeSizes.slice(StartIdx, Cnt - StartIdx), + [](std::pair &P) { + P.first = P.second = 0; + }); + StartIdx = Cnt + Size; + } + if (Cnt > Sz - Size - MinVF) { + for_each(RangeSizes.slice(Cnt + Size, Sz - (Cnt + Size)), + [](std::pair &P) { + P.first = P.second = 0; + }); + if (Sz == End) + End = Cnt; + Sz = Cnt; + } + Cnt += Size; + continue; + } + if (Size > 2 && Res && + !all_of(RangeSizes.slice(Cnt, Size), + std::bind(VFIsProfitable, Size >= MaxRegVF, TreeSize, + std::placeholders::_1))) { + Cnt += Size; + continue; + } + // Check for the very big VFs that we're not rebuilding same + // trees, just with larger number of elements. + if (Size > MaxRegVF && TreeSize > 1 && + all_of(RangeSizes.slice(Cnt, Size), + std::bind(FirstSizeSame, TreeSize, + std::placeholders::_1))) { + Cnt += Size; + while (Cnt != Sz && RangeSizes[Cnt].first == TreeSize) + ++Cnt; + continue; + } + if (TreeSize > 1) + for_each(RangeSizes.slice(Cnt, Size), + [&](std::pair &P) { + if (Size >= MaxRegVF) + P.second = std::max(P.second, TreeSize); + else + P.first = std::max(P.first, TreeSize); + }); + ++Cnt; + AnyProfitableGraph = true; + } + if (StartIdx >= End) + break; + if (Sz - StartIdx < Size && Sz - StartIdx >= MinVF) + AnyProfitableGraph = true; + StartIdx = std::distance( + RangeSizes.begin(), + find_if(RangeSizes.drop_front(Sz), + std::bind(IsNotVectorized, Size >= MaxRegVF, + std::placeholders::_1))); } - ++Cnt; + if (!AnyProfitableGraph && Size >= MaxRegVF) + break; } - // Check if the whole array was vectorized already - exit. - if (StartIdx >= Operands.size()) + // All values vectorized - exit. + if (all_of(RangeSizes, [](const std::pair &P) { + return P.first == 0 && P.second == 0; + })) break; + // Check if tried all attempts or no need for the last attempts at all. + if (Repeat >= MaxAttempts || + (Repeat > 1 && (RepeatChanged || !AnyProfitableGraph))) + break; + constexpr unsigned StoresLimit = 64; + const unsigned MaxTotalNum = bit_floor(std::min( + Operands.size(), + static_cast( + End - + std::distance( + RangeSizes.begin(), + find_if(RangeSizes, std::bind(IsNotVectorized, true, + std::placeholders::_1))) + + 1))); + unsigned VF = PowerOf2Ceil(CandidateVFs.front()) * 2; + if (VF > MaxTotalNum || VF >= StoresLimit) + break; + for_each(RangeSizes, [&](std::pair &P) { + if (P.first != 0) + P.first = std::max(P.second, P.first); + }); + // Last attempt to vectorize max number of elements, if all previous + // attempts were unsuccessful because of the cost issues. + CandidateVFs.clear(); + CandidateVFs.push_back(VF); } } }; @@ -18191,6 +18426,7 @@ bool SLPVectorizerPass::vectorizeStoreChains(BoUpSLP &R) { }; // Attempt to sort and vectorize each of the store-groups. + DenseSet> Attempted; for (auto &Pair : Stores) { if (Pair.second.size() < 2) continue; @@ -18208,8 +18444,8 @@ bool SLPVectorizerPass::vectorizeStoreChains(BoUpSLP &R) { Pair.second.rend()); Changed |= tryToVectorizeSequence( ReversedStores, StoreSorter, AreCompatibleStores, - [this, &R](ArrayRef Candidates, bool) { - return vectorizeStores(Candidates, R); + [&](ArrayRef Candidates, bool) { + return vectorizeStores(Candidates, R, Attempted); }, /*MaxVFOnly=*/false, R); } diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll index 47d918eabdfe..9bbd314a27cb 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/vec3-reorder-reshuffle.ll @@ -537,24 +537,18 @@ entry: } define void @vec3_extract(<3 x i16> %pixel.sroa.0.4.vec.insert606, ptr %call3.i536) { -; NON-POW2-LABEL: define void @vec3_extract( -; NON-POW2-SAME: <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606:%.*]], ptr [[CALL3_I536:%.*]]) { -; NON-POW2-NEXT: entry: -; NON-POW2-NEXT: store <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606]], ptr [[CALL3_I536]], align 2 -; NON-POW2-NEXT: ret void -; -; POW2-ONLY-LABEL: define void @vec3_extract( -; POW2-ONLY-SAME: <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606:%.*]], ptr [[CALL3_I536:%.*]]) { -; POW2-ONLY-NEXT: entry: -; POW2-ONLY-NEXT: [[PIXEL_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606]], i64 2 -; POW2-ONLY-NEXT: [[RED668:%.*]] = getelementptr i16, ptr [[CALL3_I536]], i64 2 -; POW2-ONLY-NEXT: store i16 [[PIXEL_SROA_0_4_VEC_EXTRACT]], ptr [[RED668]], align 2 -; POW2-ONLY-NEXT: [[PIXEL_SROA_0_2_VEC_EXTRACT:%.*]] = extractelement <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606]], i64 1 -; POW2-ONLY-NEXT: [[GREEN670:%.*]] = getelementptr i16, ptr [[CALL3_I536]], i64 1 -; POW2-ONLY-NEXT: store i16 [[PIXEL_SROA_0_2_VEC_EXTRACT]], ptr [[GREEN670]], align 2 -; POW2-ONLY-NEXT: [[PIXEL_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606]], i64 0 -; POW2-ONLY-NEXT: store i16 [[PIXEL_SROA_0_0_VEC_EXTRACT]], ptr [[CALL3_I536]], align 2 -; POW2-ONLY-NEXT: ret void +; CHECK-LABEL: define void @vec3_extract( +; CHECK-SAME: <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606:%.*]], ptr [[CALL3_I536:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[PIXEL_SROA_0_4_VEC_EXTRACT:%.*]] = extractelement <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606]], i64 2 +; CHECK-NEXT: [[RED668:%.*]] = getelementptr i16, ptr [[CALL3_I536]], i64 2 +; CHECK-NEXT: store i16 [[PIXEL_SROA_0_4_VEC_EXTRACT]], ptr [[RED668]], align 2 +; CHECK-NEXT: [[PIXEL_SROA_0_2_VEC_EXTRACT:%.*]] = extractelement <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606]], i64 1 +; CHECK-NEXT: [[GREEN670:%.*]] = getelementptr i16, ptr [[CALL3_I536]], i64 1 +; CHECK-NEXT: store i16 [[PIXEL_SROA_0_2_VEC_EXTRACT]], ptr [[GREEN670]], align 2 +; CHECK-NEXT: [[PIXEL_SROA_0_0_VEC_EXTRACT:%.*]] = extractelement <3 x i16> [[PIXEL_SROA_0_4_VEC_INSERT606]], i64 0 +; CHECK-NEXT: store i16 [[PIXEL_SROA_0_0_VEC_EXTRACT]], ptr [[CALL3_I536]], align 2 +; CHECK-NEXT: ret void ; entry: %pixel.sroa.0.4.vec.extract = extractelement <3 x i16> %pixel.sroa.0.4.vec.insert606, i64 2 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll b/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll index 75505f632a43..29021150ccd2 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/pr46983.ll @@ -1,9 +1,9 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py -; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 | FileCheck %s --check-prefixes=CHECK,SSE -; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.2 | FileCheck %s --check-prefixes=CHECK,SSE -; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s --check-prefixes=CHECK,AVX -; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s --check-prefixes=CHECK,AVX -; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,AVX +; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+sse2 -slp-threshold=-1 | FileCheck %s +; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+sse4.2 | FileCheck %s +; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx | FileCheck %s +; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx2 | FileCheck %s +; RUN: opt < %s -passes=slp-vectorizer,instcombine -S -mtriple=x86_64-unknown-linux-gnu -mattr=+avx512bw,+avx512vl | FileCheck %s define void @store_i32(ptr nocapture %0, i32 %1, i32 %2) { ; CHECK-LABEL: @store_i32( @@ -98,58 +98,19 @@ define void @store_i8(ptr nocapture %0, i32 %1, i32 %2) { } define void @store_i64(ptr nocapture %0, i32 %1, i32 %2) { -; SSE-LABEL: @store_i64( -; SSE-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1:%.*]] to i64 -; SSE-NEXT: [[TMP5:%.*]] = load i64, ptr [[TMP0:%.*]], align 8, !tbaa [[TBAA5:![0-9]+]] -; SSE-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], [[TMP4]] -; SSE-NEXT: [[TMP7:%.*]] = lshr i64 [[TMP6]], 15 -; SSE-NEXT: [[TMP8:%.*]] = trunc i64 [[TMP7]] to i32 -; SSE-NEXT: [[TMP9:%.*]] = icmp ult i32 [[TMP8]], 255 -; SSE-NEXT: [[TMP10:%.*]] = and i64 [[TMP7]], 4294967295 -; SSE-NEXT: [[TMP11:%.*]] = select i1 [[TMP9]], i64 [[TMP10]], i64 255 -; SSE-NEXT: store i64 [[TMP11]], ptr [[TMP0]], align 8, !tbaa [[TBAA5]] -; SSE-NEXT: [[TMP12:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 8 -; SSE-NEXT: [[TMP13:%.*]] = load i64, ptr [[TMP12]], align 8, !tbaa [[TBAA5]] -; SSE-NEXT: [[TMP14:%.*]] = mul i64 [[TMP13]], [[TMP4]] -; SSE-NEXT: [[TMP15:%.*]] = lshr i64 [[TMP14]], 15 -; SSE-NEXT: [[TMP16:%.*]] = trunc i64 [[TMP15]] to i32 -; SSE-NEXT: [[TMP17:%.*]] = icmp ult i32 [[TMP16]], 255 -; SSE-NEXT: [[TMP18:%.*]] = and i64 [[TMP15]], 4294967295 -; SSE-NEXT: [[TMP19:%.*]] = select i1 [[TMP17]], i64 [[TMP18]], i64 255 -; SSE-NEXT: store i64 [[TMP19]], ptr [[TMP12]], align 8, !tbaa [[TBAA5]] -; SSE-NEXT: [[TMP20:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 16 -; SSE-NEXT: [[TMP21:%.*]] = load i64, ptr [[TMP20]], align 8, !tbaa [[TBAA5]] -; SSE-NEXT: [[TMP22:%.*]] = mul i64 [[TMP21]], [[TMP4]] -; SSE-NEXT: [[TMP23:%.*]] = lshr i64 [[TMP22]], 15 -; SSE-NEXT: [[TMP24:%.*]] = trunc i64 [[TMP23]] to i32 -; SSE-NEXT: [[TMP25:%.*]] = icmp ult i32 [[TMP24]], 255 -; SSE-NEXT: [[TMP26:%.*]] = and i64 [[TMP23]], 4294967295 -; SSE-NEXT: [[TMP27:%.*]] = select i1 [[TMP25]], i64 [[TMP26]], i64 255 -; SSE-NEXT: store i64 [[TMP27]], ptr [[TMP20]], align 8, !tbaa [[TBAA5]] -; SSE-NEXT: [[TMP28:%.*]] = getelementptr inbounds i8, ptr [[TMP0]], i64 24 -; SSE-NEXT: [[TMP29:%.*]] = load i64, ptr [[TMP28]], align 8, !tbaa [[TBAA5]] -; SSE-NEXT: [[TMP30:%.*]] = mul i64 [[TMP29]], [[TMP4]] -; SSE-NEXT: [[TMP31:%.*]] = lshr i64 [[TMP30]], 15 -; SSE-NEXT: [[TMP32:%.*]] = trunc i64 [[TMP31]] to i32 -; SSE-NEXT: [[TMP33:%.*]] = icmp ult i32 [[TMP32]], 255 -; SSE-NEXT: [[TMP34:%.*]] = and i64 [[TMP31]], 4294967295 -; SSE-NEXT: [[TMP35:%.*]] = select i1 [[TMP33]], i64 [[TMP34]], i64 255 -; SSE-NEXT: store i64 [[TMP35]], ptr [[TMP28]], align 8, !tbaa [[TBAA5]] -; SSE-NEXT: ret void -; -; AVX-LABEL: @store_i64( -; AVX-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1:%.*]] to i64 -; AVX-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr [[TMP0:%.*]], align 8, !tbaa [[TBAA5:![0-9]+]] -; AVX-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i64 0 -; AVX-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> zeroinitializer -; AVX-NEXT: [[TMP8:%.*]] = mul <4 x i64> [[TMP5]], [[TMP7]] -; AVX-NEXT: [[TMP9:%.*]] = lshr <4 x i64> [[TMP8]], -; AVX-NEXT: [[TMP10:%.*]] = trunc <4 x i64> [[TMP9]] to <4 x i32> -; AVX-NEXT: [[TMP11:%.*]] = icmp ult <4 x i32> [[TMP10]], -; AVX-NEXT: [[TMP12:%.*]] = and <4 x i64> [[TMP9]], -; AVX-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x i64> [[TMP12]], <4 x i64> -; AVX-NEXT: store <4 x i64> [[TMP13]], ptr [[TMP0]], align 8, !tbaa [[TBAA5]] -; AVX-NEXT: ret void +; CHECK-LABEL: @store_i64( +; CHECK-NEXT: [[TMP4:%.*]] = zext i32 [[TMP1:%.*]] to i64 +; CHECK-NEXT: [[TMP5:%.*]] = load <4 x i64>, ptr [[TMP0:%.*]], align 8, !tbaa [[TBAA5:![0-9]+]] +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i64> poison, i64 [[TMP4]], i64 0 +; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i64> [[TMP6]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP8:%.*]] = mul <4 x i64> [[TMP5]], [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = lshr <4 x i64> [[TMP8]], +; CHECK-NEXT: [[TMP10:%.*]] = trunc <4 x i64> [[TMP9]] to <4 x i32> +; CHECK-NEXT: [[TMP11:%.*]] = icmp ult <4 x i32> [[TMP10]], +; CHECK-NEXT: [[TMP12:%.*]] = and <4 x i64> [[TMP9]], +; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x i64> [[TMP12]], <4 x i64> +; CHECK-NEXT: store <4 x i64> [[TMP13]], ptr [[TMP0]], align 8, !tbaa [[TBAA5]] +; CHECK-NEXT: ret void ; %4 = zext i32 %1 to i64 %5 = load i64, ptr %0, align 8, !tbaa !7 -- GitLab From 450ac01bb9f4ee4f9e05eb6846f256bf2079a436 Mon Sep 17 00:00:00 2001 From: Diego Caballero Date: Fri, 26 Apr 2024 16:20:24 +0200 Subject: [PATCH 063/301] [mlir][MemRef] Add ExtractStridedMetadataOpCollapseShapeFolder (#89954) This PR adds a new pattern to the set of patterns used to resolve the offset, sizes and stride of a memref. Similar to `ExtractStridedMetadataOpSubviewFolder`, the new pattern resolves strided_metadata(collapse_shape) directly, without introduce a reshape_cast op. --- .../Transforms/ExpandStridedMetadata.cpp | 201 +++++++++++++----- .../MemRef/expand-strided-metadata.mlir | 24 ++- 2 files changed, 165 insertions(+), 60 deletions(-) diff --git a/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp b/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp index 96eb7cfd2db6..585c5b738142 100644 --- a/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp +++ b/mlir/lib/Dialect/MemRef/Transforms/ExpandStridedMetadata.cpp @@ -550,6 +550,89 @@ getCollapsedStride(memref::CollapseShapeOp collapseShape, OpBuilder &builder, return {makeComposedFoldedAffineMin(builder, collapseShape.getLoc(), minMap, groupStrides)}; } + +/// From `reshape_like(memref, subSizes, subStrides))` compute +/// +/// \verbatim +/// baseBuffer, baseOffset, baseSizes, baseStrides = +/// extract_strided_metadata(memref) +/// strides#i = baseStrides#i * subStrides#i +/// sizes = subSizes +/// \endverbatim +/// +/// and return {baseBuffer, baseOffset, sizes, strides} +template +static FailureOr resolveReshapeStridedMetadata( + RewriterBase &rewriter, ReassociativeReshapeLikeOp reshape, + function_ref( + ReassociativeReshapeLikeOp, OpBuilder &, + ArrayRef /*origSizes*/, unsigned /*groupId*/)> + getReshapedSizes, + function_ref( + ReassociativeReshapeLikeOp, OpBuilder &, + ArrayRef /*origSizes*/, + ArrayRef /*origStrides*/, unsigned /*groupId*/)> + getReshapedStrides) { + // Build a plain extract_strided_metadata(memref) from + // extract_strided_metadata(reassociative_reshape_like(memref)). + Location origLoc = reshape.getLoc(); + Value source = reshape.getSrc(); + auto sourceType = cast(source.getType()); + unsigned sourceRank = sourceType.getRank(); + + auto newExtractStridedMetadata = + rewriter.create(origLoc, source); + + // Collect statically known information. + auto [strides, offset] = getStridesAndOffset(sourceType); + MemRefType reshapeType = reshape.getResultType(); + unsigned reshapeRank = reshapeType.getRank(); + + OpFoldResult offsetOfr = + ShapedType::isDynamic(offset) + ? getAsOpFoldResult(newExtractStridedMetadata.getOffset()) + : rewriter.getIndexAttr(offset); + + // Get the special case of 0-D out of the way. + if (sourceRank == 0) { + SmallVector ones(reshapeRank, rewriter.getIndexAttr(1)); + return StridedMetadata{newExtractStridedMetadata.getBaseBuffer(), offsetOfr, + /*sizes=*/ones, /*strides=*/ones}; + } + + SmallVector finalSizes; + finalSizes.reserve(reshapeRank); + SmallVector finalStrides; + finalStrides.reserve(reshapeRank); + + // Compute the reshaped strides and sizes from the base strides and sizes. + SmallVector origSizes = + getAsOpFoldResult(newExtractStridedMetadata.getSizes()); + SmallVector origStrides = + getAsOpFoldResult(newExtractStridedMetadata.getStrides()); + unsigned idx = 0, endIdx = reshape.getReassociationIndices().size(); + for (; idx != endIdx; ++idx) { + SmallVector reshapedSizes = + getReshapedSizes(reshape, rewriter, origSizes, /*groupId=*/idx); + SmallVector reshapedStrides = getReshapedStrides( + reshape, rewriter, origSizes, origStrides, /*groupId=*/idx); + + unsigned groupSize = reshapedSizes.size(); + for (unsigned i = 0; i < groupSize; ++i) { + finalSizes.push_back(reshapedSizes[i]); + finalStrides.push_back(reshapedStrides[i]); + } + } + assert(((isa(reshape) && idx == sourceRank) || + (isa(reshape) && idx == reshapeRank)) && + "We should have visited all the input dimensions"); + assert(finalSizes.size() == reshapeRank && + "We should have populated all the values"); + + return StridedMetadata{newExtractStridedMetadata.getBaseBuffer(), offsetOfr, + finalSizes, finalStrides}; +} + /// Replace `baseBuffer, offset, sizes, strides = /// extract_strided_metadata(reshapeLike(memref))` /// With @@ -580,68 +663,65 @@ public: LogicalResult matchAndRewrite(ReassociativeReshapeLikeOp reshape, PatternRewriter &rewriter) const override { - // Build a plain extract_strided_metadata(memref) from - // extract_strided_metadata(reassociative_reshape_like(memref)). - Location origLoc = reshape.getLoc(); - Value source = reshape.getSrc(); - auto sourceType = cast(source.getType()); - unsigned sourceRank = sourceType.getRank(); - - auto newExtractStridedMetadata = - rewriter.create(origLoc, source); - - // Collect statically known information. - auto [strides, offset] = getStridesAndOffset(sourceType); - MemRefType reshapeType = reshape.getResultType(); - unsigned reshapeRank = reshapeType.getRank(); - - OpFoldResult offsetOfr = - ShapedType::isDynamic(offset) - ? getAsOpFoldResult(newExtractStridedMetadata.getOffset()) - : rewriter.getIndexAttr(offset); - - // Get the special case of 0-D out of the way. - if (sourceRank == 0) { - SmallVector ones(reshapeRank, rewriter.getIndexAttr(1)); - auto memrefDesc = rewriter.create( - origLoc, reshapeType, newExtractStridedMetadata.getBaseBuffer(), - offsetOfr, /*sizes=*/ones, /*strides=*/ones); - rewriter.replaceOp(reshape, memrefDesc.getResult()); - return success(); + FailureOr stridedMetadata = + resolveReshapeStridedMetadata( + rewriter, reshape, getReshapedSizes, getReshapedStrides); + if (failed(stridedMetadata)) { + return rewriter.notifyMatchFailure(reshape, + "failed to resolve reshape metadata"); } - SmallVector finalSizes; - finalSizes.reserve(reshapeRank); - SmallVector finalStrides; - finalStrides.reserve(reshapeRank); - - // Compute the reshaped strides and sizes from the base strides and sizes. - SmallVector origSizes = - getAsOpFoldResult(newExtractStridedMetadata.getSizes()); - SmallVector origStrides = - getAsOpFoldResult(newExtractStridedMetadata.getStrides()); - unsigned idx = 0, endIdx = reshape.getReassociationIndices().size(); - for (; idx != endIdx; ++idx) { - SmallVector reshapedSizes = - getReshapedSizes(reshape, rewriter, origSizes, /*groupId=*/idx); - SmallVector reshapedStrides = getReshapedStrides( - reshape, rewriter, origSizes, origStrides, /*groupId=*/idx); - - unsigned groupSize = reshapedSizes.size(); - for (unsigned i = 0; i < groupSize; ++i) { - finalSizes.push_back(reshapedSizes[i]); - finalStrides.push_back(reshapedStrides[i]); - } + rewriter.replaceOpWithNewOp( + reshape, reshape.getType(), stridedMetadata->basePtr, + stridedMetadata->offset, stridedMetadata->sizes, + stridedMetadata->strides); + return success(); + } +}; + +/// Pattern to replace `extract_strided_metadata(collapse_shape)` +/// With +/// +/// \verbatim +/// baseBuffer, baseOffset, baseSizes, baseStrides = +/// extract_strided_metadata(memref) +/// strides#i = baseStrides#i * subSizes#i +/// offset = baseOffset + sum(subOffset#i * baseStrides#i) +/// sizes = subSizes +/// \verbatim +/// +/// with `baseBuffer`, `offset`, `sizes` and `strides` being +/// the replacements for the original `extract_strided_metadata`. +struct ExtractStridedMetadataOpCollapseShapeFolder + : OpRewritePattern { + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(memref::ExtractStridedMetadataOp op, + PatternRewriter &rewriter) const override { + auto collapseShapeOp = + op.getSource().getDefiningOp(); + if (!collapseShapeOp) + return failure(); + + FailureOr stridedMetadata = + resolveReshapeStridedMetadata( + rewriter, collapseShapeOp, getCollapsedSize, getCollapsedStride); + if (failed(stridedMetadata)) { + return rewriter.notifyMatchFailure( + op, + "failed to resolve metadata in terms of source collapse_shape op"); } - assert(((isa(reshape) && idx == sourceRank) || - (isa(reshape) && idx == reshapeRank)) && - "We should have visited all the input dimensions"); - assert(finalSizes.size() == reshapeRank && - "We should have populated all the values"); - auto memrefDesc = rewriter.create( - origLoc, reshapeType, newExtractStridedMetadata.getBaseBuffer(), - offsetOfr, finalSizes, finalStrides); - rewriter.replaceOp(reshape, memrefDesc.getResult()); + + Location loc = collapseShapeOp.getLoc(); + SmallVector results; + results.push_back(stridedMetadata->basePtr); + results.push_back(getValueOrCreateConstantIndexOp(rewriter, loc, + stridedMetadata->offset)); + results.append( + getValueOrCreateConstantIndexOp(rewriter, loc, stridedMetadata->sizes)); + results.append(getValueOrCreateConstantIndexOp(rewriter, loc, + stridedMetadata->strides)); + rewriter.replaceOp(op, results); return success(); } }; @@ -1018,9 +1098,11 @@ void memref::populateExpandStridedMetadataPatterns( getCollapsedStride>, ExtractStridedMetadataOpAllocFolder, ExtractStridedMetadataOpAllocFolder, + ExtractStridedMetadataOpCollapseShapeFolder, ExtractStridedMetadataOpGetGlobalFolder, RewriteExtractAlignedPointerAsIndexOfViewLikeOp, ExtractStridedMetadataOpReinterpretCastFolder, + ExtractStridedMetadataOpSubviewFolder, ExtractStridedMetadataOpCastFolder, ExtractStridedMetadataOpExtractStridedMetadataFolder>( patterns.getContext()); @@ -1030,6 +1112,7 @@ void memref::populateResolveExtractStridedMetadataPatterns( RewritePatternSet &patterns) { patterns.add, ExtractStridedMetadataOpAllocFolder, + ExtractStridedMetadataOpCollapseShapeFolder, ExtractStridedMetadataOpGetGlobalFolder, ExtractStridedMetadataOpSubviewFolder, RewriteExtractAlignedPointerAsIndexOfViewLikeOp, diff --git a/mlir/test/Dialect/MemRef/expand-strided-metadata.mlir b/mlir/test/Dialect/MemRef/expand-strided-metadata.mlir index 28b700430059..0705b30ca45d 100644 --- a/mlir/test/Dialect/MemRef/expand-strided-metadata.mlir +++ b/mlir/test/Dialect/MemRef/expand-strided-metadata.mlir @@ -1513,4 +1513,26 @@ func.func @zero_sized_memred(%arg0: f32) -> (memref, index,index,index) %sizes, %strides : memref, index, index, index -} \ No newline at end of file +} + +// ----- + +func.func @extract_strided_metadata_of_collapse_shape(%base: memref<5x4xf32>) + -> (memref, index, index, index) { + + %collapse = memref.collapse_shape %base[[0, 1]] : + memref<5x4xf32> into memref<20xf32> + + %base_buffer, %offset, %size, %stride = memref.extract_strided_metadata %collapse : + memref<20xf32> -> memref, index, index, index + + return %base_buffer, %offset, %size, %stride : + memref, index, index, index +} + +// CHECK-LABEL: func @extract_strided_metadata_of_collapse_shape +// CHECK-DAG: %[[OFFSET:.*]] = arith.constant 0 : index +// CHECK-DAG: %[[SIZE:.*]] = arith.constant 20 : index +// CHECK-DAG: %[[STEP:.*]] = arith.constant 1 : index +// CHECK: %[[BASE:.*]], %{{.*}}, %{{.*}}, %{{.*}} = memref.extract_strided_metadata +// CHECK: return %[[BASE]], %[[OFFSET]], %[[SIZE]], %[[STEP]] : memref, index, index, index -- GitLab From 950b7ce0b88318f9099e9a7c9817d224ebdc6337 Mon Sep 17 00:00:00 2001 From: Christian Sigg Date: Fri, 26 Apr 2024 16:28:30 +0200 Subject: [PATCH 064/301] [mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. (#89998) See https://mlir.llvm.org/deprecation and https://discourse.llvm.org/t/preferred-casting-style-going-forward. --- flang/include/flang/Lower/Mangler.h | 2 +- .../flang/Optimizer/Analysis/TBAAForest.h | 2 +- .../flang/Optimizer/Builder/BoxValue.h | 20 +- .../include/flang/Optimizer/Builder/Factory.h | 12 +- .../flang/Optimizer/Builder/HLFIRTools.h | 14 +- .../flang/Optimizer/Builder/IntrinsicCall.h | 4 +- .../Optimizer/Builder/PPCIntrinsicCall.h | 6 +- .../Dialect/CanonicalizationPatterns.td | 23 +- .../include/flang/Optimizer/Dialect/FIROps.td | 12 +- .../include/flang/Optimizer/Dialect/FIRType.h | 74 ++--- .../flang/Optimizer/Dialect/FIRTypes.td | 2 +- .../Dialect/FortranVariableInterface.td | 10 +- .../flang/Optimizer/HLFIR/HLFIRDialect.h | 20 +- flang/include/flang/Optimizer/Support/Utils.h | 4 +- flang/include/flang/Tools/PointerModels.h | 4 +- flang/lib/Lower/Allocatable.cpp | 12 +- flang/lib/Lower/Bridge.cpp | 39 +-- flang/lib/Lower/CallInterface.cpp | 6 +- flang/lib/Lower/ConvertArrayConstructor.cpp | 11 +- flang/lib/Lower/ConvertCall.cpp | 56 ++-- flang/lib/Lower/ConvertConstant.cpp | 23 +- flang/lib/Lower/ConvertExpr.cpp | 188 +++++------ flang/lib/Lower/ConvertExprToHLFIR.cpp | 28 +- .../lib/Lower/ConvertProcedureDesignator.cpp | 6 +- flang/lib/Lower/ConvertVariable.cpp | 22 +- flang/lib/Lower/CustomIntrinsicCall.cpp | 35 +- flang/lib/Lower/DirectivesCommon.h | 24 +- flang/lib/Lower/HlfirIntrinsics.cpp | 4 +- flang/lib/Lower/HostAssociations.cpp | 14 +- flang/lib/Lower/IO.cpp | 55 ++-- flang/lib/Lower/OpenACC.cpp | 4 +- flang/lib/Lower/OpenMP/ClauseProcessor.cpp | 8 +- flang/lib/Lower/OpenMP/OpenMP.cpp | 12 +- flang/lib/Lower/OpenMP/ReductionProcessor.cpp | 18 +- flang/lib/Lower/VectorSubscripts.cpp | 2 +- .../lib/Optimizer/Analysis/AliasAnalysis.cpp | 4 +- flang/lib/Optimizer/Builder/BoxValue.cpp | 4 +- flang/lib/Optimizer/Builder/Character.cpp | 41 +-- flang/lib/Optimizer/Builder/Complex.cpp | 3 +- flang/lib/Optimizer/Builder/FIRBuilder.cpp | 107 ++++--- flang/lib/Optimizer/Builder/HLFIRTools.cpp | 78 +++-- flang/lib/Optimizer/Builder/IntrinsicCall.cpp | 107 ++++--- flang/lib/Optimizer/Builder/MutableBox.cpp | 35 +- .../Optimizer/Builder/PPCIntrinsicCall.cpp | 44 ++- .../Optimizer/Builder/Runtime/Allocatable.cpp | 2 +- .../Optimizer/Builder/Runtime/Character.cpp | 8 +- .../Optimizer/Builder/Runtime/Intrinsics.cpp | 6 +- .../lib/Optimizer/Builder/Runtime/Ragged.cpp | 3 +- .../Optimizer/Builder/Runtime/Reduction.cpp | 20 +- .../lib/Optimizer/CodeGen/BoxedProcedure.cpp | 16 +- flang/lib/Optimizer/CodeGen/CGOps.cpp | 14 +- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 203 ++++++------ flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp | 18 +- flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp | 13 +- flang/lib/Optimizer/CodeGen/TBAABuilder.cpp | 2 +- flang/lib/Optimizer/CodeGen/Target.cpp | 4 +- flang/lib/Optimizer/CodeGen/TargetRewrite.cpp | 21 +- flang/lib/Optimizer/CodeGen/TypeConverter.cpp | 18 +- flang/lib/Optimizer/Dialect/FIRAttr.cpp | 14 +- flang/lib/Optimizer/Dialect/FIROps.cpp | 302 +++++++++--------- flang/lib/Optimizer/Dialect/FIRType.cpp | 121 +++---- .../Dialect/FortranVariableInterface.cpp | 11 +- flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp | 30 +- flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp | 192 ++++++----- .../HLFIR/Transforms/BufferizeHLFIR.cpp | 29 +- .../HLFIR/Transforms/ConvertToFIR.cpp | 47 +-- .../HLFIR/Transforms/LowerHLFIRIntrinsics.cpp | 2 +- .../LowerHLFIROrderedAssignments.cpp | 2 +- .../Transforms/OptimizedBufferization.cpp | 12 +- .../Transforms/SimplifyHLFIRIntrinsics.cpp | 3 +- .../Optimizer/Transforms/AbstractResult.cpp | 16 +- .../lib/Optimizer/Transforms/AddDebugInfo.cpp | 6 +- .../Optimizer/Transforms/AffineDemotion.cpp | 9 +- .../Optimizer/Transforms/AffinePromotion.cpp | 11 +- .../Optimizer/Transforms/ArrayValueCopy.cpp | 30 +- .../Transforms/CharacterConversion.cpp | 4 +- .../Optimizer/Transforms/LoopVersioning.cpp | 2 +- .../Optimizer/Transforms/MemoryAllocation.cpp | 2 +- .../Transforms/PolymorphicOpConversion.cpp | 38 +-- .../Transforms/SimplifyIntrinsics.cpp | 52 +-- .../lib/Optimizer/Transforms/StackArrays.cpp | 2 +- .../Optimizer/Builder/ComplexTest.cpp | 2 +- .../Optimizer/Builder/DoLoopHelperTest.cpp | 2 +- .../Optimizer/Builder/FIRBuilderTest.cpp | 48 +-- flang/unittests/Optimizer/RTBuilder.cpp | 2 +- llvm/include/llvm/ADT/TypeSwitch.h | 3 + .../mlir/Dialect/Linalg/IR/LinalgOps.td | 4 +- .../Dialect/OpenMP/OpenMPOpsInterfaces.td | 8 +- .../include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 10 +- mlir/include/mlir/IR/Attributes.h | 5 + .../mlir/IR/BuiltinLocationAttributes.td | 13 +- mlir/include/mlir/IR/Location.h | 3 + mlir/include/mlir/IR/Types.h | 5 + mlir/include/mlir/IR/Value.h | 8 +- .../ComplexToStandard/ComplexToStandard.cpp | 2 +- .../Polynomial/IR/PolynomialAttributes.cpp | 2 +- .../Vector/Transforms/VectorLinearize.cpp | 16 +- 97 files changed, 1342 insertions(+), 1275 deletions(-) diff --git a/flang/include/flang/Lower/Mangler.h b/flang/include/flang/Lower/Mangler.h index 41939abe29e5..99da96b0d6ba 100644 --- a/flang/include/flang/Lower/Mangler.h +++ b/flang/include/flang/Lower/Mangler.h @@ -90,7 +90,7 @@ inline std::string mangleArrayLiteral( return mangleArrayLiteral(x.values().size() * sizeof(x.values()[0]), x.shape(), Fortran::common::TypeCategory::Derived, /*kind=*/0, /*charLen=*/-1, - eleTy.cast().getName()); + mlir::cast(eleTy).getName()); } /// Return the compiler-generated name of a static namelist variable descriptor. diff --git a/flang/include/flang/Optimizer/Analysis/TBAAForest.h b/flang/include/flang/Optimizer/Analysis/TBAAForest.h index b69e50bbe05c..619ed4939c51 100644 --- a/flang/include/flang/Optimizer/Analysis/TBAAForest.h +++ b/flang/include/flang/Optimizer/Analysis/TBAAForest.h @@ -88,7 +88,7 @@ public: // name must be used so that we add to the tbaa tree added in the FIR pass mlir::Attribute attr = func->getAttr(getInternalFuncNameAttrName()); if (attr) { - return getFuncTree(attr.cast()); + return getFuncTree(mlir::cast(attr)); } return getFuncTree(func.getSymNameAttr()); } diff --git a/flang/include/flang/Optimizer/Builder/BoxValue.h b/flang/include/flang/Optimizer/Builder/BoxValue.h index 2fed2d48a7a0..5c7e89dbc08f 100644 --- a/flang/include/flang/Optimizer/Builder/BoxValue.h +++ b/flang/include/flang/Optimizer/Builder/BoxValue.h @@ -78,7 +78,7 @@ class CharBoxValue : public AbstractBox { public: CharBoxValue(mlir::Value addr, mlir::Value len) : AbstractBox{addr}, len{len} { - if (addr && addr.getType().template isa()) + if (addr && mlir::isa(addr.getType())) fir::emitFatalError(addr.getLoc(), "BoxChar should not be in CharBoxValue"); } @@ -221,7 +221,7 @@ public: auto type = getAddr().getType(); if (auto pointedTy = fir::dyn_cast_ptrEleTy(type)) type = pointedTy; - return type.cast(); + return mlir::cast(type); } /// Return the part of the address type after memory and box types. That is /// the element type, maybe wrapped in a fir.array type. @@ -243,22 +243,22 @@ public: /// Get the scalar type related to the described entity mlir::Type getEleTy() const { auto type = getBaseTy(); - if (auto seqTy = type.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(type)) return seqTy.getEleTy(); return type; } /// Is the entity an array or an assumed rank ? - bool hasRank() const { return getBaseTy().isa(); } + bool hasRank() const { return mlir::isa(getBaseTy()); } /// Is this an assumed rank ? bool hasAssumedRank() const { - auto seqTy = getBaseTy().dyn_cast(); + auto seqTy = mlir::dyn_cast(getBaseTy()); return seqTy && seqTy.hasUnknownShape(); } /// Returns the rank of the entity. Beware that zero will be returned for /// both scalars and assumed rank. unsigned rank() const { - if (auto seqTy = getBaseTy().dyn_cast()) + if (auto seqTy = mlir::dyn_cast(getBaseTy())) return seqTy.getDimension(); return 0; } @@ -267,7 +267,7 @@ public: bool isCharacter() const { return fir::isa_char(getEleTy()); } /// Is this a derived type entity ? - bool isDerived() const { return getEleTy().isa(); } + bool isDerived() const { return mlir::isa(getEleTy()); } bool isDerivedWithLenParameters() const { return fir::isRecordWithTypeParameters(getEleTy()); @@ -377,11 +377,11 @@ public: } /// Is this a Fortran pointer ? bool isPointer() const { - return getBoxTy().getEleTy().isa(); + return mlir::isa(getBoxTy().getEleTy()); } /// Is this an allocatable ? bool isAllocatable() const { - return getBoxTy().getEleTy().isa(); + return mlir::isa(getBoxTy().getEleTy()); } // Replace the fir.ref, keeping any non-deferred parameters. MutableBoxValue clone(mlir::Value newBox) const { @@ -488,7 +488,7 @@ public: if (const auto *b = getUnboxed()) { if (*b) { auto type = b->getType(); - if (type.template isa()) + if (mlir::isa(type)) fir::emitFatalError(b->getLoc(), "BoxChar should be unboxed"); type = fir::unwrapSequenceType(fir::unwrapRefType(type)); if (fir::isa_char(type)) diff --git a/flang/include/flang/Optimizer/Builder/Factory.h b/flang/include/flang/Optimizer/Builder/Factory.h index ec294d26ac96..4e5c52ac44e0 100644 --- a/flang/include/flang/Optimizer/Builder/Factory.h +++ b/flang/include/flang/Optimizer/Builder/Factory.h @@ -43,9 +43,9 @@ template void genCharacterCopy(mlir::Value src, mlir::Value srcLen, mlir::Value dst, mlir::Value dstLen, B &builder, mlir::Location loc) { auto srcTy = - fir::dyn_cast_ptrEleTy(src.getType()).template cast(); + mlir::cast(fir::dyn_cast_ptrEleTy(src.getType())); auto dstTy = - fir::dyn_cast_ptrEleTy(dst.getType()).template cast(); + mlir::cast(fir::dyn_cast_ptrEleTy(dst.getType())); if (!srcLen && !dstLen && srcTy.getFKind() == dstTy.getFKind() && srcTy.getLen() == dstTy.getLen()) { // same size, so just use load and store @@ -61,8 +61,8 @@ void genCharacterCopy(mlir::Value src, mlir::Value srcLen, mlir::Value dst, fir::CharacterType::getSingleton(ty.getContext(), ty.getFKind()))); }; auto toEleTy = [&](fir::ReferenceType ty) { - auto seqTy = ty.getEleTy().cast(); - return seqTy.getEleTy().cast(); + auto seqTy = mlir::cast(ty.getEleTy()); + return mlir::cast(seqTy.getEleTy()); }; auto toCoorTy = [&](fir::ReferenceType ty) { return fir::ReferenceType::get(toEleTy(ty)); @@ -190,8 +190,8 @@ originateIndices(mlir::Location loc, B &builder, mlir::Type memTy, if (origins.empty()) { assert(!shapeVal || mlir::isa(shapeVal.getDefiningOp())); auto ty = fir::dyn_cast_ptrOrBoxEleTy(memTy); - assert(ty && ty.isa()); - auto seqTy = ty.cast(); + assert(ty && mlir::isa(ty)); + auto seqTy = mlir::cast(ty); auto one = builder.template create(loc, 1); const auto dimension = seqTy.getDimension(); if (shapeVal) { diff --git a/flang/include/flang/Optimizer/Builder/HLFIRTools.h b/flang/include/flang/Optimizer/Builder/HLFIRTools.h index 035035601e2f..6c36f7e84db6 100644 --- a/flang/include/flang/Optimizer/Builder/HLFIRTools.h +++ b/flang/include/flang/Optimizer/Builder/HLFIRTools.h @@ -77,12 +77,12 @@ public: /// Return the rank of this entity or -1 if it is an assumed rank. int getRank() const { mlir::Type type = fir::unwrapPassByRefType(fir::unwrapRefType(getType())); - if (auto seqTy = type.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(type)) { if (seqTy.hasUnknownShape()) return -1; return seqTy.getDimension(); } - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.getRank(); return 0; } @@ -99,17 +99,17 @@ public: bool hasLengthParameters() const { mlir::Type eleTy = getFortranElementType(); - return eleTy.isa() || + return mlir::isa(eleTy) || fir::isRecordWithTypeParameters(eleTy); } bool isCharacter() const { - return getFortranElementType().isa(); + return mlir::isa(getFortranElementType()); } bool hasIntrinsicType() const { mlir::Type eleTy = getFortranElementType(); - return fir::isa_trivial(eleTy) || eleTy.isa(); + return fir::isa_trivial(eleTy) || mlir::isa(eleTy); } bool isDerivedWithLengthParameters() const { @@ -124,8 +124,8 @@ public: if (auto varIface = getIfVariableInterface()) { if (auto shape = varIface.getShape()) { auto shapeTy = shape.getType(); - return shapeTy.isa() || - shapeTy.isa(); + return mlir::isa(shapeTy) || + mlir::isa(shapeTy); } return false; } diff --git a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h index 604f2bd969ee..b7d060926761 100644 --- a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h @@ -663,8 +663,8 @@ static inline mlir::FunctionType genFuncType(mlir::MLIRContext *context, //===----------------------------------------------------------------------===// static inline mlir::Type getConvertedElementType(mlir::MLIRContext *context, mlir::Type eleTy) { - if (eleTy.isa() && !eleTy.isSignlessInteger()) { - const auto intTy{eleTy.dyn_cast()}; + if (mlir::isa(eleTy) && !eleTy.isSignlessInteger()) { + const auto intTy{mlir::dyn_cast(eleTy)}; auto newEleTy{mlir::IntegerType::get(context, intTy.getWidth())}; return newEleTy; } diff --git a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h index 1e87bf0f6ad1..a7c4c075d818 100644 --- a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h @@ -180,10 +180,10 @@ struct VecTypeInfo { // Returns a VecTypeInfo with element type and length of given fir vector type. // Preserves signness of fir vector type if element type of integer. static inline VecTypeInfo getVecTypeFromFirType(mlir::Type firTy) { - assert(firTy.isa()); + assert(mlir::isa(firTy)); VecTypeInfo vecTyInfo; - vecTyInfo.eleTy = firTy.dyn_cast().getEleTy(); - vecTyInfo.len = firTy.dyn_cast().getLen(); + vecTyInfo.eleTy = mlir::dyn_cast(firTy).getEleTy(); + vecTyInfo.len = mlir::dyn_cast(firTy).getLen(); return vecTyInfo; } diff --git a/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td b/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td index 544fc3cdf75e..0ef37a37ce94 100644 --- a/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td +++ b/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td @@ -21,17 +21,18 @@ include "flang/Optimizer/Dialect/FIROps.td" def IdenticalTypePred : Constraint>; def IntegerTypePred : Constraint>; -def IndexTypePred : Constraint()">>; +def IndexTypePred : Constraint($0.getType())">>; // Widths are monotonic. // $0.bits >= $1.bits >= $2.bits or $0.bits <= $1.bits <= $2.bits def MonotonicTypePred - : Constraint() && " - " $1.getType().isa() && " - " $2.getType().isa()) || " - " ($0.getType().isa() && " - " $1.getType().isa() && " - " $2.getType().isa())) && " + : Constraint($0.getType()) && " + " mlir::isa($1.getType()) && " + " mlir::isa($2.getType())) || " + " (mlir::isa($0.getType()) && " + " mlir::isa($1.getType()) && " + " mlir::isa($2.getType()))) && " "(($0.getType().getIntOrFloatBitWidth() <= " " $1.getType().getIntOrFloatBitWidth() && " " $1.getType().getIntOrFloatBitWidth() <= " @@ -42,8 +43,8 @@ def MonotonicTypePred " $2.getType().getIntOrFloatBitWidth()))">>; def IntPred : Constraint() && " - "$1.getType().isa()">>; + "mlir::isa($0.getType()) && " + "mlir::isa($1.getType())">>; // If both are int type and the first is smaller than the second. // $0.bits <= $1.bits @@ -101,8 +102,8 @@ def CombineConvertTruncOptPattern def createConstantOp : NativeCodeCall<"$_builder.create" "($_loc, $_builder.getIndexType(), " - "rewriter.getIndexAttr($1.dyn_cast()" - ".getInt()))">; + "rewriter.getIndexAttr(" + "mlir::dyn_cast($1).getInt()))">; def ForwardConstantConvertPattern : Pat<(fir_ConvertOp:$res (Arith_ConstantOp:$cnt $attr)), diff --git a/flang/include/flang/Optimizer/Dialect/FIROps.td b/flang/include/flang/Optimizer/Dialect/FIROps.td index 92790a691e47..496193e25cab 100644 --- a/flang/include/flang/Optimizer/Dialect/FIROps.td +++ b/flang/include/flang/Optimizer/Dialect/FIROps.td @@ -2708,14 +2708,14 @@ def fir_ConvertOp : fir_OneResultOp<"convert", [NoMemoryEffect]> { let hasCanonicalizer = 1; } -def FortranTypeAttr : Attr()">, - Or<[CPred<"$_self.cast().getValue().isa()">]>]>, - "Fortran surface type"> { +def FortranTypeAttr : Attr($_self)">, + Or<[CPred<"mlir::isa(mlir::cast($_self).getValue())" + >]>]>, "Fortran surface type"> { let storageType = [{ ::mlir::TypeAttr }]; let returnType = "mlir::Type"; - let convertFromStorage = "$_self.getValue().cast()"; + let convertFromStorage = "mlir::cast($_self.getValue())"; } def fir_TypeDescOp : fir_OneResultOp<"type_desc", [NoMemoryEffect]> { diff --git a/flang/include/flang/Optimizer/Dialect/FIRType.h b/flang/include/flang/Optimizer/Dialect/FIRType.h index 7fcd9c1babf2..b4344435db9f 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRType.h +++ b/flang/include/flang/Optimizer/Dialect/FIRType.h @@ -97,35 +97,36 @@ bool isa_fir_or_std_type(mlir::Type t); /// Is `t` a FIR dialect type that implies a memory (de)reference? inline bool isa_ref_type(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a boxed type? inline bool isa_box_type(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a type that is always trivially pass-by-reference? Specifically, this /// is testing if `t` is a ReferenceType or any box type. Compare this to /// conformsWithPassByRef(), which includes pointers and allocatables. inline bool isa_passbyref_type(mlir::Type t) { - return t.isa() || isa_box_type(t); + return mlir::isa(t) || + isa_box_type(t); } /// Is `t` a type that can conform to be pass-by-reference? Depending on the /// context, these types may simply demote to pass-by-reference or a reference /// to them may have to be passed instead. Functions are always referent. inline bool conformsWithPassByRef(mlir::Type t) { - return isa_ref_type(t) || isa_box_type(t) || t.isa(); + return isa_ref_type(t) || isa_box_type(t) || mlir::isa(t); } /// Is `t` a derived (record) type? -inline bool isa_derived(mlir::Type t) { return t.isa(); } +inline bool isa_derived(mlir::Type t) { return mlir::isa(t); } /// Is `t` type(c_ptr) or type(c_funptr)? inline bool isa_builtin_cptr_type(mlir::Type t) { - if (auto recTy = t.dyn_cast_or_null()) + if (auto recTy = mlir::dyn_cast_or_null(t)) return recTy.getName().ends_with("T__builtin_c_ptr") || recTy.getName().ends_with("T__builtin_c_funptr"); return false; @@ -133,7 +134,7 @@ inline bool isa_builtin_cptr_type(mlir::Type t) { /// Is `t` a FIR dialect aggregate type? inline bool isa_aggregate(mlir::Type t) { - return t.isa() || fir::isa_derived(t); + return mlir::isa(t) || fir::isa_derived(t); } /// Extract the `Type` pointed to from a FIR memory reference type. If `t` is @@ -146,17 +147,17 @@ mlir::Type dyn_cast_ptrOrBoxEleTy(mlir::Type t); /// Is `t` a FIR Real or MLIR Float type? inline bool isa_real(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` an integral type? inline bool isa_integer(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a vector type? inline bool isa_vector(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } mlir::Type parseFirType(FIROpsDialect *, mlir::DialectAsmParser &parser); @@ -169,22 +170,22 @@ void verifyIntegralType(mlir::Type type); /// Is `t` a FIR or MLIR Complex type? inline bool isa_complex(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a CHARACTER type? Does not check the length. -inline bool isa_char(mlir::Type t) { return t.isa(); } +inline bool isa_char(mlir::Type t) { return mlir::isa(t); } /// Is `t` a trivial intrinsic type? CHARACTER is excluded because it /// is a dependent type. inline bool isa_trivial(mlir::Type t) { return isa_integer(t) || isa_real(t) || isa_complex(t) || isa_vector(t) || - t.isa(); + mlir::isa(t); } /// Is `t` a CHARACTER type with a LEN other than 1? inline bool isa_char_string(mlir::Type t) { - if (auto ct = t.dyn_cast_or_null()) + if (auto ct = mlir::dyn_cast_or_null(t)) return ct.getLen() != fir::CharacterType::singleton(); return false; } @@ -198,7 +199,7 @@ bool isa_unknown_size_box(mlir::Type t); /// Returns true iff `t` is a fir.char type and has an unknown length. inline bool characterWithDynamicLen(mlir::Type t) { - if (auto charTy = t.dyn_cast()) + if (auto charTy = mlir::dyn_cast(t)) return charTy.hasDynamicLen(); return false; } @@ -213,11 +214,11 @@ inline bool sequenceWithNonConstantShape(fir::SequenceType seqTy) { bool hasDynamicSize(mlir::Type t); inline unsigned getRankOfShapeType(mlir::Type t) { - if (auto shTy = t.dyn_cast()) + if (auto shTy = mlir::dyn_cast(t)) return shTy.getRank(); - if (auto shTy = t.dyn_cast()) + if (auto shTy = mlir::dyn_cast(t)) return shTy.getRank(); - if (auto shTy = t.dyn_cast()) + if (auto shTy = mlir::dyn_cast(t)) return shTy.getRank(); return 0; } @@ -225,14 +226,14 @@ inline unsigned getRankOfShapeType(mlir::Type t) { /// Get the memory reference type of the data pointer from the box type, inline mlir::Type boxMemRefType(fir::BaseBoxType t) { auto eleTy = t.getEleTy(); - if (!eleTy.isa()) + if (!mlir::isa(eleTy)) eleTy = fir::ReferenceType::get(t); return eleTy; } /// If `t` is a SequenceType return its element type, otherwise return `t`. inline mlir::Type unwrapSequenceType(mlir::Type t) { - if (auto seqTy = t.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(t)) return seqTy.getEleTy(); return t; } @@ -278,7 +279,7 @@ inline fir::SequenceType unwrapUntilSeqType(mlir::Type t) { t = ty; continue; } - if (auto seqTy = t.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(t)) return seqTy; return {}; } @@ -287,8 +288,8 @@ inline fir::SequenceType unwrapUntilSeqType(mlir::Type t) { /// Unwrap the referential and sequential outer types (if any). Returns the /// the element if type is fir::RecordType inline fir::RecordType unwrapIfDerived(fir::BaseBoxType boxTy) { - return fir::unwrapSequenceType(fir::unwrapRefType(boxTy.getEleTy())) - .template dyn_cast(); + return mlir::dyn_cast( + fir::unwrapSequenceType(fir::unwrapRefType(boxTy.getEleTy()))); } /// Return true iff `boxTy` wraps a fir::RecordType with length parameters @@ -377,7 +378,7 @@ bool isRecordWithDescriptorMember(mlir::Type ty); /// Return true iff `ty` is a RecordType with type parameters. inline bool isRecordWithTypeParameters(mlir::Type ty) { - if (auto recTy = ty.dyn_cast_or_null()) + if (auto recTy = mlir::dyn_cast_or_null(ty)) return recTy.isDependentType(); return false; } @@ -401,14 +402,14 @@ mlir::Type fromRealTypeID(mlir::MLIRContext *context, llvm::Type::TypeID typeID, int getTypeCode(mlir::Type ty, const KindMapping &kindMap); inline bool BaseBoxType::classof(mlir::Type type) { - return type.isa(); + return mlir::isa(type); } /// Return true iff `ty` is none or fir.array. inline bool isNoneOrSeqNone(mlir::Type type) { - if (auto seqTy = type.dyn_cast()) - return seqTy.getEleTy().isa(); - return type.isa(); + if (auto seqTy = mlir::dyn_cast(type)) + return mlir::isa(seqTy.getEleTy()); + return mlir::isa(type); } /// Return a fir.box or fir.class if the type is polymorphic. If the type @@ -428,16 +429,16 @@ inline mlir::Type wrapInClassOrBoxType(mlir::Type eleTy, /// !fir.array<2xf32> -> !fir.array<2xnone> /// !fir.heap> -> !fir.heap> inline mlir::Type updateTypeForUnlimitedPolymorphic(mlir::Type ty) { - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return fir::SequenceType::get( seqTy.getShape(), updateTypeForUnlimitedPolymorphic(seqTy.getEleTy())); - if (auto heapTy = ty.dyn_cast()) + if (auto heapTy = mlir::dyn_cast(ty)) return fir::HeapType::get( updateTypeForUnlimitedPolymorphic(heapTy.getEleTy())); - if (auto pointerTy = ty.dyn_cast()) + if (auto pointerTy = mlir::dyn_cast(ty)) return fir::PointerType::get( updateTypeForUnlimitedPolymorphic(pointerTy.getEleTy())); - if (!ty.isa()) + if (!mlir::isa(ty)) return mlir::NoneType::get(ty.getContext()); return ty; } @@ -451,18 +452,19 @@ mlir::Type changeElementType(mlir::Type type, mlir::Type newElementType, /// Is `t` an address to fir.box or class type? inline bool isBoxAddress(mlir::Type t) { - return fir::isa_ref_type(t) && fir::unwrapRefType(t).isa(); + return fir::isa_ref_type(t) && + mlir::isa(fir::unwrapRefType(t)); } /// Is `t` a fir.box or class address or value type? inline bool isBoxAddressOrValue(mlir::Type t) { - return fir::unwrapRefType(t).isa(); + return mlir::isa(fir::unwrapRefType(t)); } /// Is this a fir.boxproc address type? inline bool isBoxProcAddressType(mlir::Type t) { t = fir::dyn_cast_ptrEleTy(t); - return t && t.isa(); + return t && mlir::isa(t); } /// Return a string representation of `ty`. diff --git a/flang/include/flang/Optimizer/Dialect/FIRTypes.td b/flang/include/flang/Optimizer/Dialect/FIRTypes.td index 3b876e4642da..7378ed93944c 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRTypes.td +++ b/flang/include/flang/Optimizer/Dialect/FIRTypes.td @@ -578,7 +578,7 @@ def fir_VoidType : FIR_Type<"Void", "void"> { // Whether a type is a BaseBoxType def IsBaseBoxTypePred - : CPred<"$_self.isa<::fir::BaseBoxType>()">; + : CPred<"mlir::isa<::fir::BaseBoxType>($_self)">; def fir_BaseBoxType : Type; // Generalized FIR and standard dialect types representing intrinsic types diff --git a/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td b/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td index 6405afbf1bfb..3f78a93a2515 100644 --- a/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td +++ b/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td @@ -75,7 +75,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// variable. mlir::Type getElementOrSequenceType() { mlir::Type type = fir::unwrapPassByRefType(fir::unwrapRefType(getBase().getType())); - if (auto boxCharType = type.dyn_cast()) + if (auto boxCharType = mlir::dyn_cast(type)) return boxCharType.getEleTy(); return type; } @@ -87,13 +87,13 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is the variable an array? bool isArray() { - return getElementOrSequenceType().isa(); + return mlir::isa(getElementOrSequenceType()); } /// Return the rank of the entity if it is known at compile time. std::optional getRank() { if (auto sequenceType = - getElementOrSequenceType().dyn_cast()) { + mlir::dyn_cast(getElementOrSequenceType())) { if (sequenceType.hasUnknownShape()) return {}; return sequenceType.getDimension(); @@ -133,7 +133,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is this a Fortran character variable? bool isCharacter() { - return getElementType().isa(); + return mlir::isa(getElementType()); } /// Is this a Fortran character variable with an explicit length? @@ -149,7 +149,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is this variable represented as a fir.box or fir.class value? bool isBoxValue() { - return getBase().getType().isa(); + return mlir::isa(getBase().getType()); } /// Is this variable represented as a fir.box or fir.class address? diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h index aa68d0811c48..3830237f96f3 100644 --- a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h +++ b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h @@ -40,9 +40,9 @@ namespace hlfir { inline mlir::Type getFortranElementType(mlir::Type type) { type = fir::unwrapSequenceType( fir::unwrapPassByRefType(fir::unwrapRefType(type))); - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.getEleTy(); - if (auto boxCharType = type.dyn_cast()) + if (auto boxCharType = mlir::dyn_cast(type)) return boxCharType.getEleTy(); return type; } @@ -51,12 +51,12 @@ inline mlir::Type getFortranElementType(mlir::Type type) { /// fir.array type. Otherwise, returns the Fortran element typeof the entity. inline mlir::Type getFortranElementOrSequenceType(mlir::Type type) { type = fir::unwrapPassByRefType(fir::unwrapRefType(type)); - if (auto exprType = type.dyn_cast()) { + if (auto exprType = mlir::dyn_cast(type)) { if (exprType.isArray()) return fir::SequenceType::get(exprType.getShape(), exprType.getEleTy()); return exprType.getEleTy(); } - if (auto boxCharType = type.dyn_cast()) + if (auto boxCharType = mlir::dyn_cast(type)) return boxCharType.getEleTy(); return type; } @@ -64,16 +64,16 @@ inline mlir::Type getFortranElementOrSequenceType(mlir::Type type) { /// Is this a fir.box or fir.class address type? inline bool isBoxAddressType(mlir::Type type) { type = fir::dyn_cast_ptrEleTy(type); - return type && type.isa(); + return type && mlir::isa(type); } /// Is this a fir.box or fir.class address or value type? inline bool isBoxAddressOrValueType(mlir::Type type) { - return fir::unwrapRefType(type).isa(); + return mlir::isa(fir::unwrapRefType(type)); } inline bool isPolymorphicType(mlir::Type type) { - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.isPolymorphic(); return fir::isPolymorphicType(type); } @@ -81,14 +81,14 @@ inline bool isPolymorphicType(mlir::Type type) { /// Is this an SSA value type for the value of a Fortran procedure /// designator ? inline bool isFortranProcedureValue(mlir::Type type) { - return type.isa() || - (type.isa() && + return mlir::isa(type) || + (mlir::isa(type) && fir::isCharacterProcedureTuple(type, /*acceptRawFunc=*/false)); } /// Is this an SSA value type for the value of a Fortran expression? inline bool isFortranValueType(mlir::Type type) { - return type.isa() || fir::isa_trivial(type) || + return mlir::isa(type) || fir::isa_trivial(type) || isFortranProcedureValue(type); } diff --git a/flang/include/flang/Optimizer/Support/Utils.h b/flang/include/flang/Optimizer/Support/Utils.h index 2b4fa50e0e42..2da6f24da40e 100644 --- a/flang/include/flang/Optimizer/Support/Utils.h +++ b/flang/include/flang/Optimizer/Support/Utils.h @@ -29,7 +29,9 @@ namespace fir { /// Return the integer value of a arith::ConstantOp. inline std::int64_t toInt(mlir::arith::ConstantOp cop) { - return cop.getValue().cast().getValue().getSExtValue(); + return mlir::cast(cop.getValue()) + .getValue() + .getSExtValue(); } // Reconstruct binding tables for dynamic dispatch. diff --git a/flang/include/flang/Tools/PointerModels.h b/flang/include/flang/Tools/PointerModels.h index 7acaf2f9fda5..c3c0977d6e54 100644 --- a/flang/include/flang/Tools/PointerModels.h +++ b/flang/include/flang/Tools/PointerModels.h @@ -20,7 +20,7 @@ struct OpenMPPointerLikeModel : public mlir::omp::PointerLikeType::ExternalModel< OpenMPPointerLikeModel, T> { mlir::Type getElementType(mlir::Type pointer) const { - return pointer.cast().getElementType(); + return mlir::cast(pointer).getElementType(); } }; @@ -29,7 +29,7 @@ struct OpenACCPointerLikeModel : public mlir::acc::PointerLikeType::ExternalModel< OpenACCPointerLikeModel, T> { mlir::Type getElementType(mlir::Type pointer) const { - return pointer.cast().getElementType(); + return mlir::cast(pointer).getElementType(); } }; diff --git a/flang/lib/Lower/Allocatable.cpp b/flang/lib/Lower/Allocatable.cpp index 8e84ea2fc5d5..a1957c0eb1bb 100644 --- a/flang/lib/Lower/Allocatable.cpp +++ b/flang/lib/Lower/Allocatable.cpp @@ -162,7 +162,7 @@ static void genRuntimeInitCharacter(fir::FirOpBuilder &builder, args.push_back(builder.createConvert(loc, inputTypes[0], box.getAddr())); args.push_back(builder.createConvert(loc, inputTypes[1], len)); if (kind == 0) - kind = box.getEleTy().cast().getFKind(); + kind = mlir::cast(box.getEleTy()).getFKind(); args.push_back(builder.createIntegerConstant(loc, inputTypes[2], kind)); int rank = box.rank(); args.push_back(builder.createIntegerConstant(loc, inputTypes[3], rank)); @@ -879,7 +879,7 @@ void Fortran::lower::genDeallocateIfAllocated( builder.genIfThen(loc, isAllocated) .genThen([&]() { if (mlir::Type eleType = box.getEleTy(); - eleType.isa() && box.isPolymorphic()) { + mlir::isa(eleType) && box.isPolymorphic()) { mlir::Value declaredTypeDesc = builder.create( loc, mlir::TypeAttr::get(eleType)); genDeallocateBox(converter, box, loc, sym, declaredTypeDesc); @@ -918,7 +918,7 @@ void Fortran::lower::genDeallocateStmt( mlir::Value declaredTypeDesc = {}; if (box.isPolymorphic()) { mlir::Type eleType = box.getEleTy(); - if (eleType.isa()) + if (mlir::isa(eleType)) if (const Fortran::semantics::DerivedTypeSpec *derivedTypeSpec = symbol.GetType()->AsDerived()) { declaredTypeDesc = @@ -1007,7 +1007,7 @@ createMutableProperties(Fortran::lower::AbstractConverter &converter, fir::MutableProperties mutableProperties; std::string name = converter.mangleName(sym); mlir::Type baseAddrTy = converter.genType(sym); - if (auto boxType = baseAddrTy.dyn_cast()) + if (auto boxType = mlir::dyn_cast(baseAddrTy)) baseAddrTy = boxType.getEleTy(); // Allocate and set a variable to hold the address. // It will be set to null in setUnallocatedStatus. @@ -1032,9 +1032,9 @@ createMutableProperties(Fortran::lower::AbstractConverter &converter, mlir::Type eleTy = baseAddrTy; if (auto newTy = fir::dyn_cast_ptrEleTy(eleTy)) eleTy = newTy; - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) eleTy = seqTy.getEleTy(); - if (auto record = eleTy.dyn_cast()) + if (auto record = mlir::dyn_cast(eleTy)) if (record.getNumLenParams() != 0) TODO(loc, "deferred length type parameters."); if (fir::isa_char(eleTy) && nonDeferredParams.empty()) { diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index f66607dfa22f..19c00884bd1b 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -683,7 +683,7 @@ public: auto if_builder = builder->genIfThenElse(loc, isAllocated); if_builder.genThen([&]() { std::string name = mangleName(sym) + ".alloc"; - if (auto seqTy = symType.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(symType)) { fir::ExtendedValue read = fir::factory::genMutableBoxRead( *builder, loc, box, /*mayBePolymorphic=*/false); if (auto read_arr_box = read.getBoxOf()) { @@ -1132,7 +1132,7 @@ private: fir::ExtendedValue lhs = symBoxToExtendedValue(lhs_sb); fir::ExtendedValue rhs = symBoxToExtendedValue(rhs_sb); mlir::Type symType = genType(sym); - if (auto seqTy = symType.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(symType)) { Fortran::lower::StatementContext stmtCtx; Fortran::lower::createSomeArrayAssignment(*this, lhs, rhs, localSymbols, stmtCtx); @@ -1355,7 +1355,7 @@ private: return; } mlir::Type selectorType = selector.getType(); - bool realSelector = selectorType.isa(); + bool realSelector = mlir::isa(selectorType); assert((inArithmeticIfContext || !realSelector) && "invalid selector type"); mlir::Value zero; if (inArithmeticIfContext) @@ -1630,7 +1630,7 @@ private: stmtCtx); stmtCtx.finalizeAndReset(); // Raise an exception if REAL expr is a NaN. - if (expr.getType().isa()) + if (mlir::isa(expr.getType())) expr = builder->create(toLocation(), expr, expr); // An empty valueList indicates to genMultiwayBranch that the branch is // an ArithmeticIfStmt that has two branches on value 0 or 0.0. @@ -2807,7 +2807,7 @@ private: auto caseValue = valueList.begin(); auto caseBlock = blockList.begin(); for (mlir::Attribute attr : attrList) { - if (attr.isa()) { + if (mlir::isa(attr)) { genBranch(*caseBlock++); break; } @@ -2825,7 +2825,7 @@ private: rhsVal.second); }; mlir::Block *newBlock = insertBlock(*caseBlock); - if (attr.isa()) { + if (mlir::isa(attr)) { mlir::Block *newBlock2 = insertBlock(*caseBlock); mlir::Value cond = genCond(*caseValue++, mlir::arith::CmpIPredicate::sge); @@ -2838,12 +2838,12 @@ private: continue; } mlir::arith::CmpIPredicate pred; - if (attr.isa()) { + if (mlir::isa(attr)) { pred = mlir::arith::CmpIPredicate::eq; - } else if (attr.isa()) { + } else if (mlir::isa(attr)) { pred = mlir::arith::CmpIPredicate::sge; } else { - assert(attr.isa() && "unexpected predicate"); + assert(mlir::isa(attr) && "unexpected predicate"); pred = mlir::arith::CmpIPredicate::sle; } mlir::Value cond = genCond(*caseValue++, pred); @@ -3105,7 +3105,7 @@ private: bool isPointer = fir::isPointerType(baseTy); bool isAllocatable = fir::isAllocatableType(baseTy); bool isArray = - fir::dyn_cast_ptrOrBoxEleTy(baseTy).isa(); + mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(baseTy)); const fir::BoxValue *selectorBox = selector.getBoxOf(); if (std::holds_alternative(guard.u)) { // CLASS DEFAULT @@ -3114,12 +3114,12 @@ private: std::get_if(&guard.u)) { // TYPE IS fir::ExactTypeAttr attr = - typeGuardAttr.dyn_cast(); + mlir::dyn_cast(typeGuardAttr); mlir::Value exactValue; mlir::Type addrTy = attr.getType(); if (isArray) { - auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(baseTy) - .dyn_cast(); + auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(baseTy)); addrTy = fir::SequenceType::get(seqTy.getShape(), attr.getType()); } if (isPointer) @@ -3141,7 +3141,7 @@ private: addAssocEntitySymbol(selectorBox->clone(exact)); } else if (intrinsic->category() == Fortran::common::TypeCategory::Character) { - auto charTy = attr.getType().dyn_cast(); + auto charTy = mlir::dyn_cast(attr.getType()); mlir::Value charLen = fir::factory::CharacterExprHelper(*builder, loc) .readLengthFromBox(fir::getBase(selector), charTy); @@ -3158,11 +3158,12 @@ private: } else if (std::holds_alternative( guard.u)) { // CLASS IS - fir::SubclassAttr attr = typeGuardAttr.dyn_cast(); + fir::SubclassAttr attr = + mlir::dyn_cast(typeGuardAttr); mlir::Type addrTy = attr.getType(); if (isArray) { - auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(baseTy) - .dyn_cast(); + auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(baseTy)); addrTy = fir::SequenceType::get(seqTy.getShape(), attr.getType()); } if (isPointer) @@ -4139,7 +4140,7 @@ private: } else if (isDerivedCategory(lhsType->category())) { // Handle parent component. if (Fortran::lower::isParentComponent(assign.lhs)) { - if (!fir::getBase(lhs).getType().isa()) + if (!mlir::isa(fir::getBase(lhs).getType())) lhs = fir::getBase(builder->createBox(loc, lhs)); lhs = Fortran::lower::updateBoxForParentComponent(*this, lhs, assign.lhs); @@ -5490,7 +5491,7 @@ Fortran::lower::LoweringBridge::LoweringBridge( default: break; } - if (!diag.getLocation().isa()) + if (!mlir::isa(diag.getLocation())) os << diag.getLocation() << ": "; os << diag << '\n'; os.flush(); diff --git a/flang/lib/Lower/CallInterface.cpp b/flang/lib/Lower/CallInterface.cpp index 5ad244600328..c1f54ad39287 100644 --- a/flang/lib/Lower/CallInterface.cpp +++ b/flang/lib/Lower/CallInterface.cpp @@ -1182,7 +1182,7 @@ private: Property prop = Property::BaseAddress; if (isValueAttr) { bool isBuiltinCptrType = fir::isa_builtin_cptr_type(type); - if (isBindC || (!type.isa() && + if (isBindC || (!mlir::isa(type) && !obj.attrs.test(Attrs::Optional) && (dynamicType.category() != Fortran::common::TypeCategory::Derived || @@ -1190,7 +1190,7 @@ private: passBy = PassEntityBy::Value; prop = Property::Value; if (isBuiltinCptrType) { - auto recTy = type.dyn_cast(); + auto recTy = mlir::dyn_cast(type); mlir::Type fieldTy = recTy.getTypeList()[0].second; passType = fir::ReferenceType::get(fieldTy); } else { @@ -1714,7 +1714,7 @@ mlir::Type Fortran::lower::getDummyProcedureType( } bool Fortran::lower::isCPtrArgByValueType(mlir::Type ty) { - return ty.isa() && + return mlir::isa(ty) && fir::isa_integer(fir::unwrapRefType(ty)); } diff --git a/flang/lib/Lower/ConvertArrayConstructor.cpp b/flang/lib/Lower/ConvertArrayConstructor.cpp index 24aa9beba6bf..a5b5838fe6b6 100644 --- a/flang/lib/Lower/ConvertArrayConstructor.cpp +++ b/flang/lib/Lower/ConvertArrayConstructor.cpp @@ -336,7 +336,7 @@ public: if (!extent) extent = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (missingLengthParameters) { - if (declaredType.getEleTy().isa()) + if (mlir::isa(declaredType.getEleTy())) emboxLengths.push_back(builder.createIntegerConstant( loc, builder.getCharacterLengthType(), 0)); else @@ -357,7 +357,7 @@ public: bool useSimplePushRuntime(hlfir::Entity value) { return value.isScalar() && - !arrayConstructorElementType.isa() && + !mlir::isa(arrayConstructorElementType) && !fir::isRecordWithAllocatableMember(arrayConstructorElementType) && !fir::isRecordWithTypeParameters(arrayConstructorElementType); } @@ -370,7 +370,7 @@ public: auto [addrExv, cleanUp] = hlfir::convertToAddress( loc, builder, value, arrayConstructorElementType); mlir::Value addr = fir::getBase(addrExv); - if (addr.getType().isa()) + if (mlir::isa(addr.getType())) addr = builder.create(loc, addr); fir::runtime::genPushArrayConstructorSimpleScalar( loc, builder, arrayConstructorVector, addr); @@ -564,7 +564,7 @@ struct LengthAndTypeCollector> { /// lowering an ac-value and must be delayed? static bool missingLengthParameters(mlir::Type elementType, llvm::ArrayRef lengths) { - return (elementType.isa() || + return (mlir::isa(elementType) || fir::isRecordWithTypeParameters(elementType)) && lengths.empty(); } @@ -702,7 +702,8 @@ static ArrayCtorLoweringStrategy selectArrayCtorLoweringStrategy( // Based on what was gathered and the result of the analysis, select and // instantiate the right lowering strategy for the array constructor. if (!extent || needToEvaluateOneExprToGetLengthParameters || - analysis.anyArrayExpr || declaredType.getEleTy().isa()) + analysis.anyArrayExpr || + mlir::isa(declaredType.getEleTy())) return RuntimeTempStrategy( loc, builder, stmtCtx, symMap, declaredType, extent ? std::optional(extent) : std::nullopt, lengths, diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp index c6f7d3410ad5..e4a0cc8d4730 100644 --- a/flang/lib/Lower/ConvertCall.cpp +++ b/flang/lib/Lower/ConvertCall.cpp @@ -49,15 +49,15 @@ static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, llvm::ArrayRef extents, llvm::ArrayRef lengths) { mlir::Type type = base.getType(); - if (type.isa()) + if (mlir::isa(type)) return fir::BoxValue(base, /*lbounds=*/{}, lengths, extents); type = fir::unwrapRefType(type); - if (type.isa()) + if (mlir::isa(type)) return fir::MutableBoxValue(base, lengths, /*mutableProperties*/ {}); - if (auto seqTy = type.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(type)) { if (seqTy.getDimension() != extents.size()) fir::emitFatalError(loc, "incorrect number of extents for array"); - if (seqTy.getEleTy().isa()) { + if (mlir::isa(seqTy.getEleTy())) { if (lengths.empty()) fir::emitFatalError(loc, "missing length for character"); assert(lengths.size() == 1); @@ -65,7 +65,7 @@ static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, } return fir::ArrayBoxValue(base, extents); } - if (type.isa()) { + if (mlir::isa(type)) { if (lengths.empty()) fir::emitFatalError(loc, "missing length for character"); assert(lengths.size() == 1); @@ -193,7 +193,7 @@ static mlir::Value remapActualToDummyDescriptor( llvm::SmallVector lengths; mlir::Type dummyBoxType = caller.getDummyArgumentType(arg); mlir::Type dummyBaseType = fir::unwrapPassByRefType(dummyBoxType); - if (dummyBaseType.isa()) + if (mlir::isa(dummyBaseType)) caller.walkDummyArgumentExtents( arg, [&](const Fortran::lower::SomeExpr &e, bool isAssumedSizeExtent) { extents.emplace_back(lowerSpecExpr(e, isAssumedSizeExtent)); @@ -338,7 +338,7 @@ std::pair Fortran::lower::genCallOpAndResult( if (!caller.callerAllocateResult()) return {}; mlir::Type type = caller.getResultStorageType(); - if (type.isa()) + if (mlir::isa(type)) caller.walkResultExtents( [&](const Fortran::lower::SomeExpr &e, bool isAssumedSizeExtent) { assert(!isAssumedSizeExtent && "result cannot be assumed-size"); @@ -353,7 +353,7 @@ std::pair Fortran::lower::genCallOpAndResult( // Result length parameters should not be provided to box storage // allocation and save_results, but they are still useful information to // keep in the ExtendedValue if non-deferred. - if (!type.isa()) { + if (!mlir::isa(type)) { if (fir::isa_char(fir::unwrapSequenceType(type)) && lengths.empty()) { // Calling an assumed length function. This is only possible if this // is a call to a character dummy procedure. @@ -478,7 +478,7 @@ std::pair Fortran::lower::genCallOpAndResult( // FIR. if (funcPointer) { operands.push_back( - funcPointer.getType().isa() + mlir::isa(funcPointer.getType()) ? builder.create(loc, funcType, funcPointer) : builder.createConvert(loc, funcType, funcPointer)); } @@ -492,8 +492,8 @@ std::pair Fortran::lower::genCallOpAndResult( // arguments of any type and vice versa. mlir::Value cast; auto *context = builder.getContext(); - if (snd.isa() && - fst.getType().isa()) { + if (mlir::isa(snd) && + mlir::isa(fst.getType())) { auto funcTy = mlir::FunctionType::get(context, std::nullopt, std::nullopt); auto boxProcTy = builder.getBoxProcType(funcTy); @@ -734,9 +734,9 @@ std::pair Fortran::lower::genCallOpAndResult( // Call a BIND(C) function that return a char. if (caller.characterize().IsBindC() && - funcType.getResults()[0].isa()) { + mlir::isa(funcType.getResults()[0])) { fir::CharacterType charTy = - funcType.getResults()[0].dyn_cast(); + mlir::dyn_cast(funcType.getResults()[0]); mlir::Value len = builder.createIntegerConstant( loc, builder.getCharacterLengthType(), charTy.getLen()); return {fir::CharBoxValue{callResult, len}, /*resultIsFinalized=*/false}; @@ -890,7 +890,7 @@ extendedValueToHlfirEntity(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type firBaseTy = firBase.getType(); if (fir::isa_trivial(firBaseTy)) return hlfir::EntityWithAttributes{firBase}; - if (auto charTy = firBase.getType().dyn_cast()) { + if (auto charTy = mlir::dyn_cast(firBase.getType())) { // CHAR() intrinsic and BIND(C) procedures returning CHARACTER(1) // are lowered to a fir.char that is not in memory. // This tends to cause a lot of bugs because the rest of the @@ -1061,7 +1061,7 @@ static hlfir::Entity fixProcedureDummyMismatch(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity actual, mlir::Type dummyType) { - if (actual.getType().isa() && + if (mlir::isa(actual.getType()) && fir::isCharacterProcedureTuple(dummyType)) { mlir::Value length = builder.create(loc, builder.getCharacterLengthType()); @@ -1070,7 +1070,7 @@ static hlfir::Entity fixProcedureDummyMismatch(mlir::Location loc, return hlfir::Entity{tuple}; } assert(fir::isCharacterProcedureTuple(actual.getType()) && - dummyType.isa() && + mlir::isa(dummyType) && "unsupported dummy procedure mismatch with the actual argument"); mlir::Value boxProc = fir::factory::extractCharacterProcedureTuple( builder, loc, actual, /*openBoxProc=*/false) @@ -1143,7 +1143,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( assert(actual.isProcedure()); // Do nothing if this is a procedure argument. It is already a // fir.boxproc/fir.tuple as it should. - if (!actual.getType().isa() && + if (!mlir::isa(actual.getType()) && actual.getType() != dummyType) // The actual argument may be a procedure that returns character (a // fir.tuple) while the dummy is not. Extract the tuple @@ -1164,7 +1164,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( // dynamic type matters to determine the contiguity. const bool mustSetDynamicTypeToDummyType = passingPolymorphicToNonPolymorphic && - (actual.isArray() || dummyType.isa()); + (actual.isArray() || mlir::isa(dummyType)); // The simple contiguity of the actual is "lost" when passing a polymorphic // to a non polymorphic entity because the dummy dynamic type matters for @@ -1236,7 +1236,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( preparedDummy.pushExprAssociateCleanUp(associate); } else if (mustDoCopyInOut) { // Copy-in non contiguous variables. - assert(entity.getType().isa() && + assert(mlir::isa(entity.getType()) && "expect non simply contiguous variables to be boxes"); if (actualIsAssumedRank) TODO(loc, "copy-in and copy-out of assumed-rank arguments"); @@ -1294,13 +1294,14 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( // Step 3: now that the dummy argument storage has been prepared, package // it according to the interface. mlir::Value addr; - if (dummyTypeWithActualRank.isa()) { + if (mlir::isa(dummyTypeWithActualRank)) { addr = hlfir::genVariableBoxChar(loc, builder, entity); - } else if (dummyTypeWithActualRank.isa()) { + } else if (mlir::isa(dummyTypeWithActualRank)) { entity = hlfir::genVariableBox(loc, builder, entity); // Ensures the box has the right attributes and that it holds an // addendum if needed. - fir::BaseBoxType actualBoxType = entity.getType().cast(); + fir::BaseBoxType actualBoxType = + mlir::cast(entity.getType()); mlir::Type boxEleType = actualBoxType.getEleTy(); // For now, assume it is not OK to pass the allocatable/pointer // descriptor to a non pointer/allocatable dummy. That is a strict @@ -1567,7 +1568,7 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, // callee side, and it is illegal to use NULL without a MOLD if any // dummy length parameters are assumed. mlir::Type boxTy = fir::dyn_cast_ptrEleTy(argTy); - assert(boxTy && boxTy.isa() && + assert(boxTy && mlir::isa(boxTy) && "must be a fir.box type"); mlir::Value boxStorage = fir::factory::genNullBoxStorage(builder, loc, boxTy); @@ -1635,7 +1636,8 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, caller, callSiteType, callContext.resultType, callContext.isElementalProcWithArrayArgs()); // For procedure pointer function result, just return the call. - if (callContext.resultType && callContext.resultType->isa()) + if (callContext.resultType && + mlir::isa(*callContext.resultType)) return hlfir::EntityWithAttributes(fir::getBase(result)); /// Clean-up associations and copy-in. @@ -2115,9 +2117,9 @@ public: hlfir::getFortranElementType(*callContext.resultType); // Get result length parameters. llvm::SmallVector typeParams; - if (elementType.isa() || + if (mlir::isa(elementType) || fir::isRecordWithTypeParameters(elementType)) { - auto charType = elementType.dyn_cast(); + auto charType = mlir::dyn_cast(elementType); if (charType && charType.hasConstantLen()) typeParams.push_back(builder.createIntegerConstant( loc, builder.getIndexType(), charType.getLen())); @@ -2523,7 +2525,7 @@ genIntrinsicRef(const Fortran::evaluate::SpecificIntrinsic *intrinsic, } std::optional result = genHLFIRIntrinsicRefCore( loweredActuals, intrinsic, argLowering, callContext); - if (result && result->getType().isa()) { + if (result && mlir::isa(result->getType())) { fir::FirOpBuilder *bldr = &callContext.getBuilder(); callContext.stmtCtx.attachCleanup( [=]() { bldr->create(loc, *result); }); diff --git a/flang/lib/Lower/ConvertConstant.cpp b/flang/lib/Lower/ConvertConstant.cpp index ed389bbe4ae5..653e874a969c 100644 --- a/flang/lib/Lower/ConvertConstant.cpp +++ b/flang/lib/Lower/ConvertConstant.cpp @@ -184,8 +184,8 @@ private: if (!attributeElementType || attributes.empty()) return {}; - assert(symTy.isa() && "expecting an array global"); - auto arrTy = symTy.cast(); + assert(mlir::isa(symTy) && "expecting an array global"); + auto arrTy = mlir::cast(symTy); llvm::SmallVector tensorShape(arrTy.getShape()); std::reverse(tensorShape.begin(), tensorShape.end()); auto tensorTy = @@ -423,14 +423,14 @@ static mlir::Value genStructureComponentInit( // address field, which ought to be an intptr_t on the target. mlir::Value addr = fir::getBase( Fortran::lower::genExtAddrInInitializer(converter, loc, expr)); - if (addr.getType().isa()) + if (mlir::isa(addr.getType())) addr = builder.create(loc, addr); assert((fir::isa_ref_type(addr.getType()) || - addr.getType().isa()) && + mlir::isa(addr.getType())) && "expect reference type for address field"); assert(fir::isa_derived(componentTy) && "expect C_PTR, C_FUNPTR to be a record"); - auto cPtrRecTy = componentTy.cast(); + auto cPtrRecTy = mlir::cast(componentTy); llvm::StringRef addrFieldName = Fortran::lower::builtin::cptrFieldName; mlir::Type addrFieldTy = cPtrRecTy.getType(addrFieldName); auto addrField = builder.create( @@ -460,7 +460,7 @@ static mlir::Value genInlinedStructureCtorLitImpl( Fortran::lower::AbstractConverter &converter, mlir::Location loc, const Fortran::evaluate::StructureConstructor &ctor, mlir::Type type) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - auto recTy = type.cast(); + auto recTy = mlir::cast(type); if (!converter.getLoweringOptions().getLowerToHighLevelFIR()) { mlir::Value res = builder.create(loc, recTy); @@ -587,7 +587,7 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, } while (con.IncrementSubscripts(subscripts)); } else if constexpr (T::category == Fortran::common::TypeCategory::Derived) { do { - mlir::Type eleTy = arrayTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); mlir::Value elementVal = genScalarLit(converter, loc, con.At(subscripts), eleTy, /*outlineInReadOnlyMemory=*/false); @@ -597,7 +597,7 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, } else { llvm::SmallVector rangeStartIdx; uint64_t rangeSize = 0; - mlir::Type eleTy = arrayTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); do { auto getElementVal = [&]() { return builder.createConvert(loc, eleTy, @@ -620,12 +620,11 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, llvm::SmallVector rangeBounds; llvm::SmallVector idx = createIdx(); for (size_t i = 0; i < idx.size(); ++i) { - rangeBounds.push_back(rangeStartIdx[i] - .cast() + rangeBounds.push_back(mlir::cast(rangeStartIdx[i]) .getValue() .getSExtValue()); rangeBounds.push_back( - idx[i].cast().getValue().getSExtValue()); + mlir::cast(idx[i]).getValue().getSExtValue()); } array = builder.create( loc, arrayTy, array, getElementVal(), @@ -647,7 +646,7 @@ genOutlineArrayLit(Fortran::lower::AbstractConverter &converter, mlir::Location loc, mlir::Type arrayTy, const Fortran::evaluate::Constant &constant) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - mlir::Type eleTy = arrayTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); llvm::StringRef globalName = converter.getUniqueLitName( loc, std::make_unique(toEvExpr(constant)), eleTy); diff --git a/flang/lib/Lower/ConvertExpr.cpp b/flang/lib/Lower/ConvertExpr.cpp index fb7807718ff8..9567685aa3d2 100644 --- a/flang/lib/Lower/ConvertExpr.cpp +++ b/flang/lib/Lower/ConvertExpr.cpp @@ -267,7 +267,7 @@ arrayLoadExtValue(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type ty = fir::applyPathToType(arrTy, path); if (!ty) fir::emitFatalError(loc, "path does not apply to type"); - if (!ty.isa()) { + if (!mlir::isa(ty)) { if (fir::isa_char(ty)) { mlir::Value len = newLen; if (!len) @@ -282,7 +282,7 @@ arrayLoadExtValue(fir::FirOpBuilder &builder, mlir::Location loc, } return newBase; } - arrTy = ty.cast(); + arrTy = mlir::cast(ty); } auto arrayToExtendedValue = @@ -412,15 +412,15 @@ static fir::ExtendedValue genLoad(fir::FirOpBuilder &builder, return addr.match( [](const fir::CharBoxValue &box) -> fir::ExtendedValue { return box; }, [&](const fir::PolymorphicValue &p) -> fir::ExtendedValue { - if (fir::unwrapRefType(fir::getBase(p).getType()) - .isa()) + if (mlir::isa( + fir::unwrapRefType(fir::getBase(p).getType()))) return p; mlir::Value load = builder.create(loc, fir::getBase(p)); return fir::PolymorphicValue(load, p.getSourceBox()); }, [&](const fir::UnboxedValue &v) -> fir::ExtendedValue { - if (fir::unwrapRefType(fir::getBase(v).getType()) - .isa()) + if (mlir::isa( + fir::unwrapRefType(fir::getBase(v).getType()))) return v; return builder.create(loc, fir::getBase(v)); }, @@ -536,8 +536,8 @@ static mlir::Value createBoxProcCharTuple(Fortran::lower::AbstractConverter &converter, mlir::Type argTy, mlir::Value funcAddr, mlir::Value charLen) { - auto boxTy = - argTy.cast().getType(0).cast(); + auto boxTy = mlir::cast( + mlir::cast(argTy).getType(0)); mlir::Location loc = converter.getCurrentLocation(); auto &builder = converter.getFirOpBuilder(); @@ -549,7 +549,7 @@ createBoxProcCharTuple(Fortran::lower::AbstractConverter &converter, mlir::Type toTy = boxTy.getEleTy(); if (fir::isa_ref_type(fromTy)) funcAddr = builder.createConvert(loc, toTy, funcAddr); - else if (fromTy.isa()) + else if (mlir::isa(fromTy)) funcAddr = builder.create(loc, toTy, funcAddr); auto boxProc = [&]() -> mlir::Value { @@ -575,7 +575,7 @@ absentBoxToUnallocatedBox(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value isPresent) { mlir::Value box = fir::getBase(exv); mlir::Type boxType = box.getType(); - assert(boxType.isa() && "argument must be a fir.box"); + assert(mlir::isa(boxType) && "argument must be a fir.box"); mlir::Value emptyBox = fir::factory::createUnallocatedBox(builder, loc, boxType, std::nullopt); auto safeToReadBox = @@ -915,7 +915,7 @@ public: if (inInitializer) return Fortran::lower::genInlinedStructureCtorLit(converter, loc, ctor); mlir::Type ty = translateSomeExprToFIRType(converter, toEvExpr(ctor)); - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); auto fieldTy = fir::FieldType::get(ty.getContext()); mlir::Value res = builder.createTemporary(loc, recTy); mlir::Value box = builder.createBox(loc, fir::ExtendedValue{res}); @@ -1172,8 +1172,8 @@ public: if (!charBox) fir::emitFatalError(loc, "expected scalar character"); mlir::Value charAddr = charBox->getAddr(); - auto charType = - fir::unwrapPassByRefType(charAddr.getType()).cast(); + auto charType = mlir::cast( + fir::unwrapPassByRefType(charAddr.getType())); if (charType.hasConstantLen()) { // Erase previous constant length from the base type. fir::CharacterType::LenType newLen = fir::CharacterType::unknownLen(); @@ -1441,7 +1441,7 @@ public: auto fldTy = fir::FieldType::get(&converter.getMLIRContext()); // FIXME: need to thread the LEN type parameters here. for (const Fortran::evaluate::Component *field : list) { - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); const Fortran::semantics::Symbol &sym = getLastSym(*field); std::string name = converter.getRecordTypeFieldName(sym); coorArgs.push_back(builder.create( @@ -1478,7 +1478,7 @@ public: mlir::Type genSubType(mlir::Type arrTy, unsigned dims) { mlir::Type unwrapTy = fir::dyn_cast_ptrOrBoxEleTy(arrTy); assert(unwrapTy && "must be a pointer or box type"); - auto seqTy = unwrapTy.cast(); + auto seqTy = mlir::cast(unwrapTy); llvm::ArrayRef shape = seqTy.getShape(); assert(shape.size() > 0 && "removing columns for sequence sans shape"); assert(dims <= shape.size() && "removing more columns than exist"); @@ -1550,9 +1550,9 @@ public: } mlir::Type eleTy = fir::dyn_cast_ptrOrBoxEleTy(base.getType()); - if (auto classTy = eleTy.dyn_cast()) + if (auto classTy = mlir::dyn_cast(eleTy)) eleTy = classTy.getEleTy(); - auto seqTy = eleTy.cast(); + auto seqTy = mlir::cast(eleTy); assert(args.size() == seqTy.getDimension()); mlir::Type ty = builder.getRefType(seqTy.getEleTy()); auto addr = builder.create(loc, ty, base, args); @@ -1571,7 +1571,7 @@ public: mlir::Location loc = getLoc(); mlir::Value addr = fir::getBase(array); mlir::Type arrTy = fir::dyn_cast_ptrEleTy(addr.getType()); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); mlir::Type seqTy = builder.getRefType(builder.getVarLenSeqTy(eleTy)); mlir::Type refTy = builder.getRefType(eleTy); mlir::Value base = builder.createConvert(loc, seqTy, addr); @@ -1656,7 +1656,7 @@ public: mlir::Location loc = getLoc(); mlir::Value addr = fir::getBase(exv); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(addr.getType()); - mlir::Type eleTy = arrTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrTy).getEleTy(); mlir::Type refTy = builder.getRefType(eleTy); mlir::IndexType idxTy = builder.getIndexType(); llvm::SmallVector arrayCoorArgs; @@ -1766,8 +1766,9 @@ public: mlir::Location loc = getLoc(); ExtValue exv = genBoxArg(expr); auto exvTy = fir::getBase(exv).getType(); - if (exvTy.isa()) { - auto boxProcTy = builder.getBoxProcType(exvTy.cast()); + if (mlir::isa(exvTy)) { + auto boxProcTy = + builder.getBoxProcType(mlir::cast(exvTy)); return builder.create(loc, boxProcTy, fir::getBase(exv)); } @@ -1861,7 +1862,7 @@ public: // IS_CONTIGUOUS may require an assumed size TYPE(*) to be passed to // the intrinsic library utility as a fir.box. if (argRules.lowerAs == fir::LowerIntrinsicArgAs::Box && - !fir::getBase(exv).getType().isa()) { + !mlir::isa(fir::getBase(exv).getType())) { operands.emplace_back( fir::factory::createBoxValue(builder, loc, exv)); continue; @@ -2005,7 +2006,7 @@ public: fir::getTypeParams(mold); mlir::Value charLen; mlir::Type elementType = fir::unwrapSequenceType(type); - if (auto charType = elementType.dyn_cast()) { + if (auto charType = mlir::dyn_cast(elementType)) { charLen = allocMemTypeParams.empty() ? fir::factory::readCharLen(builder, loc, mold) : allocMemTypeParams[0]; @@ -2017,7 +2018,7 @@ public: mlir::Value temp = builder.create( loc, type, tempName, allocMemTypeParams, extents); - if (fir::unwrapSequenceType(type).isa()) + if (mlir::isa(fir::unwrapSequenceType(type))) return fir::CharArrayBoxValue{temp, charLen, extents}; return fir::ArrayBoxValue{temp, extents}; } @@ -2166,7 +2167,7 @@ public: // We have to initialize the temp if it may have components // that need initialization. If there are no components // requiring initialization, then the call is a no-op. - if (getElementTypeOf(temp).isa()) { + if (mlir::isa(getElementTypeOf(temp))) { mlir::Value tempBox = fir::getBase(builder.createBox(loc, temp)); fir::runtime::genDerivedTypeInitialize(builder, loc, tempBox); } @@ -2312,7 +2313,7 @@ public: if (!copyOutPair.restrictCopyAndFreeAtRuntime) { doCopyOut(); - if (fir::getElementTypeOf(copyOutPair.temp).isa()) { + if (mlir::isa(fir::getElementTypeOf(copyOutPair.temp))) { // Destroy components of the temporary (if any). // If there are no components requiring destruction, then the call // is a no-op. @@ -2330,7 +2331,8 @@ public: builder.genIfThen(loc, *copyOutPair.restrictCopyAndFreeAtRuntime) .genThen([&]() { doCopyOut(); - if (fir::getElementTypeOf(copyOutPair.temp).isa()) { + if (mlir::isa( + fir::getElementTypeOf(copyOutPair.temp))) { // Destroy components of the temporary (if any). // If there are no components requiring destruction, then the call // is a no-op. @@ -2381,7 +2383,7 @@ public: mlir::Value actualArgBase = fir::getBase(actualArg); mlir::Value isPresent = builder.create( loc, builder.getI1Type(), actualArgBase); - if (!actualArgBase.getType().isa()) + if (!mlir::isa(actualArgBase.getType())) return {actualArg, isPresent}; ExtValue safeToReadBox = absentBoxToUnallocatedBox(builder, loc, actualArg, isPresent); @@ -2408,7 +2410,7 @@ public: fir::getAdaptToByRefAttr(builder)}); return fir::CharBoxValue{temp, len}; } - assert((fir::isa_trivial(type) || type.isa()) && + assert((fir::isa_trivial(type) || mlir::isa(type)) && "must be simple scalar"); return builder.createTemporary(loc, type, llvm::ArrayRef{ @@ -2585,7 +2587,7 @@ public: // callee side, and it is illegal to use NULL without a MOLD if any // dummy length parameters are assumed. mlir::Type boxTy = fir::dyn_cast_ptrEleTy(argTy); - assert(boxTy && boxTy.isa() && + assert(boxTy && mlir::isa(boxTy) && "must be a fir.box type"); mlir::Value boxStorage = builder.createTemporary(loc, boxTy); mlir::Value nullBox = fir::factory::createUnallocatedBox( @@ -2643,10 +2645,11 @@ public: // If a character procedure was passed instead, handle the // mismatch. auto funcTy = - x.getAddr().getType().dyn_cast(); + mlir::dyn_cast(x.getAddr().getType()); if (funcTy && funcTy.getNumResults() == 1 && - funcTy.getResult(0).isa()) { - auto boxTy = funcTy.getResult(0).cast(); + mlir::isa(funcTy.getResult(0))) { + auto boxTy = + mlir::cast(funcTy.getResult(0)); mlir::Value ref = builder.createConvert( loc, builder.getRefType(boxTy.getEleTy()), x.getAddr()); auto len = builder.create( @@ -2667,7 +2670,7 @@ public: // free-casting the base address to be a !fir.char reference and // setting the LEN argument to undefined. What could go wrong? auto dataPtr = fir::getBase(x); - assert(!dataPtr.getType().template isa()); + assert(!mlir::isa(dataPtr.getType())); return builder.convertWithSemantics( loc, argTy, dataPtr, /*allowCharacterConversion=*/true); @@ -2742,7 +2745,7 @@ public: loc, fir::ClassType::get(mlir::NoneType::get(builder.getContext())), box); - } else if (box.getType().isa() && + } else if (mlir::isa(box.getType()) && fir::isPolymorphicType(argTy)) { box = builder.create(loc, argTy, box, mlir::Value{}, /*slice=*/mlir::Value{}); @@ -2791,7 +2794,7 @@ public: : builder.createBox(getLoc(), genTempExtAddr(*expr), fir::isPolymorphicType(argTy), fir::isAssumedType(argTy)); - if (box.getType().isa() && + if (mlir::isa(box.getType()) && fir::isPolymorphicType(argTy) && !fir::isAssumedType(argTy)) { mlir::Type actualTy = argTy; if (Fortran::lower::isParentComponent(*expr)) @@ -3030,10 +3033,11 @@ private: Fortran::common::ScopedSet(semant, PushVal); static bool isAdjustedArrayElementType(mlir::Type t) { - return fir::isa_char(t) || fir::isa_derived(t) || t.isa(); + return fir::isa_char(t) || fir::isa_derived(t) || + mlir::isa(t); } static bool elementTypeWasAdjusted(mlir::Type t) { - if (auto ty = t.dyn_cast()) + if (auto ty = mlir::dyn_cast(t)) return isAdjustedArrayElementType(ty.getEleTy()); return false; } @@ -3050,15 +3054,15 @@ static void genScalarUserDefinedAssignmentCall(fir::FirOpBuilder &builder, auto prepareUserDefinedArg = [](fir::FirOpBuilder &builder, mlir::Location loc, const fir::ExtendedValue &value, mlir::Type argType) -> mlir::Value { - if (argType.isa()) { + if (mlir::isa(argType)) { const fir::CharBoxValue *charBox = value.getCharBox(); assert(charBox && "argument type mismatch in elemental user assignment"); return fir::factory::CharacterExprHelper{builder, loc}.createEmbox( *charBox); } - if (argType.isa()) { + if (mlir::isa(argType)) { mlir::Value box = - builder.createBox(loc, value, argType.isa()); + builder.createBox(loc, value, mlir::isa(argType)); return builder.createConvert(loc, argType, box); } // Simple pass by address. @@ -3170,7 +3174,7 @@ convertToArrayBoxValue(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value val, mlir::Value len) { mlir::Type ty = fir::unwrapRefType(val.getType()); mlir::IndexType idxTy = builder.getIndexType(); - auto seqTy = ty.cast(); + auto seqTy = mlir::cast(ty); auto undef = builder.create(loc, idxTy); llvm::SmallVector extents(seqTy.getDimension(), undef); if (fir::isa_char(seqTy.getEleTy())) @@ -3462,7 +3466,7 @@ public: [&](const auto &e) { auto f = genarr(e); ExtValue exv = f(IterationSpace{}); - if (fir::getBase(exv).getType().template isa()) + if (mlir::isa(fir::getBase(exv).getType())) return exv; fir::emitFatalError(getLoc(), "array must be emboxed"); }, @@ -3487,10 +3491,9 @@ public: tempRes, dest.getSlice(), dest.getTypeparams()); - auto arrTy = - fir::dyn_cast_ptrEleTy(tempRes.getType()).cast(); - if (auto charTy = - arrTy.getEleTy().template dyn_cast()) { + auto arrTy = mlir::cast( + fir::dyn_cast_ptrEleTy(tempRes.getType())); + if (auto charTy = mlir::dyn_cast(arrTy.getEleTy())) { if (fir::characterWithDynamicLen(charTy)) TODO(loc, "CHARACTER does not have constant LEN"); mlir::Value len = builder.createIntegerConstant( @@ -3912,17 +3915,18 @@ private: mlir::Value convertElementForUpdate(mlir::Location loc, mlir::Type eleTy, mlir::Value origVal) { if (auto origEleTy = fir::dyn_cast_ptrEleTy(origVal.getType())) - if (origEleTy.isa()) { + if (mlir::isa(origEleTy)) { // If origVal is a box variable, load it so it is in the value domain. origVal = builder.create(loc, origVal); } - if (origVal.getType().isa() && !eleTy.isa()) { + if (mlir::isa(origVal.getType()) && + !mlir::isa(eleTy)) { if (isPointerAssignment()) TODO(loc, "lhs of pointer assignment returned unexpected value"); TODO(loc, "invalid box conversion in elemental computation"); } - if (isPointerAssignment() && eleTy.isa() && - !origVal.getType().isa()) { + if (isPointerAssignment() && mlir::isa(eleTy) && + !mlir::isa(origVal.getType())) { // This is a pointer assignment and the rhs is a raw reference to a TARGET // in memory. Embox the reference so it can be stored to the boxed // POINTER variable. @@ -3930,7 +3934,7 @@ private: if (auto eleTy = fir::dyn_cast_ptrEleTy(origVal.getType()); fir::hasDynamicSize(eleTy)) TODO(loc, "TARGET of pointer assignment with runtime size/shape"); - auto memrefTy = fir::boxMemRefType(eleTy.cast()); + auto memrefTy = fir::boxMemRefType(mlir::cast(eleTy)); auto castTo = builder.createConvert(loc, memrefTy, origVal); origVal = builder.create(loc, eleTy, castTo); } @@ -3982,7 +3986,7 @@ private: auto arrayOp = builder.create( loc, resRefTy, innerArg, iterSpace.iterVec(), fir::factory::getTypeParams(loc, builder, destination)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { llvm::SmallVector substringBounds; populateBounds(substringBounds, substring); mlir::Value dstLen = fir::factory::genLenOfCharacter( @@ -3996,7 +4000,7 @@ private: loc, destination, builder, arrayOp, exv, eleTy, innerArg); return abstractArrayExtValue(amend /*FIXME: typeparams?*/); } - assert(eleTy.isa() && "must be an array"); + assert(mlir::isa(eleTy) && "must be an array"); TODO(loc, "array (as element) assignment"); } // By value semantics. The element is being assigned by value. @@ -4060,7 +4064,7 @@ private: llvm::SmallVector getShape(ArrayOperand array) { if (array.slice) return computeSliceShape(array.slice); - if (array.memref.getType().isa()) + if (mlir::isa(array.memref.getType())) return fir::factory::readExtents(builder, getLoc(), fir::BoxValue{array.memref}); return fir::factory::getExtents(array.shape); @@ -4133,7 +4137,7 @@ private: mlir::Location loc = getLoc(); return [=, builder = &converter.getFirOpBuilder()](IterSpace iters) { mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(tmp.getType()); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); mlir::Type eleRefTy = builder->getRefType(eleTy); mlir::IntegerType i1Ty = builder->getI1Type(); // Adjust indices for any shift of the origin of the array. @@ -4442,15 +4446,15 @@ private: TODO(loc, "polymorphic array temporary"); if (ccLoadDest) return (*ccLoadDest)(shape); - auto seqTy = type.dyn_cast(); + auto seqTy = mlir::dyn_cast(type); assert(seqTy && "must be an array"); // TODO: Need to thread the LEN parameters here. For character, they may // differ from the operands length (e.g concatenation). So the array loads // type parameters are not enough. - if (auto charTy = seqTy.getEleTy().dyn_cast()) + if (auto charTy = mlir::dyn_cast(seqTy.getEleTy())) if (charTy.hasDynamicLen()) TODO(loc, "character array expression temp with dynamic length"); - if (auto recTy = seqTy.getEleTy().dyn_cast()) + if (auto recTy = mlir::dyn_cast(seqTy.getEleTy())) if (recTy.getNumLenParams() > 0) TODO(loc, "derived type array expression temp with LEN parameters"); if (mlir::Type eleTy = fir::unwrapSequenceType(type); @@ -4827,7 +4831,7 @@ private: }); } else { ExtValue exv = asScalarRef(*expr); - if (fir::getBase(exv).getType().isa()) { + if (mlir::isa(fir::getBase(exv).getType())) { operands.emplace_back( [=](IterSpace iters) -> ExtValue { return exv; }); } else { @@ -5565,7 +5569,7 @@ private: } static mlir::Type unwrapBoxEleTy(mlir::Type ty) { - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return fir::unwrapRefType(boxTy.getEleTy()); return ty; } @@ -5575,7 +5579,7 @@ private: ty = unwrapBoxEleTy(ty); mlir::Location loc = getLoc(); mlir::IndexType idxTy = builder.getIndexType(); - for (auto extent : ty.cast().getShape()) { + for (auto extent : mlir::cast(ty).getShape()) { auto v = extent == fir::SequenceType::getUnknownExtent() ? builder.create(loc, idxTy).getResult() : builder.createIntegerConstant(loc, idxTy, extent); @@ -5638,7 +5642,8 @@ private: mlir::Location loc = getLoc(); mlir::Value memref = fir::getBase(extMemref); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(memref.getType()); - assert(arrTy.isa() && "memory ref must be an array"); + assert(mlir::isa(arrTy) && + "memory ref must be an array"); mlir::Value shape = builder.createShape(loc, extMemref); mlir::Value slice; if (components.isSlice()) { @@ -5688,12 +5693,12 @@ private: components.suffixComponents); } if (components.hasComponents()) { - auto seqTy = arrTy.cast(); + auto seqTy = mlir::cast(arrTy); mlir::Type eleTy = fir::applyPathToType(seqTy.getEleTy(), components.suffixComponents); if (!eleTy) fir::emitFatalError(loc, "slicing path is ill-formed"); - if (auto realTy = eleTy.dyn_cast()) + if (auto realTy = mlir::dyn_cast(eleTy)) eleTy = Fortran::lower::convertReal(realTy.getContext(), realTy.getFKind()); @@ -5713,13 +5718,14 @@ private: // value. The value of the box is forwarded in the continuation. mlir::Type reduceTy = reduceRank(arrTy, slice); mlir::Type boxTy = fir::BoxType::get(reduceTy); - if (memref.getType().isa() && !components.hasComponents()) + if (mlir::isa(memref.getType()) && + !components.hasComponents()) boxTy = fir::ClassType::get(reduceTy); if (components.substring) { // Adjust char length to substring size. fir::CharacterType charTy = fir::factory::CharacterExprHelper::getCharType(reduceTy); - auto seqTy = reduceTy.cast(); + auto seqTy = mlir::cast(reduceTy); // TODO: Use a constant for fir.char LEN if we can compute it. boxTy = fir::BoxType::get( fir::SequenceType::get(fir::CharacterType::getUnknownLen( @@ -5734,7 +5740,7 @@ private: nonDeferredLenParams = fir::factory::getNonDeferredLenParams(extMemref); } mlir::Value embox = - memref.getType().isa() + mlir::isa(memref.getType()) ? builder.create(loc, boxTy, memref, shape, slice) .getResult() : builder @@ -5745,7 +5751,7 @@ private: return fir::BoxValue(embox, lbounds, nonDeferredLenParams); }; } - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); if (isReferentiallyOpaque()) { // Semantics are an opaque reference to an array. // This case forwards a continuation that will generate the address @@ -5760,12 +5766,12 @@ private: mlir::Value coor = builder.create( loc, refEleTy, memref, shape, slice, indices, fir::getTypeParams(extMemref)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { llvm::SmallVector substringBounds; populateBounds(substringBounds, components.substring); if (!substringBounds.empty()) { mlir::Value dstLen = fir::factory::genLenOfCharacter( - builder, loc, arrTy.cast(), memref, + builder, loc, mlir::cast(arrTy), memref, fir::getTypeParams(extMemref), iters.iterVec(), substringBounds); fir::CharBoxValue dstChar(coor, dstLen); @@ -5863,7 +5869,7 @@ private: mlir::Type eleRefTy = builder.getRefType(eleTy); mlir::Value arrayOp = builder.create( loc, eleRefTy, arrLd, iters.iterVec(), arrLdTypeParams); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { llvm::SmallVector substringBounds; populateBounds(substringBounds, components.substring); if (!substringBounds.empty()) { @@ -5896,7 +5902,7 @@ private: const bool hasOptionalAttr = fir::valueHasFirAttribute(base, fir::getOptionalAttrName()); mlir::Type baseType = fir::unwrapRefType(base.getType()); - const bool isBox = baseType.isa(); + const bool isBox = mlir::isa(baseType); const bool isAllocOrPtr = Fortran::evaluate::IsAllocatableOrPointerObject(expr); mlir::Type arrType = fir::unwrapPassByRefType(baseType); @@ -5989,7 +5995,7 @@ private: if (slice) { auto slOp = mlir::dyn_cast(slice.getDefiningOp()); assert(slOp && "expected slice op"); - auto seqTy = arrTy.dyn_cast(); + auto seqTy = mlir::dyn_cast(arrTy); assert(seqTy && "expected array type"); mlir::Operation::operand_range triples = slOp.getTriples(); fir::SequenceType::Shape shape; @@ -6053,7 +6059,7 @@ private: mlir::IndexType idxTy = builder.getIndexType(); mlir::Value multiplier = builder.createIntegerConstant(loc, idxTy, 1); if (fir::hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { // Array of char with dynamic LEN parameter. Downcast to an array // of singleton char, and scale by the len type parameter from // `exv`. @@ -6074,7 +6080,7 @@ private: }); fir::CharacterType newEleTy = fir::CharacterType::getSingleton( eleTy.getContext(), charTy.getFKind()); - if (auto seqTy = resTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(resTy)) { assert(eleTy == seqTy.getEleTy()); resTy = fir::SequenceType::get(seqTy.getShape(), newEleTy); } @@ -6161,7 +6167,7 @@ private: if (!eleSz) { // Compute the element size at runtime. assert(fir::hasDynamicSize(eleTy)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { auto charBytes = builder.getKindMap().getCharacterBitsize(charTy.getFKind()) / 8; mlir::Value bytes = @@ -6181,7 +6187,7 @@ private: auto computeCoordinate = [&](mlir::Value buff, mlir::Value off) { mlir::Type refTy = eleRefTy; if (fir::hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { // Scale a simple pointer using dynamic length and offset values. auto chTy = fir::CharacterType::getSingleton(charTy.getContext(), charTy.getFKind()); @@ -6308,7 +6314,7 @@ private: builder.createConvert(loc, idxTy, fir::getBase(asScalar(x.upper()))); mlir::Value step = builder.createConvert(loc, idxTy, fir::getBase(asScalar(x.stride()))); - auto seqTy = resTy.template cast(); + auto seqTy = mlir::cast(resTy); mlir::Type eleTy = fir::unwrapSequenceType(seqTy); auto loop = builder.create(loc, lo, up, step, /*unordered=*/false, @@ -6375,7 +6381,7 @@ private: auto evExpr = toEvExpr(x); mlir::Type resTy = translateSomeExprToFIRType(converter, evExpr); mlir::IndexType idxTy = builder.getIndexType(); - auto seqTy = resTy.template cast(); + auto seqTy = mlir::cast(resTy); mlir::Type eleTy = fir::unwrapSequenceType(resTy); mlir::Value buffSize = builder.createTemporary(loc, idxTy, ".buff.size"); mlir::Value zero = builder.createIntegerConstant(loc, idxTy, 0); @@ -6719,7 +6725,7 @@ private: auto fieldTy = fir::FieldType::get(builder.getContext()); std::string name = converter.getRecordTypeFieldName(getLastSym(*x)); - if (auto recTy = ty.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(ty)) { ty = recTy.getType(name); auto fld = builder.create( loc, fieldTy, name, recTy, fir::getTypeParams(arrayExv)); @@ -6728,7 +6734,7 @@ private: // Need an intermediate dereference if the boxed value // appears in the middle of the component path or if it is // on the right and this is not a pointer assignment. - if (auto boxTy = ty.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(ty)) { auto currentFunc = components.getExtendCoorRef(); auto loc = getLoc(); auto *bldr = &converter.getFirOpBuilder(); @@ -6739,9 +6745,9 @@ private: deref = true; } } - } else if (auto boxTy = ty.dyn_cast()) { + } else if (auto boxTy = mlir::dyn_cast(ty)) { ty = fir::unwrapRefType(boxTy.getEleTy()); - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); ty = recTy.getType(name); auto fld = builder.create( loc, fieldTy, name, recTy, fir::getTypeParams(arrayExv)); @@ -6790,7 +6796,7 @@ private: auto arrayOp = builder.create( loc, eleRefTy, innerArg, iters.iterVec(), fir::factory::getTypeParams(loc, builder, load)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { mlir::Value dstLen = fir::factory::genLenOfCharacter( builder, loc, load, iters.iterVec(), substringBounds); fir::ArrayAmendOp amend = createCharArrayAmend( @@ -6806,13 +6812,13 @@ private: return arrayLoadExtValue(builder, loc, load, iters.iterVec(), amend); } - assert(eleTy.isa()); + assert(mlir::isa(eleTy)); TODO(loc, "array (as element) assignment"); } if (components.hasExtendCoorRef()) { auto eleBoxTy = fir::applyPathToType(innerArg.getType(), iters.iterVec()); - if (!eleBoxTy || !eleBoxTy.isa()) + if (!eleBoxTy || !mlir::isa(eleBoxTy)) TODO(loc, "assignment in a FORALL involving a designator with a " "POINTER or ALLOCATABLE component part-ref"); auto arrayOp = builder.create( @@ -6824,7 +6830,7 @@ private: // assignment, then insert the dereference of the box before any // conversion and store. if (!isPointerAssignment()) { - if (auto boxTy = eleTy.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(eleTy)) { eleTy = fir::boxMemRefType(boxTy); addr = builder.create(loc, eleTy, addr); eleTy = fir::unwrapRefType(eleTy); @@ -6885,7 +6891,7 @@ private: } if (components.hasExtendCoorRef()) { auto eleBoxTy = fir::applyPathToType(load.getType(), iters.iterVec()); - if (!eleBoxTy || !eleBoxTy.isa()) + if (!eleBoxTy || !mlir::isa(eleBoxTy)) TODO(loc, "assignment in a FORALL involving a designator with a " "POINTER or ALLOCATABLE component part-ref"); auto access = builder.create( @@ -6897,7 +6903,7 @@ private: } if (isPointerAssignment()) { auto eleTy = fir::applyPathToType(load.getType(), iters.iterVec()); - if (!eleTy.isa()) { + if (!mlir::isa(eleTy)) { // Rhs is a regular expression that will need to be boxed before // assigning to the boxed variable. auto typeParams = fir::factory::getTypeParams(loc, builder, load); @@ -7615,7 +7621,7 @@ mlir::Value Fortran::lower::addCrayPointerInst(mlir::Location loc, auto box = builder.create(loc, boxTy, ptrVal, empty, empty, emptyRange); mlir::Value addrof = - (ptrTy.isa()) + (mlir::isa(ptrTy)) ? builder.create(loc, ptrTy, box) : builder.create(loc, builder.getRefType(ptrTy), box); diff --git a/flang/lib/Lower/ConvertExprToHLFIR.cpp b/flang/lib/Lower/ConvertExprToHLFIR.cpp index 6e57b31d022b..93bdf650f9ff 100644 --- a/flang/lib/Lower/ConvertExprToHLFIR.cpp +++ b/flang/lib/Lower/ConvertExprToHLFIR.cpp @@ -138,8 +138,8 @@ public: mlir::Location loc = getLoc(); mlir::Type idxTy = builder.getIndexType(); llvm::SmallVector extents; - auto seqTy = hlfir::getFortranElementOrSequenceType(fieldType) - .cast(); + auto seqTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(fieldType)); for (auto extent : seqTy.getShape()) { if (extent == fir::SequenceType::getUnknownExtent()) { // We have already generated invalid hlfir.declare @@ -199,7 +199,7 @@ private: const T &designatorNode) { // Get base's shape if its a sequence type with no previously computed // result shape - if (partInfo.base && resultValueType.isa() && + if (partInfo.base && mlir::isa(resultValueType) && !partInfo.resultShape) partInfo.resultShape = hlfir::genShape(getLoc(), getBuilder(), *partInfo.base); @@ -209,7 +209,7 @@ private: return fir::ClassType::get(resultValueType); // Character scalar with dynamic length needs a fir.boxchar to hold the // designator length. - auto charType = resultValueType.dyn_cast(); + auto charType = mlir::dyn_cast(resultValueType); if (charType && charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); // Arrays with non default lower bounds or dynamic length or dynamic extent @@ -218,7 +218,7 @@ private: hasNonDefaultLowerBounds(partInfo)) return fir::BoxType::get(resultValueType); // Non simply contiguous ref require a fir.box to carry the byte stride. - if (resultValueType.isa() && + if (mlir::isa(resultValueType) && !Fortran::evaluate::IsSimplyContiguous( designatorNode, getConverter().getFoldingContext())) return fir::BoxType::get(resultValueType); @@ -398,8 +398,8 @@ private: partInfo.typeParams[0] = fir::factory::genMaxWithZero(builder, loc, rawLen); } - auto kind = hlfir::getFortranElementType(baseStringType) - .cast() + auto kind = mlir::cast( + hlfir::getFortranElementType(baseStringType)) .getFKind(); auto newCharTy = fir::CharacterType::get( baseStringType.getContext(), kind, @@ -579,7 +579,7 @@ private: return createVectorSubscriptElementAddrOp(partInfo, baseType, resultExtents); - mlir::Type resultType = baseType.cast().getEleTy(); + mlir::Type resultType = mlir::cast(baseType).getEleTy(); if (!resultTypeShape.empty()) { // Ranked array section. The result shape comes from the array section // subscripts. @@ -612,8 +612,8 @@ private: } static bool hasNonDefaultLowerBounds(const PartInfo &partInfo) { return partInfo.resultShape && - (partInfo.resultShape.getType().isa() || - partInfo.resultShape.getType().isa()); + mlir::isa( + partInfo.resultShape.getType()); } mlir::Type visit(const Fortran::evaluate::Component &component, @@ -705,7 +705,7 @@ private: const Fortran::semantics::Symbol &componentSym = component.GetLastSymbol(); partInfo.componentName = converter.getRecordTypeFieldName(componentSym); auto recordType = - hlfir::getFortranElementType(baseType).cast(); + mlir::cast(hlfir::getFortranElementType(baseType)); if (recordType.isDependentType()) TODO(getLoc(), "Designate derived type with length parameters in HLFIR"); mlir::Type fieldType = recordType.getType(partInfo.componentName); @@ -718,7 +718,7 @@ private: if (fir::isRecordWithTypeParameters(fieldEleType)) TODO(loc, "lower a component that is a parameterized derived type to HLFIR"); - if (auto charTy = fieldEleType.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(fieldEleType)) { mlir::Location loc = getLoc(); mlir::Type idxTy = builder.getIndexType(); if (charTy.hasConstantLen()) @@ -811,7 +811,7 @@ private: } } builder.setInsertionPoint(elementalAddrOp); - return baseType.cast().getEleTy(); + return mlir::cast(baseType).getEleTy(); } /// Yield the designator for the final part-ref inside the @@ -1665,7 +1665,7 @@ private: mlir::Location loc = getLoc(); fir::FirOpBuilder &builder = getBuilder(); mlir::Type ty = translateSomeExprToFIRType(converter, toEvExpr(ctor)); - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); if (recTy.isDependentType()) TODO(loc, "structure constructor for derived type with length parameters " diff --git a/flang/lib/Lower/ConvertProcedureDesignator.cpp b/flang/lib/Lower/ConvertProcedureDesignator.cpp index 2446be3a1908..aa0d7ce54788 100644 --- a/flang/lib/Lower/ConvertProcedureDesignator.cpp +++ b/flang/lib/Lower/ConvertProcedureDesignator.cpp @@ -107,11 +107,11 @@ static hlfir::EntityWithAttributes designateProcedurePointerComponent( procComponentSym); /// Passed argument may be a descriptor. This is a scalar reference, so the /// base address can be directly addressed. - if (base.getType().isa()) + if (mlir::isa(base.getType())) base = builder.create(loc, base); std::string fieldName = converter.getRecordTypeFieldName(procComponentSym); auto recordType = - hlfir::getFortranElementType(base.getType()).cast(); + mlir::cast(hlfir::getFortranElementType(base.getType())); mlir::Type fieldType = recordType.getType(fieldName); // Note: semantics turns x%p() into x%t%p() when the procedure pointer // component is part of parent component t. @@ -164,7 +164,7 @@ hlfir::EntityWithAttributes Fortran::lower::convertProcedureDesignatorToHLFIR( fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Value funcAddr = fir::getBase(procExv); - if (!funcAddr.getType().isa()) { + if (!mlir::isa(funcAddr.getType())) { mlir::Type boxTy = Fortran::lower::getUntypedBoxProcType(&converter.getMLIRContext()); if (auto host = Fortran::lower::argumentHostAssocs(converter, funcAddr)) diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index 21db0cac11bf..edf1f24a08e5 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -389,13 +389,13 @@ static mlir::Value genDefaultInitializerValue( fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Type scalarType = symTy; fir::SequenceType sequenceType; - if (auto ty = symTy.dyn_cast()) { + if (auto ty = mlir::dyn_cast(symTy)) { sequenceType = ty; scalarType = ty.getEleTy(); } // Build a scalar default value of the symbol type, looping through the // components to build each component initial value. - auto recTy = scalarType.cast(); + auto recTy = mlir::cast(scalarType); mlir::Value initialValue = builder.create(loc, scalarType); const Fortran::semantics::DeclTypeSpec *declTy = sym.GetType(); assert(declTy && "var with default initialization must have a type"); @@ -493,9 +493,9 @@ static fir::GlobalOp defineGlobal(Fortran::lower::AbstractConverter &converter, // with a tensor mlir type. This optimization currently only supports // Fortran arrays of integer, real, complex, or logical. The tensor // type does not support nested structures. - if (symTy.isa() && + if (mlir::isa(symTy) && !Fortran::semantics::IsAllocatableOrPointer(sym)) { - mlir::Type eleTy = symTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(symTy).getEleTy(); if (eleTy.isa()) { const auto *details = @@ -1292,7 +1292,7 @@ static void finalizeCommonBlockDefinition( fir::GlobalOp global, const Fortran::semantics::MutableSymbolVector &cmnBlkMems) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - mlir::TupleType commonTy = global.getType().cast(); + mlir::TupleType commonTy = mlir::cast(global.getType()); auto initFunc = [&](fir::FirOpBuilder &builder) { mlir::IndexType idxTy = builder.getIndexType(); mlir::Value cb = builder.create(loc, commonTy); @@ -1407,7 +1407,7 @@ static bool lowerToBoxValue(const Fortran::semantics::Symbol &sym, mlir::Value dummyArg, Fortran::lower::AbstractConverter &converter) { // Only dummy arguments coming as fir.box can be tracked in an BoxValue. - if (!dummyArg || !dummyArg.getType().isa()) + if (!dummyArg || !mlir::isa(dummyArg.getType())) return false; // Non contiguous arrays must be tracked in an BoxValue. if (sym.Rank() > 0 && !Fortran::evaluate::IsSimplyContiguous( @@ -1905,7 +1905,7 @@ void Fortran::lower::mapSymbolAttributes( // Do not keep scalar characters as fir.box (even when optional). // Lowering and FIR is not meant to deal with scalar characters as // fir.box outside of calls. - auto boxTy = dummyArg.getType().dyn_cast(); + auto boxTy = mlir::dyn_cast(dummyArg.getType()); mlir::Type refTy = builder.getRefType(boxTy.getEleTy()); mlir::Type lenType = builder.getCharacterLengthType(); mlir::Value addr, len; @@ -1984,8 +1984,8 @@ void Fortran::lower::mapSymbolAttributes( // a non pointer/allocatable symbol to be mapped to a MutableBox. mlir::Type ty = converter.genType(var); bool isPolymorphic = false; - if (auto boxTy = ty.dyn_cast()) { - isPolymorphic = ty.isa(); + if (auto boxTy = mlir::dyn_cast(ty)) { + isPolymorphic = mlir::isa(ty); ty = boxTy.getEleTy(); } Fortran::lower::genDeclareSymbol( @@ -2092,7 +2092,7 @@ void Fortran::lower::mapSymbolAttributes( mlir::Value addr = preAlloc; if (arg) - if (auto boxTy = arg.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(arg.getType())) { // Contiguous assumed shape that can be tracked without a fir.box. mlir::Type refTy = builder.getRefType(boxTy.getEleTy()); addr = builder.create(loc, refTy, arg); @@ -2134,7 +2134,7 @@ void Fortran::lower::mapSymbolAttributes( } else if (!len) { // Assumed length fir.box (possible for contiguous assumed shapes). // Read length from box. - assert(arg && arg.getType().isa() && + assert(arg && mlir::isa(arg.getType()) && "must be character dummy fir.box"); len = charHelp.readLengthFromBox(arg); } diff --git a/flang/lib/Lower/CustomIntrinsicCall.cpp b/flang/lib/Lower/CustomIntrinsicCall.cpp index 439fc3d915b4..30c6ce7f53b3 100644 --- a/flang/lib/Lower/CustomIntrinsicCall.cpp +++ b/flang/lib/Lower/CustomIntrinsicCall.cpp @@ -227,22 +227,23 @@ lowerIshftc(fir::FirOpBuilder &builder, mlir::Location loc, args.push_back(getOperand(1, loadOperand)); auto iPC = isPresentCheck(2); assert(iPC.has_value()); - args.push_back(builder - .genIfOp(loc, {resultType}, *iPC, - /*withElseRegion=*/true) - .genThen([&]() { - fir::ExtendedValue sizeExv = getOperand(2, loadOperand); - mlir::Value size = builder.createConvert( - loc, resultType, fir::getBase(sizeExv)); - builder.create(loc, size); - }) - .genElse([&]() { - mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, - resultType.cast().getWidth()); - builder.create(loc, bitSize); - }) - .getResults()[0]); + args.push_back( + builder + .genIfOp(loc, {resultType}, *iPC, + /*withElseRegion=*/true) + .genThen([&]() { + fir::ExtendedValue sizeExv = getOperand(2, loadOperand); + mlir::Value size = + builder.createConvert(loc, resultType, fir::getBase(sizeExv)); + builder.create(loc, size); + }) + .genElse([&]() { + mlir::Value bitSize = builder.createIntegerConstant( + loc, resultType, + mlir::cast(resultType).getWidth()); + builder.create(loc, bitSize); + }) + .getResults()[0]); return genIntrinsicCall(builder, loc, name, resultType, args, stmtCtx); } @@ -282,7 +283,7 @@ lowerAssociated(fir::FirOpBuilder &builder, mlir::Location loc, builder.create(loc, builder.getI1Type(), targetBase); mlir::Type targetType = fir::unwrapRefType(targetBase.getType()); mlir::Type targetValueType = fir::unwrapPassByRefType(targetType); - mlir::Type boxType = targetType.isa() + mlir::Type boxType = mlir::isa(targetType) ? targetType : fir::BoxType::get(targetValueType); fir::BoxValue targetBox = diff --git a/flang/lib/Lower/DirectivesCommon.h b/flang/lib/Lower/DirectivesCommon.h index 3ebf3fd965da..42bd3868196b 100644 --- a/flang/lib/Lower/DirectivesCommon.h +++ b/flang/lib/Lower/DirectivesCommon.h @@ -642,14 +642,14 @@ getDataOperandBaseAddr(Fortran::lower::AbstractConverter &converter, isPresent = builder.create(loc, builder.getI1Type(), rawInput); - if (auto boxTy = - fir::unwrapRefType(symAddr.getType()).dyn_cast()) { - if (boxTy.getEleTy().isa()) + if (auto boxTy = mlir::dyn_cast( + fir::unwrapRefType(symAddr.getType()))) { + if (mlir::isa(boxTy.getEleTy())) TODO(loc, "derived type"); // Load the box when baseAddr is a `fir.ref>` or a // `fir.ref>` type. - if (symAddr.getType().isa()) { + if (mlir::isa(symAddr.getType())) { if (Fortran::semantics::IsOptional(sym)) { mlir::Value addr = builder.genIfOp(loc, {boxTy}, isPresent, /*withElseRegion=*/true) @@ -722,7 +722,7 @@ genBoundsOpsFromBox(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type idxTy = builder.getIndexType(); mlir::Type boundTy = builder.getType(); - assert(info.addr.getType().isa() && + assert(mlir::isa(info.addr.getType()) && "expect fir.box or fir.class"); if (info.isPresent) { @@ -909,7 +909,8 @@ genBoundsOps(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value stride = one; bool strideInBytes = false; - if (fir::unwrapRefType(info.addr.getType()).isa()) { + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { if (info.isPresent) { stride = builder @@ -1020,8 +1021,8 @@ genBoundsOps(fir::FirOpBuilder &builder, mlir::Location loc, } } - if (info.isPresent && - fir::unwrapRefType(info.addr.getType()).isa()) { + if (info.isPresent && mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { extent = builder .genIfOp(loc, idxTy, info.isPresent, /*withElseRegion=*/true) @@ -1157,7 +1158,7 @@ AddrAndBoundsInfo gatherDataOperandAddrAndBounds( converter.genExprAddr(operandLocation, designator, stmtCtx); info.addr = fir::getBase(compExv); info.rawInput = info.addr; - if (fir::unwrapRefType(info.addr.getType()).isa()) + if (mlir::isa(fir::unwrapRefType(info.addr.getType()))) bounds = genBaseBoundsOps(builder, operandLocation, converter, compExv, /*isAssumedSize=*/false); @@ -1199,13 +1200,14 @@ AddrAndBoundsInfo gatherDataOperandAddrAndBounds( fir::ExtendedValue dataExv = converter.getSymbolExtendedValue(*symRef); info = getDataOperandBaseAddr(converter, builder, *symRef, operandLocation); - if (fir::unwrapRefType(info.addr.getType()).isa()) { + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { bounds = genBoundsOpsFromBox( builder, operandLocation, converter, dataExv, info); } bool dataExvIsAssumedSize = Fortran::semantics::IsAssumedSizeArray(symRef->get().GetUltimate()); - if (fir::unwrapRefType(info.addr.getType()).isa()) + if (mlir::isa(fir::unwrapRefType(info.addr.getType()))) bounds = genBaseBoundsOps( builder, operandLocation, converter, dataExv, dataExvIsAssumedSize); asFortran << symRef->get().name().ToString(); diff --git a/flang/lib/Lower/HlfirIntrinsics.cpp b/flang/lib/Lower/HlfirIntrinsics.cpp index bda04fa9689b..310b62697f71 100644 --- a/flang/lib/Lower/HlfirIntrinsics.cpp +++ b/flang/lib/Lower/HlfirIntrinsics.cpp @@ -265,7 +265,7 @@ HlfirTransformationalIntrinsic::computeResultType(mlir::Value argArray, mlir::Type stmtResultType) { mlir::Type normalisedResult = hlfir::getFortranElementOrSequenceType(stmtResultType); - if (auto array = normalisedResult.dyn_cast()) { + if (auto array = mlir::dyn_cast(normalisedResult)) { hlfir::ExprType::Shape resultShape = hlfir::ExprType::Shape{array.getShape()}; mlir::Type elementType = array.getEleTy(); @@ -341,7 +341,7 @@ mlir::Value HlfirTransposeLowering::lowerImpl( hlfir::ExprType::Shape resultShape; mlir::Type normalisedResult = hlfir::getFortranElementOrSequenceType(stmtResultType); - auto array = normalisedResult.cast(); + auto array = mlir::cast(normalisedResult); llvm::ArrayRef arrayShape = array.getShape(); assert(arrayShape.size() == 2 && "arguments to transpose have a rank of 2"); mlir::Type elementType = array.getEleTy(); diff --git a/flang/lib/Lower/HostAssociations.cpp b/flang/lib/Lower/HostAssociations.cpp index 2e2656356719..75a5bed56655 100644 --- a/flang/lib/Lower/HostAssociations.cpp +++ b/flang/lib/Lower/HostAssociations.cpp @@ -219,7 +219,7 @@ public: static mlir::Type getType(Fortran::lower::AbstractConverter &converter, const Fortran::semantics::Symbol &sym) { fir::KindTy kind = - converter.genType(sym).cast().getFKind(); + mlir::cast(converter.genType(sym)).getFKind(); return fir::BoxCharType::get(&converter.getMLIRContext(), kind); } @@ -293,7 +293,7 @@ public: mlir::Location loc = args.loc; mlir::Value box = args.valueInTuple; if (Fortran::semantics::IsOptional(sym)) { - auto boxTy = box.getType().cast(); + auto boxTy = mlir::cast(box.getType()); auto eleTy = boxTy.getEleTy(); if (!fir::isa_ref_type(eleTy)) eleTy = builder.getRefType(eleTy); @@ -381,8 +381,8 @@ public: const Fortran::semantics::Symbol &sym) { mlir::Type type = converter.genType(sym); bool isPolymorphic = Fortran::semantics::IsPolymorphic(sym); - assert((type.isa() || - (isPolymorphic && type.isa())) && + assert((mlir::isa(type) || + (isPolymorphic && mlir::isa(type))) && "must be a sequence type"); if (isPolymorphic) return type; @@ -459,7 +459,7 @@ public: // (absent boxes are null descriptor addresses, not descriptors containing // a null base address). if (Fortran::semantics::IsOptional(sym)) { - auto boxTy = box.getType().cast(); + auto boxTy = mlir::cast(box.getType()); auto eleTy = boxTy.getEleTy(); if (!fir::isa_ref_type(eleTy)) eleTy = builder.getRefType(eleTy); @@ -527,7 +527,7 @@ walkCaptureCategories(T visitor, Fortran::lower::AbstractConverter &converter, // `t` should be the result of getArgumentType, which has a type of // `!fir.ref>`. static mlir::TupleType unwrapTupleTy(mlir::Type t) { - return fir::dyn_cast_ptrEleTy(t).cast(); + return mlir::cast(fir::dyn_cast_ptrEleTy(t)); } static mlir::Value genTupleCoor(fir::FirOpBuilder &builder, mlir::Location loc, @@ -535,7 +535,7 @@ static mlir::Value genTupleCoor(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value offset) { // fir.ref and fir.ptr are forbidden. Use // fir.llvm_ptr if needed. - auto ty = varTy.isa() + auto ty = mlir::isa(varTy) ? mlir::Type(fir::LLVMPointerType::get(varTy)) : mlir::Type(builder.getRefType(varTy)); return builder.create(loc, ty, tupleArg, offset); diff --git a/flang/lib/Lower/IO.cpp b/flang/lib/Lower/IO.cpp index ac82276bcddb..ed0afad9197d 100644 --- a/flang/lib/Lower/IO.cpp +++ b/flang/lib/Lower/IO.cpp @@ -168,7 +168,7 @@ static constexpr fir::runtime::FuncTypeBuilderFunc getTypeModel() { } inline int64_t getLength(mlir::Type argTy) { - return argTy.cast().getShape()[0]; + return mlir::cast(argTy).getShape()[0]; } /// Get (or generate) the MLIR FuncOp for a given IO runtime function. @@ -656,11 +656,11 @@ static void genNamelistIO(Fortran::lower::AbstractConverter &converter, static mlir::func::FuncOp getOutputFunc(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type type, bool isFormatted) { - if (fir::unwrapPassByRefType(type).isa()) + if (mlir::isa(fir::unwrapPassByRefType(type))) return getIORuntimeFunc(loc, builder); if (!isFormatted) return getIORuntimeFunc(loc, builder); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { switch (ty.getWidth()) { case 1: return getIORuntimeFunc(loc, builder); @@ -677,14 +677,14 @@ static mlir::func::FuncOp getOutputFunc(mlir::Location loc, } llvm_unreachable("unknown OutputInteger kind"); } - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { if (auto width = ty.getWidth(); width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } auto kindMap = fir::getKindMapping(builder.getModule()); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { // COMPLEX(KIND=k) corresponds to a pair of REAL(KIND=k). auto width = kindMap.getRealBitsize(ty.getFKind()); if (width == 32) @@ -692,7 +692,7 @@ static mlir::func::FuncOp getOutputFunc(mlir::Location loc, else if (width == 64) return getIORuntimeFunc(loc, builder); } - if (type.isa()) + if (mlir::isa(type)) return getIORuntimeFunc(loc, builder); if (fir::factory::CharacterExprHelper::isCharacterScalar(type)) { // TODO: What would it mean if the default CHARACTER KIND is set to a wide @@ -731,14 +731,14 @@ static void genOutputItemList( mlir::func::FuncOp outputFunc = getOutputFunc(loc, builder, itemTy, isFormatted); mlir::Type argType = outputFunc.getFunctionType().getInput(1); - assert((isFormatted || argType.isa()) && + assert((isFormatted || mlir::isa(argType)) && "expect descriptor for unformatted IO runtime"); llvm::SmallVector outputFuncArgs = {cookie}; fir::factory::CharacterExprHelper helper{builder, loc}; - if (argType.isa()) { + if (mlir::isa(argType)) { mlir::Value box = fir::getBase(converter.genExprBox(loc, *expr, stmtCtx)); outputFuncArgs.push_back(builder.createConvert(loc, argType, box)); - if (fir::unwrapPassByRefType(itemTy).isa()) + if (mlir::isa(fir::unwrapPassByRefType(itemTy))) outputFuncArgs.push_back(getNonTbpDefinedIoTableAddr(converter)); } else if (helper.isCharacterScalar(itemTy)) { fir::ExtendedValue exv = converter.genExprAddr(loc, expr, stmtCtx); @@ -773,29 +773,29 @@ static void genOutputItemList( static mlir::func::FuncOp getInputFunc(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type type, bool isFormatted) { - if (fir::unwrapPassByRefType(type).isa()) + if (mlir::isa(fir::unwrapPassByRefType(type))) return getIORuntimeFunc(loc, builder); if (!isFormatted) return getIORuntimeFunc(loc, builder); - if (auto ty = type.dyn_cast()) + if (auto ty = mlir::dyn_cast(type)) return ty.getWidth() == 1 ? getIORuntimeFunc(loc, builder) : getIORuntimeFunc(loc, builder); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { if (auto width = ty.getWidth(); width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } auto kindMap = fir::getKindMapping(builder.getModule()); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { auto width = kindMap.getRealBitsize(ty.getFKind()); if (width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } - if (type.isa()) + if (mlir::isa(type)) return getIORuntimeFunc(loc, builder); if (fir::factory::CharacterExprHelper::isCharacterScalar(type)) { auto asciiKind = kindMap.defaultCharacterKind(); @@ -830,12 +830,12 @@ createIoRuntimeCallForItem(Fortran::lower::AbstractConverter &converter, fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Type argType = inputFunc.getFunctionType().getInput(1); llvm::SmallVector inputFuncArgs = {cookie}; - if (argType.isa()) { + if (mlir::isa(argType)) { mlir::Value box = fir::getBase(item); - auto boxTy = box.getType().dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getType()); assert(boxTy && "must be previously emboxed"); inputFuncArgs.push_back(builder.createConvert(loc, argType, box)); - if (fir::unwrapPassByRefType(boxTy).isa()) + if (mlir::isa(fir::unwrapPassByRefType(boxTy))) inputFuncArgs.push_back(getNonTbpDefinedIoTableAddr(converter)); } else { mlir::Value itemAddr = fir::getBase(item); @@ -846,16 +846,16 @@ createIoRuntimeCallForItem(Fortran::lower::AbstractConverter &converter, mlir::Value len = fir::getLen(item); inputFuncArgs.push_back(builder.createConvert( loc, inputFunc.getFunctionType().getInput(2), len)); - } else if (itemTy.isa()) { + } else if (mlir::isa(itemTy)) { inputFuncArgs.push_back(builder.create( loc, builder.getI32IntegerAttr( - itemTy.cast().getWidth() / 8))); + mlir::cast(itemTy).getWidth() / 8))); } } auto call = builder.create(loc, inputFunc, inputFuncArgs); auto itemAddr = fir::getBase(item); auto itemTy = fir::unwrapRefType(itemAddr.getType()); - if (itemTy.isa()) + if (mlir::isa(itemTy)) boolRefToLogical(loc, builder, itemAddr); return call.getResult(0); } @@ -886,7 +886,7 @@ static void genInputItemList(Fortran::lower::AbstractConverter &converter, mlir::func::FuncOp inputFunc = getInputFunc( loc, builder, vectorSubscriptBox.getElementType(), isFormatted); const bool mustBox = - inputFunc.getFunctionType().getInput(1).isa(); + mlir::isa(inputFunc.getFunctionType().getInput(1)); if (!checkResult) { auto elementalGenerator = [&](const fir::ExtendedValue &element) { createIoRuntimeCallForItem(converter, loc, inputFunc, cookie, @@ -911,9 +911,10 @@ static void genInputItemList(Fortran::lower::AbstractConverter &converter, mlir::Type itemTy = converter.genType(*expr); mlir::func::FuncOp inputFunc = getInputFunc(loc, builder, itemTy, isFormatted); - auto itemExv = inputFunc.getFunctionType().getInput(1).isa() - ? converter.genExprBox(loc, *expr, stmtCtx) - : converter.genExprAddr(loc, expr, stmtCtx); + auto itemExv = + mlir::isa(inputFunc.getFunctionType().getInput(1)) + ? converter.genExprBox(loc, *expr, stmtCtx) + : converter.genExprAddr(loc, expr, stmtCtx); ok = createIoRuntimeCallForItem(converter, loc, inputFunc, cookie, itemExv); } } @@ -1772,8 +1773,8 @@ static mlir::Value genIOUnitNumber(Fortran::lower::AbstractConverter &converter, auto &builder = converter.getFirOpBuilder(); auto rawUnit = fir::getBase(converter.genExprValue(loc, iounit, stmtCtx)); unsigned rawUnitWidth = - rawUnit.getType().cast().getWidth(); - unsigned runtimeArgWidth = ty.cast().getWidth(); + mlir::cast(rawUnit.getType()).getWidth(); + unsigned runtimeArgWidth = mlir::cast(ty).getWidth(); // The IO runtime supports `int` unit numbers, if the unit number may // overflow when passed to the IO runtime, check that the unit number is // in range before calling the BeginXXX. @@ -2331,7 +2332,7 @@ mlir::Value genInquireSpec( if (!eleTy) fir::emitFatalError(loc, "internal error: expected a memory reference type"); - auto width = eleTy.cast().getWidth(); + auto width = mlir::cast(eleTy).getWidth(); mlir::IndexType idxTy = builder.getIndexType(); mlir::Value kind = builder.createIntegerConstant(loc, idxTy, width / 8); llvm::SmallVector args = { diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index b56bdedc07bf..eae2afc760e6 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -65,7 +65,7 @@ static Op createDataEntryOp(fir::FirOpBuilder &builder, mlir::Location loc, mlir::acc::DataClause dataClause, mlir::Type retTy, mlir::Value isPresent = {}) { mlir::Value varPtrPtr; - if (auto boxTy = baseAddr.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(baseAddr.getType())) { if (isPresent) { mlir::Type ifRetTy = boxTy.getEleTy(); if (!fir::isa_ref_type(ifRetTy)) @@ -2658,7 +2658,7 @@ genACCHostDataOp(Fortran::lower::AbstractConverter &converter, if (ifCond) { if (auto cst = mlir::dyn_cast(ifCond.getDefiningOp())) - if (auto boolAttr = cst.getValue().dyn_cast()) { + if (auto boolAttr = mlir::dyn_cast(cst.getValue())) { if (boolAttr.getValue()) { // get rid of the if condition if it is always true. ifCond = mlir::Value(); diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 4c51b61f6bf0..79525d6dfe7a 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -23,10 +23,10 @@ namespace omp { /// Check for unsupported map operand types. static void checkMapType(mlir::Location location, mlir::Type type) { - if (auto refType = type.dyn_cast()) + if (auto refType = mlir::dyn_cast(type)) type = refType.getElementType(); - if (auto boxType = type.dyn_cast_or_null()) - if (!boxType.getElementType().isa()) + if (auto boxType = mlir::dyn_cast_or_null(type)) + if (!mlir::isa(boxType.getElementType())) TODO(location, "OMPD_target_data MapOperand BoxType"); } @@ -814,7 +814,7 @@ createMapInfoOp(fir::FirOpBuilder &builder, mlir::Location loc, llvm::ArrayRef members, uint64_t mapType, mlir::omp::VariableCaptureKind mapCaptureType, mlir::Type retTy, bool isVal) { - if (auto boxTy = baseAddr.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(baseAddr.getType())) { baseAddr = builder.create(loc, baseAddr); retTy = baseAddr.getType(); } diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index f454f5a45a51..64ec5ae65c82 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -84,7 +84,7 @@ static fir::GlobalOp globalInitialization( // Create default initialization for non-character scalar. if (Fortran::semantics::IsAllocatableOrObjectPointer(&sym)) { - mlir::Type baseAddrType = ty.dyn_cast().getEleTy(); + mlir::Type baseAddrType = mlir::dyn_cast(ty).getEleTy(); Fortran::lower::createGlobalInitialization( firOpBuilder, global, [&](fir::FirOpBuilder &b) { mlir::Value nullAddr = @@ -778,7 +778,7 @@ static void genBodyOfTargetDataOp( for (auto [argIndex, argSymbol] : llvm::enumerate(useDeviceSymbols)) { const mlir::BlockArgument &arg = region.front().getArgument(argIndex); fir::ExtendedValue extVal = converter.getSymbolExtendedValue(*argSymbol); - if (auto refType = arg.getType().dyn_cast()) { + if (auto refType = mlir::dyn_cast(arg.getType())) { if (fir::isa_builtin_cptr_type(refType.getElementType())) { converter.bindSymbol(*argSymbol, arg); } else { @@ -1570,13 +1570,15 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::AddrAndBoundsInfo info = getDataOperandBaseAddr( converter, firOpBuilder, sym, converter.getCurrentLocation()); - if (fir::unwrapRefType(info.addr.getType()).isa()) + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) bounds = Fortran::lower::genBoundsOpsFromBox( firOpBuilder, converter.getCurrentLocation(), converter, dataExv, info); - if (fir::unwrapRefType(info.addr.getType()).isa()) { + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { bool dataExvIsAssumedSize = Fortran::semantics::IsAssumedSizeArray(sym.GetUltimate()); bounds = Fortran::lower::genBaseBoundsOps()) + if (auto refType = mlir::dyn_cast(baseOp.getType())) eleType = refType.getElementType(); // If a variable is specified in declare target link and if device diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp index 895340549f7c..38edd1b46821 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp @@ -138,7 +138,7 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, TODO(loc, "Reduction of some types is not supported"); switch (redId) { case ReductionIdentifier::MAX: { - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, type, llvm::APFloat::getLargest(sem, /*Negative=*/true)); @@ -148,7 +148,7 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, return builder.createIntegerConstant(loc, type, minInt); } case ReductionIdentifier::MIN: { - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, type, llvm::APFloat::getLargest(sem, /*Negative=*/false)); @@ -188,12 +188,12 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, return fir::factory::Complex{builder, loc}.createComplex(type, initRe, initIm); } - if (type.isa()) + if (mlir::isa(type)) return builder.create( loc, type, builder.getFloatAttr(type, (double)getOperationIdentity(redId, loc))); - if (type.isa()) { + if (mlir::isa(type)) { mlir::Value intConst = builder.create( loc, builder.getI1Type(), builder.getIntegerAttr(builder.getI1Type(), @@ -474,11 +474,11 @@ createReductionCleanupRegion(fir::FirOpBuilder &builder, mlir::Location loc, // like fir::unwrapSeqOrBoxedSeqType except it also works for non-sequence boxes static mlir::Type unwrapSeqOrBoxedType(mlir::Type ty) { - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return seqTy.getEleTy(); - if (auto boxTy = ty.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(ty)) { auto eleTy = fir::unwrapRefType(boxTy.getEleTy()); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); return eleTy; } @@ -790,7 +790,7 @@ void ReductionProcessor::addDeclareReduction( for (mlir::Value symVal : reductionVars) { auto redType = mlir::cast(symVal.getType()); const auto &kindMap = firOpBuilder.getKindMap(); - if (redType.getEleTy().isa()) + if (mlir::isa(redType.getEleTy())) decl = createDeclareReduction(firOpBuilder, getReductionName(intrinsicOp, kindMap, firOpBuilder.getI1Type(), @@ -816,7 +816,7 @@ void ReductionProcessor::addDeclareReduction( mlir::Value symVal = converter.getSymbolAddress(*symbol); if (auto declOp = symVal.getDefiningOp()) symVal = declOp.getBase(); - auto redType = symVal.getType().cast(); + auto redType = mlir::cast(symVal.getType()); if (!redType.getEleTy().isIntOrIndexOrFloat()) TODO(currentLocation, "User Defined Reduction on non-trivial type"); decl = createDeclareReduction( diff --git a/flang/lib/Lower/VectorSubscripts.cpp b/flang/lib/Lower/VectorSubscripts.cpp index 7439b9f7df8f..d7a311d32d59 100644 --- a/flang/lib/Lower/VectorSubscripts.cpp +++ b/flang/lib/Lower/VectorSubscripts.cpp @@ -105,7 +105,7 @@ private: } mlir::Type gen(const Fortran::evaluate::Component &component) { - auto recTy = gen(component.base()).cast(); + auto recTy = mlir::cast(gen(component.base())); const Fortran::semantics::Symbol &componentSymbol = component.GetLastSymbol(); // Parent components will not be found here, they are not part diff --git a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp index c403b9effbfa..f723e8f66e3e 100644 --- a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp +++ b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp @@ -68,7 +68,7 @@ bool AliasAnalysis::Source::isPointerReference(mlir::Type ty) { if (!eleTy) return false; - return fir::isPointerType(eleTy) || eleTy.isa(); + return fir::isPointerType(eleTy) || mlir::isa(eleTy); } bool AliasAnalysis::Source::isTargetOrPointer() const { @@ -81,7 +81,7 @@ bool AliasAnalysis::Source::isRecordWithPointerComponent() const { if (!eleTy) return false; // TO DO: Look for pointer components - return eleTy.isa(); + return mlir::isa(eleTy); } AliasResult AliasAnalysis::alias(Value lhs, Value rhs) { diff --git a/flang/lib/Optimizer/Builder/BoxValue.cpp b/flang/lib/Optimizer/Builder/BoxValue.cpp index 361fa59e2040..a90ce5570de7 100644 --- a/flang/lib/Optimizer/Builder/BoxValue.cpp +++ b/flang/lib/Optimizer/Builder/BoxValue.cpp @@ -191,7 +191,7 @@ bool fir::MutableBoxValue::verify() const { mlir::Type type = fir::dyn_cast_ptrEleTy(getAddr().getType()); if (!type) return false; - auto box = type.dyn_cast(); + auto box = mlir::dyn_cast(type); if (!box) return false; // A boxed value always takes a memory reference, @@ -210,7 +210,7 @@ bool fir::MutableBoxValue::verify() const { /// Debug verifier for BoxValue ctor. There is no guarantee this will /// always be called. bool fir::BoxValue::verify() const { - if (!addr.getType().isa()) + if (!mlir::isa(addr.getType())) return false; if (!lbounds.empty() && lbounds.size() != rank()) return false; diff --git a/flang/lib/Optimizer/Builder/Character.cpp b/flang/lib/Optimizer/Builder/Character.cpp index af0786809cc2..b7a7453efdb3 100644 --- a/flang/lib/Optimizer/Builder/Character.cpp +++ b/flang/lib/Optimizer/Builder/Character.cpp @@ -26,11 +26,11 @@ /// Unwrap all the ref and box types and return the inner element type. static mlir::Type unwrapBoxAndRef(mlir::Type type) { - if (auto boxType = type.dyn_cast()) + if (auto boxType = mlir::dyn_cast(type)) return boxType.getEleTy(); while (true) { type = fir::unwrapRefType(type); - if (auto boxTy = type.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(type)) type = boxTy.getEleTy(); else break; @@ -41,19 +41,19 @@ static mlir::Type unwrapBoxAndRef(mlir::Type type) { /// Unwrap base fir.char type. static fir::CharacterType recoverCharacterType(mlir::Type type) { type = fir::unwrapSequenceType(unwrapBoxAndRef(type)); - if (auto charTy = type.dyn_cast()) + if (auto charTy = mlir::dyn_cast(type)) return charTy; llvm::report_fatal_error("expected a character type"); } bool fir::factory::CharacterExprHelper::isCharacterScalar(mlir::Type type) { type = unwrapBoxAndRef(type); - return !type.isa() && fir::isa_char(type); + return !mlir::isa(type) && fir::isa_char(type); } bool fir::factory::CharacterExprHelper::isArray(mlir::Type type) { type = unwrapBoxAndRef(type); - if (auto seqTy = type.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(type)) return fir::isa_char(seqTy.getEleTy()); return false; } @@ -92,7 +92,8 @@ getCompileTimeLength(const fir::CharBoxValue &box) { /// Detect the precondition that the value `str` does not reside in memory. Such /// values will have a type `!fir.array<...x!fir.char>` or `!fir.char`. LLVM_ATTRIBUTE_UNUSED static bool needToMaterialize(mlir::Value str) { - return str.getType().isa() || fir::isa_char(str.getType()); + return mlir::isa(str.getType()) || + fir::isa_char(str.getType()); } /// This is called only if `str` does not reside in memory. Such a bare string @@ -103,7 +104,7 @@ fir::factory::CharacterExprHelper::materializeValue(mlir::Value str) { assert(needToMaterialize(str)); auto ty = str.getType(); assert(isCharacterScalar(ty) && "expected scalar character"); - auto charTy = ty.dyn_cast(); + auto charTy = mlir::dyn_cast(ty); if (!charTy || charTy.getLen() == fir::CharacterType::unknownLen()) { LLVM_DEBUG(llvm::dbgs() << "cannot materialize: " << str << '\n'); llvm_unreachable("must be a !fir.char type"); @@ -129,7 +130,7 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, if (auto eleType = fir::dyn_cast_ptrEleTy(type)) type = eleType; - if (auto arrayType = type.dyn_cast()) { + if (auto arrayType = mlir::dyn_cast(type)) { type = arrayType.getEleTy(); auto indexType = builder.getIndexType(); for (auto extent : arrayType.getShape()) { @@ -145,10 +146,10 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, mlir::emitError(loc, "cannot retrieve array extents from type"); } - if (auto charTy = type.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(type)) { if (!resultLen && charTy.getLen() != fir::CharacterType::unknownLen()) resultLen = builder.createIntegerConstant(loc, lenType, charTy.getLen()); - } else if (auto boxCharType = type.dyn_cast()) { + } else if (auto boxCharType = mlir::dyn_cast(type)) { auto refType = builder.getRefType(boxCharType.getEleTy()); // If the embox is accessible, use its operand to avoid filling // the generated fir with embox/unbox. @@ -168,7 +169,7 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, if (!resultLen) { resultLen = boxCharLen; } - } else if (type.isa()) { + } else if (mlir::isa(type)) { mlir::emitError(loc, "descriptor or derived type not yet handled"); } else { llvm_unreachable("Cannot translate mlir::Value to character ExtendedValue"); @@ -221,7 +222,7 @@ fir::factory::CharacterExprHelper::createEmbox(const fir::CharBoxValue &box) { fir::CharBoxValue fir::factory::CharacterExprHelper::toScalarCharacter( const fir::CharArrayBoxValue &box) { - if (box.getBuffer().getType().isa()) + if (mlir::isa(box.getBuffer().getType())) TODO(loc, "concatenating non contiguous character array into a scalar"); // TODO: add a fast path multiplying new length at compile time if the info is @@ -655,7 +656,7 @@ fir::factory::CharacterExprHelper::createUnboxChar(mlir::Value boxChar) { } bool fir::factory::CharacterExprHelper::isCharacterLiteral(mlir::Type type) { - if (auto seqType = type.dyn_cast()) + if (auto seqType = mlir::dyn_cast(type)) return (seqType.getShape().size() == 1) && fir::isa_char(seqType.getEleTy()); return false; @@ -728,9 +729,9 @@ mlir::Value fir::factory::CharacterExprHelper::getLength(mlir::Value memref) { if (charType.hasConstantLen()) return builder.createIntegerConstant(loc, builder.getCharacterLengthType(), charType.getLen()); - if (memrefType.isa()) + if (mlir::isa(memrefType)) return readLengthFromBox(memref); - if (memrefType.isa()) + if (mlir::isa(memrefType)) return createUnboxChar(memref).second; // Length cannot be deduced from memref. @@ -742,14 +743,14 @@ fir::factory::extractCharacterProcedureTuple(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value tuple, bool openBoxProc) { - mlir::TupleType tupleType = tuple.getType().cast(); + mlir::TupleType tupleType = mlir::cast(tuple.getType()); mlir::Value addr = builder.create( loc, tupleType.getType(0), tuple, builder.getArrayAttr( {builder.getIntegerAttr(builder.getIndexType(), 0)})); mlir::Value proc = [&]() -> mlir::Value { if (openBoxProc) - if (auto addrTy = addr.getType().dyn_cast()) + if (auto addrTy = mlir::dyn_cast(addr.getType())) return builder.create(loc, addrTy.getEleTy(), addr); return addr; }(); @@ -763,7 +764,7 @@ fir::factory::extractCharacterProcedureTuple(fir::FirOpBuilder &builder, mlir::Value fir::factory::createCharacterProcedureTuple( fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type argTy, mlir::Value addr, mlir::Value len) { - mlir::TupleType tupleType = argTy.cast(); + mlir::TupleType tupleType = mlir::cast(argTy); addr = builder.createConvert(loc, tupleType.getType(0), addr); if (len) len = builder.createConvert(loc, tupleType.getType(1), len); @@ -866,7 +867,7 @@ fir::factory::convertCharacterKind(fir::FirOpBuilder &builder, auto kindMap = builder.getKindMap(); mlir::Value boxCharAddr = srcBoxChar.getAddr(); auto fromTy = boxCharAddr.getType(); - if (auto charTy = fromTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(fromTy)) { // boxchar is a value, not a variable. Turn it into a temporary. // As a value, it ought to have a constant LEN value. assert(charTy.hasConstantLen() && "must have constant length"); @@ -875,7 +876,7 @@ fir::factory::convertCharacterKind(fir::FirOpBuilder &builder, boxCharAddr = tmp; } auto fromBits = kindMap.getCharacterBitsize( - fir::unwrapRefType(fromTy).cast().getFKind()); + mlir::cast(fir::unwrapRefType(fromTy)).getFKind()); auto toBits = kindMap.getCharacterBitsize(toKind); if (toBits < fromBits) { // Scale by relative ratio to give a buffer of the same length. diff --git a/flang/lib/Optimizer/Builder/Complex.cpp b/flang/lib/Optimizer/Builder/Complex.cpp index e97cb3067808..cbcd4f850014 100644 --- a/flang/lib/Optimizer/Builder/Complex.cpp +++ b/flang/lib/Optimizer/Builder/Complex.cpp @@ -14,7 +14,8 @@ mlir::Type fir::factory::Complex::getComplexPartType(mlir::Type complexType) const { - return builder.getRealType(complexType.cast().getFKind()); + return builder.getRealType( + mlir::cast(complexType).getFKind()); } mlir::Type fir::factory::Complex::getComplexPartType(mlir::Value cplx) const { diff --git a/flang/lib/Optimizer/Builder/FIRBuilder.cpp b/flang/lib/Optimizer/Builder/FIRBuilder.cpp index a0fbae5b614c..a6da38763726 100644 --- a/flang/lib/Optimizer/Builder/FIRBuilder.cpp +++ b/flang/lib/Optimizer/Builder/FIRBuilder.cpp @@ -90,7 +90,7 @@ fir::FirOpBuilder::getNamedGlobal(mlir::ModuleOp modOp, } mlir::Type fir::FirOpBuilder::getRefType(mlir::Type eleTy) { - assert(!eleTy.isa() && "cannot be a reference type"); + assert(!mlir::isa(eleTy) && "cannot be a reference type"); return fir::ReferenceType::get(eleTy); } @@ -147,7 +147,7 @@ mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, llvm::APFloat::integerPart val) { auto apf = [&]() -> llvm::APFloat { - if (auto ty = fltTy.dyn_cast()) + if (auto ty = mlir::dyn_cast(fltTy)) return llvm::APFloat(kindMap.getFloatSemantics(ty.getFKind()), val); if (fltTy.isF16()) return llvm::APFloat(llvm::APFloat::IEEEhalf(), val); @@ -169,7 +169,7 @@ fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, const llvm::APFloat &value) { - if (fltTy.isa()) { + if (mlir::isa(fltTy)) { auto attr = getFloatAttr(fltTy, value); return create(loc, fltTy, attr); } @@ -178,7 +178,7 @@ mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, static llvm::SmallVector elideExtentsAlreadyInType(mlir::Type type, mlir::ValueRange shape) { - auto arrTy = type.dyn_cast(); + auto arrTy = mlir::dyn_cast(type); if (shape.empty() || !arrTy) return {}; // elide the constant dimensions before construction @@ -195,7 +195,7 @@ static llvm::SmallVector elideLengthsAlreadyInType(mlir::Type type, mlir::ValueRange lenParams) { if (lenParams.empty()) return {}; - if (auto arrTy = type.dyn_cast()) + if (auto arrTy = mlir::dyn_cast(type)) type = arrTy.getEleTy(); if (fir::hasDynamicSize(type)) return lenParams; @@ -264,7 +264,7 @@ mlir::Value fir::FirOpBuilder::createTemporaryAlloc( mlir::Location loc, mlir::Type type, llvm::StringRef name, mlir::ValueRange lenParams, mlir::ValueRange shape, llvm::ArrayRef attrs) { - assert(!type.isa() && "cannot be a reference"); + assert(!mlir::isa(type) && "cannot be a reference"); // If the alloca is inside an OpenMP Op which will be outlined then pin // the alloca here. const bool pinned = @@ -310,7 +310,7 @@ mlir::Value fir::FirOpBuilder::createHeapTemporary( llvm::SmallVector dynamicLength = elideLengthsAlreadyInType(type, lenParams); - assert(!type.isa() && "cannot be a reference"); + assert(!mlir::isa(type) && "cannot be a reference"); return create(loc, type, /*unique_name=*/llvm::StringRef{}, name, dynamicLength, dynamicShape, attrs); } @@ -376,8 +376,9 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( // imaginary part is zero auto eleTy = helper.getComplexPartType(toTy); auto cast = createConvert(loc, eleTy, val); - llvm::APFloat zero{ - kindMap.getFloatSemantics(toTy.cast().getFKind()), 0}; + llvm::APFloat zero{kindMap.getFloatSemantics( + mlir::cast(toTy).getFKind()), + 0}; auto imag = createRealConstant(loc, eleTy, zero); return helper.createComplex(toTy, cast, imag); } @@ -388,14 +389,14 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( return createConvert(loc, toTy, rp); } if (allowCharacterConversion) { - if (fromTy.isa()) { + if (mlir::isa(fromTy)) { // Extract the address of the character string and pass it fir::factory::CharacterExprHelper charHelper{*this, loc}; std::pair unboxchar = charHelper.createUnboxChar(val); return createConvert(loc, toTy, unboxchar.first); } - if (auto boxType = toTy.dyn_cast()) { + if (auto boxType = mlir::dyn_cast(toTy)) { // Extract the address of the actual argument and create a boxed // character value with an undefined length // TODO: We should really calculate the total size of the actual @@ -415,10 +416,10 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( "element types expected to match")); return create(loc, toTy, val); } - if (fir::isa_ref_type(fromTy) && toTy.isa()) { + if (fir::isa_ref_type(fromTy) && mlir::isa(toTy)) { // Call is expecting a boxed procedure, not a reference to other data type. // Convert the reference to a procedure and embox it. - mlir::Type procTy = toTy.cast().getEleTy(); + mlir::Type procTy = mlir::cast(toTy).getEleTy(); mlir::Value proc = createConvert(loc, procTy, val); return create(loc, toTy, proc); } @@ -428,7 +429,7 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( if (((fir::isPolymorphicType(fromTy) && (fir::isAllocatableType(fromTy) || fir::isPointerType(fromTy)) && fir::isPolymorphicType(toTy)) || - (fir::isPolymorphicType(fromTy) && toTy.isa())) && + (fir::isPolymorphicType(fromTy) && mlir::isa(toTy))) && !(fir::isUnlimitedPolymorphicType(fromTy) && fir::isAssumedType(toTy))) return create(loc, toTy, val, mlir::Value{}, /*slice=*/mlir::Value{}); @@ -581,7 +582,7 @@ mlir::Value fir::FirOpBuilder::createBox(mlir::Location loc, bool isPolymorphic, bool isAssumedType) { mlir::Value itemAddr = fir::getBase(exv); - if (itemAddr.getType().isa()) + if (mlir::isa(itemAddr.getType())) return itemAddr; auto elementType = fir::dyn_cast_ptrEleTy(itemAddr.getType()); if (!elementType) { @@ -592,7 +593,7 @@ mlir::Value fir::FirOpBuilder::createBox(mlir::Location loc, mlir::Type boxTy; mlir::Value tdesc; // Avoid to wrap a box/class with box/class. - if (elementType.isa()) { + if (mlir::isa(elementType)) { boxTy = elementType; } else { boxTy = fir::BoxType::get(elementType); @@ -709,7 +710,7 @@ mlir::Value fir::FirOpBuilder::genAbsentOp(mlir::Location loc, return create(loc, argTy); auto boxProc = - create(loc, argTy.cast().getType(0)); + create(loc, mlir::cast(argTy).getType(0)); mlir::Value charLen = create(loc, getCharacterLengthType()); return fir::factory::createCharacterProcedureTuple(*this, loc, argTy, boxProc, charLen); @@ -958,14 +959,14 @@ static llvm::SmallVector getFromBox(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type valTy, mlir::Value boxVal) { - if (auto boxTy = valTy.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(valTy)) { auto eleTy = fir::unwrapAllRefAndSeqType(boxTy.getEleTy()); - if (auto recTy = eleTy.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(eleTy)) { if (recTy.getNumLenParams() > 0) { // Walk each type parameter in the record and get the value. TODO(loc, "generate code to get LEN type parameters"); } - } else if (auto charTy = eleTy.dyn_cast()) { + } else if (auto charTy = mlir::dyn_cast(eleTy)) { if (charTy.hasDynamicLen()) { auto idxTy = builder.getIndexType(); auto eleSz = builder.create(loc, idxTy, boxVal); @@ -1012,7 +1013,7 @@ llvm::SmallVector fir::factory::getTypeParams(mlir::Location loc, fir::FirOpBuilder &builder, fir::ArrayLoadOp load) { mlir::Type memTy = load.getMemref().getType(); - if (auto boxTy = memTy.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(memTy)) return getFromBox(loc, builder, boxTy, load.getMemref()); return load.getTypeparams(); } @@ -1039,7 +1040,7 @@ std::string fir::factory::uniqueCGIdent(llvm::StringRef prefix, mlir::Value fir::factory::locationToFilename(fir::FirOpBuilder &builder, mlir::Location loc) { - if (auto flc = loc.dyn_cast()) { + if (auto flc = mlir::dyn_cast(loc)) { // must be encoded as asciiz, C string auto fn = flc.getFilename().str() + '\0'; return fir::getBase(createStringLiteral(builder, loc, fn)); @@ -1050,7 +1051,7 @@ mlir::Value fir::factory::locationToFilename(fir::FirOpBuilder &builder, mlir::Value fir::factory::locationToLineNo(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type type) { - if (auto flc = loc.dyn_cast()) + if (auto flc = mlir::dyn_cast(loc)) return builder.createIntegerConstant(loc, type, flc.getLine()); return builder.createIntegerConstant(loc, type, 0); } @@ -1108,10 +1109,10 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( auto fieldTy = component.getType(); if (auto ty = fir::dyn_cast_ptrEleTy(fieldTy)) fieldTy = ty; - if (fieldTy.isa()) { + if (mlir::isa(fieldTy)) { llvm::SmallVector nonDeferredTypeParams; auto eleTy = fir::unwrapSequenceType(fir::dyn_cast_ptrOrBoxEleTy(fieldTy)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { auto lenTy = builder.getCharacterLengthType(); if (charTy.hasConstantLen()) nonDeferredTypeParams.emplace_back( @@ -1120,7 +1121,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( // on a PDT length parameter. There is no way to make a difference with // deferred length here yet. } - if (auto recTy = eleTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(eleTy)) if (recTy.getNumLenParams() > 0) TODO(loc, "allocatable and pointer components non deferred length " "parameters"); @@ -1129,7 +1130,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( /*mutableProperties=*/{}); } llvm::SmallVector extents; - if (auto seqTy = fieldTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(fieldTy)) { fieldTy = seqTy.getEleTy(); auto idxTy = builder.getIndexType(); for (auto extent : seqTy.getShape()) { @@ -1138,7 +1139,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( extents.emplace_back(builder.createIntegerConstant(loc, idxTy, extent)); } } - if (auto charTy = fieldTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(fieldTy)) { auto cstLen = charTy.getLen(); if (cstLen == fir::CharacterType::unknownLen()) TODO(loc, "get character component length from length type parameters"); @@ -1148,7 +1149,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( return fir::CharArrayBoxValue{component, len, extents}; return fir::CharBoxValue{component, len}; } - if (auto recordTy = fieldTy.dyn_cast()) + if (auto recordTy = mlir::dyn_cast(fieldTy)) if (recordTy.getNumLenParams() != 0) TODO(loc, "lower component ref that is a derived type with length parameter"); @@ -1211,14 +1212,14 @@ void fir::factory::genScalarAssignment(fir::FirOpBuilder &builder, assert(lhs.rank() == 0 && rhs.rank() == 0 && "must be scalars"); auto type = fir::unwrapSequenceType( fir::unwrapPassByRefType(fir::getBase(lhs).getType())); - if (type.isa()) { + if (mlir::isa(type)) { const fir::CharBoxValue *toChar = lhs.getCharBox(); const fir::CharBoxValue *fromChar = rhs.getCharBox(); assert(toChar && fromChar); fir::factory::CharacterExprHelper helper{builder, loc}; helper.createAssign(fir::ExtendedValue{*toChar}, fir::ExtendedValue{*fromChar}); - } else if (type.isa()) { + } else if (mlir::isa(type)) { fir::factory::genRecordAssignment(builder, loc, lhs, rhs, needFinalization, isTemporaryLHS); } else { @@ -1239,10 +1240,10 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, const fir::ExtendedValue &rhs, bool isTemporaryLHS) { auto lbaseType = fir::unwrapPassByRefType(fir::getBase(lhs).getType()); - auto lhsType = lbaseType.dyn_cast(); + auto lhsType = mlir::dyn_cast(lbaseType); assert(lhsType && "lhs must be a scalar record type"); auto rbaseType = fir::unwrapPassByRefType(fir::getBase(rhs).getType()); - auto rhsType = rbaseType.dyn_cast(); + auto rhsType = mlir::dyn_cast(rbaseType); assert(rhsType && "rhs must be a scalar record type"); auto fieldIndexType = fir::FieldType::get(lhsType.getContext()); for (auto [lhsPair, rhsPair] : @@ -1261,7 +1262,7 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, mlir::Value toCoor = builder.create( loc, fieldRefType, fir::getBase(lhs), field); std::optional outerLoop; - if (auto sequenceType = lFieldTy.dyn_cast()) { + if (auto sequenceType = mlir::dyn_cast(lFieldTy)) { // Create loops to assign array components elements by elements. // Note that, since these are components, they either do not overlap, // or are the same and exactly overlap. They also have compile time @@ -1288,10 +1289,9 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, fromCoor, indices); } if (auto fieldEleTy = fir::unwrapSequenceType(lFieldTy); - fieldEleTy.isa()) { - assert(fieldEleTy.cast() - .getEleTy() - .isa() && + mlir::isa(fieldEleTy)) { + assert(mlir::isa( + mlir::cast(fieldEleTy).getEleTy()) && "allocatable members require deep copy"); auto fromPointerValue = builder.create(loc, fromCoor); auto castTo = builder.createConvert(loc, fieldEleTy, fromPointerValue); @@ -1320,11 +1320,11 @@ static bool recordTypeCanBeMemCopied(fir::RecordType recordType) { for (auto [_, fieldType] : recordType.getTypeList()) { // Derived type component may have user assignment (so far, we cannot tell // in FIR, so assume it is always the case, TODO: get the actual info). - if (fir::unwrapSequenceType(fieldType).isa()) + if (mlir::isa(fir::unwrapSequenceType(fieldType))) return false; // Allocatable components need deep copy. - if (auto boxType = fieldType.dyn_cast()) - if (boxType.getEleTy().isa()) + if (auto boxType = mlir::dyn_cast(fieldType)) + if (mlir::isa(boxType.getEleTy())) return false; } // Constant size components without user defined assignment and pointers can @@ -1353,9 +1353,10 @@ void fir::factory::genRecordAssignment(fir::FirOpBuilder &builder, // Box operands may be polymorphic, it is not entirely clear from 10.2.1.3 // if the assignment is performed on the dynamic of declared type. Use the // runtime assuming it is performed on the dynamic type. - bool hasBoxOperands = fir::getBase(lhs).getType().isa() || - fir::getBase(rhs).getType().isa(); - auto recTy = baseTy.dyn_cast(); + bool hasBoxOperands = + mlir::isa(fir::getBase(lhs).getType()) || + mlir::isa(fir::getBase(rhs).getType()); + auto recTy = mlir::dyn_cast(baseTy); assert(recTy && "must be a record type"); if ((needFinalization && mayHaveFinalizer(recTy, builder)) || hasBoxOperands || !recordTypeCanBeMemCopied(recTy)) { @@ -1401,7 +1402,7 @@ mlir::Value fir::factory::genLenOfCharacter( llvm::ArrayRef path, llvm::ArrayRef substring) { llvm::SmallVector typeParams(arrLoad.getTypeparams()); return genLenOfCharacter(builder, loc, - arrLoad.getType().cast(), + mlir::cast(arrLoad.getType()), arrLoad.getMemref(), typeParams, path, substring); } @@ -1429,7 +1430,7 @@ mlir::Value fir::factory::genLenOfCharacter( lower = builder.createConvert(loc, idxTy, substring.front()); auto eleTy = fir::applyPathToType(seqTy, path); if (!fir::hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { // Use LEN from the type. return builder.createIntegerConstant(loc, idxTy, charTy.getLen()); } @@ -1438,9 +1439,9 @@ mlir::Value fir::factory::genLenOfCharacter( "application of path did not result in a !fir.char"); } if (fir::isa_box_type(memref.getType())) { - if (memref.getType().isa()) + if (mlir::isa(memref.getType())) return builder.create(loc, idxTy, memref); - if (memref.getType().isa()) + if (mlir::isa(memref.getType())) return CharacterExprHelper(builder, loc).readLengthFromBox(memref); fir::emitFatalError(loc, "memref has wrong type"); } @@ -1457,7 +1458,7 @@ mlir::Value fir::factory::genLenOfCharacter( mlir::Value fir::factory::createZeroValue(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type type) { mlir::Type i1 = builder.getIntegerType(1); - if (type.isa() || type == i1) + if (mlir::isa(type) || type == i1) return builder.createConvert(loc, type, builder.createBool(loc, false)); if (fir::isa_integer(type)) return builder.createIntegerConstant(loc, type, 0); @@ -1507,7 +1508,7 @@ mlir::Value fir::factory::genMaxWithZero(fir::FirOpBuilder &builder, mlir::Value zero = builder.createIntegerConstant(loc, value.getType(), 0); if (mlir::Operation *definingOp = value.getDefiningOp()) if (auto cst = mlir::dyn_cast(definingOp)) - if (auto intAttr = cst.getValue().dyn_cast()) + if (auto intAttr = mlir::dyn_cast(cst.getValue())) return intAttr.getInt() > 0 ? value : zero; mlir::Value valueIsGreater = builder.create( loc, mlir::arith::CmpIPredicate::sgt, value, zero); @@ -1519,8 +1520,8 @@ mlir::Value fir::factory::genCPtrOrCFunptrAddr(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value cPtr, mlir::Type ty) { - assert(ty.isa()); - auto recTy = ty.dyn_cast(); + assert(mlir::isa(ty)); + auto recTy = mlir::dyn_cast(ty); assert(recTy.getTypeList().size() == 1); auto fieldName = recTy.getTypeList()[0].first; mlir::Type fieldTy = recTy.getTypeList()[0].second; @@ -1582,7 +1583,7 @@ mlir::Value fir::factory::genCPtrOrCFunptrValue(fir::FirOpBuilder &builder, mlir::Value fir::factory::createNullBoxProc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type boxType) { - auto boxTy{boxType.dyn_cast()}; + auto boxTy{mlir::dyn_cast(boxType)}; if (!boxTy) fir::emitFatalError(loc, "Procedure pointer must be of BoxProcType"); auto boxEleTy{fir::unwrapRefType(boxTy.getEleTy())}; diff --git a/flang/lib/Optimizer/Builder/HLFIRTools.cpp b/flang/lib/Optimizer/Builder/HLFIRTools.cpp index db638ceb4070..44779427ab55 100644 --- a/flang/lib/Optimizer/Builder/HLFIRTools.cpp +++ b/flang/lib/Optimizer/Builder/HLFIRTools.cpp @@ -38,10 +38,10 @@ hlfir::getExplicitExtentsFromShape(mlir::Value shape, } else if (mlir::dyn_cast_or_null(shapeOp)) { return {}; } else if (auto s = mlir::dyn_cast_or_null(shapeOp)) { - hlfir::ExprType expr = s.getExpr().getType().cast(); + hlfir::ExprType expr = mlir::cast(s.getExpr().getType()); llvm::ArrayRef exprShape = expr.getShape(); mlir::Type indexTy = builder.getIndexType(); - fir::ShapeType shapeTy = shape.getType().cast(); + fir::ShapeType shapeTy = mlir::cast(shape.getType()); result.reserve(shapeTy.getRank()); for (unsigned i = 0; i < shapeTy.getRank(); ++i) { int64_t extent = exprShape[i]; @@ -99,7 +99,7 @@ genLboundsAndExtentsFromBox(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity boxEntity, llvm::SmallVectorImpl &lbounds, llvm::SmallVectorImpl *extents) { - assert(boxEntity.getType().isa() && "must be a box"); + assert(mlir::isa(boxEntity.getType()) && "must be a box"); mlir::Type idxTy = builder.getIndexType(); const int rank = boxEntity.getRank(); for (int i = 0; i < rank; ++i) { @@ -154,7 +154,7 @@ static mlir::Value genCharacterVariableLength(mlir::Location loc, hlfir::Entity var) { if (mlir::Value len = tryGettingNonDeferredCharLen(var)) return len; - auto charType = var.getFortranElementType().cast(); + auto charType = mlir::cast(var.getFortranElementType()); if (charType.hasConstantLen()) return builder.createIntegerConstant(loc, builder.getIndexType(), charType.getLen()); @@ -172,7 +172,7 @@ static fir::CharBoxValue genUnboxChar(mlir::Location loc, if (auto emboxChar = boxChar.getDefiningOp()) return {emboxChar.getMemref(), emboxChar.getLen()}; mlir::Type refType = fir::ReferenceType::get( - boxChar.getType().cast().getEleTy()); + mlir::cast(boxChar.getType()).getEleTy()); auto unboxed = builder.create( loc, refType, builder.getIndexType(), boxChar); mlir::Value addr = unboxed.getResult(0); @@ -252,8 +252,8 @@ hlfir::genAssociateExpr(mlir::Location loc, fir::FirOpBuilder &builder, // and the other static). mlir::Type varEleTy = getFortranElementType(variableType); mlir::Type valueEleTy = getFortranElementType(value.getType()); - if (varEleTy != valueEleTy && !(valueEleTy.isa() && - varEleTy.isa())) { + if (varEleTy != valueEleTy && !(mlir::isa(valueEleTy) && + mlir::isa(varEleTy))) { assert(value.isScalar() && fir::isa_trivial(value.getType())); source = builder.createConvert(loc, fir::unwrapPassByRefType(variableType), value); @@ -278,9 +278,9 @@ mlir::Value hlfir::genVariableRawAddress(mlir::Location loc, if (var.isMutableBox()) baseAddr = builder.create(loc, baseAddr); // Get raw address. - if (var.getType().isa()) + if (mlir::isa(var.getType())) baseAddr = genUnboxChar(loc, builder, var.getBase()).getAddr(); - if (baseAddr.getType().isa()) + if (mlir::isa(baseAddr.getType())) baseAddr = builder.create(loc, baseAddr); return baseAddr; } @@ -289,13 +289,13 @@ mlir::Value hlfir::genVariableBoxChar(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity var) { assert(var.isVariable() && "only address of variables can be taken"); - if (var.getType().isa()) + if (mlir::isa(var.getType())) return var; mlir::Value addr = genVariableRawAddress(loc, builder, var); llvm::SmallVector lengths; genLengthParameters(loc, builder, var, lengths); assert(lengths.size() == 1); - auto charType = var.getFortranElementType().cast(); + auto charType = mlir::cast(var.getFortranElementType()); auto boxCharType = fir::BoxCharType::get(builder.getContext(), charType.getFKind()); auto scalarAddr = @@ -309,7 +309,7 @@ hlfir::Entity hlfir::genVariableBox(mlir::Location loc, hlfir::Entity var) { assert(var.isVariable() && "must be a variable"); var = hlfir::derefPointersAndAllocatables(loc, builder, var); - if (var.getType().isa()) + if (mlir::isa(var.getType())) return var; // Note: if the var is not a fir.box/fir.class at that point, it has default // lower bounds and is not polymorphic. @@ -317,11 +317,11 @@ hlfir::Entity hlfir::genVariableBox(mlir::Location loc, var.isArray() ? hlfir::genShape(loc, builder, var) : mlir::Value{}; llvm::SmallVector typeParams; auto maybeCharType = - var.getFortranElementType().dyn_cast(); + mlir::dyn_cast(var.getFortranElementType()); if (!maybeCharType || maybeCharType.hasDynamicLen()) hlfir::genLengthParameters(loc, builder, var, typeParams); mlir::Value addr = var.getBase(); - if (var.getType().isa()) + if (mlir::isa(var.getType())) addr = genVariableRawAddress(loc, builder, var); mlir::Type boxType = fir::BoxType::get(var.getElementOrSequenceType()); auto embox = @@ -348,7 +348,7 @@ hlfir::Entity hlfir::getElementAt(mlir::Location loc, return entity; llvm::SmallVector lenParams; genLengthParameters(loc, builder, entity, lenParams); - if (entity.getType().isa()) + if (mlir::isa(entity.getType())) return hlfir::Entity{builder.create( loc, entity, oneBasedIndices, lenParams)}; // Build hlfir.designate. The lower bounds may need to be added to @@ -394,7 +394,7 @@ static mlir::Value genUBound(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVector> hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, Entity entity) { - if (entity.getType().isa()) + if (mlir::isa(entity.getType())) TODO(loc, "bounds of expressions in hlfir"); auto [exv, cleanup] = translateToExtendedValue(loc, builder, entity); assert(!cleanup && "translation of entity should not yield cleanup"); @@ -415,8 +415,8 @@ hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVector> hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value shape) { - assert((shape.getType().isa() || - shape.getType().isa()) && + assert((mlir::isa(shape.getType()) || + mlir::isa(shape.getType())) && "shape must contain extents"); auto extents = hlfir::getExplicitExtentsFromShape(shape, builder); auto lowers = getExplicitLboundsFromShape(shape); @@ -474,7 +474,7 @@ static mlir::Value computeVariableExtent(mlir::Location loc, if (typeExtent != fir::SequenceType::getUnknownExtent()) return builder.createIntegerConstant(loc, idxTy, typeExtent); } - assert(variable.getType().isa() && + assert(mlir::isa(variable.getType()) && "array variable with dynamic extent must be boxed"); mlir::Value dimVal = builder.createIntegerConstant(loc, idxTy, dim); auto dimInfo = builder.create(loc, idxTy, idxTy, idxTy, @@ -496,9 +496,8 @@ llvm::SmallVector getVariableExtents(mlir::Location loc, variable = hlfir::derefPointersAndAllocatables(loc, builder, variable); // Use the type shape information, and/or the fir.box/fir.class shape // information if any extents are not static. - fir::SequenceType seqTy = - hlfir::getFortranElementOrSequenceType(variable.getType()) - .cast(); + fir::SequenceType seqTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(variable.getType())); unsigned rank = seqTy.getShape().size(); for (unsigned dim = 0; dim < rank; ++dim) extents.push_back( @@ -507,7 +506,7 @@ llvm::SmallVector getVariableExtents(mlir::Location loc, } static mlir::Value tryRetrievingShapeOrShift(hlfir::Entity entity) { - if (entity.getType().isa()) { + if (mlir::isa(entity.getType())) { if (auto elemental = entity.getDefiningOp()) return elemental.getShape(); return mlir::Value{}; @@ -523,13 +522,13 @@ mlir::Value hlfir::genShape(mlir::Location loc, fir::FirOpBuilder &builder, entity = followShapeInducingSource(entity); assert(entity && "what?"); if (auto shape = tryRetrievingShapeOrShift(entity)) { - if (shape.getType().isa()) + if (mlir::isa(shape.getType())) return shape; - if (shape.getType().isa()) + if (mlir::isa(shape.getType())) if (auto s = shape.getDefiningOp()) return builder.create(loc, s.getExtents()); } - if (entity.getType().isa()) + if (mlir::isa(entity.getType())) return builder.create(loc, entity.getBase()); // There is no shape lying around for this entity. Retrieve the extents and // build a new fir.shape. @@ -563,9 +562,8 @@ mlir::Value hlfir::genExtent(mlir::Location loc, fir::FirOpBuilder &builder, entity = hlfir::derefPointersAndAllocatables(loc, builder, entity); // Use the type shape information, and/or the fir.box/fir.class shape // information if any extents are not static. - fir::SequenceType seqTy = - hlfir::getFortranElementOrSequenceType(entity.getType()) - .cast(); + fir::SequenceType seqTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(entity.getType())); return computeVariableExtent(loc, builder, entity, seqTy, dim); } TODO(loc, "get extent from HLFIR expr without producer holding the shape"); @@ -584,7 +582,7 @@ mlir::Value hlfir::genLBound(mlir::Location loc, fir::FirOpBuilder &builder, } if (entity.isMutableBox()) entity = hlfir::derefPointersAndAllocatables(loc, builder, entity); - assert(entity.getType().isa() && "must be a box"); + assert(mlir::isa(entity.getType()) && "must be a box"); mlir::Type idxTy = builder.getIndexType(); mlir::Value dimVal = builder.createIntegerConstant(loc, idxTy, dim); auto dimInfo = @@ -597,7 +595,7 @@ void hlfir::genLengthParameters(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVectorImpl &result) { if (!entity.hasLengthParameters()) return; - if (entity.getType().isa()) { + if (mlir::isa(entity.getType())) { mlir::Value expr = entity; if (auto reassoc = expr.getDefiningOp()) expr = reassoc.getVal(); @@ -654,8 +652,8 @@ static mlir::Value asEmboxShape(mlir::Location loc, fir::FirOpBuilder &builder, // fir.shape_shift) since this information is already in the input fir.box, // it only accepts fir.shift because local lower bounds may not be reflected // in the fir.box. - if (fir::getBase(exv).getType().isa() && - !shape.getType().isa()) + if (mlir::isa(fir::getBase(exv).getType()) && + !mlir::isa(shape.getType())) return builder.createShape(loc, exv); return shape; } @@ -686,7 +684,7 @@ hlfir::Entity hlfir::derefPointersAndAllocatables(mlir::Location loc, if (!entity.isPolymorphic() && !entity.hasLengthParameters()) return hlfir::Entity{builder.create(loc, boxLoad)}; mlir::Type elementType = boxLoad.getFortranElementType(); - if (auto charType = elementType.dyn_cast()) { + if (auto charType = mlir::dyn_cast(elementType)) { mlir::Value base = builder.create(loc, boxLoad); if (charType.hasConstantLen()) return hlfir::Entity{base}; @@ -716,7 +714,7 @@ mlir::Type hlfir::getVariableElementType(hlfir::Entity variable) { mlir::Type eleTy = variable.getFortranElementType(); if (variable.isPolymorphic()) return fir::ClassType::get(eleTy); - if (auto charType = eleTy.dyn_cast()) { + if (auto charType = mlir::dyn_cast(eleTy)) { if (charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); } else if (fir::isRecordWithTypeParameters(eleTy)) { @@ -737,7 +735,7 @@ mlir::Type hlfir::getEntityElementType(hlfir::Entity entity) { static hlfir::ExprType getArrayExprType(mlir::Type elementType, mlir::Value shape, bool isPolymorphic) { - unsigned rank = shape.getType().cast().getRank(); + unsigned rank = mlir::cast(shape.getType()).getRank(); hlfir::ExprType::Shape typeShape(rank, hlfir::ExprType::getUnknownExtent()); if (auto shapeOp = shape.getDefiningOp()) for (auto extent : llvm::enumerate(shapeOp.getExtents())) @@ -859,7 +857,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, return fir::MutableBoxValue(base, getExplicitTypeParams(variable), fir::MutableProperties{}); - if (base.getType().isa()) { + if (mlir::isa(base.getType())) { if (!variable.isSimplyContiguous() || variable.isPolymorphic() || variable.isDerivedWithLengthParameters() || variable.isOptional()) { llvm::SmallVector nonDefaultLbounds = @@ -874,7 +872,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, if (variable.isScalar()) { if (variable.isCharacter()) { - if (base.getType().isa()) + if (mlir::isa(base.getType())) return genUnboxChar(loc, builder, base); mlir::Value len = genCharacterVariableLength(loc, builder, variable); return fir::CharBoxValue{base, len}; @@ -883,7 +881,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, } llvm::SmallVector extents; llvm::SmallVector nonDefaultLbounds; - if (variable.getType().isa() && + if (mlir::isa(variable.getType()) && !variable.getIfVariableInterface()) { // This special case avoids generating two sets of identical // fir.box_dim to get both the lower bounds and extents. @@ -923,7 +921,7 @@ hlfir::translateToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, return {static_cast(entity), std::nullopt}; } - if (entity.getType().isa()) { + if (mlir::isa(entity.getType())) { mlir::NamedAttribute byRefAttr = fir::getAdaptToByRefAttr(builder); hlfir::AssociateOp associate = hlfir::genAssociateExpr( loc, builder, entity, entity.getType(), "", byRefAttr); diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index e28d14cd318d..9d72e76e2369 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -786,7 +786,7 @@ mlir::Value genLibSplitComplexArgsCall(fir::FirOpBuilder &builder, auto getSplitComplexArgsType = [&builder, &args]() -> mlir::FunctionType { mlir::Type ctype = args[0].getType(); - auto fKind = ctype.cast().getFKind(); + auto fKind = mlir::cast(ctype).getFKind(); mlir::Type ftype; if (fKind == 2) @@ -894,8 +894,8 @@ mlir::Value genComplexMathOp(fir::FirOpBuilder &builder, mlir::Location loc, LLVM_DEBUG(llvm::dbgs() << "Generating '" << mathLibFuncName << "' operation with type "; mathLibFuncType.dump(); llvm::dbgs() << "\n"); - auto type = mathLibFuncType.getInput(0).cast(); - auto kind = type.getElementType().cast().getFKind(); + auto type = mlir::cast(mathLibFuncType.getInput(0)); + auto kind = mlir::cast(type.getElementType()).getFKind(); auto realTy = builder.getRealType(kind); auto mComplexTy = mlir::ComplexType::get(realTy); @@ -1394,14 +1394,14 @@ private: // Floating point can be mlir::FloatType or fir::real static unsigned getFloatingPointWidth(mlir::Type t) { - if (auto f{t.dyn_cast()}) + if (auto f{mlir::dyn_cast(t)}) return f.getWidth(); // FIXME: Get width another way for fir.real/complex // - use fir/KindMapping.h and llvm::Type // - or use evaluate/type.h - if (auto r{t.dyn_cast()}) + if (auto r{mlir::dyn_cast(t)}) return r.getFKind() * 4; - if (auto cplx{t.dyn_cast()}) + if (auto cplx{mlir::dyn_cast(t)}) return cplx.getFKind() * 4; llvm_unreachable("not a floating-point type"); } @@ -1410,8 +1410,8 @@ private: if (from == to) return Conversion::None; - if (auto fromIntTy{from.dyn_cast()}) { - if (auto toIntTy{to.dyn_cast()}) { + if (auto fromIntTy{mlir::dyn_cast(from)}) { + if (auto toIntTy{mlir::dyn_cast(to)}) { return fromIntTy.getWidth() > toIntTy.getWidth() ? Conversion::Narrow : Conversion::Extend; } @@ -1423,8 +1423,8 @@ private: : Conversion::Extend; } - if (auto fromCplxTy{from.dyn_cast()}) { - if (auto toCplxTy{to.dyn_cast()}) { + if (auto fromCplxTy{mlir::dyn_cast(from)}) { + if (auto toCplxTy{mlir::dyn_cast(to)}) { return getFloatingPointWidth(fromCplxTy) > getFloatingPointWidth(toCplxTy) ? Conversion::Narrow @@ -1550,10 +1550,10 @@ fir::ExtendedValue toExtendedValue(mlir::Value val, fir::FirOpBuilder &builder, if (charHelper.isCharacterScalar(type)) return charHelper.toExtendedValue(val); - if (auto refType = type.dyn_cast()) + if (auto refType = mlir::dyn_cast(type)) type = refType.getEleTy(); - if (auto arrayType = type.dyn_cast()) { + if (auto arrayType = mlir::dyn_cast(type)) { type = arrayType.getEleTy(); for (fir::SequenceType::Extent extent : arrayType.getShape()) { if (extent == fir::SequenceType::getUnknownExtent()) @@ -1566,7 +1566,8 @@ fir::ExtendedValue toExtendedValue(mlir::Value val, fir::FirOpBuilder &builder, // have been used in the interface). if (extents.size() + 1 < arrayType.getShape().size()) mlir::emitError(loc, "cannot retrieve array extents from type"); - } else if (type.isa() || type.isa()) { + } else if (mlir::isa(type) || + mlir::isa(type)) { fir::emitFatalError(loc, "not yet implemented: descriptor or derived type"); } @@ -1580,10 +1581,10 @@ mlir::Value toValue(const fir::ExtendedValue &val, fir::FirOpBuilder &builder, if (const fir::CharBoxValue *charBox = val.getCharBox()) { mlir::Value buffer = charBox->getBuffer(); auto buffTy = buffer.getType(); - if (buffTy.isa()) + if (mlir::isa(buffTy)) fir::emitFatalError( loc, "A character's buffer type cannot be a function type."); - if (buffTy.isa()) + if (mlir::isa(buffTy)) return buffer; return fir::factory::CharacterExprHelper{builder, loc}.createEmboxChar( buffer, charBox->getLen()); @@ -1827,27 +1828,27 @@ IntrinsicLibrary::invokeGenerator(SubroutineGenerator generator, /// Note: mlir has Type::dump(ostream) methods but it may add "!" that is not /// suitable for function names. static std::string typeToString(mlir::Type t) { - if (auto refT{t.dyn_cast()}) + if (auto refT{mlir::dyn_cast(t)}) return "ref_" + typeToString(refT.getEleTy()); - if (auto i{t.dyn_cast()}) { + if (auto i{mlir::dyn_cast(t)}) { return "i" + std::to_string(i.getWidth()); } - if (auto cplx{t.dyn_cast()}) { + if (auto cplx{mlir::dyn_cast(t)}) { return "z" + std::to_string(cplx.getFKind()); } - if (auto real{t.dyn_cast()}) { + if (auto real{mlir::dyn_cast(t)}) { return "r" + std::to_string(real.getFKind()); } - if (auto f{t.dyn_cast()}) { + if (auto f{mlir::dyn_cast(t)}) { return "f" + std::to_string(f.getWidth()); } - if (auto logical{t.dyn_cast()}) { + if (auto logical{mlir::dyn_cast(t)}) { return "l" + std::to_string(logical.getFKind()); } - if (auto character{t.dyn_cast()}) { + if (auto character{mlir::dyn_cast(t)}) { return "c" + std::to_string(character.getFKind()); } - if (auto boxCharacter{t.dyn_cast()}) { + if (auto boxCharacter{mlir::dyn_cast(t)}) { return "bc" + std::to_string(boxCharacter.getEleTy().getFKind()); } llvm_unreachable("no mangling for type"); @@ -1907,7 +1908,7 @@ mlir::func::FuncOp IntrinsicLibrary::getWrapper(GeneratorType generator, mlir::Location localLoc = localBuilder->getUnknownLoc(); llvm::SmallVector localArguments; for (mlir::BlockArgument bArg : function.front().getArguments()) { - auto refType = bArg.getType().dyn_cast(); + auto refType = mlir::dyn_cast(bArg.getType()); if (loadRefArguments && refType) { auto loaded = localBuilder->create(localLoc, bArg); localArguments.push_back(loaded); @@ -2060,7 +2061,7 @@ mlir::SymbolRefAttr IntrinsicLibrary::getUnrestrictedIntrinsicSymbolRefAttr( if (!funcOp) { llvm::SmallVector argTypes; for (mlir::Type type : signature.getInputs()) { - if (auto refType = type.dyn_cast()) + if (auto refType = mlir::dyn_cast(type)) argTypes.push_back(refType.getEleTy()); else argTypes.push_back(type); @@ -2145,7 +2146,7 @@ mlir::Value IntrinsicLibrary::genAbs(mlir::Type resultType, // math::AbsFOp but it does not support all fir floating point types. return genRuntimeCall("abs", resultType, args); } - if (auto intType = type.dyn_cast()) { + if (auto intType = mlir::dyn_cast(type)) { // At the time of this implementation there is no abs op in mlir. // So, implement abs here without branching. mlir::Value shift = @@ -2379,8 +2380,8 @@ IntrinsicLibrary::genAssociated(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); mlir::Type ptrTy = fir::getBase(args[0]).getType(); - if (ptrTy && - (fir::isBoxProcAddressType(ptrTy) || ptrTy.isa())) { + if (ptrTy && (fir::isBoxProcAddressType(ptrTy) || + mlir::isa(ptrTy))) { mlir::Value pointerBoxProc = fir::isBoxProcAddressType(ptrTy) ? builder.create(loc, fir::getBase(args[0])) @@ -2392,7 +2393,7 @@ IntrinsicLibrary::genAssociated(mlir::Type resultType, mlir::Value target = fir::getBase(args[1]); if (fir::isBoxProcAddressType(target.getType())) target = builder.create(loc, target); - if (target.getType().isa()) + if (mlir::isa(target.getType())) target = builder.create(loc, target); mlir::Type intPtrTy = builder.getIntPtrType(); mlir::Value pointerInt = @@ -2649,7 +2650,7 @@ static mlir::Value getAddrFromBox(fir::FirOpBuilder &builder, mlir::Value argValue = fir::getBase(arg); mlir::Value addr{nullptr}; if (isFunc) { - auto funcTy = argValue.getType().cast().getEleTy(); + auto funcTy = mlir::cast(argValue.getType()).getEleTy(); addr = builder.create(loc, funcTy, argValue); } else { const auto *box = arg.getBoxOf(); @@ -3029,7 +3030,7 @@ void IntrinsicLibrary::genDateAndTime(llvm::ArrayRef args) { mlir::Value IntrinsicLibrary::genDim(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (resultType.isa()) { + if (mlir::isa(resultType)) { mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); auto diff = builder.create(loc, args[0], args[1]); auto cmp = builder.create( @@ -3574,7 +3575,7 @@ IntrinsicLibrary::genReduction(FN func, FD funcDim, llvm::StringRef errMsg, if (absentDim || rank == 1) { mlir::Type ty = array.getType(); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); if (fir::isa_complex(eleTy)) { mlir::Value result = builder.createTemporary(loc, eleTy); func(builder, loc, array, mask, result); @@ -3646,7 +3647,7 @@ mlir::Value IntrinsicLibrary::genIbits(mlir::Type resultType, mlir::Value pos = builder.createConvert(loc, resultType, args[1]); mlir::Value len = builder.createConvert(loc, resultType, args[2]); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); auto shiftCount = builder.create(loc, bitSize, len); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value ones = builder.createAllOnesInteger(loc, resultType); @@ -3686,7 +3687,7 @@ IntrinsicLibrary::genIchar(mlir::Type resultType, mlir::Value buffer = charBox->getBuffer(); mlir::Type bufferTy = buffer.getType(); mlir::Value charVal; - if (auto charTy = bufferTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(bufferTy)) { assert(charTy.singleton()); charVal = buffer; } else { @@ -3759,7 +3760,7 @@ void IntrinsicLibrary::genRaiseExcept(int except, mlir::Value cond) { static std::pair getFieldRef(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value rec) { auto recType = - fir::unwrapPassByRefType(rec.getType()).dyn_cast(); + mlir::dyn_cast(fir::unwrapPassByRefType(rec.getType())); assert(recType.getTypeList().size() == 1 && "expected exactly one component"); auto [fieldName, fieldTy] = recType.getTypeList().front(); mlir::Value field = builder.create( @@ -3808,7 +3809,7 @@ mlir::Value IntrinsicLibrary::genIeeeClass(mlir::Type resultType, assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = realVal.getType().dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); const unsigned intWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(intWidth); mlir::Value intVal = @@ -4056,8 +4057,10 @@ IntrinsicLibrary::genIeeeCopySign(mlir::Type resultType, assert(args.size() == 2); mlir::Value xRealVal = args[0]; mlir::Value yRealVal = args[1]; - mlir::FloatType xRealType = xRealVal.getType().dyn_cast(); - mlir::FloatType yRealType = yRealVal.getType().dyn_cast(); + mlir::FloatType xRealType = + mlir::dyn_cast(xRealVal.getType()); + mlir::FloatType yRealType = + mlir::dyn_cast(yRealVal.getType()); if (yRealType == mlir::FloatType::getBF16(builder.getContext())) { // Workaround: CopySignOp and BitcastOp don't work for kind 3 arg Y. @@ -4106,7 +4109,7 @@ void IntrinsicLibrary::genIeeeGetFlag(llvm::ArrayRef args) { mlir::Value flag = fir::getBase(args[0]); mlir::Value flagValue = fir::getBase(args[1]); mlir::Type resultTy = - flagValue.getType().dyn_cast().getEleTy(); + mlir::dyn_cast(flagValue.getType()).getEleTy(); mlir::Type i32Ty = builder.getIntegerType(32); mlir::Value zero = builder.createIntegerConstant(loc, i32Ty, 0); auto [fieldRef, ignore] = getFieldRef(builder, loc, flag); @@ -4130,7 +4133,7 @@ void IntrinsicLibrary::genIeeeGetHaltingMode( mlir::Value flag = fir::getBase(args[0]); mlir::Value halting = fir::getBase(args[1]); mlir::Type resultTy = - halting.getType().dyn_cast().getEleTy(); + mlir::dyn_cast(halting.getType()).getEleTy(); mlir::Type i32Ty = builder.getIntegerType(32); mlir::Value zero = builder.createIntegerConstant(loc, i32Ty, 0); auto [fieldRef, ignore] = getFieldRef(builder, loc, flag); @@ -4248,7 +4251,7 @@ mlir::Value IntrinsicLibrary::genIeeeLogb(mlir::Type resultType, // : ieee_copy_sign(X, 1.0) // +infinity or NaN assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = realVal.getType().dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); int bitWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(realType.getWidth()); mlir::Value intVal = @@ -4545,7 +4548,7 @@ mlir::Value IntrinsicLibrary::genIeeeSignbit(mlir::Type resultType, // Check if the sign bit of arg X is set. assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = realVal.getType().dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); int bitWidth = realType.getWidth(); if (realType == mlir::FloatType::getBF16(builder.getContext())) { // Workaround: can't bitcast or convert real(3) to integer(2) or real(2). @@ -4642,7 +4645,7 @@ mlir::Value IntrinsicLibrary::genIeeeValue(mlir::Type resultType, // A compiler generated call has one argument: // - arg[0] is an index constant assert(args.size() == 1 || args.size() == 2); - mlir::FloatType realType = resultType.dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(resultType); int bitWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(bitWidth); mlir::Type valueTy = bitWidth <= 64 ? intType : builder.getIntegerType(64); @@ -4884,7 +4887,7 @@ mlir::Value IntrinsicLibrary::genIshft(mlir::Type resultType, // : I << abs(SHIFT) assert(args.size() == 2); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value shift = builder.createConvert(loc, resultType, args[1]); mlir::Value absShift = genAbs(resultType, {shift}); @@ -4920,7 +4923,7 @@ mlir::Value IntrinsicLibrary::genIshftc(mlir::Type resultType, // Return: SHIFT == 0 || SIZE == abs(SHIFT) ? I : (unchanged | left | right) assert(args.size() == 3); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); mlir::Value I = args[0]; mlir::Value shift = builder.createConvert(loc, resultType, args[1]); mlir::Value size = @@ -5027,7 +5030,7 @@ IntrinsicLibrary::genLoc(mlir::Type resultType, mlir::Value box = fir::getBase(args[0]); assert(fir::isa_box_type(box.getType()) && "argument must have been lowered to box type"); - bool isFunc = box.getType().isa(); + bool isFunc = mlir::isa(box.getType()); if (!isOptional(box)) { mlir::Value argAddr = getAddrFromBox(builder, loc, args[0], isFunc); return builder.createConvert(loc, resultType, argAddr); @@ -5156,7 +5159,7 @@ IntrinsicLibrary::genMerge(mlir::Type, auto convertToStaticType = [&](mlir::Value polymorphic, mlir::Value other) -> mlir::Value { mlir::Type otherType = other.getType(); - if (otherType.isa()) + if (mlir::isa(otherType)) return builder.create(loc, otherType, polymorphic, /*shape*/ mlir::Value{}, /*slice=*/mlir::Value{}); @@ -5209,7 +5212,7 @@ mlir::Value IntrinsicLibrary::genMergeBits(mlir::Type resultType, mlir::Value IntrinsicLibrary::genMod(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (resultType.isa()) + if (mlir::isa(resultType)) return builder.create(loc, args[0], args[1]); // Use runtime. @@ -5231,7 +5234,7 @@ mlir::Value IntrinsicLibrary::genModulo(mlir::Type resultType, // - Otherwise, when A/P < 0 and MOD(A,P) !=0, then MODULO(A, P) = // A-FLOOR(A/P)*P = A-(INT(A/P)-1)*P = A-INT(A/P)*P+P = MOD(A,P)+P // Note that A/P < 0 if and only if A and P signs are different. - if (resultType.isa()) { + if (mlir::isa(resultType)) { auto remainder = builder.create(loc, args[0], args[1]); auto argXor = builder.create(loc, args[0], args[1]); @@ -5344,7 +5347,7 @@ void IntrinsicLibrary::genMvbits(llvm::ArrayRef args) { mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value ones = builder.createAllOnesInteger(loc, resultType); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); auto shiftCount = builder.create(loc, bitSize, len); auto mask = builder.create(loc, ones, shiftCount); auto unchangedTmp1 = builder.create(loc, mask, topos); @@ -5628,7 +5631,7 @@ IntrinsicLibrary::genReshape(mlir::Type resultType, assert(fir::BoxValue(shape).rank() == 1); mlir::Type shapeTy = shape.getType(); mlir::Type shapeArrTy = fir::dyn_cast_ptrOrBoxEleTy(shapeTy); - auto resultRank = shapeArrTy.cast().getShape()[0]; + auto resultRank = mlir::cast(shapeArrTy).getShape()[0]; if (resultRank == fir::SequenceType::getUnknownExtent()) TODO(loc, "intrinsic: reshape requires computing rank of result"); @@ -5921,7 +5924,7 @@ void IntrinsicLibrary::genSignalSubroutine( mlir::Value IntrinsicLibrary::genSign(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (resultType.isa()) { + if (mlir::isa(resultType)) { mlir::Value abs = genAbs(resultType, {args[0]}); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); auto neg = builder.create(loc, zero, abs); diff --git a/flang/lib/Optimizer/Builder/MutableBox.cpp b/flang/lib/Optimizer/Builder/MutableBox.cpp index d4012e9c3d9d..76b920dba869 100644 --- a/flang/lib/Optimizer/Builder/MutableBox.cpp +++ b/flang/lib/Optimizer/Builder/MutableBox.cpp @@ -28,7 +28,7 @@ createNewFirBox(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, mlir::Value addr, mlir::ValueRange lbounds, mlir::ValueRange extents, mlir::ValueRange lengths, mlir::Value tdesc = {}) { - if (addr.getType().isa()) + if (mlir::isa(addr.getType())) // The entity is already boxed. return builder.createConvert(loc, box.getBoxTy(), addr); @@ -53,20 +53,21 @@ createNewFirBox(fir::FirOpBuilder &builder, mlir::Location loc, // error in the embox). llvm::SmallVector cleanedLengths; auto cleanedAddr = addr; - if (auto charTy = box.getEleTy().dyn_cast()) { + if (auto charTy = mlir::dyn_cast(box.getEleTy())) { // Cast address to box type so that both input and output type have // unknown or constant lengths. auto bt = box.getBaseTy(); auto addrTy = addr.getType(); - auto type = addrTy.isa() ? fir::HeapType::get(bt) - : addrTy.isa() ? fir::PointerType::get(bt) - : builder.getRefType(bt); + auto type = mlir::isa(addrTy) ? fir::HeapType::get(bt) + : mlir::isa(addrTy) + ? fir::PointerType::get(bt) + : builder.getRefType(bt); cleanedAddr = builder.createConvert(loc, type, addr); if (charTy.getLen() == fir::CharacterType::unknownLen()) cleanedLengths.append(lengths.begin(), lengths.end()); } else if (fir::isUnlimitedPolymorphicType(box.getBoxTy())) { - if (auto charTy = fir::dyn_cast_ptrEleTy(addr.getType()) - .dyn_cast()) { + if (auto charTy = mlir::dyn_cast( + fir::dyn_cast_ptrEleTy(addr.getType()))) { if (charTy.getLen() == fir::CharacterType::unknownLen()) cleanedLengths.append(lengths.begin(), lengths.end()); } @@ -328,18 +329,18 @@ private: mlir::Value fir::factory::createUnallocatedBox( fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type boxType, mlir::ValueRange nonDeferredParams, mlir::Value typeSourceBox) { - auto baseAddrType = boxType.dyn_cast().getEleTy(); + auto baseAddrType = mlir::dyn_cast(boxType).getEleTy(); if (!fir::isa_ref_type(baseAddrType)) baseAddrType = builder.getRefType(baseAddrType); auto type = fir::unwrapRefType(baseAddrType); auto eleTy = fir::unwrapSequenceType(type); - if (auto recTy = eleTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(eleTy)) if (recTy.getNumLenParams() > 0) TODO(loc, "creating unallocated fir.box of derived type with length " "parameters"); auto nullAddr = builder.createNullConstant(loc, baseAddrType); mlir::Value shape; - if (auto seqTy = type.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(type)) { auto zero = builder.createIntegerConstant(loc, builder.getIndexType(), 0); llvm::SmallVector extents(seqTy.getDimension(), zero); shape = builder.createShape( @@ -348,7 +349,7 @@ mlir::Value fir::factory::createUnallocatedBox( // Provide dummy length parameters if they are dynamic. If a length parameter // is deferred. It is set to zero here and will be set on allocation. llvm::SmallVector lenParams; - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { if (charTy.getLen() == fir::CharacterType::unknownLen()) { if (!nonDeferredParams.empty()) { lenParams.push_back(nonDeferredParams[0]); @@ -592,7 +593,7 @@ void fir::factory::associateMutableBoxWithRemap( auto cast = [&](mlir::Value addr) -> mlir::Value { // Cast base addr to new sequence type. auto ty = fir::dyn_cast_ptrEleTy(addr.getType()); - if (auto seqTy = ty.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(ty)) { fir::SequenceType::Shape shape(newRank, fir::SequenceType::getUnknownExtent()); ty = fir::SequenceType::get(shape, seqTy.getEleTy()); @@ -673,10 +674,10 @@ void fir::factory::disassociateMutableBox(fir::FirOpBuilder &builder, if (box.isPolymorphic() && polymorphicSetType) { // 7.3.2.3 point 7. The dynamic type of a disassociated pointer is the // same as its declared type. - auto boxTy = box.getBoxTy().dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getBoxTy()); auto eleTy = fir::unwrapPassByRefType(boxTy.getEleTy()); mlir::Type derivedType = fir::getDerivedType(eleTy); - if (auto recTy = derivedType.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(derivedType)) { fir::runtime::genNullifyDerivedType(builder, loc, box.getAddr(), recTy, box.rank()); return; @@ -690,7 +691,7 @@ getNewLengths(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, mlir::ValueRange lenParams) { llvm::SmallVector lengths; auto idxTy = builder.getIndexType(); - if (auto charTy = box.getEleTy().dyn_cast()) { + if (auto charTy = mlir::dyn_cast(box.getEleTy())) { if (charTy.getLen() == fir::CharacterType::unknownLen()) { if (box.hasNonDeferredLenParams()) { lengths.emplace_back( @@ -717,7 +718,7 @@ static mlir::Value allocateAndInitNewStorage(fir::FirOpBuilder &builder, auto lengths = getNewLengths(builder, loc, box, lenParams); auto newStorage = builder.create( loc, box.getBaseTy(), allocName, lengths, extents); - if (box.getEleTy().isa()) { + if (mlir::isa(box.getEleTy())) { // TODO: skip runtime initialization if this is not required. Currently, // there is no way to know here if a derived type needs it or not. But the // information is available at compile time and could be reflected here @@ -742,7 +743,7 @@ void fir::factory::genInlinedAllocation( lengths, safeExtents); MutablePropertyWriter{builder, loc, box}.updateMutableBox( heap, lbounds, safeExtents, lengths); - if (box.getEleTy().isa()) { + if (mlir::isa(box.getEleTy())) { // TODO: skip runtime initialization if this is not required. Currently, // there is no way to know here if a derived type needs it or not. But the // information is available at compile time and could be reflected here diff --git a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp index 160118e2c050..7f09e8822844 100644 --- a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp @@ -1119,7 +1119,7 @@ PPCIntrinsicLibrary::genVecAbs(mlir::Type resultType, funcOp = builder.createFunction(loc, fname, ftype); auto callOp{builder.create(loc, funcOp, argBases[0])}; return callOp.getResult(0); - } else if (auto eleTy = vTypeInfo.eleTy.dyn_cast()) { + } else if (auto eleTy = mlir::dyn_cast(vTypeInfo.eleTy)) { // vec_abs(arg1) = max(0 - arg1, arg1) auto newVecTy{mlir::VectorType::get(vTypeInfo.len, eleTy)}; @@ -1173,12 +1173,13 @@ fir::ExtendedValue PPCIntrinsicLibrary::genVecAddAndMulSubXor( assert(args.size() == 2); auto argBases{getBasesForArgs(args)}; auto argsTy{getTypesForArgs(argBases)}; - assert(argsTy[0].isa() && argsTy[1].isa()); + assert(mlir::isa(argsTy[0]) && + mlir::isa(argsTy[1])); auto vecTyInfo{getVecTypeFromFir(argBases[0])}; - const auto isInteger{vecTyInfo.eleTy.isa()}; - const auto isFloat{vecTyInfo.eleTy.isa()}; + const auto isInteger{mlir::isa(vecTyInfo.eleTy)}; + const auto isFloat{mlir::isa(vecTyInfo.eleTy)}; assert((isInteger || isFloat) && "unknown vector type"); auto vargs{convertVecArgs(builder, loc, vecTyInfo, argBases)}; @@ -1212,7 +1213,7 @@ fir::ExtendedValue PPCIntrinsicLibrary::genVecAddAndMulSubXor( arg2 = vargs[1]; } else if (isFloat) { // bitcast the arguments to integer - auto wd{vecTyInfo.eleTy.dyn_cast().getWidth()}; + auto wd{mlir::dyn_cast(vecTyInfo.eleTy).getWidth()}; auto ftype{builder.getIntegerType(wd)}; auto bcVecTy{mlir::VectorType::get(vecTyInfo.len, ftype)}; arg1 = builder.create(loc, bcVecTy, vargs[0]); @@ -1450,7 +1451,7 @@ PPCIntrinsicLibrary::genVecCmp(mlir::Type resultType, mlir::Value res{nullptr}; - if (auto eTy = vecTyInfo.eleTy.dyn_cast()) { + if (auto eTy = mlir::dyn_cast(vecTyInfo.eleTy)) { constexpr int firstArg{0}; constexpr int secondArg{1}; std::map> argOrder{ @@ -1559,7 +1560,7 @@ PPCIntrinsicLibrary::genVecConvert(mlir::Type resultType, case VecOp::Ctf: { assert(args.size() == 2); auto convArg{builder.createConvert(loc, i32Ty, argBases[1])}; - auto eTy{vecTyInfo.eleTy.dyn_cast()}; + auto eTy{mlir::dyn_cast(vecTyInfo.eleTy)}; assert(eTy && "Unsupported vector type"); const auto isUnsigned{eTy.isUnsignedInteger()}; const auto width{eTy.getWidth()}; @@ -1587,10 +1588,9 @@ PPCIntrinsicLibrary::genVecConvert(mlir::Type resultType, : builder.create(loc, ty, vArg1)}; // construct vector<1./(1< - auto constInt{ + auto constInt{mlir::dyn_cast_or_null( mlir::dyn_cast(argBases[1].getDefiningOp()) - .getValue() - .dyn_cast_or_null()}; + .getValue())}; assert(constInt && "expected integer constant argument"); double f{1.0 / (1 << constInt.getInt())}; llvm::SmallVector vals{f, f}; @@ -1815,7 +1815,7 @@ static mlir::Value addOffsetToAddress(fir::FirOpBuilder &builder, static mlir::Value reverseVectorElements(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value v, int64_t len) { - assert(v.getType().isa()); + assert(mlir::isa(v.getType())); assert(len > 0); llvm::SmallVector mask; for (int64_t i = 0; i < len; ++i) { @@ -2144,10 +2144,9 @@ PPCIntrinsicLibrary::genVecPerm(mlir::Type resultType, } case VecOp::Permi: { // arg3 is a constant - auto constIntOp{ + auto constIntOp{mlir::dyn_cast_or_null( mlir::dyn_cast(argBases[2].getDefiningOp()) - .getValue() - .dyn_cast_or_null()}; + .getValue())}; assert(constIntOp && "expected integer constant argument"); auto constInt{constIntOp.getInt()}; // arg1, arg2, and result type share same VecTypeInfo @@ -2321,10 +2320,9 @@ PPCIntrinsicLibrary::genVecShift(mlir::Type resultType, } } else if (vop == VecOp::Sld || vop == VecOp::Sldw) { assert(args.size() == 3); - auto constIntOp = + auto constIntOp = mlir::dyn_cast_or_null( mlir::dyn_cast(argBases[2].getDefiningOp()) - .getValue() - .dyn_cast_or_null(); + .getValue()); assert(constIntOp && "expected integer constant argument"); // Bitcast to vector<16xi8> @@ -2797,16 +2795,16 @@ void PPCIntrinsicLibrary::genMmaIntr(llvm::ArrayRef args) { auto vType{v.getType()}; mlir::Type targetType{intrFuncType.getInput(j)}; if (vType != targetType) { - if (targetType.isa()) { + if (mlir::isa(targetType)) { // Perform vector type conversion for arguments passed by value. - auto eleTy{vType.dyn_cast().getEleTy()}; - auto len{vType.dyn_cast().getLen()}; + auto eleTy{mlir::dyn_cast(vType).getEleTy()}; + auto len{mlir::dyn_cast(vType).getLen()}; mlir::VectorType mlirType = mlir::VectorType::get(len, eleTy); auto v0{builder.createConvert(loc, mlirType, v)}; auto v1{builder.create(loc, targetType, v0)}; intrArgs.push_back(v1); - } else if (targetType.isa() && - vType.isa()) { + } else if (mlir::isa(targetType) && + mlir::isa(vType)) { auto v0{builder.createConvert(loc, targetType, v)}; intrArgs.push_back(v0); } else { @@ -2861,7 +2859,7 @@ void PPCIntrinsicLibrary::genVecStore(llvm::ArrayRef args) { if (arg1TyInfo.isFloat32()) { stTy = mlir::VectorType::get(len, i32ty); fname = "llvm.ppc.altivec.stvewx"; - } else if (arg1TyInfo.eleTy.isa()) { + } else if (mlir::isa(arg1TyInfo.eleTy)) { stTy = mlir::VectorType::get(len, mlir::IntegerType::get(context, width)); switch (width) { diff --git a/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp b/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp index abff0e150ab4..70a88ff18cb1 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp @@ -27,7 +27,7 @@ mlir::Value fir::runtime::genMoveAlloc(fir::FirOpBuilder &builder, if (fir::isPolymorphicType(from.getType()) && !fir::isUnlimitedPolymorphicType(from.getType())) { fir::ClassType clTy = - fir::dyn_cast_ptrEleTy(from.getType()).dyn_cast(); + mlir::dyn_cast(fir::dyn_cast_ptrEleTy(from.getType())); mlir::Type derivedType = fir::unwrapInnerType(clTy.getEleTy()); declaredTypeDesc = builder.create(loc, mlir::TypeAttr::get(derivedType)); diff --git a/flang/lib/Optimizer/Builder/Runtime/Character.cpp b/flang/lib/Optimizer/Builder/Runtime/Character.cpp index f3663439fdd5..b16819915d5a 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Character.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Character.cpp @@ -39,15 +39,15 @@ static void genCharacterSearch(FN func, fir::FirOpBuilder &builder, /// Helper function to recover the KIND from the FIR type. static int discoverKind(mlir::Type ty) { - if (auto charTy = ty.dyn_cast()) + if (auto charTy = mlir::dyn_cast(ty)) return charTy.getFKind(); if (auto eleTy = fir::dyn_cast_ptrEleTy(ty)) return discoverKind(eleTy); - if (auto arrTy = ty.dyn_cast()) + if (auto arrTy = mlir::dyn_cast(ty)) return discoverKind(arrTy.getEleTy()); - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return discoverKind(boxTy.getEleTy()); - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return discoverKind(boxTy.getEleTy()); llvm_unreachable("unexpected character type"); } diff --git a/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp b/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp index 57c47da0f3f8..8b78a1688c73 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp @@ -228,7 +228,8 @@ void fir::runtime::genSystemClock(fir::FirOpBuilder &builder, fir::IfOp ifOp{}; const bool isOptionalArg = fir::valueHasFirAttribute(arg, fir::getOptionalAttrName()); - if (type.dyn_cast() || type.dyn_cast()) { + if (mlir::dyn_cast(type) || + mlir::dyn_cast(type)) { // Check for a disassociated pointer or an unallocated allocatable. assert(!isOptionalArg && "invalid optional argument"); ifOp = builder.create(loc, builder.genIsNotNullAddr(loc, arg), @@ -242,7 +243,8 @@ void fir::runtime::genSystemClock(fir::FirOpBuilder &builder, builder.setInsertionPointToStart(&ifOp.getThenRegion().front()); mlir::Type kindTy = func.getFunctionType().getInput(0); int integerKind = 8; - if (auto intType = fir::unwrapRefType(type).dyn_cast()) + if (auto intType = + mlir::dyn_cast(fir::unwrapRefType(type))) integerKind = intType.getWidth() / 8; mlir::Value kind = builder.createIntegerConstant(loc, kindTy, integerKind); mlir::Value res = diff --git a/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp b/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp index 4d33282a35d9..e5d0fb0fb27a 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp @@ -32,7 +32,8 @@ void fir::runtime::genRaggedArrayAllocate(mlir::Location loc, // Position of the bufferPointer in the header struct. auto one = builder.createIntegerConstant(loc, i32Ty, 1); auto eleTy = fir::unwrapSequenceType(fir::unwrapRefType(header.getType())); - auto ptrTy = builder.getRefType(eleTy.cast().getType(1)); + auto ptrTy = + builder.getRefType(mlir::cast(eleTy).getType(1)); auto ptr = builder.create(loc, ptrTy, header, one); auto heap = builder.create(loc, ptr); auto cmp = builder.genIsNullAddr(loc, heap); diff --git a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp index 66fbaddcbda1..d4076067bf10 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp @@ -666,7 +666,7 @@ void fir::runtime::genMaxloc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); fir::factory::CharacterExprHelper charHelper{builder, loc}; if (eleTy.isF32()) func = fir::runtime::getRuntimeFunc(loc, builder); @@ -713,7 +713,7 @@ mlir::Value fir::runtime::genMaxval(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -781,7 +781,7 @@ void fir::runtime::genMinloc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); fir::factory::CharacterExprHelper charHelper{builder, loc}; if (eleTy.isF32()) func = fir::runtime::getRuntimeFunc(loc, builder); @@ -853,7 +853,7 @@ mlir::Value fir::runtime::genMinval(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -895,7 +895,7 @@ void fir::runtime::genNorm2Dim(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); if (eleTy.isF128()) func = fir::runtime::getRuntimeFunc(loc, builder); else @@ -917,7 +917,7 @@ mlir::Value fir::runtime::genNorm2(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -968,7 +968,7 @@ mlir::Value fir::runtime::genProduct(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -1069,7 +1069,7 @@ mlir::Value fir::runtime::genDotProduct(fir::FirOpBuilder &builder, else if (eleTy.isInteger(builder.getKindMap().getIntegerBitsize(16))) func = fir::runtime::getRuntimeFunc(loc, builder); - else if (eleTy.isa()) + else if (mlir::isa(eleTy)) func = fir::runtime::getRuntimeFunc(loc, builder); else @@ -1111,7 +1111,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -1173,7 +1173,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; \ auto ty = arrayBox.getType(); \ auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); \ - auto eleTy = arrTy.cast().getEleTy(); \ + auto eleTy = mlir::cast(arrTy).getEleTy(); \ auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); \ \ if (eleTy.isInteger(builder.getKindMap().getIntegerBitsize(1))) \ diff --git a/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp b/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp index 48173033ecbe..5229d40f2250 100644 --- a/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp +++ b/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp @@ -51,9 +51,9 @@ public: /// not at all depending on the implementation target's characteristics and /// preference. bool needsConversion(mlir::Type ty) { - if (ty.isa()) + if (mlir::isa(ty)) return true; - if (auto funcTy = ty.dyn_cast()) { + if (auto funcTy = mlir::dyn_cast(ty)) { for (auto t : funcTy.getInputs()) if (needsConversion(t)) return true; @@ -62,13 +62,13 @@ public: return true; return false; } - if (auto tupleTy = ty.dyn_cast()) { + if (auto tupleTy = mlir::dyn_cast(ty)) { for (auto t : tupleTy.getTypes()) if (needsConversion(t)) return true; return false; } - if (auto recTy = ty.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(ty)) { auto visited = visitedTypes.find(ty); if (visited != visitedTypes.end()) return visited->second; @@ -97,11 +97,11 @@ public: visitedTypes.find(ty)->second = result; return result; } - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return needsConversion(boxTy.getEleTy()); if (isa_ref_type(ty)) return needsConversion(unwrapRefType(ty)); - if (auto t = ty.dyn_cast()) + if (auto t = mlir::dyn_cast(ty)) return needsConversion(unwrapSequenceType(ty)); return false; } @@ -246,7 +246,7 @@ public: if (typeConverter.needsConversion(ty)) { rewriter.startOpModification(func); auto toTy = - typeConverter.convertType(ty).cast(); + mlir::cast(typeConverter.convertType(ty)); if (!func.empty()) for (auto e : llvm::enumerate(toTy.getInputs())) { unsigned i = e.index(); @@ -263,7 +263,7 @@ public: // Rewrite all `fir.emboxproc` ops to either `fir.convert` or a thunk // as required. mlir::Type toTy = typeConverter.convertType( - embox.getType().cast().getEleTy()); + mlir::cast(embox.getType()).getEleTy()); rewriter.setInsertionPoint(embox); if (embox.getHost()) { // Create the thunk. diff --git a/flang/lib/Optimizer/CodeGen/CGOps.cpp b/flang/lib/Optimizer/CodeGen/CGOps.cpp index c3bcdeaf86db..44d07d26dd2b 100644 --- a/flang/lib/Optimizer/CodeGen/CGOps.cpp +++ b/flang/lib/Optimizer/CodeGen/CGOps.cpp @@ -41,24 +41,24 @@ unsigned fir::cg::XEmboxOp::getOutRank() { } unsigned fir::cg::XReboxOp::getOutRank() { - if (auto seqTy = - fir::dyn_cast_ptrOrBoxEleTy(getType()).dyn_cast()) + if (auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(getType()))) return seqTy.getDimension(); return 0; } unsigned fir::cg::XReboxOp::getRank() { - if (auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(getBox().getType()) - .dyn_cast()) + if (auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(getBox().getType()))) return seqTy.getDimension(); return 0; } unsigned fir::cg::XArrayCoorOp::getRank() { auto memrefTy = getMemref().getType(); - if (memrefTy.isa()) - if (auto seqty = - fir::dyn_cast_ptrOrBoxEleTy(memrefTy).dyn_cast()) + if (mlir::isa(memrefTy)) + if (auto seqty = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(memrefTy))) return seqty.getDimension(); return getShape().size(); } diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp index 921eac2f8f4b..19628ac71b0b 100644 --- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp +++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp @@ -101,7 +101,7 @@ static int64_t getConstantIntValue(mlir::Value val) { } static unsigned getTypeDescFieldId(mlir::Type ty) { - auto isArray = fir::dyn_cast_ptrOrBoxEleTy(ty).isa(); + auto isArray = mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(ty)); return isArray ? kOptTypePtrPosInBox : kDimsPosInBox; } static unsigned getLenParamFieldId(mlir::Type ty) { @@ -147,7 +147,7 @@ genAllocationScaleSize(OP op, mlir::Type ity, mlir::ConversionPatternRewriter &rewriter) { mlir::Location loc = op.getLoc(); mlir::Type dataTy = op.getInType(); - auto seqTy = dataTy.dyn_cast(); + auto seqTy = mlir::dyn_cast(dataTy); fir::SequenceType::Extent constSize = 1; if (seqTy) { int constRows = seqTy.getConstantRows(); @@ -191,13 +191,13 @@ struct AllocaOpConversion : public fir::FIROpConversion { for (; i < end; ++i) lenParams.push_back(operands[i]); mlir::Type scalarType = fir::unwrapSequenceType(alloc.getInType()); - if (auto chrTy = scalarType.dyn_cast()) { + if (auto chrTy = mlir::dyn_cast(scalarType)) { fir::CharacterType rawCharTy = fir::CharacterType::getUnknownLen( chrTy.getContext(), chrTy.getFKind()); llvmObjectType = convertType(rawCharTy); assert(end == 1); size = integerCast(loc, rewriter, ity, lenParams[0]); - } else if (auto recTy = scalarType.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(scalarType)) { mlir::LLVM::LLVMFuncOp memSizeFn = getDependentTypeMemSizeFn(recTy, alloc, rewriter); if (!memSizeFn) @@ -265,7 +265,8 @@ struct BoxAddrOpConversion : public fir::FIROpConversion { mlir::ConversionPatternRewriter &rewriter) const override { mlir::Value a = adaptor.getOperands()[0]; auto loc = boxaddr.getLoc(); - if (auto argty = boxaddr.getVal().getType().dyn_cast()) { + if (auto argty = + mlir::dyn_cast(boxaddr.getVal().getType())) { TypePair boxTyPair = getBoxTypePair(argty); rewriter.replaceOp(boxaddr, getBaseAddrFromBox(loc, boxTyPair, a, rewriter)); @@ -476,24 +477,25 @@ struct StringLitOpConversion : public fir::FIROpConversion { mlir::ConversionPatternRewriter &rewriter) const override { auto ty = convertType(constop.getType()); auto attr = constop.getValue(); - if (attr.isa()) { + if (mlir::isa(attr)) { rewriter.replaceOpWithNewOp(constop, ty, attr); return mlir::success(); } - auto charTy = constop.getType().cast(); + auto charTy = mlir::cast(constop.getType()); unsigned bits = lowerTy().characterBitsize(charTy); mlir::Type intTy = rewriter.getIntegerType(bits); mlir::Location loc = constop.getLoc(); mlir::Value cst = rewriter.create(loc, ty); - if (auto arr = attr.dyn_cast()) { + if (auto arr = mlir::dyn_cast(attr)) { cst = rewriter.create(loc, ty, arr); - } else if (auto arr = attr.dyn_cast()) { + } else if (auto arr = mlir::dyn_cast(attr)) { for (auto a : llvm::enumerate(arr.getValue())) { // convert each character to a precise bitsize auto elemAttr = mlir::IntegerAttr::get( intTy, - a.value().cast().getValue().zextOrTrunc(bits)); + mlir::cast(a.value()).getValue().zextOrTrunc( + bits)); auto elemCst = rewriter.create(loc, intTy, elemAttr); cst = rewriter.create(loc, cst, elemCst, @@ -528,9 +530,9 @@ struct CallOpConversion : public fir::FIROpConversion { } // namespace static mlir::Type getComplexEleTy(mlir::Type complex) { - if (auto cc = complex.dyn_cast()) + if (auto cc = mlir::dyn_cast(complex)) return cc.getElementType(); - return complex.cast().getElementType(); + return mlir::cast(complex).getElementType(); } namespace { @@ -599,7 +601,7 @@ struct ConstcOpConversion : public fir::FIROpConversion { } inline llvm::APFloat getValue(mlir::Attribute attr) const { - return attr.cast().getValue(); + return mlir::cast(attr).getValue(); } }; @@ -608,7 +610,7 @@ struct ConvertOpConversion : public fir::FIROpConversion { using FIROpConversion::FIROpConversion; static bool isFloatingPointTy(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } mlir::LogicalResult @@ -628,7 +630,8 @@ struct ConvertOpConversion : public fir::FIROpConversion { auto loc = convert.getLoc(); auto i1Type = mlir::IntegerType::get(convert.getContext(), 1); - if (fromFirTy.isa() || toFirTy.isa()) { + if (mlir::isa(fromFirTy) || + mlir::isa(toFirTy)) { // By specification fir::LogicalType value may be any number, // where non-zero value represents .true. and zero value represents // .false. @@ -641,7 +644,8 @@ struct ConvertOpConversion : public fir::FIROpConversion { // Conversion from narrow logical to wide logical may be implemented // as a zero or sign extension of the input, but it may use value // normalization as well. - if (!fromTy.isa() || !toTy.isa()) + if (!mlir::isa(fromTy) || + !mlir::isa(toTy)) return mlir::emitError(loc) << "unsupported types for logical conversion: " << fromTy << " -> " << toTy; @@ -722,13 +726,13 @@ struct ConvertOpConversion : public fir::FIROpConversion { rewriter.replaceOp(convert, v); return mlir::success(); } - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } - } else if (fromTy.isa()) { + } else if (mlir::isa(fromTy)) { // Integer to integer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { auto fromBits = mlir::LLVM::getPrimitiveTypeSizeInBits(fromTy); auto toBits = mlir::LLVM::getPrimitiveTypeSizeInBits(toTy); assert(fromBits != toBits); @@ -749,18 +753,18 @@ struct ConvertOpConversion : public fir::FIROpConversion { return mlir::success(); } // Integer to pointer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } - } else if (fromTy.isa()) { + } else if (mlir::isa(fromTy)) { // Pointer to integer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } // Pointer to pointer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } @@ -842,11 +846,11 @@ struct EmboxCharOpConversion : public fir::FIROpConversion { auto llvmStruct = rewriter.create(loc, llvmStructTy); mlir::Type lenTy = - llvmStructTy.cast().getBody()[1]; + mlir::cast(llvmStructTy).getBody()[1]; mlir::Value lenAfterCast = integerCast(loc, rewriter, lenTy, charBufferLen); mlir::Type addrTy = - llvmStructTy.cast().getBody()[0]; + mlir::cast(llvmStructTy).getBody()[0]; if (addrTy != charBuffer.getType()) charBuffer = rewriter.create(loc, addrTy, charBuffer); @@ -979,9 +983,10 @@ static mlir::SymbolRefAttr getFree(fir::FreeMemOp op, static unsigned getDimension(mlir::LLVM::LLVMArrayType ty) { unsigned result = 1; - for (auto eleTy = ty.getElementType().dyn_cast(); - eleTy; - eleTy = eleTy.getElementType().dyn_cast()) + for (auto eleTy = + mlir::dyn_cast(ty.getElementType()); + eleTy; eleTy = mlir::dyn_cast( + eleTy.getElementType())) ++result; return result; } @@ -1052,9 +1057,9 @@ struct EmboxCommonConversion : public fir::FIROpConversion { static int getCFIAttr(fir::BaseBoxType boxTy) { auto eleTy = boxTy.getEleTy(); - if (eleTy.isa()) + if (mlir::isa(eleTy)) return CFI_attribute_pointer; - if (eleTy.isa()) + if (mlir::isa(eleTy)) return CFI_attribute_allocatable; return CFI_attribute_other; } @@ -1082,27 +1087,29 @@ struct EmboxCommonConversion : public fir::FIROpConversion { auto i64Ty = mlir::IntegerType::get(rewriter.getContext(), 64); if (auto eleTy = fir::dyn_cast_ptrEleTy(boxEleTy)) boxEleTy = eleTy; - if (auto seqTy = boxEleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(boxEleTy)) return getSizeAndTypeCode(loc, rewriter, seqTy.getEleTy(), lenParams); - if (boxEleTy.isa()) // unlimited polymorphic or assumed type + if (mlir::isa( + boxEleTy)) // unlimited polymorphic or assumed type return {rewriter.create(loc, i64Ty, 0), this->genConstantOffset(loc, rewriter, CFI_type_other)}; mlir::Value typeCodeVal = this->genConstantOffset( loc, rewriter, fir::getTypeCode(boxEleTy, this->lowerTy().getKindMap())); - if (fir::isa_integer(boxEleTy) || boxEleTy.dyn_cast() || - fir::isa_real(boxEleTy) || fir::isa_complex(boxEleTy)) + if (fir::isa_integer(boxEleTy) || + mlir::dyn_cast(boxEleTy) || fir::isa_real(boxEleTy) || + fir::isa_complex(boxEleTy)) return {genTypeStrideInBytes(loc, i64Ty, rewriter, this->convertType(boxEleTy)), typeCodeVal}; - if (auto charTy = boxEleTy.dyn_cast()) + if (auto charTy = mlir::dyn_cast(boxEleTy)) return {getCharacterByteSize(loc, rewriter, charTy, lenParams), typeCodeVal}; if (fir::isa_ref_type(boxEleTy)) { auto ptrTy = ::getLlvmPtrType(rewriter.getContext()); return {genTypeStrideInBytes(loc, i64Ty, rewriter, ptrTy), typeCodeVal}; } - if (boxEleTy.isa()) + if (mlir::isa(boxEleTy)) return {genTypeStrideInBytes(loc, i64Ty, rewriter, this->convertType(boxEleTy)), typeCodeVal}; @@ -1211,8 +1218,8 @@ struct EmboxCommonConversion : public fir::FIROpConversion { if (!typeDesc) { if (useInputType) { mlir::Type innerType = fir::unwrapInnerType(inputType); - if (innerType && innerType.template isa()) { - auto recTy = innerType.template dyn_cast(); + if (innerType && mlir::isa(innerType)) { + auto recTy = mlir::dyn_cast(innerType); typeDesc = getTypeDescriptor(mod, rewriter, loc, recTy); } else { // Unlimited polymorphic type descriptor with no record type. Set @@ -1250,7 +1257,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::ValueRange lenParams, mlir::Value sourceBox = {}, mlir::Type sourceBoxType = {}) const { auto loc = box.getLoc(); - auto boxTy = box.getType().template dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getType()); bool useInputType = fir::isPolymorphicType(boxTy) && !fir::isUnlimitedPolymorphicType(inputType); llvm::SmallVector typeparams = lenParams; @@ -1293,8 +1300,8 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::ValueRange lenParams, mlir::Value typeDesc = {}) const { auto loc = box.getLoc(); - auto boxTy = box.getType().dyn_cast(); - auto inputBoxTy = box.getBox().getType().dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getType()); + auto inputBoxTy = mlir::dyn_cast(box.getBox().getType()); auto inputBoxTyPair = this->getBoxTypePair(inputBoxTy); llvm::SmallVector typeparams = lenParams; if (!box.getSubstr().empty() && fir::hasDynamicSize(boxTy.getEleTy())) @@ -1343,7 +1350,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::Type resultTy = llvmBaseObjectType; // Fortran is column major, llvm GEP is row major: reverse the indices here. for (mlir::Value interiorIndex : llvm::reverse(cstInteriorIndices)) { - auto arrayTy = resultTy.dyn_cast(); + auto arrayTy = mlir::dyn_cast(resultTy); if (!arrayTy) fir::emitFatalError( loc, @@ -1355,7 +1362,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { convertSubcomponentIndices(loc, resultTy, componentIndices, &resultTy); gepArgs.append(gepIndices.begin(), gepIndices.end()); if (substringOffset) { - if (auto arrayTy = resultTy.dyn_cast()) { + if (auto arrayTy = mlir::dyn_cast(resultTy)) { gepArgs.push_back(*substringOffset); resultTy = arrayTy.getElementType(); } else { @@ -1504,18 +1511,18 @@ struct XEmboxOpConversion : public EmboxCommonConversion { unsigned constRows = 0; mlir::Value ptrOffset = zero; mlir::Type memEleTy = fir::dyn_cast_ptrEleTy(xbox.getMemref().getType()); - assert(memEleTy.isa()); - auto seqTy = memEleTy.cast(); + assert(mlir::isa(memEleTy)); + auto seqTy = mlir::cast(memEleTy); mlir::Type seqEleTy = seqTy.getEleTy(); // Adjust the element scaling factor if the element is a dependent type. if (fir::hasDynamicSize(seqEleTy)) { - if (auto charTy = seqEleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(seqEleTy)) { // The GEP pointer type decays to llvm.ptr. // The scaling factor is the runtime value of the length. assert(!adaptor.getLenParams().empty()); prevPtrOff = FIROpConversion::integerCast( loc, rewriter, i64Ty, adaptor.getLenParams().back()); - } else if (seqEleTy.isa()) { + } else if (mlir::isa(seqEleTy)) { // prevPtrOff = ; TODO(loc, "generate call to calculate size of PDT"); } else { @@ -1540,7 +1547,7 @@ struct XEmboxOpConversion : public EmboxCommonConversion { } else if (hasSubstr) { // We have a substring. The step value needs to be the number of bytes // per CHARACTER element. - auto charTy = seqEleTy.cast(); + auto charTy = mlir::cast(seqEleTy); if (fir::hasDynamicSize(charTy)) { prevDimByteStride = getCharacterByteSize(loc, rewriter, charTy, adaptor.getLenParams()); @@ -1589,7 +1596,7 @@ struct XEmboxOpConversion : public EmboxCommonConversion { // Lower bound is normalized to 0 for BIND(C) interoperability. mlir::Value lb = zero; const bool isaPointerOrAllocatable = - eleTy.isa() || eleTy.isa(); + mlir::isa(eleTy); // Lower bound is defaults to 1 for POINTER, ALLOCATABLE, and // denormalized descriptors. if (isaPointerOrAllocatable || !normalizedLowerBound(xbox)) @@ -1695,7 +1702,7 @@ struct XReboxOpConversion : public EmboxCommonConversion { // Create new descriptor and fill its non-shape related data. llvm::SmallVector lenParams; mlir::Type inputEleTy = getInputEleTy(rebox); - if (auto charTy = inputEleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(inputEleTy)) { if (charTy.hasConstantLen()) { mlir::Value len = genConstantIndex(loc, idxTy, rewriter, charTy.getLen()); @@ -1712,15 +1719,15 @@ struct XReboxOpConversion : public EmboxCommonConversion { } lenParams.emplace_back(len); } - } else if (auto recTy = inputEleTy.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(inputEleTy)) { if (recTy.getNumLenParams() != 0) TODO(loc, "reboxing descriptor of derived type with length parameters"); } // Rebox on polymorphic entities needs to carry over the dynamic type. mlir::Value typeDescAddr; - if (inputBoxTyPair.fir.isa() && - rebox.getType().isa()) + if (mlir::isa(inputBoxTyPair.fir) && + mlir::isa(rebox.getType())) typeDescAddr = loadTypeDescAddress(loc, inputBoxTyPair, loweredBox, rewriter); @@ -1908,7 +1915,7 @@ private: /// Return scalar element type of the input box. static mlir::Type getInputEleTy(fir::cg::XReboxOp rebox) { auto ty = fir::dyn_cast_ptrOrBoxEleTy(rebox.getBox().getType()); - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return seqTy.getEleTy(); return ty; } @@ -1936,7 +1943,7 @@ struct ValueOpCommon { assert(ty && "type is null"); const auto end = indices.size(); for (std::remove_const_t i = 0; i < end; ++i) { - if (auto seq = ty.dyn_cast()) { + if (auto seq = mlir::dyn_cast(ty)) { const auto dim = getDimension(seq); if (dim > 1) { auto ub = std::min(i + dim, end); @@ -1944,7 +1951,7 @@ struct ValueOpCommon { i += dim - 1; } ty = getArrayElementType(seq); - } else if (auto st = ty.dyn_cast()) { + } else if (auto st = mlir::dyn_cast(ty)) { ty = st.getBody()[indices[i]]; } else { llvm_unreachable("index into invalid type"); @@ -1963,7 +1970,7 @@ struct ValueOpCommon { auto fieldName = i->cast().getValue(); ++i; auto ty = i->cast().getValue(); - auto index = ty.cast().getFieldIndex(fieldName); + auto index = mlir::cast(ty).getFieldIndex(fieldName); indices.push_back(index); } } @@ -1973,7 +1980,7 @@ struct ValueOpCommon { private: static mlir::Type getArrayElementType(mlir::LLVM::LLVMArrayType ty) { auto eleTy = ty.getElementType(); - while (auto arrTy = eleTy.dyn_cast()) + while (auto arrTy = mlir::dyn_cast(eleTy)) eleTy = arrTy.getElementType(); return eleTy; } @@ -2041,7 +2048,7 @@ struct InsertOnRangeOpConversion auto type = adaptor.getOperands()[0].getType(); // Iteratively extract the array dimensions from the type. - while (auto t = type.dyn_cast()) { + while (auto t = mlir::dyn_cast(type)) { dims.push_back(t.getNumElements()); type = t.getElementType(); } @@ -2107,7 +2114,8 @@ struct XArrayCoorOpConversion mlir::Value offset = genConstantIndex(loc, idxTy, rewriter, 0); const bool isShifted = !coor.getShift().empty(); const bool isSliced = !coor.getSlice().empty(); - const bool baseIsBoxed = coor.getMemref().getType().isa(); + const bool baseIsBoxed = + mlir::isa(coor.getMemref().getType()); TypePair baseBoxTyPair = baseIsBoxed ? getBoxTypePair(coor.getMemref().getType()) : TypePair{}; mlir::LLVM::IntegerOverflowFlags nsw = @@ -2185,7 +2193,8 @@ struct XArrayCoorOpConversion // components. mlir::Type elementType = getLlvmObjectTypeFromBoxType(coor.getMemref().getType()); - while (auto arrayTy = elementType.dyn_cast()) + while (auto arrayTy = + mlir::dyn_cast(elementType)) elementType = arrayTy.getElementType(); args.clear(); args.push_back(0); @@ -2275,11 +2284,12 @@ struct CoordinateOpConversion } // Boxed type - get the base pointer from the box - if (baseObjectTy.dyn_cast()) + if (mlir::dyn_cast(baseObjectTy)) return doRewriteBox(coor, operands, loc, rewriter); // Reference, pointer or a heap type - if (baseObjectTy.isa()) + if (mlir::isa( + baseObjectTy)) return doRewriteRefOrPtr(coor, llvmObjectTy, operands, loc, rewriter); return rewriter.notifyMatchFailure( @@ -2295,7 +2305,7 @@ struct CoordinateOpConversion } static bool hasSubDimensions(mlir::Type type) { - return type.isa(); + return mlir::isa(type); } /// Check whether this form of `!fir.coordinate_of` is supported. These @@ -2310,14 +2320,14 @@ struct CoordinateOpConversion bool ptrEle = false; for (; i < numOfCoors; ++i) { mlir::Value nxtOpnd = coors[i]; - if (auto arrTy = type.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(type)) { subEle = true; i += arrTy.getDimension() - 1; type = arrTy.getEleTy(); - } else if (auto recTy = type.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(type)) { subEle = true; type = recTy.getType(getFieldNumber(recTy, nxtOpnd)); - } else if (auto tupTy = type.dyn_cast()) { + } else if (auto tupTy = mlir::dyn_cast(type)) { subEle = true; type = tupTy.getType(getConstantIntValue(nxtOpnd)); } else { @@ -2335,14 +2345,14 @@ struct CoordinateOpConversion static bool arraysHaveKnownShape(mlir::Type type, mlir::ValueRange coors) { for (std::size_t i = 0, sz = coors.size(); i < sz; ++i) { mlir::Value nxtOpnd = coors[i]; - if (auto arrTy = type.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(type)) { if (fir::sequenceWithNonConstantShape(arrTy)) return false; i += arrTy.getDimension() - 1; type = arrTy.getEleTy(); - } else if (auto strTy = type.dyn_cast()) { + } else if (auto strTy = mlir::dyn_cast(type)) { type = strTy.getType(getFieldNumber(strTy, nxtOpnd)); - } else if (auto strTy = type.dyn_cast()) { + } else if (auto strTy = mlir::dyn_cast(type)) { type = strTy.getType(getConstantIntValue(nxtOpnd)); } else { return true; @@ -2357,7 +2367,8 @@ private: mlir::Location loc, mlir::ConversionPatternRewriter &rewriter) const { mlir::Type boxObjTy = coor.getBaseType(); - assert(boxObjTy.dyn_cast() && "This is not a `fir.box`"); + assert(mlir::dyn_cast(boxObjTy) && + "This is not a `fir.box`"); TypePair boxTyPair = getBoxTypePair(boxObjTy); mlir::Value boxBaseAddr = operands[0]; @@ -2399,7 +2410,7 @@ private: mlir::LLVM::IntegerOverflowFlags::nsw; for (unsigned i = 1, last = operands.size(); i < last; ++i) { - if (auto arrTy = cpnTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(cpnTy)) { if (i != 1) TODO(loc, "fir.array nested inside other array and/or derived type"); // Applies byte strides from the box. Ignore lower bound from box @@ -2421,7 +2432,7 @@ private: llvm::ArrayRef{off}); i += arrTy.getDimension() - 1; cpnTy = arrTy.getEleTy(); - } else if (auto recTy = cpnTy.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(cpnTy)) { mlir::Value nxtOpnd = operands[i]; cpnTy = recTy.getType(getFieldNumber(recTy, nxtOpnd)); auto llvmRecTy = lowerTy().convertType(recTy); @@ -2456,7 +2467,7 @@ private: // If only the column is `?`, then we can simply place the column value in // the 0-th GEP position. - if (auto arrTy = cpnTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(cpnTy)) { if (!hasKnownShape) { const unsigned sz = arrTy.getDimension(); if (arraysHaveKnownShape(arrTy.getEleTy(), @@ -2500,29 +2511,29 @@ private: dims = dimsLeft - 1; continue; } - cpnTy = cpnTy.cast().getEleTy(); + cpnTy = mlir::cast(cpnTy).getEleTy(); // append array range in reverse (FIR arrays are column-major) offs.append(arrIdx.rbegin(), arrIdx.rend()); arrIdx.clear(); dims.reset(); continue; } - if (auto arrTy = cpnTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(cpnTy)) { int d = arrTy.getDimension() - 1; if (d > 0) { dims = d; arrIdx.push_back(nxtOpnd); continue; } - cpnTy = cpnTy.cast().getEleTy(); + cpnTy = mlir::cast(cpnTy).getEleTy(); offs.push_back(nxtOpnd); continue; } // check if the i-th coordinate relates to a field - if (auto recTy = cpnTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(cpnTy)) cpnTy = recTy.getType(getFieldNumber(recTy, nxtOpnd)); - else if (auto tupTy = cpnTy.dyn_cast()) + else if (auto tupTy = mlir::dyn_cast(cpnTy)) cpnTy = tupTy.getType(getConstantIntValue(nxtOpnd)); else cpnTy = nullptr; @@ -2551,7 +2562,7 @@ struct FieldIndexOpConversion : public fir::FIROpConversion { mlir::LogicalResult matchAndRewrite(fir::FieldIndexOp field, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { - auto recTy = field.getOnType().cast(); + auto recTy = mlir::cast(field.getOnType()); unsigned index = recTy.getFieldIndex(field.getFieldId()); if (!fir::hasDynamicSize(recTy)) { @@ -2604,8 +2615,8 @@ struct TypeDescOpConversion : public fir::FIROpConversion { matchAndRewrite(fir::TypeDescOp typeDescOp, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { mlir::Type inTy = typeDescOp.getInType(); - assert(inTy.isa() && "expecting fir.type"); - auto recordType = inTy.dyn_cast(); + assert(mlir::isa(inTy) && "expecting fir.type"); + auto recordType = mlir::dyn_cast(inTy); auto module = typeDescOp.getOperation()->getParentOfType(); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recordType.getName()); @@ -2732,7 +2743,7 @@ struct GlobalOpConversion : public fir::FIROpConversion { mlir::Type vecType = mlir::VectorType::get( insertOp.getType().getShape(), constant.getType()); auto denseAttr = mlir::DenseElementsAttr::get( - vecType.cast(), constant.getValue()); + mlir::cast(vecType), constant.getValue()); rewriter.setInsertionPointAfter(insertOp); rewriter.replaceOpWithNewOp( insertOp, seqTyAttr, denseAttr); @@ -2808,7 +2819,7 @@ struct LoadOpConversion : public fir::FIROpConversion { matchAndRewrite(fir::LoadOp load, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { mlir::Type llvmLoadTy = convertObjectType(load.getType()); - if (auto boxTy = load.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(load.getType())) { // fir.box is a special case because it is considered as an ssa values in // fir, but it is lowered as a pointer to a descriptor. So // fir.ref and fir.box end up being the same llvm types and @@ -2921,7 +2932,7 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { llvm::ArrayRef cases = caseOp.getCases().getValue(); // Type can be CHARACTER, INTEGER, or LOGICAL (C1145) auto ty = caseOp.getSelector().getType(); - if (ty.isa()) { + if (mlir::isa(ty)) { TODO(caseOp.getLoc(), "fir.select_case codegen with character type"); return mlir::failure(); } @@ -2935,25 +2946,25 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { *caseOp.getCompareOperands(adaptor.getOperands(), t); mlir::Value caseArg = *(cmpOps.value().begin()); mlir::Attribute attr = cases[t]; - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::eq, selector, caseArg); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, caseArg, selector); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, selector, caseArg); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, caseArg, selector); auto *thisBlock = rewriter.getInsertionBlock(); @@ -2969,7 +2980,7 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { rewriter.setInsertionPointToEnd(newBlock2); continue; } - assert(attr.isa()); + assert(mlir::isa(attr)); assert((t + 1 == conds) && "unit must be last"); genBrOp(caseOp, dest, destOps, rewriter); } @@ -2997,7 +3008,7 @@ static void selectMatchAndRewrite(const fir::LLVMTypeConverter &lowering, mlir::Block *dest = select.getSuccessor(t); auto destOps = select.getSuccessorOperands(adaptor.getOperands(), t); const mlir::Attribute &attr = cases[t]; - if (auto intAttr = attr.template dyn_cast()) { + if (auto intAttr = mlir::dyn_cast(attr)) { destinations.push_back(dest); destinationsOperands.push_back(destOps ? *destOps : mlir::ValueRange{}); caseValues.push_back(intAttr.getInt()); @@ -3071,7 +3082,7 @@ struct StoreOpConversion : public fir::FIROpConversion { mlir::Location loc = store.getLoc(); mlir::Type storeTy = store.getValue().getType(); mlir::LLVM::StoreOp newStoreOp; - if (auto boxTy = storeTy.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(storeTy)) { // fir.box value is actually in memory, load it first before storing it. mlir::Type llvmBoxTy = lowerTy().convertBoxTypeAsStruct(boxTy); auto val = rewriter.create(loc, llvmBoxTy, @@ -3186,9 +3197,9 @@ struct IsPresentOpConversion : public fir::FIROpConversion { mlir::Location loc = isPresent.getLoc(); auto ptr = adaptor.getOperands()[0]; - if (isPresent.getVal().getType().isa()) { + if (mlir::isa(isPresent.getVal().getType())) { [[maybe_unused]] auto structTy = - ptr.getType().cast(); + mlir::cast(ptr.getType()); assert(!structTy.isOpaque() && !structTy.getBody().empty()); ptr = rewriter.create(loc, ptr, 0); @@ -3214,8 +3225,8 @@ struct AbsentOpConversion : public fir::FIROpConversion { mlir::Type ty = convertType(absent.getType()); mlir::Location loc = absent.getLoc(); - if (absent.getType().isa()) { - auto structTy = ty.cast(); + if (mlir::isa(absent.getType())) { + auto structTy = mlir::cast(ty); assert(!structTy.isOpaque() && !structTy.getBody().empty()); auto undefStruct = rewriter.create(loc, ty); auto nullField = diff --git a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp index 26871d888815..00c5f77cde7c 100644 --- a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp +++ b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp @@ -20,7 +20,7 @@ static inline mlir::Type getLlvmPtrType(mlir::MLIRContext *context, } static unsigned getTypeDescFieldId(mlir::Type ty) { - auto isArray = fir::dyn_cast_ptrOrBoxEleTy(ty).isa(); + auto isArray = mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(ty)); return isArray ? kOptTypePtrPosInBox : kDimsPosInBox; } @@ -37,7 +37,7 @@ ConvertFIRToLLVMPattern::ConvertFIRToLLVMPattern( // reference. mlir::Type ConvertFIRToLLVMPattern::convertObjectType(mlir::Type firType) const { - if (auto boxTy = firType.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(firType)) return lowerTy().convertBoxTypeAsStruct(boxTy); return lowerTy().convertType(firType); } @@ -69,7 +69,7 @@ ConvertFIRToLLVMPattern::integerCast(mlir::Location loc, auto valTy = val.getType(); // If the value was not yet lowered, lower its type so that it can // be used in getPrimitiveTypeSizeInBits. - if (!valTy.isa()) + if (!mlir::isa(valTy)) valTy = convertType(valTy); auto toSize = mlir::LLVM::getPrimitiveTypeSizeInBits(ty); auto fromSize = mlir::LLVM::getPrimitiveTypeSizeInBits(valTy); @@ -91,7 +91,7 @@ ConvertFIRToLLVMPattern::getBoxTypePair(mlir::Type firBoxTy) const { mlir::Value ConvertFIRToLLVMPattern::getValueFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, mlir::Type resultTy, mlir::ConversionPatternRewriter &rewriter, int boxValue) const { - if (box.getType().isa()) { + if (mlir::isa(box.getType())) { auto pty = getLlvmPtrType(resultTy.getContext()); auto p = rewriter.create( loc, pty, boxTy.llvm, box, @@ -133,7 +133,7 @@ llvm::SmallVector ConvertFIRToLLVMPattern::getDimsFromBox( mlir::Value ConvertFIRToLLVMPattern::loadDimFieldFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, mlir::Value dim, int off, mlir::Type ty, mlir::ConversionPatternRewriter &rewriter) const { - assert(box.getType().isa() && + assert(mlir::isa(box.getType()) && "descriptor inquiry with runtime dim can only be done on descriptor " "in memory"); mlir::LLVM::GEPOp p = genGEP(loc, boxTy.llvm, rewriter, box, 0, @@ -146,7 +146,7 @@ mlir::Value ConvertFIRToLLVMPattern::loadDimFieldFromBox( mlir::Value ConvertFIRToLLVMPattern::getDimFieldFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, int dim, int off, mlir::Type ty, mlir::ConversionPatternRewriter &rewriter) const { - if (box.getType().isa()) { + if (mlir::isa(box.getType())) { mlir::LLVM::GEPOp p = genGEP(loc, boxTy.llvm, rewriter, box, 0, static_cast(kDimsPosInBox), dim, off); auto loadOp = rewriter.create(loc, ty, p); @@ -184,12 +184,12 @@ mlir::Value ConvertFIRToLLVMPattern::getElementSizeFromBox( mlir::Type ConvertFIRToLLVMPattern::getBoxEleTy( mlir::Type type, llvm::ArrayRef indexes) const { for (unsigned i : indexes) { - if (auto t = type.dyn_cast()) { + if (auto t = mlir::dyn_cast(type)) { assert(!t.isOpaque() && i < t.getBody().size()); type = t.getBody()[i]; - } else if (auto t = type.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(type)) { type = t.getElementType(); - } else if (auto t = type.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(type)) { type = t.getElementType(); } else { fir::emitFatalError(mlir::UnknownLoc::get(type.getContext()), diff --git a/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp b/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp index 665bf09b8fc3..ce7ee22d5d77 100644 --- a/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp +++ b/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp @@ -86,10 +86,10 @@ public: // If the embox does not include a shape, then do not convert it if (auto shapeVal = embox.getShape()) return rewriteDynamicShape(embox, rewriter, shapeVal); - if (embox.getType().isa()) + if (mlir::isa(embox.getType())) TODO(embox.getLoc(), "embox conversion for fir.class type"); - if (auto boxTy = embox.getType().dyn_cast()) - if (auto seqTy = boxTy.getEleTy().dyn_cast()) + if (auto boxTy = mlir::dyn_cast(embox.getType())) + if (auto seqTy = mlir::dyn_cast(boxTy.getEleTy())) if (!seqTy.hasDynamicExtents()) return rewriteStaticShape(embox, rewriter, seqTy); return mlir::failure(); @@ -294,10 +294,9 @@ public: target.addIllegalOp(); target.addIllegalOp(); target.addDynamicallyLegalOp([](fir::EmboxOp embox) { - return !(embox.getShape() || embox.getType() - .cast() - .getEleTy() - .isa()); + return !(embox.getShape() || + mlir::isa( + mlir::cast(embox.getType()).getEleTy())); }); mlir::RewritePatternSet patterns(&context); fir::populatePreCGRewritePatterns(patterns); diff --git a/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp b/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp index b1b0e9b766a6..a21384e8d594 100644 --- a/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp +++ b/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp @@ -120,7 +120,7 @@ void TBAABuilder::attachTBAATag(AliasAnalysisOpInterface op, Type baseFIRType, // with both data and descriptor accesses. // Conservatively set any-access tag if there is any descriptor member. tbaaTagSym = getAnyAccessTag(func); - } else if (baseFIRType.isa()) { + } else if (mlir::isa(baseFIRType)) { tbaaTagSym = getBoxAccessTag(baseFIRType, accessFIRType, gep, func); } else { tbaaTagSym = getDataAccessTag(baseFIRType, accessFIRType, gep, func); diff --git a/flang/lib/Optimizer/CodeGen/Target.cpp b/flang/lib/Optimizer/CodeGen/Target.cpp index cea7a1f97f41..652e2bddc1b8 100644 --- a/flang/lib/Optimizer/CodeGen/Target.cpp +++ b/flang/lib/Optimizer/CodeGen/Target.cpp @@ -41,9 +41,9 @@ llvm::StringRef Attributes::getIntExtensionAttrName() const { static const llvm::fltSemantics &floatToSemantics(const KindMapping &kindMap, mlir::Type type) { assert(isa_real(type)); - if (auto ty = type.dyn_cast()) + if (auto ty = mlir::dyn_cast(type)) return kindMap.getFloatSemantics(ty.getFKind()); - return type.cast().getFloatSemantics(); + return mlir::cast(type).getFloatSemantics(); } static void typeTodo(const llvm::fltSemantics *sem, mlir::Location loc, diff --git a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp index 7bf31ec38695..616de78d0026 100644 --- a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp +++ b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp @@ -137,7 +137,7 @@ public: if (!hasPortableSignature(dispatch.getFunctionType(), op)) convertCallOp(dispatch); } else if (auto addr = mlir::dyn_cast(op)) { - if (addr.getType().isa() && + if (mlir::isa(addr.getType()) && !hasPortableSignature(addr.getType(), op)) convertAddrOp(addr); } @@ -601,7 +601,7 @@ public: /// Taking the address of a function. Modify the signature as needed. void convertAddrOp(fir::AddrOfOp addrOp) { rewriter->setInsertionPoint(addrOp); - auto addrTy = addrOp.getType().cast(); + auto addrTy = mlir::cast(addrOp.getType()); fir::CodeGenSpecifics::Marshalling newInTyAndAttrs; llvm::SmallVector newResTys; auto loc = addrOp.getLoc(); @@ -705,22 +705,23 @@ public: /// return `true`. Otherwise, the signature is not portable and `false` is /// returned. bool hasPortableSignature(mlir::Type signature, mlir::Operation *op) { - assert(signature.isa()); - auto func = signature.dyn_cast(); + assert(mlir::isa(signature)); + auto func = mlir::dyn_cast(signature); bool hasCCallingConv = isFuncWithCCallingConvention(op); for (auto ty : func.getResults()) - if ((ty.isa() && !noCharacterConversion) || + if ((mlir::isa(ty) && !noCharacterConversion) || (fir::isa_complex(ty) && !noComplexConversion) || - (ty.isa() && hasCCallingConv)) { + (mlir::isa(ty) && hasCCallingConv)) { LLVM_DEBUG(llvm::dbgs() << "rewrite " << signature << " for target\n"); return false; } for (auto ty : func.getInputs()) - if (((ty.isa() || fir::isCharacterProcedureTuple(ty)) && + if (((mlir::isa(ty) || + fir::isCharacterProcedureTuple(ty)) && !noCharacterConversion) || (fir::isa_complex(ty) && !noComplexConversion) || - (ty.isa() && hasCCallingConv) || - (ty.isa() && !noStructConversion)) { + (mlir::isa(ty) && hasCCallingConv) || + (mlir::isa(ty) && !noStructConversion)) { LLVM_DEBUG(llvm::dbgs() << "rewrite " << signature << " for target\n"); return false; } @@ -740,7 +741,7 @@ public: /// Rewrite the signatures and body of the `FuncOp`s in the module for /// the immediately subsequent target code gen. void convertSignature(mlir::func::FuncOp func) { - auto funcTy = func.getFunctionType().cast(); + auto funcTy = mlir::cast(func.getFunctionType()); if (hasPortableSignature(funcTy, func) && !hasHostAssociations(func)) return; llvm::SmallVector newResTys; diff --git a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp index 8fa423f35806..fb2ec3f0b2f5 100644 --- a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp +++ b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp @@ -103,10 +103,10 @@ LLVMTypeConverter::LLVMTypeConverter(mlir::ModuleOp module, bool applyTBAA, for (auto mem : tuple.getTypes()) { // Prevent fir.box from degenerating to a pointer to a descriptor in the // context of a tuple type. - if (auto box = mem.dyn_cast()) + if (auto box = mlir::dyn_cast(mem)) members.push_back(convertBoxTypeAsStruct(box)); else - members.push_back(convertType(mem).cast()); + members.push_back(mlir::cast(convertType(mem))); } return mlir::LLVM::LLVMStructType::getLiteral(&getContext(), members, /*isPacked=*/false); @@ -181,10 +181,10 @@ std::optional LLVMTypeConverter::convertRecordType( for (auto mem : derived.getTypeList()) { // Prevent fir.box from degenerating to a pointer to a descriptor in the // context of a record type. - if (auto box = mem.second.dyn_cast()) + if (auto box = mlir::dyn_cast(mem.second)) members.push_back(convertBoxTypeAsStruct(box)); else - members.push_back(convertType(mem.second).cast()); + members.push_back(mlir::cast(convertType(mem.second))); } if (mlir::failed(st.setBody(members, /*isPacked=*/false))) return mlir::failure(); @@ -196,7 +196,7 @@ std::optional LLVMTypeConverter::convertRecordType( // Extended descriptors are required for derived types. bool LLVMTypeConverter::requiresExtendedDesc(mlir::Type boxElementType) const { auto eleTy = fir::unwrapSequenceType(boxElementType); - return eleTy.isa(); + return mlir::isa(eleTy); } // This corresponds to the descriptor as defined in ISO_Fortran_binding.h and @@ -211,7 +211,8 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, ele = removeIndirection; auto eleTy = convertType(ele); // base_addr* - if (ele.isa() && eleTy.isa()) + if (mlir::isa(ele) && + mlir::isa(eleTy)) dataDescFields.push_back(eleTy); else dataDescFields.push_back( @@ -236,7 +237,7 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, getDescFieldTypeModel()(&getContext())); // [dims] if (rank == unknownRank()) { - if (auto seqTy = ele.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ele)) rank = seqTy.getDimension(); else rank = 0; @@ -252,7 +253,8 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, auto rowTy = getExtendedDescFieldTypeModel()(&getContext()); dataDescFields.push_back(mlir::LLVM::LLVMArrayType::get(rowTy, 1)); - if (auto recTy = fir::unwrapSequenceType(ele).dyn_cast()) + if (auto recTy = + mlir::dyn_cast(fir::unwrapSequenceType(ele))) if (recTy.getNumLenParams() > 0) { // The descriptor design needs to be clarified regarding the number of // length parameters in the addendum. Since it can change for diff --git a/flang/lib/Optimizer/Dialect/FIRAttr.cpp b/flang/lib/Optimizer/Dialect/FIRAttr.cpp index e43710f5627e..9ea3a0568f69 100644 --- a/flang/lib/Optimizer/Dialect/FIRAttr.cpp +++ b/flang/lib/Optimizer/Dialect/FIRAttr.cpp @@ -264,23 +264,23 @@ void fir::FortranVariableFlagsAttr::print(mlir::AsmPrinter &printer) const { void fir::printFirAttribute(FIROpsDialect *dialect, mlir::Attribute attr, mlir::DialectAsmPrinter &p) { auto &os = p.getStream(); - if (auto exact = attr.dyn_cast()) { + if (auto exact = mlir::dyn_cast(attr)) { os << fir::ExactTypeAttr::getAttrName() << '<'; p.printType(exact.getType()); os << '>'; - } else if (auto sub = attr.dyn_cast()) { + } else if (auto sub = mlir::dyn_cast(attr)) { os << fir::SubclassAttr::getAttrName() << '<'; p.printType(sub.getType()); os << '>'; - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::PointIntervalAttr::getAttrName(); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::ClosedIntervalAttr::getAttrName(); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::LowerBoundAttr::getAttrName(); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::UpperBoundAttr::getAttrName(); - } else if (auto a = attr.dyn_cast_or_null()) { + } else if (auto a = mlir::dyn_cast_or_null(attr)) { os << fir::RealAttr::getAttrName() << '<' << a.getFKind() << ", i x"; llvm::SmallString<40> ss; a.getValue().bitcastToAPInt().toStringUnsigned(ss, 16); diff --git a/flang/lib/Optimizer/Dialect/FIROps.cpp b/flang/lib/Optimizer/Dialect/FIROps.cpp index 24af94f9b90a..a39087aeb358 100644 --- a/flang/lib/Optimizer/Dialect/FIROps.cpp +++ b/flang/lib/Optimizer/Dialect/FIROps.cpp @@ -57,7 +57,7 @@ static void propagateAttributes(mlir::Operation *fromOp, static bool verifyInType(mlir::Type inType, llvm::SmallVectorImpl &visited, unsigned dynamicExtents = 0) { - if (auto st = inType.dyn_cast()) { + if (auto st = mlir::dyn_cast(inType)) { auto shape = st.getShape(); if (shape.size() == 0) return true; @@ -67,7 +67,7 @@ static bool verifyInType(mlir::Type inType, if (dynamicExtents-- == 0) return true; } - } else if (auto rt = inType.dyn_cast()) { + } else if (auto rt = mlir::dyn_cast(inType)) { // don't recurse if we're already visiting this one if (llvm::is_contained(visited, rt.getName())) return false; @@ -84,13 +84,13 @@ static bool verifyInType(mlir::Type inType, static bool verifyTypeParamCount(mlir::Type inType, unsigned numParams) { auto ty = fir::unwrapSequenceType(inType); if (numParams > 0) { - if (auto recTy = ty.dyn_cast()) + if (auto recTy = mlir::dyn_cast(ty)) return numParams != recTy.getNumLenParams(); - if (auto chrTy = ty.dyn_cast()) + if (auto chrTy = mlir::dyn_cast(ty)) return !(numParams == 1 && chrTy.hasDynamicLen()); return true; } - if (auto chrTy = ty.dyn_cast()) + if (auto chrTy = mlir::dyn_cast(ty)) return !chrTy.hasConstantLen(); return false; } @@ -171,13 +171,13 @@ static void printAllocatableOp(mlir::OpAsmPrinter &p, OP &op) { /// Create a legal memory reference as return type static mlir::Type wrapAllocaResultType(mlir::Type intype) { // FIR semantics: memory references to memory references are disallowed - if (intype.isa()) + if (mlir::isa(intype)) return {}; return fir::ReferenceType::get(intype); } mlir::Type fir::AllocaOp::getAllocatedType() { - return getType().cast().getEleTy(); + return mlir::cast(getType()).getEleTy(); } mlir::Type fir::AllocaOp::getRefTy(mlir::Type ty) { @@ -270,7 +270,7 @@ mlir::LogicalResult fir::AllocaOp::verify() { if (verifyTypeParamCount(getInType(), numLenParams())) return emitOpError("LEN params do not correspond to type"); mlir::Type outType = getType(); - if (!outType.isa()) + if (!mlir::isa(outType)) return emitOpError("must be a !fir.ref type"); if (fir::isa_unknown_size_box(fir::dyn_cast_ptrEleTy(outType))) return emitOpError("cannot allocate !fir.box of unknown rank or type"); @@ -286,14 +286,14 @@ static mlir::Type wrapAllocMemResultType(mlir::Type intype) { // Fortran semantics: C852 an entity cannot be both ALLOCATABLE and POINTER // 8.5.3 note 1 prohibits ALLOCATABLE procedures as well // FIR semantics: one may not allocate a memory reference value - if (intype.isa()) + if (mlir::isa(intype)) return {}; return fir::HeapType::get(intype); } mlir::Type fir::AllocMemOp::getAllocatedType() { - return getType().cast().getEleTy(); + return mlir::cast(getType()).getEleTy(); } mlir::Type fir::AllocMemOp::getRefTy(mlir::Type ty) { @@ -348,7 +348,7 @@ mlir::LogicalResult fir::AllocMemOp::verify() { if (verifyTypeParamCount(getInType(), numLenParams())) return emitOpError("LEN params do not correspond to type"); mlir::Type outType = getType(); - if (!outType.dyn_cast()) + if (!mlir::dyn_cast(outType)) return emitOpError("must be a !fir.heap type"); if (fir::isa_unknown_size_box(fir::dyn_cast_ptrEleTy(outType))) return emitOpError("cannot allocate !fir.box of unknown rank or type"); @@ -364,13 +364,13 @@ mlir::LogicalResult fir::AllocMemOp::verify() { static bool validTypeParams(mlir::Type dynTy, mlir::ValueRange typeParams) { dynTy = fir::unwrapAllRefAndSeqType(dynTy); // A box value will contain type parameter values itself. - if (dynTy.isa()) + if (mlir::isa(dynTy)) return typeParams.size() == 0; // Derived type must have all type parameters satisfied. - if (auto recTy = dynTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(dynTy)) return typeParams.size() == recTy.getNumLenParams(); // Characters with non-constant LEN must have a type parameter value. - if (auto charTy = dynTy.dyn_cast()) + if (auto charTy = mlir::dyn_cast(dynTy)) if (charTy.hasDynamicLen()) return typeParams.size() == 1; // Otherwise, any type parameters are invalid. @@ -379,7 +379,7 @@ static bool validTypeParams(mlir::Type dynTy, mlir::ValueRange typeParams) { mlir::LogicalResult fir::ArrayCoorOp::verify() { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - auto arrTy = eleTy.dyn_cast(); + auto arrTy = mlir::dyn_cast(eleTy); if (!arrTy) return emitOpError("must be a reference to an array"); auto arrDim = arrTy.getDimension(); @@ -387,14 +387,14 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { if (auto shapeOp = getShape()) { auto shapeTy = shapeOp.getType(); unsigned shapeTyRank = 0; - if (auto s = shapeTy.dyn_cast()) { + if (auto s = mlir::dyn_cast(shapeTy)) { shapeTyRank = s.getRank(); - } else if (auto ss = shapeTy.dyn_cast()) { + } else if (auto ss = mlir::dyn_cast(shapeTy)) { shapeTyRank = ss.getRank(); } else { - auto s = shapeTy.cast(); + auto s = mlir::cast(shapeTy); shapeTyRank = s.getRank(); - if (!getMemref().getType().isa()) + if (!mlir::isa(getMemref().getType())) return emitOpError("shift can only be provided with fir.box memref"); } if (arrDim && arrDim != shapeTyRank) @@ -407,7 +407,7 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { if (auto sl = mlir::dyn_cast_or_null(sliceOp.getDefiningOp())) if (!sl.getSubstr().empty()) return emitOpError("array_coor cannot take a slice with substring"); - if (auto sliceTy = sliceOp.getType().dyn_cast()) + if (auto sliceTy = mlir::dyn_cast(sliceOp.getType())) if (sliceTy.getRank() != arrDim) return emitOpError("rank of dimension in slice mismatched"); } @@ -422,13 +422,13 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { //===----------------------------------------------------------------------===// static mlir::Type adjustedElementType(mlir::Type t) { - if (auto ty = t.dyn_cast()) { + if (auto ty = mlir::dyn_cast(t)) { auto eleTy = ty.getEleTy(); if (fir::isa_char(eleTy)) return eleTy; if (fir::isa_derived(eleTy)) return eleTy; - if (eleTy.isa()) + if (mlir::isa(eleTy)) return eleTy; } return t; @@ -448,7 +448,7 @@ std::vector fir::ArrayLoadOp::getExtents() { mlir::LogicalResult fir::ArrayLoadOp::verify() { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - auto arrTy = eleTy.dyn_cast(); + auto arrTy = mlir::dyn_cast(eleTy); if (!arrTy) return emitOpError("must be a reference to an array"); auto arrDim = arrTy.getDimension(); @@ -456,14 +456,14 @@ mlir::LogicalResult fir::ArrayLoadOp::verify() { if (auto shapeOp = getShape()) { auto shapeTy = shapeOp.getType(); unsigned shapeTyRank = 0u; - if (auto s = shapeTy.dyn_cast()) { + if (auto s = mlir::dyn_cast(shapeTy)) { shapeTyRank = s.getRank(); - } else if (auto ss = shapeTy.dyn_cast()) { + } else if (auto ss = mlir::dyn_cast(shapeTy)) { shapeTyRank = ss.getRank(); } else { - auto s = shapeTy.cast(); + auto s = mlir::cast(shapeTy); shapeTyRank = s.getRank(); - if (!getMemref().getType().isa()) + if (!mlir::isa(getMemref().getType())) return emitOpError("shift can only be provided with fir.box memref"); } if (arrDim && arrDim != shapeTyRank) @@ -474,7 +474,7 @@ mlir::LogicalResult fir::ArrayLoadOp::verify() { if (auto sl = mlir::dyn_cast_or_null(sliceOp.getDefiningOp())) if (!sl.getSubstr().empty()) return emitOpError("array_load cannot take a slice with substring"); - if (auto sliceTy = sliceOp.getType().dyn_cast()) + if (auto sliceTy = mlir::dyn_cast(sliceOp.getType())) if (sliceTy.getRank() != arrDim) return emitOpError("rank of dimension in slice mismatched"); } @@ -502,7 +502,7 @@ mlir::LogicalResult fir::ArrayMergeStoreOp::verify() { // This is an intra-object merge, where the slice is projecting the // subfields that are to be overwritten by the merge operation. auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - if (auto seqTy = eleTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(eleTy)) { auto projTy = fir::applyPathToType(seqTy.getEleTy(), sliceOp.getFields()); if (fir::unwrapSequenceType(getOriginal().getType()) != projTy) @@ -540,7 +540,7 @@ mlir::Type validArraySubobject(A op) { } mlir::LogicalResult fir::ArrayFetchOp::verify() { - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -562,7 +562,7 @@ mlir::LogicalResult fir::ArrayFetchOp::verify() { //===----------------------------------------------------------------------===// mlir::LogicalResult fir::ArrayAccessOp::verify() { - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); std::size_t indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -584,7 +584,7 @@ mlir::LogicalResult fir::ArrayAccessOp::verify() { mlir::LogicalResult fir::ArrayUpdateOp::verify() { if (fir::isa_ref_type(getMerge().getType())) return emitOpError("does not support reference type for merge"); - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -604,7 +604,7 @@ mlir::LogicalResult fir::ArrayUpdateOp::verify() { //===----------------------------------------------------------------------===// mlir::LogicalResult fir::ArrayModifyOp::verify() { - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices must match array dimension"); @@ -740,7 +740,7 @@ mlir::ParseResult fir::CallOp::parse(mlir::OpAsmParser &parser, parser.parseType(type)) return mlir::failure(); - auto funcType = type.dyn_cast(); + auto funcType = mlir::dyn_cast(type); if (!funcType) return parser.emitError(parser.getNameLoc(), "expected function type"); if (isDirect) { @@ -785,7 +785,7 @@ void fir::CallOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, mlir::LogicalResult fir::CharConvertOp::verify() { auto unwrap = [&](mlir::Type t) { t = fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t)); - return t.dyn_cast(); + return mlir::dyn_cast(t); }; auto inTy = unwrap(getFrom().getType()); auto outTy = unwrap(getTo().getType()); @@ -832,13 +832,13 @@ static mlir::ParseResult parseCmpOp(mlir::OpAsmParser &parser, parser.resolveOperands(ops, type, result.operands)) return mlir::failure(); - if (!predicateNameAttr.isa()) + if (!mlir::isa(predicateNameAttr)) return parser.emitError(parser.getNameLoc(), "expected string comparison predicate attribute"); // Rewrite string attribute to an enum value. llvm::StringRef predicateName = - predicateNameAttr.cast().getValue(); + mlir::cast(predicateNameAttr).getValue(); auto predicate = fir::CmpcOp::getPredicateByName(predicateName); auto builder = parser.getBuilder(); mlir::Type i1Type = builder.getI1Type(); @@ -906,7 +906,7 @@ void fir::ConstcOp::print(mlir::OpAsmPrinter &p) { } mlir::LogicalResult fir::ConstcOp::verify() { - if (!getType().isa()) + if (!mlir::isa(getType())) return emitOpError("must be a !fir.complex type"); return mlir::success(); } @@ -929,15 +929,16 @@ mlir::OpFoldResult fir::ConvertOp::fold(FoldAdaptor adaptor) { if (matchPattern(getValue(), mlir::m_Op())) { auto inner = mlir::cast(getValue().getDefiningOp()); // (convert (convert 'a : logical -> i1) : i1 -> logical) ==> forward 'a - if (auto toTy = getType().dyn_cast()) - if (auto fromTy = inner.getValue().getType().dyn_cast()) - if (inner.getType().isa() && (toTy == fromTy)) + if (auto toTy = mlir::dyn_cast(getType())) + if (auto fromTy = + mlir::dyn_cast(inner.getValue().getType())) + if (mlir::isa(inner.getType()) && (toTy == fromTy)) return inner.getValue(); // (convert (convert 'a : i1 -> logical) : logical -> i1) ==> forward 'a - if (auto toTy = getType().dyn_cast()) + if (auto toTy = mlir::dyn_cast(getType())) if (auto fromTy = - inner.getValue().getType().dyn_cast()) - if (inner.getType().isa() && (toTy == fromTy) && + mlir::dyn_cast(inner.getValue().getType())) + if (mlir::isa(inner.getType()) && (toTy == fromTy) && (fromTy.getWidth() == 1)) return inner.getValue(); } @@ -945,7 +946,7 @@ mlir::OpFoldResult fir::ConvertOp::fold(FoldAdaptor adaptor) { } bool fir::ConvertOp::isInteger(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } bool fir::ConvertOp::isIntegerCompatible(mlir::Type ty) { @@ -953,13 +954,13 @@ bool fir::ConvertOp::isIntegerCompatible(mlir::Type ty) { } bool fir::ConvertOp::isFloatCompatible(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } bool fir::ConvertOp::isPointerCompatible(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } static std::optional getVectorElementType(mlir::Type ty) { @@ -1026,12 +1027,14 @@ bool fir::ConvertOp::canBeConverted(mlir::Type inType, mlir::Type outType) { (isFloatCompatible(inType) && isFloatCompatible(outType)) || (isIntegerCompatible(inType) && isPointerCompatible(outType)) || (isPointerCompatible(inType) && isIntegerCompatible(outType)) || - (inType.isa() && outType.isa()) || - (inType.isa() && outType.isa()) || + (mlir::isa(inType) && + mlir::isa(outType)) || + (mlir::isa(inType) && + mlir::isa(outType)) || (fir::isa_complex(inType) && fir::isa_complex(outType)) || (fir::isBoxedRecordType(inType) && fir::isPolymorphicType(outType)) || (fir::isPolymorphicType(inType) && fir::isPolymorphicType(outType)) || - (fir::isPolymorphicType(inType) && outType.isa()) || + (fir::isPolymorphicType(inType) && mlir::isa(outType)) || areVectorsCompatible(inType, outType); } @@ -1079,7 +1082,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { const mlir::Type refTy = getRef().getType(); if (fir::isa_ref_type(refTy)) { auto eleTy = fir::dyn_cast_ptrEleTy(refTy); - if (auto arrTy = eleTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(eleTy)) { if (arrTy.hasUnknownShape()) return emitOpError("cannot find coordinate in unknown shape"); if (arrTy.getConstantRows() < arrTy.getDimension() - 1) @@ -1094,8 +1097,8 @@ mlir::LogicalResult fir::CoordinateOp::verify() { const unsigned numCoors = getCoor().size(); for (auto coorOperand : llvm::enumerate(getCoor())) { auto co = coorOperand.value(); - if (dimension == 0 && eleTy.isa()) { - dimension = eleTy.cast().getDimension(); + if (dimension == 0 && mlir::isa(eleTy)) { + dimension = mlir::cast(eleTy).getDimension(); if (dimension == 0) return emitOpError("cannot apply to array of unknown rank"); } @@ -1104,7 +1107,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { // Recovering a LEN type parameter only makes sense from a boxed // value. For a bare reference, the LEN type parameters must be // passed as additional arguments to `index`. - if (refTy.isa()) { + if (mlir::isa(refTy)) { if (coorOperand.index() != numCoors - 1) return emitOpError("len_param_index must be last argument"); if (getNumOperands() != 2) @@ -1117,7 +1120,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { } else if (auto index = mlir::dyn_cast(defOp)) { if (eleTy != index.getOnType()) emitOpError("field_index type not compatible with reference type"); - if (auto recTy = eleTy.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(eleTy)) { eleTy = recTy.getType(index.getFieldName()); continue; } @@ -1126,21 +1129,21 @@ mlir::LogicalResult fir::CoordinateOp::verify() { } if (dimension) { if (--dimension == 0) - eleTy = eleTy.cast().getEleTy(); + eleTy = mlir::cast(eleTy).getEleTy(); } else { - if (auto t = eleTy.dyn_cast()) { + if (auto t = mlir::dyn_cast(eleTy)) { // FIXME: Generally, we don't know which field of the tuple is being // referred to unless the operand is a constant. Just assume everything // is good in the tuple case for now. return mlir::success(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { // FIXME: This is the same as the tuple case. return mlir::success(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { eleTy = t.getElementType(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { eleTy = t.getElementType(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { if (t.getLen() == fir::CharacterType::singleton()) return emitOpError("cannot apply to character singleton"); eleTy = fir::CharacterType::getSingleton(t.getContext(), t.getFKind()); @@ -1216,17 +1219,17 @@ mlir::LogicalResult fir::TypeInfoOp::verify() { mlir::LogicalResult fir::EmboxOp::verify() { auto eleTy = fir::dyn_cast_ptrEleTy(getMemref().getType()); bool isArray = false; - if (auto seqTy = eleTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(eleTy)) { eleTy = seqTy.getEleTy(); isArray = true; } if (hasLenParams()) { auto lenPs = numLenParams(); - if (auto rt = eleTy.dyn_cast()) { + if (auto rt = mlir::dyn_cast(eleTy)) { if (lenPs != rt.getNumLenParams()) return emitOpError("number of LEN params does not correspond" " to the !fir.type type"); - } else if (auto strTy = eleTy.dyn_cast()) { + } else if (auto strTy = mlir::dyn_cast(eleTy)) { if (strTy.getLen() != fir::CharacterType::unknownLen()) return emitOpError("CHARACTER already has static LEN"); } else { @@ -1240,7 +1243,7 @@ mlir::LogicalResult fir::EmboxOp::verify() { return emitOpError("shape must not be provided for a scalar"); if (getSlice() && !isArray) return emitOpError("slice must not be provided for a scalar"); - if (getSourceBox() && !getResult().getType().isa()) + if (getSourceBox() && !mlir::isa(getResult().getType())) return emitOpError("source_box must be used with fir.class result type"); return mlir::success(); } @@ -1251,7 +1254,7 @@ mlir::LogicalResult fir::EmboxOp::verify() { mlir::LogicalResult fir::EmboxCharOp::verify() { auto eleTy = fir::dyn_cast_ptrEleTy(getMemref().getType()); - if (!eleTy.dyn_cast_or_null()) + if (!mlir::dyn_cast_or_null(eleTy)) return mlir::failure(); return mlir::success(); } @@ -1263,8 +1266,8 @@ mlir::LogicalResult fir::EmboxCharOp::verify() { mlir::LogicalResult fir::EmboxProcOp::verify() { // host bindings (optional) must be a reference to a tuple if (auto h = getHost()) { - if (auto r = h.getType().dyn_cast()) - if (r.getEleTy().isa()) + if (auto r = mlir::dyn_cast(h.getType())) + if (mlir::isa(r.getEleTy())) return mlir::success(); return mlir::failure(); } @@ -1300,7 +1303,7 @@ void fir::TypeDescOp::print(mlir::OpAsmPrinter &p) { mlir::LogicalResult fir::TypeDescOp::verify() { mlir::Type resultTy = getType(); - if (auto tdesc = resultTy.dyn_cast()) { + if (auto tdesc = mlir::dyn_cast(resultTy)) { if (tdesc.getOfTy() != getInType()) return emitOpError("wrapped type mismatched"); return mlir::success(); @@ -1527,7 +1530,7 @@ mlir::ParseResult parseFieldLikeOp(mlir::OpAsmParser &parser, return mlir::failure(); result.addAttribute(fir::FieldIndexOp::getFieldAttrName(), builder.getStringAttr(fieldName)); - if (!recty.dyn_cast()) + if (!mlir::dyn_cast(recty)) return mlir::failure(); result.addAttribute(fir::FieldIndexOp::getTypeAttrName(), mlir::TypeAttr::get(recty)); @@ -1671,7 +1674,7 @@ mlir::LogicalResult fir::InsertOnRangeOp::verify() { //===----------------------------------------------------------------------===// static bool checkIsIntegerConstant(mlir::Attribute attr, std::int64_t conVal) { - if (auto iattr = attr.dyn_cast()) + if (auto iattr = mlir::dyn_cast(attr)) return iattr.getInt() == conVal; return false; } @@ -1690,7 +1693,7 @@ struct UndoComplexPattern : public mlir::RewritePattern { matchAndRewrite(mlir::Operation *op, mlir::PatternRewriter &rewriter) const override { auto insval = mlir::dyn_cast_or_null(op); - if (!insval || !insval.getType().isa()) + if (!insval || !mlir::isa(insval.getType())) return mlir::failure(); auto insval2 = mlir::dyn_cast_or_null( insval.getAdt().getDefiningOp()); @@ -1819,7 +1822,7 @@ mlir::ParseResult fir::IterWhileOp::parse(mlir::OpAsmParser &parser, parser.parseRParen()) return mlir::failure(); // Type list must be "(index, i1)". - if (typeList.size() != 2 || !typeList[0].isa() || + if (typeList.size() != 2 || !mlir::isa(typeList[0]) || !typeList[1].isSignlessInteger(1)) return mlir::failure(); result.addTypes(typeList); @@ -1873,7 +1876,7 @@ mlir::LogicalResult fir::IterWhileOp::verify() { auto opNumResults = getNumResults(); if (getFinalValue()) { // Result type must be "(index, i1, ...)". - if (!getResult(0).getType().isa()) + if (!mlir::isa(getResult(0).getType())) return emitOpError("result #0 expected to be index"); if (!getResult(1).getType().isSignlessInteger(1)) return emitOpError("result #1 expected to be i1"); @@ -2316,7 +2319,7 @@ void fir::DTEntryOp::print(mlir::OpAsmPrinter &p) { /// Example: return f32 for !fir.box>. static mlir::Type getBoxScalarEleTy(mlir::Type boxTy) { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(boxTy); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); return eleTy; } @@ -2324,8 +2327,8 @@ static mlir::Type getBoxScalarEleTy(mlir::Type boxTy) { /// Test if \p t1 and \p t2 are compatible character types (if they can /// represent the same type at runtime). static bool areCompatibleCharacterTypes(mlir::Type t1, mlir::Type t2) { - auto c1 = t1.dyn_cast(); - auto c2 = t2.dyn_cast(); + auto c1 = mlir::dyn_cast(t1); + auto c2 = mlir::dyn_cast(t2); if (!c1 || !c2) return false; if (c1.hasDynamicLen() || c2.hasDynamicLen()) @@ -2347,10 +2350,10 @@ mlir::LogicalResult fir::ReboxOp::verify() { if (auto sliceVal = getSlice()) { // Slicing case - if (sliceVal.getType().cast().getRank() != inputRank) + if (mlir::cast(sliceVal.getType()).getRank() != inputRank) return emitOpError("slice operand rank must match box operand rank"); if (auto shapeVal = getShape()) { - if (auto shiftTy = shapeVal.getType().dyn_cast()) { + if (auto shiftTy = mlir::dyn_cast(shapeVal.getType())) { if (shiftTy.getRank() != inputRank) return emitOpError("shape operand and input box ranks must match " "when there is a slice"); @@ -2370,12 +2373,12 @@ mlir::LogicalResult fir::ReboxOp::verify() { unsigned shapeRank = inputRank; if (auto shapeVal = getShape()) { auto ty = shapeVal.getType(); - if (auto shapeTy = ty.dyn_cast()) { + if (auto shapeTy = mlir::dyn_cast(ty)) { shapeRank = shapeTy.getRank(); - } else if (auto shapeShiftTy = ty.dyn_cast()) { + } else if (auto shapeShiftTy = mlir::dyn_cast(ty)) { shapeRank = shapeShiftTy.getRank(); } else { - auto shiftTy = ty.cast(); + auto shiftTy = mlir::cast(ty); shapeRank = shiftTy.getRank(); if (shapeRank != inputRank) return emitOpError("shape operand and input box ranks must match " @@ -2394,11 +2397,13 @@ mlir::LogicalResult fir::ReboxOp::verify() { // the types is a character with dynamic length, the other type can be any // character type. const bool typeCanMismatch = - inputEleTy.isa() || outEleTy.isa() || - (inputEleTy.isa() && outEleTy.isa()) || - (getSlice() && inputEleTy.isa()) || + mlir::isa(inputEleTy) || + mlir::isa(outEleTy) || + (mlir::isa(inputEleTy) && + mlir::isa(outEleTy)) || + (getSlice() && mlir::isa(inputEleTy)) || (getSlice() && fir::isa_complex(inputEleTy) && - outEleTy.isa()) || + mlir::isa(outEleTy)) || areCompatibleCharacterTypes(inputEleTy, outEleTy); if (!typeCanMismatch) return emitOpError( @@ -2435,7 +2440,7 @@ mlir::LogicalResult fir::SaveResultOp::verify() { if (fir::isa_unknown_size_box(resultType)) return emitOpError("cannot save !fir.box of unknown rank or type"); - if (resultType.isa()) { + if (mlir::isa(resultType)) { if (getShape() || !getTypeparams().empty()) return emitOpError( "must not have shape or length operands if the value is a fir.box"); @@ -2446,14 +2451,14 @@ mlir::LogicalResult fir::SaveResultOp::verify() { unsigned shapeTyRank = 0; if (auto shapeVal = getShape()) { auto shapeTy = shapeVal.getType(); - if (auto s = shapeTy.dyn_cast()) + if (auto s = mlir::dyn_cast(shapeTy)) shapeTyRank = s.getRank(); else - shapeTyRank = shapeTy.cast().getRank(); + shapeTyRank = mlir::cast(shapeTy).getRank(); } auto eleTy = resultType; - if (auto seqTy = resultType.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(resultType)) { if (seqTy.getDimension() != shapeTyRank) emitOpError("shape operand must be provided and have the value rank " "when the value is a fir.array"); @@ -2464,11 +2469,11 @@ mlir::LogicalResult fir::SaveResultOp::verify() { "shape operand should only be provided if the value is a fir.array"); } - if (auto recTy = eleTy.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(eleTy)) { if (recTy.getNumLenParams() != getTypeparams().size()) emitOpError("length parameters number must match with the value type " "length parameters"); - } else if (auto charTy = eleTy.dyn_cast()) { + } else if (auto charTy = mlir::dyn_cast(eleTy)) { if (getTypeparams().size() > 1) emitOpError("no more than one length parameter must be provided for " "character value"); @@ -2508,7 +2513,7 @@ static mlir::LogicalResult verifyIntegralSwitchTerminator(OpT op) { if (op.targetOffsetSize() != count) return op.emitOpError("incorrect number of successor operand groups"); for (decltype(count) i = 0; i != count; ++i) { - if (!cases[i].template isa()) + if (!mlir::isa(cases[i])) return op.emitOpError("invalid case alternative"); } return mlir::success(); @@ -2620,7 +2625,7 @@ getMutableSuccessorOperands(unsigned pos, mlir::MutableOperandRange operands, *owner->getAttrDictionary().getNamed(offsetAttr); return getSubOperands( pos, operands, - targetOffsetAttr.getValue().cast(), + mlir::cast(targetOffsetAttr.getValue()), mlir::MutableOperandRange::OperandSegment(pos, targetOffsetAttr)); } @@ -2742,9 +2747,9 @@ mlir::ParseResult fir::SelectCaseOp::parse(mlir::OpAsmParser &parser, parser.parseComma()) return mlir::failure(); attrs.push_back(attr); - if (attr.dyn_cast_or_null()) { + if (mlir::dyn_cast_or_null(attr)) { argOffs.push_back(0); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { mlir::OpAsmParser::UnresolvedOperand oper1; mlir::OpAsmParser::UnresolvedOperand oper2; if (parser.parseOperand(oper1) || parser.parseComma() || @@ -2806,11 +2811,11 @@ void fir::SelectCaseOp::print(mlir::OpAsmPrinter &p) { if (i) p << ", "; p << cases[i] << ", "; - if (!cases[i].isa()) { + if (!mlir::isa(cases[i])) { auto caseArgs = *getCompareOperands(i); p.printOperand(*caseArgs.begin()); p << ", "; - if (cases[i].isa()) { + if (mlir::isa(cases[i])) { p.printOperand(*(++caseArgs.begin())); p << ", "; } @@ -2848,10 +2853,10 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, llvm::SmallVector operOffs; int32_t operSize = 0; for (auto attr : compareAttrs) { - if (attr.isa()) { + if (mlir::isa(attr)) { operOffs.push_back(2); operSize += 2; - } else if (attr.isa()) { + } else if (mlir::isa(attr)) { operOffs.push_back(0); } else { operOffs.push_back(1); @@ -2900,10 +2905,10 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, llvm::SmallVector cmpOpers; auto iter = cmpOpList.begin(); for (auto &attr : compareAttrs) { - if (attr.isa()) { + if (mlir::isa(attr)) { cmpOpers.push_back(mlir::ValueRange({iter, iter + 2})); iter += 2; - } else if (attr.isa()) { + } else if (mlir::isa(attr)) { cmpOpers.push_back(mlir::ValueRange{}); } else { cmpOpers.push_back(mlir::ValueRange({iter, iter + 1})); @@ -2915,10 +2920,8 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, } mlir::LogicalResult fir::SelectCaseOp::verify() { - if (!getSelector() - .getType() - .isa()) + if (!mlir::isa(getSelector().getType())) return emitOpError("must be an integer, character, or logical"); auto cases = getOperation()->getAttrOfType(getCasesAttr()).getValue(); @@ -2933,9 +2936,11 @@ mlir::LogicalResult fir::SelectCaseOp::verify() { return emitOpError("incorrect number of successor operand groups"); for (decltype(count) i = 0; i != count; ++i) { auto &attr = cases[i]; - if (!(attr.isa() || - attr.isa() || attr.isa() || - attr.isa() || attr.isa())) + if (!(mlir::isa(attr) || + mlir::isa(attr) || + mlir::isa(attr) || + mlir::isa(attr) || + mlir::isa(attr))) return emitOpError("incorrect select case attribute type"); } return mlir::success(); @@ -3111,14 +3116,14 @@ void fir::SelectTypeOp::print(mlir::OpAsmPrinter &p) { } mlir::LogicalResult fir::SelectTypeOp::verify() { - if (!(getSelector().getType().isa())) + if (!mlir::isa(getSelector().getType())) return emitOpError("must be a fir.class or fir.box type"); - if (auto boxType = getSelector().getType().dyn_cast()) - if (!boxType.getEleTy().isa()) + if (auto boxType = mlir::dyn_cast(getSelector().getType())) + if (!mlir::isa(boxType.getEleTy())) return emitOpError("selector must be polymorphic"); auto typeGuardAttr = getCases(); for (unsigned idx = 0; idx < typeGuardAttr.size(); ++idx) - if (typeGuardAttr[idx].isa() && + if (mlir::isa(typeGuardAttr[idx]) && idx != typeGuardAttr.size() - 1) return emitOpError("default must be the last attribute"); auto count = getNumDest(); @@ -3129,9 +3134,8 @@ mlir::LogicalResult fir::SelectTypeOp::verify() { if (targetOffsetSize() != count) return emitOpError("incorrect number of successor operand groups"); for (unsigned i = 0; i != count; ++i) { - if (!(typeGuardAttr[i].isa() || - typeGuardAttr[i].isa() || - typeGuardAttr[i].isa())) + if (!mlir::isa( + typeGuardAttr[i])) return emitOpError("invalid type-case alternative"); } return mlir::success(); @@ -3175,7 +3179,7 @@ void fir::SelectTypeOp::build(mlir::OpBuilder &builder, mlir::LogicalResult fir::ShapeOp::verify() { auto size = getExtents().size(); - auto shapeTy = getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(getType()); assert(shapeTy && "must be a shape type"); if (shapeTy.getRank() != size) return emitOpError("shape type rank mismatch"); @@ -3198,7 +3202,7 @@ mlir::LogicalResult fir::ShapeShiftOp::verify() { return emitOpError("incorrect number of args"); if (size % 2 != 0) return emitOpError("requires a multiple of 2 args"); - auto shapeTy = getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(getType()); assert(shapeTy && "must be a shape shift type"); if (shapeTy.getRank() * 2 != size) return emitOpError("shape type rank mismatch"); @@ -3211,7 +3215,7 @@ mlir::LogicalResult fir::ShapeShiftOp::verify() { mlir::LogicalResult fir::ShiftOp::verify() { auto size = getOrigins().size(); - auto shiftTy = getType().dyn_cast(); + auto shiftTy = mlir::dyn_cast(getType()); assert(shiftTy && "must be a shift type"); if (shiftTy.getRank() != size) return emitOpError("shift type rank mismatch"); @@ -3251,7 +3255,7 @@ mlir::LogicalResult fir::SliceOp::verify() { return emitOpError("incorrect number of args for triple"); if (size % 3 != 0) return emitOpError("requires a multiple of 3 args"); - auto sliceTy = getType().dyn_cast(); + auto sliceTy = mlir::dyn_cast(getType()); assert(sliceTy && "must be a slice type"); if (sliceTy.getRank() * 3 != size) return emitOpError("slice type rank mismatch"); @@ -3309,8 +3313,8 @@ void fir::StoreOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, //===----------------------------------------------------------------------===// inline fir::CharacterType::KindTy stringLitOpGetKind(fir::StringLitOp op) { - auto eleTy = op.getType().cast().getEleTy(); - return eleTy.cast().getFKind(); + auto eleTy = mlir::cast(op.getType()).getEleTy(); + return mlir::cast(eleTy).getFKind(); } bool fir::StringLitOp::isWideValue() { return stringLitOpGetKind(*this) != 1; } @@ -3390,13 +3394,13 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, llvm::SMLoc trailingTypeLoc; if (parser.parseAttribute(val, "fake", attrs)) return mlir::failure(); - if (auto v = val.dyn_cast()) + if (auto v = mlir::dyn_cast(val)) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::value(), v)); - else if (auto v = val.dyn_cast()) + else if (auto v = mlir::dyn_cast(val)) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::xlist(), v)); - else if (auto v = val.dyn_cast()) + else if (auto v = mlir::dyn_cast(val)) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::xlist(), v)); else @@ -3409,7 +3413,7 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, parser.parseRParen() || parser.getCurrentLocation(&trailingTypeLoc) || parser.parseColonType(type)) return mlir::failure(); - auto charTy = type.dyn_cast(); + auto charTy = mlir::dyn_cast(type); if (!charTy) return parser.emitError(trailingTypeLoc, "must have character type"); type = fir::CharacterType::get(builder.getContext(), charTy.getFKind(), @@ -3421,19 +3425,19 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, void fir::StringLitOp::print(mlir::OpAsmPrinter &p) { p << ' ' << getValue() << '('; - p << getSize().cast().getValue() << ") : "; + p << mlir::cast(getSize()).getValue() << ") : "; p.printType(getType()); } mlir::LogicalResult fir::StringLitOp::verify() { - if (getSize().cast().getValue().isNegative()) + if (mlir::cast(getSize()).getValue().isNegative()) return emitOpError("size must be non-negative"); if (auto xl = getOperation()->getAttr(fir::StringLitOp::xlist())) { - if (auto xList = xl.dyn_cast()) { + if (auto xList = mlir::dyn_cast(xl)) { for (auto a : xList) - if (!a.isa()) + if (!mlir::isa(a)) return emitOpError("values in initializer must be integers"); - } else if (xl.isa()) { + } else if (mlir::isa(xl)) { // do nothing } else { return emitOpError("has unexpected attribute"); @@ -3448,7 +3452,7 @@ mlir::LogicalResult fir::StringLitOp::verify() { mlir::LogicalResult fir::UnboxProcOp::verify() { if (auto eleTy = fir::dyn_cast_ptrEleTy(getRefTuple().getType())) - if (eleTy.isa()) + if (mlir::isa(eleTy)) return mlir::success(); return emitOpError("second output argument has bad type"); } @@ -3527,7 +3531,7 @@ void fir::IfOp::getEntrySuccessorRegions( void fir::IfOp::getRegionInvocationBounds( llvm::ArrayRef operands, llvm::SmallVectorImpl &invocationBounds) { - if (auto cond = operands[0].dyn_cast_or_null()) { + if (auto cond = mlir::dyn_cast_or_null(operands[0])) { // If the condition is known, then one region is known to be executed once // and the other zero times. invocationBounds.emplace_back(0, cond.getValue() ? 1 : 0); @@ -3646,8 +3650,8 @@ void fir::BoxOffsetOp::build(mlir::OpBuilder &builder, //===----------------------------------------------------------------------===// mlir::ParseResult fir::isValidCaseAttr(mlir::Attribute attr) { - if (attr.isa()) + if (mlir::isa(attr)) return mlir::success(); return mlir::failure(); } @@ -3657,9 +3661,9 @@ unsigned fir::getCaseArgumentOffset(llvm::ArrayRef cases, unsigned o = 0; for (unsigned i = 0; i < dest; ++i) { auto &attr = cases[i]; - if (!attr.dyn_cast_or_null()) { + if (!mlir::dyn_cast_or_null(attr)) { ++o; - if (attr.dyn_cast_or_null()) + if (mlir::dyn_cast_or_null(attr)) ++o; } } @@ -3722,7 +3726,7 @@ fir::GlobalOp fir::createGlobalOp(mlir::Location loc, mlir::ModuleOp module, bool fir::hasHostAssociationArgument(mlir::func::FuncOp func) { if (auto allArgAttrs = func.getAllArgAttrs()) for (auto attr : allArgAttrs) - if (auto dict = attr.template dyn_cast_or_null()) + if (auto dict = mlir::dyn_cast_or_null(attr)) if (dict.get(fir::getHostAssocAttrName())) return true; return false; @@ -3772,7 +3776,7 @@ valueCheckFirAttributes(mlir::Value value, }; // If this is a fir.box that was loaded, the fir attributes will be on the // related fir.ref creation. - if (value.getType().isa()) + if (mlir::isa(value.getType())) if (auto definingOp = value.getDefiningOp()) if (auto loadOp = mlir::dyn_cast(definingOp)) value = loadOp.getMemref(); @@ -3837,10 +3841,10 @@ bool fir::anyFuncArgsHaveAttr(mlir::func::FuncOp func, llvm::StringRef attr) { std::optional fir::getIntIfConstant(mlir::Value value) { if (auto *definingOp = value.getDefiningOp()) { if (auto cst = mlir::dyn_cast(definingOp)) - if (auto intAttr = cst.getValue().dyn_cast()) + if (auto intAttr = mlir::dyn_cast(cst.getValue())) return intAttr.getInt(); if (auto llConstOp = mlir::dyn_cast(definingOp)) - if (auto attr = llConstOp.getValue().dyn_cast()) + if (auto attr = mlir::dyn_cast(llConstOp.getValue())) return attr.getValue().getSExtValue(); } return {}; @@ -4002,15 +4006,15 @@ mlir::LogicalResult fir::CUDAKernelOp::verify() { mlir::LogicalResult fir::CUDAAllocateOp::verify() { if (getPinned() && getStream()) return emitOpError("pinned and stream cannot appears at the same time"); - if (!fir::unwrapRefType(getBox().getType()).isa()) + if (!mlir::isa(fir::unwrapRefType(getBox().getType()))) return emitOpError( "expect box to be a reference to a class or box type value"); if (getSource() && - !fir::unwrapRefType(getSource().getType()).isa()) + !mlir::isa(fir::unwrapRefType(getSource().getType()))) return emitOpError( "expect source to be a reference to/or a class or box type value"); if (getErrmsg() && - !fir::unwrapRefType(getErrmsg().getType()).isa()) + !mlir::isa(fir::unwrapRefType(getErrmsg().getType()))) return emitOpError( "expect errmsg to be a reference to/or a box type value"); if (getErrmsg() && !getHasStat()) @@ -4019,11 +4023,11 @@ mlir::LogicalResult fir::CUDAAllocateOp::verify() { } mlir::LogicalResult fir::CUDADeallocateOp::verify() { - if (!fir::unwrapRefType(getBox().getType()).isa()) + if (!mlir::isa(fir::unwrapRefType(getBox().getType()))) return emitOpError( "expect box to be a reference to class or box type value"); if (getErrmsg() && - !fir::unwrapRefType(getErrmsg().getType()).isa()) + !mlir::isa(fir::unwrapRefType(getErrmsg().getType()))) return emitOpError( "expect errmsg to be a reference to/or a box type value"); if (getErrmsg() && !getHasStat()) diff --git a/flang/lib/Optimizer/Dialect/FIRType.cpp b/flang/lib/Optimizer/Dialect/FIRType.cpp index 5c4cad6d2083..38a6a09d1808 100644 --- a/flang/lib/Optimizer/Dialect/FIRType.cpp +++ b/flang/lib/Optimizer/Dialect/FIRType.cpp @@ -61,14 +61,13 @@ TYPE parseTypeSingleton(mlir::AsmParser &parser) { /// Is `ty` a standard or FIR integer type? static bool isaIntegerType(mlir::Type ty) { // TODO: why aren't we using isa_integer? investigatation required. - return ty.isa() || ty.isa(); + return mlir::isa(ty); } bool verifyRecordMemberType(mlir::Type ty) { - return !(ty.isa() || ty.isa() || - ty.isa() || ty.isa() || - ty.isa() || ty.isa() || ty.isa() || - ty.isa() || ty.isa()); + return !mlir::isa( + ty); } bool verifySameLists(llvm::ArrayRef a1, @@ -194,7 +193,7 @@ bool isa_std_type(mlir::Type t) { } bool isa_fir_or_std_type(mlir::Type t) { - if (auto funcType = t.dyn_cast()) + if (auto funcType = mlir::dyn_cast(t)) return llvm::all_of(funcType.getInputs(), isa_fir_or_std_type) && llvm::all_of(funcType.getResults(), isa_fir_or_std_type); return isa_fir_type(t) || isa_std_type(t); @@ -203,7 +202,7 @@ bool isa_fir_or_std_type(mlir::Type t) { mlir::Type getDerivedType(mlir::Type ty) { return llvm::TypeSwitch(ty) .Case([](auto p) { - if (auto seq = p.getEleTy().template dyn_cast()) + if (auto seq = mlir::dyn_cast(p.getEleTy())) return seq.getEleTy(); return p.getEleTy(); }) @@ -228,12 +227,12 @@ mlir::Type dyn_cast_ptrOrBoxEleTy(mlir::Type t) { static bool hasDynamicSize(fir::RecordType recTy) { for (auto field : recTy.getTypeList()) { - if (auto arr = field.second.dyn_cast()) { + if (auto arr = mlir::dyn_cast(field.second)) { if (sequenceWithNonConstantShape(arr)) return true; } else if (characterWithDynamicLen(field.second)) { return true; - } else if (auto rec = field.second.dyn_cast()) { + } else if (auto rec = mlir::dyn_cast(field.second)) { if (hasDynamicSize(rec)) return true; } @@ -242,14 +241,14 @@ static bool hasDynamicSize(fir::RecordType recTy) { } bool hasDynamicSize(mlir::Type t) { - if (auto arr = t.dyn_cast()) { + if (auto arr = mlir::dyn_cast(t)) { if (sequenceWithNonConstantShape(arr)) return true; t = arr.getEleTy(); } if (characterWithDynamicLen(t)) return true; - if (auto rec = t.dyn_cast()) + if (auto rec = mlir::dyn_cast(t)) return hasDynamicSize(rec); return false; } @@ -269,33 +268,33 @@ mlir::Type extractSequenceType(mlir::Type ty) { bool isPointerType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) - return boxTy.getEleTy().isa(); + if (auto boxTy = mlir::dyn_cast(ty)) + return mlir::isa(boxTy.getEleTy()); return false; } bool isAllocatableType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) - return boxTy.getEleTy().isa(); + if (auto boxTy = mlir::dyn_cast(ty)) + return mlir::isa(boxTy.getEleTy()); return false; } bool isBoxNone(mlir::Type ty) { - if (auto box = ty.dyn_cast()) - return box.getEleTy().isa(); + if (auto box = mlir::dyn_cast(ty)) + return mlir::isa(box.getEleTy()); return false; } bool isBoxedRecordType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) { - if (boxTy.getEleTy().isa()) + if (auto boxTy = mlir::dyn_cast(ty)) { + if (mlir::isa(boxTy.getEleTy())) return true; mlir::Type innerType = boxTy.unwrapInnerType(); - return innerType && innerType.isa(); + return innerType && mlir::isa(innerType); } return false; } @@ -303,13 +302,13 @@ bool isBoxedRecordType(mlir::Type ty) { bool isScalarBoxedRecordType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) { - if (boxTy.getEleTy().isa()) + if (auto boxTy = mlir::dyn_cast(ty)) { + if (mlir::isa(boxTy.getEleTy())) return true; - if (auto heapTy = boxTy.getEleTy().dyn_cast()) - return heapTy.getEleTy().isa(); - if (auto ptrTy = boxTy.getEleTy().dyn_cast()) - return ptrTy.getEleTy().isa(); + if (auto heapTy = mlir::dyn_cast(boxTy.getEleTy())) + return mlir::isa(heapTy.getEleTy()); + if (auto ptrTy = mlir::dyn_cast(boxTy.getEleTy())) + return mlir::isa(ptrTy.getEleTy()); } return false; } @@ -363,10 +362,10 @@ bool isPolymorphicType(mlir::Type ty) { bool isUnlimitedPolymorphicType(mlir::Type ty) { // CLASS(*) if (auto clTy = mlir::dyn_cast(fir::unwrapRefType(ty))) { - if (clTy.getEleTy().isa()) + if (mlir::isa(clTy.getEleTy())) return true; mlir::Type innerType = clTy.unwrapInnerType(); - return innerType && innerType.isa(); + return innerType && mlir::isa(innerType); } // TYPE(*) return isAssumedType(ty); @@ -376,7 +375,7 @@ mlir::Type unwrapInnerType(mlir::Type ty) { return llvm::TypeSwitch(ty) .Case([](auto t) { mlir::Type eleTy = t.getEleTy(); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); return eleTy; }) @@ -385,13 +384,14 @@ mlir::Type unwrapInnerType(mlir::Type ty) { } bool isRecordWithAllocatableMember(mlir::Type ty) { - if (auto recTy = ty.dyn_cast()) + if (auto recTy = mlir::dyn_cast(ty)) for (auto [field, memTy] : recTy.getTypeList()) { if (fir::isAllocatableType(memTy)) return true; // A record type cannot recursively include itself as a direct member. // There must be an intervening `ptr` type, so recursion is safe here. - if (memTy.isa() && isRecordWithAllocatableMember(memTy)) + if (mlir::isa(memTy) && + isRecordWithAllocatableMember(memTy)) return true; } return false; @@ -399,11 +399,12 @@ bool isRecordWithAllocatableMember(mlir::Type ty) { bool isRecordWithDescriptorMember(mlir::Type ty) { ty = unwrapSequenceType(ty); - if (auto recTy = ty.dyn_cast()) + if (auto recTy = mlir::dyn_cast(ty)) for (auto [field, memTy] : recTy.getTypeList()) { if (mlir::isa(memTy)) return true; - if (memTy.isa() && isRecordWithDescriptorMember(memTy)) + if (mlir::isa(memTy) && + isRecordWithDescriptorMember(memTy)) return true; } return false; @@ -412,7 +413,7 @@ bool isRecordWithDescriptorMember(mlir::Type ty) { mlir::Type unwrapAllRefAndSeqType(mlir::Type ty) { while (true) { mlir::Type nt = unwrapSequenceType(unwrapRefType(ty)); - if (auto vecTy = nt.dyn_cast()) + if (auto vecTy = mlir::dyn_cast(nt)) nt = vecTy.getEleTy(); if (nt == ty) return ty; @@ -421,11 +422,11 @@ mlir::Type unwrapAllRefAndSeqType(mlir::Type ty) { } mlir::Type unwrapSeqOrBoxedSeqType(mlir::Type ty) { - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return seqTy.getEleTy(); - if (auto boxTy = ty.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(ty)) { auto eleTy = unwrapRefType(boxTy.getEleTy()); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); } return ty; @@ -433,7 +434,7 @@ mlir::Type unwrapSeqOrBoxedSeqType(mlir::Type ty) { unsigned getBoxRank(mlir::Type boxTy) { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(boxTy); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getDimension(); return 0; } @@ -441,7 +442,7 @@ unsigned getBoxRank(mlir::Type boxTy) { /// Return the ISO_C_BINDING intrinsic module value of type \p ty. int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { unsigned width = 0; - if (mlir::IntegerType intTy = ty.dyn_cast()) { + if (mlir::IntegerType intTy = mlir::dyn_cast(ty)) { switch (intTy.getWidth()) { case 8: return CFI_type_int8_t; @@ -456,7 +457,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported integer type"); } - if (fir::LogicalType logicalTy = ty.dyn_cast()) { + if (fir::LogicalType logicalTy = mlir::dyn_cast(ty)) { switch (kindMap.getLogicalBitsize(logicalTy.getFKind())) { case 8: return CFI_type_Bool; @@ -469,7 +470,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported logical type"); } - if (mlir::FloatType floatTy = ty.dyn_cast()) { + if (mlir::FloatType floatTy = mlir::dyn_cast(ty)) { switch (floatTy.getWidth()) { case 16: return floatTy.isBF16() ? CFI_type_bfloat : CFI_type_half_float; @@ -485,13 +486,14 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { llvm_unreachable("unsupported real type"); } if (fir::isa_complex(ty)) { - if (mlir::ComplexType complexTy = ty.dyn_cast()) { + if (mlir::ComplexType complexTy = mlir::dyn_cast(ty)) { mlir::FloatType floatTy = - complexTy.getElementType().cast(); + mlir::cast(complexTy.getElementType()); if (floatTy.isBF16()) return CFI_type_bfloat_Complex; width = floatTy.getWidth(); - } else if (fir::ComplexType complexTy = ty.dyn_cast()) { + } else if (fir::ComplexType complexTy = + mlir::dyn_cast(ty)) { auto FKind = complexTy.getFKind(); if (FKind == 3) return CFI_type_bfloat_Complex; @@ -511,7 +513,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported complex size"); } - if (fir::CharacterType charTy = ty.dyn_cast()) { + if (fir::CharacterType charTy = mlir::dyn_cast(ty)) { switch (kindMap.getCharacterBitsize(charTy.getFKind())) { case 8: return CFI_type_char; @@ -524,7 +526,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } if (fir::isa_ref_type(ty)) return CFI_type_cptr; - if (ty.isa()) + if (mlir::isa(ty)) return CFI_type_struct; llvm_unreachable("unsupported type"); } @@ -542,12 +544,12 @@ std::string getTypeAsString(mlir::Type ty, const fir::KindMapping &kindMap, name << "idx"; } else if (ty.isIntOrIndex()) { name << 'i' << ty.getIntOrFloatBitWidth(); - } else if (ty.isa()) { + } else if (mlir::isa(ty)) { name << 'f' << ty.getIntOrFloatBitWidth(); } else if (fir::isa_complex(ty)) { name << 'z'; if (auto cplxTy = mlir::dyn_cast_or_null(ty)) { - auto floatTy = cplxTy.getElementType().cast(); + auto floatTy = mlir::cast(cplxTy.getElementType()); name << floatTy.getWidth(); } else if (auto cplxTy = mlir::dyn_cast_or_null(ty)) { name << kindMap.getRealBitsize(cplxTy.getFKind()); @@ -644,7 +646,7 @@ static llvm::SmallPtrSet } // namespace void fir::verifyIntegralType(mlir::Type type) { - if (isaIntegerType(type) || type.isa()) + if (isaIntegerType(type) || mlir::isa(type)) return; llvm::report_fatal_error("expected integral type"); } @@ -656,9 +658,9 @@ void fir::printFirType(FIROpsDialect *, mlir::Type ty, } bool fir::isa_unknown_size_box(mlir::Type t) { - if (auto boxTy = t.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(t)) { auto valueType = fir::unwrapPassByRefType(boxTy); - if (auto seqTy = valueType.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(valueType)) if (seqTy.hasUnknownShape()) return true; } @@ -684,10 +686,10 @@ void fir::BoxProcType::print(mlir::AsmPrinter &printer) const { mlir::LogicalResult BoxProcType::verify(llvm::function_ref emitError, mlir::Type eleTy) { - if (eleTy.isa()) + if (mlir::isa(eleTy)) return mlir::success(); - if (auto refTy = eleTy.dyn_cast()) - if (refTy.isa()) + if (auto refTy = mlir::dyn_cast(eleTy)) + if (mlir::isa(refTy)) return mlir::success(); return emitError() << "invalid type for boxproc" << eleTy << '\n'; } @@ -705,7 +707,7 @@ static bool cannotBePointerOrHeapElementType(mlir::Type eleTy) { mlir::LogicalResult fir::BoxType::verify(llvm::function_ref emitError, mlir::Type eleTy) { - if (eleTy.isa()) + if (mlir::isa(eleTy)) return emitError() << "invalid element type\n"; // TODO return mlir::success(); @@ -1236,10 +1238,10 @@ bool fir::VectorType::isValidElementType(mlir::Type t) { } bool fir::isCharacterProcedureTuple(mlir::Type ty, bool acceptRawFunc) { - mlir::TupleType tuple = ty.dyn_cast(); + mlir::TupleType tuple = mlir::dyn_cast(ty); return tuple && tuple.size() == 2 && - (tuple.getType(0).isa() || - (acceptRawFunc && tuple.getType(0).isa())) && + (mlir::isa(tuple.getType(0)) || + (acceptRawFunc && mlir::isa(tuple.getType(0)))) && fir::isa_integer(tuple.getType(1)); } @@ -1247,7 +1249,8 @@ bool fir::hasAbstractResult(mlir::FunctionType ty) { if (ty.getNumResults() == 0) return false; auto resultType = ty.getResult(0); - return resultType.isa(); + return mlir::isa( + resultType); } /// Convert llvm::Type::TypeID to mlir::Type. \p kind is provided for error diff --git a/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp b/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp index 94f1689dfb05..70b1a2f3d844 100644 --- a/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp +++ b/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp @@ -18,7 +18,7 @@ mlir::LogicalResult fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { const unsigned numExplicitTypeParams = getExplicitTypeParams().size(); mlir::Type memType = memref.getType(); - const bool sourceIsBoxValue = memType.isa(); + const bool sourceIsBoxValue = mlir::isa(memType); const bool sourceIsBoxAddress = fir::isBoxAddress(memType); const bool sourceIsBox = sourceIsBoxValue || sourceIsBoxAddress; if (isCharacter()) { @@ -29,7 +29,8 @@ fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { return emitOpError("must be provided exactly one type parameter when its " "base is a character that is not a box"); - } else if (auto recordType = getElementType().dyn_cast()) { + } else if (auto recordType = + mlir::dyn_cast(getElementType())) { if (numExplicitTypeParams < recordType.getNumLenParams() && !sourceIsBox) return emitOpError("must be provided all the derived type length " "parameters when the base is not a box"); @@ -45,16 +46,16 @@ fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { if (sourceIsBoxAddress) return emitOpError("for box address must not have a shape operand"); unsigned shapeRank = 0; - if (auto shapeType = shape.getType().dyn_cast()) { + if (auto shapeType = mlir::dyn_cast(shape.getType())) { shapeRank = shapeType.getRank(); } else if (auto shapeShiftType = - shape.getType().dyn_cast()) { + mlir::dyn_cast(shape.getType())) { shapeRank = shapeShiftType.getRank(); } else { if (!sourceIsBoxValue) emitOpError("of array entity with a raw address base must have a " "shape operand that is a shape or shapeshift"); - shapeRank = shape.getType().cast().getRank(); + shapeRank = mlir::cast(shape.getType()).getRank(); } std::optional rank = getRank(); diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp index 08b2b0538c73..0b61c0edce62 100644 --- a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp @@ -84,7 +84,8 @@ bool hlfir::isFortranVariableType(mlir::Type type) { return llvm::TypeSwitch(type) .Case([](auto p) { mlir::Type eleType = p.getEleTy(); - return eleType.isa() || !fir::hasDynamicSize(eleType); + return mlir::isa(eleType) || + !fir::hasDynamicSize(eleType); }) .Case([](auto) { return true; }) .Case([](auto) { return true; }) @@ -93,15 +94,15 @@ bool hlfir::isFortranVariableType(mlir::Type type) { bool hlfir::isFortranScalarCharacterType(mlir::Type type) { return isFortranScalarCharacterExprType(type) || - type.isa() || - fir::unwrapPassByRefType(fir::unwrapRefType(type)) - .isa(); + mlir::isa(type) || + mlir::isa( + fir::unwrapPassByRefType(fir::unwrapRefType(type))); } bool hlfir::isFortranScalarCharacterExprType(mlir::Type type) { - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.isScalar() && - exprType.getElementType().isa(); + mlir::isa(exprType.getElementType()); return false; } @@ -121,8 +122,8 @@ bool hlfir::isFortranScalarNumericalType(mlir::Type type) { bool hlfir::isFortranNumericalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = - getFortranElementOrSequenceType(type).dyn_cast()) + if (auto arrayTy = mlir::dyn_cast( + getFortranElementOrSequenceType(type))) return isFortranScalarNumericalType(arrayTy.getEleTy()); return false; } @@ -130,8 +131,8 @@ bool hlfir::isFortranNumericalArrayObject(mlir::Type type) { bool hlfir::isFortranNumericalOrLogicalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = - getFortranElementOrSequenceType(type).dyn_cast()) { + if (auto arrayTy = mlir::dyn_cast( + getFortranElementOrSequenceType(type))) { mlir::Type eleTy = arrayTy.getEleTy(); return isFortranScalarNumericalType(eleTy) || mlir::isa(eleTy); @@ -142,7 +143,8 @@ bool hlfir::isFortranNumericalOrLogicalArrayObject(mlir::Type type) { bool hlfir::isFortranArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - return !!getFortranElementOrSequenceType(type).dyn_cast(); + return !!mlir::dyn_cast( + getFortranElementOrSequenceType(type)); } bool hlfir::isPassByRefOrIntegerType(mlir::Type type) { @@ -151,7 +153,7 @@ bool hlfir::isPassByRefOrIntegerType(mlir::Type type) { } bool hlfir::isI1Type(mlir::Type type) { - if (mlir::IntegerType integer = type.dyn_cast()) + if (mlir::IntegerType integer = mlir::dyn_cast(type)) if (integer.getWidth() == 1) return true; return false; @@ -160,8 +162,8 @@ bool hlfir::isI1Type(mlir::Type type) { bool hlfir::isFortranLogicalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = - getFortranElementOrSequenceType(type).dyn_cast()) { + if (auto arrayTy = mlir::dyn_cast( + getFortranElementOrSequenceType(type))) { mlir::Type eleTy = arrayTy.getEleTy(); return mlir::isa(eleTy); } diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp index 8bad4e445082..0d62ca4954e6 100644 --- a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp @@ -74,8 +74,8 @@ getIntrinsicEffects(mlir::Operation *self, /// Is this a fir.[ref/ptr/heap]>> type? static bool isAllocatableBoxRef(mlir::Type type) { fir::BaseBoxType boxType = - fir::dyn_cast_ptrEleTy(type).dyn_cast_or_null(); - return boxType && boxType.getEleTy().isa(); + mlir::dyn_cast_or_null(fir::dyn_cast_ptrEleTy(type)); + return boxType && mlir::isa(boxType.getEleTy()); } mlir::LogicalResult hlfir::AssignOp::verify() { @@ -84,7 +84,7 @@ mlir::LogicalResult hlfir::AssignOp::verify() { return emitOpError("lhs must be an allocatable when `realloc` is set"); if (mustKeepLhsLengthInAllocatableAssignment() && !(isAllocatableAssignment() && - hlfir::getFortranElementType(lhsType).isa())) + mlir::isa(hlfir::getFortranElementType(lhsType)))) return emitOpError("`realloc` must be set and lhs must be a character " "allocatable when `keep_lhs_length_if_realloc` is set"); return mlir::success(); @@ -99,13 +99,13 @@ mlir::LogicalResult hlfir::AssignOp::verify() { mlir::Type hlfir::DeclareOp::getHLFIRVariableType(mlir::Type inputType, bool hasExplicitLowerBounds) { mlir::Type type = fir::unwrapRefType(inputType); - if (type.isa()) + if (mlir::isa(type)) return inputType; - if (auto charType = type.dyn_cast()) + if (auto charType = mlir::dyn_cast(type)) if (charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); - auto seqType = type.dyn_cast(); + auto seqType = mlir::dyn_cast(type); bool hasDynamicExtents = seqType && fir::sequenceWithNonConstantShape(seqType); mlir::Type eleType = seqType ? seqType.getEleTy() : type; @@ -117,7 +117,8 @@ mlir::Type hlfir::DeclareOp::getHLFIRVariableType(mlir::Type inputType, } static bool hasExplicitLowerBounds(mlir::Value shape) { - return shape && shape.getType().isa(); + return shape && + mlir::isa(shape.getType()); } void hlfir::DeclareOp::build(mlir::OpBuilder &builder, @@ -288,7 +289,7 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { bool hasBoxComponent; if (getComponent()) { auto component = getComponent().value(); - auto recType = baseElementType.dyn_cast(); + auto recType = mlir::dyn_cast(baseElementType); if (!recType) return emitOpError( "component must be provided only when the memref is a derived type"); @@ -300,14 +301,14 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { } mlir::Type fieldType = recType.getType(fieldIdx); mlir::Type componentBaseType = getFortranElementOrSequenceType(fieldType); - hasBoxComponent = fieldType.isa(); - if (componentBaseType.isa() && - baseType.isa() && + hasBoxComponent = mlir::isa(fieldType); + if (mlir::isa(componentBaseType) && + mlir::isa(baseType) && (numSubscripts == 0 || subscriptsRank > 0)) return emitOpError("indices must be provided and must not contain " "triplets when both memref and component are arrays"); if (numSubscripts != 0) { - if (!componentBaseType.isa()) + if (!mlir::isa(componentBaseType)) return emitOpError("indices must not be provided if component appears " "and is not an array component"); if (!getComponentShape()) @@ -315,9 +316,9 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { "component_shape must be provided when indexing a component"); mlir::Type compShapeType = getComponentShape().getType(); unsigned componentRank = - componentBaseType.cast().getDimension(); - auto shapeType = compShapeType.dyn_cast(); - auto shapeShiftType = compShapeType.dyn_cast(); + mlir::cast(componentBaseType).getDimension(); + auto shapeType = mlir::dyn_cast(compShapeType); + auto shapeShiftType = mlir::dyn_cast(compShapeType); if (!((shapeType && shapeType.getRank() == componentRank) || (shapeShiftType && shapeShiftType.getRank() == componentRank))) return emitOpError("component_shape must be a fir.shape or " @@ -325,33 +326,33 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { if (numSubscripts > componentRank) return emitOpError("indices number must match array component rank"); } - if (auto baseSeqType = baseType.dyn_cast()) + if (auto baseSeqType = mlir::dyn_cast(baseType)) // This case must come first to cover "array%array_comp(i, j)" that has // subscripts for the component but whose rank come from the base. outputRank = baseSeqType.getDimension(); else if (numSubscripts != 0) outputRank = subscriptsRank; else if (auto componentSeqType = - componentBaseType.dyn_cast()) + mlir::dyn_cast(componentBaseType)) outputRank = componentSeqType.getDimension(); outputElementType = fir::unwrapSequenceType(componentBaseType); } else { outputElementType = baseElementType; unsigned baseTypeRank = - baseType.isa() - ? baseType.cast().getDimension() + mlir::isa(baseType) + ? mlir::cast(baseType).getDimension() : 0; if (numSubscripts != 0) { if (baseTypeRank != numSubscripts) return emitOpError("indices number must match memref rank"); outputRank = subscriptsRank; - } else if (auto baseSeqType = baseType.dyn_cast()) { + } else if (auto baseSeqType = mlir::dyn_cast(baseType)) { outputRank = baseSeqType.getDimension(); } } if (!getSubstring().empty()) { - if (!outputElementType.isa()) + if (!mlir::isa(outputElementType)) return emitOpError("memref or component must have character type if " "substring indices are provided"); if (getSubstring().size() != 2) @@ -361,16 +362,16 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { if (!fir::isa_complex(outputElementType)) return emitOpError("memref or component must have complex type if " "complex_part is provided"); - if (auto firCplx = outputElementType.dyn_cast()) + if (auto firCplx = mlir::dyn_cast(outputElementType)) outputElementType = firCplx.getElementType(); else outputElementType = - outputElementType.cast().getElementType(); + mlir::cast(outputElementType).getElementType(); } mlir::Type resultBaseType = getFortranElementOrSequenceType(getResult().getType()); unsigned resultRank = 0; - if (auto resultSeqType = resultBaseType.dyn_cast()) + if (auto resultSeqType = mlir::dyn_cast(resultBaseType)) resultRank = resultSeqType.getDimension(); if (resultRank != outputRank) return emitOpError("result type rank is not consistent with operands, " @@ -380,10 +381,10 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { // result type must match the one that was inferred here, except the character // length may differ because of substrings. if (resultElementType != outputElementType && - !(resultElementType.isa() && - outputElementType.isa()) && - !(resultElementType.isa() && - outputElementType.isa())) + !(mlir::isa(resultElementType) && + mlir::isa(outputElementType)) && + !(mlir::isa(resultElementType) && + mlir::isa(outputElementType))) return emitOpError( "result element type is not consistent with operands, expected ") << outputElementType; @@ -401,22 +402,22 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { return emitOpError("shape must be provided if and only if the result is " "an array that is not a box address"); if (resultRank != 0) { - auto shapeType = getShape().getType().dyn_cast(); + auto shapeType = mlir::dyn_cast(getShape().getType()); auto shapeShiftType = - getShape().getType().dyn_cast(); + mlir::dyn_cast(getShape().getType()); if (!((shapeType && shapeType.getRank() == resultRank) || (shapeShiftType && shapeShiftType.getRank() == resultRank))) return emitOpError("shape must be a fir.shape or fir.shapeshift with " "the rank of the result"); } auto numLenParam = getTypeparams().size(); - if (outputElementType.isa()) { + if (mlir::isa(outputElementType)) { if (numLenParam != 1) return emitOpError("must be provided one length parameter when the " "result is a character"); } else if (fir::isRecordWithTypeParameters(outputElementType)) { if (numLenParam != - outputElementType.cast().getNumLenParams()) + mlir::cast(outputElementType).getNumLenParams()) return emitOpError("must be provided the same number of length " "parameters as in the result derived type"); } else if (numLenParam != 0) { @@ -434,18 +435,18 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { mlir::LogicalResult hlfir::ParentComponentOp::verify() { mlir::Type baseType = hlfir::getFortranElementOrSequenceType(getMemref().getType()); - auto maybeInputSeqType = baseType.dyn_cast(); + auto maybeInputSeqType = mlir::dyn_cast(baseType); unsigned inputTypeRank = maybeInputSeqType ? maybeInputSeqType.getDimension() : 0; unsigned shapeRank = 0; if (mlir::Value shape = getShape()) - if (auto shapeType = shape.getType().dyn_cast()) + if (auto shapeType = mlir::dyn_cast(shape.getType())) shapeRank = shapeType.getRank(); if (inputTypeRank != shapeRank) return emitOpError( "must be provided a shape if and only if the base is an array"); mlir::Type outputBaseType = hlfir::getFortranElementOrSequenceType(getType()); - auto maybeOutputSeqType = outputBaseType.dyn_cast(); + auto maybeOutputSeqType = mlir::dyn_cast(outputBaseType); unsigned outputTypeRank = maybeOutputSeqType ? maybeOutputSeqType.getDimension() : 0; if (inputTypeRank != outputTypeRank) @@ -459,23 +460,23 @@ mlir::LogicalResult hlfir::ParentComponentOp::verify() { return emitOpError( "result type extents are inconsistent with memref type"); fir::RecordType baseRecType = - hlfir::getFortranElementType(baseType).dyn_cast(); - fir::RecordType outRecType = - hlfir::getFortranElementType(outputBaseType).dyn_cast(); + mlir::dyn_cast(hlfir::getFortranElementType(baseType)); + fir::RecordType outRecType = mlir::dyn_cast( + hlfir::getFortranElementType(outputBaseType)); if (!baseRecType || !outRecType) return emitOpError("result type and input type must be derived types"); // Note: result should not be a fir.class: its dynamic type is being set to // the parent type and allowing fir.class would break the operation codegen: // it would keep the input dynamic type. - if (getType().isa()) + if (mlir::isa(getType())) return emitOpError("result type must not be polymorphic"); // The array results are known to not be dis-contiguous in most cases (the // exception being if the parent type was extended by a type without any // components): require a fir.box to be used for the result to carry the // strides. - if (!getType().isa() && + if (!mlir::isa(getType()) && (outputTypeRank != 0 || fir::isRecordWithTypeParameters(outRecType))) return emitOpError("result type must be a fir.box if the result is an " "array or has length parameters"); @@ -496,9 +497,8 @@ verifyLogicalReductionOp(LogicalReductionOp reductionOp) { mlir::Value mask = reductionOp->getMask(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType maskTy = - hlfir::getFortranElementOrSequenceType(mask.getType()) - .cast(); + fir::SequenceType maskTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(mask.getType())); mlir::Type logicalTy = maskTy.getEleTy(); llvm::ArrayRef maskShape = maskTy.getShape(); @@ -576,9 +576,8 @@ mlir::LogicalResult hlfir::CountOp::verify() { mlir::Value mask = getMask(); mlir::Value dim = getDim(); - fir::SequenceType maskTy = - hlfir::getFortranElementOrSequenceType(mask.getType()) - .cast(); + fir::SequenceType maskTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(mask.getType())); llvm::ArrayRef maskShape = maskTy.getShape(); mlir::Type resultType = results[0]; @@ -613,13 +612,14 @@ void hlfir::CountOp::getEffects( //===----------------------------------------------------------------------===// static unsigned getCharacterKind(mlir::Type t) { - return hlfir::getFortranElementType(t).cast().getFKind(); + return mlir::cast(hlfir::getFortranElementType(t)) + .getFKind(); } static std::optional getCharacterLengthIfStatic(mlir::Type t) { if (auto charType = - hlfir::getFortranElementType(t).dyn_cast()) + mlir::dyn_cast(hlfir::getFortranElementType(t))) if (charType.hasConstantLen()) return charType.getLen(); return std::nullopt; @@ -672,15 +672,13 @@ verifyArrayAndMaskForReductionOp(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value mask = reductionOp->getMask(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); llvm::ArrayRef arrayShape = arrayTy.getShape(); if (mask) { - fir::SequenceType maskSeq = - hlfir::getFortranElementOrSequenceType(mask.getType()) - .dyn_cast(); + fir::SequenceType maskSeq = mlir::dyn_cast( + hlfir::getFortranElementOrSequenceType(mask.getType())); llvm::ArrayRef maskShape; if (maskSeq) @@ -720,9 +718,8 @@ verifyNumericalReductionOp(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); mlir::Type numTy = arrayTy.getEleTy(); llvm::ArrayRef arrayShape = arrayTy.getShape(); @@ -790,13 +787,12 @@ verifyCharacterReductionOp(CharacterReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); mlir::Type numTy = arrayTy.getEleTy(); llvm::ArrayRef arrayShape = arrayTy.getShape(); - auto resultExpr = results[0].cast(); + auto resultExpr = mlir::cast(results[0]); mlir::Type resultType = resultExpr.getEleTy(); assert(mlir::isa(resultType) && "result must be character"); @@ -881,9 +877,8 @@ verifyResultForMinMaxLoc(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); llvm::ArrayRef arrayShape = arrayTy.getShape(); mlir::Type resultType = results[0]; @@ -993,12 +988,10 @@ void hlfir::SumOp::getEffects( mlir::LogicalResult hlfir::DotProductOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = - hlfir::getFortranElementOrSequenceType(lhs.getType()) - .cast(); - fir::SequenceType rhsTy = - hlfir::getFortranElementOrSequenceType(rhs.getType()) - .cast(); + fir::SequenceType lhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(lhs.getType())); + fir::SequenceType rhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(rhs.getType())); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); @@ -1051,19 +1044,17 @@ void hlfir::DotProductOp::getEffects( mlir::LogicalResult hlfir::MatmulOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = - hlfir::getFortranElementOrSequenceType(lhs.getType()) - .cast(); - fir::SequenceType rhsTy = - hlfir::getFortranElementOrSequenceType(rhs.getType()) - .cast(); + fir::SequenceType lhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(lhs.getType())); + fir::SequenceType rhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(rhs.getType())); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); std::size_t rhsRank = rhsShape.size(); mlir::Type lhsEleTy = lhsTy.getEleTy(); mlir::Type rhsEleTy = rhsTy.getEleTy(); - hlfir::ExprType resultTy = getResult().getType().cast(); + hlfir::ExprType resultTy = mlir::cast(getResult().getType()); llvm::ArrayRef resultShape = resultTy.getShape(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1180,13 +1171,12 @@ void hlfir::MatmulOp::getEffects( mlir::LogicalResult hlfir::TransposeOp::verify() { mlir::Value array = getArray(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); llvm::ArrayRef inShape = arrayTy.getShape(); std::size_t rank = inShape.size(); mlir::Type eleTy = arrayTy.getEleTy(); - hlfir::ExprType resultTy = getResult().getType().cast(); + hlfir::ExprType resultTy = mlir::cast(getResult().getType()); llvm::ArrayRef resultShape = resultTy.getShape(); std::size_t resultRank = resultShape.size(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1224,19 +1214,17 @@ void hlfir::TransposeOp::getEffects( mlir::LogicalResult hlfir::MatmulTransposeOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = - hlfir::getFortranElementOrSequenceType(lhs.getType()) - .cast(); - fir::SequenceType rhsTy = - hlfir::getFortranElementOrSequenceType(rhs.getType()) - .cast(); + fir::SequenceType lhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(lhs.getType())); + fir::SequenceType rhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(rhs.getType())); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); std::size_t rhsRank = rhsShape.size(); mlir::Type lhsEleTy = lhsTy.getEleTy(); mlir::Type rhsEleTy = rhsTy.getEleTy(); - hlfir::ExprType resultTy = getResult().getType().cast(); + hlfir::ExprType resultTy = mlir::cast(getResult().getType()); llvm::ArrayRef resultShape = resultTy.getShape(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1381,7 +1369,7 @@ void hlfir::AsExprOp::build(mlir::OpBuilder &builder, hlfir::ExprType::Shape typeShape; bool isPolymorphic = fir::isPolymorphicType(var.getType()); mlir::Type type = getFortranElementOrSequenceType(var.getType()); - if (auto seqType = type.dyn_cast()) { + if (auto seqType = mlir::dyn_cast(type)) { typeShape.append(seqType.getShape().begin(), seqType.getShape().end()); type = seqType.getEleTy(); } @@ -1427,7 +1415,7 @@ static void buildElemental(mlir::OpBuilder &builder, isUnordered ? builder.getUnitAttr() : nullptr); mlir::Region *bodyRegion = odsState.addRegion(); bodyRegion->push_back(new mlir::Block{}); - if (auto shapeType = shape.getType().dyn_cast()) { + if (auto shapeType = mlir::dyn_cast(shape.getType())) { unsigned dim = shapeType.getRank(); mlir::Type indexType = builder.getIndexType(); for (unsigned d = 0; d < dim; ++d) @@ -1468,7 +1456,7 @@ void hlfir::ApplyOp::build(mlir::OpBuilder &builder, mlir::ValueRange indices, mlir::ValueRange typeparams) { mlir::Type resultType = expr.getType(); - if (auto exprType = resultType.dyn_cast()) + if (auto exprType = mlir::dyn_cast(resultType)) resultType = exprType.getElementExprType(); build(builder, odsState, resultType, expr, indices, typeparams); } @@ -1517,20 +1505,20 @@ void hlfir::CopyInOp::build(mlir::OpBuilder &builder, void hlfir::ShapeOfOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, mlir::Value expr) { - hlfir::ExprType exprTy = expr.getType().cast(); + hlfir::ExprType exprTy = mlir::cast(expr.getType()); mlir::Type type = fir::ShapeType::get(builder.getContext(), exprTy.getRank()); build(builder, result, type, expr); } std::size_t hlfir::ShapeOfOp::getRank() { mlir::Type resTy = getResult().getType(); - fir::ShapeType shape = resTy.cast(); + fir::ShapeType shape = mlir::cast(resTy); return shape.getRank(); } mlir::LogicalResult hlfir::ShapeOfOp::verify() { mlir::Value expr = getExpr(); - hlfir::ExprType exprTy = expr.getType().cast(); + hlfir::ExprType exprTy = mlir::cast(expr.getType()); std::size_t exprRank = exprTy.getShape().size(); if (exprRank == 0) @@ -1549,7 +1537,8 @@ hlfir::ShapeOfOp::canonicalize(ShapeOfOp shapeOf, // if extent information is available at compile time, immediately fold the // hlfir.shape_of into a fir.shape mlir::Location loc = shapeOf.getLoc(); - hlfir::ExprType expr = shapeOf.getExpr().getType().cast(); + hlfir::ExprType expr = + mlir::cast(shapeOf.getExpr().getType()); mlir::Value shape = hlfir::genExprShape(rewriter, loc, expr); if (!shape) @@ -1574,7 +1563,7 @@ void hlfir::GetExtentOp::build(mlir::OpBuilder &builder, } mlir::LogicalResult hlfir::GetExtentOp::verify() { - fir::ShapeType shapeTy = getShape().getType().cast(); + fir::ShapeType shapeTy = mlir::cast(getShape().getType()); std::uint64_t rank = shapeTy.getRank(); llvm::APInt dim = getDim(); if (dim.sge(rank)) @@ -1709,10 +1698,11 @@ mlir::LogicalResult hlfir::ElementalAddrOp::verify() { return emitOpError("body region must be terminated by an hlfir.yield"); mlir::Type elementAddrType = yieldOp.getEntity().getType(); if (!hlfir::isFortranVariableType(elementAddrType) || - hlfir::getFortranElementOrSequenceType(elementAddrType) - .isa()) + mlir::isa( + hlfir::getFortranElementOrSequenceType(elementAddrType))) return emitOpError("body must compute the address of a scalar entity"); - unsigned shapeRank = getShape().getType().cast().getRank(); + unsigned shapeRank = + mlir::cast(getShape().getType()).getRank(); if (shapeRank != getIndices().size()) return emitOpError("body number of indices must match shape rank"); return mlir::success(); @@ -1817,8 +1807,8 @@ static bool yieldsLogical(mlir::Region ®ion, bool mustBeScalarI1) { if (mustBeScalarI1) return hlfir::isI1Type(yieldType); return hlfir::isMaskArgument(yieldType) && - hlfir::getFortranElementOrSequenceType(yieldType) - .isa(); + mlir::isa( + hlfir::getFortranElementOrSequenceType(yieldType)); } mlir::LogicalResult hlfir::ForallMaskOp::verify() { diff --git a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp index 1c4f82e2de81..d4e4835ee726 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp @@ -77,7 +77,7 @@ static mlir::Value packageBufferizedExpr(mlir::Location loc, /// currently enforced by the verifiers that only accept HLFIR value or /// variable types which do not include tuples. static hlfir::Entity getBufferizedExprStorage(mlir::Value bufferizedExpr) { - auto tupleType = bufferizedExpr.getType().dyn_cast(); + auto tupleType = mlir::dyn_cast(bufferizedExpr.getType()); if (!tupleType) return hlfir::Entity{bufferizedExpr}; assert(tupleType.size() == 2 && "unexpected tuple type"); @@ -90,7 +90,7 @@ static hlfir::Entity getBufferizedExprStorage(mlir::Value bufferizedExpr) { /// Helper to extract the clean-up flag from a tuple created by /// packageBufferizedExpr. static mlir::Value getBufferizedExprMustFreeFlag(mlir::Value bufferizedExpr) { - auto tupleType = bufferizedExpr.getType().dyn_cast(); + auto tupleType = mlir::dyn_cast(bufferizedExpr.getType()); if (!tupleType) return bufferizedExpr; assert(tupleType.size() == 2 && "unexpected tuple type"); @@ -218,7 +218,7 @@ struct ShapeOfOpConversion } else { // everything else failed so try to create a shape from static type info hlfir::ExprType exprTy = - adaptor.getExpr().getType().dyn_cast_or_null(); + mlir::dyn_cast_or_null(adaptor.getExpr().getType()); if (exprTy) shape = hlfir::genExprShape(builder, loc, exprTy); } @@ -480,10 +480,10 @@ struct AssociateOpConversion assert(mlir::isa(sourceVar.getType()) && fir::isAllocatableType(sourceVar.getType())); assert(sourceVar.getType() == assocType); - } else if ((sourceVar.getType().isa() && - !assocType.isa()) || - ((sourceVar.getType().isa() && - !assocType.isa()))) { + } else if ((mlir::isa(sourceVar.getType()) && + !mlir::isa(assocType)) || + ((mlir::isa(sourceVar.getType()) && + !mlir::isa(assocType)))) { sourceVar = builder.create(loc, assocType, sourceVar); } else { sourceVar = builder.createConvert(loc, assocType, sourceVar); @@ -590,13 +590,13 @@ static void genBufferDestruction(mlir::Location loc, fir::FirOpBuilder &builder, // for MERGE with polymorphic results. if (mustFinalize) TODO(loc, "finalizing polymorphic temporary in HLFIR"); - } else if (var.getType().isa()) { + } else if (mlir::isa(var.getType())) { if (mustFinalize && !mlir::isa(var.getType())) fir::emitFatalError(loc, "non-finalizable variable"); addr = builder.create(loc, heapType, var); } else { - if (!var.getType().isa()) + if (!mlir::isa(var.getType())) addr = builder.create(loc, heapType, var); if (mustFinalize || deallocComponents) { @@ -831,7 +831,7 @@ struct ElementalOpConversion // the assign, insert an hlfir.destroy to mark the expression end-of-life. // If the expression creation allocated a buffer on the heap inside the // loop, this will ensure the buffer properly deallocated. - if (elementValue.getType().isa() && + if (mlir::isa(elementValue.getType()) && wasCreatedInCurrentBlock(elementValue, builder)) builder.create(loc, elementValue); } @@ -926,11 +926,12 @@ public: hlfir::EndAssociateOp, hlfir::SetLengthOp>(); target.markUnknownOpDynamicallyLegal([](mlir::Operation *op) { - return llvm::all_of( - op->getResultTypes(), - [](mlir::Type ty) { return !ty.isa(); }) && + return llvm::all_of(op->getResultTypes(), + [](mlir::Type ty) { + return !mlir::isa(ty); + }) && llvm::all_of(op->getOperandTypes(), [](mlir::Type ty) { - return !ty.isa(); + return !mlir::isa(ty); }); }); if (mlir::failed( diff --git a/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp index cd534bae4ad2..517285dce133 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp @@ -34,7 +34,7 @@ using namespace mlir; static mlir::Value genAllocatableTempFromSourceBox(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value sourceBox) { - assert(sourceBox.getType().isa() && + assert(mlir::isa(sourceBox.getType()) && "must be a base box type"); // Use the runtime to make a quick and dirty temp with the rhs value. // Overkill for scalar rhs that could be done in much more clever ways. @@ -44,7 +44,7 @@ static mlir::Value genAllocatableTempFromSourceBox(mlir::Location loc, // This has the huge benefit of dealing with all cases, including // polymorphic entities. mlir::Type fromHeapType = fir::HeapType::get(fir::unwrapRefType( - sourceBox.getType().cast().getEleTy())); + mlir::cast(sourceBox.getType()).getEleTy())); mlir::Type fromBoxHeapType = fir::BoxType::get(fromHeapType); mlir::Value fromMutableBox = fir::factory::genNullBoxStorage(builder, loc, fromBoxHeapType); @@ -69,7 +69,7 @@ public: auto module = assignOp->getParentOfType(); fir::FirOpBuilder builder(rewriter, module); - if (rhs.getType().isa()) { + if (mlir::isa(rhs.getType())) { mlir::emitError(loc, "hlfir must be bufferized with --bufferize-hlfir " "pass before being converted to FIR"); return mlir::failure(); @@ -343,16 +343,15 @@ public: auto firBase = firDeclareOp.getResult(); mlir::Value hlfirBase; mlir::Type hlfirBaseType = declareOp.getBase().getType(); - if (hlfirBaseType.isa()) { + if (mlir::isa(hlfirBaseType)) { fir::FirOpBuilder builder(rewriter, declareOp.getOperation()); // Helper to generate the hlfir fir.box with the local lower bounds and // type parameters. auto genHlfirBox = [&]() -> mlir::Value { - if (!firBase.getType().isa()) { + if (!mlir::isa(firBase.getType())) { llvm::SmallVector typeParams; - auto maybeCharType = - fir::unwrapSequenceType(fir::unwrapPassByRefType(hlfirBaseType)) - .dyn_cast(); + auto maybeCharType = mlir::dyn_cast( + fir::unwrapSequenceType(fir::unwrapPassByRefType(hlfirBaseType))); if (!maybeCharType || maybeCharType.hasDynamicLen()) typeParams.append(declareOp.getTypeparams().begin(), declareOp.getTypeparams().end()); @@ -399,7 +398,7 @@ public: }) .getResults()[0]; } - } else if (hlfirBaseType.isa()) { + } else if (mlir::isa(hlfirBaseType)) { assert(declareOp.getTypeparams().size() == 1 && "must contain character length"); hlfirBase = rewriter.create( @@ -480,11 +479,12 @@ public: // - scalar%scalar_component [substring|complex_part] or // - scalar%static_size_array_comp // - scalar%array(indices) [substring| complex part] - mlir::Type componentType = baseEleTy.cast().getType( - designate.getComponent().value()); + mlir::Type componentType = + mlir::cast(baseEleTy).getType( + designate.getComponent().value()); mlir::Type coorTy = fir::ReferenceType::get(componentType); base = builder.create(loc, coorTy, base, fieldIndex); - if (componentType.isa()) { + if (mlir::isa(componentType)) { auto variableInterface = mlir::cast( designate.getOperation()); if (variableInterface.isAllocatable() || @@ -500,14 +500,14 @@ public: } else { // array%component[(indices) substring|complex part] cases. // Component ref of array bases are dealt with below in embox/rebox. - assert(designateResultType.isa()); + assert(mlir::isa(designateResultType)); } } - if (designateResultType.isa()) { + if (mlir::isa(designateResultType)) { // Generate embox or rebox. mlir::Type eleTy = fir::unwrapPassByRefType(designateResultType); - bool isScalarDesignator = !eleTy.isa(); + bool isScalarDesignator = !mlir::isa(eleTy); mlir::Value sourceBox; if (isScalarDesignator) { // The base box will be used for emboxing the scalar element. @@ -583,7 +583,7 @@ public: assert(sliceFields.empty() && substring.empty()); llvm::SmallVector resultType{designateResultType}; mlir::Value resultBox; - if (base.getType().isa()) + if (mlir::isa(base.getType())) resultBox = builder.create(loc, resultType, base, shape, slice); else @@ -598,7 +598,8 @@ public: // first element of a contiguous array section with compile time constant // shape. The base may be an array, or a scalar. mlir::Type resultAddressType = designateResultType; - if (auto boxCharType = designateResultType.dyn_cast()) + if (auto boxCharType = + mlir::dyn_cast(designateResultType)) resultAddressType = fir::ReferenceType::get(boxCharType.getEleTy()); // Array element indexing. @@ -620,7 +621,7 @@ public: // Scalar complex part ref if (designate.getComplexPart()) { // Sequence types should have already been handled by this point - assert(!designateResultType.isa()); + assert(!mlir::isa(designateResultType)); auto index = builder.createIntegerConstant(loc, builder.getIndexType(), *designate.getComplexPart()); auto coorTy = fir::ReferenceType::get(resultEleTy); @@ -628,7 +629,7 @@ public: } // Cast/embox the computed scalar address if needed. - if (designateResultType.isa()) { + if (mlir::isa(designateResultType)) { assert(designate.getTypeparams().size() == 1 && "must have character length"); auto emboxChar = builder.create( @@ -671,13 +672,13 @@ public: mlir::PatternRewriter &rewriter) const override { mlir::Location loc = parentComponent.getLoc(); mlir::Type resultType = parentComponent.getType(); - if (!parentComponent.getType().isa()) { + if (!mlir::isa(parentComponent.getType())) { mlir::Value baseAddr = parentComponent.getMemref(); // Scalar parent component ref without any length type parameters. The // input may be a fir.class if it is polymorphic, since this is a scalar // and the output will be monomorphic, the base address can be extracted // from the fir.class. - if (baseAddr.getType().isa()) + if (mlir::isa(baseAddr.getType())) baseAddr = rewriter.create(loc, baseAddr); rewriter.replaceOpWithNewOp(parentComponent, resultType, baseAddr); @@ -686,7 +687,7 @@ public: // Array parent component ref or PDTs. hlfir::Entity base{parentComponent.getMemref()}; mlir::Value baseAddr = base.getBase(); - if (!baseAddr.getType().isa()) { + if (!mlir::isa(baseAddr.getType())) { // Embox cannot directly be used to address parent components: it expects // the output type to match the input type when there are no slices. When // the types have at least one component, a slice to the first element can @@ -748,7 +749,7 @@ public: // the hlfir.shape_of operation which led to the creation of this get_extent // operation should now have been lowered to a fir.shape operation if (auto s = mlir::dyn_cast_or_null(shapeOp)) { - fir::ShapeType shapeTy = shape.getType().cast(); + fir::ShapeType shapeTy = mlir::cast(shape.getType()); llvm::APInt dim = getExtentOp.getDim(); uint64_t dimVal = dim.getLimitedValue(shapeTy.getRank()); mlir::Value extent = s.getExtents()[dimVal]; diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp index 0142fb0cfb0b..e9dbb7095d0e 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp @@ -185,7 +185,7 @@ protected: // the width for use in runtime intrinsic calls. static unsigned getKindForType(mlir::Type ty) { mlir::Type eltty = hlfir::getFortranElementType(ty); - unsigned width = eltty.cast().getWidth(); + unsigned width = mlir::cast(eltty).getWidth(); return width / 8; } diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp index 84101353a740..63b52c0cd0bc 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp @@ -1090,7 +1090,7 @@ void OrderedAssignmentRewriter::generateSaveEntity( mlir::Value loopExtent = computeLoopNestIterationNumber(loc, builder, loopNest); auto sequenceType = - builder.getVarLenSeqTy(entityType).cast(); + mlir::cast(builder.getVarLenSeqTy(entityType)); temp = insertSavedEntity(region, fir::factory::HomogeneousScalarStack{ loc, builder, sequenceType, loopExtent, diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp index 685c73d67625..8d68c7021608 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp @@ -249,7 +249,7 @@ static bool areIdenticalOrDisjointSlices(mlir::Value ref1, mlir::Value ref2) { auto isPositiveConstant = [](mlir::Value v) -> bool { if (auto conOp = mlir::dyn_cast(v.getDefiningOp())) - if (auto iattr = conOp.getValue().dyn_cast()) + if (auto iattr = mlir::dyn_cast(conOp.getValue())) return iattr.getInt() > 0; return false; }; @@ -601,7 +601,7 @@ mlir::LogicalResult VariableAssignBufferization::matchAndRewrite( // TODO: ExprType check is here to avoid conflicts with // ElementalAssignBufferization pattern. We need to combine // these matchers into a single one that applies to AssignOp. - if (rhs.getType().isa()) + if (mlir::isa(rhs.getType())) return rewriter.notifyMatchFailure(assign, "RHS is not in memory"); if (!rhs.isArray()) @@ -834,7 +834,7 @@ public: unsigned rank = mlir::cast(mloc.getType()).getShape()[0]; mlir::Type arrayType = array.getType(); - if (!arrayType.isa()) + if (!mlir::isa(arrayType)) return rewriter.notifyMatchFailure( mloc, "Currently requires a boxed type input"); mlir::Type elementType = hlfir::getFortranElementType(arrayType); @@ -850,7 +850,7 @@ public: auto init = [isMax](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); llvm::APFloat limit = llvm::APFloat::getInf(sem, /*Negative=*/isMax); return builder.createRealConstant(loc, elementType, limit); @@ -901,7 +901,7 @@ public: // Compare with the max reduction value mlir::Value cmp; - if (elementType.isa()) { + if (mlir::isa(elementType)) { // For FP reductions we want the first smallest value to be used, that // is not NaN. A OGL/OLT condition will usually work for this unless all // the values are Nan or Inf. This follows the same logic as @@ -918,7 +918,7 @@ public: loc, mlir::arith::CmpFPredicate::OEQ, elem, elem); cmpNan = builder.create(loc, cmpNan, cmpNan2); cmp = builder.create(loc, cmp, cmpNan); - } else if (elementType.isa()) { + } else if (mlir::isa(elementType)) { cmp = builder.create( loc, isMax ? mlir::arith::CmpIPredicate::sgt diff --git a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp index 2751575ce982..b761563eba0f 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp @@ -103,7 +103,8 @@ public: // by hlfir.elemental) target.addDynamicallyLegalOp( [](hlfir::TransposeOp transpose) { - return transpose.getType().cast().isPolymorphic(); + return mlir::cast(transpose.getType()) + .isPolymorphic(); }); target.markUnknownOpDynamicallyLegal( [](mlir::Operation *) { return true; }); diff --git a/flang/lib/Optimizer/Transforms/AbstractResult.cpp b/flang/lib/Optimizer/Transforms/AbstractResult.cpp index eb4dd637bb16..85472cdc5103 100644 --- a/flang/lib/Optimizer/Transforms/AbstractResult.cpp +++ b/flang/lib/Optimizer/Transforms/AbstractResult.cpp @@ -65,14 +65,14 @@ static mlir::FunctionType getCPtrFunctionType(mlir::FunctionType funcTy) { auto resultType = funcTy.getResult(0); assert(fir::isa_builtin_cptr_type(resultType)); llvm::SmallVector outputTypes; - auto recTy = resultType.dyn_cast(); + auto recTy = mlir::dyn_cast(resultType); outputTypes.emplace_back(recTy.getTypeList()[0].second); return mlir::FunctionType::get(funcTy.getContext(), funcTy.getInputs(), outputTypes); } static bool mustEmboxResult(mlir::Type resultType, bool shouldBoxResult) { - return resultType.isa() && + return mlir::isa(resultType) && shouldBoxResult; } @@ -114,7 +114,7 @@ public: bool isResultBuiltinCPtr = fir::isa_builtin_cptr_type(result.getType()); Op newOp; if (isResultBuiltinCPtr) { - auto recTy = result.getType().template dyn_cast(); + auto recTy = mlir::dyn_cast(result.getType()); newResultTypes.emplace_back(recTy.getTypeList()[0].second); } @@ -261,7 +261,7 @@ public: mlir::LogicalResult matchAndRewrite(fir::AddrOfOp addrOf, mlir::PatternRewriter &rewriter) const override { - auto oldFuncTy = addrOf.getType().cast(); + auto oldFuncTy = mlir::cast(addrOf.getType()); mlir::FunctionType newFuncTy; // TODO: This should be generalized for derived types, and it is // architecture and OS dependent. @@ -296,7 +296,7 @@ public: auto loc = func.getLoc(); auto *context = &getContext(); // Convert function type itself if it has an abstract result. - auto funcTy = func.getFunctionType().cast(); + auto funcTy = mlir::cast(func.getFunctionType()); if (hasAbstractResult(funcTy)) { // TODO: This should be generalized for derived types, and it is // architecture and OS dependent. @@ -343,11 +343,11 @@ public: return mlir::TypeSwitch(type) .Case([](fir::BoxProcType boxProc) { return fir::hasAbstractResult( - boxProc.getEleTy().cast()); + mlir::cast(boxProc.getEleTy())); }) .Case([](fir::PointerType pointer) { return fir::hasAbstractResult( - pointer.getEleTy().cast()); + mlir::cast(pointer.getEleTy())); }) .Default([](auto &&) { return false; }); } @@ -411,7 +411,7 @@ public: return !hasAbstractResult(call.getFunctionType()); }); target.addDynamicallyLegalOp([](fir::AddrOfOp addrOf) { - if (auto funTy = addrOf.getType().dyn_cast()) + if (auto funTy = mlir::dyn_cast(addrOf.getType())) return !hasAbstractResult(funTy); return true; }); diff --git a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp index 68584bef055b..18d98a11ef3c 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp @@ -69,7 +69,7 @@ void AddDebugInfoPass::runOnOperation() { // In that case, 'inputFilename' may be empty. Location embedded in the // module will be used to get file name and its directory. if (inputFilename.empty()) { - if (auto fileLoc = module.getLoc().dyn_cast()) { + if (auto fileLoc = mlir::dyn_cast(module.getLoc())) { fileName = llvm::sys::path::filename(fileLoc.getFilename().getValue()); filePath = llvm::sys::path::parent_path(fileLoc.getFilename().getValue()); } else @@ -94,14 +94,14 @@ void AddDebugInfoPass::runOnOperation() { mlir::Location l = funcOp->getLoc(); // If fused location has already been created then nothing to do // Otherwise, create a fused location. - if (l.dyn_cast()) + if (mlir::dyn_cast(l)) return; unsigned int CC = (funcOp.getName() == fir::NameUniquer::doProgramEntry()) ? llvm::dwarf::getCallingConvention("DW_CC_program") : llvm::dwarf::getCallingConvention("DW_CC_normal"); - if (auto funcLoc = l.dyn_cast()) { + if (auto funcLoc = mlir::dyn_cast(l)) { fileName = llvm::sys::path::filename(funcLoc.getFilename().getValue()); filePath = llvm::sys::path::parent_path(funcLoc.getFilename().getValue()); } diff --git a/flang/lib/Optimizer/Transforms/AffineDemotion.cpp b/flang/lib/Optimizer/Transforms/AffineDemotion.cpp index da29ae880700..b4523a060f5a 100644 --- a/flang/lib/Optimizer/Transforms/AffineDemotion.cpp +++ b/flang/lib/Optimizer/Transforms/AffineDemotion.cpp @@ -98,14 +98,15 @@ public: mlir::LogicalResult matchAndRewrite(fir::ConvertOp op, mlir::PatternRewriter &rewriter) const override { - if (op.getRes().getType().isa()) { + if (mlir::isa(op.getRes().getType())) { // due to index calculation moving to affine maps we still need to // add converts for sequence types this has a side effect of losing // some information about arrays with known dimensions by creating: // fir.convert %arg0 : (!fir.ref>) -> // !fir.ref> - if (auto refTy = op.getValue().getType().dyn_cast()) - if (auto arrTy = refTy.getEleTy().dyn_cast()) { + if (auto refTy = + mlir::dyn_cast(op.getValue().getType())) + if (auto arrTy = mlir::dyn_cast(refTy.getEleTy())) { fir::SequenceType::Shape flatShape = { fir::SequenceType::getUnknownExtent()}; auto flatArrTy = fir::SequenceType::get(flatShape, arrTy.getEleTy()); @@ -158,7 +159,7 @@ public: mlir::ConversionTarget target(*context); target.addIllegalOp(); target.addDynamicallyLegalOp([](fir::ConvertOp op) { - if (op.getRes().getType().isa()) + if (mlir::isa(op.getRes().getType())) return false; return true; }); diff --git a/flang/lib/Optimizer/Transforms/AffinePromotion.cpp b/flang/lib/Optimizer/Transforms/AffinePromotion.cpp index 64531cb1868e..7d0131ac6fa4 100644 --- a/flang/lib/Optimizer/Transforms/AffinePromotion.cpp +++ b/flang/lib/Optimizer/Transforms/AffinePromotion.cpp @@ -111,7 +111,7 @@ private: bool analyzeReference(mlir::Value memref, mlir::Operation *op) { if (auto acoOp = memref.getDefiningOp()) { - if (acoOp.getMemref().getType().isa()) { + if (mlir::isa(acoOp.getMemref().getType())) { // TODO: Look if and how fir.box can be promoted to affine. LLVM_DEBUG(llvm::dbgs() << "AffineLoopAnalysis: cannot promote loop, " "array memory operation uses fir.box\n"; @@ -222,7 +222,7 @@ private: return affineBinaryOp(mlir::AffineExprKind::Mod, op.getLhs(), op.getRhs()); if (auto op = value.getDefiningOp()) - if (auto intConstant = op.getValue().dyn_cast()) + if (auto intConstant = mlir::dyn_cast(op.getValue())) return toAffineExpr(intConstant.getInt()); if (auto blockArg = mlir::dyn_cast(value)) { affineArgs.push_back(value); @@ -331,15 +331,16 @@ static mlir::AffineMap createArrayIndexAffineMap(unsigned dimensions, static std::optional constantIntegerLike(const mlir::Value value) { if (auto definition = value.getDefiningOp()) - if (auto stepAttr = definition.getValue().dyn_cast()) + if (auto stepAttr = mlir::dyn_cast(definition.getValue())) return stepAttr.getInt(); return {}; } static mlir::Type coordinateArrayElement(fir::ArrayCoorOp op) { if (auto refType = - op.getMemref().getType().dyn_cast_or_null()) { - if (auto seqType = refType.getEleTy().dyn_cast_or_null()) { + mlir::dyn_cast_or_null(op.getMemref().getType())) { + if (auto seqType = + mlir::dyn_cast_or_null(refType.getEleTy())) { return seqType.getEleTy(); } } diff --git a/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp b/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp index a08d58383d3a..ebc186222525 100644 --- a/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp +++ b/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp @@ -461,9 +461,9 @@ void ArrayCopyAnalysisBase::arrayMentions( } static bool hasPointerType(mlir::Type type) { - if (auto boxTy = type.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(type)) type = boxTy.getEleTy(); - return type.isa(); + return mlir::isa(type); } // This is a NF performance hack. It makes a simple test that the slices of the @@ -512,7 +512,7 @@ static bool mutuallyExclusiveSliceRange(ArrayLoadOp ld, ArrayMergeStoreOp st) { auto isPositiveConstant = [](mlir::Value v) -> bool { if (auto conOp = mlir::dyn_cast(v.getDefiningOp())) - if (auto iattr = conOp.getValue().dyn_cast()) + if (auto iattr = mlir::dyn_cast(conOp.getValue())) return iattr.getInt() > 0; return false; }; @@ -725,8 +725,8 @@ static bool conservativeCallConflict(llvm::ArrayRef reaches) { return llvm::any_of(reaches, [](mlir::Operation *op) { if (auto call = mlir::dyn_cast(op)) - if (auto callee = - call.getCallableForCallee().dyn_cast()) { + if (auto callee = mlir::dyn_cast( + call.getCallableForCallee())) { auto module = op->getParentOfType(); return isInternalProcedure( module.lookupSymbol(callee)); @@ -891,9 +891,9 @@ static mlir::Value getOrReadExtentsAndShapeOp( if (arrLoad->hasAttr(fir::getOptionalAttrName())) fir::emitFatalError( loc, "shapes from array load of OPTIONAL arrays must not be used"); - if (auto boxTy = arrLoad.getMemref().getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(arrLoad.getMemref().getType())) { auto rank = - dyn_cast_ptrOrBoxEleTy(boxTy).cast().getDimension(); + mlir::cast(dyn_cast_ptrOrBoxEleTy(boxTy)).getDimension(); auto idxTy = rewriter.getIndexType(); for (decltype(rank) dim = 0; dim < rank; ++dim) { auto dimVal = rewriter.create(loc, dim); @@ -929,7 +929,7 @@ static mlir::Type toRefType(mlir::Type ty) { static llvm::SmallVector getTypeParamsIfRawData(mlir::Location loc, FirOpBuilder &builder, ArrayLoadOp arrLoad, mlir::Type ty) { - if (ty.isa()) + if (mlir::isa(ty)) return {}; return fir::factory::getTypeParams(loc, builder, arrLoad); } @@ -947,8 +947,8 @@ static mlir::Value genCoorOp(mlir::PatternRewriter &rewriter, originated = factory::originateIndices(loc, rewriter, alloc.getType(), shape, indices); auto seqTy = dyn_cast_ptrOrBoxEleTy(alloc.getType()); - assert(seqTy && seqTy.isa()); - const auto dimension = seqTy.cast().getDimension(); + assert(seqTy && mlir::isa(seqTy)); + const auto dimension = mlir::cast(seqTy).getDimension(); auto module = load->getParentOfType(); FirOpBuilder builder(rewriter, module); auto typeparams = getTypeParamsIfRawData(loc, builder, load, alloc.getType()); @@ -967,7 +967,7 @@ static mlir::Value getCharacterLen(mlir::Location loc, FirOpBuilder &builder, ArrayLoadOp load, CharacterType charTy) { auto charLenTy = builder.getCharacterLengthType(); if (charTy.hasDynamicLen()) { - if (load.getMemref().getType().isa()) { + if (mlir::isa(load.getMemref().getType())) { // The loaded array is an emboxed value. Get the CHARACTER length from // the box value. auto eleSzInBytes = @@ -1027,7 +1027,7 @@ void genArrayCopy(mlir::Location loc, mlir::PatternRewriter &rewriter, getTypeParamsIfRawData(loc, builder, arrLoad, dst.getType())); auto eleTy = unwrapSequenceType(unwrapPassByRefType(dst.getType())); // Copy from (to) object to (from) temp copy of same object. - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { auto len = getCharacterLen(loc, builder, arrLoad, charTy); CharBoxValue toChar(toAddr, len); CharBoxValue fromChar(fromAddr, len); @@ -1049,8 +1049,8 @@ genArrayLoadTypeParameters(mlir::Location loc, mlir::PatternRewriter &rewriter, auto eleTy = unwrapSequenceType(unwrapPassByRefType(load.getMemref().getType())); if (hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { - assert(load.getMemref().getType().isa()); + if (auto charTy = mlir::dyn_cast(eleTy)) { + assert(mlir::isa(load.getMemref().getType())); auto module = load->getParentOfType(); FirOpBuilder builder(rewriter, module); return {getCharacterLen(loc, builder, load, charTy)}; @@ -1067,7 +1067,7 @@ findNonconstantExtents(mlir::Type memrefTy, llvm::ArrayRef extents) { llvm::SmallVector nce; auto arrTy = unwrapPassByRefType(memrefTy); - auto seqTy = arrTy.cast(); + auto seqTy = mlir::cast(arrTy); for (auto [s, x] : llvm::zip(seqTy.getShape(), extents)) if (s == SequenceType::getUnknownExtent()) nce.emplace_back(x); diff --git a/flang/lib/Optimizer/Transforms/CharacterConversion.cpp b/flang/lib/Optimizer/Transforms/CharacterConversion.cpp index 87ea72dbca9b..44baad73aa25 100644 --- a/flang/lib/Optimizer/Transforms/CharacterConversion.cpp +++ b/flang/lib/Optimizer/Transforms/CharacterConversion.cpp @@ -60,8 +60,8 @@ public: // For each code point in the `from` string, convert naively to the `to` // string code point. Conversion is done blindly on size only, not value. auto getCharBits = [&](mlir::Type t) { - auto chrTy = fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t)) - .cast(); + auto chrTy = mlir::cast( + fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t))); return kindMap.getCharacterBitsize(chrTy.getFKind()); }; auto fromBits = getCharBits(conv.getFrom().getType()); diff --git a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp index 0afc9c24b45b..38cdc2b1388d 100644 --- a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp +++ b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp @@ -147,7 +147,7 @@ struct ArgsUsageInLoop { static fir::SequenceType getAsSequenceType(mlir::Value *v) { mlir::Type argTy = fir::unwrapPassByRefType(fir::unwrapRefType(v->getType())); - return argTy.dyn_cast(); + return mlir::dyn_cast(argTy); } /// if a value comes from a fir.declare, follow it to the original source, diff --git a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp index 40b452a6202b..ada67b4201e1 100644 --- a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp +++ b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp @@ -65,7 +65,7 @@ keepStackAllocation(fir::AllocaOp alloca, mlir::Block *entry, // TODO: Generalize the algorithm and placement of the freemem nodes. if (alloca->getBlock() != entry) return true; - if (auto seqTy = alloca.getInType().dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(alloca.getInType())) { if (fir::hasDynamicSize(seqTy)) { // Move all arrays with runtime determined size to the heap. if (options.dynamicArrayOnHeap) diff --git a/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp b/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp index 93efea434cb1..d933dc58f375 100644 --- a/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp +++ b/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp @@ -97,8 +97,8 @@ struct DispatchOpConv : public OpConversionPattern { // Get derived type information. mlir::Type declaredType = fir::getDerivedType(dispatch.getObject().getType().getEleTy()); - assert(declaredType.isa() && "expecting fir.type"); - auto recordType = declaredType.dyn_cast(); + assert(mlir::isa(declaredType) && "expecting fir.type"); + auto recordType = mlir::dyn_cast(declaredType); // Lookup for the binding table. auto bindingsIter = bindingTables.find(recordType.getName()); @@ -157,7 +157,7 @@ struct DispatchOpConv : public OpConversionPattern { // Load the bindings descriptor. auto bindingsCompName = Fortran::semantics::bindingDescCompName; - fir::RecordType typeDescRecTy = typeDescTy.cast(); + fir::RecordType typeDescRecTy = mlir::cast(typeDescTy); mlir::Value field = rewriter.create( loc, fieldTy, bindingsCompName, typeDescRecTy, mlir::ValueRange{}); mlir::Type coorTy = @@ -168,8 +168,8 @@ struct DispatchOpConv : public OpConversionPattern { // Load the correct binding. mlir::Value bindings = rewriter.create(loc, bindingBox); - fir::RecordType bindingTy = - fir::unwrapIfDerived(bindingBox.getType().cast()); + fir::RecordType bindingTy = fir::unwrapIfDerived( + mlir::cast(bindingBox.getType())); mlir::Type bindingAddrTy = fir::ReferenceType::get(bindingTy); mlir::Value bindingIdxVal = rewriter.create( loc, rewriter.getIndexType(), rewriter.getIndexAttr(bindingIdx)); @@ -181,7 +181,7 @@ struct DispatchOpConv : public OpConversionPattern { mlir::Value procField = rewriter.create( loc, fieldTy, procCompName, bindingTy, mlir::ValueRange{}); fir::RecordType procTy = - bindingTy.getType(procCompName).cast(); + mlir::cast(bindingTy.getType(procCompName)); mlir::Type procRefTy = fir::ReferenceType::get(procTy); mlir::Value procRef = rewriter.create( loc, procRefTy, bindingAddr, procField); @@ -298,13 +298,13 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( // before in the list to respect point 3. above. Otherwise it is just // added in order at the end. for (unsigned t = 0; t < typeGuardNum; ++t) { - if (auto a = typeGuards[t].dyn_cast()) { + if (auto a = mlir::dyn_cast(typeGuards[t])) { orderedTypeGuards.push_back(t); continue; } - if (auto a = typeGuards[t].dyn_cast()) { - if (auto recTy = a.getType().dyn_cast()) { + if (auto a = mlir::dyn_cast(typeGuards[t])) { + if (auto recTy = mlir::dyn_cast(a.getType())) { auto dt = mod.lookupSymbol(recTy.getName()); assert(dt && "dispatch table not found"); llvm::SmallSet ancestors = @@ -313,8 +313,8 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( auto it = orderedClassIsGuards.begin(); while (it != orderedClassIsGuards.end()) { fir::SubclassAttr sAttr = - typeGuards[*it].dyn_cast(); - if (auto ty = sAttr.getType().dyn_cast()) { + mlir::dyn_cast(typeGuards[*it]); + if (auto ty = mlir::dyn_cast(sAttr.getType())) { if (ancestors.contains(ty.getName())) break; } @@ -339,7 +339,7 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( auto *dest = selectType.getSuccessor(idx); std::optional destOps = selectType.getSuccessorOperands(operands, idx); - if (typeGuards[idx].dyn_cast()) + if (mlir::dyn_cast(typeGuards[idx])) rewriter.replaceOpWithNewOp( selectType, dest, destOps.value_or(mlir::ValueRange{})); else if (mlir::failed(genTypeLadderStep(loc, selector, typeGuards[idx], @@ -357,9 +357,9 @@ mlir::LogicalResult SelectTypeConv::genTypeLadderStep( fir::KindMapping &kindMap) const { mlir::Value cmp; // TYPE IS type guard comparison are all done inlined. - if (auto a = attr.dyn_cast()) { + if (auto a = mlir::dyn_cast(attr)) { if (fir::isa_trivial(a.getType()) || - a.getType().isa()) { + mlir::isa(a.getType())) { // For type guard statement with Intrinsic type spec the type code of // the descriptor is compared. int code = fir::getTypeCode(a.getType(), kindMap); @@ -383,10 +383,10 @@ mlir::LogicalResult SelectTypeConv::genTypeLadderStep( cmp = res; } // CLASS IS type guard statement is done with a runtime call. - } else if (auto a = attr.dyn_cast()) { + } else if (auto a = mlir::dyn_cast(attr)) { // Retrieve the type descriptor from the type guard statement record type. - assert(a.getType().isa() && "expect fir.record type"); - fir::RecordType recTy = a.getType().dyn_cast(); + assert(mlir::isa(a.getType()) && "expect fir.record type"); + fir::RecordType recTy = mlir::dyn_cast(a.getType()); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recTy.getName()); auto typeDescGlobal = mod.lookupSymbol(typeDescName); @@ -438,8 +438,8 @@ mlir::Value SelectTypeConv::genTypeDescCompare(mlir::Location loc, mlir::Value selector, mlir::Type ty, mlir::ModuleOp mod, mlir::PatternRewriter &rewriter) const { - assert(ty.isa() && "expect fir.record type"); - fir::RecordType recTy = ty.dyn_cast(); + assert(mlir::isa(ty) && "expect fir.record type"); + fir::RecordType recTy = mlir::dyn_cast(ty); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recTy.getName()); auto typeDescGlobal = mod.lookupSymbol(typeDescName); diff --git a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp index a4f2f5238e40..601bf04ce5e9 100644 --- a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp +++ b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp @@ -215,8 +215,8 @@ static unsigned getDimCount(mlir::Value val) { // the first ConvertOp that has non-opaque box type that we meet // going through the ConvertOp chain. if (mlir::Value emboxVal = findBoxDef(val)) - if (auto boxTy = emboxVal.getType().dyn_cast()) - if (auto seqTy = boxTy.getEleTy().dyn_cast()) + if (auto boxTy = mlir::dyn_cast(emboxVal.getType())) + if (auto seqTy = mlir::dyn_cast(boxTy.getEleTy())) return seqTy.getDimension(); return 0; } @@ -237,9 +237,9 @@ static std::optional getArgElementType(mlir::Value val) { val = defOp->getOperand(0); // The convert operation is expected to convert from one // box type to another box type. - auto boxType = val.getType().cast(); + auto boxType = mlir::cast(val.getType()); auto elementType = fir::unwrapSeqOrBoxedSeqType(boxType); - if (!elementType.isa()) + if (!mlir::isa(elementType)) return elementType; } while (true); } @@ -381,7 +381,7 @@ static void genRuntimeSumBody(fir::FirOpBuilder &builder, // end function RTNAME(Sum)x_simplified auto zero = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant(loc, elementType, llvm::APFloat::getZero(sem)); @@ -392,9 +392,9 @@ static void genRuntimeSumBody(fir::FirOpBuilder &builder, auto genBodyOp = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType, mlir::Value elem1, mlir::Value elem2) -> mlir::Value { - if (elementType.isa()) + if (mlir::isa(elementType)) return builder.create(loc, elem1, elem2); - if (elementType.isa()) + if (mlir::isa(elementType)) return builder.create(loc, elem1, elem2); llvm_unreachable("unsupported type"); @@ -414,7 +414,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, mlir::Type elementType) { auto init = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, elementType, llvm::APFloat::getLargest(sem, /*Negative=*/true)); @@ -427,7 +427,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, auto genBodyOp = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType, mlir::Value elem1, mlir::Value elem2) -> mlir::Value { - if (elementType.isa()) { + if (mlir::isa(elementType)) { // arith.maxf later converted to llvm.intr.maxnum does not work // correctly for NaNs and -0.0 (see maxnum/minnum pattern matching // in LLVM's InstCombine pass). Moreover, llvm.intr.maxnum @@ -439,7 +439,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, loc, mlir::arith::CmpFPredicate::OGT, elem1, elem2); return builder.create(loc, compare, elem1, elem2); } - if (elementType.isa()) + if (mlir::isa(elementType)) return builder.create(loc, elem1, elem2); llvm_unreachable("unsupported type"); @@ -662,7 +662,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, mlir::Type resultElemTy, bool isDim) { auto init = [isMax](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); llvm::APFloat limit = llvm::APFloat::getInf(sem, /*Negative=*/isMax); return builder.createRealConstant(loc, elementType, limit); @@ -744,7 +744,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, mlir::Value elem = builder.create(loc, addr); mlir::Value cmp; - if (elementType.isa()) { + if (mlir::isa(elementType)) { // For FP reductions we want the first smallest value to be used, that // is not NaN. A OGL/OLT condition will usually work for this unless all // the values are Nan or Inf. This follows the same logic as @@ -761,7 +761,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, loc, mlir::arith::CmpFPredicate::OEQ, elem, elem); cmpNan = builder.create(loc, cmpNan, cmpNan2); cmp = builder.create(loc, cmp, cmpNan); - } else if (elementType.isa()) { + } else if (mlir::isa(elementType)) { cmp = builder.create( loc, isMax ? mlir::arith::CmpIPredicate::sgt @@ -839,7 +839,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, builder.setInsertionPointToStart(&ifOp.getElseRegion().front()); mlir::Value basicValue; - if (elementType.isa()) { + if (mlir::isa(elementType)) { basicValue = builder.createIntegerConstant(loc, elementType, 0); } else { basicValue = builder.createRealConstant(loc, elementType, 0); @@ -921,7 +921,7 @@ static void genRuntimeDotBody(fir::FirOpBuilder &builder, mlir::IndexType idxTy = builder.getIndexType(); mlir::Value zero = - resultElementType.isa() + mlir::isa(resultElementType) ? builder.createRealConstant(loc, resultElementType, 0.0) : builder.createIntegerConstant(loc, resultElementType, 0); @@ -978,10 +978,10 @@ static void genRuntimeDotBody(fir::FirOpBuilder &builder, // Convert to the result type. elem2 = builder.create(loc, resultElementType, elem2); - if (resultElementType.isa()) + if (mlir::isa(resultElementType)) sumVal = builder.create( loc, builder.create(loc, elem1, elem2), sumVal); - else if (resultElementType.isa()) + else if (mlir::isa(resultElementType)) sumVal = builder.create( loc, builder.create(loc, elem1, elem2), sumVal); else @@ -1056,8 +1056,8 @@ void SimplifyIntrinsicsPass::simplifyIntOrFloatReduction( mlir::Type resultType = call.getResult(0).getType(); - if (!resultType.isa() && - !resultType.isa()) + if (!mlir::isa(resultType) && + !mlir::isa(resultType)) return; auto argType = getArgElementType(args[0]); @@ -1103,7 +1103,8 @@ void SimplifyIntrinsicsPass::simplifyLogicalDim0Reduction( fir::FirOpBuilder builder{getSimplificationBuilder(call, kindMap)}; // Treating logicals as integers makes things a lot easier - fir::LogicalType logicalType = {elementType.dyn_cast()}; + fir::LogicalType logicalType = { + mlir::dyn_cast(elementType)}; fir::KindTy kind = logicalType.getFKind(); mlir::Type intElementType = builder.getIntegerType(kind * 8); @@ -1138,7 +1139,8 @@ void SimplifyIntrinsicsPass::simplifyLogicalDim1Reduction( fir::FirOpBuilder builder{getSimplificationBuilder(call, kindMap)}; // Treating logicals as integers makes things a lot easier - fir::LogicalType logicalType = {elementType.dyn_cast()}; + fir::LogicalType logicalType = { + mlir::dyn_cast(elementType)}; fir::KindTy kind = logicalType.getFKind(); mlir::Type intElementType = builder.getIntegerType(kind * 8); @@ -1182,7 +1184,7 @@ void SimplifyIntrinsicsPass::simplifyMinMaxlocReduction( auto inputBox = findBoxDef(args[1]); mlir::Type inputType = hlfir::getFortranElementType(inputBox.getType()); - if (inputType.isa()) + if (mlir::isa(inputType)) return; int maskRank; @@ -1193,7 +1195,8 @@ void SimplifyIntrinsicsPass::simplifyMinMaxlocReduction( } else { maskRank = getDimCount(mask); mlir::Type maskElemTy = hlfir::getFortranElementType(maskDef.getType()); - fir::LogicalType logicalFirType = {maskElemTy.dyn_cast()}; + fir::LogicalType logicalFirType = { + mlir::dyn_cast(maskElemTy)}; kind = logicalFirType.getFKind(); // Convert fir::LogicalType to mlir::Type logicalElemType = logicalFirType; @@ -1302,7 +1305,8 @@ void SimplifyIntrinsicsPass::runOnOperation() { std::string fmfString{builder.getFastMathFlagsString()}; mlir::Type type = call.getResult(0).getType(); - if (!type.isa() && !type.isa()) + if (!mlir::isa(type) && + !mlir::isa(type)) return; // Try to find the element types of the boxed arguments. diff --git a/flang/lib/Optimizer/Transforms/StackArrays.cpp b/flang/lib/Optimizer/Transforms/StackArrays.cpp index c81524dd16a7..16bbb1c35646 100644 --- a/flang/lib/Optimizer/Transforms/StackArrays.cpp +++ b/flang/lib/Optimizer/Transforms/StackArrays.cpp @@ -351,7 +351,7 @@ void AllocationAnalysis::visitOperation(mlir::Operation *op, } auto retTy = allocmem.getAllocatedType(); - if (!retTy.isa()) { + if (!mlir::isa(retTy)) { LLVM_DEBUG(llvm::dbgs() << "--Allocation is not for an array: skipping\n"); return; diff --git a/flang/unittests/Optimizer/Builder/ComplexTest.cpp b/flang/unittests/Optimizer/Builder/ComplexTest.cpp index 5364eec904ff..17171512470a 100644 --- a/flang/unittests/Optimizer/Builder/ComplexTest.cpp +++ b/flang/unittests/Optimizer/Builder/ComplexTest.cpp @@ -96,6 +96,6 @@ TEST_F(ComplexTest, verifyConvertWithSemantics) { // Convert complex to integer mlir::Value v2 = firBuilder->convertWithSemantics(loc, integerTy1, v1); - EXPECT_TRUE(v2.getType().isa()); + EXPECT_TRUE(mlir::isa(v2.getType())); EXPECT_TRUE(mlir::dyn_cast(v2.getDefiningOp())); } diff --git a/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp b/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp index 7e7206dbf934..d0a9342914a3 100644 --- a/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp +++ b/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp @@ -34,7 +34,7 @@ public: void checkConstantValue(const mlir::Value &value, int64_t v) { EXPECT_TRUE(mlir::isa(value.getDefiningOp())); auto cstOp = dyn_cast(value.getDefiningOp()); - auto valueAttr = cstOp.getValue().dyn_cast_or_null(); + auto valueAttr = dyn_cast_or_null(cstOp.getValue()); EXPECT_EQ(v, valueAttr.getInt()); } diff --git a/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp b/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp index b6a1f9c9db8f..e5e5454ee88a 100644 --- a/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp +++ b/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp @@ -54,7 +54,7 @@ static void checkIntegerConstant(mlir::Value value, mlir::Type ty, int64_t v) { EXPECT_TRUE(mlir::isa(value.getDefiningOp())); auto cstOp = dyn_cast(value.getDefiningOp()); EXPECT_EQ(ty, cstOp.getType()); - auto valueAttr = cstOp.getValue().dyn_cast_or_null(); + auto valueAttr = mlir::dyn_cast_or_null(cstOp.getValue()); EXPECT_EQ(v, valueAttr.getInt()); } @@ -151,7 +151,7 @@ TEST_F(FIRBuilderTest, createRealZeroConstant) { auto cstOp = dyn_cast(cst.getDefiningOp()); EXPECT_EQ(realTy, cstOp.getType()); EXPECT_EQ( - 0u, cstOp.getValue().cast().getValue().convertToDouble()); + 0u, mlir::cast(cstOp.getValue()).getValue().convertToDouble()); } TEST_F(FIRBuilderTest, createBool) { @@ -164,8 +164,8 @@ TEST_F(FIRBuilderTest, createBool) { TEST_F(FIRBuilderTest, getVarLenSeqTy) { auto builder = getBuilder(); auto ty = builder.getVarLenSeqTy(builder.getI64Type()); - EXPECT_TRUE(ty.isa()); - fir::SequenceType seqTy = ty.dyn_cast(); + EXPECT_TRUE(mlir::isa(ty)); + fir::SequenceType seqTy = mlir::dyn_cast(ty); EXPECT_EQ(1u, seqTy.getDimension()); EXPECT_TRUE(fir::unwrapSequenceType(ty).isInteger(64)); } @@ -216,9 +216,9 @@ TEST_F(FIRBuilderTest, createGlobal2) { EXPECT_FALSE(global.getConstant().has_value()); EXPECT_EQ(i32Type, global.getType()); EXPECT_TRUE(global.getInitVal().has_value()); - EXPECT_TRUE(global.getInitVal().value().isa()); - EXPECT_EQ( - 16, global.getInitVal().value().cast().getValue()); + EXPECT_TRUE(mlir::isa(global.getInitVal().value())); + EXPECT_EQ(16, + mlir::cast(global.getInitVal().value()).getValue()); EXPECT_TRUE(global.getLinkName().has_value()); EXPECT_EQ( builder.createLinkOnceLinkage().getValue(), global.getLinkName().value()); @@ -271,12 +271,12 @@ TEST_F(FIRBuilderTest, locationToFilename) { auto stringLitOps = global.getRegion().front().getOps(); EXPECT_TRUE(llvm::hasSingleElement(stringLitOps)); for (auto stringLit : stringLitOps) { - EXPECT_EQ(10, stringLit.getSize().cast().getValue()); - EXPECT_TRUE(stringLit.getValue().isa()); + EXPECT_EQ( + 10, mlir::cast(stringLit.getSize()).getValue()); + EXPECT_TRUE(mlir::isa(stringLit.getValue())); EXPECT_EQ(0, strcmp("file1.f90\0", - stringLit.getValue() - .dyn_cast() + mlir::dyn_cast(stringLit.getValue()) .getValue() .str() .c_str())); @@ -288,9 +288,9 @@ TEST_F(FIRBuilderTest, createStringLitOp) { llvm::StringRef data("mystringlitdata"); auto loc = builder.getUnknownLoc(); auto op = builder.createStringLitOp(loc, data); - EXPECT_EQ(15, op.getSize().cast().getValue()); - EXPECT_TRUE(op.getValue().isa()); - EXPECT_EQ(data, op.getValue().dyn_cast().getValue()); + EXPECT_EQ(15, mlir::cast(op.getSize()).getValue()); + EXPECT_TRUE(mlir::isa(op.getValue())); + EXPECT_EQ(data, mlir::dyn_cast(op.getValue()).getValue()); } TEST_F(FIRBuilderTest, createStringLiteral) { @@ -318,9 +318,11 @@ TEST_F(FIRBuilderTest, createStringLiteral) { auto stringLitOps = global.getRegion().front().getOps(); EXPECT_TRUE(llvm::hasSingleElement(stringLitOps)); for (auto stringLit : stringLitOps) { - EXPECT_EQ(16, stringLit.getSize().cast().getValue()); - EXPECT_TRUE(stringLit.getValue().isa()); - EXPECT_EQ(strValue, stringLit.getValue().dyn_cast().getValue()); + EXPECT_EQ( + 16, mlir::cast(stringLit.getSize()).getValue()); + EXPECT_TRUE(mlir::isa(stringLit.getValue())); + EXPECT_EQ( + strValue, mlir::dyn_cast(stringLit.getValue()).getValue()); } } @@ -344,7 +346,7 @@ TEST_F(FIRBuilderTest, allocateLocal) { static void checkShapeOp(mlir::Value shape, mlir::Value c10, mlir::Value c100) { EXPECT_TRUE(mlir::isa(shape.getDefiningOp())); fir::ShapeOp op = dyn_cast(shape.getDefiningOp()); - auto shapeTy = op.getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(op.getType()); EXPECT_EQ(2u, shapeTy.getRank()); EXPECT_EQ(2u, op.getExtents().size()); EXPECT_EQ(c10, op.getExtents()[0]); @@ -372,7 +374,7 @@ TEST_F(FIRBuilderTest, genShapeWithExtentsAndShapeShift) { auto shape = builder.genShape(loc, shifts, extents); EXPECT_TRUE(mlir::isa(shape.getDefiningOp())); fir::ShapeShiftOp op = dyn_cast(shape.getDefiningOp()); - auto shapeTy = op.getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(op.getType()); EXPECT_EQ(2u, shapeTy.getRank()); EXPECT_EQ(2u, op.getExtents().size()); EXPECT_EQ(2u, op.getOrigins().size()); @@ -428,7 +430,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst = mlir::dyn_cast_or_null(zeroInt.getDefiningOp()); EXPECT_TRUE(cst); - auto intAttr = cst.getValue().dyn_cast(); + auto intAttr = mlir::dyn_cast(cst.getValue()); EXPECT_TRUE(intAttr && intAttr.getInt() == 0); mlir::Type f32Ty = mlir::FloatType::getF32(builder.getContext()); @@ -437,7 +439,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst2 = mlir::dyn_cast_or_null( zeroFloat.getDefiningOp()); EXPECT_TRUE(cst2); - auto floatAttr = cst2.getValue().dyn_cast(); + auto floatAttr = mlir::dyn_cast(cst2.getValue()); EXPECT_TRUE(floatAttr && floatAttr.getValueAsDouble() == 0.); mlir::Type boolTy = mlir::IntegerType::get(builder.getContext(), 1); @@ -446,7 +448,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst3 = mlir::dyn_cast_or_null( flaseBool.getDefiningOp()); EXPECT_TRUE(cst3); - auto intAttr2 = cst.getValue().dyn_cast(); + auto intAttr2 = mlir::dyn_cast(cst.getValue()); EXPECT_TRUE(intAttr2 && intAttr2.getInt() == 0); } @@ -482,7 +484,7 @@ TEST_F(FIRBuilderTest, getBaseTypeOf) { llvm::SmallVector arrays; auto extent = builder.create(loc, builder.getIndexType()); llvm::SmallVector extents( - arrayType.dyn_cast().getDimension(), + mlir::dyn_cast(arrayType).getDimension(), extent.getResult()); arrays.emplace_back(fir::ArrayBoxValue(ptrValArray, extents)); arrays.emplace_back(fir::BoxValue(boxValArray)); diff --git a/flang/unittests/Optimizer/RTBuilder.cpp b/flang/unittests/Optimizer/RTBuilder.cpp index 7fff7f71fc3b..d6cf96c4351c 100644 --- a/flang/unittests/Optimizer/RTBuilder.cpp +++ b/flang/unittests/Optimizer/RTBuilder.cpp @@ -27,7 +27,7 @@ TEST(RTBuilderTest, ComplexRuntimeInterface) { mlir::Type c99_cacosf_signature{ fir::runtime::RuntimeTableKey::getTypeModel()( &ctx)}; - auto c99_cacosf_funcTy = c99_cacosf_signature.cast(); + auto c99_cacosf_funcTy = mlir::cast(c99_cacosf_signature); EXPECT_EQ(c99_cacosf_funcTy.getNumInputs(), 1u); EXPECT_EQ(c99_cacosf_funcTy.getNumResults(), 1u); auto cplx_ty = fir::ComplexType::get(&ctx, 4); diff --git a/llvm/include/llvm/ADT/TypeSwitch.h b/llvm/include/llvm/ADT/TypeSwitch.h index 10a2d48e918d..14ad56ad575f 100644 --- a/llvm/include/llvm/ADT/TypeSwitch.h +++ b/llvm/include/llvm/ADT/TypeSwitch.h @@ -74,7 +74,10 @@ protected: ValueT &&value, std::enable_if_t::value> * = nullptr) { + // Silence warnings about MLIR's deprecated dyn_cast member functions. + LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_PUSH return value.template dyn_cast(); + LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_POP } /// Attempt to dyn_cast the given `value` to `CastT`. This overload is diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td index da12e7c83b22..64c538367267 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td @@ -138,10 +138,10 @@ def Linalg_SoftmaxOp : Linalg_Op<"softmax", let extraClassDeclaration = [{ ShapedType getInputOperandType() { - return getInput().getType().cast(); + return cast(getInput().getType()); } ShapedType getOutputOperandType() { - return getOutput().getType().cast(); + return cast(getOutput().getType()); } int64_t getInputOperandRank() { return getInputOperandType().getRank(); diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td index ab9b78e755d9..d9569d9d294d 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td @@ -234,8 +234,8 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getIsTargetDevice", (ins), [{}], [{ if (Attribute isTargetDevice = $_op->getAttr("omp.is_target_device")) - if (isTargetDevice.isa()) - return isTargetDevice.dyn_cast().getValue(); + if (::llvm::isa(isTargetDevice)) + return ::llvm::dyn_cast(isTargetDevice).getValue(); return false; }]>, InterfaceMethod< @@ -259,7 +259,7 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getIsGPU", (ins), [{}], [{ if (Attribute isTargetCGAttr = $_op->getAttr("omp.is_gpu")) - if (auto isTargetCGVal = isTargetCGAttr.dyn_cast()) + if (auto isTargetCGVal = ::llvm::dyn_cast(isTargetCGAttr)) return isTargetCGVal.getValue(); return false; }]>, @@ -332,7 +332,7 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getRequires", (ins), [{}], [{ if (Attribute requiresAttr = $_op->getAttr("omp.requires")) - if (auto requiresVal = requiresAttr.dyn_cast()) + if (auto requiresVal = ::llvm::dyn_cast(requiresAttr)) return requiresVal.getValue(); return mlir::omp::ClauseRequires::none; }]>, diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td index 88f2e1acfeeb..e477d9a0ca3f 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td @@ -164,10 +164,10 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// source operand. They overide static shape from source memref type. ArrayRef getStaticSizes() { auto attr = getConstShapeAttr(); - if (getSourceType().isa() || attr) + if (llvm::isa(getSourceType()) || attr) return attr; - auto memrefType = getSourceType().dyn_cast(); + auto memrefType = llvm::dyn_cast(getSourceType()); assert(memrefType && "Incorrect use of getStaticSizes"); return memrefType.getShape(); } @@ -179,10 +179,10 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// source operand. They overide static strides from source memref type. ArrayRef getStaticStrides() { auto attr = getConstStridesAttr(); - if (getSourceType().isa() || attr) + if (llvm::isa(getSourceType()) || attr) return attr; - auto memrefType = getSourceType().dyn_cast(); + auto memrefType = llvm::dyn_cast(getSourceType()); assert(memrefType && "Incorrect use of getStaticStrides"); auto [strides, offset] = getStridesAndOffset(memrefType); // reuse the storage of ConstStridesAttr since strides from @@ -196,7 +196,7 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// `static_shape` and `static_strides` attributes. std::array getArrayAttrMaxRanks() { unsigned rank; - if (auto ty = getSourceType().dyn_cast()) { + if (auto ty = llvm::dyn_cast(getSourceType())) { rank = ty.getRank(); } else { rank = (unsigned)getMixedOffsets().size(); diff --git a/mlir/include/mlir/IR/Attributes.h b/mlir/include/mlir/IR/Attributes.h index cc0cee6a3118..8a077865b51b 100644 --- a/mlir/include/mlir/IR/Attributes.h +++ b/mlir/include/mlir/IR/Attributes.h @@ -50,14 +50,19 @@ public: /// Casting utility functions. These are deprecated and will be removed, /// please prefer using the `llvm` namespace variants instead. template + [[deprecated("Use mlir::isa() instead")]] bool isa() const; template + [[deprecated("Use mlir::isa_and_nonnull() instead")]] bool isa_and_nonnull() const; template + [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const; template + [[deprecated("Use mlir::dyn_cast_or_null() instead")]] U dyn_cast_or_null() const; template + [[deprecated("Use mlir::cast() instead")]] U cast() const; /// Return a unique identifier for the concrete attribute type. This is used diff --git a/mlir/include/mlir/IR/BuiltinLocationAttributes.td b/mlir/include/mlir/IR/BuiltinLocationAttributes.td index dfcc180071f7..5a72404dea15 100644 --- a/mlir/include/mlir/IR/BuiltinLocationAttributes.td +++ b/mlir/include/mlir/IR/BuiltinLocationAttributes.td @@ -228,7 +228,8 @@ def OpaqueLoc : Builtin_LocationAttr<"OpaqueLoc"> { template static T getUnderlyingLocation(Location location) { assert(isa(location)); return reinterpret_cast( - location.cast().getUnderlyingLocation()); + mlir::cast(static_cast(location)) + .getUnderlyingLocation()); } /// Returns a pointer to some data structure that opaque location stores. @@ -237,15 +238,17 @@ def OpaqueLoc : Builtin_LocationAttr<"OpaqueLoc"> { template static T getUnderlyingLocationOrNull(Location location) { return isa(location) - ? reinterpret_cast( - location.cast().getUnderlyingLocation()) - : T(nullptr); + ? reinterpret_cast(mlir::cast( + static_cast(location)) + .getUnderlyingLocation()) + : T(nullptr); } /// Checks whether provided location is opaque location and contains a /// pointer to an object of particular type. template static bool isa(Location location) { - auto opaque_loc = location.dyn_cast(); + auto opaque_loc = + mlir::dyn_cast(static_cast(location)); return opaque_loc && opaque_loc.getUnderlyingTypeID() == TypeID::get(); } }]; diff --git a/mlir/include/mlir/IR/Location.h b/mlir/include/mlir/IR/Location.h index aa8314f38cdf..423b4d19b5b9 100644 --- a/mlir/include/mlir/IR/Location.h +++ b/mlir/include/mlir/IR/Location.h @@ -78,14 +78,17 @@ public: /// Type casting utilities on the underlying location. template + [[deprecated("Use mlir::isa() instead")]] bool isa() const { return llvm::isa(*this); } template + [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const { return llvm::dyn_cast(*this); } template + [[deprecated("Use mlir::cast() instead")]] U cast() const { return llvm::cast(*this); } diff --git a/mlir/include/mlir/IR/Types.h b/mlir/include/mlir/IR/Types.h index a89e13b625bf..65824531fdc9 100644 --- a/mlir/include/mlir/IR/Types.h +++ b/mlir/include/mlir/IR/Types.h @@ -97,14 +97,19 @@ public: bool operator!() const { return impl == nullptr; } template + [[deprecated("Use mlir::isa() instead")]] bool isa() const; template + [[deprecated("Use mlir::isa_and_nonnull() instead")]] bool isa_and_nonnull() const; template + [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const; template + [[deprecated("Use mlir::dyn_cast_or_null() instead")]] U dyn_cast_or_null() const; template + [[deprecated("Use mlir::cast() instead")]] U cast() const; /// Return a unique identifier for the concrete type. This is used to support diff --git a/mlir/include/mlir/IR/Value.h b/mlir/include/mlir/IR/Value.h index cdbc6cc37436..a7344c64e673 100644 --- a/mlir/include/mlir/IR/Value.h +++ b/mlir/include/mlir/IR/Value.h @@ -98,25 +98,25 @@ public: constexpr Value(detail::ValueImpl *impl = nullptr) : impl(impl) {} template - [[deprecated("Use isa() instead")]] + [[deprecated("Use mlir::isa() instead")]] bool isa() const { return llvm::isa(*this); } template - [[deprecated("Use dyn_cast() instead")]] + [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const { return llvm::dyn_cast(*this); } template - [[deprecated("Use dyn_cast_or_null() instead")]] + [[deprecated("Use mlir::dyn_cast_or_null() instead")]] U dyn_cast_or_null() const { return llvm::dyn_cast_or_null(*this); } template - [[deprecated("Use cast() instead")]] + [[deprecated("Use mlir::cast() instead")]] U cast() const { return llvm::cast(*this); } diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index 4a15976d40c7..c2a83f90bcbe 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -857,7 +857,7 @@ struct SqrtOpConversion : public OpConversionPattern { ImplicitLocOpBuilder b(op.getLoc(), rewriter); auto type = cast(op.getType()); - auto elementType = type.getElementType().cast(); + auto elementType = cast(type.getElementType()); arith::FastMathFlags fmf = op.getFastMathFlagsAttr().getValue(); auto cst = [&](APFloat v) { diff --git a/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp b/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp index ee09c73bb3c4..f1ec2be72a33 100644 --- a/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp +++ b/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp @@ -172,7 +172,7 @@ Attribute RingAttr::parse(AsmParser &parser, Type type) { if (failed(parser.parseEqual())) return {}; - IntegerType iType = ty.dyn_cast(); + IntegerType iType = mlir::dyn_cast(ty); if (!iType) { parser.emitError(parser.getCurrentLocation(), "coefficientType must specify an integer type"); diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp index 69999f0918c1..802a64b0805e 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp @@ -140,7 +140,7 @@ struct LinearizeVectorExtractStridedSlice final ConversionPatternRewriter &rewriter) const override { Type dstType = getTypeConverter()->convertType(extractOp.getType()); assert(!(extractOp.getVector().getType().isScalable() || - dstType.cast().isScalable()) && + cast(dstType).isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(extractOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -172,7 +172,7 @@ struct LinearizeVectorExtractStridedSlice final // Get total number of extracted slices. int64_t nExtractedSlices = 1; for (Attribute size : sizes) { - nExtractedSlices *= size.cast().getInt(); + nExtractedSlices *= cast(size).getInt(); } // Compute the strides of the source vector considering first k dimensions. llvm::SmallVector sourceStrides(kD, extractGranularitySize); @@ -189,7 +189,7 @@ struct LinearizeVectorExtractStridedSlice final // Compute extractedStrides. for (int i = kD - 2; i >= 0; --i) { extractedStrides[i] = - extractedStrides[i + 1] * sizes[i + 1].cast().getInt(); + extractedStrides[i + 1] * cast(sizes[i + 1]).getInt(); } // Iterate over all extracted slices from 0 to nExtractedSlices - 1 // and compute the multi-dimensional index and the corresponding linearized @@ -207,7 +207,7 @@ struct LinearizeVectorExtractStridedSlice final int64_t linearizedIndex = 0; for (int64_t j = 0; j < kD; ++j) { linearizedIndex += - (offsets[j].cast().getInt() + multiDimIndex[j]) * + (cast(offsets[j]).getInt() + multiDimIndex[j]) * sourceStrides[j]; } // Fill the indices array form linearizedIndex to linearizedIndex + @@ -254,7 +254,7 @@ struct LinearizeVectorShuffle final Type dstType = getTypeConverter()->convertType(shuffleOp.getType()); assert(!(shuffleOp.getV1VectorType().isScalable() || shuffleOp.getV2VectorType().isScalable() || - dstType.cast().isScalable()) && + cast(dstType).isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(shuffleOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -324,7 +324,7 @@ struct LinearizeVectorExtract final ConversionPatternRewriter &rewriter) const override { Type dstTy = getTypeConverter()->convertType(extractOp.getType()); assert(!(extractOp.getVector().getType().isScalable() || - dstTy.cast().isScalable()) && + cast(dstTy).isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(extractOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -405,9 +405,7 @@ void mlir::vector::populateVectorLinearizeShuffleLikeOpsPatterns( [=](vector::ShuffleOp shuffleOp) -> bool { return isLessThanTargetBitWidth(shuffleOp, targetBitWidth) ? (typeConverter.isLegal(shuffleOp) && - shuffleOp.getResult() - .getType() - .cast() + cast(shuffleOp.getResult().getType()) .getRank() == 1) : true; }); -- GitLab From 1728a56d0e66c9e64a2e62fa6c5508580ccd28a0 Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Fri, 26 Apr 2024 18:33:58 +0400 Subject: [PATCH 065/301] [clang] Add test for CWG2149 "Brace elision and array length deduction" (#90079) This patch adds test for [CWG2149](https://cplusplus.github.io/CWG/issues/2149.html), following [P3106R1](https://wg21.link/p3106R1) "Clarifying rules for brace elision in aggregate initialization" and a clarification note on top of it added on April 2024. I haven't found a better way to check for equality of values inside array in 98 mode than to dump AST. I'm open to suggestions there. --- clang/test/CXX/drs/cwg2149.cpp | 77 ++++++++++++++++++++++++++++++++++ clang/www/cxx_dr_status.html | 2 +- 2 files changed, 78 insertions(+), 1 deletion(-) create mode 100644 clang/test/CXX/drs/cwg2149.cpp diff --git a/clang/test/CXX/drs/cwg2149.cpp b/clang/test/CXX/drs/cwg2149.cpp new file mode 100644 index 000000000000..d0f8cb2dfc0a --- /dev/null +++ b/clang/test/CXX/drs/cwg2149.cpp @@ -0,0 +1,77 @@ +// RUN: %clang_cc1 -std=c++98 -triple x86_64-unknown-unknown %s -verify=expected,cxx98 -fexceptions -fcxx-exceptions -pedantic-errors -ast-dump | FileCheck %s --check-prefixes CXX98 +// RUN: %clang_cc1 -std=c++11 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++14 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++17 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++20 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++23 -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors +// RUN: %clang_cc1 -std=c++2c -triple x86_64-unknown-unknown %s -verify=expected,since-cxx11 -fexceptions -fcxx-exceptions -pedantic-errors + +#if __cplusplus == 199711L +#define static_assert(...) __extension__ _Static_assert(__VA_ARGS__) +// cxx98-error@-1 {{variadic macros are a C99 feature}} +#endif + +namespace cwg2149 { // cwg2149: 3.1 drafting 2024-04 +#if __cplusplus <= 201103L +struct X { int i, j, k; }; +#else +struct X { int i, j, k = 42; }; +#endif + +template +void f1(const X(&)[N]); // #cwg2149-f1 + +template +void f2(const X(&)[N][2]); // #cwg2149-f2 + +void f() { + X a[] = { 1, 2, 3, 4, 5, 6 }; + static_assert(sizeof(a) / sizeof(X) == 2, ""); + X b[2] = { { 1, 2, 3 }, { 4, 5, 6 } }; + X c[][2] = { 1, 2, 3, 4, 5, 6 }; + static_assert(sizeof(c) / sizeof(X[2]) == 1, ""); + + #if __cplusplus >= 201103L + constexpr X ca[] = { 1, 2, 3, 4, 5, 6 }; + constexpr X cb[2] = { { 1, 2, 3 }, { 4, 5, 6 } }; + static_assert(ca[0].i == cb[0].i, ""); + static_assert(ca[0].j == cb[0].j, ""); + static_assert(ca[0].k == cb[0].k, ""); + static_assert(ca[1].i == cb[1].i, ""); + static_assert(ca[1].j == cb[1].j, ""); + static_assert(ca[1].k == cb[1].k, ""); + + f1({ 1, 2, 3, 4, 5, 6 }); + // since-cxx11-error@-1 {{no matching function for call to 'f1'}} + // since-cxx11-note@#cwg2149-f1 {{candidate function [with N = 6] not viable: no known conversion from 'int' to 'const X' for 1st argument}} + f2({ 1, 2, 3, 4, 5, 6 }); + // since-cxx11-error@-1 {{no matching function for call to 'f2'}} + // since-cxx11-note@#cwg2149-f2 {{candidate function [with N = 6] not viable: no known conversion from 'int' to 'const X[2]' for 1st argument}} + #endif +} +} // namespace cwg2149 + +// Constant evaluation is not powerful enough in 98 mode to check for equality +// via static_assert, even with constant folding enabled. + +// CXX98: VarDecl {{.+}} a 'X[2]' +// CXX98-NEXT: `-InitListExpr {{.+}} 'X[2]' +// CXX98-NEXT: |-InitListExpr {{.+}} 'X':'cwg2149::X' +// CXX98-NEXT: | |-IntegerLiteral {{.+}} 'int' 1 +// CXX98-NEXT: | |-IntegerLiteral {{.+}} 'int' 2 +// CXX98-NEXT: | `-IntegerLiteral {{.+}} 'int' 3 +// CXX98-NEXT: `-InitListExpr {{.+}} 'X':'cwg2149::X' +// CXX98-NEXT: |-IntegerLiteral {{.+}} 'int' 4 +// CXX98-NEXT: |-IntegerLiteral {{.+}} 'int' 5 +// CXX98-NEXT: `-IntegerLiteral {{.+}} 'int' 6 + +// CXX98: VarDecl {{.+}} b 'X[2]' +// CXX98-NEXT: `-InitListExpr {{.+}} 'X[2]' +// CXX98-NEXT: |-InitListExpr {{.+}} 'X':'cwg2149::X' +// CXX98-NEXT: | |-IntegerLiteral {{.+}} 'int' 1 +// CXX98-NEXT: | |-IntegerLiteral {{.+}} 'int' 2 +// CXX98-NEXT: | `-IntegerLiteral {{.+}} 'int' 3 +// CXX98-NEXT: `-InitListExpr {{.+}} 'X':'cwg2149::X' +// CXX98-NEXT: |-IntegerLiteral {{.+}} 'int' 4 +// CXX98-NEXT: |-IntegerLiteral {{.+}} 'int' 5 +// CXX98-NEXT: `-IntegerLiteral {{.+}} 'int' 6 diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 83b71e7c122d..ea8872c91be6 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -12702,7 +12702,7 @@ and POD class 2149 drafting Brace elision and array length deduction - Not resolved + Not Resolved* 2150 -- GitLab From e74be35c1abedf87cfaa141284cb730911211ee1 Mon Sep 17 00:00:00 2001 From: Xiaoyang Liu Date: Fri, 26 Apr 2024 11:00:47 -0400 Subject: [PATCH 066/301] [libc++][ranges] LWG3984: ranges::to's recursion branch may be ill-formed (#87964) This pull request implements LWG3984: ranges::to's recursion branch may be ill-formed. In the current implementation, ranges::to's recursion branch pipes the range into a `views::transform(/* lambda */)`, which is a __range_adaptor_closure object. In libc++, the pipe operator of __range_adaptor_closure requires a viewable_range, so the following code won't compile, as the type of lvalue `r` doesn't model viewable_range: #include #include #include int main() { std::vector> v; auto r = std::views::all(std::move(v)); auto l = std::ranges::to>>(r); } Co-authored-by: A. Jiang --- libcxx/docs/Status/Cxx2cIssues.csv | 2 +- libcxx/include/__ranges/to.h | 3 ++- .../std/ranges/range.utility/range.utility.conv/to.pass.cpp | 5 +++++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/libcxx/docs/Status/Cxx2cIssues.csv b/libcxx/docs/Status/Cxx2cIssues.csv index 666be319757c..eb99414c48be 100644 --- a/libcxx/docs/Status/Cxx2cIssues.csv +++ b/libcxx/docs/Status/Cxx2cIssues.csv @@ -44,7 +44,7 @@ "`3919 `__","``enumerate_view`` may invoke UB for sized common non-forward underlying ranges","Tokyo March 2024","","","|ranges|" "`3950 `__","``std::basic_string_view`` comparison operators are overspecified","Tokyo March 2024","|Complete|","18.0","" "`3975 `__","Specializations of ``basic_format_context`` should not be permitted","Tokyo March 2024","|Nothing To Do|","","|format|" -"`3984 `__","``ranges::to``'s recursion branch may be ill-formed","Tokyo March 2024","","","|ranges|" +"`3984 `__","``ranges::to``'s recursion branch may be ill-formed","Tokyo March 2024","|Complete|","19.0","|ranges|" "`4011 `__","``""Effects: Equivalent to return""`` in ``[span.elem]``","Tokyo March 2024","|Nothing To Do|","","" "`4012 `__","``common_view::begin/end`` are missing the ``simple-view`` check","Tokyo March 2024","","","|ranges|" "`4013 `__","``lazy_split_view::outer-iterator::value_type`` should not provide default constructor","Tokyo March 2024","","","|ranges|" diff --git a/libcxx/include/__ranges/to.h b/libcxx/include/__ranges/to.h index 8a815bce5811..e0abe6290b8f 100644 --- a/libcxx/include/__ranges/to.h +++ b/libcxx/include/__ranges/to.h @@ -24,6 +24,7 @@ #include <__ranges/concepts.h> #include <__ranges/from_range.h> #include <__ranges/range_adaptor.h> +#include <__ranges/ref_view.h> #include <__ranges/size.h> #include <__ranges/transform_view.h> #include <__type_traits/add_pointer.h> @@ -129,7 +130,7 @@ template // Try the recursive case. } else if constexpr (input_range>) { return ranges::to<_Container>( - __range | views::transform([](auto&& __elem) { + ref_view(__range) | views::transform([](auto&& __elem) { return ranges::to>(std::forward(__elem)); }), std::forward<_Args>(__args)...); diff --git a/libcxx/test/std/ranges/range.utility/range.utility.conv/to.pass.cpp b/libcxx/test/std/ranges/range.utility/range.utility.conv/to.pass.cpp index 3df88d6a2dcc..7f816bb21a19 100644 --- a/libcxx/test/std/ranges/range.utility/range.utility.conv/to.pass.cpp +++ b/libcxx/test/std/ranges/range.utility/range.utility.conv/to.pass.cpp @@ -560,6 +560,11 @@ constexpr void test_recursive() { } assert((in | std::ranges::to()) == result); + + // LWG3984: ranges::to's recursion branch may be ill-formed + auto in_owning_view = std::views::all(std::move(in)); + static_assert(!std::ranges::viewable_range); + assert(std::ranges::to(in_owning_view) == result); } constexpr bool test() { -- GitLab From 2d09ac4037415ab0044ad508aae2ff8b2559a9d8 Mon Sep 17 00:00:00 2001 From: NagyDonat Date: Fri, 26 Apr 2024 17:17:57 +0200 Subject: [PATCH 067/301] [clang-tidy][NFC] Fix broken link in documentation of cert-env33-c (#90216) It seems that the description of the SEI CERT rules was moved from `www.securecoding.cert.org` to `wiki.sei.cmu.edu` and the page IDs were not preserved during the transition. However, the old domain name redirects to the new one and permalinks derived from the name of the rule still work, so I kept using the old domain name to be consistent with other documentation files using it. --- clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst b/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst index c5321b07f7f8..9271c9ecccc0 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/cert/env33-c.rst @@ -10,4 +10,4 @@ but does not actually attempt to execute a command. This check corresponds to the CERT C Coding Standard rule `ENV33-C. Do not call system() -`_. +`_. -- GitLab From 64d514a2e1f1396d54bca0597b1e8b4e580bfd7b Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Fri, 26 Apr 2024 23:26:44 +0800 Subject: [PATCH 068/301] [mlir] Fix -Wdeprecated-declarations of cast in VCIXToLLVMIRTranslation.cpp (NFC) In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70: /llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:8:48: error: 'cast' is deprecated: Use mlir::cast() instead [-Werror,-Wdeprecated-declarations] VectorType vt = op.getResult().getType().cast(); ^ /llvm-project/mlir/include/mlir/IR/Types.h:345:9: note: 'cast' has been explicitly marked deprecated here U Type::cast() const { ^ In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70: /llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:8:48: error: 'cast' is deprecated: Use mlir::cast() instead [-Werror,-Wdeprecated-declarations] VectorType vt = op.getResult().getType().cast(); ^ /llvm-project/mlir/include/mlir/IR/Types.h:112:5: note: 'cast' has been explicitly marked deprecated here [[deprecated("Use mlir::cast() instead")]] ^ In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70: /llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:32:48: error: 'cast' is deprecated: Use mlir::cast() instead [-Werror,-Wdeprecated-declarations] VectorType vt = op.getResult().getType().cast(); ^ /llvm-project/mlir/include/mlir/IR/Types.h:345:9: note: 'cast' has been explicitly marked deprecated here U Type::cast() const { ^ In file included from /llvm-project/mlir/lib/Target/LLVMIR/Dialect/VCIX/VCIXToLLVMIRTranslation.cpp:70: /llvm-project/build-Release/tools/mlir/include/mlir/Dialect/LLVMIR/VCIXConversions.inc:32:48: error: 'cast' is deprecated: Use mlir::cast() instead [-Werror,-Wdeprecated-declarations] VectorType vt = op.getResult().getType().cast(); ^ /llvm-project/mlir/include/mlir/IR/Types.h:112:5: note: 'cast' has been explicitly marked deprecated here [[deprecated("Use mlir::cast() instead")]] ^ 4 errors generated. --- mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td b/mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td index 25c1d027768a..27d9a32dd8e0 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/VCIXOps.td @@ -78,7 +78,7 @@ def VCIX_BinaryImmOp : VCIX_Op<"v.iv">, xlen, $opcode, $_location, moduleTranslation); llvm::Value *immConst = mlir::LLVM::detail::getLLVMConstant( xlen, $imm, $_location, moduleTranslation); - VectorType vt = op.getResult().getType().cast(); + VectorType vt = mlir::cast(op.getResult().getType()); llvm::Value *vl = createVL(builder, $vl, vt, xlen, $_location, moduleTranslation); $res = createIntrinsicCall( @@ -120,7 +120,7 @@ def VCIX_BinaryOp : VCIX_Op<"v.sv">, } else { id = llvm::Intrinsic::riscv_sf_vc_v_fv_se; } - VectorType vt = op.getResult().getType().cast(); + VectorType vt = mlir::cast(op.getResult().getType()); llvm::Value *vl = createVL(builder, $vl, vt, xlen, $_location, moduleTranslation); $res = createIntrinsicCall( -- GitLab From 571831a680faa9615183f855fddf43fd1a9ba192 Mon Sep 17 00:00:00 2001 From: Diego Caballero Date: Fri, 26 Apr 2024 17:29:06 +0200 Subject: [PATCH 069/301] [mlir] Add sub-byte type emulation support for `memref.collapse_shape` (#89962) This PR adds support for `memref.collapse_shape` to sub-byte type emulation. The `memref.collapse_shape` becomes a no-opt given that we are flattening the memref as part of the emulation (i.e., we are collapsing all the dimensions). --- .../MemRef/Transforms/EmulateNarrowType.cpp | 32 +++++++++++++++++-- .../Dialect/MemRef/emulate-narrow-type.mlir | 20 ++++++++++++ 2 files changed, 49 insertions(+), 3 deletions(-) diff --git a/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp b/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp index 4449733f0daf..77c108aab480 100644 --- a/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp +++ b/mlir/lib/Dialect/MemRef/Transforms/EmulateNarrowType.cpp @@ -13,7 +13,6 @@ #include "mlir/Dialect/Arith/Transforms/Passes.h" #include "mlir/Dialect/Arith/Utils/Utils.h" #include "mlir/Dialect/MemRef/IR/MemRef.h" -#include "mlir/Dialect/MemRef/Transforms/Passes.h" #include "mlir/Dialect/MemRef/Transforms/Transforms.h" #include "mlir/Dialect/MemRef/Utils/MemRefUtils.h" #include "mlir/Dialect/Vector/IR/VectorOps.h" @@ -24,7 +23,6 @@ #include "mlir/Support/MathExtras.h" #include "mlir/Transforms/DialectConversion.h" #include "llvm/Support/FormatVariadic.h" -#include "llvm/Support/MathExtras.h" #include #include @@ -430,6 +428,33 @@ struct ConvertMemRefSubview final : OpConversionPattern { } }; +//===----------------------------------------------------------------------===// +// ConvertMemRefCollapseShape +//===----------------------------------------------------------------------===// + +/// Emulating a `memref.collapse_shape` becomes a no-op after emulation given +/// that we flatten memrefs to a single dimension as part of the emulation and +/// there is no dimension to collapse any further. +struct ConvertMemRefCollapseShape final + : OpConversionPattern { + using OpConversionPattern::OpConversionPattern; + + LogicalResult + matchAndRewrite(memref::CollapseShapeOp collapseShapeOp, OpAdaptor adaptor, + ConversionPatternRewriter &rewriter) const override { + Value srcVal = adaptor.getSrc(); + auto newTy = dyn_cast(srcVal.getType()); + if (!newTy) + return failure(); + + if (newTy.getRank() != 1) + return failure(); + + rewriter.replaceOp(collapseShapeOp, srcVal); + return success(); + } +}; + } // end anonymous namespace //===----------------------------------------------------------------------===// @@ -442,7 +467,8 @@ void memref::populateMemRefNarrowTypeEmulationPatterns( // Populate `memref.*` conversion patterns. patterns.add, - ConvertMemRefAllocation, ConvertMemRefLoad, + ConvertMemRefAllocation, + ConvertMemRefCollapseShape, ConvertMemRefLoad, ConvertMemrefStore, ConvertMemRefAssumeAlignment, ConvertMemRefSubview, ConvertMemRefReinterpretCast>( typeConverter, patterns.getContext()); diff --git a/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir b/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir index fd37b7ff0a27..435dcc944778 100644 --- a/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir +++ b/mlir/test/Dialect/MemRef/emulate-narrow-type.mlir @@ -430,3 +430,23 @@ func.func @rank_zero_memref_store(%arg0: i4) -> () { // CHECK32: %[[EXTUI:.+]] = arith.extui %[[ARG0]] : i4 to i32 // CHECK32: %[[WRITE_RMW:.+]] = memref.atomic_rmw assign %[[EXTUI]], %[[ALLOC]][] : (i32, memref) -> i32 // CHECK32: return + +// ----- + +func.func @memref_collapse_shape_i4(%idx0 : index, %idx1 : index) -> i4 { + %arr = memref.alloc() : memref<32x8x128xi4> + %collapse = memref.collapse_shape %arr[[0, 1], [2]] : memref<32x8x128xi4> into memref<256x128xi4> + %1 = memref.load %collapse[%idx0, %idx1] : memref<256x128xi4> + return %1 : i4 +} + +// CHECK-LABEL: func.func @memref_collapse_shape_i4( +// CHECK: %[[ALLOC:.*]] = memref.alloc() : memref<16384xi8> +// CHECK-NOT: memref.collapse_shape +// CHECK: memref.load %[[ALLOC]][%{{.*}}] : memref<16384xi8> + +// CHECK32-LABEL: func.func @memref_collapse_shape_i4( +// CHECK32: %[[ALLOC:.*]] = memref.alloc() : memref<4096xi32> +// CHECK32-NOT: memref.collapse_shape +// CHECK32: memref.load %[[ALLOC]][%{{.*}}] : memref<4096xi32> + -- GitLab From bf67610a8ac07ec143f243f129eecd456aa63383 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 26 Apr 2024 08:30:27 -0700 Subject: [PATCH 070/301] [MC] Rename temporary symbols of empty name to ".L0 " (#89693) Temporary symbols generated for .eh_frame and .debug_line have an empty name, which appear in .symtab in the presence of RISC-V style linker relaxation and will not be discarded by ld/objcopy --discard-locals (-X). In contrast, GNU assembler's riscv port assigns a fake name ".L0 " (with a trailing space) to these symbols so that will be discarded by ld/objcopy --discard-locals. This patch matches the GNU behavior. Since Clang's RISC-V targets pass -X to ld, and GNU ld defaults to -X for RISC-V targets, these ".L0 " symbols will be discarded after linking by default, as expected by users. The llvm-symbolizer special case for RISC-V `SF_FormatSpecific` symbols https://reviews.llvm.org/D98669 needs to be adjusted. Note: `"":` in assembly currently crashes. Note: bolt tests used /usr/bin/clang before llvmorg-19-init-9532-g59bfc3106874. The revert llvmorg-19-init-9531-g28b55342e1a8 actually broke bolt/test/RISCV/fake-label-no-entry.c --- lld/test/ELF/mips-eh_frame-pic.s | 4 +-- llvm/include/llvm/Object/ELFObjectFile.h | 5 ++- llvm/lib/MC/ELFObjectWriter.cpp | 6 ++++ llvm/test/CodeGen/RISCV/fixups-diff.ll | 2 +- .../LoongArch/dwarf-loongarch-relocs.ll | 18 +++++------ .../DebugInfo/RISCV/dwarf-riscv-relocs.ll | 12 +++---- .../test/DebugInfo/RISCV/relax-debug-frame.ll | 10 +++--- ...name-symbol.s => riscv-temporary-symbol.s} | 5 +-- .../JITLink/RISCV/anonymous_symbol.s | 2 +- llvm/test/MC/ELF/RISCV/gen-dwarf.s | 26 +++++++-------- llvm/test/MC/RISCV/cfi-advance.s | 32 +++++++++++++++---- llvm/test/MC/RISCV/fde-reloc.s | 2 +- llvm/test/MC/RISCV/scoped-relaxation.s | 6 ++-- 13 files changed, 78 insertions(+), 52 deletions(-) rename llvm/test/DebugInfo/Symbolize/ELF/{riscv-empty-name-symbol.s => riscv-temporary-symbol.s} (71%) diff --git a/lld/test/ELF/mips-eh_frame-pic.s b/lld/test/ELF/mips-eh_frame-pic.s index a84c36b0e5ec..c04dbdf57b08 100644 --- a/lld/test/ELF/mips-eh_frame-pic.s +++ b/lld/test/ELF/mips-eh_frame-pic.s @@ -36,8 +36,8 @@ # RELOCS: .rel{{a?}}.eh_frame { # ABS32-RELOCS-NEXT: 0x1C R_MIPS_32 .text # ABS64-RELOCS-NEXT: 0x1C R_MIPS_64/R_MIPS_NONE/R_MIPS_NONE .text -# PIC64-RELOCS-NEXT: 0x1C R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE -# PIC32-RELOCS-NEXT: 0x1C R_MIPS_PC32 +# PIC64-RELOCS-NEXT: 0x1C R_MIPS_PC32/R_MIPS_NONE/R_MIPS_NONE .L0 +# PIC32-RELOCS-NEXT: 0x1C R_MIPS_PC32 .L0 # RELOCS-NEXT: } # ABS64-EH-FRAME: Augmentation data: 0C diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h index 1d457be93741..4494d9b96189 100644 --- a/llvm/include/llvm/Object/ELFObjectFile.h +++ b/llvm/include/llvm/Object/ELFObjectFile.h @@ -801,9 +801,8 @@ Expected ELFObjectFile::getSymbolFlags(DataRefImpl Sym) const { } else if (EF.getHeader().e_machine == ELF::EM_RISCV) { if (Expected NameOrErr = getSymbolName(Sym)) { StringRef Name = *NameOrErr; - // Mark empty name symbols (used for label differences) and mapping - // symbols. - if (Name.empty() || Name.starts_with("$d") || Name.starts_with("$x")) + // Mark fake labels (used for label differences) and mapping symbols. + if (Name == ".L0 " || Name.starts_with("$d") || Name.starts_with("$x")) Result |= SymbolRef::SF_FormatSpecific; } else { // TODO: Actually report errors helpfully. diff --git a/llvm/lib/MC/ELFObjectWriter.cpp b/llvm/lib/MC/ELFObjectWriter.cpp index 005521bad6e0..b8ef2654ed6e 100644 --- a/llvm/lib/MC/ELFObjectWriter.cpp +++ b/llvm/lib/MC/ELFObjectWriter.cpp @@ -725,7 +725,13 @@ void ELFWriter::computeSymbolTable( HasLargeSectionIndex = true; } + // Temporary symbols generated for certain assembler features (.eh_frame, + // .debug_line) of an empty name may be referenced by relocations due to + // linker relaxation. Rename them to ".L0 " to match the gas fake label name + // and allow ld/objcopy --discard-locals to discard such symbols. StringRef Name = Symbol.getName(); + if (Name.empty()) + Name = ".L0 "; // Sections have their own string table if (Symbol.getType() != ELF::STT_SECTION) { diff --git a/llvm/test/CodeGen/RISCV/fixups-diff.ll b/llvm/test/CodeGen/RISCV/fixups-diff.ll index cc1c87b1fe37..84a7d18ed150 100644 --- a/llvm/test/CodeGen/RISCV/fixups-diff.ll +++ b/llvm/test/CodeGen/RISCV/fixups-diff.ll @@ -27,7 +27,7 @@ entry: ; CHECK: } ; CHECK: Section {{.*}} .rela.eh_frame { -; CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 +; CHECK-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 ; CHECK-NEXT: } !llvm.dbg.cu = !{!0} diff --git a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll index d6a1d8d6e136..d28836d56037 100644 --- a/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll +++ b/llvm/test/DebugInfo/LoongArch/dwarf-loongarch-relocs.ll @@ -18,21 +18,21 @@ ; RELOCS-BOTH: Section ({{.*}}) .rela.debug_frame { ; RELOCS-NORL-NEXT: 0x1C R_LARCH_32 .debug_frame 0x0 ; RELOCS-NORL-NEXT: 0x20 R_LARCH_64 .text 0x0 -; RELOCS-ENRL-NEXT: 0x1C R_LARCH_32 0x0 -; RELOCS-ENRL-NEXT: 0x20 R_LARCH_64 0x0 -; RELOCS-ENRL-NEXT: 0x28 R_LARCH_ADD64 0x0 -; RELOCS-ENRL-NEXT: 0x28 R_LARCH_SUB64 0x0 -; RELOCS-ENRL-NEXT: 0x3F R_LARCH_ADD6 0x0 -; RELOCS-ENRL-NEXT: 0x3F R_LARCH_SUB6 0x0 +; RELOCS-ENRL-NEXT: 0x1C R_LARCH_32 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x20 R_LARCH_64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x28 R_LARCH_ADD64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x28 R_LARCH_SUB64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x3F R_LARCH_ADD6 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x3F R_LARCH_SUB6 .L0 0x0 ; RELOCS-BOTH-NEXT: } ; RELOCS-BOTH: Section ({{.*}}) .rela.debug_line { ; RELOCS-BOTH-NEXT: 0x22 R_LARCH_32 .debug_line_str 0x0 ; RELOCS-BOTH-NEXT: 0x31 R_LARCH_32 .debug_line_str 0x2 ; RELOCS-BOTH-NEXT: 0x46 R_LARCH_32 .debug_line_str 0x1B ; RELOCS-NORL-NEXT: 0x4F R_LARCH_64 .text 0x0 -; RELOCS-ENRL-NEXT: 0x4F R_LARCH_64 0x0 -; RELOCS-ENRL-NEXT: 0x5F R_LARCH_ADD16 0x0 -; RELOCS-ENRL-NEXT: 0x5F R_LARCH_SUB16 0x0 +; RELOCS-ENRL-NEXT: 0x4F R_LARCH_64 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x5F R_LARCH_ADD16 .L0 0x0 +; RELOCS-ENRL-NEXT: 0x5F R_LARCH_SUB16 .L0 0x0 ; RELOCS-BOTH-NEXT: } ; RELOCS-BOTH-NEXT: ] diff --git a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll index e5de1713f4e0..99594b5e01e9 100644 --- a/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll +++ b/llvm/test/DebugInfo/RISCV/dwarf-riscv-relocs.ll @@ -6,14 +6,14 @@ ; Check that we actually have relocations, otherwise this is kind of pointless. ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_info { -; READOBJ-RELOCS: 0x1B R_RISCV_ADD32 0x0 -; READOBJ-RELOCS-NEXT: 0x1B R_RISCV_SUB32 0x0 +; READOBJ-RELOCS: 0x1B R_RISCV_ADD32 .L0 0x0 +; READOBJ-RELOCS-NEXT: 0x1B R_RISCV_SUB32 .L0 0x0 ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_frame { -; READOBJ-RELOCS: 0x20 R_RISCV_ADD32 0x0 -; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 0x0 +; READOBJ-RELOCS: 0x20 R_RISCV_ADD32 .L0 0x0 +; READOBJ-RELOCS-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 ; READOBJ-RELOCS: Section ({{.*}}) .rela.debug_line { -; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 0x0 -; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 0x0 +; READOBJ-RELOCS: 0x5A R_RISCV_ADD16 .L0 0x0 +; READOBJ-RELOCS-NEXT: 0x5A R_RISCV_SUB16 .L0 0x0 ; Check that we can print the source, even with relocations. ; OBJDUMP-SOURCE: Disassembly of section .text: diff --git a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll index f655a7c0a7ef..ffef0ec23406 100644 --- a/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll +++ b/llvm/test/DebugInfo/RISCV/relax-debug-frame.ll @@ -4,11 +4,11 @@ ; RUN: | FileCheck -check-prefix=RELAX-DWARFDUMP %s ; ; RELAX: Section ({{.*}}) .rela.eh_frame { -; RELAX-NEXT: 0x1C R_RISCV_32_PCREL 0x0 -; RELAX-NEXT: 0x30 R_RISCV_32_PCREL 0x0 -; RELAX-NEXT: 0x44 R_RISCV_32_PCREL 0x0 -; RELAX-NEXT: 0x48 R_RISCV_ADD32 0x0 -; RELAX-NEXT: 0x48 R_RISCV_SUB32 0x0 +; RELAX-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 +; RELAX-NEXT: 0x30 R_RISCV_32_PCREL .L0 0x0 +; RELAX-NEXT: 0x44 R_RISCV_32_PCREL .L0 0x0 +; RELAX-NEXT: 0x48 R_RISCV_ADD32 .L0 0x0 +; RELAX-NEXT: 0x48 R_RISCV_SUB32 .L0 0x0 ; RELAX-NEXT: } ; RELAX-DWARFDUMP-NOT: error: failed to compute relocation diff --git a/llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s b/llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s similarity index 71% rename from llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s rename to llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s index 1e0fa8a30618..0b54f104ab95 100644 --- a/llvm/test/DebugInfo/Symbolize/ELF/riscv-empty-name-symbol.s +++ b/llvm/test/DebugInfo/Symbolize/ELF/riscv-temporary-symbol.s @@ -1,10 +1,11 @@ # REQUIRES: riscv-registered-target -## Ignore empty name symbols. +## Ignore .L0 symbols that are generated by LLVM integrated assembler and GNU +## assembler for .debug_line/.eh_frame related assembler directives. # RUN: llvm-mc -filetype=obj -triple=riscv64 %s -o %t # RUN: llvm-readelf -s %t | FileCheck %s --check-prefix=SYM -# SYM: 0000000000000004 0 NOTYPE LOCAL DEFAULT [[#]] {{$}} +# SYM: 0000000000000004 0 NOTYPE LOCAL DEFAULT [[#]] .L0 {{$}} # SYM: 0000000000000000 0 NOTYPE GLOBAL DEFAULT [[#]] foo ## Make sure we test at an address larger than or equal to an empty name symbol. diff --git a/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s b/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s index a5038022dfe0..e7114e4d643c 100644 --- a/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s +++ b/llvm/test/ExecutionEngine/JITLink/RISCV/anonymous_symbol.s @@ -7,7 +7,7 @@ # the section start and section end. So that by relocating these symbol, the section length # can be calculated. # -# CHECK: Creating defined graph symbol for ELF symbol "" +# CHECK: Creating defined graph symbol for ELF symbol ".L0 " # CHECK: Creating defined graph symbol for ELF symbol "main" .text .globl main diff --git a/llvm/test/MC/ELF/RISCV/gen-dwarf.s b/llvm/test/MC/ELF/RISCV/gen-dwarf.s index 342ed1cc0e7e..34d02f5da44f 100644 --- a/llvm/test/MC/ELF/RISCV/gen-dwarf.s +++ b/llvm/test/MC/ELF/RISCV/gen-dwarf.s @@ -40,28 +40,28 @@ # CHECK-NEXT: 0x00000020: [DW_RLE_end_of_list ] # RELOC: Section ([[#]]) .rela.eh_frame { -# RELOC-NEXT: 0x1C R_RISCV_32_PCREL 0x0 -# RELOC-NEXT: 0x20 R_RISCV_ADD32 0x0 -# RELOC-NEXT: 0x20 R_RISCV_SUB32 0x0 -# RELOC-NEXT: 0x25 R_RISCV_SET6 0x0 -# RELOC-NEXT: 0x25 R_RISCV_SUB6 0x0 -# RELOC-NEXT: 0x34 R_RISCV_32_PCREL 0x0 +# RELOC-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 +# RELOC-NEXT: 0x20 R_RISCV_ADD32 .L0 0x0 +# RELOC-NEXT: 0x20 R_RISCV_SUB32 .L0 0x0 +# RELOC-NEXT: 0x25 R_RISCV_SET6 .L0 0x0 +# RELOC-NEXT: 0x25 R_RISCV_SUB6 .L0 0x0 +# RELOC-NEXT: 0x34 R_RISCV_32_PCREL .L0 0x0 # RELOC-NEXT: } # RELOC: Section ([[#]]) .rela.debug_rnglists { # RELOC-NEXT: 0xD R_RISCV_64 .text.foo 0x0 -# RELOC-NEXT: 0x15 R_RISCV_SET_ULEB128 0x0 +# RELOC-NEXT: 0x15 R_RISCV_SET_ULEB128 .L0 0x0 # RELOC-NEXT: 0x15 R_RISCV_SUB_ULEB128 .text.foo 0x0 # RELOC-NEXT: 0x17 R_RISCV_64 .text.bar 0x0 # RELOC-NEXT: } # RELOC: Section ([[#]]) .rela.debug_line { -# RELOC: R_RISCV_ADD16 0x0 -# RELOC-NEXT: R_RISCV_SUB16 0x0 -# RELOC-NEXT: R_RISCV_ADD16 0x0 -# RELOC-NEXT: R_RISCV_SUB16 0x0 -# RELOC-NEXT: R_RISCV_ADD16 0x0 -# RELOC-NEXT: R_RISCV_SUB16 0x0 +# RELOC: R_RISCV_ADD16 .L0 0x0 +# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 +# RELOC-NEXT: R_RISCV_ADD16 .L0 0x0 +# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 +# RELOC-NEXT: R_RISCV_ADD16 .L0 0x0 +# RELOC-NEXT: R_RISCV_SUB16 .L0 0x0 # RELOC: } # RELOC: Hex dump of section '.eh_frame': diff --git a/llvm/test/MC/RISCV/cfi-advance.s b/llvm/test/MC/RISCV/cfi-advance.s index c4af390be757..b99af38f553a 100644 --- a/llvm/test/MC/RISCV/cfi-advance.s +++ b/llvm/test/MC/RISCV/cfi-advance.s @@ -1,13 +1,27 @@ # RUN: llvm-mc -filetype=obj -triple riscv32 %s -o %t.o -# RUN: llvm-readobj -r %t.o | FileCheck -check-prefix=CHECK %s +# RUN: llvm-readelf -sr %t.o | FileCheck %s # RUN: llvm-dwarfdump --debug-frame %t.o 2>&1 \ # RUN: | FileCheck -check-prefix=CHECK-DWARFDUMP %s -# CHECK: .rela.eh_frame { -# CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 -# CHECK-NEXT: 0x35 R_RISCV_SET6 0x0 -# CHECK-NEXT: 0x35 R_RISCV_SUB6 0x0 -# CHECK-NEXT: } + +# CHECK: Relocation section '.rela.text1' at offset {{.*}} contains 1 entries: +# CHECK-NEXT: Offset Info Type Sym. Value Symbol's Name + Addend +# CHECK-NEXT: 00000000 00000313 R_RISCV_CALL_PLT 00000004 .L0 + 0 +# CHECK-EMPTY: +# CHECK-NEXT: Relocation section '.rela.eh_frame' at offset {{.*}} contains 3 entries: +# CHECK: Offset Info Type Sym. Value Symbol's Name + Addend +# CHECK-NEXT: 0000001c 00000139 R_RISCV_32_PCREL 00000000 .L0 + 0 +# CHECK-NEXT: 00000035 00000b35 R_RISCV_SET6 00010178 .L0 + 0 +# CHECK-NEXT: 00000035 00000934 R_RISCV_SUB6 0001016e .L0 + 0 +# CHECK-EMPTY: +# CHECK: Symbol table '.symtab' contains 15 entries: +# CHECK-NEXT: Num: Value Size Type Bind Vis Ndx Name +# CHECK-NEXT: 0: 00000000 0 NOTYPE LOCAL DEFAULT UND +# CHECK-NEXT: 1: 00000000 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} +# CHECK: 3: 00000004 0 NOTYPE LOCAL DEFAULT 2 .L0{{$}} +# CHECK: 9: 0001016e 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} +# CHECK: 11: 00010178 0 NOTYPE LOCAL DEFAULT 2 .L0 {{$}} + # CHECK-DWARFDUMP: DW_CFA_advance_loc1: 104 # CHECK-DWARFDUMP-NEXT: DW_CFA_def_cfa_offset: +8 # CHECK-DWARFDUMP-NEXT: DW_CFA_advance_loc2: 259 @@ -23,6 +37,9 @@ test: .cfi_startproc nop +## This looks similar to fake label names ".L0 ". Even if this is ".L0 ", +## the assembler will not conflate it with fake labels. +.L0: .zero 100, 0x90 .cfi_def_cfa_offset 8 nop @@ -36,3 +53,6 @@ test: .cfi_def_cfa_offset 8 nop .cfi_endproc + +.section .text1,"ax" +call .L0 diff --git a/llvm/test/MC/RISCV/fde-reloc.s b/llvm/test/MC/RISCV/fde-reloc.s index 1db8929e0747..81ec426c8b61 100644 --- a/llvm/test/MC/RISCV/fde-reloc.s +++ b/llvm/test/MC/RISCV/fde-reloc.s @@ -12,7 +12,7 @@ func: .cfi_endproc # CHECK: Section (4) .rela.eh_frame { -# CHECK-NEXT: 0x1C R_RISCV_32_PCREL 0x0 +# CHECK-NEXT: 0x1C R_RISCV_32_PCREL .L0 0x0 # CHECK-NEXT: } # CHECK: Hex dump of section '.eh_frame': # CHECK-NEXT: 0x00000000 10000000 00000000 017a5200 017c0101 diff --git a/llvm/test/MC/RISCV/scoped-relaxation.s b/llvm/test/MC/RISCV/scoped-relaxation.s index 0b797ee5aca5..56394fd80532 100644 --- a/llvm/test/MC/RISCV/scoped-relaxation.s +++ b/llvm/test/MC/RISCV/scoped-relaxation.s @@ -9,7 +9,7 @@ .dword function - . # CHECK: 0x0 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x0 R_RISCV_SUB64 0x0 +# CHECK-NEXT: 0x0 R_RISCV_SUB64 .L0 0x0 # Relaxed reference, this will resolve to a pair of `RISCV_ADD64` and # `RISCV_SUB64` relocation. @@ -19,7 +19,7 @@ .option pop # CHECK: 0x8 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x8 R_RISCV_SUB64 0x0 +# CHECK-NEXT: 0x8 R_RISCV_SUB64 .L0 0x0 # Unrelaxed reference, this will resolve to a pair of `RISCV_ADD64` and # `RISCV_SUB64` relocation due to relaxation being sticky to the file. @@ -29,6 +29,6 @@ .option pop # CHECK: 0x10 R_RISCV_ADD64 function 0x0 -# CHECK-NEXT: 0x10 R_RISCV_SUB64 0x0 +# CHECK-NEXT: 0x10 R_RISCV_SUB64 .L0 0x0 # CHECK: } -- GitLab From 0620a637e362d1add1fe506307a25d0353e254f5 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Fri, 26 Apr 2024 16:46:21 +0100 Subject: [PATCH 071/301] [X86] Regenerate subreg-to-reg tests with update_llc_test_checks.py --- llvm/test/CodeGen/X86/subreg-to-reg-1.ll | 9 ++++++--- llvm/test/CodeGen/X86/subreg-to-reg-3.ll | 8 ++++++-- llvm/test/CodeGen/X86/subreg-to-reg-6.ll | 22 +++++++++++++++++++++- 3 files changed, 33 insertions(+), 6 deletions(-) diff --git a/llvm/test/CodeGen/X86/subreg-to-reg-1.ll b/llvm/test/CodeGen/X86/subreg-to-reg-1.ll index 8acdb6176f57..49bff9e075e5 100644 --- a/llvm/test/CodeGen/X86/subreg-to-reg-1.ll +++ b/llvm/test/CodeGen/X86/subreg-to-reg-1.ll @@ -1,14 +1,17 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s -; CHECK: {{leal .*[)], %e.*}} -; CHECK-NOT: {{leal .*[)], %e.*}} - ; Don't eliminate or coalesce away the explicit zero-extension! ; This is currently using an leal because of a 3-addressification detail, ; though this isn't necessary; The point of this test is to make sure ; a 32-bit add is used. define i64 @foo(i64 %a) nounwind { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: +; CHECK-NEXT: leal -1(%rdi), %eax +; CHECK-NEXT: incq %rax +; CHECK-NEXT: retq %b = add i64 %a, 4294967295 %c = and i64 %b, 4294967295 %d = add i64 %c, 1 diff --git a/llvm/test/CodeGen/X86/subreg-to-reg-3.ll b/llvm/test/CodeGen/X86/subreg-to-reg-3.ll index db9d0d12c3d7..2bd5ca1716af 100644 --- a/llvm/test/CodeGen/X86/subreg-to-reg-3.ll +++ b/llvm/test/CodeGen/X86/subreg-to-reg-3.ll @@ -1,10 +1,14 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 ; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s -; CHECK: imull - ; Don't eliminate or coalesce away the explicit zero-extension! define i64 @foo(i64 %a) { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: +; CHECK-NEXT: imull $7823, %edi, %eax # imm = 0x1E8F +; CHECK-NEXT: incq %rax +; CHECK-NEXT: retq %b = mul i64 %a, 7823 %c = and i64 %b, 4294967295 %d = add i64 %c, 1 diff --git a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll index 7a6f78fac368..f0dc17b55661 100644 --- a/llvm/test/CodeGen/X86/subreg-to-reg-6.ll +++ b/llvm/test/CodeGen/X86/subreg-to-reg-6.ll @@ -1,6 +1,18 @@ -; RUN: llc < %s -mtriple=x86_64-- +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc < %s -mtriple=x86_64-- | FileCheck %s define i64 @foo() nounwind { +; CHECK-LABEL: foo: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: cmpl $12, 0 +; CHECK-NEXT: je .LBB0_1 +; CHECK-NEXT: # %bb.2: # %bb65 +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: #APP +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: xorl %eax, %eax +; CHECK-NEXT: retq +; CHECK-NEXT: .LBB0_1: # %bb56 entry: %t0 = load i32, ptr null, align 8 switch i32 %t0, label %bb65 [ @@ -22,6 +34,14 @@ bb65: } define i64 @bar(i64 %t0) nounwind { +; CHECK-LABEL: bar: +; CHECK: # %bb.0: +; CHECK-NEXT: movq %rdi, %rax +; CHECK-NEXT: xorl %ecx, %ecx +; CHECK-NEXT: #APP +; CHECK-NEXT: #NO_APP +; CHECK-NEXT: negl %eax +; CHECK-NEXT: retq call void asm "", "{cx}"(i64 0) nounwind %t1 = sub i64 0, %t0 %t2 = and i64 %t1, 4294967295 -- GitLab From 72c373bfdc9860b3d75e72c219b2c81c90bc4364 Mon Sep 17 00:00:00 2001 From: Aaron Ballman Date: Fri, 26 Apr 2024 12:05:15 -0400 Subject: [PATCH 072/301] [C++17] Support __GCC_[CON|DE]STRUCTIVE_SIZE (#89446) These macros are used by STL implementations to support implementation of std::hardware_destructive_interference_size and std::hardware_constructive_interference_size Fixes #60174 --------- Co-authored-by: Louis Dionne --- .../test/pp-trace/pp-trace-pragma-general.cpp | 6 +++ .../test/pp-trace/pp-trace-pragma-ms.cpp | 8 ++- .../test/pp-trace/pp-trace-pragma-opencl.cpp | 6 +++ clang/docs/LanguageExtensions.rst | 22 +++++++++ clang/docs/ReleaseNotes.rst | 12 +++++ clang/include/clang/Basic/TargetInfo.h | 10 ++++ clang/lib/Basic/Targets/ARM.h | 4 ++ clang/lib/Basic/Targets/AVR.h | 4 ++ clang/lib/Basic/Targets/BPF.h | 4 ++ clang/lib/Basic/Targets/M68k.h | 4 ++ clang/lib/Basic/Targets/Mips.h | 4 ++ clang/lib/Basic/Targets/PPC.h | 8 +++ clang/lib/Basic/Targets/RISCV.h | 4 ++ clang/lib/Basic/Targets/Sparc.h | 4 ++ clang/lib/Basic/Targets/SystemZ.h | 4 ++ clang/lib/Frontend/InitPreprocessor.cpp | 10 ++++ clang/test/AST/ast-dump-macro-json.c | 4 +- .../relevant_lines/multifile.c | 2 +- .../update_consecutive_macro_address_space.c | 13 ++--- .../Preprocessor/hardware_interference.cpp | 17 +++++++ clang/test/Preprocessor/init-aarch64.c | 12 +++-- clang/test/Preprocessor/init.c | 49 +++++++++++-------- .../test/Preprocessor/predefined-win-macros.c | 6 ++- .../hardware_inference_size.compile.pass.cpp | 2 +- 24 files changed, 181 insertions(+), 38 deletions(-) create mode 100644 clang/test/Preprocessor/hardware_interference.cpp diff --git a/clang-tools-extra/test/pp-trace/pp-trace-pragma-general.cpp b/clang-tools-extra/test/pp-trace/pp-trace-pragma-general.cpp index f01ebd1ec67d..b16ec56e321b 100644 --- a/clang-tools-extra/test/pp-trace/pp-trace-pragma-general.cpp +++ b/clang-tools-extra/test/pp-trace/pp-trace-pragma-general.cpp @@ -21,6 +21,12 @@ void foo() { // CHECK: --- // CHECK-NEXT: - Callback: PragmaDirective +// CHECK-NEXT: Loc: ":{{.+}}:1" +// CHECK-NEXT: Introducer: PIK_HashPragma +// CHECK-NEXT: - Callback: PragmaDirective +// CHECK-NEXT: Loc: ":{{.+}}:1" +// CHECK-NEXT: Introducer: PIK_HashPragma +// CHECK-NEXT: - Callback: PragmaDirective // CHECK-NEXT: Loc: "{{.*}}{{[/\\]}}pp-trace-pragma-general.cpp:3:1" // CHECK-NEXT: Introducer: PIK_HashPragma // CHECK-NEXT: - Callback: PragmaDiagnosticPush diff --git a/clang-tools-extra/test/pp-trace/pp-trace-pragma-ms.cpp b/clang-tools-extra/test/pp-trace/pp-trace-pragma-ms.cpp index 932b0eb93c90..f5bf9ac2b955 100644 --- a/clang-tools-extra/test/pp-trace/pp-trace-pragma-ms.cpp +++ b/clang-tools-extra/test/pp-trace/pp-trace-pragma-ms.cpp @@ -18,6 +18,12 @@ // CHECK: --- // CHECK-NEXT: - Callback: PragmaDirective +// CHECK-NEXT: Loc: ":{{.+}}:1" +// CHECK-NEXT: Introducer: PIK_HashPragma +// CHECK-NEXT: - Callback: PragmaDirective +// CHECK-NEXT: Loc: ":{{.+}}:1" +// CHECK-NEXT: Introducer: PIK_HashPragma +// CHECK-NEXT: - Callback: PragmaDirective // CHECK-NEXT: Loc: "{{.*}}{{[/\\]}}pp-trace-pragma-ms.cpp:3:1" // CHECK-NEXT: Introducer: PIK_HashPragma // CHECK-NEXT: - Callback: PragmaComment @@ -67,7 +73,7 @@ // CHECK-NEXT: Introducer: PIK_HashPragma // CHECK-NEXT: - Callback: PragmaMessage // CHECK-NEXT: Loc: "{{.*}}{{[/\\]}}pp-trace-pragma-ms.cpp:13:9" -// CHECK-NEXT: Namespace: +// CHECK-NEXT: Namespace: // CHECK-NEXT: Kind: PMK_Message // CHECK-NEXT: Str: message argument // CHECK-NEXT: - Callback: PragmaDirective diff --git a/clang-tools-extra/test/pp-trace/pp-trace-pragma-opencl.cpp b/clang-tools-extra/test/pp-trace/pp-trace-pragma-opencl.cpp index 31f61027994f..ed33d37eb3d5 100644 --- a/clang-tools-extra/test/pp-trace/pp-trace-pragma-opencl.cpp +++ b/clang-tools-extra/test/pp-trace/pp-trace-pragma-opencl.cpp @@ -6,6 +6,12 @@ // CHECK: --- // CHECK-NEXT: - Callback: PragmaDirective +// CHECK-NEXT: Loc: ":{{.+}}:1" +// CHECK-NEXT: Introducer: PIK_HashPragma +// CHECK-NEXT: - Callback: PragmaDirective +// CHECK-NEXT: Loc: ":{{.+}}:1" +// CHECK-NEXT: Introducer: PIK_HashPragma +// CHECK-NEXT: - Callback: PragmaDirective // CHECK-NEXT: Loc: "{{.*}}{{[/\\]}}pp-trace-pragma-opencl.cpp:3:1" // CHECK-NEXT: Introducer: PIK_HashPragma // CHECK-NEXT: - Callback: PragmaOpenCLExtension diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 84fc4dee02fa..f18b946efd4b 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -5572,3 +5572,25 @@ but the expression has no runtime effects. Type- and value-dependent expressions are not supported yet. This facility is designed to aid with testing name lookup machinery. + +Predefined Macros +================= + +`__GCC_DESTRUCTIVE_SIZE` and `__GCC_CONSTRUCTIVE_SIZE` +------------------------------------------------------ +Specify the mimum offset between two objects to avoid false sharing and the +maximum size of contiguous memory to promote true sharing, respectively. These +macros are predefined in all C and C++ language modes, but can be redefined on +the command line with ``-D`` to specify different values as needed or can be +undefined on the command line with ``-U`` to disable support for the feature. + +**Note: the values the macros expand to are not guaranteed to be stable. They +are are affected by architectures and CPU tuning flags, can change between +releases of Clang and will not match the values defined by other compilers such +as GCC.** + +Compiling different TUs depending on these flags (including use of +``std::hardware_constructive_interference`` or +``std::hardware_destructive_interference``) with different compilers, macro +definitions, or architecture flags will lead to ODR violations and should be +avoided. \ No newline at end of file diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 92563262cc67..5d4d152b2eb5 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -95,6 +95,18 @@ C++14 Feature Support - Sized deallocation is enabled by default in C++14 onwards. The user may specify ``-fno-sized-deallocation`` to disable it if there are some regressions. +C++17 Feature Support +^^^^^^^^^^^^^^^^^^^^^ +- Clang now exposes ``__GCC_DESTRUCTIVE_SIZE`` and ``__GCC_CONSTRUCTIVE_SIZE`` + predefined macros to support standard library implementations of + ``std::hardware_destructive_interference_size`` and + ``std::hardware_constructive_interference_size``, respectively. These macros + are predefined in all C and C++ language modes. The values the macros + expand to are not stable between releases of Clang and do not need to match + the values produced by GCC, so these macros should not be used from header + files because they may not be stable across multiple TUs (the values may vary + based on compiler version as well as CPU tuning). #GH60174 + C++20 Feature Support ^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/TargetInfo.h b/clang/include/clang/Basic/TargetInfo.h index e1ef7454f016..3ced2e7397a7 100644 --- a/clang/include/clang/Basic/TargetInfo.h +++ b/clang/include/clang/Basic/TargetInfo.h @@ -40,6 +40,7 @@ #include #include #include +#include #include namespace llvm { @@ -1792,6 +1793,15 @@ public: /// Whether to support HIP image/texture API's. virtual bool hasHIPImageSupport() const { return true; } + /// The first value in the pair is the minimum offset between two objects to + /// avoid false sharing (destructive interference). The second value in the + /// pair is maximum size of contiguous memory to promote true sharing + /// (constructive interference). Neither of these values are considered part + /// of the ABI and can be changed by targets at any time. + virtual std::pair hardwareInterferenceSizes() const { + return std::make_pair(64, 64); + } + protected: /// Copy type and layout related info. void copyAuxTarget(const TargetInfo *Aux); diff --git a/clang/lib/Basic/Targets/ARM.h b/clang/lib/Basic/Targets/ARM.h index e69adbe75473..df9855a52e61 100644 --- a/clang/lib/Basic/Targets/ARM.h +++ b/clang/lib/Basic/Targets/ARM.h @@ -225,6 +225,10 @@ public: bool hasBitIntType() const override { return true; } const char *getBFloat16Mangling() const override { return "u6__bf16"; }; + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(getTriple().isArch64Bit() ? 256 : 64, 64); + } }; class LLVM_LIBRARY_VISIBILITY ARMleTargetInfo : public ARMTargetInfo { diff --git a/clang/lib/Basic/Targets/AVR.h b/clang/lib/Basic/Targets/AVR.h index 9376c46cd98c..feeb04f37eeb 100644 --- a/clang/lib/Basic/Targets/AVR.h +++ b/clang/lib/Basic/Targets/AVR.h @@ -175,6 +175,10 @@ public: std::optional handleAsmEscapedChar(char EscChar) const override; StringRef getABI() const override { return ABI; } + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } + protected: std::string CPU; StringRef ABI; diff --git a/clang/lib/Basic/Targets/BPF.h b/clang/lib/Basic/Targets/BPF.h index 489f29fc4fea..d19b37dd4df7 100644 --- a/clang/lib/Basic/Targets/BPF.h +++ b/clang/lib/Basic/Targets/BPF.h @@ -113,6 +113,10 @@ public: StringRef CPUName(Name); return isValidCPUName(CPUName); } + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; } // namespace targets } // namespace clang diff --git a/clang/lib/Basic/Targets/M68k.h b/clang/lib/Basic/Targets/M68k.h index 7ffa901127e5..b732add77e03 100644 --- a/clang/lib/Basic/Targets/M68k.h +++ b/clang/lib/Basic/Targets/M68k.h @@ -56,6 +56,10 @@ public: BuiltinVaListKind getBuiltinVaListKind() const override; bool setCPU(const std::string &Name) override; CallingConvCheckResult checkCallingConvention(CallingConv CC) const override; + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; } // namespace targets diff --git a/clang/lib/Basic/Targets/Mips.h b/clang/lib/Basic/Targets/Mips.h index 0d6e4b4d0808..730deb674aa5 100644 --- a/clang/lib/Basic/Targets/Mips.h +++ b/clang/lib/Basic/Targets/Mips.h @@ -431,6 +431,10 @@ public: bool validateTarget(DiagnosticsEngine &Diags) const override; bool hasBitIntType() const override { return true; } + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; } // namespace targets } // namespace clang diff --git a/clang/lib/Basic/Targets/PPC.h b/clang/lib/Basic/Targets/PPC.h index 60bc1dec8f95..cd0f08dfb3bc 100644 --- a/clang/lib/Basic/Targets/PPC.h +++ b/clang/lib/Basic/Targets/PPC.h @@ -423,6 +423,10 @@ public: // This is the ELF definition return TargetInfo::PowerABIBuiltinVaList; } + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; // Note: ABI differences may eventually require us to have a separate @@ -503,6 +507,10 @@ public: return CCCR_Warning; } } + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(128, 128); + } }; class LLVM_LIBRARY_VISIBILITY AIXPPC32TargetInfo : diff --git a/clang/lib/Basic/Targets/RISCV.h b/clang/lib/Basic/Targets/RISCV.h index 9fa42e75bbfd..d0e9cdc6da07 100644 --- a/clang/lib/Basic/Targets/RISCV.h +++ b/clang/lib/Basic/Targets/RISCV.h @@ -122,6 +122,10 @@ public: void fillValidTuneCPUList(SmallVectorImpl &Values) const override; bool supportsTargetAttributeTune() const override { return true; } ParsedTargetAttr parseTargetAttr(StringRef Str) const override; + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; class LLVM_LIBRARY_VISIBILITY RISCV32TargetInfo : public RISCVTargetInfo { public: diff --git a/clang/lib/Basic/Targets/Sparc.h b/clang/lib/Basic/Targets/Sparc.h index 214fef88e1dc..3357bee33e1a 100644 --- a/clang/lib/Basic/Targets/Sparc.h +++ b/clang/lib/Basic/Targets/Sparc.h @@ -140,6 +140,10 @@ public: CPU = getCPUKind(Name); return CPU != CK_GENERIC; } + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(32, 32); + } }; // SPARC v8 is the 32-bit mode selected by Triple::sparc. diff --git a/clang/lib/Basic/Targets/SystemZ.h b/clang/lib/Basic/Targets/SystemZ.h index 8e302acd51b8..73d3aa01a043 100644 --- a/clang/lib/Basic/Targets/SystemZ.h +++ b/clang/lib/Basic/Targets/SystemZ.h @@ -220,6 +220,10 @@ public: int getEHDataRegisterNumber(unsigned RegNo) const override { return RegNo < 4 ? 6 + RegNo : -1; } + + std::pair hardwareInterferenceSizes() const override { + return std::make_pair(256, 256); + } }; } // namespace targets } // namespace clang diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index 6bdd734e8a27..745d1a5aca55 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -1308,6 +1308,16 @@ static void InitializePredefinedMacros(const TargetInfo &TI, Builder.defineMacro("__GCC_ATOMIC_TEST_AND_SET_TRUEVAL", "1"); } + // GCC defines these macros in both C and C++ modes despite them being needed + // mostly for STL implementations in C++. + auto [Destructive, Constructive] = TI.hardwareInterferenceSizes(); + Builder.defineMacro("__GCC_DESTRUCTIVE_SIZE", Twine(Destructive)); + Builder.defineMacro("__GCC_CONSTRUCTIVE_SIZE", Twine(Constructive)); + // We need to use push_macro to allow users to redefine these macros from the + // command line with -D and not issue a -Wmacro-redefined warning. + Builder.append("#pragma push_macro(\"__GCC_DESTRUCTIVE_SIZE\")"); + Builder.append("#pragma push_macro(\"__GCC_CONSTRUCTIVE_SIZE\")"); + auto addLockFreeMacros = [&](const llvm::Twine &Prefix) { // Used by libc++ and libstdc++ to implement ATOMIC__LOCK_FREE. #define DEFINE_LOCK_FREE_MACRO(TYPE, Type) \ diff --git a/clang/test/AST/ast-dump-macro-json.c b/clang/test/AST/ast-dump-macro-json.c index 96f4be6fec3d..fb9b4118b4f1 100644 --- a/clang/test/AST/ast-dump-macro-json.c +++ b/clang/test/AST/ast-dump-macro-json.c @@ -132,7 +132,7 @@ void BLAP(foo, __COUNTER__)(void); // CHECK-NEXT: "spellingLoc": { // CHECK-NEXT: "offset": {{[0-9]+}}, // CHECK-NEXT: "file": "", -// CHECK-NEXT: "line": 3, +// CHECK-NEXT: "line": 5, // CHECK-NEXT: "col": 1, // CHECK-NEXT: "tokLen": 4 // CHECK-NEXT: }, @@ -169,7 +169,7 @@ void BLAP(foo, __COUNTER__)(void); // CHECK-NEXT: "spellingLoc": { // CHECK-NEXT: "offset": {{[0-9]+}}, // CHECK-NEXT: "file": "", -// CHECK-NEXT: "line": 5, +// CHECK-NEXT: "line": 7, // CHECK-NEXT: "col": 1, // CHECK-NEXT: "tokLen": 4 // CHECK-NEXT: }, diff --git a/clang/test/Analysis/html_diagnostics/relevant_lines/multifile.c b/clang/test/Analysis/html_diagnostics/relevant_lines/multifile.c index 3abffd609b5b..1998c9383d9d 100644 --- a/clang/test/Analysis/html_diagnostics/relevant_lines/multifile.c +++ b/clang/test/Analysis/html_diagnostics/relevant_lines/multifile.c @@ -11,4 +11,4 @@ int f(int coin) { // RUN: rm -rf %t.output // RUN: %clang_analyze_cc1 -analyze -analyzer-checker=core -analyzer-output html -o %t.output %s // RUN: cat %t.output/* | FileCheck %s --match-full-lines -// CHECK: var relevant_lines = {"1": {"3": 1, "4": 1, "5": 1, "6": 1}, "3": {"3": 1, "4": 1, "5": 1, "6": 1, "7": 1}}; +// CHECK: var relevant_lines = {"1": {"3": 1, "4": 1, "5": 1, "6": 1}, "4": {"3": 1, "4": 1, "5": 1, "6": 1, "7": 1}}; diff --git a/clang/test/Lexer/update_consecutive_macro_address_space.c b/clang/test/Lexer/update_consecutive_macro_address_space.c index 80ef4557591c..6f74709556c0 100644 --- a/clang/test/Lexer/update_consecutive_macro_address_space.c +++ b/clang/test/Lexer/update_consecutive_macro_address_space.c @@ -1,14 +1,15 @@ // RUN: %clang -cc1 -print-stats %s 2>&1 | FileCheck %s -// CHECK: 6 local SLocEntries allocated +// CHECK: 7 local SLocEntries allocated // -// Verify that the macro arg expansion is split to two file ids, we have 6 file -// ids rather than 5: +// Verify that the macro arg expansion is split to two file ids, we have 7 file +// ids rather than 6: // 0: invalid file id // 1: main file // 2: builtin file -// 3: macro expansion for X -// 4: macro arg expansions for 1 -// 5: macro arg expansions for == 2 +// 3: scratch space for __GCC_[CON|DE]STRUCTIVE_SIZE macros +// 4: macro expansion for X +// 5: macro arg expansions for 1 +// 6: macro arg expansions for == 2 #define X(x) (int)(x); void func() { X(1 diff --git a/clang/test/Preprocessor/hardware_interference.cpp b/clang/test/Preprocessor/hardware_interference.cpp new file mode 100644 index 000000000000..f3727aadd32a --- /dev/null +++ b/clang/test/Preprocessor/hardware_interference.cpp @@ -0,0 +1,17 @@ +// RUN: %clang_cc1 -E -dM -D__GCC_CONSTRUCTIVE_SIZE=1000 -D__GCC_DESTRUCTIVE_SIZE=1001 %s -verify -Weverything | FileCheck %s +// RUN: %clang_cc1 -D__GCC_CONSTRUCTIVE_SIZE=1000 -D__GCC_DESTRUCTIVE_SIZE=1001 %s -verify -Weverything +// RUN: %clang_cc1 -E -dM -U__GCC_CONSTRUCTIVE_SIZE -U__GCC_DESTRUCTIVE_SIZE %s -verify -Weverything | FileCheck --check-prefix DISABLED %s +// expected-no-diagnostics + +// Validate that we can set a new value on the command line without issuing any +// diagnostics and that we can disabled the macro on the command line without +// issuing any diagnostics. + +// CHECK: #define __GCC_CONSTRUCTIVE_SIZE 1000 +// CHECK: #define __GCC_DESTRUCTIVE_SIZE 1001 +// DISABLED-NOT: __GCC_CONSTRUCTIVE_SIZE +// DISABLED-NOT: __GCC_DESTRUCTIVE_SIZE + +int main() { + return 0; +} diff --git a/clang/test/Preprocessor/init-aarch64.c b/clang/test/Preprocessor/init-aarch64.c index cf96870b27ac..f0845985c9ef 100644 --- a/clang/test/Preprocessor/init-aarch64.c +++ b/clang/test/Preprocessor/init-aarch64.c @@ -119,6 +119,8 @@ // AARCH64-NEXT: #define __FP_FAST_FMA 1 // AARCH64-NEXT: #define __FP_FAST_FMAF 1 // AARCH64-NEXT: #define __GCC_ASM_FLAG_OUTPUTS__ 1 +// AARCH64-NEXT: #define __GCC_CONSTRUCTIVE_SIZE {{.+}} +// AARCH64-NEXT: #define __GCC_DESTRUCTIVE_SIZE {{.+}} // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_16 1 // AARCH64-NEXT: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 @@ -220,11 +222,11 @@ // AARCH64-NEXT: #define __LONG_MAX__ 9223372036854775807L // AARCH64-NEXT: #define __LONG_WIDTH__ 64 // AARCH64-NEXT: #define __LP64__ 1 -// AARCH64-NEXT: #define __MEMORY_SCOPE_DEVICE 1 -// AARCH64-NEXT: #define __MEMORY_SCOPE_SINGLE 4 -// AARCH64-NEXT: #define __MEMORY_SCOPE_SYSTEM 0 -// AARCH64-NEXT: #define __MEMORY_SCOPE_WRKGRP 2 -// AARCH64-NEXT: #define __MEMORY_SCOPE_WVFRNT 3 +// AARCH64-NEXT: #define __MEMORY_SCOPE_DEVICE 1 +// AARCH64-NEXT: #define __MEMORY_SCOPE_SINGLE 4 +// AARCH64-NEXT: #define __MEMORY_SCOPE_SYSTEM 0 +// AARCH64-NEXT: #define __MEMORY_SCOPE_WRKGRP 2 +// AARCH64-NEXT: #define __MEMORY_SCOPE_WVFRNT 3 // AARCH64-NEXT: #define __NO_INLINE__ 1 // AARCH64-NEXT: #define __NO_MATH_ERRNO__ 1 // AARCH64-NEXT: #define __OBJC_BOOL_IS_BOOL 0 diff --git a/clang/test/Preprocessor/init.c b/clang/test/Preprocessor/init.c index c4a55efca6f7..2641fee94023 100644 --- a/clang/test/Preprocessor/init.c +++ b/clang/test/Preprocessor/init.c @@ -1,3 +1,10 @@ +// RUN: %clang_cc1 -E -dM < /dev/null | FileCheck -match-full-lines -check-prefix INTERFERENCE %s +// +// We purposefully do not test the values produced, only that the macros are +// predefined to some value. +// INTERFERENCE:#define __GCC_CONSTRUCTIVE_SIZE {{.+}} +// INTERFERENCE:#define __GCC_DESTRUCTIVE_SIZE {{.+}} + // RUN: %clang_cc1 -E -dM -x assembler-with-cpp < /dev/null | FileCheck -match-full-lines -check-prefix ASM %s // // ASM:#define __ASSEMBLER__ 1 @@ -1697,6 +1704,8 @@ // WEBASSEMBLY-NEXT:#define __GCC_ATOMIC_SHORT_LOCK_FREE 2 // WEBASSEMBLY-NEXT:#define __GCC_ATOMIC_TEST_AND_SET_TRUEVAL 1 // WEBASSEMBLY-NEXT:#define __GCC_ATOMIC_WCHAR_T_LOCK_FREE 2 +// WEBASSEMBLY-NEXT:#define __GCC_CONSTRUCTIVE_SIZE {{.+}} +// WEBASSEMBLY-NEXT:#define __GCC_DESTRUCTIVE_SIZE {{.+}} // WEBASSEMBLY-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // WEBASSEMBLY-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // WEBASSEMBLY-NEXT:#define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 @@ -1806,11 +1815,11 @@ // WEBASSEMBLY64-NEXT:#define __LONG_MAX__ 9223372036854775807L // WEBASSEMBLY64-NEXT:#define __LONG_WIDTH__ 64 // WEBASSEMBLY64-NEXT:#define __LP64__ 1 -// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_DEVICE 1 -// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_SINGLE 4 -// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_SYSTEM 0 -// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_WRKGRP 2 -// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_WVFRNT 3 +// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_DEVICE 1 +// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_SINGLE 4 +// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_SYSTEM 0 +// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_WRKGRP 2 +// WEBASSEMBLY-NEXT:#define __MEMORY_SCOPE_WVFRNT 3 // WEBASSEMBLY-NEXT:#define __NO_INLINE__ 1 // WEBASSEMBLY-NEXT:#define __NO_MATH_ERRNO__ 1 // WEBASSEMBLY-NEXT:#define __OBJC_BOOL_IS_BOOL 0 @@ -2126,11 +2135,11 @@ // AVR:#define __LDBL_MIN__ 1.17549435e-38L // AVR:#define __LONG_LONG_MAX__ 9223372036854775807LL // AVR:#define __LONG_MAX__ 2147483647L -// AVR:#define __MEMORY_SCOPE_DEVICE 1 -// AVR:#define __MEMORY_SCOPE_SINGLE 4 -// AVR:#define __MEMORY_SCOPE_SYSTEM 0 -// AVR:#define __MEMORY_SCOPE_WRKGRP 2 -// AVR:#define __MEMORY_SCOPE_WVFRNT 3 +// AVR:#define __MEMORY_SCOPE_DEVICE 1 +// AVR:#define __MEMORY_SCOPE_SINGLE 4 +// AVR:#define __MEMORY_SCOPE_SYSTEM 0 +// AVR:#define __MEMORY_SCOPE_WRKGRP 2 +// AVR:#define __MEMORY_SCOPE_WVFRNT 3 // AVR:#define __NO_INLINE__ 1 // AVR:#define __ORDER_BIG_ENDIAN__ 4321 // AVR:#define __ORDER_LITTLE_ENDIAN__ 1234 @@ -2422,11 +2431,11 @@ // RISCV32: #define __LITTLE_ENDIAN__ 1 // RISCV32: #define __LONG_LONG_MAX__ 9223372036854775807LL // RISCV32: #define __LONG_MAX__ 2147483647L -// RISCV32: #define __MEMORY_SCOPE_DEVICE 1 -// RISCV32: #define __MEMORY_SCOPE_SINGLE 4 -// RISCV32: #define __MEMORY_SCOPE_SYSTEM 0 -// RISCV32: #define __MEMORY_SCOPE_WRKGRP 2 -// RISCV32: #define __MEMORY_SCOPE_WVFRNT 3 +// RISCV32: #define __MEMORY_SCOPE_DEVICE 1 +// RISCV32: #define __MEMORY_SCOPE_SINGLE 4 +// RISCV32: #define __MEMORY_SCOPE_SYSTEM 0 +// RISCV32: #define __MEMORY_SCOPE_WRKGRP 2 +// RISCV32: #define __MEMORY_SCOPE_WVFRNT 3 // RISCV32: #define __NO_INLINE__ 1 // RISCV32: #define __POINTER_WIDTH__ 32 // RISCV32: #define __PRAGMA_REDEFINE_EXTNAME 1 @@ -2634,11 +2643,11 @@ // RISCV64: #define __LONG_LONG_MAX__ 9223372036854775807LL // RISCV64: #define __LONG_MAX__ 9223372036854775807L // RISCV64: #define __LP64__ 1 -// RISCV64: #define __MEMORY_SCOPE_DEVICE 1 -// RISCV64: #define __MEMORY_SCOPE_SINGLE 4 -// RISCV64: #define __MEMORY_SCOPE_SYSTEM 0 -// RISCV64: #define __MEMORY_SCOPE_WRKGRP 2 -// RISCV64: #define __MEMORY_SCOPE_WVFRNT 3 +// RISCV64: #define __MEMORY_SCOPE_DEVICE 1 +// RISCV64: #define __MEMORY_SCOPE_SINGLE 4 +// RISCV64: #define __MEMORY_SCOPE_SYSTEM 0 +// RISCV64: #define __MEMORY_SCOPE_WRKGRP 2 +// RISCV64: #define __MEMORY_SCOPE_WVFRNT 3 // RISCV64: #define __NO_INLINE__ 1 // RISCV64: #define __POINTER_WIDTH__ 64 // RISCV64: #define __PRAGMA_REDEFINE_EXTNAME 1 diff --git a/clang/test/Preprocessor/predefined-win-macros.c b/clang/test/Preprocessor/predefined-win-macros.c index b830dc39d477..14e2f584bd09 100644 --- a/clang/test/Preprocessor/predefined-win-macros.c +++ b/clang/test/Preprocessor/predefined-win-macros.c @@ -3,7 +3,7 @@ // RUN: %clang_cc1 %s -x c++ -E -dM -triple x86_64-pc-win32 -fms-extensions -fms-compatibility \ // RUN: -fms-compatibility-version=19.00 -std=c++14 -o - | FileCheck -match-full-lines %s --check-prefix=CHECK-MS64 // RUN: %clang_cc1 %s -x c++ -E -dM -triple x86_64-pc-win32 -fms-extensions -fms-compatibility \ -// RUN: -fms-compatibility-version=19.00 -std=c++14 -o - | grep GCC | count 5 +// RUN: -fms-compatibility-version=19.00 -std=c++14 -o - | grep GCC | count 7 // CHECK-MS64: #define _INTEGRAL_MAX_BITS 64 // CHECK-MS64: #define _ISO_VOLATILE 1 // CHECK-MS64: #define _MSC_EXTENSIONS 1 @@ -26,7 +26,7 @@ // RUN: %clang_cc1 %s -x c++ -E -dM -triple i686-pc-win32 -fms-extensions -fms-compatibility \ // RUN: -fms-compatibility-version=19.00 -std=c++17 -o - | FileCheck -match-full-lines %s --check-prefix=CHECK-MS // RUN: %clang_cc1 %s -x c++ -E -dM -triple i686-pc-win32 -fms-extensions -fms-compatibility \ -// RUN: -fms-compatibility-version=19.00 -std=c++17 -o - | grep GCC | count 5 +// RUN: -fms-compatibility-version=19.00 -std=c++17 -o - | grep GCC | count 7 // CHECK-MS: #define _INTEGRAL_MAX_BITS 64 // CHECK-MS: #define _ISO_VOLATILE 1 // CHECK-MS: #define _MSC_EXTENSIONS 1 @@ -39,6 +39,8 @@ // CHECK-MS-NOT: GNU // CHECK-MS-NOT: GXX // CHECK-MS: #define __GCC_ASM_FLAG_OUTPUTS__ 1 +// CHECK-MS: #define __GCC_CONSTRUCTIVE_SIZE {{.+}} +// CHECK-MS: #define __GCC_DESTRUCTIVE_SIZE {{.+}} // CHECK-MS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK-MS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK-MS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 diff --git a/libcxx/test/std/language.support/support.dynamic/hardware_inference_size.compile.pass.cpp b/libcxx/test/std/language.support/support.dynamic/hardware_inference_size.compile.pass.cpp index ae277d53e46f..2656f0595bf5 100644 --- a/libcxx/test/std/language.support/support.dynamic/hardware_inference_size.compile.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/hardware_inference_size.compile.pass.cpp @@ -7,7 +7,7 @@ //===----------------------------------------------------------------------===// // UNSUPPORTED: c++03, c++11, c++14 -// XFAIL: (clang || apple-clang) && stdlib=libc++ +// UNSUPPORTED: (clang || apple-clang) && stdlib=libc++ #include -- GitLab From 37a92f9f60fc2f77264b06c5602a61aaa5196edb Mon Sep 17 00:00:00 2001 From: Dinar Temirbulatov Date: Fri, 26 Apr 2024 17:07:25 +0100 Subject: [PATCH 073/301] [AArch64][SVE2] SVE2 NBSL instruction lowering. (#89732) Allow to fold BSL/EOR instuctions to NBSL instruction for scalable vectors. --- llvm/lib/Target/AArch64/AArch64InstrInfo.td | 2 + .../lib/Target/AArch64/AArch64SVEInstrInfo.td | 2 +- llvm/test/CodeGen/AArch64/sve2-bsl.ll | 52 +++++++++++++++++++ 3 files changed, 55 insertions(+), 1 deletion(-) diff --git a/llvm/lib/Target/AArch64/AArch64InstrInfo.td b/llvm/lib/Target/AArch64/AArch64InstrInfo.td index 17d96370c04a..2159116d1ab7 100644 --- a/llvm/lib/Target/AArch64/AArch64InstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64InstrInfo.td @@ -746,6 +746,8 @@ def AArch64vsli : SDNode<"AArch64ISD::VSLI", SDT_AArch64vshiftinsert>; def AArch64vsri : SDNode<"AArch64ISD::VSRI", SDT_AArch64vshiftinsert>; def AArch64bsp: SDNode<"AArch64ISD::BSP", SDT_AArch64trivec>; +def AArch64nbsl: PatFrag<(ops node:$Op1, node:$Op2, node:$Op3), + (vnot (AArch64bsp node:$Op1, node:$Op2, node:$Op3))>; def AArch64cmeq: SDNode<"AArch64ISD::CMEQ", SDT_AArch64binvec>; def AArch64cmge: SDNode<"AArch64ISD::CMGE", SDT_AArch64binvec>; diff --git a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td index 3331ba7f99a1..b90ac0ff1fe0 100644 --- a/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td +++ b/llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td @@ -3760,7 +3760,7 @@ let Predicates = [HasSVE2orSME] in { defm BSL_ZZZZ : sve2_int_bitwise_ternary_op<0b001, "bsl", int_aarch64_sve_bsl, AArch64bsp>; defm BSL1N_ZZZZ : sve2_int_bitwise_ternary_op<0b011, "bsl1n", int_aarch64_sve_bsl1n>; defm BSL2N_ZZZZ : sve2_int_bitwise_ternary_op<0b101, "bsl2n", int_aarch64_sve_bsl2n>; - defm NBSL_ZZZZ : sve2_int_bitwise_ternary_op<0b111, "nbsl", int_aarch64_sve_nbsl>; + defm NBSL_ZZZZ : sve2_int_bitwise_ternary_op<0b111, "nbsl", int_aarch64_sve_nbsl, AArch64nbsl>; // SVE2 bitwise xor and rotate right by immediate defm XAR_ZZZI : sve2_int_rotate_right_imm<"xar", int_aarch64_sve_xar>; diff --git a/llvm/test/CodeGen/AArch64/sve2-bsl.ll b/llvm/test/CodeGen/AArch64/sve2-bsl.ll index 23b2622f5f58..ef7d4abe5c5f 100644 --- a/llvm/test/CodeGen/AArch64/sve2-bsl.ll +++ b/llvm/test/CodeGen/AArch64/sve2-bsl.ll @@ -41,3 +41,55 @@ define @no_bsl_fold( %a, %c = or %1, %2 ret %c } + +define @nbsl_i8( %a, %b) { +; CHECK-LABEL: nbsl_i8: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z2.b, #127 // =0x7f +; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d +; CHECK-NEXT: ret + %1 = and %a, splat(i8 127) + %2 = and %b, splat(i8 -128) + %3 = or %1, %2 + %4 = xor %3, splat(i8 -1) + ret %4 +} + +define @nbsl_i16( %a, %b) { +; CHECK-LABEL: nbsl_i16: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z2.h, #32767 // =0x7fff +; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d +; CHECK-NEXT: ret + %1 = and %a, splat(i16 32767) + %2 = and %b, splat(i16 -32768) + %3 = or %1, %2 + %4 = xor %3, splat(i16 -1) + ret %4 +} + +define @nbsl_i32( %a, %b) { +; CHECK-LABEL: nbsl_i32: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z2.s, #0x7fffffff +; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d +; CHECK-NEXT: ret + %1 = and %a, splat(i32 2147483647) + %2 = and %b, splat(i32 -2147483648) + %3 = or %1, %2 + %4 = xor %3, splat(i32 -1) + ret %4 +} + +define @nbsl_i64( %a, %b) { +; CHECK-LABEL: nbsl_i64: +; CHECK: // %bb.0: +; CHECK-NEXT: mov z2.d, #0x7fffffffffffffff +; CHECK-NEXT: nbsl z0.d, z0.d, z1.d, z2.d +; CHECK-NEXT: ret + %1 = and %a, splat(i64 9223372036854775807) + %2 = and %b, splat(i64 -9223372036854775808) + %3 = or %1, %2 + %4 = xor %3, splat(i64 -1) + ret %4 +} -- GitLab From d6c4ebbf78c67cd298f6ba2da6c06e2362f4d0f4 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Fri, 26 Apr 2024 18:20:45 +0200 Subject: [PATCH 074/301] [libc++][ranges] Exports operator|. (#90071) This was omitted in c1086532d4d5 and not detected by the CI since clang-tidy is not running. This fixes the exports. Fixes: https://github.com/llvm/llvm-project/issues/89898 --- libcxx/modules/std/ranges.inc | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/libcxx/modules/std/ranges.inc b/libcxx/modules/std/ranges.inc index 7d215867a431..80f31c79a1a4 100644 --- a/libcxx/modules/std/ranges.inc +++ b/libcxx/modules/std/ranges.inc @@ -141,6 +141,17 @@ export namespace std { #if _LIBCPP_STD_VER >= 23 // [range.adaptor.object], range adaptor objects using std::ranges::range_adaptor_closure; + // Note: This declaration not in the synopsis or explicitly in the wording. + // However it is needed for the range adaptors. + // [range.adaptor.object]/3 + // The template parameter D for range_adaptor_closure may be an + // incomplete type. If an expression of type cv D is used as an operand + // to the | operator, D shall be complete and model + // derived_from>. The behavior of an expression + // involving an object of type cv D as an operand to the | operator is + // undefined if overload resolution selects a program-defined operator| + // function. + using std::ranges::operator|; #endif // [range.all], all view -- GitLab From 7683d07d84fa7206e435fca5a2d518a9ee8b5b56 Mon Sep 17 00:00:00 2001 From: Xuan Zhang <144393379+xuanzh-meta@users.noreply.github.com> Date: Fri, 26 Apr 2024 12:52:43 -0400 Subject: [PATCH 075/301] [NFC] update comments from an earlier version of SuffixTree (#89800) LeafChildren is used in an earlier version of the SuffixTree implementation to keep track of each nodes' leaf nodes. In the new/current version, this variable is no longer used, but a comment is left behind. This patch updates the comment. --- llvm/lib/Support/SuffixTree.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Support/SuffixTree.cpp b/llvm/lib/Support/SuffixTree.cpp index eaa653078e09..c00c7989d1a6 100644 --- a/llvm/lib/Support/SuffixTree.cpp +++ b/llvm/lib/Support/SuffixTree.cpp @@ -242,8 +242,8 @@ void SuffixTree::RepeatedSubstringIterator::advance() { unsigned Length = Curr->getConcatLen(); // Iterate over each child, saving internal nodes for visiting, and - // leaf nodes in LeafChildren. Internal nodes represent individual - // strings, which may repeat. + // leaf nodes' SuffixIdx in RepeatedSubstringStarts. Internal nodes + // represent individual strings, which may repeat. for (auto &ChildPair : Curr->Children) { // Save all of this node's children for processing. if (auto *InternalChild = -- GitLab From 6904e0e8852a587b49a673055997e88855f219ea Mon Sep 17 00:00:00 2001 From: ChiaHungDuan Date: Fri, 26 Apr 2024 09:55:42 -0700 Subject: [PATCH 076/301] [scudo] Reflect the allowed values for M_DECAY_TIME on Android (#89114) --- compiler-rt/lib/scudo/standalone/wrappers_c.inc | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/compiler-rt/lib/scudo/standalone/wrappers_c.inc b/compiler-rt/lib/scudo/standalone/wrappers_c.inc index 21d5b7add512..59f3fb0962f8 100644 --- a/compiler-rt/lib/scudo/standalone/wrappers_c.inc +++ b/compiler-rt/lib/scudo/standalone/wrappers_c.inc @@ -252,13 +252,11 @@ INTERFACE WEAK int SCUDO_PREFIX(mallopt)(int param, int value) { // introduced by interval transition. SCUDO_ALLOCATOR.releaseToOS(scudo::ReleaseToOS::Force); - if (value == 0) { - // Will set the release values to their minimum values. - value = INT32_MIN; - } else { - // Will set the release values to their maximum values. + // The values allowed on Android are {-1, 0, 1}. "1" means the longest + // interval. + CHECK(value >= -1 && value <= 1); + if (value == 1) value = INT32_MAX; - } } SCUDO_ALLOCATOR.setOption(scudo::Option::ReleaseInterval, -- GitLab From d2caaabf5d1532d210334d7092c2ad292334f15f Mon Sep 17 00:00:00 2001 From: Farzon Lotfi <1802579+farzonl@users.noreply.github.com> Date: Fri, 26 Apr 2024 13:19:52 -0400 Subject: [PATCH 077/301] [DXIL] Fix build warning (#90226) --- llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp index 4d99bc006900..4b162a35365c 100644 --- a/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp +++ b/llvm/lib/Target/DirectX/DXILIntrinsicExpansion.cpp @@ -77,8 +77,8 @@ static bool expandIntegerDot(CallInst *Orig, Intrinsic::ID DotIntrinsic) { : Intrinsic::dx_umad; Value *A = Orig->getOperand(0); Value *B = Orig->getOperand(1); - Type *ATy = A->getType(); - Type *BTy = B->getType(); + [[maybe_unused]] Type *ATy = A->getType(); + [[maybe_unused]] Type *BTy = B->getType(); assert(ATy->isVectorTy() && BTy->isVectorTy()); IRBuilder<> Builder(Orig->getParent()); -- GitLab From 690c929b6c68b4cd0ff314a0a88d3b218d46db2d Mon Sep 17 00:00:00 2001 From: Xing Xue Date: Fri, 26 Apr 2024 13:23:33 -0400 Subject: [PATCH 078/301] [OpenMP][AIX] Use syssmt() to get the number of SMTs per physical CPU (#89985) This patch changes to use system call `syssmt()` instead of `lpar_get_info()` to get the number of SMTs (logical processors) per physical processor for AIX. `lpar_get_info()` gives the max number of SMTs that the physical processor can support while `syssmt()` returns the number that is currently configured. --- openmp/runtime/src/kmp_affinity.cpp | 10 +--------- openmp/runtime/src/kmp_affinity.h | 2 ++ 2 files changed, 3 insertions(+), 9 deletions(-) diff --git a/openmp/runtime/src/kmp_affinity.cpp b/openmp/runtime/src/kmp_affinity.cpp index 378e5aa296c4..f34e55555545 100644 --- a/openmp/runtime/src/kmp_affinity.cpp +++ b/openmp/runtime/src/kmp_affinity.cpp @@ -3038,15 +3038,7 @@ static bool __kmp_affinity_create_cpuinfo_map(int *line, KMP_INFORM(AffParseFilename, "KMP_AFFINITY", "system info for topology"); // Get the number of SMT threads per core. - int retval = - lpar_get_info(LPAR_INFO_FORMAT1, &cpuinfo, sizeof(lpar_info_format1_t)); - if (!retval) - smt_threads = cpuinfo.smt_threads; - else { - CLEANUP_THREAD_INFO; - *msg_id = kmp_i18n_str_UnknownTopology; - return false; - } + smt_threads = syssmt(GET_NUMBER_SMT_SETS, 0, 0, NULL); // Allocate a resource set containing available system resourses. rsethandle_t sys_rset = rs_alloc(RS_SYSTEM); diff --git a/openmp/runtime/src/kmp_affinity.h b/openmp/runtime/src/kmp_affinity.h index 8e9e7667eb90..3dc2c84d53f7 100644 --- a/openmp/runtime/src/kmp_affinity.h +++ b/openmp/runtime/src/kmp_affinity.h @@ -322,6 +322,8 @@ public: #include #include #define VMI_MAXRADS 64 // Maximum number of RADs allowed by AIX. +#define GET_NUMBER_SMT_SETS 0x0004 +extern "C" int syssmt(int flags, int, int, int *); #endif class KMPNativeAffinity : public KMPAffinity { class Mask : public KMPAffinity::Mask { -- GitLab From 451e853e512ba6fca51f0743ffa24d252f7fc633 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 26 Apr 2024 10:32:21 -0700 Subject: [PATCH 079/301] [RISCV] Flatten the ImpliedExts table in RISCVISAInfo.cpp (#89975) Previously we had an individiaul global array of implied extensions for each extension that needed it. This allowed each array to have a different length. Then we had a sorted table that stored pointers and size for the indivual arrays keyed by the extension name. This patch changes the sorted table to use multiple rows if multiple extensions are implied. We use equal_range instead of lower_bound to find all the rows that apply to a given extension. The CombineIntoExts array was also modified to store only the extension name that need to be combined. This extension name is looked up in the implied table to find all the extensions it depends on. --- llvm/lib/TargetParser/RISCVISAInfo.cpp | 81 +++++++++---------- llvm/test/TableGen/riscv-target-def.td | 4 +- llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 30 +------ 3 files changed, 45 insertions(+), 70 deletions(-) diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index ea0b56b9a133..ac0f958dbb26 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -847,15 +847,21 @@ Error RISCVISAInfo::checkDependency() { struct ImpliedExtsEntry { StringLiteral Name; - ArrayRef Exts; + const char *ImpliedExt; bool operator<(const ImpliedExtsEntry &Other) const { return Name < Other.Name; } - - bool operator<(StringRef Other) const { return Name < Other; } }; +static bool operator<(const ImpliedExtsEntry &LHS, StringRef RHS) { + return LHS.Name < RHS; +} + +static bool operator<(StringRef LHS, const ImpliedExtsEntry &RHS) { + return LHS < RHS.Name; +} + #define GET_IMPLIED_EXTENSIONS #include "llvm/TargetParser/RISCVTargetParserDef.inc" @@ -880,18 +886,19 @@ void RISCVISAInfo::updateImplication() { while (!WorkList.empty()) { StringRef ExtName = WorkList.pop_back_val(); - auto I = llvm::lower_bound(ImpliedExts, ExtName); - if (I != std::end(ImpliedExts) && I->Name == ExtName) { - for (const char *ImpliedExt : I->Exts) { - if (WorkList.count(ImpliedExt)) - continue; - if (Exts.count(ImpliedExt)) - continue; - auto Version = findDefaultVersion(ImpliedExt); - addExtension(ImpliedExt, Version.value()); - WorkList.insert(ImpliedExt); - } - } + auto Range = std::equal_range(std::begin(ImpliedExts), + std::end(ImpliedExts), ExtName); + std::for_each(Range.first, Range.second, + [&](const ImpliedExtsEntry &Implied) { + const char *ImpliedExt = Implied.ImpliedExt; + if (WorkList.count(ImpliedExt)) + return; + if (Exts.count(ImpliedExt)) + return; + auto Version = findDefaultVersion(ImpliedExt); + addExtension(ImpliedExt, Version.value()); + WorkList.insert(ImpliedExt); + }); } // Add Zcf if Zce and F are enabled on RV32. @@ -902,42 +909,34 @@ void RISCVISAInfo::updateImplication() { } } -struct CombinedExtsEntry { - StringLiteral CombineExt; - ArrayRef RequiredExts; -}; - -static constexpr CombinedExtsEntry CombineIntoExts[] = { - {{"zk"}, {ImpliedExtsZk}}, - {{"zkn"}, {ImpliedExtsZkn}}, - {{"zks"}, {ImpliedExtsZks}}, - {{"zvkn"}, {ImpliedExtsZvkn}}, - {{"zvknc"}, {ImpliedExtsZvknc}}, - {{"zvkng"}, {ImpliedExtsZvkng}}, - {{"zvks"}, {ImpliedExtsZvks}}, - {{"zvksc"}, {ImpliedExtsZvksc}}, - {{"zvksg"}, {ImpliedExtsZvksg}}, +static constexpr StringLiteral CombineIntoExts[] = { + {"zk"}, {"zkn"}, {"zks"}, {"zvkn"}, {"zvknc"}, + {"zvkng"}, {"zvks"}, {"zvksc"}, {"zvksg"}, }; void RISCVISAInfo::updateCombination() { - bool IsNewCombine = false; + bool MadeChange = false; do { - IsNewCombine = false; - for (CombinedExtsEntry CombineIntoExt : CombineIntoExts) { - auto CombineExt = CombineIntoExt.CombineExt; - auto RequiredExts = CombineIntoExt.RequiredExts; + MadeChange = false; + for (StringRef CombineExt : CombineIntoExts) { if (hasExtension(CombineExt)) continue; - bool IsAllRequiredFeatureExist = true; - for (const char *Ext : RequiredExts) - IsAllRequiredFeatureExist &= hasExtension(Ext); - if (IsAllRequiredFeatureExist) { + + // Look up the extension in the ImpliesExt table to find everything it + // depends on. + auto Range = std::equal_range(std::begin(ImpliedExts), + std::end(ImpliedExts), CombineExt); + bool HasAllRequiredFeatures = std::all_of( + Range.first, Range.second, [&](const ImpliedExtsEntry &Implied) { + return hasExtension(Implied.ImpliedExt); + }); + if (HasAllRequiredFeatures) { auto Version = findDefaultVersion(CombineExt); addExtension(CombineExt, Version.value()); - IsNewCombine = true; + MadeChange = true; } } - } while (IsNewCombine); + } while (MadeChange); } void RISCVISAInfo::updateFLen() { diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index b23c7e4d4019..01c72e07460e 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -113,10 +113,8 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", // CHECK: #ifdef GET_IMPLIED_EXTENSIONS // CHECK-NEXT: #undef GET_IMPLIED_EXTENSIONS -// CHECK: static const char *ImpliedExtsF[] = {"zicsr"}; - // CHECK: static constexpr ImpliedExtsEntry ImpliedExts[] = { -// CHECK-NEXT: { {"f"}, {ImpliedExtsF} }, +// CHECK-NEXT: { {"f"}, "zicsr"}, // CHECK-NEXT: }; // CHECK: #endif // GET_IMPLIED_EXTENSIONS diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 217b531dcfd3..c34c4b3f1881 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -43,16 +43,6 @@ static void printExtensionTable(raw_ostream &OS, OS << "};\n\n"; } -// Get the extension name from the Record name. This gives the canonical -// capitalization. -static StringRef getExtensionNameFromRecordName(const Record *R) { - StringRef Name = R->getName(); - if (!Name.consume_front("FeatureStdExt")) - Name.consume_front("FeatureVendor"); - - return Name; -} - static void emitRISCVExtensions(RecordKeeper &Records, raw_ostream &OS) { OS << "#ifdef GET_SUPPORTED_EXTENSIONS\n"; OS << "#undef GET_SUPPORTED_EXTENSIONS\n\n"; @@ -71,33 +61,21 @@ static void emitRISCVExtensions(RecordKeeper &Records, raw_ostream &OS) { OS << "#ifdef GET_IMPLIED_EXTENSIONS\n"; OS << "#undef GET_IMPLIED_EXTENSIONS\n\n"; + OS << "\nstatic constexpr ImpliedExtsEntry ImpliedExts[] = {\n"; for (Record *Ext : Extensions) { auto ImpliesList = Ext->getValueAsListOfDefs("Implies"); if (ImpliesList.empty()) continue; - OS << "static const char *ImpliedExts" - << getExtensionNameFromRecordName(Ext) << "[] = {"; + StringRef Name = getExtensionName(Ext); - ListSeparator LS(", "); for (auto *ImpliedExt : ImpliesList) { if (!ImpliedExt->isSubClassOf("RISCVExtension")) continue; - OS << LS << '"' << getExtensionName(ImpliedExt) << '"'; + OS << " { {\"" << Name << "\"}, \"" << getExtensionName(ImpliedExt) + << "\"},\n"; } - - OS << "};\n"; - } - - OS << "\nstatic constexpr ImpliedExtsEntry ImpliedExts[] = {\n"; - for (Record *Ext : Extensions) { - auto ImpliesList = Ext->getValueAsListOfDefs("Implies"); - if (ImpliesList.empty()) - continue; - - OS << " { {\"" << getExtensionName(Ext) << "\"}, {ImpliedExts" - << getExtensionNameFromRecordName(Ext) << "} },\n"; } OS << "};\n\n"; -- GitLab From c49b74a4e6fff813a9ca402fa6494f80f8f0e3d6 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 26 Apr 2024 18:41:22 +0100 Subject: [PATCH 080/301] [LV] Add tests showing missed propgation of versiond stride values. Strides are used through a sext/zext and the known constant value (1) isn't propagated during codegen. --- .../version-stride-with-integer-casts.ll | 444 ++++++++++++++++++ 1 file changed, 444 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll diff --git a/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll b/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll new file mode 100644 index 000000000000..693a8b287615 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll @@ -0,0 +1,444 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -passes=loop-vectorize -force-vector-width=4 -S %s | FileCheck %s + +target datalayout = "e-m:o-p270:32:32-p271:32:32-p272:64:64-i64:64-i128:128-f80:128-n8:16:32:64-S128" + +define void @test_versioned_with_sext_use(i32 %offset, ptr %dst) { +; CHECK-LABEL: define void @test_versioned_with_sext_use( +; CHECK-SAME: i32 [[OFFSET:%.*]], ptr [[DST:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[OFFSET_EXT:%.*]] = sext i32 [[OFFSET]] to i64 +; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] +; CHECK: outer.header.loopexit: +; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ] +; CHECK-NEXT: br label [[OUTER_HEADER]] +; CHECK: outer.header: +; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ] +; CHECK-NEXT: [[C:%.*]] = call i1 @cond() +; CHECK-NEXT: br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]] +; CHECK: inner.loop.preheader: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; CHECK: vector.scevcheck: +; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 +; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]] +; CHECK-NEXT: [[IND_END]] = add i64 [[IV_1]], [[TMP0]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]] +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 +; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label [[INNER_LOOP]] +; CHECK: inner.loop: +; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_2]] +; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 +; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]] +; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 +; CHECK-NEXT: br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %offset.ext = sext i32 %offset to i64 + br label %outer.header + +outer.header: + %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ] + %c = call i1 @cond() + br i1 %c, label %inner.loop, label %exit + +inner.loop: + %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ] + %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ] + %gep = getelementptr i32, ptr %dst, i64 %iv.2 + store i32 0, ptr %gep, align 8 + %iv.2.next = add i64 %iv.2, %offset.ext + %iv.3.next = add i32 %iv.3, 1 + %ec = icmp eq i32 %iv.3, 200 + br i1 %ec, label %outer.header, label %inner.loop + +exit: + ret void +} + +define void @test_versioned_with_zext_use(i32 %offset, ptr %dst) { +; CHECK-LABEL: define void @test_versioned_with_zext_use( +; CHECK-SAME: i32 [[OFFSET:%.*]], ptr [[DST:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64 +; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] +; CHECK: outer.header.loopexit: +; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ] +; CHECK-NEXT: br label [[OUTER_HEADER]] +; CHECK: outer.header: +; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ] +; CHECK-NEXT: [[C:%.*]] = call i1 @cond() +; CHECK-NEXT: br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]] +; CHECK: inner.loop.preheader: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; CHECK: vector.scevcheck: +; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 +; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]] +; CHECK-NEXT: [[IND_END]] = add i64 [[IV_1]], [[TMP0]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]] +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8 +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 +; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label [[INNER_LOOP]] +; CHECK: inner.loop: +; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_2]] +; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 +; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]] +; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 +; CHECK-NEXT: br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %offset.ext = zext i32 %offset to i64 + br label %outer.header + +outer.header: + %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ] + %c = call i1 @cond() + br i1 %c, label %inner.loop, label %exit + +inner.loop: + %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ] + %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ] + %gep = getelementptr i32, ptr %dst, i64 %iv.2 + store i32 0, ptr %gep, align 8 + %iv.2.next = add i64 %iv.2, %offset.ext + %iv.3.next = add i32 %iv.3, 1 + %ec = icmp eq i32 %iv.3, 200 + br i1 %ec, label %outer.header, label %inner.loop + +exit: + ret void +} + +define void @versioned_sext_use_in_gep(i32 %scale, ptr %dst, i64 %scale.2) { +; CHECK-LABEL: define void @versioned_sext_use_in_gep( +; CHECK-SAME: i32 [[SCALE:%.*]], ptr [[DST:%.*]], i64 [[SCALE_2:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[SCALE_EXT:%.*]] = sext i32 [[SCALE]] to i64 +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; CHECK: vector.scevcheck: +; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[SCALE]], 1 +; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[SCALE_EXT]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[SCALE_2]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP0:%.*]] = mul <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]] +; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP0]], i32 1 +; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP0]], i32 2 +; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP5]] +; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[TMP0]], i32 3 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP7]] +; CHECK-NEXT: [[TMP9:%.*]] = mul <4 x i64> [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT2]] +; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i64> [[TMP9]], i32 0 +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP10]] +; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP9]], i32 1 +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP12]] +; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i64> [[TMP9]], i32 2 +; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP14]] +; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i64> [[TMP9]], i32 3 +; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP16]] +; CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP2]], align 8 +; CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP4]], align 8 +; CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP6]], align 8 +; CHECK-NEXT: store ptr [[TMP17]], ptr [[TMP8]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], +; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 +; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 256, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[IV_MUL:%.*]] = mul i64 [[IV]], [[SCALE_EXT]] +; CHECK-NEXT: [[GEP_1:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV_MUL]] +; CHECK-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; CHECK-NEXT: [[SCALE_MUL:%.*]] = mul i64 [[SCALE_EXT]], [[SCALE_2]] +; CHECK-NEXT: [[GEP_2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[SCALE_MUL]] +; CHECK-NEXT: store ptr [[GEP_2]], ptr [[GEP_1]], align 8 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 256 +; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %scale.ext = sext i32 %scale to i64 + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %iv.mul = mul i64 %iv, %scale.ext + %gep.1 = getelementptr i8, ptr %dst, i64 %iv.mul + %iv.next = add i64 %iv, 1 + %scale.mul = mul i64 %scale.ext, %scale.2 + %gep.2 = getelementptr i8, ptr %dst, i64 %scale.mul + store ptr %gep.2, ptr %gep.1, align 8 + %ec = icmp eq i64 %iv.next, 256 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +declare i1 @cond() + +define void @test_versioned_with_different_uses(i32 %offset, ptr noalias %dst.1, ptr %dst.2) { +; CHECK-LABEL: define void @test_versioned_with_different_uses( +; CHECK-SAME: i32 [[OFFSET:%.*]], ptr noalias [[DST_1:%.*]], ptr [[DST_2:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64 +; CHECK-NEXT: br label [[OUTER_HEADER:%.*]] +; CHECK: outer.header.loopexit: +; CHECK-NEXT: [[IV_2_NEXT_LCSSA:%.*]] = phi i64 [ [[IV_2_NEXT:%.*]], [[INNER_LOOP:%.*]] ], [ [[IND_END:%.*]], [[MIDDLE_BLOCK:%.*]] ] +; CHECK-NEXT: br label [[OUTER_HEADER]] +; CHECK: outer.header: +; CHECK-NEXT: [[IV_1:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_2_NEXT_LCSSA]], [[OUTER_HEADER_LOOPEXIT:%.*]] ] +; CHECK-NEXT: [[C:%.*]] = call i1 @cond() +; CHECK-NEXT: br i1 [[C]], label [[INNER_LOOP_PREHEADER:%.*]], label [[EXIT:%.*]] +; CHECK: inner.loop.preheader: +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; CHECK: vector.scevcheck: +; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 +; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[TMP0:%.*]] = mul i64 200, [[OFFSET_EXT]] +; CHECK-NEXT: [[IND_END]] = add i64 [[IV_1]], [[TMP0]] +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP1:%.*]] = mul i64 [[INDEX]], [[OFFSET_EXT]] +; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 [[IV_1]], [[TMP1]] +; CHECK-NEXT: [[TMP2:%.*]] = mul i64 0, [[OFFSET_EXT]] +; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], [[TMP2]] +; CHECK-NEXT: [[OFFSET_IDX2:%.*]] = trunc i64 [[INDEX]] to i32 +; CHECK-NEXT: [[TMP4:%.*]] = add i32 [[OFFSET_IDX2]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = add i32 [[OFFSET_IDX2]], 1 +; CHECK-NEXT: [[TMP6:%.*]] = add i32 [[OFFSET_IDX2]], 2 +; CHECK-NEXT: [[TMP7:%.*]] = add i32 [[OFFSET_IDX2]], 3 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP4]] +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP5]] +; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP6]] +; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP7]] +; CHECK-NEXT: store i32 0, ptr [[TMP8]], align 8 +; CHECK-NEXT: store i32 0, ptr [[TMP9]], align 8 +; CHECK-NEXT: store i32 0, ptr [[TMP10]], align 8 +; CHECK-NEXT: store i32 0, ptr [[TMP11]], align 8 +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP3]] +; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i32 0 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP13]], align 8 +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]] +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 +; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 false, label [[OUTER_HEADER_LOOPEXIT]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[IV_1]], [[INNER_LOOP_PREHEADER]] ], [ [[IV_1]], [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[INNER_LOOP_PREHEADER]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label [[INNER_LOOP]] +; CHECK: inner.loop: +; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[IV_2_NEXT]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[IV_3_NEXT:%.*]], [[INNER_LOOP]] ], [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ] +; CHECK-NEXT: [[IV_MUL:%.*]] = mul i32 [[IV_3]], [[OFFSET]] +; CHECK-NEXT: [[GEP_MUL:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[IV_MUL]] +; CHECK-NEXT: store i32 0, ptr [[GEP_MUL]], align 8 +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[IV_2]] +; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 +; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], [[OFFSET_EXT]] +; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 +; CHECK-NEXT: br i1 [[EC]], label [[OUTER_HEADER_LOOPEXIT]], label [[INNER_LOOP]], !llvm.loop [[LOOP9:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %offset.ext = zext i32 %offset to i64 + br label %outer.header + +outer.header: + %iv.1 = phi i64 [ 0, %entry ], [ %iv.2.next, %inner.loop ] + %c = call i1 @cond() + br i1 %c, label %inner.loop, label %exit + +inner.loop: + %iv.2 = phi i64 [ %iv.1, %outer.header ], [ %iv.2.next, %inner.loop ] + %iv.3 = phi i32 [ 0, %outer.header ], [ %iv.3.next, %inner.loop ] + %iv.mul = mul i32 %iv.3, %offset + %gep.mul = getelementptr i8, ptr %dst.1, i32 %iv.mul + store i32 0, ptr %gep.mul, align 8 + %gep = getelementptr i32, ptr %dst.2, i64 %iv.2 + store i32 0, ptr %gep, align 8 + %iv.2.next = add i64 %iv.2, %offset.ext + %iv.3.next = add i32 %iv.3, 1 + %ec = icmp eq i32 %iv.3, 200 + br i1 %ec, label %outer.header, label %inner.loop + +exit: + ret void +} + +define void @test_versioned_with_non_ex_use(i32 %offset, ptr noalias %dst.1, ptr %dst.2) { +; CHECK-LABEL: define void @test_versioned_with_non_ex_use( +; CHECK-SAME: i32 [[OFFSET:%.*]], ptr noalias [[DST_1:%.*]], ptr [[DST_2:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[OFFSET_EXT:%.*]] = zext i32 [[OFFSET]] to i64 +; CHECK-NEXT: [[ADD:%.*]] = add i32 [[OFFSET]], 3 +; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; CHECK: vector.scevcheck: +; CHECK-NEXT: [[TMP0:%.*]] = sub i32 -3, [[OFFSET]] +; CHECK-NEXT: [[TMP1:%.*]] = icmp slt i32 [[ADD]], 0 +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i32 [[TMP0]], i32 [[ADD]] +; CHECK-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP2]], i32 200) +; CHECK-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 +; CHECK-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 +; CHECK-NEXT: [[TMP3:%.*]] = sub i32 0, [[MUL_RESULT]] +; CHECK-NEXT: [[TMP4:%.*]] = icmp slt i32 [[MUL_RESULT]], 0 +; CHECK-NEXT: [[TMP5:%.*]] = icmp sgt i32 [[TMP3]], 0 +; CHECK-NEXT: [[TMP6:%.*]] = select i1 [[TMP1]], i1 [[TMP5]], i1 [[TMP4]] +; CHECK-NEXT: [[TMP7:%.*]] = or i1 [[TMP6]], [[MUL_OVERFLOW]] +; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[OFFSET]], 1 +; CHECK-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[IDENT_CHECK]] +; CHECK-NEXT: br i1 [[TMP8]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; CHECK: vector.ph: +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[ADD]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] +; CHECK: vector.body: +; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[TMP9:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP10:%.*]] = mul <4 x i32> [[VEC_IND]], [[BROADCAST_SPLAT]] +; CHECK-NEXT: [[TMP11:%.*]] = extractelement <4 x i32> [[TMP10]], i32 0 +; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP11]] +; CHECK-NEXT: [[TMP13:%.*]] = extractelement <4 x i32> [[TMP10]], i32 1 +; CHECK-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP13]] +; CHECK-NEXT: [[TMP15:%.*]] = extractelement <4 x i32> [[TMP10]], i32 2 +; CHECK-NEXT: [[TMP16:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP15]] +; CHECK-NEXT: [[TMP17:%.*]] = extractelement <4 x i32> [[TMP10]], i32 3 +; CHECK-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[TMP17]] +; CHECK-NEXT: store i32 0, ptr [[TMP12]], align 8 +; CHECK-NEXT: store i32 0, ptr [[TMP14]], align 8 +; CHECK-NEXT: store i32 0, ptr [[TMP16]], align 8 +; CHECK-NEXT: store i32 0, ptr [[TMP18]], align 8 +; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP9]], [[OFFSET_EXT]] +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP19]] +; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i32 0 +; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP21]], align 8 +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], +; CHECK-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 +; CHECK-NEXT: br i1 [[TMP22]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] +; CHECK: middle.block: +; CHECK-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] +; CHECK: scalar.ph: +; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ 200, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; CHECK-NEXT: br label [[LOOP:%.*]] +; CHECK: loop: +; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[IV_3:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_3_NEXT:%.*]], [[LOOP]] ] +; CHECK-NEXT: [[IV_MUL:%.*]] = mul i32 [[IV_3]], [[ADD]] +; CHECK-NEXT: [[GEP_MUL:%.*]] = getelementptr i8, ptr [[DST_1]], i32 [[IV_MUL]] +; CHECK-NEXT: store i32 0, ptr [[GEP_MUL]], align 8 +; CHECK-NEXT: [[IV_2_MUL:%.*]] = mul i64 [[IV_2]], [[OFFSET_EXT]] +; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[IV_2_MUL]] +; CHECK-NEXT: store i32 0, ptr [[GEP]], align 8 +; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 1 +; CHECK-NEXT: [[IV_3_NEXT]] = add i32 [[IV_3]], 1 +; CHECK-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_3]], 200 +; CHECK-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP11:![0-9]+]] +; CHECK: exit: +; CHECK-NEXT: ret void +; +entry: + %offset.ext = zext i32 %offset to i64 + %add = add i32 %offset, 3 + br label %loop + +loop: + %iv.2 = phi i64 [ 0, %entry ], [ %iv.2.next, %loop ] + %iv.3 = phi i32 [ 0, %entry ], [ %iv.3.next, %loop ] + %iv.mul = mul i32 %iv.3, %add + %gep.mul = getelementptr i8, ptr %dst.1, i32 %iv.mul + store i32 0, ptr %gep.mul, align 8 + %iv.2.mul = mul i64 %iv.2, %offset.ext + %gep = getelementptr i32, ptr %dst.2, i64 %iv.2.mul + store i32 0, ptr %gep, align 8 + %iv.2.next = add i64 %iv.2, 1 + %iv.3.next = add i32 %iv.3, 1 + %ec = icmp eq i32 %iv.3, 200 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} +;. +; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} +; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]} +; CHECK: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} +; CHECK: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]} +; CHECK: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} +; CHECK: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]} +; CHECK: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} +; CHECK: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]]} +;. -- GitLab From 3aeb28b93fb740f531bc66a33b1b4ce520663582 Mon Sep 17 00:00:00 2001 From: Peiming Liu Date: Fri, 26 Apr 2024 10:48:15 -0700 Subject: [PATCH 081/301] [mlir][sparse] fold sparse convert into producer linalg op. (#89999) --- .../Dialect/SparseTensor/IR/SparseTensor.h | 15 ++-- .../Transforms/SparseTensorRewriting.cpp | 38 ++++++++- .../Transforms/Sparsification.cpp | 44 +++++++---- .../fuse_sparse_convert_into_producer.mlir | 78 +++++++++++++++++++ .../SparseTensor/no_fold_into_consumer.mlir | 47 ----------- 5 files changed, 151 insertions(+), 71 deletions(-) create mode 100644 mlir/test/Dialect/SparseTensor/fuse_sparse_convert_into_producer.mlir delete mode 100644 mlir/test/Dialect/SparseTensor/no_fold_into_consumer.mlir diff --git a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h index 5e523ec428ae..b182b4c72b95 100644 --- a/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h +++ b/mlir/include/mlir/Dialect/SparseTensor/IR/SparseTensor.h @@ -89,18 +89,21 @@ inline MemRefType getMemRefType(T &&t) { /// Returns null-attribute for any type without an encoding. SparseTensorEncodingAttr getSparseTensorEncoding(Type type); +/// Returns true iff the type range has any sparse tensor type. +inline bool hasAnySparseType(TypeRange types) { + return llvm::any_of(types, [](Type type) { + return getSparseTensorEncoding(type) != nullptr; + }); +} + /// Returns true iff MLIR operand has any sparse operand. inline bool hasAnySparseOperand(Operation *op) { - return llvm::any_of(op->getOperands().getTypes(), [](Type t) { - return getSparseTensorEncoding(t) != nullptr; - }); + return hasAnySparseType(op->getOperands().getTypes()); } /// Returns true iff MLIR operand has any sparse result. inline bool hasAnySparseResult(Operation *op) { - return llvm::any_of(op->getResults().getTypes(), [](Type t) { - return getSparseTensorEncoding(t) != nullptr; - }); + return hasAnySparseType(op->getResults().getTypes()); } /// Returns true iff MLIR operand has any sparse operand or result. diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp index 5a39dfc62077..9a8c6422a7ff 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/SparseTensorRewriting.cpp @@ -289,6 +289,37 @@ struct FuseExtractSliceWithConcat } }; +/// Rewriting rule that fuses sparse_tensor.convert into producer. +struct FoldConvertIntoProducer : public OpRewritePattern { +public: + using OpRewritePattern::OpRewritePattern; + + LogicalResult matchAndRewrite(ConvertOp op, + PatternRewriter &rewriter) const override { + auto producer = op.getSource().getDefiningOp(); + if (!producer || producer.getDpsInits().size() != 1 || + !isMaterializing(producer.getDpsInitOperand(0), false) || + !producer.getResult(0).hasOneUse()) { + return failure(); + } + rewriter.modifyOpInPlace(producer, [&]() { + producer.getResult(0).setType(op.getResult().getType()); + }); + + Operation *materializeOp = + producer.getDpsInitOperand(0)->get().getDefiningOp(); + + rewriter.modifyOpInPlace(materializeOp, [&]() { + materializeOp->getResult(0).setType(op.getResult().getType()); + }); + + rewriter.replaceAllOpUsesWith(op, producer); + op->erase(); + + return success(); + } +}; + /// Rewriting rule that converts direct yield of zero with initial allocation. struct FoldInvariantYield : public OpRewritePattern { public: @@ -1506,9 +1537,10 @@ struct OutRewriter : public OpRewritePattern { //===---------------------------------------------------------------------===// void mlir::populatePreSparsificationRewriting(RewritePatternSet &patterns) { - patterns.add(patterns.getContext()); + patterns.add( + patterns.getContext()); } void mlir::populateLowerSparseOpsToForeachPatterns(RewritePatternSet &patterns, diff --git a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp index cd046b670d9a..0a9bb40b458d 100644 --- a/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp +++ b/mlir/lib/Dialect/SparseTensor/Transforms/Sparsification.cpp @@ -403,6 +403,22 @@ static Value genInsertionLoadReduce(CodegenEnv &env, OpBuilder &builder, return builder.create(loc, isFilled, valAtIndex, identity); } +static Value genConditionalInsert(Location loc, OpBuilder &builder, Value cond, + Value sparseOut, ValueRange ivs, Value v) { + scf::IfOp condInsert = + builder.create(loc, sparseOut.getType(), cond, true); + // True branch. + builder.setInsertionPointToStart(condInsert.thenBlock()); + Value res = builder.create(loc, v, sparseOut, ivs); + builder.create(loc, res); + // False branch. + builder.setInsertionPointToStart(condInsert.elseBlock()); + builder.create(loc, sparseOut); + // Value assignment. + builder.setInsertionPointAfter(condInsert); + return condInsert.getResult(0); +} + /// Generates insertion code to implement dynamic tensor store. static void genInsertionStore(CodegenEnv &env, OpBuilder &builder, OpOperand *t, Value rhs) { @@ -423,23 +439,21 @@ static void genInsertionStore(CodegenEnv &env, OpBuilder &builder, OpOperand *t, // return updated chain // else // return unmodified chain - scf::IfOp ifValidLexInsert = builder.create( - loc, chain.getType(), env.getValidLexInsert(), - /*else=*/true); - // True branch. - builder.setInsertionPointToStart(ifValidLexInsert.thenBlock()); - Value res = builder.create(loc, rhs, chain, ivs); - builder.create(loc, res); - // False branch. - builder.setInsertionPointToStart(ifValidLexInsert.elseBlock()); - builder.create(loc, chain); - // Value assignment. - builder.setInsertionPointAfter(ifValidLexInsert); - env.updateInsertionChain(ifValidLexInsert.getResult(0)); + Value out = genConditionalInsert(loc, builder, env.getValidLexInsert(), + chain, ivs, rhs); + env.updateInsertionChain(out); } else { + Value sparseOut; + if (!hasAnySparseType(env.op().getInputs().getTypes())) { + // This is an all-dense -> sparse kernel, test rhs != 0 before + // insertion. + Value nz = genIsNonzero(builder, loc, rhs); + sparseOut = genConditionalInsert(loc, builder, nz, chain, ivs, rhs); + } else { + sparseOut = builder.create(loc, rhs, chain, ivs); + } // Generates regular insertion chain. - env.updateInsertionChain( - builder.create(loc, rhs, chain, ivs)); + env.updateInsertionChain(sparseOut); } return; } diff --git a/mlir/test/Dialect/SparseTensor/fuse_sparse_convert_into_producer.mlir b/mlir/test/Dialect/SparseTensor/fuse_sparse_convert_into_producer.mlir new file mode 100644 index 000000000000..efa92e565ba5 --- /dev/null +++ b/mlir/test/Dialect/SparseTensor/fuse_sparse_convert_into_producer.mlir @@ -0,0 +1,78 @@ +// RUN: mlir-opt %s --pre-sparsification-rewrite --sparse-reinterpret-map | FileCheck %s --check-prefix=CHECK-FOLD +// RUN: mlir-opt %s --pre-sparsification-rewrite --sparse-reinterpret-map --sparsification | FileCheck %s + +#trait = { + indexing_maps = [ + affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>, + affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>, + affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)>, + affine_map<(d0, d1, d2, d3) -> (d0, d1, d2, d3)> + ], + iterator_types = ["parallel", "parallel", "parallel", "parallel"] +} + +#map = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +#COO = #sparse_tensor.encoding<{map = (d0, d1, d2) -> (d0 : compressed(nonunique), d1 : singleton(nonunique, soa), d2 : singleton(soa))}> +#CCCD = #sparse_tensor.encoding<{ map = (d0, d1, d2, d3) -> (d0 : compressed, d1 : compressed, d2 : compressed, d3 : dense) }> + +// CHECK-LABEL: func.func @fold_convert( +// CHECK: scf.for +// CHECK: scf.for +// CHECK: scf.for +// CHECK: scf.if +// CHECK-NEXT: tensor.insert +// CHECK-NEXT: scf.yield +// CHECK-NEXT: else +// CHECK-NEXT: scf.yield +// CHECK: scf.yield +// CHECK: scf.yield +// CHECK: scf.yield +// CHECK: sparse_tensor.load + +// CHECK-FOLD-LABEL: func.func @fold_convert( +// CHECK-FOLD-NOT: sparse_tensor.convert +func.func @fold_convert(%arg0: tensor<128x32x32x1xf32>, %arg1: tensor<128x32x32x1xf32>, %arg2: tensor<128x32x32x1xf32>) -> tensor<128x32x32x1xf32, #CCCD> { + %cst = arith.constant 0.000000e+00 : f32 + %cst_0 = arith.constant 1.000000e+00 : f32 + %cst_1 = arith.constant 1.000000e+00 : f32 + %0 = tensor.empty() : tensor<128x32x32x1xf32> + %1 = linalg.generic #trait + ins(%arg0, %arg1, %arg2 : tensor<128x32x32x1xf32>, tensor<128x32x32x1xf32>, tensor<128x32x32x1xf32>) + outs(%0 : tensor<128x32x32x1xf32>) { + ^bb0(%in: f32, %in_2: f32, %in_3: f32, %out: f32): + %3 = arith.subf %cst_0, %in_2 : f32 + %4 = arith.mulf %in, %3 : f32 + %5 = arith.mulf %4, %cst_1 : f32 + %6 = arith.addf %5, %in_3 : f32 + %7 = arith.subf %6, %cst_0 : f32 + %8 = arith.cmpf uge, %7, %cst : f32 + %9 = arith.uitofp %8 : i1 to f32 + linalg.yield %9 : f32 + } -> tensor<128x32x32x1xf32> + %2 = sparse_tensor.convert %1 : tensor<128x32x32x1xf32> to tensor<128x32x32x1xf32, #CCCD> + return %2 : tensor<128x32x32x1xf32, #CCCD> +} + + +// FIXME: The following kernel is not sparsifiable because `arith.select` +// operations is not handled by the sparse compiler at the moment. +// +// CHECK-FOLD-LABEL: func.func @fold_cast( +// CHECK-FOLD-NOT: sparse_tensor.convert +func.func @fold_cast(%0: tensor<10x20x30xf64, #COO>) -> tensor<10x20x30xf64, #COO> { + %cst = arith.constant 0.000000e+00 : f64 + %1 = tensor.empty() : tensor<10x20x30xf64> + %2 = linalg.generic { indexing_maps = [#map, #map], + iterator_types = ["parallel", "parallel", "parallel"] + } + ins (%0 : tensor<10x20x30xf64, #COO>) + outs(%1 : tensor<10x20x30xf64>) { + ^bb0(%in: f64, %out: f64): + %4 = arith.cmpf ugt, %in, %cst : f64 + %5 = arith.select %4, %in, %cst : f64 + linalg.yield %5 : f64 + } -> tensor<10x20x30xf64> + %cast = tensor.cast %2 : tensor<10x20x30xf64> to tensor<10x20x30xf64, #COO> + return %cast : tensor<10x20x30xf64, #COO> +} diff --git a/mlir/test/Dialect/SparseTensor/no_fold_into_consumer.mlir b/mlir/test/Dialect/SparseTensor/no_fold_into_consumer.mlir deleted file mode 100644 index bbc7f397e793..000000000000 --- a/mlir/test/Dialect/SparseTensor/no_fold_into_consumer.mlir +++ /dev/null @@ -1,47 +0,0 @@ -// RUN: mlir-opt %s --canonicalize --pre-sparsification-rewrite | FileCheck %s - -#map = affine_map<(d0, d1, d2) -> (d0, d1, d2)> - -#sparse = #sparse_tensor.encoding<{ - map = (d0, d1, d2) -> - (d0 : compressed(nonunique), - d1 : singleton(nonunique, soa), - d2 : singleton(soa)), - posWidth = 64, - crdWidth = 64 -}> - - -module { - // - // This IR should not end up in an infinite loop trying to fold - // the linalg producer into the tensor cast consumer (even though - // static sizes can fold, the different encodings cannot). The - // cast was sloppy to begin with (but it has been observed by - // external sources) and can be easily repaired by the sparsifier. - // - // CHECK-LABEL: func @avoid_fold - // CHECK: arith.constant - // CHECK: tensor.empty() - // CHECK: linalg.generic - // CHECK: sparse_tensor.convert - // CHECK: return - // - func.func @avoid_fold(%0: tensor<10x20x30xf64, #sparse>) -> tensor<10x20x30xf64, #sparse> { - %1 = tensor.empty() : tensor<10x20x30xf64> - %2 = linalg.generic { indexing_maps = [#map, #map], - iterator_types = ["parallel", "parallel", "parallel"] - } - ins (%0 : tensor<10x20x30xf64, #sparse>) - outs(%1 : tensor<10x20x30xf64>) { - ^bb0(%in: f64, %out: f64): - %cst = arith.constant 0.000000e+00 : f64 - %4 = arith.cmpf ugt, %in, %cst : f64 - %5 = arith.select %4, %in, %cst : f64 - linalg.yield %5 : f64 - } -> tensor<10x20x30xf64> - %cast = tensor.cast %2 : tensor<10x20x30xf64> to tensor<10x20x30xf64, #sparse> - return %cast : tensor<10x20x30xf64, #sparse> - } -} - -- GitLab From 760910ddb918d77e7632be1678f69909384d69ae Mon Sep 17 00:00:00 2001 From: Eli Friedman Date: Fri, 26 Apr 2024 11:06:11 -0700 Subject: [PATCH 082/301] [Arm64EC] Improve alignment mangling in arm64ec thunks. (#90115) In some cases, MSVC's mangling for arm64ec thunks includes the alignment of a struct. I added some code to try to match... but it never really worked right. The issues: - Alignment is only mangled if it's 16 or more (I guess the default is supposed to be 8). - Alignment isn't mangled on return values (since the memory is allocated by the caller). The current patch leaves hooks to make alignment mangling work... but doesn't actually ever mangle alignment: clang never actually encodes a relevant alignment into the IR. Once we get clang to emit the real size/alignment of structs, we can start emitting it. --- llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp | 7 ++++--- llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll | 6 +++--- llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll | 10 +++++----- 3 files changed, 12 insertions(+), 11 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp index 3bf6283b79e9..dddc181b0314 100644 --- a/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64Arm64ECCallLowering.cpp @@ -178,13 +178,14 @@ void AArch64Arm64ECCallLowering::getThunkArgTypes( } for (unsigned E = FT->getNumParams(); I != E; ++I) { - Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne(); #if 0 // FIXME: Need more information about argument size; see // https://reviews.llvm.org/D132926 uint64_t ArgSizeBytes = AttrList.getParamArm64ECArgSizeBytes(I); + Align ParamAlign = AttrList.getParamAlignment(I).valueOrOne(); #else uint64_t ArgSizeBytes = 0; + Align ParamAlign = Align(); #endif Type *Arm64Ty, *X64Ty; canonicalizeThunkType(FT->getParamType(I), ParamAlign, @@ -294,7 +295,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType( uint64_t TotalSizeBytes = ElementCnt * ElementSizePerBytes; if (ElementTy->isFloatTy() || ElementTy->isDoubleTy()) { Out << (ElementTy->isFloatTy() ? "F" : "D") << TotalSizeBytes; - if (Alignment.value() >= 8 && !T->isPointerTy()) + if (Alignment.value() >= 16 && !Ret) Out << "a" << Alignment.value(); Arm64Ty = T; if (TotalSizeBytes <= 8) { @@ -325,7 +326,7 @@ void AArch64Arm64ECCallLowering::canonicalizeThunkType( Out << "m"; if (TypeSize != 4) Out << TypeSize; - if (Alignment.value() >= 8 && !T->isPointerTy()) + if (Alignment.value() >= 16 && !Ret) Out << "a" << Alignment.value(); // FIXME: Try to canonicalize Arm64Ty more thoroughly? Arm64Ty = T; diff --git a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll index bb9ba05f7a27..c00c9bfe127e 100644 --- a/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll +++ b/llvm/test/CodeGen/AArch64/arm64ec-entry-thunks.ll @@ -223,8 +223,8 @@ define i8 @matches_has_sret() nounwind { %TSRet = type { i64, i64 } define void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind { -; CHECK-LABEL: .def $ientry_thunk$cdecl$m16a32$v; -; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16a32$v +; CHECK-LABEL: .def $ientry_thunk$cdecl$m16$v; +; CHECK: .section .wowthk$aa,"xr",discard,$ientry_thunk$cdecl$m16$v ; CHECK: // %bb.0: ; CHECK-NEXT: stp q6, q7, [sp, #-176]! // 32-byte Folded Spill ; CHECK-NEXT: .seh_save_any_reg_px q6, 176 @@ -457,7 +457,7 @@ define %T2 @simple_struct(%T1 %0, %T2 %1, %T3, %T4) nounwind { ; CHECK-NEXT: .symidx $ientry_thunk$cdecl$i8$v ; CHECK-NEXT: .word 1 ; CHECK-NEXT: .symidx "#has_aligned_sret" -; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16a32$v +; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m16$v ; CHECK-NEXT: .word 1 ; CHECK-NEXT: .symidx "#small_array" ; CHECK-NEXT: .symidx $ientry_thunk$cdecl$m2$m2F8 diff --git a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll index 3b911e78aff2..7a40fcd85ac5 100644 --- a/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll +++ b/llvm/test/CodeGen/AArch64/arm64ec-exit-thunks.ll @@ -236,8 +236,8 @@ declare void @has_sret(ptr sret([100 x i8])) nounwind; %TSRet = type { i64, i64 } declare void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind; -; CHECK-LABEL: .def $iexit_thunk$cdecl$m16a32$v; -; CHECK: .section .wowthk$aa,"xr",discard,$iexit_thunk$cdecl$m16a32$v +; CHECK-LABEL: .def $iexit_thunk$cdecl$m16$v; +; CHECK: .section .wowthk$aa,"xr",discard,$iexit_thunk$cdecl$m16$v ; CHECK: // %bb.0: ; CHECK-NEXT: sub sp, sp, #48 ; CHECK-NEXT: .seh_stackalloc 48 @@ -271,8 +271,8 @@ declare void @has_aligned_sret(ptr align 32 sret(%TSRet)) nounwind; ; CHECK: adrp x11, has_aligned_sret ; CHECK: add x11, x11, :lo12:has_aligned_sret ; CHECK: ldr x9, [x9, :lo12:__os_arm64x_check_icall] -; CHECK: adrp x10, ($iexit_thunk$cdecl$m16a32$v) -; CHECK: add x10, x10, :lo12:($iexit_thunk$cdecl$m16a32$v) +; CHECK: adrp x10, ($iexit_thunk$cdecl$m16$v) +; CHECK: add x10, x10, :lo12:($iexit_thunk$cdecl$m16$v) ; CHECK: blr x9 ; CHECK: .seh_startepilogue ; CHECK: ldr x30, [sp], #16 // 8-byte Folded Reload @@ -492,7 +492,7 @@ declare %T2 @simple_struct(%T1, %T2, %T3, %T4) nounwind; ; CHECK-NEXT: .symidx has_sret ; CHECK-NEXT: .word 0 ; CHECK-NEXT: .symidx has_aligned_sret -; CHECK-NEXT: .symidx $iexit_thunk$cdecl$m16a32$v +; CHECK-NEXT: .symidx $iexit_thunk$cdecl$m16$v ; CHECK-NEXT: .word 4 ; CHECK-NEXT: .symidx "#has_aligned_sret$exit_thunk" ; CHECK-NEXT: .symidx has_aligned_sret -- GitLab From b27f86b40b20942c0e809128214b43d6edde365a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 26 Apr 2024 11:27:28 -0700 Subject: [PATCH 083/301] [RISCV] Add an instruction PrettyPrinter to llvm-objdump (#90093) This prints the opcode bytes in the same order as GNU objdump without a space between them. --- lld/test/ELF/riscv-branch.s | 16 +- lld/test/ELF/riscv-call.s | 16 +- lld/test/ELF/riscv-hi20-lo12.s | 24 +- lld/test/ELF/riscv-jal.s | 16 +- llvm/docs/ReleaseNotes.rst | 2 + llvm/test/MC/RISCV/XTHeadVdot-valid.s | 28 +- llvm/test/MC/RISCV/align.s | 8 +- llvm/test/MC/RISCV/compress-cjal.s | 2 +- llvm/test/MC/RISCV/compress-rv32d.s | 8 +- llvm/test/MC/RISCV/compress-rv32f.s | 8 +- llvm/test/MC/RISCV/compress-rv32i.s | 70 +- llvm/test/MC/RISCV/compress-rv64i.s | 16 +- llvm/test/MC/RISCV/nop-slide.s | 22 +- llvm/test/MC/RISCV/option-pushpop.s | 8 +- llvm/test/MC/RISCV/option-rvc.s | 20 +- llvm/test/MC/RISCV/rv32e-invalid.s | 64 +- llvm/test/MC/RISCV/rvv/add.s | 118 +-- llvm/test/MC/RISCV/rvv/and.s | 12 +- llvm/test/MC/RISCV/rvv/clip.s | 24 +- llvm/test/MC/RISCV/rvv/compare.s | 166 ++-- llvm/test/MC/RISCV/rvv/convert.s | 86 +- llvm/test/MC/RISCV/rvv/div.s | 32 +- llvm/test/MC/RISCV/rvv/ext.s | 24 +- llvm/test/MC/RISCV/rvv/fadd.s | 24 +- llvm/test/MC/RISCV/rvv/fcompare.s | 50 +- llvm/test/MC/RISCV/rvv/fdiv.s | 12 +- llvm/test/MC/RISCV/rvv/fmacc.s | 96 +- llvm/test/MC/RISCV/rvv/fminmax.s | 16 +- llvm/test/MC/RISCV/rvv/fmul.s | 16 +- llvm/test/MC/RISCV/rvv/fmv.s | 6 +- llvm/test/MC/RISCV/rvv/fothers.s | 26 +- llvm/test/MC/RISCV/rvv/freduction.s | 26 +- llvm/test/MC/RISCV/rvv/fsub.s | 28 +- llvm/test/MC/RISCV/rvv/load.s | 128 +-- llvm/test/MC/RISCV/rvv/macc.s | 60 +- llvm/test/MC/RISCV/rvv/mask.s | 52 +- llvm/test/MC/RISCV/rvv/minmax.s | 32 +- llvm/test/MC/RISCV/rvv/mul.s | 64 +- llvm/test/MC/RISCV/rvv/mv.s | 18 +- llvm/test/MC/RISCV/rvv/or.s | 12 +- llvm/test/MC/RISCV/rvv/others.s | 48 +- llvm/test/MC/RISCV/rvv/reduction.s | 42 +- llvm/test/MC/RISCV/rvv/shift.s | 86 +- llvm/test/MC/RISCV/rvv/sign-injection.s | 24 +- llvm/test/MC/RISCV/rvv/snippet.s | 24 +- llvm/test/MC/RISCV/rvv/store.s | 84 +- llvm/test/MC/RISCV/rvv/sub.s | 100 +-- llvm/test/MC/RISCV/rvv/vsetvl.s | 50 +- llvm/test/MC/RISCV/rvv/xor.s | 16 +- llvm/test/MC/RISCV/rvv/xsfvcp.s | 56 +- llvm/test/MC/RISCV/rvv/xsfvfnrclip.s | 8 +- llvm/test/MC/RISCV/rvv/xsfvfwmacc.s | 2 +- llvm/test/MC/RISCV/rvv/xsfvqmacc.s | 16 +- llvm/test/MC/RISCV/rvv/zvbb.s | 14 +- llvm/test/MC/RISCV/rvv/zvbc.s | 8 +- llvm/test/MC/RISCV/rvv/zvfbfmin.s | 8 +- llvm/test/MC/RISCV/rvv/zvfbfwma.s | 16 +- llvm/test/MC/RISCV/rvv/zvkb.s | 18 +- llvm/test/MC/RISCV/rvv/zvkg.s | 4 +- llvm/test/MC/RISCV/rvv/zvkned.s | 26 +- llvm/test/MC/RISCV/rvv/zvknh.s | 6 +- llvm/test/MC/RISCV/rvv/zvksed.s | 8 +- llvm/test/MC/RISCV/rvv/zvksh.s | 6 +- llvm/test/MC/RISCV/rvv/zvlsseg.s | 1026 +++++++++++----------- llvm/tools/llvm-objdump/llvm-objdump.cpp | 52 ++ 65 files changed, 1629 insertions(+), 1575 deletions(-) diff --git a/lld/test/ELF/riscv-branch.s b/lld/test/ELF/riscv-branch.s index dbf39dc0bb8f..1a2b446b5a43 100644 --- a/lld/test/ELF/riscv-branch.s +++ b/lld/test/ELF/riscv-branch.s @@ -7,19 +7,19 @@ # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64 # RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32 # RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64 -# CHECK-32: 63 02 00 00 beqz zero, 0x110b8 -# CHECK-32: e3 1e 00 fe bnez zero, 0x110b4 -# CHECK-64: 63 02 00 00 beqz zero, 0x11124 -# CHECK-64: e3 1e 00 fe bnez zero, 0x11120 +# CHECK-32: 00000263 beqz zero, 0x110b8 +# CHECK-32: fe001ee3 bnez zero, 0x110b4 +# CHECK-64: 00000263 beqz zero, 0x11124 +# CHECK-64: fe001ee3 bnez zero, 0x11120 # # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffe --defsym bar=_start+4-0x1000 -o %t.rv64.limits # RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s # RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s -# LIMITS-32: e3 0f 00 7e beqz zero, 0x120b2 -# LIMITS-32-NEXT: 63 10 00 80 bnez zero, 0x100b8 -# LIMITS-64: e3 0f 00 7e beqz zero, 0x1211e -# LIMITS-64-NEXT: 63 10 00 80 bnez zero, 0x10124 +# LIMITS-32: 7e000fe3 beqz zero, 0x120b2 +# LIMITS-32-NEXT: 80001063 bnez zero, 0x100b8 +# LIMITS-64: 7e000fe3 beqz zero, 0x1211e +# LIMITS-64-NEXT: 80001063 bnez zero, 0x10124 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x1000 --defsym bar=_start+4-0x1002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s diff --git a/lld/test/ELF/riscv-call.s b/lld/test/ELF/riscv-call.s index 5fef156df0bb..0e81e9b4710e 100644 --- a/lld/test/ELF/riscv-call.s +++ b/lld/test/ELF/riscv-call.s @@ -7,19 +7,19 @@ # RUN: ld.lld %t.rv64.o --defsym foo=_start+8 --defsym bar=_start -o %t.rv64 # RUN: llvm-objdump -d %t.rv32 | FileCheck %s # RUN: llvm-objdump -d %t.rv64 | FileCheck %s -# CHECK: 97 00 00 00 auipc ra, 0x0 -# CHECK-NEXT: e7 80 80 00 jalr 0x8(ra) -# CHECK: 97 00 00 00 auipc ra, 0x0 -# CHECK-NEXT: e7 80 80 ff jalr -0x8(ra) +# CHECK: 00000097 auipc ra, 0x0 +# CHECK-NEXT: 008080e7 jalr 0x8(ra) +# CHECK: 00000097 auipc ra, 0x0 +# CHECK-NEXT: ff8080e7 jalr -0x8(ra) # RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=_start+0x7ffff7ff --defsym bar=_start+8-0x80000800 -o %t.rv64.limits # RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s # RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s -# LIMITS: 97 f0 ff 7f auipc ra, 0x7ffff -# LIMITS-NEXT: e7 80 f0 7f jalr 0x7ff(ra) -# LIMITS-NEXT: 97 00 00 80 auipc ra, 0x80000 -# LIMITS-NEXT: e7 80 00 80 jalr -0x800(ra) +# LIMITS: 7ffff097 auipc ra, 0x7ffff +# LIMITS-NEXT: 7ff080e7 jalr 0x7ff(ra) +# LIMITS-NEXT: 80000097 auipc ra, 0x80000 +# LIMITS-NEXT: 800080e7 jalr -0x800(ra) # RUN: ld.lld %t.rv32.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o %t # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x7ffff800 --defsym bar=_start+8-0x80000801 -o /dev/null 2>&1 | \ diff --git a/lld/test/ELF/riscv-hi20-lo12.s b/lld/test/ELF/riscv-hi20-lo12.s index 85861432db0b..b9786f563f28 100644 --- a/lld/test/ELF/riscv-hi20-lo12.s +++ b/lld/test/ELF/riscv-hi20-lo12.s @@ -7,23 +7,23 @@ # RUN: ld.lld %t.rv64.o --defsym foo=0 --defsym bar=42 -o %t.rv64 # RUN: llvm-objdump -d %t.rv32 | FileCheck %s # RUN: llvm-objdump -d %t.rv64 | FileCheck %s -# CHECK: 37 05 00 00 lui a0, 0x0 -# CHECK-NEXT: 13 05 05 00 mv a0, a0 -# CHECK-NEXT: 23 20 a5 00 sw a0, 0x0(a0) -# CHECK-NEXT: b7 05 00 00 lui a1, 0x0 -# CHECK-NEXT: 93 85 a5 02 addi a1, a1, 0x2a -# CHECK-NEXT: 23 a5 b5 02 sw a1, 0x2a(a1) +# CHECK: 00000537 lui a0, 0x0 +# CHECK-NEXT: 00050513 mv a0, a0 +# CHECK-NEXT: 00a52023 sw a0, 0x0(a0) +# CHECK-NEXT: 000005b7 lui a1, 0x0 +# CHECK-NEXT: 02a58593 addi a1, a1, 0x2a +# CHECK-NEXT: 02b5a523 sw a1, 0x2a(a1) # RUN: ld.lld %t.rv32.o --defsym foo=0x7ffff7ff --defsym bar=0x7ffff800 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=0x7ffff7ff --defsym bar=0xffffffff7ffff800 -o %t.rv64.limits # RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS %s # RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS %s -# LIMITS: 37 f5 ff 7f lui a0, 0x7ffff -# LIMITS-NEXT: 13 05 f5 7f addi a0, a0, 0x7ff -# LIMITS-NEXT: a3 2f a5 7e sw a0, 0x7ff(a0) -# LIMITS-NEXT: b7 05 00 80 lui a1, 0x80000 -# LIMITS-NEXT: 93 85 05 80 addi a1, a1, -0x800 -# LIMITS-NEXT: 23 a0 b5 80 sw a1, -0x800(a1) +# LIMITS: 7ffff537 lui a0, 0x7ffff +# LIMITS-NEXT: 7ff50513 addi a0, a0, 0x7ff +# LIMITS-NEXT: 7ea52fa3 sw a0, 0x7ff(a0) +# LIMITS-NEXT: 800005b7 lui a1, 0x80000 +# LIMITS-NEXT: 80058593 addi a1, a1, -0x800 +# LIMITS-NEXT: 80b5a023 sw a1, -0x800(a1) # RUN: not ld.lld %t.rv64.o --defsym foo=0x7ffff800 --defsym bar=0xffffffff7ffff7ff -o /dev/null 2>&1 | FileCheck --check-prefix ERROR %s # ERROR: relocation R_RISCV_HI20 out of range: 524288 is not in [-524288, 524287]; references 'foo' diff --git a/lld/test/ELF/riscv-jal.s b/lld/test/ELF/riscv-jal.s index cd3b842aad60..2129e4454706 100644 --- a/lld/test/ELF/riscv-jal.s +++ b/lld/test/ELF/riscv-jal.s @@ -7,19 +7,19 @@ # RUN: ld.lld %t.rv64.o --defsym foo=_start+4 --defsym bar=_start -o %t.rv64 # RUN: llvm-objdump -d %t.rv32 | FileCheck %s --check-prefix=CHECK-32 # RUN: llvm-objdump -d %t.rv64 | FileCheck %s --check-prefix=CHECK-64 -# CHECK-32: 6f 00 40 00 j 0x110b8 -# CHECK-32: ef f0 df ff jal 0x110b4 -# CHECK-64: 6f 00 40 00 j 0x11124 -# CHECK-64: ef f0 df ff jal 0x11120 +# CHECK-32: 0040006f j 0x110b8 +# CHECK-32: ffdff0ef jal 0x110b4 +# CHECK-64: 0040006f j 0x11124 +# CHECK-64: ffdff0ef jal 0x11120 # RUN: ld.lld %t.rv32.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv32.limits # RUN: ld.lld %t.rv64.o --defsym foo=_start+0xffffe --defsym bar=_start+4-0x100000 -o %t.rv64.limits # RUN: llvm-objdump -d %t.rv32.limits | FileCheck --check-prefix=LIMITS-32 %s # RUN: llvm-objdump -d %t.rv64.limits | FileCheck --check-prefix=LIMITS-64 %s -# LIMITS-32: 6f f0 ff 7f j 0x1110b2 -# LIMITS-32-NEXT: ef 00 00 80 jal 0xfff110b8 -# LIMITS-64: 6f f0 ff 7f j 0x11111e -# LIMITS-64-NEXT: ef 00 00 80 jal 0xfffffffffff11124 +# LIMITS-32: 7ffff06f j 0x1110b2 +# LIMITS-32-NEXT: 800000ef jal 0xfff110b8 +# LIMITS-64: 7ffff06f j 0x11111e +# LIMITS-64-NEXT: 800000ef jal 0xfffffffffff11124 # RUN: not ld.lld %t.rv32.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s # RUN: not ld.lld %t.rv64.o --defsym foo=_start+0x100000 --defsym bar=_start+4-0x100002 -o /dev/null 2>&1 | FileCheck --check-prefix=ERROR-RANGE %s diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index a83b8bb79a1c..64a698325212 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -113,6 +113,8 @@ Changes to the RISC-V Backend * The experimental Ssqosid extension is supported. * Zacas is no longer experimental. * Added the CSR names from the Resumable Non-Maskable Interrupts (Smrnmi) extension. +* llvm-objdump now prints disassembled opcode bytes in groups of 2 or 4 bytes to + match GNU objdump. The bytes within the groups are in big endian order. Changes to the WebAssembly Backend ---------------------------------- diff --git a/llvm/test/MC/RISCV/XTHeadVdot-valid.s b/llvm/test/MC/RISCV/XTHeadVdot-valid.s index 2e00bd1cac3e..ab411dfac730 100644 --- a/llvm/test/MC/RISCV/XTHeadVdot-valid.s +++ b/llvm/test/MC/RISCV/XTHeadVdot-valid.s @@ -12,82 +12,82 @@ th.vmaqau.vv v8, v20, v4, v0.t # CHECK-INST: th.vmaqau.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x0b,0x64,0x4a,0x88] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 4a 88 +# CHECK-UNKNOWN: 884a640b th.vmaqau.vv v8, v20, v4 # CHECK-INST: th.vmaqau.vv v8, v20, v4 # CHECK-ENCODING: [0x0b,0x64,0x4a,0x8a] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 4a 8a +# CHECK-UNKNOWN: 8a4a640b th.vmaqau.vx v8, a0, v4, v0.t # CHECK-INST: th.vmaqau.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x0b,0x64,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 8c +# CHECK-UNKNOWN: 8c45640b th.vmaqau.vx v8, a0, v4 # CHECK-INST: th.vmaqau.vx v8, a0, v4 # CHECK-ENCODING: [0x0b,0x64,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 8e +# CHECK-UNKNOWN: 8e45640b th.vmaqa.vv v8, v20, v4, v0.t # CHECK-INST: th.vmaqa.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x0b,0x64,0x4a,0x80] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 4a 80 +# CHECK-UNKNOWN: 804a640b th.vmaqa.vv v8, v20, v4 # CHECK-INST: th.vmaqa.vv v8, v20, v4 # CHECK-ENCODING: [0x0b,0x64,0x4a,0x82] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 4a 82 +# CHECK-UNKNOWN: 824a640b th.vmaqa.vx v8, a0, v4, v0.t # CHECK-INST: th.vmaqa.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x0b,0x64,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 84 +# CHECK-UNKNOWN: 8445640b th.vmaqa.vx v8, a0, v4 # CHECK-INST: th.vmaqa.vx v8, a0, v4 # CHECK-ENCODING: [0x0b,0x64,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 86 +# CHECK-UNKNOWN: 8645640b th.vmaqasu.vv v8, v20, v4, v0.t # CHECK-INST: th.vmaqasu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x0b,0x64,0x4a,0x90] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 4a 90 +# CHECK-UNKNOWN: 904a640b th.vmaqasu.vv v8, v20, v4 # CHECK-INST: th.vmaqasu.vv v8, v20, v4 # CHECK-ENCODING: [0x0b,0x64,0x4a,0x92] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 4a 92 +# CHECK-UNKNOWN: 924a640b th.vmaqasu.vx v8, a0, v4, v0.t # CHECK-INST: th.vmaqasu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x0b,0x64,0x45,0x94] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 94 +# CHECK-UNKNOWN: 9445640b th.vmaqasu.vx v8, a0, v4 # CHECK-INST: th.vmaqasu.vx v8, a0, v4 # CHECK-ENCODING: [0x0b,0x64,0x45,0x96] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 96 +# CHECK-UNKNOWN: 9645640b th.vmaqaus.vx v8, a0, v4, v0.t # CHECK-INST: th.vmaqaus.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x0b,0x64,0x45,0x9c] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 9c +# CHECK-UNKNOWN: 9c45640b th.vmaqaus.vx v8, a0, v4 # CHECK-INST: th.vmaqaus.vx v8, a0, v4 # CHECK-ENCODING: [0x0b,0x64,0x45,0x9e] # CHECK-ERROR: instruction requires the following: 'xtheadvdot' (T-Head Vector Extensions for Dot){{$}} -# CHECK-UNKNOWN: 0b 64 45 9e +# CHECK-UNKNOWN: 9e45640b diff --git a/llvm/test/MC/RISCV/align.s b/llvm/test/MC/RISCV/align.s index 2eb7186d0de9..32cc071b613c 100644 --- a/llvm/test/MC/RISCV/align.s +++ b/llvm/test/MC/RISCV/align.s @@ -98,11 +98,11 @@ test: # The behavior is the same as GNU assembler. .p2align 4, 1 # RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xC -# RELAX-INST: 01 01 -# RELAX-INST: 01 01 +# RELAX-INST: 0101 +# RELAX-INST: 0101 # C-OR-ZCA-EXT-RELAX-RELOC-NOT: R_RISCV_ALIGN - 0xE -# C-OR-ZCA-EXT-RELAX-INST: 01 01 -# C-EXT-INST: 01 01 +# C-OR-ZCA-EXT-RELAX-INST: 0101 +# C-EXT-INST: 0101 ret # NORELAX-RELOC-NOT: R_RISCV # C-OR-ZCA-EXT-NORELAX-RELOC-NOT: R_RISCV diff --git a/llvm/test/MC/RISCV/compress-cjal.s b/llvm/test/MC/RISCV/compress-cjal.s index 31b9c30c2b01..d55586b005c7 100644 --- a/llvm/test/MC/RISCV/compress-cjal.s +++ b/llvm/test/MC/RISCV/compress-cjal.s @@ -11,7 +11,7 @@ # c.jal is an rv32 only instruction. jal ra, 2046 -# CHECK-BYTES: fd 2f +# CHECK-BYTES: 2ffd # CHECK-ALIASOBJ: jal 0x7fe # CHECK-ALIAS: jal 2046 # CHECK-INST: c.jal 2046 diff --git a/llvm/test/MC/RISCV/compress-rv32d.s b/llvm/test/MC/RISCV/compress-rv32d.s index bebc78ef8690..c41a08892862 100644 --- a/llvm/test/MC/RISCV/compress-rv32d.s +++ b/llvm/test/MC/RISCV/compress-rv32d.s @@ -43,22 +43,22 @@ # Tests double precision floating point instructions available in rv32 and in rv64. fld ft0, 64(sp) -# CHECK-BYTES: 06 20 +# CHECK-BYTES: 2006 # CHECK-ALIAS: fld ft0, 64(sp) # CHECK-INST: c.fldsp ft0, 64(sp) # CHECK: # encoding: [0x06,0x20] fsd ft0, 64(sp) -# CHECK-BYTES: 82 a0 +# CHECK-BYTES: a082 # CHECK-ALIAS: fsd ft0, 64(sp) # CHECK-INST: c.fsdsp ft0, 64(sp) # CHECK: # encoding: [0x82,0xa0] fld fs0, 248(s0) -# CHECK-BYTES: 60 3c +# CHECK-BYTES: 3c60 # CHECK-ALIAS: fld fs0, 248(s0) # CHECK-INST: c.fld fs0, 248(s0) # CHECK: # encoding: [0x60,0x3c] fsd fs0, 248(s0) -# CHECK-BYTES: 60 bc +# CHECK-BYTES: bc60 # CHECK-ALIAS: fsd fs0, 248(s0) # CHECK-INST: c.fsd fs0, 248(s0) # CHECK: # encoding: [0x60,0xbc] diff --git a/llvm/test/MC/RISCV/compress-rv32f.s b/llvm/test/MC/RISCV/compress-rv32f.s index 3f0c69fb9893..afe15c598bb6 100644 --- a/llvm/test/MC/RISCV/compress-rv32f.s +++ b/llvm/test/MC/RISCV/compress-rv32f.s @@ -21,22 +21,22 @@ # Instructions that are 32 bit only. flw ft0, 124(sp) -# CHECK-BYTES: 76 70 +# CHECK-BYTES: 7076 # CHECK-ALIAS: flw ft0, 124(sp) # CHECK-INST: c.flwsp ft0, 124(sp) # CHECK: # encoding: [0x76,0x70] fsw ft0, 124(sp) -# CHECK-BYTES: 82 fe +# CHECK-BYTES: fe82 # CHECK-ALIAS: fsw ft0, 124(sp) # CHECK-INST: c.fswsp ft0, 124(sp) # CHECK: # encoding: [0x82,0xfe] flw fs0, 124(s0) -# CHECK-BYTES: 60 7c +# CHECK-BYTES: 7c60 # CHECK-ALIAS: flw fs0, 124(s0) # CHECK-INST: c.flw fs0, 124(s0) # CHECK: # encoding: [0x60,0x7c] fsw fs0, 124(s0) -# CHECK-BYTES: 60 fc +# CHECK-BYTES: fc60 # CHECK-ALIAS: fsw fs0, 124(s0) # CHECK-INST: c.fsw fs0, 124(s0) # CHECK: # encoding: [0x60,0xfc] diff --git a/llvm/test/MC/RISCV/compress-rv32i.s b/llvm/test/MC/RISCV/compress-rv32i.s index b4fd72a0f81c..a75bea32ac0c 100644 --- a/llvm/test/MC/RISCV/compress-rv32i.s +++ b/llvm/test/MC/RISCV/compress-rv32i.s @@ -20,121 +20,121 @@ # RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST,CHECK-INSTOBJ64 %s -# CHECK-BYTES: 2e 85 +# CHECK-BYTES: 852e # CHECK-ALIAS: mv a0, a1 # CHECK-INST: c.mv a0, a1 # CHECK: # encoding: [0x2e,0x85] addi a0, a1, 0 -# CHECK-BYTES: e0 1f +# CHECK-BYTES: 1fe0 # CHECK-ALIAS: addi s0, sp, 1020 # CHECK-INST: c.addi4spn s0, sp, 1020 # CHECK: # encoding: [0xe0,0x1f] addi s0, sp, 1020 -# CHECK-BYTES: e0 5f +# CHECK-BYTES: 5fe0 # CHECK-ALIAS: lw s0, 124(a5) # CHECK-INST: c.lw s0, 124(a5) # CHECK: # encoding: [0xe0,0x5f] lw s0, 124(a5) -# CHECK-BYTES: e0 df +# CHECK-BYTES: dfe0 # CHECK-ALIAS: sw s0, 124(a5) # CHECK-INST: c.sw s0, 124(a5) # CHECK: # encoding: [0xe0,0xdf] sw s0, 124(a5) -# CHECK-BYTES: 01 00 +# CHECK-BYTES: 0001 # CHECK-ALIAS: nop # CHECK-INST: c.nop # CHECK: # encoding: [0x01,0x00] nop -# CHECK-BYTES: 81 10 +# CHECK-BYTES: 1081 # CHECK-ALIAS: addi ra, ra, -32 # CHECK-INST: c.addi ra, -32 # CHECK: # encoding: [0x81,0x10] addi ra, ra, -32 -# CHECK-BYTES: 85 50 +# CHECK-BYTES: 5085 # CHECK-ALIAS: li ra, -31 # CHECK-INST: c.li ra, -31 # CHECK: # encoding: [0x85,0x50] li ra, -31 -# CHECK-BYTES: 39 71 +# CHECK-BYTES: 7139 # CHECK-ALIAS: addi sp, sp, -64 # CHECK-INST: c.addi16sp sp, -64 # CHECK: # encoding: [0x39,0x71] addi sp, sp, -64 -# CHECK-BYTES: fd 61 +# CHECK-BYTES: 61fd # CHECK-ALIAS: lui gp, 31 # CHECK-INST: c.lui gp, 31 # CHECK: # encoding: [0xfd,0x61] lui gp, 31 -# CHECK-BYTES: 7d 80 +# CHECK-BYTES: 807d # CHECK-ALIAS: srli s0, s0, 31 # CHECK-INST: c.srli s0, 31 # CHECK: # encoding: [0x7d,0x80] srli s0, s0, 31 -# CHECK-BYTES: 7d 84 +# CHECK-BYTES: 847d # CHECK-ALIAS: srai s0, s0, 31 # CHECK-INST: c.srai s0, 31 # CHECK: # encoding: [0x7d,0x84] srai s0, s0, 31 -# CHECK-BYTES: 7d 88 +# CHECK-BYTES: 887d # CHECK-ALIAS: andi s0, s0, 31 # CHECK-INST: c.andi s0, 31 # CHECK: # encoding: [0x7d,0x88] andi s0, s0, 31 -# CHECK-BYTES: 1d 8c +# CHECK-BYTES: 8c1d # CHECK-ALIAS: sub s0, s0, a5 # CHECK-INST: c.sub s0, a5 # CHECK: # encoding: [0x1d,0x8c] sub s0, s0, a5 -# CHECK-BYTES: 3d 8c +# CHECK-BYTES: 8c3d # CHECK-ALIAS: xor s0, s0, a5 # CHECK-INST: c.xor s0, a5 # CHECK: # encoding: [0x3d,0x8c] xor s0, s0, a5 -# CHECK-BYTES: 3d 8c +# CHECK-BYTES: 8c3d # CHECK-ALIAS: xor s0, s0, a5 # CHECK-INST: c.xor s0, a5 # CHECK: # encoding: [0x3d,0x8c] xor s0, a5, s0 -# CHECK-BYTES: 5d 8c +# CHECK-BYTES: 8c5d # CHECK-ALIAS: or s0, s0, a5 # CHECK-INST: c.or s0, a5 # CHECK: # encoding: [0x5d,0x8c] or s0, s0, a5 -# CHECK-BYTES: 45 8c +# CHECK-BYTES: 8c45 # CHECK-ALIAS: or s0, s0, s1 # CHECK-INST: c.or s0, s1 # CHECK: # encoding: [0x45,0x8c] or s0, s1, s0 -# CHECK-BYTES: 7d 8c +# CHECK-BYTES: 8c7d # CHECK-ALIAS: and s0, s0, a5 # CHECK-INST: c.and s0, a5 # CHECK: # encoding: [0x7d,0x8c] and s0, s0, a5 -# CHECK-BYTES: 7d 8c +# CHECK-BYTES: 8c7d # CHECK-ALIAS: and s0, s0, a5 # CHECK-INST: c.and s0, a5 # CHECK: # encoding: [0x7d,0x8c] and s0, a5, s0 -# CHECK-BYTES: 01 b0 +# CHECK-BYTES: b001 # CHECK-ALIASASM: j -2048 # CHECK-ALIASOBJ32: j 0xfffff826 # CHECK-ALIASOBJ64: j 0xfffffffffffff826 @@ -144,7 +144,7 @@ and s0, a5, s0 # CHECK: # encoding: [0x01,0xb0] jal zero, -2048 -# CHECK-BYTES: 01 d0 +# CHECK-BYTES: d001 # CHECK-ALIASASM: beqz s0, -256 # CHECK-ALIASOBJ32: beqz s0, 0xffffff28 # CHECK-ALIASOBJ64: beqz s0, 0xffffffffffffff28 @@ -154,7 +154,7 @@ jal zero, -2048 # CHECK: # encoding: [0x01,0xd0] beq s0, zero, -256 -# CHECK-BYTES: 01 d0 +# CHECK-BYTES: d001 # CHECK-ALIASASM: beqz s0, -256 # CHECK-ALIASOBJ32: beqz s0, 0xffffff2a # CHECK-ALIASOBJ64: beqz s0, 0xffffffffffffff2a @@ -164,7 +164,7 @@ beq s0, zero, -256 # CHECK: # encoding: [0x01,0xd0] beq zero, s0, -256 -# CHECK-BYTES: 7d ec +# CHECK-BYTES: ec7d # CHECK-ALIASASM: bnez s0, 254 # CHECK-ALIASOBJ32: bnez s0, 0x12a # CHECK-ALIASOBJ64: bnez s0, 0x12a @@ -174,7 +174,7 @@ beq zero, s0, -256 # CHECK: # encoding: [0x7d,0xec] bne s0, zero, 254 -# CHECK-BYTES: 7d ec +# CHECK-BYTES: ec7d # CHECK-ALIASASM: bnez s0, 254 # CHECK-ALIASOBJ32: bnez s0, 0x12c # CHECK-ALIASOBJ64: bnez s0, 0x12c @@ -184,67 +184,67 @@ bne s0, zero, 254 # CHECK: # encoding: [0x7d,0xec] bne zero, s0, 254 -# CHECK-BYTES: 7e 04 +# CHECK-BYTES: 047e # CHECK-ALIAS: slli s0, s0, 31 # CHECK-INST: c.slli s0, 31 # CHECK: # encoding: [0x7e,0x04] slli s0, s0, 31 -# CHECK-BYTES: fe 50 +# CHECK-BYTES: 50fe # CHECK-ALIAS: lw ra, 252(sp) # CHECK-INST: c.lwsp ra, 252(sp) # CHECK: # encoding: [0xfe,0x50] lw ra, 252(sp) -# CHECK-BYTES: 82 80 +# CHECK-BYTES: 8082 # CHECK-ALIAS: ret # CHECK-INST: c.jr ra # CHECK: # encoding: [0x82,0x80] jalr zero, 0(ra) -# CHECK-BYTES: 92 80 +# CHECK-BYTES: 8092 # CHECK-ALIAS: mv ra, tp # CHECK-INST: c.mv ra, tp # CHECK: # encoding: [0x92,0x80] add ra, zero, tp -# CHECK-BYTES: 92 80 +# CHECK-BYTES: 8092 # CHECK-ALIAS: mv ra, tp # CHECK-INST: c.mv ra, tp # CHECK: # encoding: [0x92,0x80] add ra, tp, zero -# CHECK-BYTES: 02 90 +# CHECK-BYTES: 9002 # CHECK-ALIAS: ebreak # CHECK-INST: c.ebreak # CHECK: # encoding: [0x02,0x90] ebreak -# CHECK-BYTES: 02 94 +# CHECK-BYTES: 9402 # CHECK-ALIAS: jalr s0 # CHECK-INST: c.jalr s0 # CHECK: # encoding: [0x02,0x94] jalr ra, 0(s0) -# CHECK-BYTES: 3e 94 +# CHECK-BYTES: 943e # CHECK-ALIAS: add s0, s0, a5 # CHECK-INST: c.add s0, a5 # CHECK: # encoding: [0x3e,0x94] add s0, a5, s0 -# CHECK-BYTES: 3e 94 +# CHECK-BYTES: 943e # CHECK-ALIAS: add s0, s0, a5 # CHECK-INST: c.add s0, a5 # CHECK: # encoding: [0x3e,0x94] add s0, s0, a5 -# CHECK-BYTES: 82 df +# CHECK-BYTES: df82 # CHECK-ALIAS: sw zero, 252(sp) # CHECK-INST: c.swsp zero, 252(sp) # CHECK: # encoding: [0x82,0xdf] sw zero, 252(sp) -# CHECK-BYTES: 00 00 +# CHECK-BYTES: 0000 # CHECK-ALIAS: unimp # CHECK-INST: c.unimp # CHECK: # encoding: [0x00,0x00] diff --git a/llvm/test/MC/RISCV/compress-rv64i.s b/llvm/test/MC/RISCV/compress-rv64i.s index 55d24f0d41c0..ab5b24307cd1 100644 --- a/llvm/test/MC/RISCV/compress-rv64i.s +++ b/llvm/test/MC/RISCV/compress-rv64i.s @@ -11,49 +11,49 @@ # Tests compressed instructions available in rv64 and not in rv32. -# CHECK-BYTES: e0 7f +# CHECK-BYTES: 7fe0 # CHECK-ALIAS: ld s0, 248(a5) # CHECK-INST: c.ld s0, 248(a5) # CHECK: # encoding: [0xe0,0x7f] ld s0, 248(a5) -# CHECK-BYTES: a0 e3 +# CHECK-BYTES: e3a0 # CHECK-ALIAS: sd s0, 64(a5) # CHECK-INST: c.sd s0, 64(a5) # CHECK: # encoding: [0xa0,0xe3] sd s0, 64(a5) -# CHECK-BYTES: 7d 22 +# CHECK-BYTES: 227d # CHEACK-ALIAS: addiw tp, tp, 31 # CHECK-INST: c.addiw tp, 31 # CHECK: # encoding: [0x7d,0x22] addiw tp, tp, 31 -# CHECK-BYTES: 1d 9c +# CHECK-BYTES: 9c1d # CHEACK-ALIAS: subw s0, s0, a5 # CHECK-INST: c.subw s0, a5 # CHECK: # encoding: [0x1d,0x9c] subw s0, s0, a5 -# CHECK-BYTES: 3d 9c +# CHECK-BYTES: 9c3d # CHECK-ALIAS: addw s0, s0, a5 # CHECK-INST: c.addw s0, a5 # CHECK: # encoding: [0x3d,0x9c] addw s0, s0, a5 -# CHECK-BYTES: 3d 9c +# CHECK-BYTES: 9c3d # CHECK-ALIAS: addw s0, s0, a5 # CHECK-INST: c.addw s0, a5 # CHECK: # encoding: [0x3d,0x9c] addw s0, a5, s0 -# CHECK-BYTES: ee 70 +# CHECK-BYTES: 70ee # CHECK-ALIAS: ld ra, 248(sp) # CHECK-INST: c.ldsp ra, 248(sp) # CHECK: # encoding: [0xee,0x70] ld ra, 248(sp) -# CHECK-BYTES: a2 e0 +# CHECK-BYTES: e0a2 # CHECK-ALIAS: sd s0, 64(sp) # CHECK-INST: c.sdsp s0, 64(sp) # CHECK: # encoding: [0xa2,0xe0] diff --git a/llvm/test/MC/RISCV/nop-slide.s b/llvm/test/MC/RISCV/nop-slide.s index f280d6e521e3..4dc888b3ba77 100644 --- a/llvm/test/MC/RISCV/nop-slide.s +++ b/llvm/test/MC/RISCV/nop-slide.s @@ -10,18 +10,18 @@ auipc a0, 0 # CHECK-RVC-NORELAX: 0000000000000000 <.text>: -# CHECK-RVC-NORELAX-NEXT: 0: 00 00 unimp -# CHECK-RVC-NORELAX-NEXT: 2: 01 00 nop -# CHECK-RVC-NORELAX-NEXT: 4: 17 05 00 00 auipc a0, 0x0 +# CHECK-RVC-NORELAX-NEXT: 0: 0000 unimp +# CHECK-RVC-NORELAX-NEXT: 2: 0001 nop +# CHECK-RVC-NORELAX-NEXT: 4: 00000517 auipc a0, 0x0 # CHECK-RVC-RELAX: 0000000000000000 <.text>: -# CHECK-RVC-RELAX-NEXT: 0: 01 00 nop -# CHECK-RVC-RELAX-NEXT: 2: 00 01 addi s0, sp, 0x80 -# CHECK-RVC-RELAX-NEXT: 4: 00 17 addi s0, sp, 0x3a0 -# CHECK-RVC-RELAX-NEXT: 6: 05 00 c.nop 0x1 -# CHECK-RVC-RELAX-NEXT: 8: 00 +# CHECK-RVC-RELAX-NEXT: 0: 0001 nop +# CHECK-RVC-RELAX-NEXT: 2: 0100 addi s0, sp, 0x80 +# CHECK-RVC-RELAX-NEXT: 4: 1700 addi s0, sp, 0x3a0 +# CHECK-RVC-RELAX-NEXT: 6: 0005 c.nop 0x1 +# CHECK-RVC-RELAX-NEXT: 8: 00 # CHECK: 0000000000000000 <.text>: -# CHECK-NEXT: 0: 00 00 -# CHECK-NEXT: 2: 00 00 -# CHECK-NEXT: 4: 17 05 00 00 auipc a0, 0x0 +# CHECK-NEXT: 0: 0000 +# CHECK-NEXT: 2: 0000 +# CHECK-NEXT: 4: 00000517 auipc a0, 0x0 diff --git a/llvm/test/MC/RISCV/option-pushpop.s b/llvm/test/MC/RISCV/option-pushpop.s index c830d16e590b..9c61b5dab5f3 100644 --- a/llvm/test/MC/RISCV/option-pushpop.s +++ b/llvm/test/MC/RISCV/option-pushpop.s @@ -25,7 +25,7 @@ call foo # CHECK-INST: addi s0, sp, 1020 -# CHECK-BYTES: 13 04 c1 3f +# CHECK-BYTES: 3fc10413 # CHECK-ALIAS: addi s0, sp, 1020 addi s0, sp, 1020 @@ -45,14 +45,14 @@ call bar .option rvc # CHECK-INST: .option rvc # CHECK-INST: c.addi4spn s0, sp, 1020 -# CHECK-BYTES: e0 1f +# CHECK-BYTES: 1fe0 # CHECK-ALIAS: addi s0, sp, 1020 addi s0, sp, 1020 .option pop # Pop relax=true, rvc=false # CHECK-INST: .option pop # CHECK-INST: addi s0, sp, 1020 -# CHECK-BYTES: 13 04 c1 3f +# CHECK-BYTES: 3fc10413 # CHECK-ALIAS: addi s0, sp, 1020 addi s0, sp, 1020 @@ -69,7 +69,7 @@ call bar call baz # CHECK-INST: addi s0, sp, 1020 -# CHECK-BYTES: 13 04 c1 3f +# CHECK-BYTES: 3fc10413 # CHECK-ALIAS: addi s0, sp, 1020 addi s0, sp, 1020 diff --git a/llvm/test/MC/RISCV/option-rvc.s b/llvm/test/MC/RISCV/option-rvc.s index 00c8ea167bcd..894fbab562d7 100644 --- a/llvm/test/MC/RISCV/option-rvc.s +++ b/llvm/test/MC/RISCV/option-rvc.s @@ -20,13 +20,13 @@ # RUN: | llvm-objdump --triple=riscv64 --mattr=+c --no-print-imm-hex -d -M no-aliases - \ # RUN: | FileCheck -check-prefixes=CHECK-BYTES,CHECK-INST %s -# CHECK-BYTES: 13 85 05 00 +# CHECK-BYTES: 00058513 # CHECK-ALIAS: mv a0, a1 # CHECK-INST: addi a0, a1, 0 # CHECK: # encoding: [0x13,0x85,0x05,0x00] addi a0, a1, 0 -# CHECK-BYTES: 13 04 c1 3f +# CHECK-BYTES: 3fc10413 # CHECK-ALIAS: addi s0, sp, 1020 # CHECK-INST: addi s0, sp, 1020 # CHECK: # encoding: [0x13,0x04,0xc1,0x3f] @@ -35,13 +35,13 @@ addi s0, sp, 1020 # CHECK: .option rvc .option rvc -# CHECK-BYTES: 2e 85 +# CHECK-BYTES: 852e # CHECK-ALIAS: mv a0, a1 # CHECK-INST: c.mv a0, a1 # CHECK: # encoding: [0x2e,0x85] addi a0, a1, 0 -# CHECK-BYTES: e0 1f +# CHECK-BYTES: 1fe0 # CHECK-ALIAS: addi s0, sp, 1020 # CHECK-INST: c.addi4spn s0, sp, 1020 # CHECK: # encoding: [0xe0,0x1f] @@ -49,13 +49,13 @@ addi s0, sp, 1020 # CHECK: .option norvc .option norvc -# CHECK-BYTES: 13 85 05 00 +# CHECK-BYTES: 00058513 # CHECK-ALIAS: mv a0, a1 # CHECK-INST: addi a0, a1, 0 # CHECK: # encoding: [0x13,0x85,0x05,0x00] addi a0, a1, 0 -# CHECK-BYTES: 13 04 c1 3f +# CHECK-BYTES: 3fc10413 # CHECK-ALIAS: addi s0, sp, 1020 # CHECK-INST: addi s0, sp, 1020 # CHECK: # encoding: [0x13,0x04,0xc1,0x3f] @@ -63,13 +63,13 @@ addi s0, sp, 1020 # CHECK: .option rvc .option rvc -# CHECK-BYTES: 2e 85 +# CHECK-BYTES: 852e # CHECK-ALIAS: mv a0, a1 # CHECK-INST: c.mv a0, a1 # CHECK: # encoding: [0x2e,0x85] addi a0, a1, 0 -# CHECK-BYTES: e0 1f +# CHECK-BYTES: 1fe0 # CHECK-ALIAS: addi s0, sp, 1020 # CHECK-INST: c.addi4spn s0, sp, 1020 # CHECK: # encoding: [0xe0,0x1f] @@ -77,13 +77,13 @@ addi s0, sp, 1020 # CHECK: .option norvc .option norvc -# CHECK-BYTES: 13 85 05 00 +# CHECK-BYTES: 00058513 # CHECK-ALIAS: mv a0, a1 # CHECK-INST: addi a0, a1, 0 # CHECK: # encoding: [0x13,0x85,0x05,0x00] addi a0, a1, 0 -# CHECK-BYTES: 13 04 c1 3f +# CHECK-BYTES: 3fc10413 # CHECK-ALIAS: addi s0, sp, 1020 # CHECK-INST: addi s0, sp, 1020 # CHECK: # encoding: [0x13,0x04,0xc1,0x3f] diff --git a/llvm/test/MC/RISCV/rv32e-invalid.s b/llvm/test/MC/RISCV/rv32e-invalid.s index 9c19d3f40bcf..95dc156f250a 100644 --- a/llvm/test/MC/RISCV/rv32e-invalid.s +++ b/llvm/test/MC/RISCV/rv32e-invalid.s @@ -11,100 +11,100 @@ # are rejected for RV32E/RV64E, when both assembling and disassembling. -# CHECK-DIS: 37 18 00 00 +# CHECK-DIS: 00001837 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x16, 1 -# CHECK-DIS: b7 28 00 00 +# CHECK-DIS: 000028b7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x17, 2 -# CHECK-DIS: 37 39 00 00 +# CHECK-DIS: 00003937 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x18, 3 -# CHECK-DIS: b7 49 00 00 +# CHECK-DIS: 000049b7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x19, 4 -# CHECK-DIS: 37 5a 00 00 +# CHECK-DIS: 00005a37 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x20, 5 -# CHECK-DIS: b7 6a 00 00 +# CHECK-DIS: 00006ab7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x21, 6 -# CHECK-DIS: 37 7b 00 00 +# CHECK-DIS: 00007b37 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x22, 7 -# CHECK-DIS: b7 8b 00 00 +# CHECK-DIS: 00008bb7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x23, 8 -# CHECK-DIS: 37 9c 00 00 +# CHECK-DIS: 00009c37 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x24, 9 -# CHECK-DIS: b7 ac 00 00 +# CHECK-DIS: 0000acb7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x25, 10 -# CHECK-DIS: 37 bd 00 00 +# CHECK-DIS: 0000bd37 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x26, 11 -# CHECK-DIS: b7 cd 00 00 +# CHECK-DIS: 0000cdb7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x27, 12 -# CHECK-DIS: 37 de 00 00 +# CHECK-DIS: 0000de37 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x28, 13 -# CHECK-DIS: b7 ee 00 00 +# CHECK-DIS: 0000eeb7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x29, 14 -# CHECK-DIS: 37 ff 00 00 +# CHECK-DIS: 0000ff37 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x30, 15 -# CHECK-DIS: b7 0f 01 00 +# CHECK-DIS: 00010fb7 # CHECK: :[[@LINE+1]]:5: error: invalid operand for instruction lui x31, 16 -# CHECK-DIS: 17 18 01 00 +# CHECK-DIS: 00011817 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc a6, 17 -# CHECK-DIS: 97 28 01 00 +# CHECK-DIS: 00012897 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc a7, 18 -# CHECK-DIS: 17 39 01 00 +# CHECK-DIS: 00013917 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s2, 19 -# CHECK-DIS: 97 49 01 00 +# CHECK-DIS: 00014997 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s3, 20 -# CHECK-DIS: 17 5a 01 00 +# CHECK-DIS: 00015a17 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s4, 21 -# CHECK-DIS: 97 6a 01 00 +# CHECK-DIS: 00016a97 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s5, 22 -# CHECK-DIS: 17 7b 01 00 +# CHECK-DIS: 00017b17 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s6, 23 -# CHECK-DIS: 97 8b 01 00 +# CHECK-DIS: 00018b97 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s7, 24 -# CHECK-DIS: 17 9c 01 00 +# CHECK-DIS: 00019c17 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s8, 25 -# CHECK-DIS: 97 ac 01 00 +# CHECK-DIS: 0001ac97 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s9, 26 -# CHECK-DIS: 17 bd 01 00 +# CHECK-DIS: 0001bd17 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s10, 27 -# CHECK-DIS: 97 cd 01 00 +# CHECK-DIS: 0001cd97 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc s11, 28 -# CHECK-DIS: 17 de 01 00 +# CHECK-DIS: 0001de17 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc t3, 29 -# CHECK-DIS: 97 ee 01 00 +# CHECK-DIS: 0001ee97 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc t4, 30 -# CHECK-DIS: 17 ff 01 00 +# CHECK-DIS: 0001ff17 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc t5, 31 -# CHECK-DIS: 97 0f 02 00 +# CHECK-DIS: 00020f97 # CHECK: :[[@LINE+1]]:7: error: invalid operand for instruction auipc t6, 32 diff --git a/llvm/test/MC/RISCV/rvv/add.s b/llvm/test/MC/RISCV/rvv/add.s index 89cef5dc0a4c..ebfe50f2d958 100644 --- a/llvm/test/MC/RISCV/rvv/add.s +++ b/llvm/test/MC/RISCV/rvv/add.s @@ -12,352 +12,352 @@ vadd.vv v8, v4, v20, v0.t # CHECK-INST: vadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 00 +# CHECK-UNKNOWN: 004a0457 vadd.vv v8, v4, v20 # CHECK-INST: vadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 02 +# CHECK-UNKNOWN: 024a0457 vadd.vx v8, v4, a0, v0.t # CHECK-INST: vadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 00 +# CHECK-UNKNOWN: 00454457 vadd.vx v8, v4, a0 # CHECK-INST: vadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 02 +# CHECK-UNKNOWN: 02454457 vadd.vi v8, v4, 15, v0.t # CHECK-INST: vadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 00 +# CHECK-UNKNOWN: 0047b457 vadd.vi v8, v4, 15 # CHECK-INST: vadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 02 +# CHECK-UNKNOWN: 0247b457 vwaddu.vv v8, v4, v20, v0.t # CHECK-INST: vwaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a c0 +# CHECK-UNKNOWN: c04a2457 vwaddu.vv v8, v4, v20 # CHECK-INST: vwaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a c2 +# CHECK-UNKNOWN: c24a2457 vwaddu.vx v8, v4, a0, v0.t # CHECK-INST: vwaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 c0 +# CHECK-UNKNOWN: c0456457 vwaddu.vx v8, v4, a0 # CHECK-INST: vwaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 c2 +# CHECK-UNKNOWN: c2456457 vwadd.vv v8, v4, v20, v0.t # CHECK-INST: vwadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a c4 +# CHECK-UNKNOWN: c44a2457 vwadd.vv v8, v4, v20 # CHECK-INST: vwadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a c6 +# CHECK-UNKNOWN: c64a2457 vwadd.vx v8, v4, a0, v0.t # CHECK-INST: vwadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 c4 +# CHECK-UNKNOWN: c4456457 vwadd.vx v8, v4, a0 # CHECK-INST: vwadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 c6 +# CHECK-UNKNOWN: c6456457 vwaddu.wv v8, v4, v20, v0.t # CHECK-INST: vwaddu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a d0 +# CHECK-UNKNOWN: d04a2457 vwaddu.wv v8, v4, v20 # CHECK-INST: vwaddu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a d2 +# CHECK-UNKNOWN: d24a2457 vwaddu.wx v8, v4, a0, v0.t # CHECK-INST: vwaddu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 d0 +# CHECK-UNKNOWN: d0456457 vwaddu.wx v8, v4, a0 # CHECK-INST: vwaddu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 d2 +# CHECK-UNKNOWN: d2456457 vwadd.wv v8, v4, v20, v0.t # CHECK-INST: vwadd.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a d4 +# CHECK-UNKNOWN: d44a2457 vwadd.wv v8, v4, v20 # CHECK-INST: vwadd.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xd6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a d6 +# CHECK-UNKNOWN: d64a2457 vwadd.wx v8, v4, a0, v0.t # CHECK-INST: vwadd.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 d4 +# CHECK-UNKNOWN: d4456457 vwadd.wx v8, v4, a0 # CHECK-INST: vwadd.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xd6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 d6 +# CHECK-UNKNOWN: d6456457 vadc.vvm v8, v4, v20, v0 # CHECK-INST: vadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 40 +# CHECK-UNKNOWN: 404a0457 vadc.vvm v4, v4, v20, v0 # CHECK-INST: vadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 02 4a 40 +# CHECK-UNKNOWN: 404a0257 vadc.vvm v8, v4, v8, v0 # CHECK-INST: vadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 44 40 +# CHECK-UNKNOWN: 40440457 vadc.vxm v8, v4, a0, v0 # CHECK-INST: vadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 40 +# CHECK-UNKNOWN: 40454457 vadc.vim v8, v4, 15, v0 # CHECK-INST: vadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 40 +# CHECK-UNKNOWN: 4047b457 vmadc.vvm v8, v4, v20, v0 # CHECK-INST: vmadc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 44 +# CHECK-UNKNOWN: 444a0457 vmadc.vvm v4, v4, v20, v0 # CHECK-INST: vmadc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 02 4a 44 +# CHECK-UNKNOWN: 444a0257 vmadc.vvm v8, v4, v8, v0 # CHECK-INST: vmadc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 44 44 +# CHECK-UNKNOWN: 44440457 vmadc.vxm v8, v4, a0, v0 # CHECK-INST: vmadc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 44 +# CHECK-UNKNOWN: 44454457 vmadc.vim v8, v4, 15, v0 # CHECK-INST: vmadc.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 44 +# CHECK-UNKNOWN: 4447b457 vmadc.vv v8, v4, v20 # CHECK-INST: vmadc.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 46 +# CHECK-UNKNOWN: 464a0457 vmadc.vx v8, v4, a0 # CHECK-INST: vmadc.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 46 +# CHECK-UNKNOWN: 46454457 vmadc.vi v8, v4, 15 # CHECK-INST: vmadc.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 46 +# CHECK-UNKNOWN: 4647b457 vsaddu.vv v8, v4, v20, v0.t # CHECK-INST: vsaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 80 +# CHECK-UNKNOWN: 804a0457 vsaddu.vv v8, v4, v20 # CHECK-INST: vsaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 82 +# CHECK-UNKNOWN: 824a0457 vsaddu.vx v8, v4, a0, v0.t # CHECK-INST: vsaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 80 +# CHECK-UNKNOWN: 80454457 vsaddu.vx v8, v4, a0 # CHECK-INST: vsaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 82 +# CHECK-UNKNOWN: 82454457 vsaddu.vi v8, v4, 15, v0.t # CHECK-INST: vsaddu.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 80 +# CHECK-UNKNOWN: 8047b457 vsaddu.vi v8, v4, 15 # CHECK-INST: vsaddu.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 82 +# CHECK-UNKNOWN: 8247b457 vsadd.vv v8, v4, v20, v0.t # CHECK-INST: vsadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 84 +# CHECK-UNKNOWN: 844a0457 vsadd.vv v8, v4, v20 # CHECK-INST: vsadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 86 +# CHECK-UNKNOWN: 864a0457 vsadd.vx v8, v4, a0, v0.t # CHECK-INST: vsadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 84 +# CHECK-UNKNOWN: 84454457 vsadd.vx v8, v4, a0 # CHECK-INST: vsadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 86 +# CHECK-UNKNOWN: 86454457 vsadd.vi v8, v4, 15, v0.t # CHECK-INST: vsadd.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 84 +# CHECK-UNKNOWN: 8447b457 vsadd.vi v8, v4, 15 # CHECK-INST: vsadd.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 86 +# CHECK-UNKNOWN: 8647b457 vaadd.vv v8, v4, v20, v0.t # CHECK-INST: vaadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 24 +# CHECK-UNKNOWN: 244a2457 vaadd.vv v8, v4, v20 # CHECK-INST: vaadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 26 +# CHECK-UNKNOWN: 264a2457 vaadd.vx v8, v4, a0, v0.t # CHECK-INST: vaadd.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 24 +# CHECK-UNKNOWN: 24456457 vaadd.vx v8, v4, a0 # CHECK-INST: vaadd.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 26 +# CHECK-UNKNOWN: 26456457 vaaddu.vv v8, v4, v20, v0.t # CHECK-INST: vaaddu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 20 +# CHECK-UNKNOWN: 204a2457 vaaddu.vv v8, v4, v20 # CHECK-INST: vaaddu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 22 +# CHECK-UNKNOWN: 224a2457 vaaddu.vx v8, v4, a0, v0.t # CHECK-INST: vaaddu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 20 +# CHECK-UNKNOWN: 20456457 vaaddu.vx v8, v4, a0 # CHECK-INST: vaaddu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 22 +# CHECK-UNKNOWN: 22456457 vwcvt.x.x.v v8, v4, v0.t # CHECK-INST: vwcvt.x.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x40,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 40 c4 +# CHECK-UNKNOWN: c4406457 vwcvt.x.x.v v8, v4 # CHECK-INST: vwcvt.x.x.v v8, v4 # CHECK-ENCODING: [0x57,0x64,0x40,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 40 c6 +# CHECK-UNKNOWN: c6406457 vwcvtu.x.x.v v8, v4, v0.t # CHECK-INST: vwcvtu.x.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x40,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 40 c0 +# CHECK-UNKNOWN: c0406457 vwcvtu.x.x.v v8, v4 # CHECK-INST: vwcvtu.x.x.v v8, v4 # CHECK-ENCODING: [0x57,0x64,0x40,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 40 c2 +# CHECK-UNKNOWN: c2406457 diff --git a/llvm/test/MC/RISCV/rvv/and.s b/llvm/test/MC/RISCV/rvv/and.s index 894263fe0152..b1182c175a5d 100644 --- a/llvm/test/MC/RISCV/rvv/and.s +++ b/llvm/test/MC/RISCV/rvv/and.s @@ -12,34 +12,34 @@ vand.vv v8, v4, v20, v0.t # CHECK-INST: vand.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 24 +# CHECK-UNKNOWN: 244a0457 vand.vv v8, v4, v20 # CHECK-INST: vand.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 26 +# CHECK-UNKNOWN: 264a0457 vand.vx v8, v4, a0, v0.t # CHECK-INST: vand.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 24 +# CHECK-UNKNOWN: 24454457 vand.vx v8, v4, a0 # CHECK-INST: vand.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 26 +# CHECK-UNKNOWN: 26454457 vand.vi v8, v4, 15, v0.t # CHECK-INST: vand.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 24 +# CHECK-UNKNOWN: 2447b457 vand.vi v8, v4, 15 # CHECK-INST: vand.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 26 +# CHECK-UNKNOWN: 2647b457 diff --git a/llvm/test/MC/RISCV/rvv/clip.s b/llvm/test/MC/RISCV/rvv/clip.s index f4fb2c576b30..70c23d8ec0b1 100644 --- a/llvm/test/MC/RISCV/rvv/clip.s +++ b/llvm/test/MC/RISCV/rvv/clip.s @@ -12,70 +12,70 @@ vnclipu.wv v8, v4, v20, v0.t # CHECK-INST: vnclipu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a b8 +# CHECK-UNKNOWN: b84a0457 vnclipu.wv v8, v4, v20 # CHECK-INST: vnclipu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xba] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a ba +# CHECK-UNKNOWN: ba4a0457 vnclipu.wx v8, v4, a0, v0.t # CHECK-INST: vnclipu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 b8 +# CHECK-UNKNOWN: b8454457 vnclipu.wx v8, v4, a0 # CHECK-INST: vnclipu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xba] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 ba +# CHECK-UNKNOWN: ba454457 vnclipu.wi v8, v4, 31, v0.t # CHECK-INST: vnclipu.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f b8 +# CHECK-UNKNOWN: b84fb457 vnclipu.wi v8, v4, 31 # CHECK-INST: vnclipu.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xba] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f ba +# CHECK-UNKNOWN: ba4fb457 vnclip.wv v8, v4, v20, v0.t # CHECK-INST: vnclip.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xbc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a bc +# CHECK-UNKNOWN: bc4a0457 vnclip.wv v8, v4, v20 # CHECK-INST: vnclip.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xbe] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a be +# CHECK-UNKNOWN: be4a0457 vnclip.wx v8, v4, a0, v0.t # CHECK-INST: vnclip.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xbc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 bc +# CHECK-UNKNOWN: bc454457 vnclip.wx v8, v4, a0 # CHECK-INST: vnclip.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xbe] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 be +# CHECK-UNKNOWN: be454457 vnclip.wi v8, v4, 31, v0.t # CHECK-INST: vnclip.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f bc +# CHECK-UNKNOWN: bc4fb457 vnclip.wi v8, v4, 31 # CHECK-INST: vnclip.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xbe] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f be +# CHECK-UNKNOWN: be4fb457 diff --git a/llvm/test/MC/RISCV/rvv/compare.s b/llvm/test/MC/RISCV/rvv/compare.s index fe7c1144a3c0..b1b9518a1d5a 100644 --- a/llvm/test/MC/RISCV/rvv/compare.s +++ b/llvm/test/MC/RISCV/rvv/compare.s @@ -12,367 +12,367 @@ vmslt.vv v0, v4, v20, v0.t # CHECK-INST: vmslt.vv v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x00,0x4a,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 00 4a 6c +# CHECK-UNKNOWN: 6c4a0057 vmseq.vv v8, v4, v20, v0.t # CHECK-INST: vmseq.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 60 +# CHECK-UNKNOWN: 604a0457 vmseq.vv v8, v4, v20 # CHECK-INST: vmseq.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 62 +# CHECK-UNKNOWN: 624a0457 vmseq.vx v8, v4, a0, v0.t # CHECK-INST: vmseq.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 60 +# CHECK-UNKNOWN: 60454457 vmseq.vx v8, v4, a0 # CHECK-INST: vmseq.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 62 +# CHECK-UNKNOWN: 62454457 vmseq.vi v8, v4, 15, v0.t # CHECK-INST: vmseq.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 60 +# CHECK-UNKNOWN: 6047b457 vmseq.vi v8, v4, 15 # CHECK-INST: vmseq.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 62 +# CHECK-UNKNOWN: 6247b457 vmsne.vv v8, v4, v20, v0.t # CHECK-INST: vmsne.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 64 +# CHECK-UNKNOWN: 644a0457 vmsne.vv v8, v4, v20 # CHECK-INST: vmsne.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 66 +# CHECK-UNKNOWN: 664a0457 vmsne.vx v8, v4, a0, v0.t # CHECK-INST: vmsne.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 64 +# CHECK-UNKNOWN: 64454457 vmsne.vx v8, v4, a0 # CHECK-INST: vmsne.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 66 +# CHECK-UNKNOWN: 66454457 vmsne.vi v8, v4, 15, v0.t # CHECK-INST: vmsne.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 64 +# CHECK-UNKNOWN: 6447b457 vmsne.vi v8, v4, 15 # CHECK-INST: vmsne.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 66 +# CHECK-UNKNOWN: 6647b457 vmsltu.vv v8, v4, v20, v0.t # CHECK-INST: vmsltu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 68 +# CHECK-UNKNOWN: 684a0457 vmsltu.vv v8, v4, v20 # CHECK-INST: vmsltu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 6a +# CHECK-UNKNOWN: 6a4a0457 vmsltu.vx v8, v4, a0, v0.t # CHECK-INST: vmsltu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 68 +# CHECK-UNKNOWN: 68454457 vmsltu.vx v8, v4, a0 # CHECK-INST: vmsltu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 6a +# CHECK-UNKNOWN: 6a454457 vmslt.vv v8, v4, v20, v0.t # CHECK-INST: vmslt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 6c +# CHECK-UNKNOWN: 6c4a0457 vmslt.vv v8, v4, v20 # CHECK-INST: vmslt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 6e +# CHECK-UNKNOWN: 6e4a0457 vmslt.vx v8, v4, a0, v0.t # CHECK-INST: vmslt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 6c +# CHECK-UNKNOWN: 6c454457 vmslt.vx v8, v4, a0 # CHECK-INST: vmslt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 6e +# CHECK-UNKNOWN: 6e454457 vmsleu.vv v8, v4, v20, v0.t # CHECK-INST: vmsleu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x70] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 70 +# CHECK-UNKNOWN: 704a0457 vmsleu.vv v8, v4, v20 # CHECK-INST: vmsleu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x72] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 72 +# CHECK-UNKNOWN: 724a0457 vmsleu.vx v8, v4, a0, v0.t # CHECK-INST: vmsleu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x70] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 70 +# CHECK-UNKNOWN: 70454457 vmsleu.vx v8, v4, a0 # CHECK-INST: vmsleu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x72] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 72 +# CHECK-UNKNOWN: 72454457 vmsleu.vi v8, v4, 15, v0.t # CHECK-INST: vmsleu.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x70] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 70 +# CHECK-UNKNOWN: 7047b457 vmsleu.vi v8, v4, 15 # CHECK-INST: vmsleu.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x72] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 72 +# CHECK-UNKNOWN: 7247b457 vmsle.vv v8, v4, v20, v0.t # CHECK-INST: vmsle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x74] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 74 +# CHECK-UNKNOWN: 744a0457 vmsle.vv v8, v4, v20 # CHECK-INST: vmsle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 76 +# CHECK-UNKNOWN: 764a0457 vmsle.vx v8, v4, a0, v0.t # CHECK-INST: vmsle.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x74] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 74 +# CHECK-UNKNOWN: 74454457 vmsle.vx v8, v4, a0 # CHECK-INST: vmsle.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 76 +# CHECK-UNKNOWN: 76454457 vmsle.vi v8, v4, 15, v0.t # CHECK-INST: vmsle.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x74] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 74 +# CHECK-UNKNOWN: 7447b457 vmsle.vi v8, v4, 15 # CHECK-INST: vmsle.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 76 +# CHECK-UNKNOWN: 7647b457 vmsgtu.vx v8, v4, a0, v0.t # CHECK-INST: vmsgtu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x78] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 78 +# CHECK-UNKNOWN: 78454457 vmsgtu.vx v8, v4, a0 # CHECK-INST: vmsgtu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 7a +# CHECK-UNKNOWN: 7a454457 vmsgtu.vi v8, v4, 15, v0.t # CHECK-INST: vmsgtu.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x78] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 78 +# CHECK-UNKNOWN: 7847b457 vmsgtu.vi v8, v4, 15 # CHECK-INST: vmsgtu.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 7a +# CHECK-UNKNOWN: 7a47b457 vmsgt.vx v8, v4, a0, v0.t # CHECK-INST: vmsgt.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x7c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 7c +# CHECK-UNKNOWN: 7c454457 vmsgt.vx v8, v4, a0 # CHECK-INST: vmsgt.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x7e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 7e +# CHECK-UNKNOWN: 7e454457 vmsgt.vi v8, v4, 15, v0.t # CHECK-INST: vmsgt.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 7c +# CHECK-UNKNOWN: 7c47b457 vmsgt.vi v8, v4, 15 # CHECK-INST: vmsgt.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 7e +# CHECK-UNKNOWN: 7e47b457 vmsgtu.vv v8, v20, v4, v0.t # CHECK-INST: vmsltu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 68 +# CHECK-UNKNOWN: 684a0457 vmsgtu.vv v8, v20, v4 # CHECK-INST: vmsltu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 6a +# CHECK-UNKNOWN: 6a4a0457 vmsgt.vv v8, v20, v4, v0.t # CHECK-INST: vmslt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 6c +# CHECK-UNKNOWN: 6c4a0457 vmsgt.vv v8, v20, v4 # CHECK-INST: vmslt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 6e +# CHECK-UNKNOWN: 6e4a0457 vmsgeu.vv v8, v20, v4, v0.t # CHECK-INST: vmsleu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x70] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 70 +# CHECK-UNKNOWN: 704a0457 vmsgeu.vv v8, v20, v4 # CHECK-INST: vmsleu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x72] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 72 +# CHECK-UNKNOWN: 724a0457 vmsge.vv v8, v20, v4, v0.t # CHECK-INST: vmsle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x74] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 74 +# CHECK-UNKNOWN: 744a0457 vmsge.vv v8, v20, v4 # CHECK-INST: vmsle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 76 +# CHECK-UNKNOWN: 764a0457 vmsltu.vi v8, v4, 16, v0.t # CHECK-INST: vmsleu.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x70] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 70 +# CHECK-UNKNOWN: 7047b457 vmsltu.vi v8, v4, 16 # CHECK-INST: vmsleu.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x72] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 72 +# CHECK-UNKNOWN: 7247b457 vmsltu.vi v8, v4, 0, v0.t # CHECK-INST: vmsne.vv v8, v4, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x42,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 42 64 +# CHECK-UNKNOWN: 64420457 vmsltu.vi v8, v4, 0 # CHECK-INST: vmsne.vv v8, v4, v4 # CHECK-ENCODING: [0x57,0x04,0x42,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 42 66 +# CHECK-UNKNOWN: 66420457 vmslt.vi v8, v4, 16, v0.t # CHECK-INST: vmsle.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x74] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 74 +# CHECK-UNKNOWN: 7447b457 vmslt.vi v8, v4, 16 # CHECK-INST: vmsle.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 76 +# CHECK-UNKNOWN: 7647b457 vmsgeu.vi v8, v4, 16, v0.t # CHECK-INST: vmsgtu.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x78] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 78 +# CHECK-UNKNOWN: 7847b457 vmsgeu.vi v8, v4, 16 # CHECK-INST: vmsgtu.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x7a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 7a +# CHECK-UNKNOWN: 7a47b457 vmsgeu.vi v8, v4, 0, v0.t # CHECK-INST: vmseq.vv v8, v4, v4, v0.t # CHECK-ENCODING: [0x57,0x04,0x42,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 42 60 +# CHECK-UNKNOWN: 60420457 vmsgeu.vi v8, v4, 0 # CHECK-INST: vmseq.vv v8, v4, v4 # CHECK-ENCODING: [0x57,0x04,0x42,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 42 62 +# CHECK-UNKNOWN: 62420457 vmsge.vi v8, v4, 16, v0.t # CHECK-INST: vmsgt.vi v8, v4, 0xf, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x7c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 7c +# CHECK-UNKNOWN: 7c47b457 vmsge.vi v8, v4, 16 # CHECK-INST: vmsgt.vi v8, v4, 0xf # CHECK-ENCODING: [0x57,0xb4,0x47,0x7e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 7e +# CHECK-UNKNOWN: 7e47b457 vmsgeu.vx v8, v4, a0 # CHECK-INST: vmsltu.vx v8, v4, a0 @@ -380,8 +380,8 @@ vmsgeu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6a] # CHECK-ENCODING: [0x57,0x24,0x84,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 6a -# CHECK-UNKNOWN: 57 24 84 76 +# CHECK-UNKNOWN: 6a454457 +# CHECK-UNKNOWN: 76842457 vmsge.vx v0, v4, a0 # CHECK-INST: vmslt.vx v0, v4, a0 @@ -389,8 +389,8 @@ vmsge.vx v0, v4, a0 # CHECK-ENCODING: [0x57,0x40,0x45,0x6e] # CHECK-ENCODING: [0x57,0x20,0x00,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 40 45 6e -# CHECK-UNKNOWN: 57 20 00 76 +# CHECK-UNKNOWN: 6e454057 +# CHECK-UNKNOWN: 76002057 vmsge.vx v8, v4, a0 # CHECK-INST: vmslt.vx v8, v4, a0 @@ -398,8 +398,8 @@ vmsge.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x6e] # CHECK-ENCODING: [0x57,0x24,0x84,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 6e -# CHECK-UNKNOWN: 57 24 84 76 +# CHECK-UNKNOWN: 6e454457 +# CHECK-UNKNOWN: 76842457 vmsgeu.vx v8, v4, a0, v0.t # CHECK-INST: vmsltu.vx v8, v4, a0, v0.t @@ -407,8 +407,8 @@ vmsgeu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x68] # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 68 -# CHECK-UNKNOWN: 57 24 80 6e +# CHECK-UNKNOWN: 68454457 +# CHECK-UNKNOWN: 6e802457 vmsge.vx v8, v4, a0, v0.t # CHECK-INST: vmslt.vx v8, v4, a0, v0.t @@ -416,8 +416,8 @@ vmsge.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x6c] # CHECK-ENCODING: [0x57,0x24,0x80,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 6c -# CHECK-UNKNOWN: 57 24 80 6e +# CHECK-UNKNOWN: 6c454457 +# CHECK-UNKNOWN: 6e802457 vmsgeu.vx v0, v4, a0, v0.t, v2 # CHECK-INST: vmsltu.vx v2, v4, a0 @@ -425,8 +425,8 @@ vmsgeu.vx v0, v4, a0, v0.t, v2 # CHECK-ENCODING: [0x57,0x41,0x45,0x6a] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 41 45 6a -# CHECK-UNKNOWN: 57 20 01 62 +# CHECK-UNKNOWN: 6a454157 +# CHECK-UNKNOWN: 62012057 vmsge.vx v0, v4, a0, v0.t, v2 # CHECK-INST: vmslt.vx v2, v4, a0 @@ -434,8 +434,8 @@ vmsge.vx v0, v4, a0, v0.t, v2 # CHECK-ENCODING: [0x57,0x41,0x45,0x6e] # CHECK-ENCODING: [0x57,0x20,0x01,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 41 45 6e -# CHECK-UNKNOWN: 57 20 01 62 +# CHECK-UNKNOWN: 6e454157 +# CHECK-UNKNOWN: 62012057 vmsgeu.vx v9, v4, a0, v0.t, v2 # CHECK-INST: vmsltu.vx v2, v4, a0 @@ -447,10 +447,10 @@ vmsgeu.vx v9, v4, a0, v0.t, v2 # CHECK-ENCODING: [0xd7,0x24,0x90,0x62] # CHECK-ENCODING: [0xd7,0xa4,0x24,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 41 45 6a -# CHECK-UNKNOWN: 57 21 01 62 -# CHECK-UNKNOWN: d7 24 90 62 -# CHECK-UNKNOWN: d7 a4 24 6a +# CHECK-UNKNOWN: 6a454157 +# CHECK-UNKNOWN: 62012157 +# CHECK-UNKNOWN: 629024d7 +# CHECK-UNKNOWN: 6a24a4d7 vmsge.vx v8, v4, a0, v0.t, v2 # CHECK-INST: vmslt.vx v2, v4, a0 @@ -462,7 +462,7 @@ vmsge.vx v8, v4, a0, v0.t, v2 # CHECK-ENCODING: [0x57,0x24,0x80,0x62] # CHECK-ENCODING: [0x57,0x24,0x24,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 41 45 6e -# CHECK-UNKNOWN: 57 21 01 62 -# CHECK-UNKNOWN: 57 24 80 62 -# CHECK-UNKNOWN: 57 24 24 6a +# CHECK-UNKNOWN: 6e454157 +# CHECK-UNKNOWN: 62012157 +# CHECK-UNKNOWN: 62802457 +# CHECK-UNKNOWN: 6a242457 diff --git a/llvm/test/MC/RISCV/rvv/convert.s b/llvm/test/MC/RISCV/rvv/convert.s index 28c0a0fa837e..269c86cef473 100644 --- a/llvm/test/MC/RISCV/rvv/convert.s +++ b/llvm/test/MC/RISCV/rvv/convert.s @@ -15,256 +15,256 @@ vfcvt.xu.f.v v8, v4, v0.t # CHECK-INST: vfcvt.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x40,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 40 48 +# CHECK-UNKNOWN: 48401457 vfcvt.xu.f.v v8, v4 # CHECK-INST: vfcvt.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x40,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 40 4a +# CHECK-UNKNOWN: 4a401457 vfcvt.x.f.v v8, v4, v0.t # CHECK-INST: vfcvt.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x40,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 40 48 +# CHECK-UNKNOWN: 48409457 vfcvt.x.f.v v8, v4 # CHECK-INST: vfcvt.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x40,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 40 4a +# CHECK-UNKNOWN: 4a409457 vfcvt.f.xu.v v8, v4, v0.t # CHECK-INST: vfcvt.f.xu.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x41,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 41 48 +# CHECK-UNKNOWN: 48411457 vfcvt.f.xu.v v8, v4 # CHECK-INST: vfcvt.f.xu.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x41,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 41 4a +# CHECK-UNKNOWN: 4a411457 vfcvt.f.x.v v8, v4, v0.t # CHECK-INST: vfcvt.f.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x41,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 41 48 +# CHECK-UNKNOWN: 48419457 vfcvt.f.x.v v8, v4 # CHECK-INST: vfcvt.f.x.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x41,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 41 4a +# CHECK-UNKNOWN: 4a419457 vfcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-INST: vfcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x43,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 43 48 +# CHECK-UNKNOWN: 48431457 vfcvt.rtz.xu.f.v v8, v4 # CHECK-INST: vfcvt.rtz.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x43,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 43 4a +# CHECK-UNKNOWN: 4a431457 vfcvt.rtz.x.f.v v8, v4, v0.t # CHECK-INST: vfcvt.rtz.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x43,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 43 48 +# CHECK-UNKNOWN: 48439457 vfcvt.rtz.x.f.v v8, v4 # CHECK-INST: vfcvt.rtz.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x43,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 43 4a +# CHECK-UNKNOWN: 4a439457 vfwcvt.xu.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x44,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 44 48 +# CHECK-UNKNOWN: 48441457 vfwcvt.xu.f.v v8, v4 # CHECK-INST: vfwcvt.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x44,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 44 4a +# CHECK-UNKNOWN: 4a441457 vfwcvt.x.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x44,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 44 48 +# CHECK-UNKNOWN: 48449457 vfwcvt.x.f.v v8, v4 # CHECK-INST: vfwcvt.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x44,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 44 4a +# CHECK-UNKNOWN: 4a449457 vfwcvt.f.xu.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.xu.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x45,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 45 48 +# CHECK-UNKNOWN: 48451457 vfwcvt.f.xu.v v8, v4 # CHECK-INST: vfwcvt.f.xu.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x45,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 45 4a +# CHECK-UNKNOWN: 4a451457 vfwcvt.f.x.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.x.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x45,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 45 48 +# CHECK-UNKNOWN: 48459457 vfwcvt.f.x.v v8, v4 # CHECK-INST: vfwcvt.f.x.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x45,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 45 4a +# CHECK-UNKNOWN: 4a459457 vfwcvt.f.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x46,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 46 48 +# CHECK-UNKNOWN: 48461457 vfwcvt.f.f.v v8, v4 # CHECK-INST: vfwcvt.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x46,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 46 4a +# CHECK-UNKNOWN: 4a461457 vfwcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x47,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 47 48 +# CHECK-UNKNOWN: 48471457 vfwcvt.rtz.xu.f.v v8, v4 # CHECK-INST: vfwcvt.rtz.xu.f.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x47,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 47 4a +# CHECK-UNKNOWN: 4a471457 vfwcvt.rtz.x.f.v v8, v4, v0.t # CHECK-INST: vfwcvt.rtz.x.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x47,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 47 48 +# CHECK-UNKNOWN: 48479457 vfwcvt.rtz.x.f.v v8, v4 # CHECK-INST: vfwcvt.rtz.x.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x47,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 47 4a +# CHECK-UNKNOWN: 4a479457 vfncvt.xu.f.w v8, v4, v0.t # CHECK-INST: vfncvt.xu.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x48,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 48 48 +# CHECK-UNKNOWN: 48481457 vfncvt.xu.f.w v4, v4, v0.t # CHECK-INST: vfncvt.xu.f.w v4, v4, v0.t # CHECK-ENCODING: [0x57,0x12,0x48,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 12 48 48 +# CHECK-UNKNOWN: 48481257 vfncvt.xu.f.w v8, v4 # CHECK-INST: vfncvt.xu.f.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x48,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 48 4a +# CHECK-UNKNOWN: 4a481457 vfncvt.x.f.w v8, v4, v0.t # CHECK-INST: vfncvt.x.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x48,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 48 48 +# CHECK-UNKNOWN: 48489457 vfncvt.x.f.w v8, v4 # CHECK-INST: vfncvt.x.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x48,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 48 4a +# CHECK-UNKNOWN: 4a489457 vfncvt.f.xu.w v8, v4, v0.t # CHECK-INST: vfncvt.f.xu.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x49,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 49 48 +# CHECK-UNKNOWN: 48491457 vfncvt.f.xu.w v8, v4 # CHECK-INST: vfncvt.f.xu.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x49,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 49 4a +# CHECK-UNKNOWN: 4a491457 vfncvt.f.x.w v8, v4, v0.t # CHECK-INST: vfncvt.f.x.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x49,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 49 48 +# CHECK-UNKNOWN: 48499457 vfncvt.f.x.w v8, v4 # CHECK-INST: vfncvt.f.x.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x49,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 49 4a +# CHECK-UNKNOWN: 4a499457 vfncvt.f.f.w v8, v4, v0.t # CHECK-INST: vfncvt.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 48 +# CHECK-UNKNOWN: 484a1457 vfncvt.f.f.w v8, v4 # CHECK-INST: vfncvt.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 4a +# CHECK-UNKNOWN: 4a4a1457 vfncvt.rod.f.f.w v8, v4, v0.t # CHECK-INST: vfncvt.rod.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4a,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 4a 48 +# CHECK-UNKNOWN: 484a9457 vfncvt.rod.f.f.w v8, v4 # CHECK-INST: vfncvt.rod.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4a,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 4a 4a +# CHECK-UNKNOWN: 4a4a9457 vfncvt.rtz.xu.f.w v8, v4, v0.t # CHECK-INST: vfncvt.rtz.xu.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4b,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4b 48 +# CHECK-UNKNOWN: 484b1457 vfncvt.rtz.xu.f.w v8, v4 # CHECK-INST: vfncvt.rtz.xu.f.w v8, v4 # CHECK-ENCODING: [0x57,0x14,0x4b,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4b 4a +# CHECK-UNKNOWN: 4a4b1457 vfncvt.rtz.x.f.w v8, v4, v0.t # CHECK-INST: vfncvt.rtz.x.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4b,0x48] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 4b 48 +# CHECK-UNKNOWN: 484b9457 vfncvt.rtz.x.f.w v8, v4 # CHECK-INST: vfncvt.rtz.x.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4b,0x4a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 4b 4a +# CHECK-UNKNOWN: 4a4b9457 diff --git a/llvm/test/MC/RISCV/rvv/div.s b/llvm/test/MC/RISCV/rvv/div.s index 229124c671c6..aca04375f61e 100644 --- a/llvm/test/MC/RISCV/rvv/div.s +++ b/llvm/test/MC/RISCV/rvv/div.s @@ -12,94 +12,94 @@ vdivu.vv v8, v4, v20, v0.t # CHECK-INST: vdivu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 80 +# CHECK-UNKNOWN: 804a2457 vdivu.vv v8, v4, v20 # CHECK-INST: vdivu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 82 +# CHECK-UNKNOWN: 824a2457 vdivu.vx v8, v4, a0, v0.t # CHECK-INST: vdivu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 80 +# CHECK-UNKNOWN: 80456457 vdivu.vx v8, v4, a0 # CHECK-INST: vdivu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 82 +# CHECK-UNKNOWN: 82456457 vdiv.vv v8, v4, v20, v0.t # CHECK-INST: vdiv.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 84 +# CHECK-UNKNOWN: 844a2457 vdiv.vv v8, v4, v20 # CHECK-INST: vdiv.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 86 +# CHECK-UNKNOWN: 864a2457 vdiv.vx v8, v4, a0, v0.t # CHECK-INST: vdiv.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 84 +# CHECK-UNKNOWN: 84456457 vdiv.vx v8, v4, a0 # CHECK-INST: vdiv.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 86 +# CHECK-UNKNOWN: 86456457 vremu.vv v8, v4, v20, v0.t # CHECK-INST: vremu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 88 +# CHECK-UNKNOWN: 884a2457 vremu.vv v8, v4, v20 # CHECK-INST: vremu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 8a +# CHECK-UNKNOWN: 8a4a2457 vremu.vx v8, v4, a0, v0.t # CHECK-INST: vremu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 88 +# CHECK-UNKNOWN: 88456457 vremu.vx v8, v4, a0 # CHECK-INST: vremu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 8a +# CHECK-UNKNOWN: 8a456457 vrem.vv v8, v4, v20, v0.t # CHECK-INST: vrem.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 8c +# CHECK-UNKNOWN: 8c4a2457 vrem.vv v8, v4, v20 # CHECK-INST: vrem.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 8e +# CHECK-UNKNOWN: 8e4a2457 vrem.vx v8, v4, a0, v0.t # CHECK-INST: vrem.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 8c +# CHECK-UNKNOWN: 8c456457 vrem.vx v8, v4, a0 # CHECK-INST: vrem.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 8e +# CHECK-UNKNOWN: 8e456457 diff --git a/llvm/test/MC/RISCV/rvv/ext.s b/llvm/test/MC/RISCV/rvv/ext.s index 80cadc096104..3bf1351d77a7 100644 --- a/llvm/test/MC/RISCV/rvv/ext.s +++ b/llvm/test/MC/RISCV/rvv/ext.s @@ -12,70 +12,70 @@ vzext.vf2 v8, v4, v0.t # CHECK-INST: vzext.vf2 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x43,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 43 48 +# CHECK-UNKNOWN: 48432457 vzext.vf2 v8, v4 # CHECK-INST: vzext.vf2 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x43,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 43 4a +# CHECK-UNKNOWN: 4a432457 vsext.vf2 v8, v4, v0.t # CHECK-INST: vsext.vf2 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x43,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 43 48 +# CHECK-UNKNOWN: 4843a457 vsext.vf2 v8, v4 # CHECK-INST: vsext.vf2 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x43,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 43 4a +# CHECK-UNKNOWN: 4a43a457 vzext.vf4 v8, v4, v0.t # CHECK-INST: vzext.vf4 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x42,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 42 48 +# CHECK-UNKNOWN: 48422457 vzext.vf4 v8, v4 # CHECK-INST: vzext.vf4 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 42 4a +# CHECK-UNKNOWN: 4a422457 vsext.vf4 v8, v4, v0.t # CHECK-INST: vsext.vf4 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x42,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 42 48 +# CHECK-UNKNOWN: 4842a457 vsext.vf4 v8, v4 # CHECK-INST: vsext.vf4 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x42,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 42 4a +# CHECK-UNKNOWN: 4a42a457 vzext.vf8 v8, v4, v0.t # CHECK-INST: vzext.vf8 v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x41,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 41 48 +# CHECK-UNKNOWN: 48412457 vzext.vf8 v8, v4 # CHECK-INST: vzext.vf8 v8, v4 # CHECK-ENCODING: [0x57,0x24,0x41,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 41 4a +# CHECK-UNKNOWN: 4a412457 vsext.vf8 v8, v4, v0.t # CHECK-INST: vsext.vf8 v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x41,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 41 48 +# CHECK-UNKNOWN: 4841a457 vsext.vf8 v8, v4 # CHECK-INST: vsext.vf8 v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x41,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 41 4a +# CHECK-UNKNOWN: 4a41a457 diff --git a/llvm/test/MC/RISCV/rvv/fadd.s b/llvm/test/MC/RISCV/rvv/fadd.s index 60ffaf62ca6b..890b2c0ad68b 100644 --- a/llvm/test/MC/RISCV/rvv/fadd.s +++ b/llvm/test/MC/RISCV/rvv/fadd.s @@ -15,70 +15,70 @@ vfadd.vv v8, v4, v20, v0.t # CHECK-INST: vfadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x00] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 00 +# CHECK-UNKNOWN: 004a1457 vfadd.vv v8, v4, v20 # CHECK-INST: vfadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x02] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 02 +# CHECK-UNKNOWN: 024a1457 vfadd.vf v8, v4, fa0, v0.t # CHECK-INST: vfadd.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x00] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 00 +# CHECK-UNKNOWN: 00455457 vfadd.vf v8, v4, fa0 # CHECK-INST: vfadd.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x02] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 02 +# CHECK-UNKNOWN: 02455457 vfwadd.vv v8, v4, v20, v0.t # CHECK-INST: vfwadd.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a c0 +# CHECK-UNKNOWN: c04a1457 vfwadd.vv v8, v4, v20 # CHECK-INST: vfwadd.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xc2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a c2 +# CHECK-UNKNOWN: c24a1457 vfwadd.vf v8, v4, fa0, v0.t # CHECK-INST: vfwadd.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xc0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 c0 +# CHECK-UNKNOWN: c0455457 vfwadd.vf v8, v4, fa0 # CHECK-INST: vfwadd.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xc2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 c2 +# CHECK-UNKNOWN: c2455457 vfwadd.wv v8, v4, v20, v0.t # CHECK-INST: vfwadd.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xd0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a d0 +# CHECK-UNKNOWN: d04a1457 vfwadd.wv v8, v4, v20 # CHECK-INST: vfwadd.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xd2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a d2 +# CHECK-UNKNOWN: d24a1457 vfwadd.wf v8, v4, fa0, v0.t # CHECK-INST: vfwadd.wf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xd0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 d0 +# CHECK-UNKNOWN: d0455457 vfwadd.wf v8, v4, fa0 # CHECK-INST: vfwadd.wf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xd2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 d2 +# CHECK-UNKNOWN: d2455457 diff --git a/llvm/test/MC/RISCV/rvv/fcompare.s b/llvm/test/MC/RISCV/rvv/fcompare.s index 11dd7e05467b..3903bbdab650 100644 --- a/llvm/test/MC/RISCV/rvv/fcompare.s +++ b/llvm/test/MC/RISCV/rvv/fcompare.s @@ -15,148 +15,148 @@ vmfeq.vv v8, v4, v20, v0.t # CHECK-INST: vmfeq.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x60] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 60 +# CHECK-UNKNOWN: 604a1457 vmfeq.vv v8, v4, v20 # CHECK-INST: vmfeq.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x62] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 62 +# CHECK-UNKNOWN: 624a1457 vmfeq.vf v8, v4, fa0, v0.t # CHECK-INST: vmfeq.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x60] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 60 +# CHECK-UNKNOWN: 60455457 vmfeq.vf v8, v4, fa0 # CHECK-INST: vmfeq.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x62] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 62 +# CHECK-UNKNOWN: 62455457 vmfne.vv v8, v4, v20, v0.t # CHECK-INST: vmfne.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x70] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 70 +# CHECK-UNKNOWN: 704a1457 vmfne.vv v8, v4, v20 # CHECK-INST: vmfne.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x72] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 72 +# CHECK-UNKNOWN: 724a1457 vmfne.vf v8, v4, fa0, v0.t # CHECK-INST: vmfne.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x70] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 70 +# CHECK-UNKNOWN: 70455457 vmfne.vf v8, v4, fa0 # CHECK-INST: vmfne.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x72] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 72 +# CHECK-UNKNOWN: 72455457 vmflt.vv v8, v4, v20, v0.t # CHECK-INST: vmflt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x6c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 6c +# CHECK-UNKNOWN: 6c4a1457 vmflt.vv v8, v4, v20 # CHECK-INST: vmflt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x6e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 6e +# CHECK-UNKNOWN: 6e4a1457 vmflt.vf v8, v4, fa0, v0.t # CHECK-INST: vmflt.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 6c +# CHECK-UNKNOWN: 6c455457 vmflt.vf v8, v4, fa0 # CHECK-INST: vmflt.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 6e +# CHECK-UNKNOWN: 6e455457 vmfle.vv v8, v4, v20, v0.t # CHECK-INST: vmfle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x64] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 64 +# CHECK-UNKNOWN: 644a1457 vmfle.vv v8, v4, v20 # CHECK-INST: vmfle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x66] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 66 +# CHECK-UNKNOWN: 664a1457 vmfle.vf v8, v4, fa0, v0.t # CHECK-INST: vmfle.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 64 +# CHECK-UNKNOWN: 64455457 vmfle.vf v8, v4, fa0 # CHECK-INST: vmfle.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 66 +# CHECK-UNKNOWN: 66455457 vmfgt.vf v8, v4, fa0, v0.t # CHECK-INST: vmfgt.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x74] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 74 +# CHECK-UNKNOWN: 74455457 vmfgt.vf v8, v4, fa0 # CHECK-INST: vmfgt.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x76] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 76 +# CHECK-UNKNOWN: 76455457 vmfge.vf v8, v4, fa0, v0.t # CHECK-INST: vmfge.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x7c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 7c +# CHECK-UNKNOWN: 7c455457 vmfge.vf v8, v4, fa0 # CHECK-INST: vmfge.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x7e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 7e +# CHECK-UNKNOWN: 7e455457 vmfgt.vv v8, v20, v4, v0.t # CHECK-INST: vmflt.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x6c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 6c +# CHECK-UNKNOWN: 6c4a1457 vmfgt.vv v8, v20, v4 # CHECK-INST: vmflt.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x6e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 6e +# CHECK-UNKNOWN: 6e4a1457 vmfge.vv v8, v20, v4, v0.t # CHECK-INST: vmfle.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x64] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 64 +# CHECK-UNKNOWN: 644a1457 vmfge.vv v8, v20, v4 # CHECK-INST: vmfle.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x66] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 66 +# CHECK-UNKNOWN: 664a1457 vmfeq.vv v0, v4, v20, v0.t # CHECK-INST: vmfeq.vv v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x10,0x4a,0x60] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 10 4a 60 +# CHECK-UNKNOWN: 604a1057 diff --git a/llvm/test/MC/RISCV/rvv/fdiv.s b/llvm/test/MC/RISCV/rvv/fdiv.s index 7eb048f3cd58..aa3aae5841a2 100644 --- a/llvm/test/MC/RISCV/rvv/fdiv.s +++ b/llvm/test/MC/RISCV/rvv/fdiv.s @@ -15,34 +15,34 @@ vfdiv.vv v8, v4, v20, v0.t # CHECK-INST: vfdiv.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x80] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 80 +# CHECK-UNKNOWN: 804a1457 vfdiv.vv v8, v4, v20 # CHECK-INST: vfdiv.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x82] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 82 +# CHECK-UNKNOWN: 824a1457 vfdiv.vf v8, v4, fa0, v0.t # CHECK-INST: vfdiv.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x80] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 80 +# CHECK-UNKNOWN: 80455457 vfdiv.vf v8, v4, fa0 # CHECK-INST: vfdiv.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x82] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 82 +# CHECK-UNKNOWN: 82455457 vfrdiv.vf v8, v4, fa0, v0.t # CHECK-INST: vfrdiv.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 84 +# CHECK-UNKNOWN: 84455457 vfrdiv.vf v8, v4, fa0 # CHECK-INST: vfrdiv.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 86 +# CHECK-UNKNOWN: 86455457 diff --git a/llvm/test/MC/RISCV/rvv/fmacc.s b/llvm/test/MC/RISCV/rvv/fmacc.s index 129455901b93..8ca43da80961 100644 --- a/llvm/test/MC/RISCV/rvv/fmacc.s +++ b/llvm/test/MC/RISCV/rvv/fmacc.s @@ -15,286 +15,286 @@ vfmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a b0 +# CHECK-UNKNOWN: b04a1457 vfmacc.vv v8, v20, v4 # CHECK-INST: vfmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xb2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a b2 +# CHECK-UNKNOWN: b24a1457 vfmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 b0 +# CHECK-UNKNOWN: b0455457 vfmacc.vf v8, fa0, v4 # CHECK-INST: vfmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xb2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 b2 +# CHECK-UNKNOWN: b2455457 vfnmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfnmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb4] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a b4 +# CHECK-UNKNOWN: b44a1457 vfnmacc.vv v8, v20, v4 # CHECK-INST: vfnmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xb6] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a b6 +# CHECK-UNKNOWN: b64a1457 vfnmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb4] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 b4 +# CHECK-UNKNOWN: b4455457 vfnmacc.vf v8, fa0, v4 # CHECK-INST: vfnmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xb6] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 b6 +# CHECK-UNKNOWN: b6455457 vfmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xb8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a b8 +# CHECK-UNKNOWN: b84a1457 vfmsac.vv v8, v20, v4 # CHECK-INST: vfmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xba] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a ba +# CHECK-UNKNOWN: ba4a1457 vfmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xb8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 b8 +# CHECK-UNKNOWN: b8455457 vfmsac.vf v8, fa0, v4 # CHECK-INST: vfmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xba] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 ba +# CHECK-UNKNOWN: ba455457 vfnmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xbc] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a bc +# CHECK-UNKNOWN: bc4a1457 vfnmsac.vv v8, v20, v4 # CHECK-INST: vfnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xbe] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a be +# CHECK-UNKNOWN: be4a1457 vfnmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xbc] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 bc +# CHECK-UNKNOWN: bc455457 vfnmsac.vf v8, fa0, v4 # CHECK-INST: vfnmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xbe] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 be +# CHECK-UNKNOWN: be455457 vfmadd.vv v8, v20, v4, v0.t # CHECK-INST: vfmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a a0 +# CHECK-UNKNOWN: a04a1457 vfmadd.vv v8, v20, v4 # CHECK-INST: vfmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xa2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a a2 +# CHECK-UNKNOWN: a24a1457 vfmadd.vf v8, fa0, v4, v0.t # CHECK-INST: vfmadd.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 a0 +# CHECK-UNKNOWN: a0455457 vfmadd.vf v8, fa0, v4 # CHECK-INST: vfmadd.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xa2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 a2 +# CHECK-UNKNOWN: a2455457 vfnmadd.vv v8, v20, v4, v0.t # CHECK-INST: vfnmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa4] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a a4 +# CHECK-UNKNOWN: a44a1457 vfnmadd.vv v8, v20, v4 # CHECK-INST: vfnmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xa6] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a a6 +# CHECK-UNKNOWN: a64a1457 vfnmadd.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmadd.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 a4 +# CHECK-UNKNOWN: a4455457 vfnmadd.vf v8, fa0, v4 # CHECK-INST: vfnmadd.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 a6 +# CHECK-UNKNOWN: a6455457 vfmsub.vv v8, v20, v4, v0.t # CHECK-INST: vfmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xa8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a a8 +# CHECK-UNKNOWN: a84a1457 vfmsub.vv v8, v20, v4 # CHECK-INST: vfmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xaa] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a aa +# CHECK-UNKNOWN: aa4a1457 vfmsub.vf v8, fa0, v4, v0.t # CHECK-INST: vfmsub.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xa8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 a8 +# CHECK-UNKNOWN: a8455457 vfmsub.vf v8, fa0, v4 # CHECK-INST: vfmsub.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xaa] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 aa +# CHECK-UNKNOWN: aa455457 vfnmsub.vv v8, v20, v4, v0.t # CHECK-INST: vfnmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xac] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a ac +# CHECK-UNKNOWN: ac4a1457 vfnmsub.vv v8, v20, v4 # CHECK-INST: vfnmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xae] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a ae +# CHECK-UNKNOWN: ae4a1457 vfnmsub.vf v8, fa0, v4, v0.t # CHECK-INST: vfnmsub.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 ac +# CHECK-UNKNOWN: ac455457 vfnmsub.vf v8, fa0, v4 # CHECK-INST: vfnmsub.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 ae +# CHECK-UNKNOWN: ae455457 vfwmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfwmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a f0 +# CHECK-UNKNOWN: f04a1457 vfwmacc.vv v8, v20, v4 # CHECK-INST: vfwmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xf2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a f2 +# CHECK-UNKNOWN: f24a1457 vfwmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfwmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 f0 +# CHECK-UNKNOWN: f0455457 vfwmacc.vf v8, fa0, v4 # CHECK-INST: vfwmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xf2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 f2 +# CHECK-UNKNOWN: f2455457 vfwnmacc.vv v8, v20, v4, v0.t # CHECK-INST: vfwnmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf4] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a f4 +# CHECK-UNKNOWN: f44a1457 vfwnmacc.vv v8, v20, v4 # CHECK-INST: vfwnmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xf6] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a f6 +# CHECK-UNKNOWN: f64a1457 vfwnmacc.vf v8, fa0, v4, v0.t # CHECK-INST: vfwnmacc.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf4] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 f4 +# CHECK-UNKNOWN: f4455457 vfwnmacc.vf v8, fa0, v4 # CHECK-INST: vfwnmacc.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xf6] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 f6 +# CHECK-UNKNOWN: f6455457 vfwmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfwmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xf8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a f8 +# CHECK-UNKNOWN: f84a1457 vfwmsac.vv v8, v20, v4 # CHECK-INST: vfwmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xfa] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a fa +# CHECK-UNKNOWN: fa4a1457 vfwmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfwmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xf8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 f8 +# CHECK-UNKNOWN: f8455457 vfwmsac.vf v8, fa0, v4 # CHECK-INST: vfwmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xfa] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 fa +# CHECK-UNKNOWN: fa455457 vfwnmsac.vv v8, v20, v4, v0.t # CHECK-INST: vfwnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xfc] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a fc +# CHECK-UNKNOWN: fc4a1457 vfwnmsac.vv v8, v20, v4 # CHECK-INST: vfwnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xfe] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a fe +# CHECK-UNKNOWN: fe4a1457 vfwnmsac.vf v8, fa0, v4, v0.t # CHECK-INST: vfwnmsac.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xfc] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 fc +# CHECK-UNKNOWN: fc455457 vfwnmsac.vf v8, fa0, v4 # CHECK-INST: vfwnmsac.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xfe] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 fe +# CHECK-UNKNOWN: fe455457 diff --git a/llvm/test/MC/RISCV/rvv/fminmax.s b/llvm/test/MC/RISCV/rvv/fminmax.s index c8aab38e1fc8..f7e85ed31c33 100644 --- a/llvm/test/MC/RISCV/rvv/fminmax.s +++ b/llvm/test/MC/RISCV/rvv/fminmax.s @@ -15,46 +15,46 @@ vfmin.vv v8, v4, v20, v0.t # CHECK-INST: vfmin.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x10] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 10 +# CHECK-UNKNOWN: 104a1457 vfmin.vv v8, v4, v20 # CHECK-INST: vfmin.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x12] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 12 +# CHECK-UNKNOWN: 124a1457 vfmin.vf v8, v4, fa0, v0.t # CHECK-INST: vfmin.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x10] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 10 +# CHECK-UNKNOWN: 10455457 vfmin.vf v8, v4, fa0 # CHECK-INST: vfmin.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x12] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 12 +# CHECK-UNKNOWN: 12455457 vfmax.vv v8, v4, v20, v0.t # CHECK-INST: vfmax.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x18] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 18 +# CHECK-UNKNOWN: 184a1457 vfmax.vv v8, v4, v20 # CHECK-INST: vfmax.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x1a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 1a +# CHECK-UNKNOWN: 1a4a1457 vfmax.vf v8, v4, fa0, v0.t # CHECK-INST: vfmax.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x18] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 18 +# CHECK-UNKNOWN: 18455457 vfmax.vf v8, v4, fa0 # CHECK-INST: vfmax.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x1a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 1a +# CHECK-UNKNOWN: 1a455457 diff --git a/llvm/test/MC/RISCV/rvv/fmul.s b/llvm/test/MC/RISCV/rvv/fmul.s index 42c37932043c..9cd6e5287750 100644 --- a/llvm/test/MC/RISCV/rvv/fmul.s +++ b/llvm/test/MC/RISCV/rvv/fmul.s @@ -15,46 +15,46 @@ vfmul.vv v8, v4, v20, v0.t # CHECK-INST: vfmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x90] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 90 +# CHECK-UNKNOWN: 904a1457 vfmul.vv v8, v4, v20 # CHECK-INST: vfmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x92] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 92 +# CHECK-UNKNOWN: 924a1457 vfmul.vf v8, v4, fa0, v0.t # CHECK-INST: vfmul.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x90] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 90 +# CHECK-UNKNOWN: 90455457 vfmul.vf v8, v4, fa0 # CHECK-INST: vfmul.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x92] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 92 +# CHECK-UNKNOWN: 92455457 vfwmul.vv v8, v4, v20, v0.t # CHECK-INST: vfwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xe0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a e0 +# CHECK-UNKNOWN: e04a1457 vfwmul.vv v8, v4, v20 # CHECK-INST: vfwmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xe2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a e2 +# CHECK-UNKNOWN: e24a1457 vfwmul.vf v8, v4, fa0, v0.t # CHECK-INST: vfwmul.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xe0] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 e0 +# CHECK-UNKNOWN: e0455457 vfwmul.vf v8, v4, fa0 # CHECK-INST: vfwmul.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xe2] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 e2 +# CHECK-UNKNOWN: e2455457 diff --git a/llvm/test/MC/RISCV/rvv/fmv.s b/llvm/test/MC/RISCV/rvv/fmv.s index a5b814f130fb..2534b5171b3e 100644 --- a/llvm/test/MC/RISCV/rvv/fmv.s +++ b/llvm/test/MC/RISCV/rvv/fmv.s @@ -15,16 +15,16 @@ vfmv.v.f v8, fa0 # CHECK-INST: vfmv.v.f v8, fa0 # CHECK-ENCODING: [0x57,0x54,0x05,0x5e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 05 5e +# CHECK-UNKNOWN: 5e055457 vfmv.f.s fa0, v4 # CHECK-INST: vfmv.f.s fa0, v4 # CHECK-ENCODING: [0x57,0x15,0x40,0x42] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 15 40 42 +# CHECK-UNKNOWN: 42401557 vfmv.s.f v8, fa0 # CHECK-INST: vfmv.s.f v8, fa0 # CHECK-ENCODING: [0x57,0x54,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 05 42 +# CHECK-UNKNOWN: 42055457 diff --git a/llvm/test/MC/RISCV/rvv/fothers.s b/llvm/test/MC/RISCV/rvv/fothers.s index 451f6ca39ccc..997115f96bd9 100644 --- a/llvm/test/MC/RISCV/rvv/fothers.s +++ b/llvm/test/MC/RISCV/rvv/fothers.s @@ -13,76 +13,76 @@ vfsqrt.v v8, v4, v0.t # CHECK-INST: vfsqrt.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x40,0x4c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 40 4c +# CHECK-UNKNOWN: 4c401457 vfsqrt.v v8, v4 # CHECK-INST: vfsqrt.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x40,0x4e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 40 4e +# CHECK-UNKNOWN: 4e401457 vfrsqrt7.v v8, v4, v0.t # CHECK-INST: vfrsqrt7.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x42,0x4c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 42 4c +# CHECK-UNKNOWN: 4c421457 vfrsqrt7.v v8, v4 # CHECK-INST: vfrsqrt7.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x42,0x4e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 42 4e +# CHECK-UNKNOWN: 4e421457 vfrec7.v v8, v4, v0.t # CHECK-INST: vfrec7.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x42,0x4c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 42 4c +# CHECK-UNKNOWN: 4c429457 vfrec7.v v8, v4 # CHECK-INST: vfrec7.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x42,0x4e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 94 42 4e +# CHECK-UNKNOWN: 4e429457 vfclass.v v8, v4, v0.t # CHECK-INST: vfclass.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x48,0x4c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 48 4c +# CHECK-UNKNOWN: 4c481457 vfclass.v v8, v4 # CHECK-INST: vfclass.v v8, v4 # CHECK-ENCODING: [0x57,0x14,0x48,0x4e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 48 4e +# CHECK-UNKNOWN: 4e481457 vfmerge.vfm v8, v4, fa0, v0 # CHECK-INST: vfmerge.vfm v8, v4, fa0, v0 # CHECK-ENCODING: [0x57,0x54,0x45,0x5c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 5c +# CHECK-UNKNOWN: 5c455457 vfslide1up.vf v8, v4, fa0, v0.t # CHECK-INST: vfslide1up.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x38] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 38 +# CHECK-UNKNOWN: 38455457 vfslide1up.vf v8, v4, fa0 # CHECK-INST: vfslide1up.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x3a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 3a +# CHECK-UNKNOWN: 3a455457 vfslide1down.vf v8, v4, fa0, v0.t # CHECK-INST: vfslide1down.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x3c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 3c +# CHECK-UNKNOWN: 3c455457 vfslide1down.vf v8, v4, fa0 # CHECK-INST: vfslide1down.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x3e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 3e +# CHECK-UNKNOWN: 3e455457 diff --git a/llvm/test/MC/RISCV/rvv/freduction.s b/llvm/test/MC/RISCV/rvv/freduction.s index fca64372b15f..12326942e6e8 100644 --- a/llvm/test/MC/RISCV/rvv/freduction.s +++ b/llvm/test/MC/RISCV/rvv/freduction.s @@ -15,76 +15,76 @@ vfredosum.vs v8, v4, v20, v0.t # CHECK-INST: vfredosum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x0c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 0c +# CHECK-UNKNOWN: 0c4a1457 vfredosum.vs v8, v4, v20 # CHECK-INST: vfredosum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x0e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 0e +# CHECK-UNKNOWN: 0e4a1457 vfredusum.vs v8, v4, v20, v0.t # CHECK-INST: vfredusum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x04] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 04 +# CHECK-UNKNOWN: 044a1457 vfredusum.vs v8, v4, v20 # CHECK-INST: vfredusum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x06] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 06 +# CHECK-UNKNOWN: 064a1457 vfredmax.vs v8, v4, v20, v0.t # CHECK-INST: vfredmax.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x1c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 1c +# CHECK-UNKNOWN: 1c4a1457 vfredmax.vs v8, v4, v20 # CHECK-INST: vfredmax.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x1e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 1e +# CHECK-UNKNOWN: 1e4a1457 vfredmin.vs v8, v4, v20, v0.t # CHECK-INST: vfredmin.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x14] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 14 +# CHECK-UNKNOWN: 144a1457 vfredmin.vs v8, v4, v20 # CHECK-INST: vfredmin.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x16] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 16 +# CHECK-UNKNOWN: 164a1457 vfwredosum.vs v8, v4, v20, v0.t # CHECK-INST: vfwredosum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xcc] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a cc +# CHECK-UNKNOWN: cc4a1457 vfwredosum.vs v8, v4, v20 # CHECK-INST: vfwredosum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xce] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a ce +# CHECK-UNKNOWN: ce4a1457 vfwredusum.vs v8, v4, v20, v0.t # CHECK-INST: vfwredusum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc4] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a c4 +# CHECK-UNKNOWN: c44a1457 vfwredusum.vs v8, v4, v20 # CHECK-INST: vfwredusum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xc6] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a c6 +# CHECK-UNKNOWN: c64a1457 vfredosum.vs v0, v4, v20, v0.t # CHECK-INST: vfredosum.vs v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x10,0x4a,0x0c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 10 4a 0c +# CHECK-UNKNOWN: 0c4a1057 diff --git a/llvm/test/MC/RISCV/rvv/fsub.s b/llvm/test/MC/RISCV/rvv/fsub.s index a8f2bc6260b9..62ff2e744c78 100644 --- a/llvm/test/MC/RISCV/rvv/fsub.s +++ b/llvm/test/MC/RISCV/rvv/fsub.s @@ -15,82 +15,82 @@ vfsub.vv v8, v4, v20, v0.t # CHECK-INST: vfsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x08] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 08 +# CHECK-UNKNOWN: 084a1457 vfsub.vv v8, v4, v20 # CHECK-INST: vfsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x0a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 0a +# CHECK-UNKNOWN: 0a4a1457 vfsub.vf v8, v4, fa0, v0.t # CHECK-INST: vfsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x08] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 08 +# CHECK-UNKNOWN: 08455457 vfsub.vf v8, v4, fa0 # CHECK-INST: vfsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x0a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 0a +# CHECK-UNKNOWN: 0a455457 vfrsub.vf v8, v4, fa0, v0.t # CHECK-INST: vfrsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x9c] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 9c +# CHECK-UNKNOWN: 9c455457 vfrsub.vf v8, v4, fa0 # CHECK-INST: vfrsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x9e] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 9e +# CHECK-UNKNOWN: 9e455457 vfwsub.vv v8, v4, v20, v0.t # CHECK-INST: vfwsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xc8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a c8 +# CHECK-UNKNOWN: c84a1457 vfwsub.vv v8, v4, v20 # CHECK-INST: vfwsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xca] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a ca +# CHECK-UNKNOWN: ca4a1457 vfwsub.vf v8, v4, fa0, v0.t # CHECK-INST: vfwsub.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xc8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 c8 +# CHECK-UNKNOWN: c8455457 vfwsub.vf v8, v4, fa0 # CHECK-INST: vfwsub.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xca] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 ca +# CHECK-UNKNOWN: ca455457 vfwsub.wv v8, v4, v20, v0.t # CHECK-INST: vfwsub.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xd8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a d8 +# CHECK-UNKNOWN: d84a1457 vfwsub.wv v8, v4, v20 # CHECK-INST: vfwsub.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0xda] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a da +# CHECK-UNKNOWN: da4a1457 vfwsub.wf v8, v4, fa0, v0.t # CHECK-INST: vfwsub.wf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xd8] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 d8 +# CHECK-UNKNOWN: d8455457 vfwsub.wf v8, v4, fa0 # CHECK-INST: vfwsub.wf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0xda] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 da +# CHECK-UNKNOWN: da455457 diff --git a/llvm/test/MC/RISCV/rvv/load.s b/llvm/test/MC/RISCV/rvv/load.s index 23357df88d3f..3c251a3a8d75 100644 --- a/llvm/test/MC/RISCV/rvv/load.s +++ b/llvm/test/MC/RISCV/rvv/load.s @@ -12,382 +12,382 @@ vlm.v v0, (a0) # CHECK-INST: vlm.v v0, (a0) # CHECK-ENCODING: [0x07,0x00,0xb5,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 00 b5 02 +# CHECK-UNKNOWN: 02b50007 vlm.v v8, (a0) # CHECK-INST: vlm.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0xb5,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 02 +# CHECK-UNKNOWN: 02b50407 vle8.v v8, (a0), v0.t # CHECK-INST: vle8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 00 +# CHECK-UNKNOWN: 00050407 vle8.v v8, (a0) # CHECK-INST: vle8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 02 +# CHECK-UNKNOWN: 02050407 vle16.v v8, (a0), v0.t # CHECK-INST: vle16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 00 +# CHECK-UNKNOWN: 00055407 vle16.v v8, (a0) # CHECK-INST: vle16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 02 +# CHECK-UNKNOWN: 02055407 vle32.v v8, (a0), v0.t # CHECK-INST: vle32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 00 +# CHECK-UNKNOWN: 00056407 vle32.v v8, (a0) # CHECK-INST: vle32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 02 +# CHECK-UNKNOWN: 02056407 vle64.v v8, (a0), v0.t # CHECK-INST: vle64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 00 +# CHECK-UNKNOWN: 00057407 vle64.v v8, (a0) # CHECK-INST: vle64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 02 +# CHECK-UNKNOWN: 02057407 vle8ff.v v8, (a0), v0.t # CHECK-INST: vle8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 01 +# CHECK-UNKNOWN: 01050407 vle8ff.v v8, (a0) # CHECK-INST: vle8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 03 +# CHECK-UNKNOWN: 03050407 vle16ff.v v8, (a0), v0.t # CHECK-INST: vle16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 01 +# CHECK-UNKNOWN: 01055407 vle16ff.v v8, (a0) # CHECK-INST: vle16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 03 +# CHECK-UNKNOWN: 03055407 vle32ff.v v8, (a0), v0.t # CHECK-INST: vle32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 01 +# CHECK-UNKNOWN: 01056407 vle32ff.v v8, (a0) # CHECK-INST: vle32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 03 +# CHECK-UNKNOWN: 03056407 vle64ff.v v8, (a0), v0.t # CHECK-INST: vle64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 01 +# CHECK-UNKNOWN: 01057407 vle64ff.v v8, (a0) # CHECK-INST: vle64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x03] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 03 +# CHECK-UNKNOWN: 03057407 vlse8.v v8, (a0), a1, v0.t # CHECK-INST: vlse8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 08 +# CHECK-UNKNOWN: 08b50407 vlse8.v v8, (a0), a1 # CHECK-INST: vlse8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 0a +# CHECK-UNKNOWN: 0ab50407 vlse16.v v8, (a0), a1, v0.t # CHECK-INST: vlse16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 08 +# CHECK-UNKNOWN: 08b55407 vlse16.v v8, (a0), a1 # CHECK-INST: vlse16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 0a +# CHECK-UNKNOWN: 0ab55407 vlse32.v v8, (a0), a1, v0.t # CHECK-INST: vlse32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 08 +# CHECK-UNKNOWN: 08b56407 vlse32.v v8, (a0), a1 # CHECK-INST: vlse32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 0a +# CHECK-UNKNOWN: 0ab56407 vlse64.v v8, (a0), a1, v0.t # CHECK-INST: vlse64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 08 +# CHECK-UNKNOWN: 08b57407 vlse64.v v8, (a0), a1 # CHECK-INST: vlse64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 0a +# CHECK-UNKNOWN: 0ab57407 vluxei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 04 +# CHECK-UNKNOWN: 04450407 vluxei8.v v8, (a0), v4 # CHECK-INST: vluxei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 06 +# CHECK-UNKNOWN: 06450407 vluxei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 04 +# CHECK-UNKNOWN: 04455407 vluxei16.v v8, (a0), v4 # CHECK-INST: vluxei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 06 +# CHECK-UNKNOWN: 06455407 vluxei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 04 +# CHECK-UNKNOWN: 04456407 vluxei32.v v8, (a0), v4 # CHECK-INST: vluxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 06 +# CHECK-UNKNOWN: 06456407 vluxei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 04 +# CHECK-UNKNOWN: 04457407 vluxei64.v v8, (a0), v4 # CHECK-INST: vluxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 06 +# CHECK-UNKNOWN: 06457407 vloxei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 0c +# CHECK-UNKNOWN: 0c450407 vloxei8.v v8, (a0), v4 # CHECK-INST: vloxei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 0e +# CHECK-UNKNOWN: 0e450407 vloxei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 0c +# CHECK-UNKNOWN: 0c455407 vloxei16.v v8, (a0), v4 # CHECK-INST: vloxei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 0e +# CHECK-UNKNOWN: 0e455407 vloxei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 0c +# CHECK-UNKNOWN: 0c456407 vloxei32.v v8, (a0), v4 # CHECK-INST: vloxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 0e +# CHECK-UNKNOWN: 0e456407 vloxei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 0c +# CHECK-UNKNOWN: 0c457407 vloxei64.v v8, (a0), v4 # CHECK-INST: vloxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 0e +# CHECK-UNKNOWN: 0e457407 vl1re8.v v8, (a0) # CHECK-INST: vl1re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 85 02 +# CHECK-UNKNOWN: 02850407 vl1re16.v v8, (a0) # CHECK-INST: vl1re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 85 02 +# CHECK-UNKNOWN: 02855407 vl1re32.v v8, (a0) # CHECK-INST: vl1re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 85 02 +# CHECK-UNKNOWN: 02856407 vl1re64.v v8, (a0) # CHECK-INST: vl1re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 85 02 +# CHECK-UNKNOWN: 02857407 vl2re8.v v8, (a0) # CHECK-INST: vl2re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 85 22 +# CHECK-UNKNOWN: 22850407 vl2re16.v v8, (a0) # CHECK-INST: vl2re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 85 22 +# CHECK-UNKNOWN: 22855407 vl2re32.v v8, (a0) # CHECK-INST: vl2re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 85 22 +# CHECK-UNKNOWN: 22856407 vl2re64.v v8, (a0) # CHECK-INST: vl2re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 85 22 +# CHECK-UNKNOWN: 22857407 vl4re8.v v8, (a0) # CHECK-INST: vl4re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 85 62 +# CHECK-UNKNOWN: 62850407 vl4re16.v v8, (a0) # CHECK-INST: vl4re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 85 62 +# CHECK-UNKNOWN: 62855407 vl4re32.v v8, (a0) # CHECK-INST: vl4re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 85 62 +# CHECK-UNKNOWN: 62856407 vl4re64.v v8, (a0) # CHECK-INST: vl4re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 85 62 +# CHECK-UNKNOWN: 62857407 vl8re8.v v8, (a0) # CHECK-INST: vl8re8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 85 e2 +# CHECK-UNKNOWN: e2850407 vl8re16.v v8, (a0) # CHECK-INST: vl8re16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 85 e2 +# CHECK-UNKNOWN: e2855407 vl8re32.v v8, (a0) # CHECK-INST: vl8re32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 85 e2 +# CHECK-UNKNOWN: e2856407 vl8re64.v v8, (a0) # CHECK-INST: vl8re64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 85 e2 +# CHECK-UNKNOWN: e2857407 vlm.v v0, 0(a0) # CHECK-INST: vlm.v v0, (a0) # CHECK-ENCODING: [0x07,0x00,0xb5,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 00 b5 02 +# CHECK-UNKNOWN: 02b50007 vle8.v v8, 0(a0) # CHECK-INST: vle8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 02 +# CHECK-UNKNOWN: 02050407 vle8ff.v v8, 0(a0), v0.t # CHECK-INST: vle8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 01 +# CHECK-UNKNOWN: 01050407 vlse16.v v8, 0(a0), a1, v0.t # CHECK-INST: vlse16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 08 +# CHECK-UNKNOWN: 08b55407 vluxei32.v v8, 0(a0), v4 # CHECK-INST: vluxei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 06 +# CHECK-UNKNOWN: 06456407 vloxei64.v v8, 0(a0), v4 # CHECK-INST: vloxei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 0e +# CHECK-UNKNOWN: 0e457407 diff --git a/llvm/test/MC/RISCV/rvv/macc.s b/llvm/test/MC/RISCV/rvv/macc.s index 0662620b455a..ffdc2d646929 100644 --- a/llvm/test/MC/RISCV/rvv/macc.s +++ b/llvm/test/MC/RISCV/rvv/macc.s @@ -12,178 +12,178 @@ vmacc.vv v8, v20, v4, v0.t # CHECK-INST: vmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xb4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a b4 +# CHECK-UNKNOWN: b44a2457 vmacc.vv v8, v20, v4 # CHECK-INST: vmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xb6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a b6 +# CHECK-UNKNOWN: b64a2457 vmacc.vx v8, a0, v4, v0.t # CHECK-INST: vmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xb4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 b4 +# CHECK-UNKNOWN: b4456457 vmacc.vx v8, a0, v4 # CHECK-INST: vmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xb6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 b6 +# CHECK-UNKNOWN: b6456457 vnmsac.vv v8, v20, v4, v0.t # CHECK-INST: vnmsac.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xbc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a bc +# CHECK-UNKNOWN: bc4a2457 vnmsac.vv v8, v20, v4 # CHECK-INST: vnmsac.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xbe] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a be +# CHECK-UNKNOWN: be4a2457 vnmsac.vx v8, a0, v4, v0.t # CHECK-INST: vnmsac.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xbc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 bc +# CHECK-UNKNOWN: bc456457 vnmsac.vx v8, a0, v4 # CHECK-INST: vnmsac.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xbe] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 be +# CHECK-UNKNOWN: be456457 vmadd.vv v8, v20, v4, v0.t # CHECK-INST: vmadd.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a a4 +# CHECK-UNKNOWN: a44a2457 vmadd.vv v8, v20, v4 # CHECK-INST: vmadd.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a a6 +# CHECK-UNKNOWN: a64a2457 vmadd.vx v8, a0, v4, v0.t # CHECK-INST: vmadd.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 a4 +# CHECK-UNKNOWN: a4456457 vmadd.vx v8, a0, v4 # CHECK-INST: vmadd.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 a6 +# CHECK-UNKNOWN: a6456457 vnmsub.vv v8, v20, v4, v0.t # CHECK-INST: vnmsub.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a ac +# CHECK-UNKNOWN: ac4a2457 vnmsub.vv v8, v20, v4 # CHECK-INST: vnmsub.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a ae +# CHECK-UNKNOWN: ae4a2457 vnmsub.vx v8, a0, v4, v0.t # CHECK-INST: vnmsub.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 ac +# CHECK-UNKNOWN: ac456457 vnmsub.vx v8, a0, v4 # CHECK-INST: vnmsub.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 ae +# CHECK-UNKNOWN: ae456457 vwmaccu.vv v8, v20, v4, v0.t # CHECK-INST: vwmaccu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a f0 +# CHECK-UNKNOWN: f04a2457 vwmaccu.vv v8, v20, v4 # CHECK-INST: vwmaccu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a f2 +# CHECK-UNKNOWN: f24a2457 vwmaccu.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 f0 +# CHECK-UNKNOWN: f0456457 vwmaccu.vx v8, a0, v4 # CHECK-INST: vwmaccu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 f2 +# CHECK-UNKNOWN: f2456457 vwmacc.vv v8, v20, v4, v0.t # CHECK-INST: vwmacc.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xf4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a f4 +# CHECK-UNKNOWN: f44a2457 vwmacc.vv v8, v20, v4 # CHECK-INST: vwmacc.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xf6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a f6 +# CHECK-UNKNOWN: f64a2457 vwmacc.vx v8, a0, v4, v0.t # CHECK-INST: vwmacc.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 f4 +# CHECK-UNKNOWN: f4456457 vwmacc.vx v8, a0, v4 # CHECK-INST: vwmacc.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xf6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 f6 +# CHECK-UNKNOWN: f6456457 vwmaccsu.vv v8, v20, v4, v0.t # CHECK-INST: vwmaccsu.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xfc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a fc +# CHECK-UNKNOWN: fc4a2457 vwmaccsu.vv v8, v20, v4 # CHECK-INST: vwmaccsu.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x24,0x4a,0xfe] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a fe +# CHECK-UNKNOWN: fe4a2457 vwmaccsu.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccsu.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xfc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 fc +# CHECK-UNKNOWN: fc456457 vwmaccsu.vx v8, a0, v4 # CHECK-INST: vwmaccsu.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfe] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 fe +# CHECK-UNKNOWN: fe456457 vwmaccus.vx v8, a0, v4, v0.t # CHECK-INST: vwmaccus.vx v8, a0, v4, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xf8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 f8 +# CHECK-UNKNOWN: f8456457 vwmaccus.vx v8, a0, v4 # CHECK-INST: vwmaccus.vx v8, a0, v4 # CHECK-ENCODING: [0x57,0x64,0x45,0xfa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 fa +# CHECK-UNKNOWN: fa456457 diff --git a/llvm/test/MC/RISCV/rvv/mask.s b/llvm/test/MC/RISCV/rvv/mask.s index c0691b97f1d9..c0dd44b6fc67 100644 --- a/llvm/test/MC/RISCV/rvv/mask.s +++ b/llvm/test/MC/RISCV/rvv/mask.s @@ -12,154 +12,154 @@ vmand.mm v8, v4, v20 # CHECK-INST: vmand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 66 +# CHECK-UNKNOWN: 664a2457 vmnand.mm v8, v4, v20 # CHECK-INST: vmnand.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 76 +# CHECK-UNKNOWN: 764a2457 vmandn.mm v8, v4, v20 # CHECK-INST: vmandn.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 62 +# CHECK-UNKNOWN: 624a2457 vmxor.mm v8, v4, v20 # CHECK-INST: vmxor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 6e +# CHECK-UNKNOWN: 6e4a2457 vmor.mm v8, v4, v20 # CHECK-INST: vmor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 6a +# CHECK-UNKNOWN: 6a4a2457 vmnor.mm v8, v4, v20 # CHECK-INST: vmnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 7a +# CHECK-UNKNOWN: 7a4a2457 vmorn.mm v8, v4, v20 # CHECK-INST: vmorn.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x72] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 72 +# CHECK-UNKNOWN: 724a2457 vmxnor.mm v8, v4, v20 # CHECK-INST: vmxnor.mm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x7e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 7e +# CHECK-UNKNOWN: 7e4a2457 vcpop.m a2, v4, v0.t # CHECK-INST: vcpop.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0x26,0x48,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 26 48 40 +# CHECK-UNKNOWN: 40482657 vcpop.m a2, v4 # CHECK-INST: vcpop.m a2, v4 # CHECK-ENCODING: [0x57,0x26,0x48,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 26 48 42 +# CHECK-UNKNOWN: 42482657 vfirst.m a2, v4, v0.t # CHECK-INST: vfirst.m a2, v4, v0.t # CHECK-ENCODING: [0x57,0xa6,0x48,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a6 48 40 +# CHECK-UNKNOWN: 4048a657 vfirst.m a2, v4 # CHECK-INST: vfirst.m a2, v4 # CHECK-ENCODING: [0x57,0xa6,0x48,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a6 48 42 +# CHECK-UNKNOWN: 4248a657 vmsbf.m v8, v4, v0.t # CHECK-INST: vmsbf.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x40,0x50] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 40 50 +# CHECK-UNKNOWN: 5040a457 vmsbf.m v8, v4 # CHECK-INST: vmsbf.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x40,0x52] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 40 52 +# CHECK-UNKNOWN: 5240a457 vmsif.m v8, v4, v0.t # CHECK-INST: vmsif.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0xa4,0x41,0x50] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 41 50 +# CHECK-UNKNOWN: 5041a457 vmsif.m v8, v4 # CHECK-INST: vmsif.m v8, v4 # CHECK-ENCODING: [0x57,0xa4,0x41,0x52] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 41 52 +# CHECK-UNKNOWN: 5241a457 vmsof.m v8, v4, v0.t # CHECK-INST: vmsof.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x41,0x50] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 41 50 +# CHECK-UNKNOWN: 50412457 vmsof.m v8, v4 # CHECK-INST: vmsof.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x41,0x52] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 41 52 +# CHECK-UNKNOWN: 52412457 viota.m v8, v4, v0.t # CHECK-INST: viota.m v8, v4, v0.t # CHECK-ENCODING: [0x57,0x24,0x48,0x50] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 48 50 +# CHECK-UNKNOWN: 50482457 viota.m v8, v4 # CHECK-INST: viota.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x48,0x52] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 48 52 +# CHECK-UNKNOWN: 52482457 vid.v v8, v0.t # CHECK-INST: vid.v v8, v0.t # CHECK-ENCODING: [0x57,0xa4,0x08,0x50] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 08 50 +# CHECK-UNKNOWN: 5008a457 vid.v v8 # CHECK-INST: vid.v v8 # CHECK-ENCODING: [0x57,0xa4,0x08,0x52] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 a4 08 52 +# CHECK-UNKNOWN: 5208a457 vmmv.m v8, v4 # CHECK-INST: vmmv.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 42 66 +# CHECK-UNKNOWN: 66422457 vmclr.m v8 # CHECK-INST: vmclr.m v8 # CHECK-ENCODING: [0x57,0x24,0x84,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 84 6e +# CHECK-UNKNOWN: 6e842457 vmset.m v8 # CHECK-INST: vmset.m v8 # CHECK-ENCODING: [0x57,0x24,0x84,0x7e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 84 7e +# CHECK-UNKNOWN: 7e842457 vmnot.m v8, v4 # CHECK-INST: vmnot.m v8, v4 # CHECK-ENCODING: [0x57,0x24,0x42,0x76] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 42 76 +# CHECK-UNKNOWN: 76422457 diff --git a/llvm/test/MC/RISCV/rvv/minmax.s b/llvm/test/MC/RISCV/rvv/minmax.s index 4eaf897b84c4..70fe040f07f9 100644 --- a/llvm/test/MC/RISCV/rvv/minmax.s +++ b/llvm/test/MC/RISCV/rvv/minmax.s @@ -12,94 +12,94 @@ vminu.vv v8, v4, v20, v0.t # CHECK-INST: vminu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x10] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 10 +# CHECK-UNKNOWN: 104a0457 vminu.vv v8, v4, v20 # CHECK-INST: vminu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x12] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 12 +# CHECK-UNKNOWN: 124a0457 vminu.vx v8, v4, a0, v0.t # CHECK-INST: vminu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x10] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 10 +# CHECK-UNKNOWN: 10454457 vminu.vx v8, v4, a0 # CHECK-INST: vminu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x12] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 12 +# CHECK-UNKNOWN: 12454457 vmin.vv v8, v4, v20, v0.t # CHECK-INST: vmin.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x14] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 14 +# CHECK-UNKNOWN: 144a0457 vmin.vv v8, v4, v20 # CHECK-INST: vmin.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x16] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 16 +# CHECK-UNKNOWN: 164a0457 vmin.vx v8, v4, a0, v0.t # CHECK-INST: vmin.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x14] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 14 +# CHECK-UNKNOWN: 14454457 vmin.vx v8, v4, a0 # CHECK-INST: vmin.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x16] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 16 +# CHECK-UNKNOWN: 16454457 vmaxu.vv v8, v4, v20, v0.t # CHECK-INST: vmaxu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x18] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 18 +# CHECK-UNKNOWN: 184a0457 vmaxu.vv v8, v4, v20 # CHECK-INST: vmaxu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 1a +# CHECK-UNKNOWN: 1a4a0457 vmaxu.vx v8, v4, a0, v0.t # CHECK-INST: vmaxu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x18] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 18 +# CHECK-UNKNOWN: 18454457 vmaxu.vx v8, v4, a0 # CHECK-INST: vmaxu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 1a +# CHECK-UNKNOWN: 1a454457 vmax.vv v8, v4, v20, v0.t # CHECK-INST: vmax.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x1c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 1c +# CHECK-UNKNOWN: 1c4a0457 vmax.vv v8, v4, v20 # CHECK-INST: vmax.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x1e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 1e +# CHECK-UNKNOWN: 1e4a0457 vmax.vx v8, v4, a0, v0.t # CHECK-INST: vmax.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x1c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 1c +# CHECK-UNKNOWN: 1c454457 vmax.vx v8, v4, a0 # CHECK-INST: vmax.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x1e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 1e +# CHECK-UNKNOWN: 1e454457 diff --git a/llvm/test/MC/RISCV/rvv/mul.s b/llvm/test/MC/RISCV/rvv/mul.s index 9f7d6182d80f..2782ea683f9c 100644 --- a/llvm/test/MC/RISCV/rvv/mul.s +++ b/llvm/test/MC/RISCV/rvv/mul.s @@ -12,190 +12,190 @@ vmul.vv v8, v4, v20, v0.t # CHECK-INST: vmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x94] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 94 +# CHECK-UNKNOWN: 944a2457 vmul.vv v8, v4, v20 # CHECK-INST: vmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x96] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 96 +# CHECK-UNKNOWN: 964a2457 vmul.vx v8, v4, a0, v0.t # CHECK-INST: vmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x94] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 94 +# CHECK-UNKNOWN: 94456457 vmul.vx v8, v4, a0 # CHECK-INST: vmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x96] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 96 +# CHECK-UNKNOWN: 96456457 vmulh.vv v8, v4, v20, v0.t # CHECK-INST: vmulh.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x9c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 9c +# CHECK-UNKNOWN: 9c4a2457 vmulh.vv v8, v4, v20 # CHECK-INST: vmulh.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 9e +# CHECK-UNKNOWN: 9e4a2457 vmulh.vx v8, v4, a0, v0.t # CHECK-INST: vmulh.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x9c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 9c +# CHECK-UNKNOWN: 9c456457 vmulh.vx v8, v4, a0 # CHECK-INST: vmulh.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 9e +# CHECK-UNKNOWN: 9e456457 vmulhu.vv v8, v4, v20, v0.t # CHECK-INST: vmulhu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x90] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 90 +# CHECK-UNKNOWN: 904a2457 vmulhu.vv v8, v4, v20 # CHECK-INST: vmulhu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x92] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 92 +# CHECK-UNKNOWN: 924a2457 vmulhu.vx v8, v4, a0, v0.t # CHECK-INST: vmulhu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x90] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 90 +# CHECK-UNKNOWN: 90456457 vmulhu.vx v8, v4, a0 # CHECK-INST: vmulhu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x92] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 92 +# CHECK-UNKNOWN: 92456457 vmulhsu.vv v8, v4, v20, v0.t # CHECK-INST: vmulhsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x98] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 98 +# CHECK-UNKNOWN: 984a2457 vmulhsu.vv v8, v4, v20 # CHECK-INST: vmulhsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x9a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 9a +# CHECK-UNKNOWN: 9a4a2457 vmulhsu.vx v8, v4, a0, v0.t # CHECK-INST: vmulhsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x98] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 98 +# CHECK-UNKNOWN: 98456457 vmulhsu.vx v8, v4, a0 # CHECK-INST: vmulhsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x9a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 9a +# CHECK-UNKNOWN: 9a456457 vwmul.vv v8, v4, v20, v0.t # CHECK-INST: vwmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a ec +# CHECK-UNKNOWN: ec4a2457 vwmul.vv v8, v4, v20 # CHECK-INST: vwmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a ee +# CHECK-UNKNOWN: ee4a2457 vwmul.vx v8, v4, a0, v0.t # CHECK-INST: vwmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 ec +# CHECK-UNKNOWN: ec456457 vwmul.vx v8, v4, a0 # CHECK-INST: vwmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 ee +# CHECK-UNKNOWN: ee456457 vwmulu.vv v8, v4, v20, v0.t # CHECK-INST: vwmulu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a e0 +# CHECK-UNKNOWN: e04a2457 vwmulu.vv v8, v4, v20 # CHECK-INST: vwmulu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a e2 +# CHECK-UNKNOWN: e24a2457 vwmulu.vx v8, v4, a0, v0.t # CHECK-INST: vwmulu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 e0 +# CHECK-UNKNOWN: e0456457 vwmulu.vx v8, v4, a0 # CHECK-INST: vwmulu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 e2 +# CHECK-UNKNOWN: e2456457 vwmulsu.vv v8, v4, v20, v0.t # CHECK-INST: vwmulsu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a e8 +# CHECK-UNKNOWN: e84a2457 vwmulsu.vv v8, v4, v20 # CHECK-INST: vwmulsu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a ea +# CHECK-UNKNOWN: ea4a2457 vwmulsu.vx v8, v4, a0, v0.t # CHECK-INST: vwmulsu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 e8 +# CHECK-UNKNOWN: e8456457 vwmulsu.vx v8, v4, a0 # CHECK-INST: vwmulsu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 ea +# CHECK-UNKNOWN: ea456457 vsmul.vv v8, v4, v20, v0.t # CHECK-INST: vsmul.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x9c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 9c +# CHECK-UNKNOWN: 9c4a0457 vsmul.vv v8, v4, v20 # CHECK-INST: vsmul.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x9e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 9e +# CHECK-UNKNOWN: 9e4a0457 vsmul.vx v8, v4, a0, v0.t # CHECK-INST: vsmul.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x9c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 9c +# CHECK-UNKNOWN: 9c454457 vsmul.vx v8, v4, a0 # CHECK-INST: vsmul.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x9e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 9e +# CHECK-UNKNOWN: 9e454457 diff --git a/llvm/test/MC/RISCV/rvv/mv.s b/llvm/test/MC/RISCV/rvv/mv.s index cd02aa94d18e..f96e14932ead 100644 --- a/llvm/test/MC/RISCV/rvv/mv.s +++ b/llvm/test/MC/RISCV/rvv/mv.s @@ -12,52 +12,52 @@ vmv.v.v v8, v20 # CHECK-INST: vmv.v.v v8, v20 # CHECK-ENCODING: [0x57,0x04,0x0a,0x5e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 0a 5e +# CHECK-UNKNOWN: 5e0a0457 vmv.v.x v8, a0 # CHECK-INST: vmv.v.x v8, a0 # CHECK-ENCODING: [0x57,0x44,0x05,0x5e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 05 5e +# CHECK-UNKNOWN: 5e054457 vmv.v.i v8, 15 # CHECK-INST: vmv.v.i v8, 15 # CHECK-ENCODING: [0x57,0xb4,0x07,0x5e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 07 5e +# CHECK-UNKNOWN: 5e07b457 vmv.x.s a2, v4 # CHECK-INST: vmv.x.s a2, v4 # CHECK-ENCODING: [0x57,0x26,0x40,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 26 40 42 +# CHECK-UNKNOWN: 42402657 vmv.s.x v8, a0 # CHECK-INST: vmv.s.x v8, a0 # CHECK-ENCODING: [0x57,0x64,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 05 42 +# CHECK-UNKNOWN: 42056457 vmv1r.v v8, v4 # CHECK-INST: vmv1r.v v8, v4 # CHECK-ENCODING: [0x57,0x34,0x40,0x9e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 34 40 9e +# CHECK-UNKNOWN: 9e403457 vmv2r.v v8, v4 # CHECK-INST: vmv2r.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x40,0x9e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 40 9e +# CHECK-UNKNOWN: 9e40b457 vmv4r.v v8, v4 # CHECK-INST: vmv4r.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x41,0x9e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 41 9e +# CHECK-UNKNOWN: 9e41b457 vmv8r.v v8, v24 # CHECK-INST: vmv8r.v v8, v24 # CHECK-ENCODING: [0x57,0xb4,0x83,0x9f] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 83 9f +# CHECK-UNKNOWN: 9f83b457 diff --git a/llvm/test/MC/RISCV/rvv/or.s b/llvm/test/MC/RISCV/rvv/or.s index ef281fe80bd4..306d7ae81442 100644 --- a/llvm/test/MC/RISCV/rvv/or.s +++ b/llvm/test/MC/RISCV/rvv/or.s @@ -12,34 +12,34 @@ vor.vv v8, v4, v20, v0.t # CHECK-INST: vor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 28 +# CHECK-UNKNOWN: 284a0457 vor.vv v8, v4, v20 # CHECK-INST: vor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 2a +# CHECK-UNKNOWN: 2a4a0457 vor.vx v8, v4, a0, v0.t # CHECK-INST: vor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 28 +# CHECK-UNKNOWN: 28454457 vor.vx v8, v4, a0 # CHECK-INST: vor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 2a +# CHECK-UNKNOWN: 2a454457 vor.vi v8, v4, 15, v0.t # CHECK-INST: vor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 28 +# CHECK-UNKNOWN: 2847b457 vor.vi v8, v4, 15 # CHECK-INST: vor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 2a +# CHECK-UNKNOWN: 2a47b457 diff --git a/llvm/test/MC/RISCV/rvv/others.s b/llvm/test/MC/RISCV/rvv/others.s index d1845e0bb238..cc16a8774b82 100644 --- a/llvm/test/MC/RISCV/rvv/others.s +++ b/llvm/test/MC/RISCV/rvv/others.s @@ -12,142 +12,142 @@ vmerge.vvm v8, v4, v20, v0 # CHECK-INST: vmerge.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x5c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 5c +# CHECK-UNKNOWN: 5c4a0457 vmerge.vxm v8, v4, a0, v0 # CHECK-INST: vmerge.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x5c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 5c +# CHECK-UNKNOWN: 5c454457 vmerge.vim v8, v4, 15, v0 # CHECK-INST: vmerge.vim v8, v4, 15, v0 # CHECK-ENCODING: [0x57,0xb4,0x47,0x5c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 5c +# CHECK-UNKNOWN: 5c47b457 vslideup.vx v8, v4, a0, v0.t # CHECK-INST: vslideup.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x38] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 38 +# CHECK-UNKNOWN: 38454457 vslideup.vx v8, v4, a0 # CHECK-INST: vslideup.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 3a +# CHECK-UNKNOWN: 3a454457 vslideup.vi v8, v4, 31, v0.t # CHECK-INST: vslideup.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x38] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 38 +# CHECK-UNKNOWN: 384fb457 vslideup.vi v8, v4, 31 # CHECK-INST: vslideup.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 3a +# CHECK-UNKNOWN: 3a4fb457 vslidedown.vx v8, v4, a0, v0.t # CHECK-INST: vslidedown.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x3c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 3c +# CHECK-UNKNOWN: 3c454457 vslidedown.vx v8, v4, a0 # CHECK-INST: vslidedown.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x3e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 3e +# CHECK-UNKNOWN: 3e454457 vslidedown.vi v8, v4, 31, v0.t # CHECK-INST: vslidedown.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 3c +# CHECK-UNKNOWN: 3c4fb457 vslidedown.vi v8, v4, 31 # CHECK-INST: vslidedown.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x3e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 3e +# CHECK-UNKNOWN: 3e4fb457 vslide1up.vx v8, v4, a0, v0.t # CHECK-INST: vslide1up.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x38] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 38 +# CHECK-UNKNOWN: 38456457 vslide1up.vx v8, v4, a0 # CHECK-INST: vslide1up.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 3a +# CHECK-UNKNOWN: 3a456457 vslide1down.vx v8, v4, a0, v0.t # CHECK-INST: vslide1down.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x3c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 3c +# CHECK-UNKNOWN: 3c456457 vslide1down.vx v8, v4, a0 # CHECK-INST: vslide1down.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x3e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 3e +# CHECK-UNKNOWN: 3e456457 vrgather.vv v8, v4, v20, v0.t # CHECK-INST: vrgather.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x30] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 30 +# CHECK-UNKNOWN: 304a0457 vrgather.vv v8, v4, v20 # CHECK-INST: vrgather.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x32] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 32 +# CHECK-UNKNOWN: 324a0457 vrgather.vx v8, v4, a0, v0.t # CHECK-INST: vrgather.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x30] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 30 +# CHECK-UNKNOWN: 30454457 vrgather.vx v8, v4, a0 # CHECK-INST: vrgather.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x32] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 32 +# CHECK-UNKNOWN: 32454457 vrgather.vi v8, v4, 31, v0.t # CHECK-INST: vrgather.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x30] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 30 +# CHECK-UNKNOWN: 304fb457 vrgather.vi v8, v4, 31 # CHECK-INST: vrgather.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x32] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 32 +# CHECK-UNKNOWN: 324fb457 vrgatherei16.vv v8, v4, v20, v0.t # CHECK-INST: vrgatherei16.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x38] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 38 +# CHECK-UNKNOWN: 384a0457 vrgatherei16.vv v8, v4, v20 # CHECK-INST: vrgatherei16.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x3a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 3a +# CHECK-UNKNOWN: 3a4a0457 vcompress.vm v8, v4, v20 # CHECK-INST: vcompress.vm v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x5e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 5e +# CHECK-UNKNOWN: 5e4a2457 diff --git a/llvm/test/MC/RISCV/rvv/reduction.s b/llvm/test/MC/RISCV/rvv/reduction.s index 2172589b7c38..006f54d9b545 100644 --- a/llvm/test/MC/RISCV/rvv/reduction.s +++ b/llvm/test/MC/RISCV/rvv/reduction.s @@ -12,124 +12,124 @@ vredsum.vs v8, v4, v20, v0.t # CHECK-INST: vredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 00 +# CHECK-UNKNOWN: 004a2457 vredsum.vs v8, v4, v20 # CHECK-INST: vredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 02 +# CHECK-UNKNOWN: 024a2457 vredmaxu.vs v8, v4, v20, v0.t # CHECK-INST: vredmaxu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x18] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 18 +# CHECK-UNKNOWN: 184a2457 vredmaxu.vs v8, v4, v20 # CHECK-INST: vredmaxu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 1a +# CHECK-UNKNOWN: 1a4a2457 vredmax.vs v8, v4, v20, v0.t # CHECK-INST: vredmax.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x1c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 1c +# CHECK-UNKNOWN: 1c4a2457 vredmax.vs v8, v4, v20 # CHECK-INST: vredmax.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x1e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 1e +# CHECK-UNKNOWN: 1e4a2457 vredminu.vs v8, v4, v20, v0.t # CHECK-INST: vredminu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x10] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 10 +# CHECK-UNKNOWN: 104a2457 vredminu.vs v8, v4, v20 # CHECK-INST: vredminu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x12] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 12 +# CHECK-UNKNOWN: 124a2457 vredmin.vs v8, v4, v20, v0.t # CHECK-INST: vredmin.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x14] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 14 +# CHECK-UNKNOWN: 144a2457 vredmin.vs v8, v4, v20 # CHECK-INST: vredmin.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x16] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 16 +# CHECK-UNKNOWN: 164a2457 vredand.vs v8, v4, v20, v0.t # CHECK-INST: vredand.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 04 +# CHECK-UNKNOWN: 044a2457 vredand.vs v8, v4, v20 # CHECK-INST: vredand.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 06 +# CHECK-UNKNOWN: 064a2457 vredor.vs v8, v4, v20, v0.t # CHECK-INST: vredor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 08 +# CHECK-UNKNOWN: 084a2457 vredor.vs v8, v4, v20 # CHECK-INST: vredor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 0a +# CHECK-UNKNOWN: 0a4a2457 vredxor.vs v8, v4, v20, v0.t # CHECK-INST: vredxor.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 0c +# CHECK-UNKNOWN: 0c4a2457 vredxor.vs v8, v4, v20 # CHECK-INST: vredxor.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 0e +# CHECK-UNKNOWN: 0e4a2457 vwredsumu.vs v8, v4, v20, v0.t # CHECK-INST: vwredsumu.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a c0 +# CHECK-UNKNOWN: c04a0457 vwredsumu.vs v8, v4, v20 # CHECK-INST: vwredsumu.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a c2 +# CHECK-UNKNOWN: c24a0457 vwredsum.vs v8, v4, v20, v0.t # CHECK-INST: vwredsum.vs v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a c4 +# CHECK-UNKNOWN: c44a0457 vwredsum.vs v8, v4, v20 # CHECK-INST: vwredsum.vs v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a c6 +# CHECK-UNKNOWN: c64a0457 vredsum.vs v0, v4, v20, v0.t # CHECK-INST: vredsum.vs v0, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x20,0x4a,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 20 4a 00 +# CHECK-UNKNOWN: 004a2057 diff --git a/llvm/test/MC/RISCV/rvv/shift.s b/llvm/test/MC/RISCV/rvv/shift.s index 8a2e82f3c8fe..017e12499dc2 100644 --- a/llvm/test/MC/RISCV/rvv/shift.s +++ b/llvm/test/MC/RISCV/rvv/shift.s @@ -12,256 +12,256 @@ vsll.vv v8, v4, v20, v0.t # CHECK-INST: vsll.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x94] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 94 +# CHECK-UNKNOWN: 944a0457 vsll.vv v8, v4, v20 # CHECK-INST: vsll.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x96] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 96 +# CHECK-UNKNOWN: 964a0457 vsll.vx v8, v4, a0, v0.t # CHECK-INST: vsll.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x94] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 94 +# CHECK-UNKNOWN: 94454457 vsll.vx v8, v4, a0 # CHECK-INST: vsll.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x96] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 96 +# CHECK-UNKNOWN: 96454457 vsll.vi v8, v4, 31, v0.t # CHECK-INST: vsll.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x94] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 94 +# CHECK-UNKNOWN: 944fb457 vsll.vi v8, v4, 31 # CHECK-INST: vsll.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x96] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 96 +# CHECK-UNKNOWN: 964fb457 vsrl.vv v8, v4, v20, v0.t # CHECK-INST: vsrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a a0 +# CHECK-UNKNOWN: a04a0457 vsrl.vv v8, v4, v20 # CHECK-INST: vsrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a a2 +# CHECK-UNKNOWN: a24a0457 vsrl.vx v8, v4, a0, v0.t # CHECK-INST: vsrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 a0 +# CHECK-UNKNOWN: a0454457 vsrl.vx v8, v4, a0 # CHECK-INST: vsrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 a2 +# CHECK-UNKNOWN: a2454457 vsrl.vi v8, v4, 31, v0.t # CHECK-INST: vsrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f a0 +# CHECK-UNKNOWN: a04fb457 vsrl.vi v8, v4, 31 # CHECK-INST: vsrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f a2 +# CHECK-UNKNOWN: a24fb457 vsra.vv v8, v4, v20, v0.t # CHECK-INST: vsra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a a4 +# CHECK-UNKNOWN: a44a0457 vsra.vv v8, v4, v20 # CHECK-INST: vsra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a a6 +# CHECK-UNKNOWN: a64a0457 vsra.vx v8, v4, a0, v0.t # CHECK-INST: vsra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 a4 +# CHECK-UNKNOWN: a4454457 vsra.vx v8, v4, a0 # CHECK-INST: vsra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 a6 +# CHECK-UNKNOWN: a6454457 vsra.vi v8, v4, 31, v0.t # CHECK-INST: vsra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f a4 +# CHECK-UNKNOWN: a44fb457 vsra.vi v8, v4, 31 # CHECK-INST: vsra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f a6 +# CHECK-UNKNOWN: a64fb457 vnsrl.wv v8, v4, v20, v0.t # CHECK-INST: vnsrl.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a b0 +# CHECK-UNKNOWN: b04a0457 vnsrl.wv v4, v4, v20, v0.t # CHECK-INST: vnsrl.wv v4, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x02,0x4a,0xb0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 02 4a b0 +# CHECK-UNKNOWN: b04a0257 vnsrl.wv v8, v4, v20 # CHECK-INST: vnsrl.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a b2 +# CHECK-UNKNOWN: b24a0457 vnsrl.wx v8, v4, a0, v0.t # CHECK-INST: vnsrl.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 b0 +# CHECK-UNKNOWN: b0454457 vnsrl.wx v8, v4, a0 # CHECK-INST: vnsrl.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 b2 +# CHECK-UNKNOWN: b2454457 vnsrl.wi v8, v4, 31, v0.t # CHECK-INST: vnsrl.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f b0 +# CHECK-UNKNOWN: b04fb457 vnsrl.wi v8, v4, 31 # CHECK-INST: vnsrl.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f b2 +# CHECK-UNKNOWN: b24fb457 vnsra.wv v8, v4, v20, v0.t # CHECK-INST: vnsra.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xb4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a b4 +# CHECK-UNKNOWN: b44a0457 vnsra.wv v8, v4, v20 # CHECK-INST: vnsra.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xb6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a b6 +# CHECK-UNKNOWN: b64a0457 vnsra.wx v8, v4, a0, v0.t # CHECK-INST: vnsra.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xb4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 b4 +# CHECK-UNKNOWN: b4454457 vnsra.wx v8, v4, a0 # CHECK-INST: vnsra.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xb6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 b6 +# CHECK-UNKNOWN: b6454457 vnsra.wi v8, v4, 31, v0.t # CHECK-INST: vnsra.wi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f b4 +# CHECK-UNKNOWN: b44fb457 vnsra.wi v8, v4, 31 # CHECK-INST: vnsra.wi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xb6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f b6 +# CHECK-UNKNOWN: b64fb457 vssrl.vv v8, v4, v20, v0.t # CHECK-INST: vssrl.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a a8 +# CHECK-UNKNOWN: a84a0457 vssrl.vv v8, v4, v20 # CHECK-INST: vssrl.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a aa +# CHECK-UNKNOWN: aa4a0457 vssrl.vx v8, v4, a0, v0.t # CHECK-INST: vssrl.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 a8 +# CHECK-UNKNOWN: a8454457 vssrl.vx v8, v4, a0 # CHECK-INST: vssrl.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 aa +# CHECK-UNKNOWN: aa454457 vssrl.vi v8, v4, 31, v0.t # CHECK-INST: vssrl.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f a8 +# CHECK-UNKNOWN: a84fb457 vssrl.vi v8, v4, 31 # CHECK-INST: vssrl.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f aa +# CHECK-UNKNOWN: aa4fb457 vssra.vv v8, v4, v20, v0.t # CHECK-INST: vssra.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a ac +# CHECK-UNKNOWN: ac4a0457 vssra.vv v8, v4, v20 # CHECK-INST: vssra.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a ae +# CHECK-UNKNOWN: ae4a0457 vssra.vx v8, v4, a0, v0.t # CHECK-INST: vssra.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 ac +# CHECK-UNKNOWN: ac454457 vssra.vx v8, v4, a0 # CHECK-INST: vssra.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 ae +# CHECK-UNKNOWN: ae454457 vssra.vi v8, v4, 31, v0.t # CHECK-INST: vssra.vi v8, v4, 31, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f ac +# CHECK-UNKNOWN: ac4fb457 vssra.vi v8, v4, 31 # CHECK-INST: vssra.vi v8, v4, 31 # CHECK-ENCODING: [0x57,0xb4,0x4f,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f ae +# CHECK-UNKNOWN: ae4fb457 diff --git a/llvm/test/MC/RISCV/rvv/sign-injection.s b/llvm/test/MC/RISCV/rvv/sign-injection.s index 96d37c42d208..23e9be868a42 100644 --- a/llvm/test/MC/RISCV/rvv/sign-injection.s +++ b/llvm/test/MC/RISCV/rvv/sign-injection.s @@ -15,70 +15,70 @@ vfsgnj.vv v8, v4, v20, v0.t # CHECK-INST: vfsgnj.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x20] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 20 +# CHECK-UNKNOWN: 204a1457 vfsgnj.vv v8, v4, v20 # CHECK-INST: vfsgnj.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x22] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 22 +# CHECK-UNKNOWN: 224a1457 vfsgnj.vf v8, v4, fa0, v0.t # CHECK-INST: vfsgnj.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x20] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 20 +# CHECK-UNKNOWN: 20455457 vfsgnj.vf v8, v4, fa0 # CHECK-INST: vfsgnj.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x22] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 22 +# CHECK-UNKNOWN: 22455457 vfsgnjn.vv v8, v4, v20, v0.t # CHECK-INST: vfsgnjn.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x24] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 24 +# CHECK-UNKNOWN: 244a1457 vfsgnjn.vv v8, v4, v20 # CHECK-INST: vfsgnjn.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x26] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 26 +# CHECK-UNKNOWN: 264a1457 vfsgnjn.vf v8, v4, fa0, v0.t # CHECK-INST: vfsgnjn.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 24 +# CHECK-UNKNOWN: 24455457 vfsgnjn.vf v8, v4, fa0 # CHECK-INST: vfsgnjn.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 26 +# CHECK-UNKNOWN: 26455457 vfsgnjx.vv v8, v4, v20, v0.t # CHECK-INST: vfsgnjx.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0x28] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 28 +# CHECK-UNKNOWN: 284a1457 vfsgnjx.vv v8, v4, v20 # CHECK-INST: vfsgnjx.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x14,0x4a,0x2a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 14 4a 2a +# CHECK-UNKNOWN: 2a4a1457 vfsgnjx.vf v8, v4, fa0, v0.t # CHECK-INST: vfsgnjx.vf v8, v4, fa0, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0x28] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 28 +# CHECK-UNKNOWN: 28455457 vfsgnjx.vf v8, v4, fa0 # CHECK-INST: vfsgnjx.vf v8, v4, fa0 # CHECK-ENCODING: [0x57,0x54,0x45,0x2a] # CHECK-ERROR: instruction requires the following: 'V'{{.*}}'Zve32f' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 54 45 2a +# CHECK-UNKNOWN: 2a455457 diff --git a/llvm/test/MC/RISCV/rvv/snippet.s b/llvm/test/MC/RISCV/rvv/snippet.s index c032e468dede..c3e57e193f84 100644 --- a/llvm/test/MC/RISCV/rvv/snippet.s +++ b/llvm/test/MC/RISCV/rvv/snippet.s @@ -6,27 +6,27 @@ loop: vsetvli a3, a0, e16,m4,ta,ma # vtype = 16-bit integer vectors -# CHECK-INST: d7 76 a5 0c vsetvli a3, a0, e16, m4, ta, ma +# CHECK-INST: 0ca576d7 vsetvli a3, a0, e16, m4, ta, ma vle16.v v4, (a1) # Get 16b vector -# CHECK-INST: 07 d2 05 02 vle16.v v4, (a1) +# CHECK-INST: 0205d207 vle16.v v4, (a1) slli t1, a3, 1 # Multiply length by two bytes/element -# CHECK-INST: 13 93 16 00 slli t1, a3, 0x1 +# CHECK-INST: 00169313 slli t1, a3, 0x1 add a1, a1, t1 # Bump pointer -# CHECK-INST: b3 85 65 00 add a1, a1, t1 +# CHECK-INST: 006585b3 add a1, a1, t1 vwmul.vx v8, v4, x10 # 32b in -# CHECK-INST: 57 64 45 ee vwmul.vx v8, v4, a0 +# CHECK-INST: ee456457 vwmul.vx v8, v4, a0 vsetvli x0, a0, e32,m8,ta,ma # Operate on 32b values -# CHECK-INST: 57 70 35 0d vsetvli zero, a0, e32, m8, ta, ma +# CHECK-INST: 0d357057 vsetvli zero, a0, e32, m8, ta, ma vsrl.vi v8, v8, 3 -# CHECK-INST: 57 b4 81 a2 vsrl.vi v8, v8, 0x3 +# CHECK-INST: a281b457 vsrl.vi v8, v8, 0x3 vse32.v v8, (a2) # Store vector of 32b -# CHECK-INST: 27 64 06 02 vse32.v v8, (a2) +# CHECK-INST: 02066427 vse32.v v8, (a2) slli t1, a3, 2 # Multiply length by four bytes/element -# CHECK-INST: 13 93 26 00 slli t1, a3, 0x2 +# CHECK-INST: 00269313 slli t1, a3, 0x2 add a2, a2, t1 # Bump pointer -# CHECK-INST: 33 06 66 00 add a2, a2, t1 +# CHECK-INST: 00660633 add a2, a2, t1 sub a0, a0, a3 # Decrement count -# CHECK-INST: 33 05 d5 40 sub a0, a0, a3 +# CHECK-INST: 40d50533 sub a0, a0, a3 bnez a0, loop # Any more? -# CHECK-INST: e3 1a 05 fc bnez a0, 0x0 +# CHECK-INST: fc051ae3 bnez a0, 0x0 diff --git a/llvm/test/MC/RISCV/rvv/store.s b/llvm/test/MC/RISCV/rvv/store.s index a38f19f266fa..c6a34705fa4a 100644 --- a/llvm/test/MC/RISCV/rvv/store.s +++ b/llvm/test/MC/RISCV/rvv/store.s @@ -12,250 +12,250 @@ vsm.v v24, (a0) # CHECK-INST: vsm.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0xb5,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 02 +# CHECK-UNKNOWN: 02b50c27 vse8.v v24, (a0), v0.t # CHECK-INST: vse8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 00 +# CHECK-UNKNOWN: 00050c27 vse8.v v24, (a0) # CHECK-INST: vse8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 02 +# CHECK-UNKNOWN: 02050c27 vse16.v v24, (a0), v0.t # CHECK-INST: vse16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 00 +# CHECK-UNKNOWN: 00055c27 vse16.v v24, (a0) # CHECK-INST: vse16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 02 +# CHECK-UNKNOWN: 02055c27 vse32.v v24, (a0), v0.t # CHECK-INST: vse32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 00 +# CHECK-UNKNOWN: 00056c27 vse32.v v24, (a0) # CHECK-INST: vse32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 02 +# CHECK-UNKNOWN: 02056c27 vse64.v v24, (a0), v0.t # CHECK-INST: vse64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 00 +# CHECK-UNKNOWN: 00057c27 vse64.v v24, (a0) # CHECK-INST: vse64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 02 +# CHECK-UNKNOWN: 02057c27 vsse8.v v24, (a0), a1, v0.t # CHECK-INST: vsse8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 08 +# CHECK-UNKNOWN: 08b50c27 vsse8.v v24, (a0), a1 # CHECK-INST: vsse8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 0a +# CHECK-UNKNOWN: 0ab50c27 vsse16.v v24, (a0), a1, v0.t # CHECK-INST: vsse16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 08 +# CHECK-UNKNOWN: 08b55c27 vsse16.v v24, (a0), a1 # CHECK-INST: vsse16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 0a +# CHECK-UNKNOWN: 0ab55c27 vsse32.v v24, (a0), a1, v0.t # CHECK-INST: vsse32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 08 +# CHECK-UNKNOWN: 08b56c27 vsse32.v v24, (a0), a1 # CHECK-INST: vsse32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 0a +# CHECK-UNKNOWN: 0ab56c27 vsse64.v v24, (a0), a1, v0.t # CHECK-INST: vsse64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 08 +# CHECK-UNKNOWN: 08b57c27 vsse64.v v24, (a0), a1 # CHECK-INST: vsse64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 0a +# CHECK-UNKNOWN: 0ab57c27 vsuxei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 04 +# CHECK-UNKNOWN: 04450c27 vsuxei8.v v24, (a0), v4 # CHECK-INST: vsuxei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 06 +# CHECK-UNKNOWN: 06450c27 vsuxei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 04 +# CHECK-UNKNOWN: 04455c27 vsuxei16.v v24, (a0), v4 # CHECK-INST: vsuxei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 06 +# CHECK-UNKNOWN: 06455c27 vsuxei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 04 +# CHECK-UNKNOWN: 04456c27 vsuxei32.v v24, (a0), v4 # CHECK-INST: vsuxei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 06 +# CHECK-UNKNOWN: 06456c27 vsuxei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 04 +# CHECK-UNKNOWN: 04457c27 vsuxei64.v v24, (a0), v4 # CHECK-INST: vsuxei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x06] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 06 +# CHECK-UNKNOWN: 06457c27 vsoxei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 0c +# CHECK-UNKNOWN: 0c450c27 vsoxei8.v v24, (a0), v4 # CHECK-INST: vsoxei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 0e +# CHECK-UNKNOWN: 0e450c27 vsoxei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 0c +# CHECK-UNKNOWN: 0c455c27 vsoxei16.v v24, (a0), v4 # CHECK-INST: vsoxei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 0e +# CHECK-UNKNOWN: 0e455c27 vsoxei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 0c +# CHECK-UNKNOWN: 0c456c27 vsoxei32.v v24, (a0), v4 # CHECK-INST: vsoxei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 0e +# CHECK-UNKNOWN: 0e456c27 vsoxei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 0c +# CHECK-UNKNOWN: 0c457c27 vsoxei64.v v24, (a0), v4 # CHECK-INST: vsoxei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 0e +# CHECK-UNKNOWN: 0e457c27 vs1r.v v24, (a0) # CHECK-INST: vs1r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 85 02 +# CHECK-UNKNOWN: 02850c27 vs2r.v v24, (a0) # CHECK-INST: vs2r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 85 22 +# CHECK-UNKNOWN: 22850c27 vs4r.v v24, (a0) # CHECK-INST: vs4r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 85 62 +# CHECK-UNKNOWN: 62850c27 vs8r.v v24, (a0) # CHECK-INST: vs8r.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x85,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 85 e2 +# CHECK-UNKNOWN: e2850c27 vsm.v v24, 0(a0) # CHECK-INST: vsm.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0xb5,0x02] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 02 +# CHECK-UNKNOWN: 02b50c27 vse8.v v24, 0(a0), v0.t # CHECK-INST: vse8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x00] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 00 +# CHECK-UNKNOWN: 00050c27 vsse16.v v24, 0(a0), a1, v0.t # CHECK-INST: vsse16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 08 +# CHECK-UNKNOWN: 08b55c27 vsuxei8.v v24, 0(a0), v4, v0.t # CHECK-INST: vsuxei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x04] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 04 +# CHECK-UNKNOWN: 04450c27 vsoxei32.v v24, 0(a0), v4, v0.t # CHECK-INST: vsoxei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 0c +# CHECK-UNKNOWN: 0c456c27 diff --git a/llvm/test/MC/RISCV/rvv/sub.s b/llvm/test/MC/RISCV/rvv/sub.s index 3cc75ae730e7..6a637d9207ee 100644 --- a/llvm/test/MC/RISCV/rvv/sub.s +++ b/llvm/test/MC/RISCV/rvv/sub.s @@ -12,298 +12,298 @@ vsub.vv v8, v4, v20, v0.t # CHECK-INST: vsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 08 +# CHECK-UNKNOWN: 084a0457 vsub.vv v8, v4, v20 # CHECK-INST: vsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 0a +# CHECK-UNKNOWN: 0a4a0457 vsub.vx v8, v4, a0, v0.t # CHECK-INST: vsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x08] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 08 +# CHECK-UNKNOWN: 08454457 vsub.vx v8, v4, a0 # CHECK-INST: vsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 0a +# CHECK-UNKNOWN: 0a454457 vrsub.vx v8, v4, a0, v0.t # CHECK-INST: vrsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 0c +# CHECK-UNKNOWN: 0c454457 vrsub.vx v8, v4, a0 # CHECK-INST: vrsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 0e +# CHECK-UNKNOWN: 0e454457 vrsub.vi v8, v4, 15, v0.t # CHECK-INST: vrsub.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x0c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 0c +# CHECK-UNKNOWN: 0c47b457 vrsub.vi v8, v4, 15 # CHECK-INST: vrsub.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x0e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 0e +# CHECK-UNKNOWN: 0e47b457 vwsubu.vv v8, v4, v20, v0.t # CHECK-INST: vwsubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a c8 +# CHECK-UNKNOWN: c84a2457 vwsubu.vv v8, v4, v20 # CHECK-INST: vwsubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a ca +# CHECK-UNKNOWN: ca4a2457 vwsubu.vx v8, v4, a0, v0.t # CHECK-INST: vwsubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 c8 +# CHECK-UNKNOWN: c8456457 vwsubu.vx v8, v4, a0 # CHECK-INST: vwsubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 ca +# CHECK-UNKNOWN: ca456457 vwsub.vv v8, v4, v20, v0.t # CHECK-INST: vwsub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a cc +# CHECK-UNKNOWN: cc4a2457 vwsub.vv v8, v4, v20 # CHECK-INST: vwsub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a ce +# CHECK-UNKNOWN: ce4a2457 vwsub.vx v8, v4, a0, v0.t # CHECK-INST: vwsub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 cc +# CHECK-UNKNOWN: cc456457 vwsub.vx v8, v4, a0 # CHECK-INST: vwsub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 ce +# CHECK-UNKNOWN: ce456457 vwsubu.wv v8, v4, v20, v0.t # CHECK-INST: vwsubu.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xd8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a d8 +# CHECK-UNKNOWN: d84a2457 vwsubu.wv v8, v4, v20 # CHECK-INST: vwsubu.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xda] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a da +# CHECK-UNKNOWN: da4a2457 vwsubu.wx v8, v4, a0, v0.t # CHECK-INST: vwsubu.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xd8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 d8 +# CHECK-UNKNOWN: d8456457 vwsubu.wx v8, v4, a0 # CHECK-INST: vwsubu.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xda] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 da +# CHECK-UNKNOWN: da456457 vwsub.wv v8, v4, v20, v0.t # CHECK-INST: vwsub.wv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0xdc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a dc +# CHECK-UNKNOWN: dc4a2457 vwsub.wv v8, v4, v20 # CHECK-INST: vwsub.wv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0xde] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a de +# CHECK-UNKNOWN: de4a2457 vwsub.wx v8, v4, a0, v0.t # CHECK-INST: vwsub.wx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0xdc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 dc +# CHECK-UNKNOWN: dc456457 vwsub.wx v8, v4, a0 # CHECK-INST: vwsub.wx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0xde] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 de +# CHECK-UNKNOWN: de456457 vsbc.vvm v8, v4, v20, v0 # CHECK-INST: vsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 48 +# CHECK-UNKNOWN: 484a0457 vsbc.vvm v4, v4, v20, v0 # CHECK-INST: vsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 02 4a 48 +# CHECK-UNKNOWN: 484a0257 vsbc.vvm v8, v4, v8, v0 # CHECK-INST: vsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 44 48 +# CHECK-UNKNOWN: 48440457 vsbc.vxm v8, v4, a0, v0 # CHECK-INST: vsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 48 +# CHECK-UNKNOWN: 48454457 vmsbc.vvm v8, v4, v20, v0 # CHECK-INST: vmsbc.vvm v8, v4, v20, v0 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 4c +# CHECK-UNKNOWN: 4c4a0457 vmsbc.vvm v4, v4, v20, v0 # CHECK-INST: vmsbc.vvm v4, v4, v20, v0 # CHECK-ENCODING: [0x57,0x02,0x4a,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 02 4a 4c +# CHECK-UNKNOWN: 4c4a0257 vmsbc.vvm v8, v4, v8, v0 # CHECK-INST: vmsbc.vvm v8, v4, v8, v0 # CHECK-ENCODING: [0x57,0x04,0x44,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 44 4c +# CHECK-UNKNOWN: 4c440457 vmsbc.vxm v8, v4, a0, v0 # CHECK-INST: vmsbc.vxm v8, v4, a0, v0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 4c +# CHECK-UNKNOWN: 4c454457 vmsbc.vv v8, v4, v20 # CHECK-INST: vmsbc.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 4e +# CHECK-UNKNOWN: 4e4a0457 vmsbc.vx v8, v4, a0 # CHECK-INST: vmsbc.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 4e +# CHECK-UNKNOWN: 4e454457 vssubu.vv v8, v4, v20, v0.t # CHECK-INST: vssubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 88 +# CHECK-UNKNOWN: 884a0457 vssubu.vv v8, v4, v20 # CHECK-INST: vssubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 8a +# CHECK-UNKNOWN: 8a4a0457 vssubu.vx v8, v4, a0, v0.t # CHECK-INST: vssubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 88 +# CHECK-UNKNOWN: 88454457 vssubu.vx v8, v4, a0 # CHECK-INST: vssubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 8a +# CHECK-UNKNOWN: 8a454457 vssub.vv v8, v4, v20, v0.t # CHECK-INST: vssub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 8c +# CHECK-UNKNOWN: 8c4a0457 vssub.vv v8, v4, v20 # CHECK-INST: vssub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 8e +# CHECK-UNKNOWN: 8e4a0457 vssub.vx v8, v4, a0, v0.t # CHECK-INST: vssub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 8c +# CHECK-UNKNOWN: 8c454457 vssub.vx v8, v4, a0 # CHECK-INST: vssub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 8e +# CHECK-UNKNOWN: 8e454457 vasub.vv v8, v4, v20, v0.t # CHECK-INST: vasub.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 2c +# CHECK-UNKNOWN: 2c4a2457 vasub.vv v8, v4, v20 # CHECK-INST: vasub.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 2e +# CHECK-UNKNOWN: 2e4a2457 vasub.vx v8, v4, a0, v0.t # CHECK-INST: vasub.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 2c +# CHECK-UNKNOWN: 2c456457 vasub.vx v8, v4, a0 # CHECK-INST: vasub.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 2e +# CHECK-UNKNOWN: 2e456457 vasubu.vv v8, v4, v20, v0.t # CHECK-INST: vasubu.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x24,0x4a,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 28 +# CHECK-UNKNOWN: 284a2457 vasubu.vv v8, v4, v20 # CHECK-INST: vasubu.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x24,0x4a,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 24 4a 2a +# CHECK-UNKNOWN: 2a4a2457 vasubu.vx v8, v4, a0, v0.t # CHECK-INST: vasubu.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x64,0x45,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 28 +# CHECK-UNKNOWN: 28456457 vasubu.vx v8, v4, a0 # CHECK-INST: vasubu.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x64,0x45,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 64 45 2a +# CHECK-UNKNOWN: 2a456457 diff --git a/llvm/test/MC/RISCV/rvv/vsetvl.s b/llvm/test/MC/RISCV/rvv/vsetvl.s index 69a48d24f190..c9197d8917a4 100644 --- a/llvm/test/MC/RISCV/rvv/vsetvl.s +++ b/llvm/test/MC/RISCV/rvv/vsetvl.s @@ -13,149 +13,149 @@ vsetvli a2, a0, 0x224 # CHECK-INST: vsetvli a2, a0, 548 # CHECK-ENCODING: [0x57,0x76,0x45,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 45 22 +# CHECK-UNKNOWN: 22457657 vsetvli a2, a0, 0xd0 # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 0d +# CHECK-UNKNOWN: 0d057657 vsetvli a2, a0, 0xd1 # CHECK-INST: vsetvli a2, a0, e32, m2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x15,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 15 0d +# CHECK-UNKNOWN: 0d157657 vsetvli a2, a0, 0x50 # CHECK-INST: vsetvli a2, a0, e32, m1, ta, mu # CHECK-ENCODING: [0x57,0x76,0x05,0x05] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 05 +# CHECK-UNKNOWN: 05057657 vsetvli a2, a0, 0x90 # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 09 +# CHECK-UNKNOWN: 09057657 vsetvli a2, a0, 144 # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 09 +# CHECK-UNKNOWN: 09057657 vsetvli a2, a0, e32, m1, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 0d +# CHECK-UNKNOWN: 0d057657 vsetvli a2, a0, e32, m2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x15,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 15 0d +# CHECK-UNKNOWN: 0d157657 vsetvli a2, a0, e32, m4, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m4, ta, ma # CHECK-ENCODING: [0x57,0x76,0x25,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 25 0d +# CHECK-UNKNOWN: 0d257657 vsetvli a2, a0, e32, m8, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m8, ta, ma # CHECK-ENCODING: [0x57,0x76,0x35,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 35 0d +# CHECK-UNKNOWN: 0d357657 vsetvli a2, a0, e32, mf2, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf2, ta, ma # CHECK-ENCODING: [0x57,0x76,0x75,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 75 0d +# CHECK-UNKNOWN: 0d757657 vsetvli a2, a0, e32, mf4, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf4, ta, ma # CHECK-ENCODING: [0x57,0x76,0x65,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 65 0d +# CHECK-UNKNOWN: 0d657657 vsetvli a2, a0, e32, mf8, ta, ma # CHECK-INST: vsetvli a2, a0, e32, mf8, ta, ma # CHECK-ENCODING: [0x57,0x76,0x55,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 55 0d +# CHECK-UNKNOWN: 0d557657 vsetvli a2, a0, e32, m1, ta, ma # CHECK-INST: vsetvli a2, a0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x0d] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 0d +# CHECK-UNKNOWN: 0d057657 vsetvli a2, a0, e32, m1, tu, ma # CHECK-INST: vsetvli a2, a0, e32, m1, tu, ma # CHECK-ENCODING: [0x57,0x76,0x05,0x09] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 09 +# CHECK-UNKNOWN: 09057657 vsetvli a2, a0, e32, m1, ta, mu # CHECK-INST: vsetvli a2, a0, e32, m1, ta, mu # CHECK-ENCODING: [0x57,0x76,0x05,0x05] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 05 +# CHECK-UNKNOWN: 05057657 vsetvli a2, a0, e32, m1, tu, mu # CHECK-INST: vsetvli a2, a0, e32, m1 # CHECK-ENCODING: [0x57,0x76,0x05,0x01] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 05 01 +# CHECK-UNKNOWN: 01057657 vsetvl a2, a0, a1 # CHECK-INST: vsetvl a2, a0, a1 # CHECK-ENCODING: [0x57,0x76,0xb5,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 b5 80 +# CHECK-UNKNOWN: 80b57657 # reserved filed: vlmul[2:0]=4, vsew[2:0]=0b1xx, non-zero bits 8/9/10. vsetivli a2, 0, 0x224 # CHECK-INST: vsetivli a2, 0, 548 # CHECK-ENCODING: [0x57,0x76,0x40,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 40 e2 +# CHECK-UNKNOWN: e2407657 vsetivli a2, 0, 0xd0 # CHECK-INST: vsetivli a2, 0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x00,0xcd] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 00 cd +# CHECK-UNKNOWN: cd007657 vsetivli a2, 15, 0xd0 # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 f6 07 cd +# CHECK-UNKNOWN: cd07f657 vsetivli a2, 15, 208 # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 f6 07 cd +# CHECK-UNKNOWN: cd07f657 vsetivli a2, 0, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 0, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0x76,0x00,0xcd] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 76 00 cd +# CHECK-UNKNOWN: cd007657 vsetivli a2, 15, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 15, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x07,0xcd] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 f6 07 cd +# CHECK-UNKNOWN: cd07f657 vsetivli a2, 31, e32, m1, ta, ma # CHECK-INST: vsetivli a2, 31, e32, m1, ta, ma # CHECK-ENCODING: [0x57,0xf6,0x0f,0xcd] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 f6 0f cd +# CHECK-UNKNOWN: cd0ff657 diff --git a/llvm/test/MC/RISCV/rvv/xor.s b/llvm/test/MC/RISCV/rvv/xor.s index 5ea0f694e0d6..572388ed2267 100644 --- a/llvm/test/MC/RISCV/rvv/xor.s +++ b/llvm/test/MC/RISCV/rvv/xor.s @@ -12,46 +12,46 @@ vxor.vv v8, v4, v20, v0.t # CHECK-INST: vxor.vv v8, v4, v20, v0.t # CHECK-ENCODING: [0x57,0x04,0x4a,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 2c +# CHECK-UNKNOWN: 2c4a0457 vxor.vv v8, v4, v20 # CHECK-INST: vxor.vv v8, v4, v20 # CHECK-ENCODING: [0x57,0x04,0x4a,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 04 4a 2e +# CHECK-UNKNOWN: 2e4a0457 vxor.vx v8, v4, a0, v0.t # CHECK-INST: vxor.vx v8, v4, a0, v0.t # CHECK-ENCODING: [0x57,0x44,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 2c +# CHECK-UNKNOWN: 2c454457 vxor.vx v8, v4, a0 # CHECK-INST: vxor.vx v8, v4, a0 # CHECK-ENCODING: [0x57,0x44,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 44 45 2e +# CHECK-UNKNOWN: 2e454457 vxor.vi v8, v4, 15, v0.t # CHECK-INST: vxor.vi v8, v4, 15, v0.t # CHECK-ENCODING: [0x57,0xb4,0x47,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 2c +# CHECK-UNKNOWN: 2c47b457 vxor.vi v8, v4, 15 # CHECK-INST: vxor.vi v8, v4, 15 # CHECK-ENCODING: [0x57,0xb4,0x47,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 47 2e +# CHECK-UNKNOWN: 2e47b457 vnot.v v8, v4, v0.t # CHECK-INST: vnot.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0xb4,0x4f,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 2c +# CHECK-UNKNOWN: 2c4fb457 vnot.v v8, v4 # CHECK-INST: vnot.v v8, v4 # CHECK-ENCODING: [0x57,0xb4,0x4f,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 57 b4 4f 2e +# CHECK-UNKNOWN: 2e4fb457 diff --git a/llvm/test/MC/RISCV/rvv/xsfvcp.s b/llvm/test/MC/RISCV/rvv/xsfvcp.s index a137311f575a..4298bf7a7b7a 100644 --- a/llvm/test/MC/RISCV/rvv/xsfvcp.s +++ b/llvm/test/MC/RISCV/rvv/xsfvcp.s @@ -21,166 +21,166 @@ sf.vc.x 0x3, 0xf, 0x1f, a1 # CHECK-INST: sf.vc.x 3, 15, 31, a1 # CHECK-ENCODING: [0xdb,0xcf,0xf5,0x0e] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: db cf f5 0e +# CHECK-UNKNOWN: 0ef5cfdb sf.vc.i 0x3, 0xf, 0x1f, 15 # CHECK-INST: sf.vc.i 3, 15, 31, 15 # CHECK-ENCODING: [0xdb,0xbf,0xf7,0x0e] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: db bf f7 0e +# CHECK-UNKNOWN: 0ef7bfdb sf.vc.vv 0x3, 0x1f, v2, v1 # CHECK-INST: sf.vc.vv 3, 31, v2, v1 # CHECK-ENCODING: [0xdb,0x8f,0x20,0x2e] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: db 8f 20 2e +# CHECK-UNKNOWN: 2e208fdb sf.vc.xv 0x3, 0x1f, v2, a1 # CHECK-INST: sf.vc.xv 3, 31, v2, a1 # CHECK-ENCODING: [0xdb,0xcf,0x25,0x2e] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: db cf 25 2e +# CHECK-UNKNOWN: 2e25cfdb sf.vc.iv 0x3, 0x1f, v2, 15 # CHECK-INST: sf.vc.iv 3, 31, v2, 15 # CHECK-ENCODING: [0xdb,0xbf,0x27,0x2e] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: db bf 27 2e +# CHECK-UNKNOWN: 2e27bfdb sf.vc.fv 0x1, 0x1f, v2, fa1 # CHECK-INST: sf.vc.fv 1, 31, v2, fa1 # CHECK-ENCODING: [0xdb,0xdf,0x25,0x2e] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: db df 25 2e +# CHECK-UNKNOWN: 2e25dfdb sf.vc.vvv 0x3, v0, v2, v1 # CHECK-INST: sf.vc.vvv 3, v0, v2, v1 # CHECK-ENCODING: [0x5b,0x80,0x20,0xae] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b 80 20 ae +# CHECK-UNKNOWN: ae20805b sf.vc.xvv 0x3, v0, v2, a1 # CHECK-INST: sf.vc.xvv 3, v0, v2, a1 # CHECK-ENCODING: [0x5b,0xc0,0x25,0xae] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b c0 25 ae +# CHECK-UNKNOWN: ae25c05b sf.vc.ivv 0x3, v0, v2, 15 # CHECK-INST: sf.vc.ivv 3, v0, v2, 15 # CHECK-ENCODING: [0x5b,0xb0,0x27,0xae] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b b0 27 ae +# CHECK-UNKNOWN: ae27b05b sf.vc.fvv 0x1, v0, v2, fa1 # CHECK-INST: sf.vc.fvv 1, v0, v2, fa1 # CHECK-ENCODING: [0x5b,0xd0,0x25,0xae] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b d0 25 ae +# CHECK-UNKNOWN: ae25d05b sf.vc.vvw 0x3, v0, v2, v1 # CHECK-INST: sf.vc.vvw 3, v0, v2, v1 # CHECK-ENCODING: [0x5b,0x80,0x20,0xfe] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b 80 20 fe +# CHECK-UNKNOWN: fe20805b sf.vc.xvw 0x3, v0, v2, a1 # CHECK-INST: sf.vc.xvw 3, v0, v2, a1 # CHECK-ENCODING: [0x5b,0xc0,0x25,0xfe] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b c0 25 fe +# CHECK-UNKNOWN: fe25c05b sf.vc.ivw 0x3, v0, v2, 15 # CHECK-INST: sf.vc.ivw 3, v0, v2, 15 # CHECK-ENCODING: [0x5b,0xb0,0x27,0xfe] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b b0 27 fe +# CHECK-UNKNOWN: fe27b05b sf.vc.fvw 0x1, v0, v2, fa1 # CHECK-INST: sf.vc.fvw 1, v0, v2, fa1 # CHECK-ENCODING: [0x5b,0xd0,0x25,0xfe] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b d0 25 fe +# CHECK-UNKNOWN: fe25d05b sf.vc.v.x 0x3, 0xf, v0, a1 # CHECK-INST: sf.vc.v.x 3, 15, v0, a1 # CHECK-ENCODING: [0x5b,0xc0,0xf5,0x0c] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b c0 f5 0c +# CHECK-UNKNOWN: 0cf5c05b sf.vc.v.i 0x3, 0xf, v0, 15 # CHECK-INST: sf.vc.v.i 3, 15, v0, 15 # CHECK-ENCODING: [0x5b,0xb0,0xf7,0x0c] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b b0 f7 0c +# CHECK-UNKNOWN: 0cf7b05b sf.vc.v.vv 0x3, v0, v2, v1 # CHECK-INST: sf.vc.v.vv 3, v0, v2, v1 # CHECK-ENCODING: [0x5b,0x80,0x20,0x2c] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b 80 20 2c +# CHECK-UNKNOWN: 2c20805b sf.vc.v.xv 0x3, v0, v2, a1 # CHECK-INST: sf.vc.v.xv 3, v0, v2, a1 # CHECK-ENCODING: [0x5b,0xc0,0x25,0x2c] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b c0 25 2c +# CHECK-UNKNOWN: 2c25c05b sf.vc.v.iv 0x3, v0, v2, 15 # CHECK-INST: sf.vc.v.iv 3, v0, v2, 15 # CHECK-ENCODING: [0x5b,0xb0,0x27,0x2c] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b b0 27 2c +# CHECK-UNKNOWN: 2c27b05b sf.vc.v.fv 0x1, v0, v2, fa1 # CHECK-INST: sf.vc.v.fv 1, v0, v2, fa1 # CHECK-ENCODING: [0x5b,0xd0,0x25,0x2c] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b d0 25 2c +# CHECK-UNKNOWN: 2c25d05b sf.vc.v.vvv 0x3, v0, v2, v1 # CHECK-INST: sf.vc.v.vvv 3, v0, v2, v1 # CHECK-ENCODING: [0x5b,0x80,0x20,0xac] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b 80 20 ac +# CHECK-UNKNOWN: ac20805b sf.vc.v.xvv 0x3, v0, v2, a1 # CHECK-INST: sf.vc.v.xvv 3, v0, v2, a1 # CHECK-ENCODING: [0x5b,0xc0,0x25,0xac] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b c0 25 ac +# CHECK-UNKNOWN: ac25c05b sf.vc.v.ivv 0x3, v0, v2, 15 # CHECK-INST: sf.vc.v.ivv 3, v0, v2, 15 # CHECK-ENCODING: [0x5b,0xb0,0x27,0xac] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b b0 27 ac +# CHECK-UNKNOWN: ac27b05b sf.vc.v.fvv 0x1, v0, v2, fa1 # CHECK-INST: sf.vc.v.fvv 1, v0, v2, fa1 # CHECK-ENCODING: [0x5b,0xd0,0x25,0xac] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b d0 25 ac +# CHECK-UNKNOWN: ac25d05b sf.vc.v.vvw 0x3, v0, v2, v1 # CHECK-INST: sf.vc.v.vvw 3, v0, v2, v1 # CHECK-ENCODING: [0x5b,0x80,0x20,0xfc] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b 80 20 fc +# CHECK-UNKNOWN: fc20805b sf.vc.v.xvw 0x3, v0, v2, a1 # CHECK-INST: sf.vc.v.xvw 3, v0, v2, a1 # CHECK-ENCODING: [0x5b,0xc0,0x25,0xfc] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b c0 25 fc +# CHECK-UNKNOWN: fc25c05b sf.vc.v.ivw 0x3, v0, v2, 15 # CHECK-INST: sf.vc.v.ivw 3, v0, v2, 15 # CHECK-ENCODING: [0x5b,0xb0,0x27,0xfc] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b b0 27 fc +# CHECK-UNKNOWN: fc27b05b sf.vc.v.fvw 0x1, v0, v2, fa1 # CHECK-INST: sf.vc.v.fvw 1, v0, v2, fa1 # CHECK-ENCODING: [0x5b,0xd0,0x25,0xfc] # CHECK-ERROR: instruction requires the following: 'XSfvcp' (SiFive Custom Vector Coprocessor Interface Instructions){{$}} -# CHECK-UNKNOWN: 5b d0 25 fc +# CHECK-UNKNOWN: fc25d05b diff --git a/llvm/test/MC/RISCV/rvv/xsfvfnrclip.s b/llvm/test/MC/RISCV/rvv/xsfvfnrclip.s index d8b184659ac4..7508d44bc916 100644 --- a/llvm/test/MC/RISCV/rvv/xsfvfnrclip.s +++ b/llvm/test/MC/RISCV/rvv/xsfvfnrclip.s @@ -12,22 +12,22 @@ sf.vfnrclip.xu.f.qf v4, v8, fa2 # CHECK-INST: sf.vfnrclip.xu.f.qf v4, v8, fa2 # CHECK-ENCODING: [0x5b,0x52,0x86,0x8a] # CHECK-ERROR: instruction requires the following: 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions) -# CHECK-UNKNOWN: 5b 52 86 8a +# CHECK-UNKNOWN: 8a86525b sf.vfnrclip.xu.f.qf v4, v8, fa2, v0.t # CHECK-INST: sf.vfnrclip.xu.f.qf v4, v8, fa2 # CHECK-ENCODING: [0x5b,0x52,0x86,0x88] # CHECK-ERROR: instruction requires the following: 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions) -# CHECK-UNKNOWN: 5b 52 86 88 +# CHECK-UNKNOWN: 8886525b sf.vfnrclip.x.f.qf v4, v8, fa2 # CHECK-INST: sf.vfnrclip.x.f.qf v4, v8, fa2 # CHECK-ENCODING: [0x5b,0x52,0x86,0x8e] # CHECK-ERROR: instruction requires the following: 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions) -# CHECK-UNKNOWN: 5b 52 86 8e +# CHECK-UNKNOWN: 8e86525b sf.vfnrclip.x.f.qf v4, v8, fa2, v0.t # CHECK-INST: sf.vfnrclip.x.f.qf v4, v8, fa2 # CHECK-ENCODING: [0x5b,0x52,0x86,0x8c] # CHECK-ERROR: instruction requires the following: 'XSfvfnrclipxfqf' (SiFive FP32-to-int8 Ranged Clip Instructions) -# CHECK-UNKNOWN: 5b 52 86 8c +# CHECK-UNKNOWN: 8c86525b diff --git a/llvm/test/MC/RISCV/rvv/xsfvfwmacc.s b/llvm/test/MC/RISCV/rvv/xsfvfwmacc.s index ba054fff2bd8..a9843c350fc8 100644 --- a/llvm/test/MC/RISCV/rvv/xsfvfwmacc.s +++ b/llvm/test/MC/RISCV/rvv/xsfvfwmacc.s @@ -12,4 +12,4 @@ sf.vfwmacc.4x4x4 v8, v4, v20 # CHECK-INST: sf.vfwmacc.4x4x4 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x14,0x42,0xf3] # CHECK-ERROR: instruction requires the following: 'XSfvfwmaccqqq' (SiFive Matrix Multiply Accumulate Instruction and 4-by-4)) -# CHECK-UNKNOWN: 5b 14 42 f3 +# CHECK-UNKNOWN: f342145b diff --git a/llvm/test/MC/RISCV/rvv/xsfvqmacc.s b/llvm/test/MC/RISCV/rvv/xsfvqmacc.s index ba19f2184486..81703c847d74 100644 --- a/llvm/test/MC/RISCV/rvv/xsfvqmacc.s +++ b/llvm/test/MC/RISCV/rvv/xsfvqmacc.s @@ -12,46 +12,46 @@ sf.vqmaccu.2x8x2 v8, v4, v20 # CHECK-INST: sf.vqmaccu.2x8x2 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xb3] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)) -# CHECK-UNKNOWN: 5b 24 42 b3 +# CHECK-UNKNOWN: b342245b sf.vqmacc.2x8x2 v8, v4, v20 # CHECK-INST: sf.vqmacc.2x8x2 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xb7] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)) -# CHECK-UNKNOWN: 5b 24 42 b7 +# CHECK-UNKNOWN: b742245b sf.vqmaccus.2x8x2 v8, v4, v20 # CHECK-INST: sf.vqmaccus.2x8x2 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xbb] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)) -# CHECK-UNKNOWN: 5b 24 42 bb +# CHECK-UNKNOWN: bb42245b sf.vqmaccsu.2x8x2 v8, v4, v20 # CHECK-INST: sf.vqmaccsu.2x8x2 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xbf] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccdod' (SiFive Int8 Matrix Multiplication Instructions (2-by-8 and 8-by-2)) -# CHECK-UNKNOWN: 5b 24 42 bf +# CHECK-UNKNOWN: bf42245b sf.vqmaccu.4x8x4 v8, v4, v20 # CHECK-INST: sf.vqmaccu.4x8x4 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xf3] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)) -# CHECK-UNKNOWN: 5b 24 42 f3 +# CHECK-UNKNOWN: f342245b sf.vqmacc.4x8x4 v8, v4, v20 # CHECK-INST: sf.vqmacc.4x8x4 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xf7] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)) -# CHECK-UNKNOWN: 5b 24 42 f7 +# CHECK-UNKNOWN: f742245b sf.vqmaccus.4x8x4 v8, v4, v20 # CHECK-INST: sf.vqmaccus.4x8x4 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xfb] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)) -# CHECK-UNKNOWN: 5b 24 42 fb +# CHECK-UNKNOWN: fb42245b sf.vqmaccsu.4x8x4 v8, v4, v20 # CHECK-INST: sf.vqmaccsu.4x8x4 v8, v4, v20 # CHECK-ENCODING: [0x5b,0x24,0x42,0xff] # CHECK-ERROR: instruction requires the following: 'XSfvqmaccqoq' (SiFive Int8 Matrix Multiplication Instructions (4-by-8 and 8-by-4)) -# CHECK-UNKNOWN: 5b 24 42 ff +# CHECK-UNKNOWN: ff42245b diff --git a/llvm/test/MC/RISCV/rvv/zvbb.s b/llvm/test/MC/RISCV/rvv/zvbb.s index 04e5ad6e03f7..d9d1f6f42d32 100644 --- a/llvm/test/MC/RISCV/rvv/zvbb.s +++ b/llvm/test/MC/RISCV/rvv/zvbb.s @@ -12,40 +12,40 @@ vbrev.v v10, v9, v0.t # CHECK-INST: vbrev.v v10, v9, v0.t # CHECK-ENCODING: [0x57,0x25,0x95,0x48] # CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions){{$}} -# CHECK-UNKNOWN: 57 25 95 48 +# CHECK-UNKNOWN: 48952557 vclz.v v10, v9, v0.t # CHECK-INST: vclz.v v10, v9, v0.t # CHECK-ENCODING: [0x57,0x25,0x96,0x48] # CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions){{$}} -# CHECK-UNKNOWN: 57 25 96 48 +# CHECK-UNKNOWN: 48962557 vcpop.v v10, v9, v0.t # CHECK-INST: vcpop.v v10, v9, v0.t # CHECK-ENCODING: [0x57,0x25,0x97,0x48] # CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions){{$}} -# CHECK-UNKNOWN: 57 25 97 48 +# CHECK-UNKNOWN: 48972557 vctz.v v10, v9, v0.t # CHECK-INST: vctz.v v10, v9, v0.t # CHECK-ENCODING: [0x57,0xa5,0x96,0x48] # CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions){{$}} -# CHECK-UNKNOWN: 57 a5 96 48 +# CHECK-UNKNOWN: 4896a557 vwsll.vv v10, v9, v8, v0.t # CHECK-INST: vwsll.vv v10, v9, v8, v0.t # CHECK-ENCODING: [0x57,0x05,0x94,0xd4] # CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions){{$}} -# CHECK-UNKNOWN: 57 05 94 d4 +# CHECK-UNKNOWN: d4940557 vwsll.vx v10, v9, a0, v0.t # CHECK-INST: vwsll.vx v10, v9, a0, v0.t # CHECK-ENCODING: [0x57,0x45,0x95,0xd4] # CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions){{$}} -# CHECK-UNKNOWN: 57 45 95 d4 +# CHECK-UNKNOWN: d4954557 vwsll.vi v10, v9, 29, v0.t # CHECK-INST: vwsll.vi v10, v9, 29, v0.t # CHECK-ENCODING: [0x57,0xb5,0x9e,0xd4] # CHECK-ERROR: instruction requires the following: 'Zvbb' (Vector basic bit-manipulation instructions){{$}} -# CHECK-UNKNOWN: 57 b5 9e d4 +# CHECK-UNKNOWN: d49eb557 diff --git a/llvm/test/MC/RISCV/rvv/zvbc.s b/llvm/test/MC/RISCV/rvv/zvbc.s index b32349a2db13..0eb02d153b79 100644 --- a/llvm/test/MC/RISCV/rvv/zvbc.s +++ b/llvm/test/MC/RISCV/rvv/zvbc.s @@ -12,22 +12,22 @@ vclmul.vv v10, v9, v8 # CHECK-INST: vclmul.vv v10, v9, v8 # CHECK-ENCODING: [0x57,0x25,0x94,0x32] # CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} -# CHECK-UNKNOWN: 57 25 94 32 +# CHECK-UNKNOWN: 32942557 vclmul.vx v10, v9, a0 # CHECK-INST: vclmul.vx v10, v9, a0 # CHECK-ENCODING: [0x57,0x65,0x95,0x32] # CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} -# CHECK-UNKNOWN: 57 65 95 32 +# CHECK-UNKNOWN: 32956557 vclmulh.vv v10, v9, v8 # CHECK-INST: vclmulh.vv v10, v9, v8 # CHECK-ENCODING: [0x57,0x25,0x94,0x36] # CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} -# CHECK-UNKNOWN: 57 25 94 36 +# CHECK-UNKNOWN: 36942557 vclmulh.vx v10, v9, a0 # CHECK-INST: vclmulh.vx v10, v9, a0 # CHECK-ENCODING: [0x57,0x65,0x95,0x36] # CHECK-ERROR: instruction requires the following: 'Zvbc' (Vector Carryless Multiplication){{$}} -# CHECK-UNKNOWN: 57 65 95 36 +# CHECK-UNKNOWN: 36956557 diff --git a/llvm/test/MC/RISCV/rvv/zvfbfmin.s b/llvm/test/MC/RISCV/rvv/zvfbfmin.s index 1cbe027ef26c..7965c2482b00 100644 --- a/llvm/test/MC/RISCV/rvv/zvfbfmin.s +++ b/llvm/test/MC/RISCV/rvv/zvfbfmin.s @@ -20,23 +20,23 @@ # CHECK-INST: vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x4e,0x48] # CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} -# CHECK-UNKNOWN: 57 94 4e 48 +# CHECK-UNKNOWN: 484e9457 vfncvtbf16.f.f.w v8, v4, v0.t # CHECK-INST: vfncvtbf16.f.f.w v8, v4 # CHECK-ENCODING: [0x57,0x94,0x4e,0x4a] # CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} -# CHECK-UNKNOWN: 57 94 4e 4a +# CHECK-UNKNOWN: 4a4e9457 vfncvtbf16.f.f.w v8, v4 # CHECK-INST: vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-ENCODING: [0x57,0x94,0x46,0x48] # CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} -# CHECK-UNKNOWN: 57 94 46 48 +# CHECK-UNKNOWN: 48469457 vfwcvtbf16.f.f.v v8, v4, v0.t # CHECK-INST: vfwcvtbf16.f.f.v v8, v4 # CHECK-ENCODING: [0x57,0x94,0x46,0x4a] # CHECK-ERROR: instruction requires the following: 'Zvfbfmin' (Vector BF16 Converts){{$}} -# CHECK-UNKNOWN: 57 94 46 4a +# CHECK-UNKNOWN: 4a469457 vfwcvtbf16.f.f.v v8, v4 diff --git a/llvm/test/MC/RISCV/rvv/zvfbfwma.s b/llvm/test/MC/RISCV/rvv/zvfbfwma.s index 5a30d9f19ab6..330dee58d836 100644 --- a/llvm/test/MC/RISCV/rvv/zvfbfwma.s +++ b/llvm/test/MC/RISCV/rvv/zvfbfwma.s @@ -20,25 +20,25 @@ # CHECK-INST: vfwmaccbf16.vv v8, v20, v4, v0.t # CHECK-ENCODING: [0x57,0x14,0x4a,0xec] # CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} -# CHECK-UNKNOWN: 57 14 4a ec +# CHECK-UNKNOWN: ec4a1457 vfwmaccbf16.vv v8, v20, v4, v0.t # CHECK-INST: vfwmaccbf16.vv v8, v20, v4 # CHECK-ENCODING: [0x57,0x14,0x4a,0xee] # CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} -# CHECK-UNKNOWN: 57 14 4a ee +# CHECK-UNKNOWN: ee4a1457 vfwmaccbf16.vv v8, v20, v4 # CHECK-INST: vfwmaccbf16.vf v8, fa0, v4, v0.t # CHECK-ENCODING: [0x57,0x54,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} -# CHECK-UNKNOWN: 57 54 45 ec +# CHECK-UNKNOWN: ec455457 vfwmaccbf16.vf v8, fa0, v4, v0.t # CHECK-INST: vfwmaccbf16.vf v8, fa0, v4 # CHECK-ENCODING: [0x57,0x54,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'Zvfbfwma' (Vector BF16 widening mul-add){{$}} -# CHECK-UNKNOWN: 57 54 45 ee +# CHECK-UNKNOWN: ee455457 vfwmaccbf16.vf v8, fa0, v4 # Check scalar half FP load/store/move included in this extension. @@ -46,23 +46,23 @@ vfwmaccbf16.vf v8, fa0, v4 # CHECK-INST: flh ft0, 12(a0) # CHECK-ENCODING: [0x07,0x10,0xc5,0x00] # CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} -# CHECK-UNKNOWN: 07 10 c5 00 +# CHECK-UNKNOWN: 00c51007 flh f0, 12(a0) # CHECK-INST: fsh ft6, 2047(s4) # CHECK-ENCODING: [0xa7,0x1f,0x6a,0x7e] # CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} -# CHECK-UNKNOWN: a7 1f 6a 7e +# CHECK-UNKNOWN: 7e6a1fa7 fsh f6, 2047(s4) # CHECK-INST: fmv.x.h a2, fs7 # CHECK-ENCODING: [0x53,0x86,0x0b,0xe4] # CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} -# CHECK-UNKNOWN: 53 86 0b e4 +# CHECK-UNKNOWN: e40b8653 fmv.x.h a2, fs7 # CHECK-INST: fmv.h.x ft1, a6 # CHECK-ENCODING: [0xd3,0x00,0x08,0xf4] # CHECK-ERROR: instruction requires the following: 'Zfh' (Half-Precision Floating-Point) or 'Zfhmin' (Half-Precision Floating-Point Minimal) or 'Zfbfmin' (Scalar BF16 Converts){{$}} -# CHECK-UNKNOWN: d3 00 08 f4 +# CHECK-UNKNOWN: f40800d3 fmv.h.x ft1, a6 diff --git a/llvm/test/MC/RISCV/rvv/zvkb.s b/llvm/test/MC/RISCV/rvv/zvkb.s index ae2dec18d33c..1833ba860c90 100644 --- a/llvm/test/MC/RISCV/rvv/zvkb.s +++ b/llvm/test/MC/RISCV/rvv/zvkb.s @@ -12,52 +12,52 @@ vandn.vv v10, v9, v8, v0.t # CHECK-INST: vandn.vv v10, v9, v8, v0.t # CHECK-ENCODING: [0x57,0x05,0x94,0x04] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 05 94 04 +# CHECK-UNKNOWN: 04940557 vandn.vx v10, v9, a0, v0.t # CHECK-INST: vandn.vx v10, v9, a0, v0.t # CHECK-ENCODING: [0x57,0x45,0x95,0x04] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 45 95 04 +# CHECK-UNKNOWN: 04954557 vbrev8.v v10, v9, v0.t # CHECK-INST: vbrev8.v v10, v9, v0.t # CHECK-ENCODING: [0x57,0x25,0x94,0x48] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 25 94 48 +# CHECK-UNKNOWN: 48942557 vrev8.v v10, v9, v0.t # CHECK-INST: vrev8.v v10, v9, v0.t # CHECK-ENCODING: [0x57,0xa5,0x94,0x48] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 a5 94 48 +# CHECK-UNKNOWN: 4894a557 vrol.vv v10, v9, v8, v0.t # CHECK-INST: vrol.vv v10, v9, v8, v0.t # CHECK-ENCODING: [0x57,0x05,0x94,0x54] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 05 94 54 +# CHECK-UNKNOWN: 54940557 vrol.vx v10, v9, a0, v0.t # CHECK-INST: vrol.vx v10, v9, a0, v0.t # CHECK-ENCODING: [0x57,0x45,0x95,0x54] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 45 95 54 +# CHECK-UNKNOWN: 54954557 vror.vv v10, v9, v8, v0.t # CHECK-INST: vror.vv v10, v9, v8, v0.t # CHECK-ENCODING: [0x57,0x05,0x94,0x50] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 05 94 50 +# CHECK-UNKNOWN: 50940557 vror.vx v10, v9, a0, v0.t # CHECK-INST: vror.vx v10, v9, a0, v0.t # CHECK-ENCODING: [0x57,0x45,0x95,0x50] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 45 95 50 +# CHECK-UNKNOWN: 50954557 vror.vi v10, v9, 33, v0.t # CHECK-INST: vror.vi v10, v9, 33, v0.t # CHECK-ENCODING: [0x57,0xb5,0x90,0x54] # CHECK-ERROR: instruction requires the following: 'Zvkb' (Vector Bit-manipulation used in Cryptography){{$}} -# CHECK-UNKNOWN: 57 b5 90 54 +# CHECK-UNKNOWN: 5490b557 diff --git a/llvm/test/MC/RISCV/rvv/zvkg.s b/llvm/test/MC/RISCV/rvv/zvkg.s index f2016bc116b6..48b84659e0ae 100644 --- a/llvm/test/MC/RISCV/rvv/zvkg.s +++ b/llvm/test/MC/RISCV/rvv/zvkg.s @@ -12,10 +12,10 @@ vghsh.vv v10, v9, v8 # CHECK-INST: vghsh.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xb2] # CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography){{$}} -# CHECK-UNKNOWN: 77 25 94 b2 +# CHECK-UNKNOWN: b2942577 vgmul.vv v10, v9 # CHECK-INST: vgmul.vv v10, v9 # CHECK-ENCODING: [0x77,0xa5,0x98,0xa2] # CHECK-ERROR: instruction requires the following: 'Zvkg' (Vector GCM instructions for Cryptography){{$}} -# CHECK-UNKNOWN: 77 a5 98 a2 +# CHECK-UNKNOWN: a298a577 diff --git a/llvm/test/MC/RISCV/rvv/zvkned.s b/llvm/test/MC/RISCV/rvv/zvkned.s index e51a9cc562f1..bee3d74ee88d 100644 --- a/llvm/test/MC/RISCV/rvv/zvkned.s +++ b/llvm/test/MC/RISCV/rvv/zvkned.s @@ -12,76 +12,76 @@ vaesdf.vv v10, v9 # CHECK-INST: vaesdf.vv v10, v9 # CHECK-ENCODING: [0x77,0xa5,0x90,0xa2] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 90 a2 +# CHECK-UNKNOWN: a290a577 vaesdf.vs v10, v9 # CHECK-INST: vaesdf.vs v10, v9 # CHECK-ENCODING: [0x77,0xa5,0x90,0xa6] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 90 a6 +# CHECK-UNKNOWN: a690a577 vaesef.vv v10, v9 # CHECK-INST: vaesef.vv v10, v9 # CHECK-ENCODING: [0x77,0xa5,0x91,0xa2] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 91 a2 +# CHECK-UNKNOWN: a291a577 vaesef.vs v10, v9 # CHECK-INST: vaesef.vs v10, v9 # CHECK-ENCODING: [0x77,0xa5,0x91,0xa6] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 91 a6 +# CHECK-UNKNOWN: a691a577 vaesdm.vv v10, v9 # CHECK-INST: vaesdm.vv v10, v9 # CHECK-ENCODING: [0x77,0x25,0x90,0xa2] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 25 90 a2 +# CHECK-UNKNOWN: a2902577 vaesdm.vs v10, v9 # CHECK-INST: vaesdm.vs v10, v9 # CHECK-ENCODING: [0x77,0x25,0x90,0xa6] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 25 90 a6 +# CHECK-UNKNOWN: a6902577 vaesem.vv v10, v9 # CHECK-INST: vaesem.vv v10, v9 # CHECK-ENCODING: [0x77,0x25,0x91,0xa2] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 25 91 a2 +# CHECK-UNKNOWN: a2912577 vaesem.vs v10, v9 # CHECK-INST: vaesem.vs v10, v9 # CHECK-ENCODING: [0x77,0x25,0x91,0xa6] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 25 91 a6 +# CHECK-UNKNOWN: a6912577 vaeskf1.vi v10, v9, 1 # CHECK-INST: vaeskf1.vi v10, v9, 1 # CHECK-ENCODING: [0x77,0xa5,0x90,0x8a] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 90 8a +# CHECK-UNKNOWN: 8a90a577 vaeskf1.vi v10, v9, 31 # CHECK-INST: vaeskf1.vi v10, v9, 31 # CHECK-ENCODING: [0x77,0xa5,0x9f,0x8a] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 9f 8a +# CHECK-UNKNOWN: 8a9fa577 vaeskf2.vi v10, v9, 2 # CHECK-INST: vaeskf2.vi v10, v9, 2 # CHECK-ENCODING: [0x77,0x25,0x91,0xaa] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 25 91 aa +# CHECK-UNKNOWN: aa912577 vaeskf2.vi v10, v9, 31 # CHECK-INST: vaeskf2.vi v10, v9, 31 # CHECK-ENCODING: [0x77,0xa5,0x9f,0xaa] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 9f aa +# CHECK-UNKNOWN: aa9fa577 vaesz.vs v10, v9 # CHECK-INST: vaesz.vs v10, v9 # CHECK-ENCODING: [0x77,0xa5,0x93,0xa6] # CHECK-ERROR: instruction requires the following: 'Zvkned' (Vector AES Encryption & Decryption (Single Round)){{$}} -# CHECK-UNKNOWN: 77 a5 93 a6 +# CHECK-UNKNOWN: a693a577 diff --git a/llvm/test/MC/RISCV/rvv/zvknh.s b/llvm/test/MC/RISCV/rvv/zvknh.s index aa8033a5f217..b16b9081f7e6 100644 --- a/llvm/test/MC/RISCV/rvv/zvknh.s +++ b/llvm/test/MC/RISCV/rvv/zvknh.s @@ -18,17 +18,17 @@ vsha2ms.vv v10, v9, v8 # CHECK-INST: vsha2ms.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xb6] -# CHECK-UNKNOWN: 77 25 94 b6 +# CHECK-UNKNOWN: b6942577 # CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb' (Vector SHA-2){{$}} vsha2ch.vv v10, v9, v8 # CHECK-INST: vsha2ch.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xba] -# CHECK-UNKNOWN: 77 25 94 ba +# CHECK-UNKNOWN: ba942577 # CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb' (Vector SHA-2){{$}} vsha2cl.vv v10, v9, v8 # CHECK-INST: vsha2cl.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0xbe] -# CHECK-UNKNOWN: 77 25 94 be +# CHECK-UNKNOWN: be942577 # CHECK-ERROR: instruction requires the following: 'Zvknha' or 'Zvknhb' (Vector SHA-2){{$}} diff --git a/llvm/test/MC/RISCV/rvv/zvksed.s b/llvm/test/MC/RISCV/rvv/zvksed.s index 87c9713f8c65..f7a0949272ff 100644 --- a/llvm/test/MC/RISCV/rvv/zvksed.s +++ b/llvm/test/MC/RISCV/rvv/zvksed.s @@ -12,22 +12,22 @@ vsm4k.vi v10, v9, 7 # CHECK-INST: vsm4k.vi v10, v9, 7 # CHECK-ENCODING: [0x77,0xa5,0x93,0x86] # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}} -# CHECK-UNKNOWN: 77 a5 93 86 +# CHECK-UNKNOWN: 8693a577 vsm4k.vi v10, v9, 31 # CHECK-INST: vsm4k.vi v10, v9, 31 # CHECK-ENCODING: [0x77,0xa5,0x9f,0x86] # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}} -# CHECK-UNKNOWN: 77 a5 9f 86 +# CHECK-UNKNOWN: 869fa577 vsm4r.vv v10, v9 # CHECK-INST: vsm4r.vv v10, v9 # CHECK-ENCODING: [0x77,0x25,0x98,0xa2] # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}} -# CHECK-UNKNOWN: 77 25 98 a2 +# CHECK-UNKNOWN: a2982577 vsm4r.vs v10, v9 # CHECK-INST: vsm4r.vs v10, v9 # CHECK-ENCODING: [0x77,0x25,0x98,0xa6] # CHECK-ERROR: instruction requires the following: 'Zvksed' (SM4 Block Cipher Instructions){{$}} -# CHECK-UNKNOWN: 77 25 98 a6 +# CHECK-UNKNOWN: a6982577 diff --git a/llvm/test/MC/RISCV/rvv/zvksh.s b/llvm/test/MC/RISCV/rvv/zvksh.s index 06251ff6efe5..ef1c654b4605 100644 --- a/llvm/test/MC/RISCV/rvv/zvksh.s +++ b/llvm/test/MC/RISCV/rvv/zvksh.s @@ -12,17 +12,17 @@ vsm3c.vi v10, v9, 7 # CHECK-INST: vsm3c.vi v10, v9, 7 # CHECK-ENCODING: [0x77,0xa5,0x93,0xae] # CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions){{$}} -# CHECK-UNKNOWN: 77 a5 93 ae +# CHECK-UNKNOWN: ae93a577 vsm3me.vv v10, v9, v8 # CHECK-INST: vsm3me.vv v10, v9, v8 # CHECK-ENCODING: [0x77,0x25,0x94,0x82] # CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions){{$}} -# CHECK-UNKNOWN: 77 25 94 82 +# CHECK-UNKNOWN: 82942577 # vs1 is allowed to overlap, but not vs2. vsm3me.vv v10, v9, v10 # CHECK-INST: vsm3me.vv v10, v9, v10 # CHECK-ENCODING: [0x77,0x25,0x95,0x82] # CHECK-ERROR: instruction requires the following: 'Zvksh' (SM3 Hash Function Instructions){{$}} -# CHECK-UNKNOWN: 77 25 95 82 +# CHECK-UNKNOWN: 82952577 diff --git a/llvm/test/MC/RISCV/rvv/zvlsseg.s b/llvm/test/MC/RISCV/rvv/zvlsseg.s index 9a83ea9f8721..65089e2261be 100644 --- a/llvm/test/MC/RISCV/rvv/zvlsseg.s +++ b/llvm/test/MC/RISCV/rvv/zvlsseg.s @@ -13,3076 +13,3076 @@ vlseg2e8.v v8, (a0), v0.t # CHECK-INST: vlseg2e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 20 +# CHECK-UNKNOWN: 20050407 vlseg2e8.v v8, (a0) # CHECK-INST: vlseg2e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 22 +# CHECK-UNKNOWN: 22050407 vlseg2e16.v v8, (a0), v0.t # CHECK-INST: vlseg2e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 20 +# CHECK-UNKNOWN: 20055407 vlseg2e16.v v8, (a0) # CHECK-INST: vlseg2e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 22 +# CHECK-UNKNOWN: 22055407 vlseg2e32.v v8, (a0), v0.t # CHECK-INST: vlseg2e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 20 +# CHECK-UNKNOWN: 20056407 vlseg2e32.v v8, (a0) # CHECK-INST: vlseg2e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 22 +# CHECK-UNKNOWN: 22056407 vlseg2e64.v v8, (a0), v0.t # CHECK-INST: vlseg2e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 20 +# CHECK-UNKNOWN: 20057407 vlseg2e64.v v8, (a0) # CHECK-INST: vlseg2e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 22 +# CHECK-UNKNOWN: 22057407 vlseg2e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x21] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 21 +# CHECK-UNKNOWN: 21050407 vlseg2e8ff.v v8, (a0) # CHECK-INST: vlseg2e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x23] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 23 +# CHECK-UNKNOWN: 23050407 vlseg2e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x21] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 21 +# CHECK-UNKNOWN: 21055407 vlseg2e16ff.v v8, (a0) # CHECK-INST: vlseg2e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x23] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 23 +# CHECK-UNKNOWN: 23055407 vlseg2e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x21] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 21 +# CHECK-UNKNOWN: 21056407 vlseg2e32ff.v v8, (a0) # CHECK-INST: vlseg2e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x23] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 23 +# CHECK-UNKNOWN: 23056407 vlseg2e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg2e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x21] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 21 +# CHECK-UNKNOWN: 21057407 vlseg2e64ff.v v8, (a0) # CHECK-INST: vlseg2e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x23] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 23 +# CHECK-UNKNOWN: 23057407 vlsseg2e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 28 +# CHECK-UNKNOWN: 28b50407 vlsseg2e8.v v8, (a0), a1 # CHECK-INST: vlsseg2e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 2a +# CHECK-UNKNOWN: 2ab50407 vlsseg2e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 28 +# CHECK-UNKNOWN: 28b55407 vlsseg2e16.v v8, (a0), a1 # CHECK-INST: vlsseg2e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 2a +# CHECK-UNKNOWN: 2ab55407 vlsseg2e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 28 +# CHECK-UNKNOWN: 28b56407 vlsseg2e32.v v8, (a0), a1 # CHECK-INST: vlsseg2e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 2a +# CHECK-UNKNOWN: 2ab56407 vlsseg2e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg2e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 28 +# CHECK-UNKNOWN: 28b57407 vlsseg2e64.v v8, (a0), a1 # CHECK-INST: vlsseg2e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 2a +# CHECK-UNKNOWN: 2ab57407 vluxseg2ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 24 +# CHECK-UNKNOWN: 24450407 vluxseg2ei8.v v8, (a0), v4 # CHECK-INST: vluxseg2ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 26 +# CHECK-UNKNOWN: 26450407 vluxseg2ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 24 +# CHECK-UNKNOWN: 24455407 vluxseg2ei16.v v8, (a0), v4 # CHECK-INST: vluxseg2ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 26 +# CHECK-UNKNOWN: 26455407 vluxseg2ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 24 +# CHECK-UNKNOWN: 24456407 vluxseg2ei32.v v8, (a0), v4 # CHECK-INST: vluxseg2ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 26 +# CHECK-UNKNOWN: 26456407 vluxseg2ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg2ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 24 +# CHECK-UNKNOWN: 24457407 vluxseg2ei64.v v8, (a0), v4 # CHECK-INST: vluxseg2ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 26 +# CHECK-UNKNOWN: 26457407 vloxseg2ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 2c +# CHECK-UNKNOWN: 2c450407 vloxseg2ei8.v v8, (a0), v4 # CHECK-INST: vloxseg2ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 2e +# CHECK-UNKNOWN: 2e450407 vloxseg2ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 2c +# CHECK-UNKNOWN: 2c455407 vloxseg2ei16.v v8, (a0), v4 # CHECK-INST: vloxseg2ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 2e +# CHECK-UNKNOWN: 2e455407 vloxseg2ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 2c +# CHECK-UNKNOWN: 2c456407 vloxseg2ei32.v v8, (a0), v4 # CHECK-INST: vloxseg2ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 2e +# CHECK-UNKNOWN: 2e456407 vloxseg2ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg2ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 2c +# CHECK-UNKNOWN: 2c457407 vloxseg2ei64.v v8, (a0), v4 # CHECK-INST: vloxseg2ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 2e +# CHECK-UNKNOWN: 2e457407 vlseg3e8.v v8, (a0), v0.t # CHECK-INST: vlseg3e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 40 +# CHECK-UNKNOWN: 40050407 vlseg3e8.v v8, (a0) # CHECK-INST: vlseg3e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 42 +# CHECK-UNKNOWN: 42050407 vlseg3e16.v v8, (a0), v0.t # CHECK-INST: vlseg3e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 40 +# CHECK-UNKNOWN: 40055407 vlseg3e16.v v8, (a0) # CHECK-INST: vlseg3e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 42 +# CHECK-UNKNOWN: 42055407 vlseg3e32.v v8, (a0), v0.t # CHECK-INST: vlseg3e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 40 +# CHECK-UNKNOWN: 40056407 vlseg3e32.v v8, (a0) # CHECK-INST: vlseg3e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 42 +# CHECK-UNKNOWN: 42056407 vlseg3e64.v v8, (a0), v0.t # CHECK-INST: vlseg3e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 40 +# CHECK-UNKNOWN: 40057407 vlseg3e64.v v8, (a0) # CHECK-INST: vlseg3e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 42 +# CHECK-UNKNOWN: 42057407 vlseg3e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x41] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 41 +# CHECK-UNKNOWN: 41050407 vlseg3e8ff.v v8, (a0) # CHECK-INST: vlseg3e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x43] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 43 +# CHECK-UNKNOWN: 43050407 vlseg3e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x41] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 41 +# CHECK-UNKNOWN: 41055407 vlseg3e16ff.v v8, (a0) # CHECK-INST: vlseg3e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x43] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 43 +# CHECK-UNKNOWN: 43055407 vlseg3e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x41] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 41 +# CHECK-UNKNOWN: 41056407 vlseg3e32ff.v v8, (a0) # CHECK-INST: vlseg3e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x43] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 43 +# CHECK-UNKNOWN: 43056407 vlseg3e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg3e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x41] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 41 +# CHECK-UNKNOWN: 41057407 vlseg3e64ff.v v8, (a0) # CHECK-INST: vlseg3e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x43] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 43 +# CHECK-UNKNOWN: 43057407 vlsseg3e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 48 +# CHECK-UNKNOWN: 48b50407 vlsseg3e8.v v8, (a0), a1 # CHECK-INST: vlsseg3e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 4a +# CHECK-UNKNOWN: 4ab50407 vlsseg3e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 48 +# CHECK-UNKNOWN: 48b55407 vlsseg3e16.v v8, (a0), a1 # CHECK-INST: vlsseg3e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 4a +# CHECK-UNKNOWN: 4ab55407 vlsseg3e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 48 +# CHECK-UNKNOWN: 48b56407 vlsseg3e32.v v8, (a0), a1 # CHECK-INST: vlsseg3e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 4a +# CHECK-UNKNOWN: 4ab56407 vlsseg3e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg3e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 48 +# CHECK-UNKNOWN: 48b57407 vlsseg3e64.v v8, (a0), a1 # CHECK-INST: vlsseg3e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 4a +# CHECK-UNKNOWN: 4ab57407 vluxseg3ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 44 +# CHECK-UNKNOWN: 44450407 vluxseg3ei8.v v8, (a0), v4 # CHECK-INST: vluxseg3ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 46 +# CHECK-UNKNOWN: 46450407 vluxseg3ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 44 +# CHECK-UNKNOWN: 44455407 vluxseg3ei16.v v8, (a0), v4 # CHECK-INST: vluxseg3ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 46 +# CHECK-UNKNOWN: 46455407 vluxseg3ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 44 +# CHECK-UNKNOWN: 44456407 vluxseg3ei32.v v8, (a0), v4 # CHECK-INST: vluxseg3ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 46 +# CHECK-UNKNOWN: 46456407 vluxseg3ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg3ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 44 +# CHECK-UNKNOWN: 44457407 vluxseg3ei64.v v8, (a0), v4 # CHECK-INST: vluxseg3ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 46 +# CHECK-UNKNOWN: 46457407 vloxseg3ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 4c +# CHECK-UNKNOWN: 4c450407 vloxseg3ei8.v v8, (a0), v4 # CHECK-INST: vloxseg3ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 4e +# CHECK-UNKNOWN: 4e450407 vloxseg3ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 4c +# CHECK-UNKNOWN: 4c455407 vloxseg3ei16.v v8, (a0), v4 # CHECK-INST: vloxseg3ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 4e +# CHECK-UNKNOWN: 4e455407 vloxseg3ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 4c +# CHECK-UNKNOWN: 4c456407 vloxseg3ei32.v v8, (a0), v4 # CHECK-INST: vloxseg3ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 4e +# CHECK-UNKNOWN: 4e456407 vloxseg3ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg3ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 4c +# CHECK-UNKNOWN: 4c457407 vloxseg3ei64.v v8, (a0), v4 # CHECK-INST: vloxseg3ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 4e +# CHECK-UNKNOWN: 4e457407 vlseg4e8.v v8, (a0), v0.t # CHECK-INST: vlseg4e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 60 +# CHECK-UNKNOWN: 60050407 vlseg4e8.v v8, (a0) # CHECK-INST: vlseg4e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 62 +# CHECK-UNKNOWN: 62050407 vlseg4e16.v v8, (a0), v0.t # CHECK-INST: vlseg4e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 60 +# CHECK-UNKNOWN: 60055407 vlseg4e16.v v8, (a0) # CHECK-INST: vlseg4e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 62 +# CHECK-UNKNOWN: 62055407 vlseg4e32.v v8, (a0), v0.t # CHECK-INST: vlseg4e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 60 +# CHECK-UNKNOWN: 60056407 vlseg4e32.v v8, (a0) # CHECK-INST: vlseg4e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 62 +# CHECK-UNKNOWN: 62056407 vlseg4e64.v v8, (a0), v0.t # CHECK-INST: vlseg4e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 60 +# CHECK-UNKNOWN: 60057407 vlseg4e64.v v8, (a0) # CHECK-INST: vlseg4e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 62 +# CHECK-UNKNOWN: 62057407 vlseg4e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x61] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 61 +# CHECK-UNKNOWN: 61050407 vlseg4e8ff.v v8, (a0) # CHECK-INST: vlseg4e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x63] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 63 +# CHECK-UNKNOWN: 63050407 vlseg4e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x61] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 61 +# CHECK-UNKNOWN: 61055407 vlseg4e16ff.v v8, (a0) # CHECK-INST: vlseg4e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x63] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 63 +# CHECK-UNKNOWN: 63055407 vlseg4e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x61] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 61 +# CHECK-UNKNOWN: 61056407 vlseg4e32ff.v v8, (a0) # CHECK-INST: vlseg4e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x63] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 63 +# CHECK-UNKNOWN: 63056407 vlseg4e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg4e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x61] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 61 +# CHECK-UNKNOWN: 61057407 vlseg4e64ff.v v8, (a0) # CHECK-INST: vlseg4e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x63] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 63 +# CHECK-UNKNOWN: 63057407 vlsseg4e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 68 +# CHECK-UNKNOWN: 68b50407 vlsseg4e8.v v8, (a0), a1 # CHECK-INST: vlsseg4e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 6a +# CHECK-UNKNOWN: 6ab50407 vlsseg4e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 68 +# CHECK-UNKNOWN: 68b55407 vlsseg4e16.v v8, (a0), a1 # CHECK-INST: vlsseg4e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 6a +# CHECK-UNKNOWN: 6ab55407 vlsseg4e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 68 +# CHECK-UNKNOWN: 68b56407 vlsseg4e32.v v8, (a0), a1 # CHECK-INST: vlsseg4e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 6a +# CHECK-UNKNOWN: 6ab56407 vlsseg4e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg4e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 68 +# CHECK-UNKNOWN: 68b57407 vlsseg4e64.v v8, (a0), a1 # CHECK-INST: vlsseg4e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 6a +# CHECK-UNKNOWN: 6ab57407 vluxseg4ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 64 +# CHECK-UNKNOWN: 64450407 vluxseg4ei8.v v8, (a0), v4 # CHECK-INST: vluxseg4ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 66 +# CHECK-UNKNOWN: 66450407 vluxseg4ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 64 +# CHECK-UNKNOWN: 64455407 vluxseg4ei16.v v8, (a0), v4 # CHECK-INST: vluxseg4ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 66 +# CHECK-UNKNOWN: 66455407 vluxseg4ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 64 +# CHECK-UNKNOWN: 64456407 vluxseg4ei32.v v8, (a0), v4 # CHECK-INST: vluxseg4ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 66 +# CHECK-UNKNOWN: 66456407 vluxseg4ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg4ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 64 +# CHECK-UNKNOWN: 64457407 vluxseg4ei64.v v8, (a0), v4 # CHECK-INST: vluxseg4ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 66 +# CHECK-UNKNOWN: 66457407 vloxseg4ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 6c +# CHECK-UNKNOWN: 6c450407 vloxseg4ei8.v v8, (a0), v4 # CHECK-INST: vloxseg4ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 6e +# CHECK-UNKNOWN: 6e450407 vloxseg4ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 6c +# CHECK-UNKNOWN: 6c455407 vloxseg4ei16.v v8, (a0), v4 # CHECK-INST: vloxseg4ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 6e +# CHECK-UNKNOWN: 6e455407 vloxseg4ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 6c +# CHECK-UNKNOWN: 6c456407 vloxseg4ei32.v v8, (a0), v4 # CHECK-INST: vloxseg4ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 6e +# CHECK-UNKNOWN: 6e456407 vloxseg4ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 6c +# CHECK-UNKNOWN: 6c457407 vloxseg4ei64.v v8, (a0), v4 # CHECK-INST: vloxseg4ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 6e +# CHECK-UNKNOWN: 6e457407 vlseg5e8.v v8, (a0), v0.t # CHECK-INST: vlseg5e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 80 +# CHECK-UNKNOWN: 80050407 vlseg5e8.v v8, (a0) # CHECK-INST: vlseg5e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 82 +# CHECK-UNKNOWN: 82050407 vlseg5e16.v v8, (a0), v0.t # CHECK-INST: vlseg5e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 80 +# CHECK-UNKNOWN: 80055407 vlseg5e16.v v8, (a0) # CHECK-INST: vlseg5e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 82 +# CHECK-UNKNOWN: 82055407 vlseg5e32.v v8, (a0), v0.t # CHECK-INST: vlseg5e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 80 +# CHECK-UNKNOWN: 80056407 vlseg5e32.v v8, (a0) # CHECK-INST: vlseg5e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 82 +# CHECK-UNKNOWN: 82056407 vlseg5e64.v v8, (a0), v0.t # CHECK-INST: vlseg5e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 80 +# CHECK-UNKNOWN: 80057407 vlseg5e64.v v8, (a0) # CHECK-INST: vlseg5e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 82 +# CHECK-UNKNOWN: 82057407 vlseg5e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x81] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 81 +# CHECK-UNKNOWN: 81050407 vlseg5e8ff.v v8, (a0) # CHECK-INST: vlseg5e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0x83] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 83 +# CHECK-UNKNOWN: 83050407 vlseg5e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0x81] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 81 +# CHECK-UNKNOWN: 81055407 vlseg5e16ff.v v8, (a0) # CHECK-INST: vlseg5e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x83] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 83 +# CHECK-UNKNOWN: 83055407 vlseg5e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0x81] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 81 +# CHECK-UNKNOWN: 81056407 vlseg5e32ff.v v8, (a0) # CHECK-INST: vlseg5e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0x83] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 83 +# CHECK-UNKNOWN: 83056407 vlseg5e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg5e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0x81] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 81 +# CHECK-UNKNOWN: 81057407 vlseg5e64ff.v v8, (a0) # CHECK-INST: vlseg5e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0x83] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 83 +# CHECK-UNKNOWN: 83057407 vlsseg5e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 88 +# CHECK-UNKNOWN: 88b50407 vlsseg5e8.v v8, (a0), a1 # CHECK-INST: vlsseg5e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 8a +# CHECK-UNKNOWN: 8ab50407 vlsseg5e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 88 +# CHECK-UNKNOWN: 88b55407 vlsseg5e16.v v8, (a0), a1 # CHECK-INST: vlsseg5e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 8a +# CHECK-UNKNOWN: 8ab55407 vlsseg5e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 88 +# CHECK-UNKNOWN: 88b56407 vlsseg5e32.v v8, (a0), a1 # CHECK-INST: vlsseg5e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 8a +# CHECK-UNKNOWN: 8ab56407 vlsseg5e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg5e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 88 +# CHECK-UNKNOWN: 88b57407 vlsseg5e64.v v8, (a0), a1 # CHECK-INST: vlsseg5e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 8a +# CHECK-UNKNOWN: 8ab57407 vluxseg5ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 84 +# CHECK-UNKNOWN: 84450407 vluxseg5ei8.v v8, (a0), v4 # CHECK-INST: vluxseg5ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 86 +# CHECK-UNKNOWN: 86450407 vluxseg5ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 84 +# CHECK-UNKNOWN: 84455407 vluxseg5ei16.v v8, (a0), v4 # CHECK-INST: vluxseg5ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 86 +# CHECK-UNKNOWN: 86455407 vluxseg5ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 84 +# CHECK-UNKNOWN: 84456407 vluxseg5ei32.v v8, (a0), v4 # CHECK-INST: vluxseg5ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 86 +# CHECK-UNKNOWN: 86456407 vluxseg5ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg5ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 84 +# CHECK-UNKNOWN: 84457407 vluxseg5ei64.v v8, (a0), v4 # CHECK-INST: vluxseg5ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 86 +# CHECK-UNKNOWN: 86457407 vloxseg5ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 8c +# CHECK-UNKNOWN: 8c450407 vloxseg5ei8.v v8, (a0), v4 # CHECK-INST: vloxseg5ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 8e +# CHECK-UNKNOWN: 8e450407 vloxseg5ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 8c +# CHECK-UNKNOWN: 8c455407 vloxseg5ei16.v v8, (a0), v4 # CHECK-INST: vloxseg5ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 8e +# CHECK-UNKNOWN: 8e455407 vloxseg5ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 8c +# CHECK-UNKNOWN: 8c456407 vloxseg5ei32.v v8, (a0), v4 # CHECK-INST: vloxseg5ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 8e +# CHECK-UNKNOWN: 8e456407 vloxseg5ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg5ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 8c +# CHECK-UNKNOWN: 8c457407 vloxseg5ei64.v v8, (a0), v4 # CHECK-INST: vloxseg5ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 8e +# CHECK-UNKNOWN: 8e457407 vlseg6e8.v v8, (a0), v0.t # CHECK-INST: vlseg6e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 a0 +# CHECK-UNKNOWN: a0050407 vlseg6e8.v v8, (a0) # CHECK-INST: vlseg6e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 a2 +# CHECK-UNKNOWN: a2050407 vlseg6e16.v v8, (a0), v0.t # CHECK-INST: vlseg6e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 a0 +# CHECK-UNKNOWN: a0055407 vlseg6e16.v v8, (a0) # CHECK-INST: vlseg6e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 a2 +# CHECK-UNKNOWN: a2055407 vlseg6e32.v v8, (a0), v0.t # CHECK-INST: vlseg6e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 a0 +# CHECK-UNKNOWN: a0056407 vlseg6e32.v v8, (a0) # CHECK-INST: vlseg6e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 a2 +# CHECK-UNKNOWN: a2056407 vlseg6e64.v v8, (a0), v0.t # CHECK-INST: vlseg6e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 a0 +# CHECK-UNKNOWN: a0057407 vlseg6e64.v v8, (a0) # CHECK-INST: vlseg6e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 a2 +# CHECK-UNKNOWN: a2057407 vlseg6e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xa1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 a1 +# CHECK-UNKNOWN: a1050407 vlseg6e8ff.v v8, (a0) # CHECK-INST: vlseg6e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xa3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 a3 +# CHECK-UNKNOWN: a3050407 vlseg6e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xa1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 a1 +# CHECK-UNKNOWN: a1055407 vlseg6e16ff.v v8, (a0) # CHECK-INST: vlseg6e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xa3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 a3 +# CHECK-UNKNOWN: a3055407 vlseg6e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xa1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 a1 +# CHECK-UNKNOWN: a1056407 vlseg6e32ff.v v8, (a0) # CHECK-INST: vlseg6e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xa3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 a3 +# CHECK-UNKNOWN: a3056407 vlseg6e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg6e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xa1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 a1 +# CHECK-UNKNOWN: a1057407 vlseg6e64ff.v v8, (a0) # CHECK-INST: vlseg6e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xa3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 a3 +# CHECK-UNKNOWN: a3057407 vlsseg6e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 a8 +# CHECK-UNKNOWN: a8b50407 vlsseg6e8.v v8, (a0), a1 # CHECK-INST: vlsseg6e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 aa +# CHECK-UNKNOWN: aab50407 vlsseg6e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 a8 +# CHECK-UNKNOWN: a8b55407 vlsseg6e16.v v8, (a0), a1 # CHECK-INST: vlsseg6e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 aa +# CHECK-UNKNOWN: aab55407 vlsseg6e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 a8 +# CHECK-UNKNOWN: a8b56407 vlsseg6e32.v v8, (a0), a1 # CHECK-INST: vlsseg6e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 aa +# CHECK-UNKNOWN: aab56407 vlsseg6e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg6e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 a8 +# CHECK-UNKNOWN: a8b57407 vlsseg6e64.v v8, (a0), a1 # CHECK-INST: vlsseg6e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 aa +# CHECK-UNKNOWN: aab57407 vluxseg6ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 a4 +# CHECK-UNKNOWN: a4450407 vluxseg6ei8.v v8, (a0), v4 # CHECK-INST: vluxseg6ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 a6 +# CHECK-UNKNOWN: a6450407 vluxseg6ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 a4 +# CHECK-UNKNOWN: a4455407 vluxseg6ei16.v v8, (a0), v4 # CHECK-INST: vluxseg6ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 a6 +# CHECK-UNKNOWN: a6455407 vluxseg6ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 a4 +# CHECK-UNKNOWN: a4456407 vluxseg6ei32.v v8, (a0), v4 # CHECK-INST: vluxseg6ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 a6 +# CHECK-UNKNOWN: a6456407 vluxseg6ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg6ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 a4 +# CHECK-UNKNOWN: a4457407 vluxseg6ei64.v v8, (a0), v4 # CHECK-INST: vluxseg6ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 a6 +# CHECK-UNKNOWN: a6457407 vloxseg6ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 ac +# CHECK-UNKNOWN: ac450407 vloxseg6ei8.v v8, (a0), v4 # CHECK-INST: vloxseg6ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 ae +# CHECK-UNKNOWN: ae450407 vloxseg6ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 ac +# CHECK-UNKNOWN: ac455407 vloxseg6ei16.v v8, (a0), v4 # CHECK-INST: vloxseg6ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 ae +# CHECK-UNKNOWN: ae455407 vloxseg6ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 ac +# CHECK-UNKNOWN: ac456407 vloxseg6ei32.v v8, (a0), v4 # CHECK-INST: vloxseg6ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 ae +# CHECK-UNKNOWN: ae456407 vloxseg6ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg6ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 ac +# CHECK-UNKNOWN: ac457407 vloxseg6ei64.v v8, (a0), v4 # CHECK-INST: vloxseg6ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 ae +# CHECK-UNKNOWN: ae457407 vlseg7e8.v v8, (a0), v0.t # CHECK-INST: vlseg7e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 c0 +# CHECK-UNKNOWN: c0050407 vlseg7e8.v v8, (a0) # CHECK-INST: vlseg7e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 c2 +# CHECK-UNKNOWN: c2050407 vlseg7e16.v v8, (a0), v0.t # CHECK-INST: vlseg7e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 c0 +# CHECK-UNKNOWN: c0055407 vlseg7e16.v v8, (a0) # CHECK-INST: vlseg7e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 c2 +# CHECK-UNKNOWN: c2055407 vlseg7e32.v v8, (a0), v0.t # CHECK-INST: vlseg7e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 c0 +# CHECK-UNKNOWN: c0056407 vlseg7e32.v v8, (a0) # CHECK-INST: vlseg7e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 c2 +# CHECK-UNKNOWN: c2056407 vlseg7e64.v v8, (a0), v0.t # CHECK-INST: vlseg7e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 c0 +# CHECK-UNKNOWN: c0057407 vlseg7e64.v v8, (a0) # CHECK-INST: vlseg7e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 c2 +# CHECK-UNKNOWN: c2057407 vlseg7e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xc1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 c1 +# CHECK-UNKNOWN: c1050407 vlseg7e8ff.v v8, (a0) # CHECK-INST: vlseg7e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xc3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 c3 +# CHECK-UNKNOWN: c3050407 vlseg7e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xc1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 c1 +# CHECK-UNKNOWN: c1055407 vlseg7e16ff.v v8, (a0) # CHECK-INST: vlseg7e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xc3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 c3 +# CHECK-UNKNOWN: c3055407 vlseg7e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xc1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 c1 +# CHECK-UNKNOWN: c1056407 vlseg7e32ff.v v8, (a0) # CHECK-INST: vlseg7e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xc3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 c3 +# CHECK-UNKNOWN: c3056407 vlseg7e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg7e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xc1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 c1 +# CHECK-UNKNOWN: c1057407 vlseg7e64ff.v v8, (a0) # CHECK-INST: vlseg7e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xc3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 c3 +# CHECK-UNKNOWN: c3057407 vlsseg7e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 c8 +# CHECK-UNKNOWN: c8b50407 vlsseg7e8.v v8, (a0), a1 # CHECK-INST: vlsseg7e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 ca +# CHECK-UNKNOWN: cab50407 vlsseg7e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 c8 +# CHECK-UNKNOWN: c8b55407 vlsseg7e16.v v8, (a0), a1 # CHECK-INST: vlsseg7e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 ca +# CHECK-UNKNOWN: cab55407 vlsseg7e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 c8 +# CHECK-UNKNOWN: c8b56407 vlsseg7e32.v v8, (a0), a1 # CHECK-INST: vlsseg7e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 ca +# CHECK-UNKNOWN: cab56407 vlsseg7e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg7e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 c8 +# CHECK-UNKNOWN: c8b57407 vlsseg7e64.v v8, (a0), a1 # CHECK-INST: vlsseg7e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 ca +# CHECK-UNKNOWN: cab57407 vluxseg7ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 c4 +# CHECK-UNKNOWN: c4450407 vluxseg7ei8.v v8, (a0), v4 # CHECK-INST: vluxseg7ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 c6 +# CHECK-UNKNOWN: c6450407 vluxseg7ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 c4 +# CHECK-UNKNOWN: c4455407 vluxseg7ei16.v v8, (a0), v4 # CHECK-INST: vluxseg7ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 c6 +# CHECK-UNKNOWN: c6455407 vluxseg7ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 c4 +# CHECK-UNKNOWN: c4456407 vluxseg7ei32.v v8, (a0), v4 # CHECK-INST: vluxseg7ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 c6 +# CHECK-UNKNOWN: c6456407 vluxseg7ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg7ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 c4 +# CHECK-UNKNOWN: c4457407 vluxseg7ei64.v v8, (a0), v4 # CHECK-INST: vluxseg7ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 c6 +# CHECK-UNKNOWN: c6457407 vloxseg7ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 cc +# CHECK-UNKNOWN: cc450407 vloxseg7ei8.v v8, (a0), v4 # CHECK-INST: vloxseg7ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 ce +# CHECK-UNKNOWN: ce450407 vloxseg7ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 cc +# CHECK-UNKNOWN: cc455407 vloxseg7ei16.v v8, (a0), v4 # CHECK-INST: vloxseg7ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 ce +# CHECK-UNKNOWN: ce455407 vloxseg7ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 cc +# CHECK-UNKNOWN: cc456407 vloxseg7ei32.v v8, (a0), v4 # CHECK-INST: vloxseg7ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 ce +# CHECK-UNKNOWN: ce456407 vloxseg7ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg7ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 cc +# CHECK-UNKNOWN: cc457407 vloxseg7ei64.v v8, (a0), v4 # CHECK-INST: vloxseg7ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 ce +# CHECK-UNKNOWN: ce457407 vlseg8e8.v v8, (a0), v0.t # CHECK-INST: vlseg8e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 e0 +# CHECK-UNKNOWN: e0050407 vlseg8e8.v v8, (a0) # CHECK-INST: vlseg8e8.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 e2 +# CHECK-UNKNOWN: e2050407 vlseg8e16.v v8, (a0), v0.t # CHECK-INST: vlseg8e16.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 e0 +# CHECK-UNKNOWN: e0055407 vlseg8e16.v v8, (a0) # CHECK-INST: vlseg8e16.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 e2 +# CHECK-UNKNOWN: e2055407 vlseg8e32.v v8, (a0), v0.t # CHECK-INST: vlseg8e32.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 e0 +# CHECK-UNKNOWN: e0056407 vlseg8e32.v v8, (a0) # CHECK-INST: vlseg8e32.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 e2 +# CHECK-UNKNOWN: e2056407 vlseg8e64.v v8, (a0), v0.t # CHECK-INST: vlseg8e64.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 e0 +# CHECK-UNKNOWN: e0057407 vlseg8e64.v v8, (a0) # CHECK-INST: vlseg8e64.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 e2 +# CHECK-UNKNOWN: e2057407 vlseg8e8ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e8ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0xe1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 e1 +# CHECK-UNKNOWN: e1050407 vlseg8e8ff.v v8, (a0) # CHECK-INST: vlseg8e8ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x04,0x05,0xe3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 e3 +# CHECK-UNKNOWN: e3050407 vlseg8e16ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e16ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x54,0x05,0xe1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 e1 +# CHECK-UNKNOWN: e1055407 vlseg8e16ff.v v8, (a0) # CHECK-INST: vlseg8e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0xe3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 e3 +# CHECK-UNKNOWN: e3055407 vlseg8e32ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e32ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x64,0x05,0xe1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 e1 +# CHECK-UNKNOWN: e1056407 vlseg8e32ff.v v8, (a0) # CHECK-INST: vlseg8e32ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x64,0x05,0xe3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 05 e3 +# CHECK-UNKNOWN: e3056407 vlseg8e64ff.v v8, (a0), v0.t # CHECK-INST: vlseg8e64ff.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x74,0x05,0xe1] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 e1 +# CHECK-UNKNOWN: e1057407 vlseg8e64ff.v v8, (a0) # CHECK-INST: vlseg8e64ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x74,0x05,0xe3] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 05 e3 +# CHECK-UNKNOWN: e3057407 vlsseg8e8.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e8.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x04,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 e8 +# CHECK-UNKNOWN: e8b50407 vlsseg8e8.v v8, (a0), a1 # CHECK-INST: vlsseg8e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 ea +# CHECK-UNKNOWN: eab50407 vlsseg8e16.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e16.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x54,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 e8 +# CHECK-UNKNOWN: e8b55407 vlsseg8e16.v v8, (a0), a1 # CHECK-INST: vlsseg8e16.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x54,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 b5 ea +# CHECK-UNKNOWN: eab55407 vlsseg8e32.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e32.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x64,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 e8 +# CHECK-UNKNOWN: e8b56407 vlsseg8e32.v v8, (a0), a1 # CHECK-INST: vlsseg8e32.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x64,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 b5 ea +# CHECK-UNKNOWN: eab56407 vlsseg8e64.v v8, (a0), a1, v0.t # CHECK-INST: vlsseg8e64.v v8, (a0), a1, v0.t # CHECK-ENCODING: [0x07,0x74,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 e8 +# CHECK-UNKNOWN: e8b57407 vlsseg8e64.v v8, (a0), a1 # CHECK-INST: vlsseg8e64.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x74,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 b5 ea +# CHECK-UNKNOWN: eab57407 vluxseg8ei8.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 e4 +# CHECK-UNKNOWN: e4450407 vluxseg8ei8.v v8, (a0), v4 # CHECK-INST: vluxseg8ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 e6 +# CHECK-UNKNOWN: e6450407 vluxseg8ei16.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 e4 +# CHECK-UNKNOWN: e4455407 vluxseg8ei16.v v8, (a0), v4 # CHECK-INST: vluxseg8ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 e6 +# CHECK-UNKNOWN: e6455407 vluxseg8ei32.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 e4 +# CHECK-UNKNOWN: e4456407 vluxseg8ei32.v v8, (a0), v4 # CHECK-INST: vluxseg8ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 e6 +# CHECK-UNKNOWN: e6456407 vluxseg8ei64.v v8, (a0), v4, v0.t # CHECK-INST: vluxseg8ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 e4 +# CHECK-UNKNOWN: e4457407 vluxseg8ei64.v v8, (a0), v4 # CHECK-INST: vluxseg8ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 e6 +# CHECK-UNKNOWN: e6457407 vloxseg8ei8.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei8.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x04,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 ec +# CHECK-UNKNOWN: ec450407 vloxseg8ei8.v v8, (a0), v4 # CHECK-INST: vloxseg8ei8.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x04,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 45 ee +# CHECK-UNKNOWN: ee450407 vloxseg8ei16.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei16.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x54,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 ec +# CHECK-UNKNOWN: ec455407 vloxseg8ei16.v v8, (a0), v4 # CHECK-INST: vloxseg8ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 ee +# CHECK-UNKNOWN: ee455407 vloxseg8ei32.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei32.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x64,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 ec +# CHECK-UNKNOWN: ec456407 vloxseg8ei32.v v8, (a0), v4 # CHECK-INST: vloxseg8ei32.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x64,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 64 45 ee +# CHECK-UNKNOWN: ee456407 vloxseg8ei64.v v8, (a0), v4, v0.t # CHECK-INST: vloxseg8ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 ec +# CHECK-UNKNOWN: ec457407 vloxseg8ei64.v v8, (a0), v4 # CHECK-INST: vloxseg8ei64.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x74,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 ee +# CHECK-UNKNOWN: ee457407 vsseg2e8.v v24, (a0), v0.t # CHECK-INST: vsseg2e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 20 +# CHECK-UNKNOWN: 20050c27 vsseg2e8.v v24, (a0) # CHECK-INST: vsseg2e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 22 +# CHECK-UNKNOWN: 22050c27 vsseg2e16.v v24, (a0), v0.t # CHECK-INST: vsseg2e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 20 +# CHECK-UNKNOWN: 20055c27 vsseg2e16.v v24, (a0) # CHECK-INST: vsseg2e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 22 +# CHECK-UNKNOWN: 22055c27 vsseg2e32.v v24, (a0), v0.t # CHECK-INST: vsseg2e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 20 +# CHECK-UNKNOWN: 20056c27 vsseg2e32.v v24, (a0) # CHECK-INST: vsseg2e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 22 +# CHECK-UNKNOWN: 22056c27 vsseg2e64.v v24, (a0), v0.t # CHECK-INST: vsseg2e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 20 +# CHECK-UNKNOWN: 20057c27 vsseg2e64.v v24, (a0) # CHECK-INST: vsseg2e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x22] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 22 +# CHECK-UNKNOWN: 22057c27 vssseg2e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 28 +# CHECK-UNKNOWN: 28b50c27 vssseg2e8.v v24, (a0), a1 # CHECK-INST: vssseg2e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 2a +# CHECK-UNKNOWN: 2ab50c27 vssseg2e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 28 +# CHECK-UNKNOWN: 28b55c27 vssseg2e16.v v24, (a0), a1 # CHECK-INST: vssseg2e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 2a +# CHECK-UNKNOWN: 2ab55c27 vssseg2e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 28 +# CHECK-UNKNOWN: 28b56c27 vssseg2e32.v v24, (a0), a1 # CHECK-INST: vssseg2e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 2a +# CHECK-UNKNOWN: 2ab56c27 vssseg2e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg2e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 28 +# CHECK-UNKNOWN: 28b57c27 vssseg2e64.v v24, (a0), a1 # CHECK-INST: vssseg2e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 2a +# CHECK-UNKNOWN: 2ab57c27 vsuxseg2ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 24 +# CHECK-UNKNOWN: 24450c27 vsuxseg2ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 26 +# CHECK-UNKNOWN: 26450c27 vsuxseg2ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 24 +# CHECK-UNKNOWN: 24455c27 vsuxseg2ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 26 +# CHECK-UNKNOWN: 26455c27 vsuxseg2ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 24 +# CHECK-UNKNOWN: 24456c27 vsuxseg2ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 26 +# CHECK-UNKNOWN: 26456c27 vsuxseg2ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg2ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x24] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 24 +# CHECK-UNKNOWN: 24457c27 vsuxseg2ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg2ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x26] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 26 +# CHECK-UNKNOWN: 26457c27 vsoxseg2ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 2c +# CHECK-UNKNOWN: 2c450c27 vsoxseg2ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 2e +# CHECK-UNKNOWN: 2e450c27 vsoxseg2ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 2c +# CHECK-UNKNOWN: 2c455c27 vsoxseg2ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 2e +# CHECK-UNKNOWN: 2e455c27 vsoxseg2ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 2c +# CHECK-UNKNOWN: 2c456c27 vsoxseg2ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 2e +# CHECK-UNKNOWN: 2e456c27 vsoxseg2ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg2ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x2c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 2c +# CHECK-UNKNOWN: 2c457c27 vsoxseg2ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg2ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x2e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 2e +# CHECK-UNKNOWN: 2e457c27 vsseg3e8.v v24, (a0), v0.t # CHECK-INST: vsseg3e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 40 +# CHECK-UNKNOWN: 40050c27 vsseg3e8.v v24, (a0) # CHECK-INST: vsseg3e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 42 +# CHECK-UNKNOWN: 42050c27 vsseg3e16.v v24, (a0), v0.t # CHECK-INST: vsseg3e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 40 +# CHECK-UNKNOWN: 40055c27 vsseg3e16.v v24, (a0) # CHECK-INST: vsseg3e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 42 +# CHECK-UNKNOWN: 42055c27 vsseg3e32.v v24, (a0), v0.t # CHECK-INST: vsseg3e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 40 +# CHECK-UNKNOWN: 40056c27 vsseg3e32.v v24, (a0) # CHECK-INST: vsseg3e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 42 +# CHECK-UNKNOWN: 42056c27 vsseg3e64.v v24, (a0), v0.t # CHECK-INST: vsseg3e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x40] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 40 +# CHECK-UNKNOWN: 40057c27 vsseg3e64.v v24, (a0) # CHECK-INST: vsseg3e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x42] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 42 +# CHECK-UNKNOWN: 42057c27 vssseg3e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 48 +# CHECK-UNKNOWN: 48b50c27 vssseg3e8.v v24, (a0), a1 # CHECK-INST: vssseg3e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 4a +# CHECK-UNKNOWN: 4ab50c27 vssseg3e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 48 +# CHECK-UNKNOWN: 48b55c27 vssseg3e16.v v24, (a0), a1 # CHECK-INST: vssseg3e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 4a +# CHECK-UNKNOWN: 4ab55c27 vssseg3e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 48 +# CHECK-UNKNOWN: 48b56c27 vssseg3e32.v v24, (a0), a1 # CHECK-INST: vssseg3e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 4a +# CHECK-UNKNOWN: 4ab56c27 vssseg3e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg3e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x48] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 48 +# CHECK-UNKNOWN: 48b57c27 vssseg3e64.v v24, (a0), a1 # CHECK-INST: vssseg3e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x4a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 4a +# CHECK-UNKNOWN: 4ab57c27 vsuxseg3ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 44 +# CHECK-UNKNOWN: 44450c27 vsuxseg3ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 46 +# CHECK-UNKNOWN: 46450c27 vsuxseg3ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 44 +# CHECK-UNKNOWN: 44455c27 vsuxseg3ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 46 +# CHECK-UNKNOWN: 46455c27 vsuxseg3ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 44 +# CHECK-UNKNOWN: 44456c27 vsuxseg3ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 46 +# CHECK-UNKNOWN: 46456c27 vsuxseg3ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg3ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x44] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 44 +# CHECK-UNKNOWN: 44457c27 vsuxseg3ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg3ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 46 +# CHECK-UNKNOWN: 46457c27 vsoxseg3ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 4c +# CHECK-UNKNOWN: 4c450c27 vsoxseg3ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 4e +# CHECK-UNKNOWN: 4e450c27 vsoxseg3ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 4c +# CHECK-UNKNOWN: 4c455c27 vsoxseg3ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 4e +# CHECK-UNKNOWN: 4e455c27 vsoxseg3ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 4c +# CHECK-UNKNOWN: 4c456c27 vsoxseg3ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 4e +# CHECK-UNKNOWN: 4e456c27 vsoxseg3ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg3ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x4c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 4c +# CHECK-UNKNOWN: 4c457c27 vsoxseg3ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg3ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x4e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 4e +# CHECK-UNKNOWN: 4e457c27 vsseg4e8.v v24, (a0), v0.t # CHECK-INST: vsseg4e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 60 +# CHECK-UNKNOWN: 60050c27 vsseg4e8.v v24, (a0) # CHECK-INST: vsseg4e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 62 +# CHECK-UNKNOWN: 62050c27 vsseg4e16.v v24, (a0), v0.t # CHECK-INST: vsseg4e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 60 +# CHECK-UNKNOWN: 60055c27 vsseg4e16.v v24, (a0) # CHECK-INST: vsseg4e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 62 +# CHECK-UNKNOWN: 62055c27 vsseg4e32.v v24, (a0), v0.t # CHECK-INST: vsseg4e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 60 +# CHECK-UNKNOWN: 60056c27 vsseg4e32.v v24, (a0) # CHECK-INST: vsseg4e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 62 +# CHECK-UNKNOWN: 62056c27 vsseg4e64.v v24, (a0), v0.t # CHECK-INST: vsseg4e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x60] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 60 +# CHECK-UNKNOWN: 60057c27 vsseg4e64.v v24, (a0) # CHECK-INST: vsseg4e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x62] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 62 +# CHECK-UNKNOWN: 62057c27 vssseg4e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 68 +# CHECK-UNKNOWN: 68b50c27 vssseg4e8.v v24, (a0), a1 # CHECK-INST: vssseg4e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 6a +# CHECK-UNKNOWN: 6ab50c27 vssseg4e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 68 +# CHECK-UNKNOWN: 68b55c27 vssseg4e16.v v24, (a0), a1 # CHECK-INST: vssseg4e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 6a +# CHECK-UNKNOWN: 6ab55c27 vssseg4e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 68 +# CHECK-UNKNOWN: 68b56c27 vssseg4e32.v v24, (a0), a1 # CHECK-INST: vssseg4e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 6a +# CHECK-UNKNOWN: 6ab56c27 vssseg4e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg4e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x68] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 68 +# CHECK-UNKNOWN: 68b57c27 vssseg4e64.v v24, (a0), a1 # CHECK-INST: vssseg4e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x6a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 6a +# CHECK-UNKNOWN: 6ab57c27 vsuxseg4ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 64 +# CHECK-UNKNOWN: 64450c27 vsuxseg4ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 66 +# CHECK-UNKNOWN: 66450c27 vsuxseg4ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 64 +# CHECK-UNKNOWN: 64455c27 vsuxseg4ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 66 +# CHECK-UNKNOWN: 66455c27 vsuxseg4ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 64 +# CHECK-UNKNOWN: 64456c27 vsuxseg4ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 66 +# CHECK-UNKNOWN: 66456c27 vsuxseg4ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg4ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x64] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 64 +# CHECK-UNKNOWN: 64457c27 vsuxseg4ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg4ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x66] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 66 +# CHECK-UNKNOWN: 66457c27 vsoxseg4ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 6c +# CHECK-UNKNOWN: 6c450c27 vsoxseg4ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 6e +# CHECK-UNKNOWN: 6e450c27 vsoxseg4ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 6c +# CHECK-UNKNOWN: 6c455c27 vsoxseg4ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 6e +# CHECK-UNKNOWN: 6e455c27 vsoxseg4ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 6c +# CHECK-UNKNOWN: 6c456c27 vsoxseg4ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 6e +# CHECK-UNKNOWN: 6e456c27 vsoxseg4ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg4ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 6c +# CHECK-UNKNOWN: 6c457c27 vsoxseg4ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg4ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x6e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 6e +# CHECK-UNKNOWN: 6e457c27 vsseg5e8.v v24, (a0), v0.t # CHECK-INST: vsseg5e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 80 +# CHECK-UNKNOWN: 80050c27 vsseg5e8.v v24, (a0) # CHECK-INST: vsseg5e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 82 +# CHECK-UNKNOWN: 82050c27 vsseg5e16.v v24, (a0), v0.t # CHECK-INST: vsseg5e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 80 +# CHECK-UNKNOWN: 80055c27 vsseg5e16.v v24, (a0) # CHECK-INST: vsseg5e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 82 +# CHECK-UNKNOWN: 82055c27 vsseg5e32.v v24, (a0), v0.t # CHECK-INST: vsseg5e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 80 +# CHECK-UNKNOWN: 80056c27 vsseg5e32.v v24, (a0) # CHECK-INST: vsseg5e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 82 +# CHECK-UNKNOWN: 82056c27 vsseg5e64.v v24, (a0), v0.t # CHECK-INST: vsseg5e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 80 +# CHECK-UNKNOWN: 80057c27 vsseg5e64.v v24, (a0) # CHECK-INST: vsseg5e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0x82] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 82 +# CHECK-UNKNOWN: 82057c27 vssseg5e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 88 +# CHECK-UNKNOWN: 88b50c27 vssseg5e8.v v24, (a0), a1 # CHECK-INST: vssseg5e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 8a +# CHECK-UNKNOWN: 8ab50c27 vssseg5e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 88 +# CHECK-UNKNOWN: 88b55c27 vssseg5e16.v v24, (a0), a1 # CHECK-INST: vssseg5e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 8a +# CHECK-UNKNOWN: 8ab55c27 vssseg5e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 88 +# CHECK-UNKNOWN: 88b56c27 vssseg5e32.v v24, (a0), a1 # CHECK-INST: vssseg5e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 8a +# CHECK-UNKNOWN: 8ab56c27 vssseg5e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg5e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0x88] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 88 +# CHECK-UNKNOWN: 88b57c27 vssseg5e64.v v24, (a0), a1 # CHECK-INST: vssseg5e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0x8a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 8a +# CHECK-UNKNOWN: 8ab57c27 vsuxseg5ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 84 +# CHECK-UNKNOWN: 84450c27 vsuxseg5ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 86 +# CHECK-UNKNOWN: 86450c27 vsuxseg5ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 84 +# CHECK-UNKNOWN: 84455c27 vsuxseg5ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 86 +# CHECK-UNKNOWN: 86455c27 vsuxseg5ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 84 +# CHECK-UNKNOWN: 84456c27 vsuxseg5ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 86 +# CHECK-UNKNOWN: 86456c27 vsuxseg5ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg5ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x84] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 84 +# CHECK-UNKNOWN: 84457c27 vsuxseg5ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg5ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x86] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 86 +# CHECK-UNKNOWN: 86457c27 vsoxseg5ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 8c +# CHECK-UNKNOWN: 8c450c27 vsoxseg5ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 8e +# CHECK-UNKNOWN: 8e450c27 vsoxseg5ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 8c +# CHECK-UNKNOWN: 8c455c27 vsoxseg5ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 8e +# CHECK-UNKNOWN: 8e455c27 vsoxseg5ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 8c +# CHECK-UNKNOWN: 8c456c27 vsoxseg5ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 8e +# CHECK-UNKNOWN: 8e456c27 vsoxseg5ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg5ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0x8c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 8c +# CHECK-UNKNOWN: 8c457c27 vsoxseg5ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg5ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0x8e] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 8e +# CHECK-UNKNOWN: 8e457c27 vsseg6e8.v v24, (a0), v0.t # CHECK-INST: vsseg6e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 a0 +# CHECK-UNKNOWN: a0050c27 vsseg6e8.v v24, (a0) # CHECK-INST: vsseg6e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 a2 +# CHECK-UNKNOWN: a2050c27 vsseg6e16.v v24, (a0), v0.t # CHECK-INST: vsseg6e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 a0 +# CHECK-UNKNOWN: a0055c27 vsseg6e16.v v24, (a0) # CHECK-INST: vsseg6e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 a2 +# CHECK-UNKNOWN: a2055c27 vsseg6e32.v v24, (a0), v0.t # CHECK-INST: vsseg6e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 a0 +# CHECK-UNKNOWN: a0056c27 vsseg6e32.v v24, (a0) # CHECK-INST: vsseg6e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 a2 +# CHECK-UNKNOWN: a2056c27 vsseg6e64.v v24, (a0), v0.t # CHECK-INST: vsseg6e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0xa0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 a0 +# CHECK-UNKNOWN: a0057c27 vsseg6e64.v v24, (a0) # CHECK-INST: vsseg6e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0xa2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 a2 +# CHECK-UNKNOWN: a2057c27 vssseg6e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 a8 +# CHECK-UNKNOWN: a8b50c27 vssseg6e8.v v24, (a0), a1 # CHECK-INST: vssseg6e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 aa +# CHECK-UNKNOWN: aab50c27 vssseg6e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 a8 +# CHECK-UNKNOWN: a8b55c27 vssseg6e16.v v24, (a0), a1 # CHECK-INST: vssseg6e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 aa +# CHECK-UNKNOWN: aab55c27 vssseg6e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 a8 +# CHECK-UNKNOWN: a8b56c27 vssseg6e32.v v24, (a0), a1 # CHECK-INST: vssseg6e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 aa +# CHECK-UNKNOWN: aab56c27 vssseg6e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg6e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0xa8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 a8 +# CHECK-UNKNOWN: a8b57c27 vssseg6e64.v v24, (a0), a1 # CHECK-INST: vssseg6e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xaa] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 aa +# CHECK-UNKNOWN: aab57c27 vsuxseg6ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 a4 +# CHECK-UNKNOWN: a4450c27 vsuxseg6ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 a6 +# CHECK-UNKNOWN: a6450c27 vsuxseg6ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 a4 +# CHECK-UNKNOWN: a4455c27 vsuxseg6ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 a6 +# CHECK-UNKNOWN: a6455c27 vsuxseg6ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 a4 +# CHECK-UNKNOWN: a4456c27 vsuxseg6ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 a6 +# CHECK-UNKNOWN: a6456c27 vsuxseg6ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg6ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 a4 +# CHECK-UNKNOWN: a4457c27 vsuxseg6ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg6ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xa6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 a6 +# CHECK-UNKNOWN: a6457c27 vsoxseg6ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 ac +# CHECK-UNKNOWN: ac450c27 vsoxseg6ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 ae +# CHECK-UNKNOWN: ae450c27 vsoxseg6ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 ac +# CHECK-UNKNOWN: ac455c27 vsoxseg6ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 ae +# CHECK-UNKNOWN: ae455c27 vsoxseg6ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 ac +# CHECK-UNKNOWN: ac456c27 vsoxseg6ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 ae +# CHECK-UNKNOWN: ae456c27 vsoxseg6ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg6ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xac] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 ac +# CHECK-UNKNOWN: ac457c27 vsoxseg6ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg6ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xae] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 ae +# CHECK-UNKNOWN: ae457c27 vsseg7e8.v v24, (a0), v0.t # CHECK-INST: vsseg7e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 c0 +# CHECK-UNKNOWN: c0050c27 vsseg7e8.v v24, (a0) # CHECK-INST: vsseg7e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 c2 +# CHECK-UNKNOWN: c2050c27 vsseg7e16.v v24, (a0), v0.t # CHECK-INST: vsseg7e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 c0 +# CHECK-UNKNOWN: c0055c27 vsseg7e16.v v24, (a0) # CHECK-INST: vsseg7e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 c2 +# CHECK-UNKNOWN: c2055c27 vsseg7e32.v v24, (a0), v0.t # CHECK-INST: vsseg7e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 c0 +# CHECK-UNKNOWN: c0056c27 vsseg7e32.v v24, (a0) # CHECK-INST: vsseg7e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 c2 +# CHECK-UNKNOWN: c2056c27 vsseg7e64.v v24, (a0), v0.t # CHECK-INST: vsseg7e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0xc0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 c0 +# CHECK-UNKNOWN: c0057c27 vsseg7e64.v v24, (a0) # CHECK-INST: vsseg7e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0xc2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 c2 +# CHECK-UNKNOWN: c2057c27 vssseg7e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 c8 +# CHECK-UNKNOWN: c8b50c27 vssseg7e8.v v24, (a0), a1 # CHECK-INST: vssseg7e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 ca +# CHECK-UNKNOWN: cab50c27 vssseg7e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 c8 +# CHECK-UNKNOWN: c8b55c27 vssseg7e16.v v24, (a0), a1 # CHECK-INST: vssseg7e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 ca +# CHECK-UNKNOWN: cab55c27 vssseg7e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 c8 +# CHECK-UNKNOWN: c8b56c27 vssseg7e32.v v24, (a0), a1 # CHECK-INST: vssseg7e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 ca +# CHECK-UNKNOWN: cab56c27 vssseg7e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg7e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0xc8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 c8 +# CHECK-UNKNOWN: c8b57c27 vssseg7e64.v v24, (a0), a1 # CHECK-INST: vssseg7e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xca] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 ca +# CHECK-UNKNOWN: cab57c27 vsuxseg7ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 c4 +# CHECK-UNKNOWN: c4450c27 vsuxseg7ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 c6 +# CHECK-UNKNOWN: c6450c27 vsuxseg7ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 c4 +# CHECK-UNKNOWN: c4455c27 vsuxseg7ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 c6 +# CHECK-UNKNOWN: c6455c27 vsuxseg7ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 c4 +# CHECK-UNKNOWN: c4456c27 vsuxseg7ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 c6 +# CHECK-UNKNOWN: c6456c27 vsuxseg7ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg7ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xc4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 c4 +# CHECK-UNKNOWN: c4457c27 vsuxseg7ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg7ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xc6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 c6 +# CHECK-UNKNOWN: c6457c27 vsoxseg7ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 cc +# CHECK-UNKNOWN: cc450c27 vsoxseg7ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 ce +# CHECK-UNKNOWN: ce450c27 vsoxseg7ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 cc +# CHECK-UNKNOWN: cc455c27 vsoxseg7ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 ce +# CHECK-UNKNOWN: ce455c27 vsoxseg7ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 cc +# CHECK-UNKNOWN: cc456c27 vsoxseg7ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 ce +# CHECK-UNKNOWN: ce456c27 vsoxseg7ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg7ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xcc] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 cc +# CHECK-UNKNOWN: cc457c27 vsoxseg7ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg7ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 ce +# CHECK-UNKNOWN: ce457c27 vsseg8e8.v v24, (a0), v0.t # CHECK-INST: vsseg8e8.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x0c,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 e0 +# CHECK-UNKNOWN: e0050c27 vsseg8e8.v v24, (a0) # CHECK-INST: vsseg8e8.v v24, (a0) # CHECK-ENCODING: [0x27,0x0c,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 05 e2 +# CHECK-UNKNOWN: e2050c27 vsseg8e16.v v24, (a0), v0.t # CHECK-INST: vsseg8e16.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x5c,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 e0 +# CHECK-UNKNOWN: e0055c27 vsseg8e16.v v24, (a0) # CHECK-INST: vsseg8e16.v v24, (a0) # CHECK-ENCODING: [0x27,0x5c,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 05 e2 +# CHECK-UNKNOWN: e2055c27 vsseg8e32.v v24, (a0), v0.t # CHECK-INST: vsseg8e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 e0 +# CHECK-UNKNOWN: e0056c27 vsseg8e32.v v24, (a0) # CHECK-INST: vsseg8e32.v v24, (a0) # CHECK-ENCODING: [0x27,0x6c,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 e2 +# CHECK-UNKNOWN: e2056c27 vsseg8e64.v v24, (a0), v0.t # CHECK-INST: vsseg8e64.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x7c,0x05,0xe0] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 e0 +# CHECK-UNKNOWN: e0057c27 vsseg8e64.v v24, (a0) # CHECK-INST: vsseg8e64.v v24, (a0) # CHECK-ENCODING: [0x27,0x7c,0x05,0xe2] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 05 e2 +# CHECK-UNKNOWN: e2057c27 vssseg8e8.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 e8 +# CHECK-UNKNOWN: e8b50c27 vssseg8e8.v v24, (a0), a1 # CHECK-INST: vssseg8e8.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x0c,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 ea +# CHECK-UNKNOWN: eab50c27 vssseg8e16.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e16.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x5c,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 e8 +# CHECK-UNKNOWN: e8b55c27 vssseg8e16.v v24, (a0), a1 # CHECK-INST: vssseg8e16.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x5c,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c b5 ea +# CHECK-UNKNOWN: eab55c27 vssseg8e32.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e32.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x6c,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 e8 +# CHECK-UNKNOWN: e8b56c27 vssseg8e32.v v24, (a0), a1 # CHECK-INST: vssseg8e32.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x6c,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c b5 ea +# CHECK-UNKNOWN: eab56c27 vssseg8e64.v v24, (a0), a1, v0.t # CHECK-INST: vssseg8e64.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x7c,0xb5,0xe8] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 e8 +# CHECK-UNKNOWN: e8b57c27 vssseg8e64.v v24, (a0), a1 # CHECK-INST: vssseg8e64.v v24, (a0), a1 # CHECK-ENCODING: [0x27,0x7c,0xb5,0xea] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c b5 ea +# CHECK-UNKNOWN: eab57c27 vsuxseg8ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 e4 +# CHECK-UNKNOWN: e4450c27 vsuxseg8ei8.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 e6 +# CHECK-UNKNOWN: e6450c27 vsuxseg8ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 e4 +# CHECK-UNKNOWN: e4455c27 vsuxseg8ei16.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 e6 +# CHECK-UNKNOWN: e6455c27 vsuxseg8ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 e4 +# CHECK-UNKNOWN: e4456c27 vsuxseg8ei32.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 e6 +# CHECK-UNKNOWN: e6456c27 vsuxseg8ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsuxseg8ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xe4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 e4 +# CHECK-UNKNOWN: e4457c27 vsuxseg8ei64.v v24, (a0), v4 # CHECK-INST: vsuxseg8ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xe6] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 e6 +# CHECK-UNKNOWN: e6457c27 vsoxseg8ei8.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei8.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x0c,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 ec +# CHECK-UNKNOWN: ec450c27 vsoxseg8ei8.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei8.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x0c,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c 45 ee +# CHECK-UNKNOWN: ee450c27 vsoxseg8ei16.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei16.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x5c,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 ec +# CHECK-UNKNOWN: ec455c27 vsoxseg8ei16.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 ee +# CHECK-UNKNOWN: ee455c27 vsoxseg8ei32.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 ec +# CHECK-UNKNOWN: ec456c27 vsoxseg8ei32.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei32.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x6c,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 ee +# CHECK-UNKNOWN: ee456c27 vsoxseg8ei64.v v24, (a0), v4, v0.t # CHECK-INST: vsoxseg8ei64.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x7c,0x45,0xec] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 ec +# CHECK-UNKNOWN: ec457c27 vsoxseg8ei64.v v24, (a0), v4 # CHECK-INST: vsoxseg8ei64.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x7c,0x45,0xee] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 7c 45 ee +# CHECK-UNKNOWN: ee457c27 vlseg2e8.v v8, 0(a0), v0.t # CHECK-INST: vlseg2e8.v v8, (a0), v0.t # CHECK-ENCODING: [0x07,0x04,0x05,0x20] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 05 20 +# CHECK-UNKNOWN: 20050407 vlseg2e16ff.v v8, 0(a0) # CHECK-INST: vlseg2e16ff.v v8, (a0) # CHECK-ENCODING: [0x07,0x54,0x05,0x23] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 05 23 +# CHECK-UNKNOWN: 23055407 vlsseg2e8.v v8, 0(a0), a1 # CHECK-INST: vlsseg2e8.v v8, (a0), a1 # CHECK-ENCODING: [0x07,0x04,0xb5,0x2a] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 04 b5 2a +# CHECK-UNKNOWN: 2ab50407 vluxseg3ei16.v v8, 0(a0), v4 # CHECK-INST: vluxseg3ei16.v v8, (a0), v4 # CHECK-ENCODING: [0x07,0x54,0x45,0x46] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 54 45 46 +# CHECK-UNKNOWN: 46455407 vloxseg4ei64.v v8, 0(a0), v4, v0.t # CHECK-INST: vloxseg4ei64.v v8, (a0), v4, v0.t # CHECK-ENCODING: [0x07,0x74,0x45,0x6c] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors) or 'Zve64x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 07 74 45 6c +# CHECK-UNKNOWN: 6c457407 vsseg5e32.v v24, 0(a0), v0.t # CHECK-INST: vsseg5e32.v v24, (a0), v0.t # CHECK-ENCODING: [0x27,0x6c,0x05,0x80] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 05 80 +# CHECK-UNKNOWN: 80056c27 vssseg2e8.v v24, 0(a0), a1, v0.t # CHECK-INST: vssseg2e8.v v24, (a0), a1, v0.t # CHECK-ENCODING: [0x27,0x0c,0xb5,0x28] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 0c b5 28 +# CHECK-UNKNOWN: 28b50c27 vsoxseg7ei16.v v24, 0(a0), v4 # CHECK-INST: vsoxseg7ei16.v v24, (a0), v4 # CHECK-ENCODING: [0x27,0x5c,0x45,0xce] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 5c 45 ce +# CHECK-UNKNOWN: ce455c27 vsuxseg6ei32.v v24, 0(a0), v4, v0.t # CHECK-INST: vsuxseg6ei32.v v24, (a0), v4, v0.t # CHECK-ENCODING: [0x27,0x6c,0x45,0xa4] # CHECK-ERROR: instruction requires the following: 'V' (Vector Extension for Application Processors), 'Zve32x' (Vector Extensions for Embedded Processors){{$}} -# CHECK-UNKNOWN: 27 6c 45 a4 +# CHECK-UNKNOWN: a4456c27 diff --git a/llvm/tools/llvm-objdump/llvm-objdump.cpp b/llvm/tools/llvm-objdump/llvm-objdump.cpp index 339822e4adcd..675364a1c1bc 100644 --- a/llvm/tools/llvm-objdump/llvm-objdump.cpp +++ b/llvm/tools/llvm-objdump/llvm-objdump.cpp @@ -947,6 +947,55 @@ public: }; AArch64PrettyPrinter AArch64PrettyPrinterInst; +class RISCVPrettyPrinter : public PrettyPrinter { +public: + void printInst(MCInstPrinter &IP, const MCInst *MI, ArrayRef Bytes, + object::SectionedAddress Address, formatted_raw_ostream &OS, + StringRef Annot, MCSubtargetInfo const &STI, SourcePrinter *SP, + StringRef ObjectFilename, std::vector *Rels, + LiveVariablePrinter &LVP) override { + if (SP && (PrintSource || PrintLines)) + SP->printSourceLine(OS, Address, ObjectFilename, LVP); + LVP.printBetweenInsts(OS, false); + + size_t Start = OS.tell(); + if (LeadingAddr) + OS << format("%8" PRIx64 ":", Address.Address); + if (ShowRawInsn) { + size_t Pos = 0, End = Bytes.size(); + if (End % 4 == 0) { + // 32-bit and 64-bit instructions. + for (; Pos + 4 <= End; Pos += 4) + OS << ' ' + << format_hex_no_prefix( + llvm::support::endian::read( + Bytes.data() + Pos, llvm::endianness::little), + 8); + } else if (End % 2 == 0) { + // 16-bit and 48-bits instructions. + for (; Pos + 2 <= End; Pos += 2) + OS << ' ' + << format_hex_no_prefix( + llvm::support::endian::read( + Bytes.data() + Pos, llvm::endianness::little), + 4); + } + if (Pos < End) { + OS << ' '; + dumpBytes(Bytes.slice(Pos), OS); + } + } + + AlignToInstStartColumn(Start, STI, OS); + + if (MI) { + IP.printInst(MI, Address.Address, "", STI, OS); + } else + OS << "\t"; + } +}; +RISCVPrettyPrinter RISCVPrettyPrinterInst; + PrettyPrinter &selectPrettyPrinter(Triple const &Triple) { switch(Triple.getArch()) { default: @@ -967,6 +1016,9 @@ PrettyPrinter &selectPrettyPrinter(Triple const &Triple) { case Triple::aarch64_be: case Triple::aarch64_32: return AArch64PrettyPrinterInst; + case Triple::riscv32: + case Triple::riscv64: + return RISCVPrettyPrinterInst; } } -- GitLab From b2098db2485331e01503e1452a7a60cd8c031a3f Mon Sep 17 00:00:00 2001 From: Egor Zhdan Date: Fri, 26 Apr 2024 19:30:08 +0100 Subject: [PATCH 084/301] [APINotes] Allow annotating a C++ type as non-copyable in Swift Certain C++ types, such as `std::chrono::tzdb` in libstdc++, are non-copyable, but don't explicitly delete their copy constructor. Instead, they trigger template instantiation errors when trying to call their implicit copy constructor. The Swift compiler inserts implicit copies of value types in some cases, which trigger compiler errors for such types. This adds a Clang API Notes attribute that allows annotating C++ types as non-copyable in Swift. This lets the Swift compiler know that it should not try to instantiate the implicit copy constructor for a C++ struct. rdar://127049438 --- clang/include/clang/APINotes/Types.h | 22 ++++++++++++++++++- clang/lib/APINotes/APINotesFormat.h | 5 ++++- clang/lib/APINotes/APINotesReader.cpp | 7 ++++++ clang/lib/APINotes/APINotesWriter.cpp | 7 +++++- clang/lib/APINotes/APINotesYAMLCompiler.cpp | 5 +++++ clang/lib/Sema/SemaAPINotes.cpp | 5 +++++ .../Inputs/Headers/SwiftImportAs.apinotes | 4 ++++ .../APINotes/Inputs/Headers/SwiftImportAs.h | 3 +++ clang/test/APINotes/swift-import-as.cpp | 10 +++++++++ 9 files changed, 65 insertions(+), 3 deletions(-) diff --git a/clang/include/clang/APINotes/Types.h b/clang/include/clang/APINotes/Types.h index 93bb045d6a66..026a4a431e73 100644 --- a/clang/include/clang/APINotes/Types.h +++ b/clang/include/clang/APINotes/Types.h @@ -675,6 +675,11 @@ class TagInfo : public CommonTypeInfo { LLVM_PREFERRED_TYPE(bool) unsigned IsFlagEnum : 1; + LLVM_PREFERRED_TYPE(bool) + unsigned SwiftCopyableSpecified : 1; + LLVM_PREFERRED_TYPE(bool) + unsigned SwiftCopyable : 1; + public: std::optional SwiftImportAs; std::optional SwiftRetainOp; @@ -682,7 +687,9 @@ public: std::optional EnumExtensibility; - TagInfo() : HasFlagEnum(0), IsFlagEnum(0) {} + TagInfo() + : HasFlagEnum(0), IsFlagEnum(0), SwiftCopyableSpecified(false), + SwiftCopyable(false) {} std::optional isFlagEnum() const { if (HasFlagEnum) @@ -694,6 +701,15 @@ public: IsFlagEnum = Value.value_or(false); } + std::optional isSwiftCopyable() const { + return SwiftCopyableSpecified ? std::optional(SwiftCopyable) + : std::nullopt; + } + void setSwiftCopyable(std::optional Value) { + SwiftCopyableSpecified = Value.has_value(); + SwiftCopyable = Value.value_or(false); + } + TagInfo &operator|=(const TagInfo &RHS) { static_cast(*this) |= RHS; @@ -710,6 +726,9 @@ public: if (!EnumExtensibility) EnumExtensibility = RHS.EnumExtensibility; + if (!SwiftCopyableSpecified) + setSwiftCopyable(RHS.isSwiftCopyable()); + return *this; } @@ -724,6 +743,7 @@ inline bool operator==(const TagInfo &LHS, const TagInfo &RHS) { LHS.SwiftRetainOp == RHS.SwiftRetainOp && LHS.SwiftReleaseOp == RHS.SwiftReleaseOp && LHS.isFlagEnum() == RHS.isFlagEnum() && + LHS.isSwiftCopyable() == RHS.isSwiftCopyable() && LHS.EnumExtensibility == RHS.EnumExtensibility; } diff --git a/clang/lib/APINotes/APINotesFormat.h b/clang/lib/APINotes/APINotesFormat.h index 615314c46f09..97e630e97fdc 100644 --- a/clang/lib/APINotes/APINotesFormat.h +++ b/clang/lib/APINotes/APINotesFormat.h @@ -24,7 +24,10 @@ const uint16_t VERSION_MAJOR = 0; /// API notes file minor version number. /// /// When the format changes IN ANY WAY, this number should be incremented. -const uint16_t VERSION_MINOR = 25; // SwiftImportAs +const uint16_t VERSION_MINOR = 26; // SwiftCopyable + +const uint8_t kSwiftCopyable = 1; +const uint8_t kSwiftNonCopyable = 2; using IdentifierID = llvm::PointerEmbeddedInt; using IdentifierIDField = llvm::BCVBR<16>; diff --git a/clang/lib/APINotes/APINotesReader.cpp b/clang/lib/APINotes/APINotesReader.cpp index dfc3beb6fa13..b60ca685f62c 100644 --- a/clang/lib/APINotes/APINotesReader.cpp +++ b/clang/lib/APINotes/APINotesReader.cpp @@ -527,6 +527,13 @@ public: Info.EnumExtensibility = static_cast((Payload & 0x3) - 1); + uint8_t Copyable = + endian::readNext(Data); + if (Copyable == kSwiftNonCopyable) + Info.setSwiftCopyable(std::optional(false)); + else if (Copyable == kSwiftCopyable) + Info.setSwiftCopyable(std::optional(true)); + unsigned ImportAsLength = endian::readNext(Data); if (ImportAsLength > 0) { diff --git a/clang/lib/APINotes/APINotesWriter.cpp b/clang/lib/APINotes/APINotesWriter.cpp index e3f5d102fcd0..3e6159763150 100644 --- a/clang/lib/APINotes/APINotesWriter.cpp +++ b/clang/lib/APINotes/APINotesWriter.cpp @@ -1128,7 +1128,7 @@ public: return 2 + (TI.SwiftImportAs ? TI.SwiftImportAs->size() : 0) + 2 + (TI.SwiftRetainOp ? TI.SwiftRetainOp->size() : 0) + 2 + (TI.SwiftReleaseOp ? TI.SwiftReleaseOp->size() : 0) + - 1 + getCommonTypeInfoSize(TI); + 2 + getCommonTypeInfoSize(TI); } void emitUnversionedInfo(raw_ostream &OS, const TagInfo &TI) { @@ -1146,6 +1146,11 @@ public: writer.write(Flags); + if (auto Copyable = TI.isSwiftCopyable()) + writer.write(*Copyable ? kSwiftCopyable : kSwiftNonCopyable); + else + writer.write(0); + if (auto ImportAs = TI.SwiftImportAs) { writer.write(ImportAs->size() + 1); OS.write(ImportAs->c_str(), ImportAs->size()); diff --git a/clang/lib/APINotes/APINotesYAMLCompiler.cpp b/clang/lib/APINotes/APINotesYAMLCompiler.cpp index 57d6da7a1775..2295d769d344 100644 --- a/clang/lib/APINotes/APINotesYAMLCompiler.cpp +++ b/clang/lib/APINotes/APINotesYAMLCompiler.cpp @@ -419,6 +419,7 @@ struct Tag { std::optional EnumExtensibility; std::optional FlagEnum; std::optional EnumConvenienceKind; + std::optional SwiftCopyable; }; typedef std::vector TagsSeq; @@ -452,6 +453,7 @@ template <> struct MappingTraits { IO.mapOptional("EnumExtensibility", T.EnumExtensibility); IO.mapOptional("FlagEnum", T.FlagEnum); IO.mapOptional("EnumKind", T.EnumConvenienceKind); + IO.mapOptional("SwiftCopyable", T.SwiftCopyable); } }; } // namespace yaml @@ -1009,6 +1011,9 @@ public: if (Tag.SwiftReleaseOp) TI.SwiftReleaseOp = Tag.SwiftReleaseOp; + if (Tag.SwiftCopyable) + TI.setSwiftCopyable(Tag.SwiftCopyable); + if (Tag.EnumConvenienceKind) { if (Tag.EnumExtensibility) { emitError( diff --git a/clang/lib/Sema/SemaAPINotes.cpp b/clang/lib/Sema/SemaAPINotes.cpp index 4c445f28bba8..c5998aca0d72 100644 --- a/clang/lib/Sema/SemaAPINotes.cpp +++ b/clang/lib/Sema/SemaAPINotes.cpp @@ -594,6 +594,11 @@ static void ProcessAPINotes(Sema &S, TagDecl *D, const api_notes::TagInfo &Info, D->addAttr( SwiftAttrAttr::Create(S.Context, "release:" + ReleaseOp.value())); + if (auto Copyable = Info.isSwiftCopyable()) { + if (!*Copyable) + D->addAttr(SwiftAttrAttr::Create(S.Context, "~Copyable")); + } + if (auto Extensibility = Info.EnumExtensibility) { using api_notes::EnumExtensibilityKind; bool ShouldAddAttribute = (*Extensibility != EnumExtensibilityKind::None); diff --git a/clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes b/clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes index 5dbb83cab86b..b0eead42869a 100644 --- a/clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes +++ b/clang/test/APINotes/Inputs/Headers/SwiftImportAs.apinotes @@ -7,3 +7,7 @@ Tags: SwiftImportAs: reference SwiftReleaseOp: RCRelease SwiftRetainOp: RCRetain +- Name: NonCopyableType + SwiftCopyable: false +- Name: CopyableType + SwiftCopyable: true diff --git a/clang/test/APINotes/Inputs/Headers/SwiftImportAs.h b/clang/test/APINotes/Inputs/Headers/SwiftImportAs.h index 82b8a6749c4f..a8f6d0248eae 100644 --- a/clang/test/APINotes/Inputs/Headers/SwiftImportAs.h +++ b/clang/test/APINotes/Inputs/Headers/SwiftImportAs.h @@ -4,3 +4,6 @@ struct RefCountedType { int value; }; inline void RCRetain(RefCountedType *x) { x->value++; } inline void RCRelease(RefCountedType *x) { x->value--; } + +struct NonCopyableType { int value; }; +struct CopyableType { int value; }; diff --git a/clang/test/APINotes/swift-import-as.cpp b/clang/test/APINotes/swift-import-as.cpp index 904857e58593..103cf02f431a 100644 --- a/clang/test/APINotes/swift-import-as.cpp +++ b/clang/test/APINotes/swift-import-as.cpp @@ -2,6 +2,8 @@ // RUN: %clang_cc1 -fmodules -fblocks -fimplicit-module-maps -fmodules-cache-path=%t/ModulesCache -fdisable-module-hash -fapinotes-modules -fsyntax-only -I %S/Inputs/Headers %s -x c++ // RUN: %clang_cc1 -fmodules -fblocks -fimplicit-module-maps -fmodules-cache-path=%t/ModulesCache -fdisable-module-hash -fapinotes-modules -fsyntax-only -I %S/Inputs/Headers %s -x c++ -ast-dump -ast-dump-filter ImmortalRefType | FileCheck -check-prefix=CHECK-IMMORTAL %s // RUN: %clang_cc1 -fmodules -fblocks -fimplicit-module-maps -fmodules-cache-path=%t/ModulesCache -fdisable-module-hash -fapinotes-modules -fsyntax-only -I %S/Inputs/Headers %s -x c++ -ast-dump -ast-dump-filter RefCountedType | FileCheck -check-prefix=CHECK-REF-COUNTED %s +// RUN: %clang_cc1 -fmodules -fblocks -fimplicit-module-maps -fmodules-cache-path=%t/ModulesCache -fdisable-module-hash -fapinotes-modules -fsyntax-only -I %S/Inputs/Headers %s -x c++ -ast-dump -ast-dump-filter NonCopyableType | FileCheck -check-prefix=CHECK-NON-COPYABLE %s +// RUN: %clang_cc1 -fmodules -fblocks -fimplicit-module-maps -fmodules-cache-path=%t/ModulesCache -fdisable-module-hash -fapinotes-modules -fsyntax-only -I %S/Inputs/Headers %s -x c++ -ast-dump -ast-dump-filter CopyableType | FileCheck -check-prefix=CHECK-COPYABLE %s #include @@ -14,3 +16,11 @@ // CHECK-REF-COUNTED: SwiftAttrAttr {{.+}} <> "import_reference" // CHECK-REF-COUNTED: SwiftAttrAttr {{.+}} <> "retain:RCRetain" // CHECK-REF-COUNTED: SwiftAttrAttr {{.+}} <> "release:RCRelease" + +// CHECK-NON-COPYABLE: Dumping NonCopyableType: +// CHECK-NON-COPYABLE-NEXT: CXXRecordDecl {{.+}} imported in SwiftImportAs {{.+}} struct NonCopyableType +// CHECK-NON-COPYABLE: SwiftAttrAttr {{.+}} <> "~Copyable" + +// CHECK-COPYABLE: Dumping CopyableType: +// CHECK-COPYABLE-NEXT: CXXRecordDecl {{.+}} imported in SwiftImportAs {{.+}} struct CopyableType +// CHECK-COPYABLE-NOT: SwiftAttrAttr -- GitLab From 01d7dcfe5e3b261f587c05e33ffeecae7a11da80 Mon Sep 17 00:00:00 2001 From: Alex Langford Date: Fri, 26 Apr 2024 11:32:12 -0700 Subject: [PATCH 085/301] [lldb] Switch to llvm::DWARFUnitHeader (#89808) These are now close enough that they can be swapped out. --- .../SymbolFile/DWARF/DWARFCompileUnit.h | 2 +- .../Plugins/SymbolFile/DWARF/DWARFTypeUnit.h | 6 +- .../Plugins/SymbolFile/DWARF/DWARFUnit.cpp | 137 +++++------------- .../Plugins/SymbolFile/DWARF/DWARFUnit.h | 68 ++------- 4 files changed, 48 insertions(+), 165 deletions(-) diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.h index dd130977d4b1..b8344f548ac3 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFCompileUnit.h @@ -32,7 +32,7 @@ public: private: DWARFCompileUnit(SymbolFileDWARF &dwarf, lldb::user_id_t uid, - const DWARFUnitHeader &header, + const llvm::DWARFUnitHeader &header, const llvm::DWARFAbbreviationDeclarationSet &abbrevs, DIERef::Section section, bool is_dwo) : DWARFUnit(dwarf, uid, header, abbrevs, section, is_dwo) {} diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFTypeUnit.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFTypeUnit.h index 7b58c632c6c5..8c1f932d8c7f 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFTypeUnit.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFTypeUnit.h @@ -24,15 +24,15 @@ public: void Dump(Stream *s) const override; - uint64_t GetTypeHash() { return m_header.GetTypeHash(); } + uint64_t GetTypeHash() { return m_header.getTypeHash(); } - dw_offset_t GetTypeOffset() { return GetOffset() + m_header.GetTypeOffset(); } + dw_offset_t GetTypeOffset() { return GetOffset() + m_header.getTypeOffset(); } static bool classof(const DWARFUnit *unit) { return unit->IsTypeUnit(); } private: DWARFTypeUnit(SymbolFileDWARF &dwarf, lldb::user_id_t uid, - const DWARFUnitHeader &header, + const llvm::DWARFUnitHeader &header, const llvm::DWARFAbbreviationDeclarationSet &abbrevs, DIERef::Section section, bool is_dwo) : DWARFUnit(dwarf, uid, header, abbrevs, section, is_dwo) {} diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp index e28036d34b34..dabc595427df 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.cpp @@ -33,12 +33,12 @@ using namespace lldb_private::plugin::dwarf; extern int g_verbose; DWARFUnit::DWARFUnit(SymbolFileDWARF &dwarf, lldb::user_id_t uid, - const DWARFUnitHeader &header, + const llvm::DWARFUnitHeader &header, const llvm::DWARFAbbreviationDeclarationSet &abbrevs, DIERef::Section section, bool is_dwo) : UserID(uid), m_dwarf(dwarf), m_header(header), m_abbrevs(&abbrevs), m_cancel_scopes(false), m_section(section), m_is_dwo(is_dwo), - m_has_parsed_non_skeleton_unit(false), m_dwo_id(header.GetDWOId()) {} + m_has_parsed_non_skeleton_unit(false), m_dwo_id(header.getDWOId()) {} DWARFUnit::~DWARFUnit() = default; @@ -345,7 +345,7 @@ void DWARFUnit::ExtractDIEsRWLocked() { void DWARFUnit::SetDwoStrOffsetsBase() { lldb::offset_t baseOffset = 0; - if (const llvm::DWARFUnitIndex::Entry *entry = m_header.GetIndexEntry()) { + if (const llvm::DWARFUnitIndex::Entry *entry = m_header.getIndexEntry()) { if (const auto *contribution = entry->getContribution(llvm::DW_SECT_STR_OFFSETS)) baseOffset = contribution->getOffset(); @@ -489,7 +489,7 @@ ParseListTableHeader(const llvm::DWARFDataExtractor &data, uint64_t offset, void DWARFUnit::SetLoclistsBase(dw_addr_t loclists_base) { uint64_t offset = 0; - if (const llvm::DWARFUnitIndex::Entry *entry = m_header.GetIndexEntry()) { + if (const llvm::DWARFUnitIndex::Entry *entry = m_header.getIndexEntry()) { const auto *contribution = entry->getContribution(llvm::DW_SECT_LOCLISTS); if (!contribution) { GetSymbolFileDWARF().GetObjectFile()->GetModule()->ReportError( @@ -533,7 +533,7 @@ DWARFDataExtractor DWARFUnit::GetLocationData() const { DWARFContext &Ctx = GetSymbolFileDWARF().GetDWARFContext(); const DWARFDataExtractor &data = GetVersion() >= 5 ? Ctx.getOrLoadLocListsData() : Ctx.getOrLoadLocData(); - if (const llvm::DWARFUnitIndex::Entry *entry = m_header.GetIndexEntry()) { + if (const llvm::DWARFUnitIndex::Entry *entry = m_header.getIndexEntry()) { if (const auto *contribution = entry->getContribution( GetVersion() >= 5 ? llvm::DW_SECT_LOCLISTS : llvm::DW_SECT_EXT_LOC)) return DWARFDataExtractor(data, contribution->getOffset(), @@ -546,7 +546,7 @@ DWARFDataExtractor DWARFUnit::GetLocationData() const { DWARFDataExtractor DWARFUnit::GetRnglistData() const { DWARFContext &Ctx = GetSymbolFileDWARF().GetDWARFContext(); const DWARFDataExtractor &data = Ctx.getOrLoadRngListsData(); - if (const llvm::DWARFUnitIndex::Entry *entry = m_header.GetIndexEntry()) { + if (const llvm::DWARFUnitIndex::Entry *entry = m_header.getIndexEntry()) { if (const auto *contribution = entry->getContribution(llvm::DW_SECT_RNGLISTS)) return DWARFDataExtractor(data, contribution->getOffset(), @@ -924,84 +924,6 @@ const DWARFDebugAranges &DWARFUnit::GetFunctionAranges() { return *m_func_aranges_up; } -llvm::Error DWARFUnitHeader::ApplyIndexEntry( - const llvm::DWARFUnitIndex::Entry *index_entry) { - // We should only be calling this function when the index entry is not set and - // we have a valid one to set it to. - assert(index_entry); - assert(!m_index_entry); - - if (m_abbr_offset) - return llvm::createStringError( - llvm::inconvertibleErrorCode(), - "Package unit with a non-zero abbreviation offset"); - - auto *unit_contrib = index_entry->getContribution(); - if (!unit_contrib || unit_contrib->getLength32() != m_length + 4) - return llvm::createStringError(llvm::inconvertibleErrorCode(), - "Inconsistent DWARF package unit index"); - - auto *abbr_entry = index_entry->getContribution(llvm::DW_SECT_ABBREV); - if (!abbr_entry) - return llvm::createStringError( - llvm::inconvertibleErrorCode(), - "DWARF package index missing abbreviation column"); - - m_abbr_offset = abbr_entry->getOffset(); - m_index_entry = index_entry; - return llvm::Error::success(); -} - -llvm::Expected -DWARFUnitHeader::extract(const DWARFDataExtractor &data, - DIERef::Section section, DWARFContext &context, - lldb::offset_t *offset_ptr) { - DWARFUnitHeader header; - header.m_offset = *offset_ptr; - header.m_length = data.GetDWARFInitialLength(offset_ptr); - header.m_version = data.GetU16(offset_ptr); - if (header.m_version == 5) { - header.m_unit_type = data.GetU8(offset_ptr); - header.m_addr_size = data.GetU8(offset_ptr); - header.m_abbr_offset = data.GetDWARFOffset(offset_ptr); - if (header.m_unit_type == llvm::dwarf::DW_UT_skeleton || - header.m_unit_type == llvm::dwarf::DW_UT_split_compile) - header.m_dwo_id = data.GetU64(offset_ptr); - } else { - header.m_abbr_offset = data.GetDWARFOffset(offset_ptr); - header.m_addr_size = data.GetU8(offset_ptr); - header.m_unit_type = - section == DIERef::Section::DebugTypes ? DW_UT_type : DW_UT_compile; - } - - if (header.IsTypeUnit()) { - header.m_type_hash = data.GetU64(offset_ptr); - header.m_type_offset = data.GetDWARFOffset(offset_ptr); - } - - bool length_OK = data.ValidOffset(header.GetNextUnitOffset() - 1); - bool version_OK = SymbolFileDWARF::SupportedVersion(header.m_version); - bool addr_size_OK = (header.m_addr_size == 2) || (header.m_addr_size == 4) || - (header.m_addr_size == 8); - bool type_offset_OK = - !header.IsTypeUnit() || (header.m_type_offset <= header.GetLength()); - - if (!length_OK) - return llvm::make_error( - "Invalid unit length"); - if (!version_OK) - return llvm::make_error( - "Unsupported unit version"); - if (!addr_size_OK) - return llvm::make_error( - "Invalid unit address size"); - if (!type_offset_OK) - return llvm::make_error( - "Type offset out of range"); - - return header; -} - llvm::Expected DWARFUnit::extract(SymbolFileDWARF &dwarf, user_id_t uid, const DWARFDataExtractor &debug_info, @@ -1009,26 +931,35 @@ DWARFUnit::extract(SymbolFileDWARF &dwarf, user_id_t uid, assert(debug_info.ValidOffset(*offset_ptr)); DWARFContext &context = dwarf.GetDWARFContext(); - auto expected_header = - DWARFUnitHeader::extract(debug_info, section, context, offset_ptr); - if (!expected_header) - return expected_header.takeError(); + + // FIXME: Either properly map between DIERef::Section and + // llvm::DWARFSectionKind or switch to llvm's definition entirely. + llvm::DWARFSectionKind section_kind_llvm = + section == DIERef::Section::DebugInfo + ? llvm::DWARFSectionKind::DW_SECT_INFO + : llvm::DWARFSectionKind::DW_SECT_EXT_TYPES; + + llvm::DWARFDataExtractor debug_info_llvm = debug_info.GetAsLLVMDWARF(); + llvm::DWARFUnitHeader header; + if (llvm::Error extract_err = header.extract( + context.GetAsLLVM(), debug_info_llvm, offset_ptr, section_kind_llvm)) + return std::move(extract_err); if (context.isDwo()) { const llvm::DWARFUnitIndex::Entry *entry = nullptr; - const llvm::DWARFUnitIndex &index = expected_header->IsTypeUnit() + const llvm::DWARFUnitIndex &index = header.isTypeUnit() ? context.GetAsLLVM().getTUIndex() : context.GetAsLLVM().getCUIndex(); if (index) { - if (expected_header->IsTypeUnit()) - entry = index.getFromHash(expected_header->GetTypeHash()); - else if (auto dwo_id = expected_header->GetDWOId()) + if (header.isTypeUnit()) + entry = index.getFromHash(header.getTypeHash()); + else if (auto dwo_id = header.getDWOId()) entry = index.getFromHash(*dwo_id); } if (!entry) - entry = index.getFromOffset(expected_header->GetOffset()); + entry = index.getFromOffset(header.getOffset()); if (entry) - if (llvm::Error err = expected_header->ApplyIndexEntry(entry)) + if (llvm::Error err = header.applyIndexEntry(entry)) return std::move(err); } @@ -1039,13 +970,13 @@ DWARFUnit::extract(SymbolFileDWARF &dwarf, user_id_t uid, bool abbr_offset_OK = dwarf.GetDWARFContext().getOrLoadAbbrevData().ValidOffset( - expected_header->GetAbbrOffset()); + header.getAbbrOffset()); if (!abbr_offset_OK) return llvm::make_error( "Abbreviation offset for unit is not valid"); llvm::Expected abbrevs_or_err = - abbr->getAbbreviationDeclarationSet(expected_header->GetAbbrOffset()); + abbr->getAbbreviationDeclarationSet(header.getAbbrOffset()); if (!abbrevs_or_err) return abbrevs_or_err.takeError(); @@ -1055,11 +986,11 @@ DWARFUnit::extract(SymbolFileDWARF &dwarf, user_id_t uid, "No abbrev exists at the specified offset."); bool is_dwo = dwarf.GetDWARFContext().isDwo(); - if (expected_header->IsTypeUnit()) - return DWARFUnitSP(new DWARFTypeUnit(dwarf, uid, *expected_header, *abbrevs, - section, is_dwo)); - return DWARFUnitSP(new DWARFCompileUnit(dwarf, uid, *expected_header, - *abbrevs, section, is_dwo)); + if (header.isTypeUnit()) + return DWARFUnitSP( + new DWARFTypeUnit(dwarf, uid, header, *abbrevs, section, is_dwo)); + return DWARFUnitSP( + new DWARFCompileUnit(dwarf, uid, header, *abbrevs, section, is_dwo)); } const lldb_private::DWARFDataExtractor &DWARFUnit::GetData() const { @@ -1069,7 +1000,7 @@ const lldb_private::DWARFDataExtractor &DWARFUnit::GetData() const { } uint32_t DWARFUnit::GetHeaderByteSize() const { - switch (m_header.GetUnitType()) { + switch (m_header.getUnitType()) { case llvm::dwarf::DW_UT_compile: case llvm::dwarf::DW_UT_partial: return GetVersion() < 5 ? 11 : 12; @@ -1106,7 +1037,7 @@ DWARFUnit::FindRnglistFromOffset(dw_offset_t offset) { llvm::DWARFDataExtractor data = GetRnglistData().GetAsLLVMDWARF(); // As DW_AT_rnglists_base may be missing we need to call setAddressSize. - data.setAddressSize(m_header.GetAddressByteSize()); + data.setAddressSize(m_header.getAddressByteSize()); auto range_list_or_error = GetRnglistTable()->findList(data, offset); if (!range_list_or_error) return range_list_or_error.takeError(); diff --git a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h index 28981b51bfcb..85c37971ced8 100644 --- a/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h +++ b/lldb/source/Plugins/SymbolFile/DWARF/DWARFUnit.h @@ -38,54 +38,6 @@ enum DWARFProducer { eProducerOther }; -/// Base class describing the header of any kind of "unit." Some information -/// is specific to certain unit types. We separate this class out so we can -/// parse the header before deciding what specific kind of unit to construct. -class DWARFUnitHeader { - dw_offset_t m_offset = 0; - dw_offset_t m_length = 0; - uint16_t m_version = 0; - dw_offset_t m_abbr_offset = 0; - - const llvm::DWARFUnitIndex::Entry *m_index_entry = nullptr; - - uint8_t m_unit_type = 0; - uint8_t m_addr_size = 0; - - uint64_t m_type_hash = 0; - uint32_t m_type_offset = 0; - - std::optional m_dwo_id; - - DWARFUnitHeader() = default; - -public: - dw_offset_t GetOffset() const { return m_offset; } - uint16_t GetVersion() const { return m_version; } - uint16_t GetAddressByteSize() const { return m_addr_size; } - dw_offset_t GetLength() const { return m_length; } - dw_offset_t GetAbbrOffset() const { return m_abbr_offset; } - uint8_t GetUnitType() const { return m_unit_type; } - const llvm::DWARFUnitIndex::Entry *GetIndexEntry() const { - return m_index_entry; - } - uint64_t GetTypeHash() const { return m_type_hash; } - dw_offset_t GetTypeOffset() const { return m_type_offset; } - std::optional GetDWOId() const { return m_dwo_id; } - bool IsTypeUnit() const { - return m_unit_type == llvm::dwarf::DW_UT_type || - m_unit_type == llvm::dwarf::DW_UT_split_type; - } - dw_offset_t GetNextUnitOffset() const { return m_offset + m_length + 4; } - - llvm::Error ApplyIndexEntry(const llvm::DWARFUnitIndex::Entry *index_entry); - - static llvm::Expected extract(const DWARFDataExtractor &data, - DIERef::Section section, - DWARFContext &dwarf_context, - lldb::offset_t *offset_ptr); -}; - class DWARFUnit : public UserID { using die_iterator_range = llvm::iterator_range; @@ -105,7 +57,7 @@ public: /// the DWO ID in the compile unit header and we sometimes only want to access /// this cheap value without causing the more expensive attribute fetches that /// GetDWOId() uses. - std::optional GetHeaderDWOId() { return m_header.GetDWOId(); } + std::optional GetHeaderDWOId() { return m_header.getDWOId(); } void ExtractUnitDIEIfNeeded(); void ExtractUnitDIENoDwoIfNeeded(); void ExtractDIEsIfNeeded(); @@ -143,7 +95,7 @@ public: uint32_t GetHeaderByteSize() const; // Offset of the initial length field. - dw_offset_t GetOffset() const { return m_header.GetOffset(); } + dw_offset_t GetOffset() const { return m_header.getOffset(); } /// Get the size in bytes of the length field in the header. /// /// In DWARF32 this is just 4 bytes @@ -159,15 +111,15 @@ public: dw_offset_t GetFirstDIEOffset() const { return GetOffset() + GetHeaderByteSize(); } - dw_offset_t GetNextUnitOffset() const { return m_header.GetNextUnitOffset(); } + dw_offset_t GetNextUnitOffset() const { return m_header.getNextUnitOffset(); } // Size of the CU data (without initial length and without header). size_t GetDebugInfoSize() const; // Size of the CU data incl. header but without initial length. - dw_offset_t GetLength() const { return m_header.GetLength(); } - uint16_t GetVersion() const { return m_header.GetVersion(); } + dw_offset_t GetLength() const { return m_header.getLength(); } + uint16_t GetVersion() const { return m_header.getVersion(); } const llvm::DWARFAbbreviationDeclarationSet *GetAbbreviations() const; dw_offset_t GetAbbrevOffset() const; - uint8_t GetAddressByteSize() const { return m_header.GetAddressByteSize(); } + uint8_t GetAddressByteSize() const { return m_header.getAddressByteSize(); } dw_addr_t GetAddrBase() const { return m_addr_base.value_or(0); } dw_addr_t GetBaseAddress() const { return m_base_addr; } dw_offset_t GetLineTableOffset(); @@ -250,8 +202,8 @@ public: DIERef::Section GetDebugSection() const { return m_section; } - uint8_t GetUnitType() const { return m_header.GetUnitType(); } - bool IsTypeUnit() const { return m_header.IsTypeUnit(); } + uint8_t GetUnitType() const { return m_header.getUnitType(); } + bool IsTypeUnit() const { return m_header.isTypeUnit(); } /// Note that this check only works for DWARF5+. bool IsSkeletonUnit() const { return GetUnitType() == llvm::dwarf::DW_UT_skeleton; @@ -320,7 +272,7 @@ public: protected: DWARFUnit(SymbolFileDWARF &dwarf, lldb::user_id_t uid, - const DWARFUnitHeader &header, + const llvm::DWARFUnitHeader &header, const llvm::DWARFAbbreviationDeclarationSet &abbrevs, DIERef::Section section, bool is_dwo); @@ -352,7 +304,7 @@ protected: SymbolFileDWARF &m_dwarf; std::shared_ptr m_dwo; - DWARFUnitHeader m_header; + llvm::DWARFUnitHeader m_header; const llvm::DWARFAbbreviationDeclarationSet *m_abbrevs = nullptr; lldb_private::CompileUnit *m_lldb_cu = nullptr; // If this is a DWO file, we have a backlink to our skeleton compile unit. -- GitLab From 79314c64d0f88fa4ccc1709dee373fdfb9a6ca49 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Fri, 26 Apr 2024 11:22:52 -0700 Subject: [PATCH 086/301] [SLP]Fix PR90224: check that users of gep are all vectorized. Before deleting extractelement instruction for vectorized GEP with external users, need to check that all users vectorized before deleting this extractelement. --- .../Transforms/Vectorize/SLPVectorizer.cpp | 15 +++++++++-- .../X86/gep-with-extractelement-many-users.ll | 26 +++++++++++++++++++ 2 files changed, 39 insertions(+), 2 deletions(-) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index fbece8c0109c..f62270fe62eb 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -8499,6 +8499,12 @@ public: const TreeEntry *VE = R.getTreeEntry(V); if (!CheckedExtracts.insert(V).second || !R.areAllUsersVectorized(cast(V), &VectorizedVals) || + any_of(EE->users(), + [&](User *U) { + return isa(U) && + !R.areAllUsersVectorized(cast(U), + &VectorizedVals); + }) || (VE && VE != E)) continue; std::optional EEIdx = getExtractIndex(EE); @@ -11397,6 +11403,8 @@ public: any_of(EI->users(), [&](User *U) { const TreeEntry *UTE = R.getTreeEntry(U); return !UTE || R.MultiNodeScalars.contains(U) || + (isa(U) && + !R.areAllUsersVectorized(cast(U))) || count_if(R.VectorizableTree, [&](const std::unique_ptr &TE) { return any_of(TE->UserTreeIndices, @@ -13329,8 +13337,11 @@ Value *BoUpSLP::vectorizeTree( // Leave the GEPs as is, they are free in most cases and better to // keep them as GEPs. auto *CloneGEP = GEP->clone(); - CloneGEP->insertBefore(*Builder.GetInsertBlock(), - Builder.GetInsertPoint()); + if (isa(Vec)) + CloneGEP->insertBefore(*Builder.GetInsertBlock(), + Builder.GetInsertPoint()); + else + CloneGEP->insertBefore(GEP); if (GEP->hasName()) CloneGEP->takeName(GEP); Ex = CloneGEP; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll b/llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll new file mode 100644 index 000000000000..37d166953c33 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/gep-with-extractelement-many-users.ll @@ -0,0 +1,26 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -slp-threshold=-99999 < %s | FileCheck %s + +define void @test() { +; CHECK-LABEL: define void @test() { +; CHECK-NEXT: bb: +; CHECK-NEXT: [[TMP0:%.*]] = extractelement <2 x ptr> zeroinitializer, i32 0 +; CHECK-NEXT: [[GETELEMENTPTR6:%.*]] = getelementptr i8, ptr [[TMP0]], i64 872 +; CHECK-NEXT: store double 0.000000e+00, ptr [[GETELEMENTPTR6]], align 8 +; CHECK-NEXT: br label [[BB9:%.*]] +; CHECK: bb9: +; CHECK-NEXT: [[TMP1:%.*]] = phi <2 x ptr> [ getelementptr (i8, <2 x ptr> zeroinitializer, <2 x i64> ), [[BB:%.*]] ] +; CHECK-NEXT: ret void +; +bb: + %getelementptr = getelementptr i8, ptr null, i64 32 + %0 = extractelement <2 x ptr> zeroinitializer, i32 0 + %getelementptr6 = getelementptr i8, ptr %0, i64 872 + store double 0.000000e+00, ptr %getelementptr6, align 8 + br label %bb9 + +bb9: + %phi10 = phi ptr [ %getelementptr, %bb ] + %phi11 = phi ptr [ %getelementptr6, %bb ] + ret void +} -- GitLab From 266a9274dd14d06d559ca8a37e2d1b5f985a5398 Mon Sep 17 00:00:00 2001 From: Marc Auberer Date: Fri, 26 Apr 2024 20:57:04 +0200 Subject: [PATCH 087/301] [lldb] Fix typo in CumulativeSystemTimeIsValid check (#89680) Resolves #89674 --- lldb/include/lldb/Utility/ProcessInfo.h | 2 +- lldb/unittests/Host/HostTest.cpp | 21 +++++++++++++++++++++ 2 files changed, 22 insertions(+), 1 deletion(-) diff --git a/lldb/include/lldb/Utility/ProcessInfo.h b/lldb/include/lldb/Utility/ProcessInfo.h index e9fe71e1b851..54ac000dc7fc 100644 --- a/lldb/include/lldb/Utility/ProcessInfo.h +++ b/lldb/include/lldb/Utility/ProcessInfo.h @@ -234,7 +234,7 @@ public: bool CumulativeSystemTimeIsValid() const { return m_cumulative_system_time.tv_sec > 0 || - m_cumulative_system_time.tv_sec > 0; + m_cumulative_system_time.tv_usec > 0; } void Dump(Stream &s, UserIDResolver &resolver) const; diff --git a/lldb/unittests/Host/HostTest.cpp b/lldb/unittests/Host/HostTest.cpp index 5e01a6835c03..a1d8a3b7f485 100644 --- a/lldb/unittests/Host/HostTest.cpp +++ b/lldb/unittests/Host/HostTest.cpp @@ -7,6 +7,7 @@ //===----------------------------------------------------------------------===// #include "lldb/Host/Host.h" +#include "lldb/Utility/ProcessInfo.h" #include "gtest/gtest.h" using namespace lldb_private; @@ -25,3 +26,23 @@ TEST(Host, GetEnvironment) { ASSERT_EQ("Host::GetEnvironment", Host::GetEnvironment().lookup("LLDB_TEST_ENVIRONMENT_VAR")); } + +TEST(Host, ProcessInstanceInfoCumulativeUserTimeIsValid) { + ProcessInstanceInfo info; + info.SetCumulativeUserTime(ProcessInstanceInfo::timespec{0, 0}); + EXPECT_FALSE(info.CumulativeUserTimeIsValid()); + info.SetCumulativeUserTime(ProcessInstanceInfo::timespec{0, 1}); + EXPECT_TRUE(info.CumulativeUserTimeIsValid()); + info.SetCumulativeUserTime(ProcessInstanceInfo::timespec{1, 0}); + EXPECT_TRUE(info.CumulativeUserTimeIsValid()); +} + +TEST(Host, ProcessInstanceInfoCumulativeSystemTimeIsValid) { + ProcessInstanceInfo info; + info.SetCumulativeSystemTime(ProcessInstanceInfo::timespec{0, 0}); + EXPECT_FALSE(info.CumulativeSystemTimeIsValid()); + info.SetCumulativeSystemTime(ProcessInstanceInfo::timespec{0, 1}); + EXPECT_TRUE(info.CumulativeSystemTimeIsValid()); + info.SetCumulativeSystemTime(ProcessInstanceInfo::timespec{1, 0}); + EXPECT_TRUE(info.CumulativeSystemTimeIsValid()); +} \ No newline at end of file -- GitLab From 72b0c11cfd267b754076dfc2908ba921c4f69ee3 Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Fri, 26 Apr 2024 13:58:11 -0500 Subject: [PATCH 088/301] [Libomptarget] Rename `libomptarget.rtl.x86_64` to `libomptarget.rtl.host` (#86868) Summary: All of these are functionally the same code, just compiled for separate architectures. We currently do not expose a way to execute these on separate architectures as the host plugin works using `dlopen` into the same process, and therefore cannot possibly be an incompatible architecture. (This could work with a remote plugin, but this is not supported yet). This patch simply renames all of these to the same thing so we no longer need to check around for its varying definitions. --- offload/plugins-nextgen/host/CMakeLists.txt | 40 ++++++++++----------- offload/src/CMakeLists.txt | 5 +-- 2 files changed, 21 insertions(+), 24 deletions(-) diff --git a/offload/plugins-nextgen/host/CMakeLists.txt b/offload/plugins-nextgen/host/CMakeLists.txt index 7da18ee278d4..6407f72e8db0 100644 --- a/offload/plugins-nextgen/host/CMakeLists.txt +++ b/offload/plugins-nextgen/host/CMakeLists.txt @@ -14,36 +14,36 @@ if(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64le$") endif() # Create the library and add the default arguments. -add_target_library(omptarget.rtl.${machine} ${machine}) +add_target_library(omptarget.rtl.host ${machine}) -target_sources(omptarget.rtl.${machine} PRIVATE src/rtl.cpp) +target_sources(omptarget.rtl.host PRIVATE src/rtl.cpp) if(LIBOMPTARGET_DEP_LIBFFI_FOUND) libomptarget_say("Building ${machine} plugin linked with libffi") if(FFI_STATIC_LIBRARIES) - target_link_libraries(omptarget.rtl.${machine} PRIVATE FFI::ffi_static) + target_link_libraries(omptarget.rtl.host PRIVATE FFI::ffi_static) else() - target_link_libraries(omptarget.rtl.${machine} PRIVATE FFI::ffi) + target_link_libraries(omptarget.rtl.host PRIVATE FFI::ffi) endif() else() libomptarget_say("Building ${machine} plugin for dlopened libffi") - target_sources(omptarget.rtl.${machine} PRIVATE dynamic_ffi/ffi.cpp) - target_include_directories(omptarget.rtl.${machine} PRIVATE dynamic_ffi) + target_sources(omptarget.rtl.host PRIVATE dynamic_ffi/ffi.cpp) + target_include_directories(omptarget.rtl.host PRIVATE dynamic_ffi) endif() # Install plugin under the lib destination folder. -install(TARGETS omptarget.rtl.${machine} +install(TARGETS omptarget.rtl.host LIBRARY DESTINATION "${OFFLOAD_INSTALL_LIBDIR}") -set_target_properties(omptarget.rtl.${machine} PROPERTIES +set_target_properties(omptarget.rtl.host PROPERTIES INSTALL_RPATH "$ORIGIN" BUILD_RPATH "$ORIGIN:${CMAKE_CURRENT_BINARY_DIR}/.." POSITION_INDEPENDENT_CODE ON CXX_VISIBILITY_PRESET protected) -target_include_directories(omptarget.rtl.${machine} PRIVATE +target_include_directories(omptarget.rtl.host PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) if(LIBOMPTARGET_DEP_LIBFFI_FOUND) - list(APPEND LIBOMPTARGET_TESTED_PLUGINS omptarget.rtl.${machine}) + list(APPEND LIBOMPTARGET_TESTED_PLUGINS omptarget.rtl.host) set(LIBOMPTARGET_TESTED_PLUGINS "${LIBOMPTARGET_TESTED_PLUGINS}" PARENT_SCOPE) else() @@ -52,36 +52,36 @@ endif() # Define the target specific triples and ELF machine values. if(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64le$") - target_compile_definitions(omptarget.rtl.${machine} PRIVATE TARGET_ELF_ID=EM_PPC64) - target_compile_definitions(omptarget.rtl.${machine} PRIVATE + target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_PPC64) + target_compile_definitions(omptarget.rtl.host PRIVATE LIBOMPTARGET_NEXTGEN_GENERIC_PLUGIN_TRIPLE="powerpc64le-ibm-linux-gnu") list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "powerpc64le-ibm-linux-gnu" "powerpc64le-ibm-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "ppc64$") - target_compile_definitions(omptarget.rtl.${machine} PRIVATE TARGET_ELF_ID=EM_PPC64) - target_compile_definitions(omptarget.rtl.${machine} PRIVATE + target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_PPC64) + target_compile_definitions(omptarget.rtl.host PRIVATE LIBOMPTARGET_NEXTGEN_GENERIC_PLUGIN_TRIPLE="powerpc64-ibm-linux-gnu") list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "powerpc64-ibm-linux-gnu" "powerpc64-ibm-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "x86_64$") - target_compile_definitions(omptarget.rtl.${machine} PRIVATE TARGET_ELF_ID=EM_X86_64) - target_compile_definitions(omptarget.rtl.${machine} PRIVATE + target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_X86_64) + target_compile_definitions(omptarget.rtl.host PRIVATE LIBOMPTARGET_NEXTGEN_GENERIC_PLUGIN_TRIPLE="x86_64-pc-linux-gnu") list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "x86_64-pc-linux-gnu" "x86_64-pc-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "aarch64$") - target_compile_definitions(omptarget.rtl.${machine} PRIVATE TARGET_ELF_ID=EM_AARCH64) - target_compile_definitions(omptarget.rtl.${machine} PRIVATE + target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_AARCH64) + target_compile_definitions(omptarget.rtl.host PRIVATE LIBOMPTARGET_NEXTGEN_GENERIC_PLUGIN_TRIPLE="aarch64-unknown-linux-gnu") list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "aarch64-unknown-linux-gnu" "aarch64-unknown-linux-gnu-LTO") set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) elseif(CMAKE_SYSTEM_PROCESSOR MATCHES "s390x$") - target_compile_definitions(omptarget.rtl.${machine} PRIVATE TARGET_ELF_ID=EM_S390) - target_compile_definitions(omptarget.rtl.${machine} PRIVATE + target_compile_definitions(omptarget.rtl.host PRIVATE TARGET_ELF_ID=EM_S390) + target_compile_definitions(omptarget.rtl.host PRIVATE LIBOMPTARGET_NEXTGEN_GENERIC_PLUGIN_TRIPLE="s390x-ibm-linux-gnu") list(APPEND LIBOMPTARGET_SYSTEM_TARGETS "s390x-ibm-linux-gnu" "s390x-ibm-linux-gnu-LTO") diff --git a/offload/src/CMakeLists.txt b/offload/src/CMakeLists.txt index fb1ad3d7ae70..8b7be98771a9 100644 --- a/offload/src/CMakeLists.txt +++ b/offload/src/CMakeLists.txt @@ -74,12 +74,9 @@ endmacro() set(LIBOMPTARGET_PLUGINS_TO_LOAD "" CACHE STRING "Comma separated list of plugin names to look for at runtime") if (NOT LIBOMPTARGET_PLUGINS_TO_LOAD) - check_plugin_target(ppc64) - check_plugin_target(x86_64) check_plugin_target(cuda) - check_plugin_target(aarch64) check_plugin_target(amdgpu) - check_plugin_target(s390x) + check_plugin_target(host) endif() list(TRANSFORM LIBOMPTARGET_PLUGINS_TO_LOAD PREPEND "\"libomptarget.rtl.") -- GitLab From ac45bb5cbc4e37b41b78614f0cdd67d70485019a Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 26 Apr 2024 11:53:18 -0700 Subject: [PATCH 089/301] [RISCV] Consistently use uint32_t in Disassembler decode functions. NFC We had some uses of uint64_t and unsigned. These all come from tblgen code that is templated on InsnType which is currently uint32_t. --- .../Target/RISCV/Disassembler/RISCVDisassembler.cpp | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 998b9181efe6..3cd6e7434183 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -182,7 +182,7 @@ static DecodeStatus DecodeGPRPairRegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } -static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint64_t RegNo, +static DecodeStatus DecodeSR07RegisterClass(MCInst &Inst, uint32_t RegNo, uint64_t Address, const void *Decoder) { if (RegNo >= 8) @@ -255,7 +255,7 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, return MCDisassembler::Success; } -static DecodeStatus decodeVMaskReg(MCInst &Inst, uint64_t RegNo, +static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { if (RegNo > 2) { @@ -361,13 +361,13 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder); -static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, +static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder); static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, const MCDisassembler *Decoder); -static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, +static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder); static DecodeStatus decodeCSSPushPopchk(MCInst &Inst, uint32_t Insn, @@ -470,7 +470,7 @@ static DecodeStatus decodeXTHeadMemPair(MCInst &Inst, uint32_t Insn, return MCDisassembler::Success; } -static DecodeStatus decodeZcmpRlist(MCInst &Inst, unsigned Imm, +static DecodeStatus decodeZcmpRlist(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder) { if (Imm <= 3) return MCDisassembler::Fail; @@ -487,7 +487,7 @@ static DecodeStatus decodeRegReg(MCInst &Inst, uint32_t Insn, uint64_t Address, return MCDisassembler::Success; } -static DecodeStatus decodeZcmpSpimm(MCInst &Inst, unsigned Imm, +static DecodeStatus decodeZcmpSpimm(MCInst &Inst, uint32_t Imm, uint64_t Address, const void *Decoder) { Inst.addOperand(MCOperand::createImm(Imm)); return MCDisassembler::Success; -- GitLab From 56c4971d33230607a7329bb831b6c8588231e872 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 26 Apr 2024 11:59:03 -0700 Subject: [PATCH 090/301] [Driver,test] Replace CHECK-NOT: warning with -### -Werror After https://reviews.llvm.org/D156363 changed -### to exist with code 1 if hasErrorOccurred, we can use -Werror to assert no warnings. This is more reliable than a NOT pattern, which may go stale (when the diagnostic is updated) without being noticed. --- clang/test/Driver/claim-unused.c | 3 --- clang/test/Driver/fp-model.c | 5 ++-- clang/test/Driver/gcc-param.c | 2 ++ clang/test/Driver/linux-ld.c | 45 +++++++++++--------------------- 4 files changed, 19 insertions(+), 36 deletions(-) delete mode 100644 clang/test/Driver/claim-unused.c create mode 100644 clang/test/Driver/gcc-param.c diff --git a/clang/test/Driver/claim-unused.c b/clang/test/Driver/claim-unused.c deleted file mode 100644 index c7b798934b3c..000000000000 --- a/clang/test/Driver/claim-unused.c +++ /dev/null @@ -1,3 +0,0 @@ -// RUN: touch %t.o -// RUN: %clang --param ssp-buffer-size=1 %t.o -### 2>&1 | FileCheck %s -// CHECK-NOT: warning: argument unused during compilation: '--param ssp-buffer-size=1' diff --git a/clang/test/Driver/fp-model.c b/clang/test/Driver/fp-model.c index 74b7de7a275a..a464729edb45 100644 --- a/clang/test/Driver/fp-model.c +++ b/clang/test/Driver/fp-model.c @@ -73,9 +73,8 @@ // RUN: %clang -### -Ofast -ffp-model=strict -c %s 2>&1 | FileCheck \ // RUN: --check-prefix=WARN12 %s -// RUN: %clang -### -ffast-math -ffp-model=strict -c %s 2>&1 | FileCheck \ -// RUN: --check-prefix=WARN12 %s -// WARN12-NOT: warning: overriding '-ffp-model=strict' option with '-ffp-model=strict' [-Woverriding-option] +// RUN: %clang -### -Werror -ffast-math -ffp-model=strict -c %s +// WARN12: warning: overriding '-ffp-model=strict' option with '-Ofast' // RUN: %clang -### -ffp-model=strict -fapprox-func -c %s 2>&1 \ // RUN: | FileCheck --check-prefix=WARN13 %s diff --git a/clang/test/Driver/gcc-param.c b/clang/test/Driver/gcc-param.c new file mode 100644 index 000000000000..4672e1156ce7 --- /dev/null +++ b/clang/test/Driver/gcc-param.c @@ -0,0 +1,2 @@ +// RUN: touch %t.o +// RUN: %clang -Werror --param ssp-buffer-size=1 %t.o -### diff --git a/clang/test/Driver/linux-ld.c b/clang/test/Driver/linux-ld.c index 958e682b6c3c..e2043ab22afc 100644 --- a/clang/test/Driver/linux-ld.c +++ b/clang/test/Driver/linux-ld.c @@ -2,11 +2,10 @@ // General tests that ld invocations on Linux targets sane. Note that we use // sysroot to make these tests independent of the host system. // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### -Werror %s -no-pie 2>&1 \ // RUN: --target=i386-unknown-linux -rtlib=platform --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-32 %s -// CHECK-LD-32-NOT: warning: // CHECK-LD-32: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-32: "{{.*}}/usr/lib/gcc/i386-unknown-linux/10.2.0{{/|\\\\}}crtbegin.o" // CHECK-LD-32: "-L[[SYSROOT]]/usr/lib/gcc/i386-unknown-linux/10.2.0" @@ -14,11 +13,10 @@ // CHECK-LD-32: "-L[[SYSROOT]]/lib" // CHECK-LD-32: "-L[[SYSROOT]]/usr/lib" // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-64 %s -// CHECK-LD-64-NOT: warning: // CHECK-LD-64: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-64: "--eh-frame-hdr" // CHECK-LD-64: "-m" "elf_x86_64" @@ -32,11 +30,10 @@ // CHECK-LD-64: "-lc" // CHECK-LD-64: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux-gnux32 -rtlib=platform --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-X32 %s -// CHECK-LD-X32-NOT: warning: // CHECK-LD-X32: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-X32: "--eh-frame-hdr" // CHECK-LD-X32: "-m" "elf32_x86_64" @@ -45,13 +42,12 @@ // CHECK-LD-X32: "-lc" // CHECK-LD-X32: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux \ // RUN: -resource-dir=%S/Inputs/resource_dir \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: --rtlib=compiler-rt \ // RUN: | FileCheck --check-prefix=CHECK-LD-RT %s -// CHECK-LD-RT-NOT: warning: // CHECK-LD-RT: "-resource-dir" "[[RESDIR:[^"]*]]" // CHECK-LD-RT: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-RT: "--eh-frame-hdr" @@ -67,13 +63,12 @@ // CHECK-LD-RT: libclang_rt.builtins.a" // CHECK-LD-RT: "[[RESDIR]]{{/|\\\\}}lib{{/|\\\\}}x86_64-unknown-linux{{/|\\\\}}clang_rt.crtend.o" // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=i686-unknown-linux \ // RUN: -resource-dir=%S/Inputs/resource_dir \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: --rtlib=compiler-rt \ // RUN: | FileCheck --check-prefix=CHECK-LD-RT-I686 %s -// CHECK-LD-RT-I686-NOT: warning: // CHECK-LD-RT-I686: "-resource-dir" "[[RESDIR:[^"]*]]" // CHECK-LD-RT-I686: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-RT-I686: "--eh-frame-hdr" @@ -89,13 +84,12 @@ // CHECK-LD-RT-I686: libclang_rt.builtins.a" // CHECK-LD-RT-I686: "[[RESDIR]]{{/|\\\\}}lib{{/|\\\\}}i686-unknown-linux{{/|\\\\}}clang_rt.crtend.o" // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=arm-linux-androideabi \ // RUN: --sysroot=%S/Inputs/basic_android_tree/sysroot \ // RUN: -resource-dir=%S/Inputs/resource_dir \ // RUN: --rtlib=compiler-rt \ // RUN: | FileCheck --check-prefix=CHECK-LD-RT-ANDROID %s -// CHECK-LD-RT-ANDROID-NOT: warning: // CHECK-LD-RT-ANDROID: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-RT-ANDROID: "--eh-frame-hdr" // CHECK-LD-RT-ANDROID: "-m" "armelf_linux_eabi" @@ -104,11 +98,10 @@ // CHECK-LD-RT-ANDROID: "-lc" // CHECK-LD-RT-ANDROID: libclang_rt.builtins.a" // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-GCC %s -// CHECK-LD-GCC-NOT: warning: // CHECK-LD-GCC: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-GCC: "--eh-frame-hdr" // CHECK-LD-GCC: "-m" "elf_x86_64" @@ -122,12 +115,11 @@ // CHECK-LD-GCC: "-lc" // CHECK-LD-GCC: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" // -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ // RUN: -static-libgcc \ // RUN: --sysroot=%S/Inputs/basic_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-64-STATIC-LIBGCC %s -// CHECK-LD-64-STATIC-LIBGCC-NOT: warning: // CHECK-LD-64-STATIC-LIBGCC: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-64-STATIC-LIBGCC: "--eh-frame-hdr" // CHECK-LD-64-STATIC-LIBGCC: "-m" "elf_x86_64" @@ -268,12 +260,10 @@ // CHECK-CLANG-ANDROID-STATIC: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-CLANG-ANDROID-STATIC: "--start-group" "{{[^"]*}}{{/|\\\\}}libclang_rt.builtins.a" "-l:libunwind.a" "-lc" "--end-group" // -// RUN: %clang -### %s 2>&1 \ -// RUN: --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ +// RUN: %clang -### %s -Werror --target=x86_64-unknown-linux -rtlib=platform --unwindlib=platform \ // RUN: -static \ -// RUN: --sysroot=%S/Inputs/basic_linux_tree \ +// RUN: --sysroot=%S/Inputs/basic_linux_tree 2>&1 \ // RUN: | FileCheck --check-prefix=CHECK-LD-64-STATIC %s -// CHECK-LD-64-STATIC-NOT: warning: // CHECK-LD-64-STATIC: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-64-STATIC: "--eh-frame-hdr" // CHECK-LD-64-STATIC: "-m" "elf_x86_64" @@ -486,13 +476,12 @@ // // Test that we can use -stdlib=libc++ in a build system even when it // occasionally links C code instead of C++ code. -// RUN: %clang -x c -### %s -no-pie 2>&1 \ +// RUN: %clang -x c -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux-gnu \ // RUN: -stdlib=libc++ \ // RUN: -ccc-install-dir %S/Inputs/basic_linux_libcxx_tree/usr/bin \ // RUN: --sysroot=%S/Inputs/basic_linux_libcxx_tree \ // RUN: | FileCheck --check-prefix=CHECK-BASIC-LIBCXX-C-LINK %s -// CHECK-BASIC-LIBCXX-C-LINK-NOT: warning: // CHECK-BASIC-LIBCXX-C-LINK: "-cc1" // CHECK-BASIC-LIBCXX-C-LINK: "-isysroot" "[[SYSROOT:[^"]+]]" // CHECK-BASIC-LIBCXX-C-LINK-NOT: "-internal-isystem" "[[SYSROOT]]/usr/bin/../include/c++/v1" @@ -1661,11 +1650,10 @@ // CHECK-MUSL-AARCH64_BE: "-dynamic-linker" "/lib/ld-musl-aarch64_be.so.1" // Check whether multilib gcc install works fine on Gentoo with gcc-config -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux-gnu -rtlib=platform --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/gentoo_linux_gcc_multi_version_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-GENTOO %s -// CHECK-LD-GENTOO-NOT: warning: // CHECK-LD-GENTOO: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-GENTOO: "--eh-frame-hdr" // CHECK-LD-GENTOO: "-m" "elf_x86_64" @@ -1676,11 +1664,10 @@ // CHECK-LD-GENTOO: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" // CHECK-LD-GENTOO: "-lc" // CHECK-LD-GENTOO: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=i686-unknown-linux-gnu -rtlib=platform --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/gentoo_linux_gcc_multi_version_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-GENTOO-32 %s -// CHECK-LD-GENTOO-32-NOT: warning: // CHECK-LD-GENTOO-32: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-GENTOO-32: "--eh-frame-hdr" // CHECK-LD-GENTOO-32: "-m" "elf_i386" @@ -1691,11 +1678,10 @@ // CHECK-LD-GENTOO-32: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" // CHECK-LD-GENTOO-32: "-lc" // CHECK-LD-GENTOO-32: "-lgcc" "--as-needed" "-lgcc_s" "--no-as-needed" -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-unknown-linux-gnux32 -rtlib=platform --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/gentoo_linux_gcc_multi_version_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-GENTOO-X32 %s -// CHECK-LD-GENTOO-X32-NOT: warning: // CHECK-LD-GENTOO-X32: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-GENTOO-X32: "--eh-frame-hdr" // CHECK-LD-GENTOO-X32: "-m" "elf32_x86_64" @@ -1717,11 +1703,10 @@ // CHECK-LD-RHEL7-DTS: [[SYSROOT]]/usr/lib/gcc/x86_64-redhat-linux/7/../../../../bin/ld // Check whether gcc7 install works fine on Amazon Linux AMI -// RUN: %clang -### %s -no-pie 2>&1 \ +// RUN: %clang -### %s -Werror -no-pie 2>&1 \ // RUN: --target=x86_64-amazon-linux -rtlib=libgcc --unwindlib=platform \ // RUN: --sysroot=%S/Inputs/ami_linux_tree \ // RUN: | FileCheck --check-prefix=CHECK-LD-AMI %s -// CHECK-LD-AMI-NOT: warning: // CHECK-LD-AMI: "{{.*}}ld{{(.exe)?}}" "--sysroot=[[SYSROOT:[^"]+]]" // CHECK-LD-AMI: "--eh-frame-hdr" // CHECK-LD-AMI: "-m" "elf_x86_64" -- GitLab From 1b7db405b97cc350e2de243683273e9946fc0bd0 Mon Sep 17 00:00:00 2001 From: Michael Liao Date: Fri, 26 Apr 2024 15:05:42 -0400 Subject: [PATCH 091/301] [HLSL][SPIR-V] Target `directx` is required - One of tests needs target directx --- clang/test/Driver/hlsl-lang-targets-spirv.hlsl | 1 + 1 file changed, 1 insertion(+) diff --git a/clang/test/Driver/hlsl-lang-targets-spirv.hlsl b/clang/test/Driver/hlsl-lang-targets-spirv.hlsl index b86c2e01f8d8..61b10e1648c5 100644 --- a/clang/test/Driver/hlsl-lang-targets-spirv.hlsl +++ b/clang/test/Driver/hlsl-lang-targets-spirv.hlsl @@ -1,4 +1,5 @@ // REQUIRES: spirv-registered-target +// REQUIRES: directx-registered-target // Supported targets // -- GitLab From 7aedd7dc754c74a49fe84ed2640e269c25414087 Mon Sep 17 00:00:00 2001 From: dyung Date: Fri, 26 Apr 2024 12:09:13 -0700 Subject: [PATCH 092/301] Revert "[mlir] Mark `isa/dyn_cast/cast/...` member functions deprecated. (#89998)" (#90250) This reverts commit 950b7ce0b88318f9099e9a7c9817d224ebdc6337. This change is causing build failures on a bot https://lab.llvm.org/buildbot/#/builders/216/builds/38157 --- flang/include/flang/Lower/Mangler.h | 2 +- .../flang/Optimizer/Analysis/TBAAForest.h | 2 +- .../flang/Optimizer/Builder/BoxValue.h | 20 +- .../include/flang/Optimizer/Builder/Factory.h | 12 +- .../flang/Optimizer/Builder/HLFIRTools.h | 14 +- .../flang/Optimizer/Builder/IntrinsicCall.h | 4 +- .../Optimizer/Builder/PPCIntrinsicCall.h | 6 +- .../Dialect/CanonicalizationPatterns.td | 23 +- .../include/flang/Optimizer/Dialect/FIROps.td | 12 +- .../include/flang/Optimizer/Dialect/FIRType.h | 74 +++-- .../flang/Optimizer/Dialect/FIRTypes.td | 2 +- .../Dialect/FortranVariableInterface.td | 10 +- .../flang/Optimizer/HLFIR/HLFIRDialect.h | 20 +- flang/include/flang/Optimizer/Support/Utils.h | 4 +- flang/include/flang/Tools/PointerModels.h | 4 +- flang/lib/Lower/Allocatable.cpp | 12 +- flang/lib/Lower/Bridge.cpp | 39 ++- flang/lib/Lower/CallInterface.cpp | 6 +- flang/lib/Lower/ConvertArrayConstructor.cpp | 11 +- flang/lib/Lower/ConvertCall.cpp | 56 ++-- flang/lib/Lower/ConvertConstant.cpp | 23 +- flang/lib/Lower/ConvertExpr.cpp | 188 ++++++----- flang/lib/Lower/ConvertExprToHLFIR.cpp | 28 +- .../lib/Lower/ConvertProcedureDesignator.cpp | 6 +- flang/lib/Lower/ConvertVariable.cpp | 22 +- flang/lib/Lower/CustomIntrinsicCall.cpp | 35 +- flang/lib/Lower/DirectivesCommon.h | 24 +- flang/lib/Lower/HlfirIntrinsics.cpp | 4 +- flang/lib/Lower/HostAssociations.cpp | 14 +- flang/lib/Lower/IO.cpp | 55 ++-- flang/lib/Lower/OpenACC.cpp | 4 +- flang/lib/Lower/OpenMP/ClauseProcessor.cpp | 8 +- flang/lib/Lower/OpenMP/OpenMP.cpp | 12 +- flang/lib/Lower/OpenMP/ReductionProcessor.cpp | 18 +- flang/lib/Lower/VectorSubscripts.cpp | 2 +- .../lib/Optimizer/Analysis/AliasAnalysis.cpp | 4 +- flang/lib/Optimizer/Builder/BoxValue.cpp | 4 +- flang/lib/Optimizer/Builder/Character.cpp | 41 ++- flang/lib/Optimizer/Builder/Complex.cpp | 3 +- flang/lib/Optimizer/Builder/FIRBuilder.cpp | 107 +++---- flang/lib/Optimizer/Builder/HLFIRTools.cpp | 78 ++--- flang/lib/Optimizer/Builder/IntrinsicCall.cpp | 107 +++---- flang/lib/Optimizer/Builder/MutableBox.cpp | 35 +- .../Optimizer/Builder/PPCIntrinsicCall.cpp | 44 +-- .../Optimizer/Builder/Runtime/Allocatable.cpp | 2 +- .../Optimizer/Builder/Runtime/Character.cpp | 8 +- .../Optimizer/Builder/Runtime/Intrinsics.cpp | 6 +- .../lib/Optimizer/Builder/Runtime/Ragged.cpp | 3 +- .../Optimizer/Builder/Runtime/Reduction.cpp | 20 +- .../lib/Optimizer/CodeGen/BoxedProcedure.cpp | 16 +- flang/lib/Optimizer/CodeGen/CGOps.cpp | 14 +- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 203 ++++++------ flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp | 18 +- flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp | 13 +- flang/lib/Optimizer/CodeGen/TBAABuilder.cpp | 2 +- flang/lib/Optimizer/CodeGen/Target.cpp | 4 +- flang/lib/Optimizer/CodeGen/TargetRewrite.cpp | 21 +- flang/lib/Optimizer/CodeGen/TypeConverter.cpp | 18 +- flang/lib/Optimizer/Dialect/FIRAttr.cpp | 14 +- flang/lib/Optimizer/Dialect/FIROps.cpp | 302 +++++++++--------- flang/lib/Optimizer/Dialect/FIRType.cpp | 121 ++++--- .../Dialect/FortranVariableInterface.cpp | 11 +- flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp | 30 +- flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp | 192 +++++------ .../HLFIR/Transforms/BufferizeHLFIR.cpp | 29 +- .../HLFIR/Transforms/ConvertToFIR.cpp | 47 ++- .../HLFIR/Transforms/LowerHLFIRIntrinsics.cpp | 2 +- .../LowerHLFIROrderedAssignments.cpp | 2 +- .../Transforms/OptimizedBufferization.cpp | 12 +- .../Transforms/SimplifyHLFIRIntrinsics.cpp | 3 +- .../Optimizer/Transforms/AbstractResult.cpp | 16 +- .../lib/Optimizer/Transforms/AddDebugInfo.cpp | 6 +- .../Optimizer/Transforms/AffineDemotion.cpp | 9 +- .../Optimizer/Transforms/AffinePromotion.cpp | 11 +- .../Optimizer/Transforms/ArrayValueCopy.cpp | 30 +- .../Transforms/CharacterConversion.cpp | 4 +- .../Optimizer/Transforms/LoopVersioning.cpp | 2 +- .../Optimizer/Transforms/MemoryAllocation.cpp | 2 +- .../Transforms/PolymorphicOpConversion.cpp | 38 +-- .../Transforms/SimplifyIntrinsics.cpp | 52 ++- .../lib/Optimizer/Transforms/StackArrays.cpp | 2 +- .../Optimizer/Builder/ComplexTest.cpp | 2 +- .../Optimizer/Builder/DoLoopHelperTest.cpp | 2 +- .../Optimizer/Builder/FIRBuilderTest.cpp | 48 ++- flang/unittests/Optimizer/RTBuilder.cpp | 2 +- llvm/include/llvm/ADT/TypeSwitch.h | 3 - .../mlir/Dialect/Linalg/IR/LinalgOps.td | 4 +- .../Dialect/OpenMP/OpenMPOpsInterfaces.td | 8 +- .../include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 10 +- mlir/include/mlir/IR/Attributes.h | 5 - .../mlir/IR/BuiltinLocationAttributes.td | 13 +- mlir/include/mlir/IR/Location.h | 3 - mlir/include/mlir/IR/Types.h | 5 - mlir/include/mlir/IR/Value.h | 8 +- .../ComplexToStandard/ComplexToStandard.cpp | 2 +- .../Polynomial/IR/PolynomialAttributes.cpp | 2 +- .../Vector/Transforms/VectorLinearize.cpp | 16 +- 97 files changed, 1275 insertions(+), 1342 deletions(-) diff --git a/flang/include/flang/Lower/Mangler.h b/flang/include/flang/Lower/Mangler.h index 99da96b0d6ba..41939abe29e5 100644 --- a/flang/include/flang/Lower/Mangler.h +++ b/flang/include/flang/Lower/Mangler.h @@ -90,7 +90,7 @@ inline std::string mangleArrayLiteral( return mangleArrayLiteral(x.values().size() * sizeof(x.values()[0]), x.shape(), Fortran::common::TypeCategory::Derived, /*kind=*/0, /*charLen=*/-1, - mlir::cast(eleTy).getName()); + eleTy.cast().getName()); } /// Return the compiler-generated name of a static namelist variable descriptor. diff --git a/flang/include/flang/Optimizer/Analysis/TBAAForest.h b/flang/include/flang/Optimizer/Analysis/TBAAForest.h index 619ed4939c51..b69e50bbe05c 100644 --- a/flang/include/flang/Optimizer/Analysis/TBAAForest.h +++ b/flang/include/flang/Optimizer/Analysis/TBAAForest.h @@ -88,7 +88,7 @@ public: // name must be used so that we add to the tbaa tree added in the FIR pass mlir::Attribute attr = func->getAttr(getInternalFuncNameAttrName()); if (attr) { - return getFuncTree(mlir::cast(attr)); + return getFuncTree(attr.cast()); } return getFuncTree(func.getSymNameAttr()); } diff --git a/flang/include/flang/Optimizer/Builder/BoxValue.h b/flang/include/flang/Optimizer/Builder/BoxValue.h index 5c7e89dbc08f..2fed2d48a7a0 100644 --- a/flang/include/flang/Optimizer/Builder/BoxValue.h +++ b/flang/include/flang/Optimizer/Builder/BoxValue.h @@ -78,7 +78,7 @@ class CharBoxValue : public AbstractBox { public: CharBoxValue(mlir::Value addr, mlir::Value len) : AbstractBox{addr}, len{len} { - if (addr && mlir::isa(addr.getType())) + if (addr && addr.getType().template isa()) fir::emitFatalError(addr.getLoc(), "BoxChar should not be in CharBoxValue"); } @@ -221,7 +221,7 @@ public: auto type = getAddr().getType(); if (auto pointedTy = fir::dyn_cast_ptrEleTy(type)) type = pointedTy; - return mlir::cast(type); + return type.cast(); } /// Return the part of the address type after memory and box types. That is /// the element type, maybe wrapped in a fir.array type. @@ -243,22 +243,22 @@ public: /// Get the scalar type related to the described entity mlir::Type getEleTy() const { auto type = getBaseTy(); - if (auto seqTy = mlir::dyn_cast(type)) + if (auto seqTy = type.dyn_cast()) return seqTy.getEleTy(); return type; } /// Is the entity an array or an assumed rank ? - bool hasRank() const { return mlir::isa(getBaseTy()); } + bool hasRank() const { return getBaseTy().isa(); } /// Is this an assumed rank ? bool hasAssumedRank() const { - auto seqTy = mlir::dyn_cast(getBaseTy()); + auto seqTy = getBaseTy().dyn_cast(); return seqTy && seqTy.hasUnknownShape(); } /// Returns the rank of the entity. Beware that zero will be returned for /// both scalars and assumed rank. unsigned rank() const { - if (auto seqTy = mlir::dyn_cast(getBaseTy())) + if (auto seqTy = getBaseTy().dyn_cast()) return seqTy.getDimension(); return 0; } @@ -267,7 +267,7 @@ public: bool isCharacter() const { return fir::isa_char(getEleTy()); } /// Is this a derived type entity ? - bool isDerived() const { return mlir::isa(getEleTy()); } + bool isDerived() const { return getEleTy().isa(); } bool isDerivedWithLenParameters() const { return fir::isRecordWithTypeParameters(getEleTy()); @@ -377,11 +377,11 @@ public: } /// Is this a Fortran pointer ? bool isPointer() const { - return mlir::isa(getBoxTy().getEleTy()); + return getBoxTy().getEleTy().isa(); } /// Is this an allocatable ? bool isAllocatable() const { - return mlir::isa(getBoxTy().getEleTy()); + return getBoxTy().getEleTy().isa(); } // Replace the fir.ref, keeping any non-deferred parameters. MutableBoxValue clone(mlir::Value newBox) const { @@ -488,7 +488,7 @@ public: if (const auto *b = getUnboxed()) { if (*b) { auto type = b->getType(); - if (mlir::isa(type)) + if (type.template isa()) fir::emitFatalError(b->getLoc(), "BoxChar should be unboxed"); type = fir::unwrapSequenceType(fir::unwrapRefType(type)); if (fir::isa_char(type)) diff --git a/flang/include/flang/Optimizer/Builder/Factory.h b/flang/include/flang/Optimizer/Builder/Factory.h index 4e5c52ac44e0..ec294d26ac96 100644 --- a/flang/include/flang/Optimizer/Builder/Factory.h +++ b/flang/include/flang/Optimizer/Builder/Factory.h @@ -43,9 +43,9 @@ template void genCharacterCopy(mlir::Value src, mlir::Value srcLen, mlir::Value dst, mlir::Value dstLen, B &builder, mlir::Location loc) { auto srcTy = - mlir::cast(fir::dyn_cast_ptrEleTy(src.getType())); + fir::dyn_cast_ptrEleTy(src.getType()).template cast(); auto dstTy = - mlir::cast(fir::dyn_cast_ptrEleTy(dst.getType())); + fir::dyn_cast_ptrEleTy(dst.getType()).template cast(); if (!srcLen && !dstLen && srcTy.getFKind() == dstTy.getFKind() && srcTy.getLen() == dstTy.getLen()) { // same size, so just use load and store @@ -61,8 +61,8 @@ void genCharacterCopy(mlir::Value src, mlir::Value srcLen, mlir::Value dst, fir::CharacterType::getSingleton(ty.getContext(), ty.getFKind()))); }; auto toEleTy = [&](fir::ReferenceType ty) { - auto seqTy = mlir::cast(ty.getEleTy()); - return mlir::cast(seqTy.getEleTy()); + auto seqTy = ty.getEleTy().cast(); + return seqTy.getEleTy().cast(); }; auto toCoorTy = [&](fir::ReferenceType ty) { return fir::ReferenceType::get(toEleTy(ty)); @@ -190,8 +190,8 @@ originateIndices(mlir::Location loc, B &builder, mlir::Type memTy, if (origins.empty()) { assert(!shapeVal || mlir::isa(shapeVal.getDefiningOp())); auto ty = fir::dyn_cast_ptrOrBoxEleTy(memTy); - assert(ty && mlir::isa(ty)); - auto seqTy = mlir::cast(ty); + assert(ty && ty.isa()); + auto seqTy = ty.cast(); auto one = builder.template create(loc, 1); const auto dimension = seqTy.getDimension(); if (shapeVal) { diff --git a/flang/include/flang/Optimizer/Builder/HLFIRTools.h b/flang/include/flang/Optimizer/Builder/HLFIRTools.h index 6c36f7e84db6..035035601e2f 100644 --- a/flang/include/flang/Optimizer/Builder/HLFIRTools.h +++ b/flang/include/flang/Optimizer/Builder/HLFIRTools.h @@ -77,12 +77,12 @@ public: /// Return the rank of this entity or -1 if it is an assumed rank. int getRank() const { mlir::Type type = fir::unwrapPassByRefType(fir::unwrapRefType(getType())); - if (auto seqTy = mlir::dyn_cast(type)) { + if (auto seqTy = type.dyn_cast()) { if (seqTy.hasUnknownShape()) return -1; return seqTy.getDimension(); } - if (auto exprType = mlir::dyn_cast(type)) + if (auto exprType = type.dyn_cast()) return exprType.getRank(); return 0; } @@ -99,17 +99,17 @@ public: bool hasLengthParameters() const { mlir::Type eleTy = getFortranElementType(); - return mlir::isa(eleTy) || + return eleTy.isa() || fir::isRecordWithTypeParameters(eleTy); } bool isCharacter() const { - return mlir::isa(getFortranElementType()); + return getFortranElementType().isa(); } bool hasIntrinsicType() const { mlir::Type eleTy = getFortranElementType(); - return fir::isa_trivial(eleTy) || mlir::isa(eleTy); + return fir::isa_trivial(eleTy) || eleTy.isa(); } bool isDerivedWithLengthParameters() const { @@ -124,8 +124,8 @@ public: if (auto varIface = getIfVariableInterface()) { if (auto shape = varIface.getShape()) { auto shapeTy = shape.getType(); - return mlir::isa(shapeTy) || - mlir::isa(shapeTy); + return shapeTy.isa() || + shapeTy.isa(); } return false; } diff --git a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h index b7d060926761..604f2bd969ee 100644 --- a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h @@ -663,8 +663,8 @@ static inline mlir::FunctionType genFuncType(mlir::MLIRContext *context, //===----------------------------------------------------------------------===// static inline mlir::Type getConvertedElementType(mlir::MLIRContext *context, mlir::Type eleTy) { - if (mlir::isa(eleTy) && !eleTy.isSignlessInteger()) { - const auto intTy{mlir::dyn_cast(eleTy)}; + if (eleTy.isa() && !eleTy.isSignlessInteger()) { + const auto intTy{eleTy.dyn_cast()}; auto newEleTy{mlir::IntegerType::get(context, intTy.getWidth())}; return newEleTy; } diff --git a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h index a7c4c075d818..1e87bf0f6ad1 100644 --- a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h @@ -180,10 +180,10 @@ struct VecTypeInfo { // Returns a VecTypeInfo with element type and length of given fir vector type. // Preserves signness of fir vector type if element type of integer. static inline VecTypeInfo getVecTypeFromFirType(mlir::Type firTy) { - assert(mlir::isa(firTy)); + assert(firTy.isa()); VecTypeInfo vecTyInfo; - vecTyInfo.eleTy = mlir::dyn_cast(firTy).getEleTy(); - vecTyInfo.len = mlir::dyn_cast(firTy).getLen(); + vecTyInfo.eleTy = firTy.dyn_cast().getEleTy(); + vecTyInfo.len = firTy.dyn_cast().getLen(); return vecTyInfo; } diff --git a/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td b/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td index 0ef37a37ce94..544fc3cdf75e 100644 --- a/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td +++ b/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td @@ -21,18 +21,17 @@ include "flang/Optimizer/Dialect/FIROps.td" def IdenticalTypePred : Constraint>; def IntegerTypePred : Constraint>; -def IndexTypePred : Constraint($0.getType())">>; +def IndexTypePred : Constraint()">>; // Widths are monotonic. // $0.bits >= $1.bits >= $2.bits or $0.bits <= $1.bits <= $2.bits def MonotonicTypePred - : Constraint($0.getType()) && " - " mlir::isa($1.getType()) && " - " mlir::isa($2.getType())) || " - " (mlir::isa($0.getType()) && " - " mlir::isa($1.getType()) && " - " mlir::isa($2.getType()))) && " + : Constraint() && " + " $1.getType().isa() && " + " $2.getType().isa()) || " + " ($0.getType().isa() && " + " $1.getType().isa() && " + " $2.getType().isa())) && " "(($0.getType().getIntOrFloatBitWidth() <= " " $1.getType().getIntOrFloatBitWidth() && " " $1.getType().getIntOrFloatBitWidth() <= " @@ -43,8 +42,8 @@ def MonotonicTypePred " $2.getType().getIntOrFloatBitWidth()))">>; def IntPred : Constraint($0.getType()) && " - "mlir::isa($1.getType())">>; + "$0.getType().isa() && " + "$1.getType().isa()">>; // If both are int type and the first is smaller than the second. // $0.bits <= $1.bits @@ -102,8 +101,8 @@ def CombineConvertTruncOptPattern def createConstantOp : NativeCodeCall<"$_builder.create" "($_loc, $_builder.getIndexType(), " - "rewriter.getIndexAttr(" - "mlir::dyn_cast($1).getInt()))">; + "rewriter.getIndexAttr($1.dyn_cast()" + ".getInt()))">; def ForwardConstantConvertPattern : Pat<(fir_ConvertOp:$res (Arith_ConstantOp:$cnt $attr)), diff --git a/flang/include/flang/Optimizer/Dialect/FIROps.td b/flang/include/flang/Optimizer/Dialect/FIROps.td index 496193e25cab..92790a691e47 100644 --- a/flang/include/flang/Optimizer/Dialect/FIROps.td +++ b/flang/include/flang/Optimizer/Dialect/FIROps.td @@ -2708,14 +2708,14 @@ def fir_ConvertOp : fir_OneResultOp<"convert", [NoMemoryEffect]> { let hasCanonicalizer = 1; } -def FortranTypeAttr : Attr($_self)">, - Or<[CPred<"mlir::isa(mlir::cast($_self).getValue())" - >]>]>, "Fortran surface type"> { +def FortranTypeAttr : Attr()">, + Or<[CPred<"$_self.cast().getValue().isa()">]>]>, + "Fortran surface type"> { let storageType = [{ ::mlir::TypeAttr }]; let returnType = "mlir::Type"; - let convertFromStorage = "mlir::cast($_self.getValue())"; + let convertFromStorage = "$_self.getValue().cast()"; } def fir_TypeDescOp : fir_OneResultOp<"type_desc", [NoMemoryEffect]> { diff --git a/flang/include/flang/Optimizer/Dialect/FIRType.h b/flang/include/flang/Optimizer/Dialect/FIRType.h index b4344435db9f..7fcd9c1babf2 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRType.h +++ b/flang/include/flang/Optimizer/Dialect/FIRType.h @@ -97,36 +97,35 @@ bool isa_fir_or_std_type(mlir::Type t); /// Is `t` a FIR dialect type that implies a memory (de)reference? inline bool isa_ref_type(mlir::Type t) { - return mlir::isa(t); + return t.isa(); } /// Is `t` a boxed type? inline bool isa_box_type(mlir::Type t) { - return mlir::isa(t); + return t.isa(); } /// Is `t` a type that is always trivially pass-by-reference? Specifically, this /// is testing if `t` is a ReferenceType or any box type. Compare this to /// conformsWithPassByRef(), which includes pointers and allocatables. inline bool isa_passbyref_type(mlir::Type t) { - return mlir::isa(t) || - isa_box_type(t); + return t.isa() || isa_box_type(t); } /// Is `t` a type that can conform to be pass-by-reference? Depending on the /// context, these types may simply demote to pass-by-reference or a reference /// to them may have to be passed instead. Functions are always referent. inline bool conformsWithPassByRef(mlir::Type t) { - return isa_ref_type(t) || isa_box_type(t) || mlir::isa(t); + return isa_ref_type(t) || isa_box_type(t) || t.isa(); } /// Is `t` a derived (record) type? -inline bool isa_derived(mlir::Type t) { return mlir::isa(t); } +inline bool isa_derived(mlir::Type t) { return t.isa(); } /// Is `t` type(c_ptr) or type(c_funptr)? inline bool isa_builtin_cptr_type(mlir::Type t) { - if (auto recTy = mlir::dyn_cast_or_null(t)) + if (auto recTy = t.dyn_cast_or_null()) return recTy.getName().ends_with("T__builtin_c_ptr") || recTy.getName().ends_with("T__builtin_c_funptr"); return false; @@ -134,7 +133,7 @@ inline bool isa_builtin_cptr_type(mlir::Type t) { /// Is `t` a FIR dialect aggregate type? inline bool isa_aggregate(mlir::Type t) { - return mlir::isa(t) || fir::isa_derived(t); + return t.isa() || fir::isa_derived(t); } /// Extract the `Type` pointed to from a FIR memory reference type. If `t` is @@ -147,17 +146,17 @@ mlir::Type dyn_cast_ptrOrBoxEleTy(mlir::Type t); /// Is `t` a FIR Real or MLIR Float type? inline bool isa_real(mlir::Type t) { - return mlir::isa(t); + return t.isa(); } /// Is `t` an integral type? inline bool isa_integer(mlir::Type t) { - return mlir::isa(t); + return t.isa(); } /// Is `t` a vector type? inline bool isa_vector(mlir::Type t) { - return mlir::isa(t); + return t.isa(); } mlir::Type parseFirType(FIROpsDialect *, mlir::DialectAsmParser &parser); @@ -170,22 +169,22 @@ void verifyIntegralType(mlir::Type type); /// Is `t` a FIR or MLIR Complex type? inline bool isa_complex(mlir::Type t) { - return mlir::isa(t); + return t.isa(); } /// Is `t` a CHARACTER type? Does not check the length. -inline bool isa_char(mlir::Type t) { return mlir::isa(t); } +inline bool isa_char(mlir::Type t) { return t.isa(); } /// Is `t` a trivial intrinsic type? CHARACTER is excluded because it /// is a dependent type. inline bool isa_trivial(mlir::Type t) { return isa_integer(t) || isa_real(t) || isa_complex(t) || isa_vector(t) || - mlir::isa(t); + t.isa(); } /// Is `t` a CHARACTER type with a LEN other than 1? inline bool isa_char_string(mlir::Type t) { - if (auto ct = mlir::dyn_cast_or_null(t)) + if (auto ct = t.dyn_cast_or_null()) return ct.getLen() != fir::CharacterType::singleton(); return false; } @@ -199,7 +198,7 @@ bool isa_unknown_size_box(mlir::Type t); /// Returns true iff `t` is a fir.char type and has an unknown length. inline bool characterWithDynamicLen(mlir::Type t) { - if (auto charTy = mlir::dyn_cast(t)) + if (auto charTy = t.dyn_cast()) return charTy.hasDynamicLen(); return false; } @@ -214,11 +213,11 @@ inline bool sequenceWithNonConstantShape(fir::SequenceType seqTy) { bool hasDynamicSize(mlir::Type t); inline unsigned getRankOfShapeType(mlir::Type t) { - if (auto shTy = mlir::dyn_cast(t)) + if (auto shTy = t.dyn_cast()) return shTy.getRank(); - if (auto shTy = mlir::dyn_cast(t)) + if (auto shTy = t.dyn_cast()) return shTy.getRank(); - if (auto shTy = mlir::dyn_cast(t)) + if (auto shTy = t.dyn_cast()) return shTy.getRank(); return 0; } @@ -226,14 +225,14 @@ inline unsigned getRankOfShapeType(mlir::Type t) { /// Get the memory reference type of the data pointer from the box type, inline mlir::Type boxMemRefType(fir::BaseBoxType t) { auto eleTy = t.getEleTy(); - if (!mlir::isa(eleTy)) + if (!eleTy.isa()) eleTy = fir::ReferenceType::get(t); return eleTy; } /// If `t` is a SequenceType return its element type, otherwise return `t`. inline mlir::Type unwrapSequenceType(mlir::Type t) { - if (auto seqTy = mlir::dyn_cast(t)) + if (auto seqTy = t.dyn_cast()) return seqTy.getEleTy(); return t; } @@ -279,7 +278,7 @@ inline fir::SequenceType unwrapUntilSeqType(mlir::Type t) { t = ty; continue; } - if (auto seqTy = mlir::dyn_cast(t)) + if (auto seqTy = t.dyn_cast()) return seqTy; return {}; } @@ -288,8 +287,8 @@ inline fir::SequenceType unwrapUntilSeqType(mlir::Type t) { /// Unwrap the referential and sequential outer types (if any). Returns the /// the element if type is fir::RecordType inline fir::RecordType unwrapIfDerived(fir::BaseBoxType boxTy) { - return mlir::dyn_cast( - fir::unwrapSequenceType(fir::unwrapRefType(boxTy.getEleTy()))); + return fir::unwrapSequenceType(fir::unwrapRefType(boxTy.getEleTy())) + .template dyn_cast(); } /// Return true iff `boxTy` wraps a fir::RecordType with length parameters @@ -378,7 +377,7 @@ bool isRecordWithDescriptorMember(mlir::Type ty); /// Return true iff `ty` is a RecordType with type parameters. inline bool isRecordWithTypeParameters(mlir::Type ty) { - if (auto recTy = mlir::dyn_cast_or_null(ty)) + if (auto recTy = ty.dyn_cast_or_null()) return recTy.isDependentType(); return false; } @@ -402,14 +401,14 @@ mlir::Type fromRealTypeID(mlir::MLIRContext *context, llvm::Type::TypeID typeID, int getTypeCode(mlir::Type ty, const KindMapping &kindMap); inline bool BaseBoxType::classof(mlir::Type type) { - return mlir::isa(type); + return type.isa(); } /// Return true iff `ty` is none or fir.array. inline bool isNoneOrSeqNone(mlir::Type type) { - if (auto seqTy = mlir::dyn_cast(type)) - return mlir::isa(seqTy.getEleTy()); - return mlir::isa(type); + if (auto seqTy = type.dyn_cast()) + return seqTy.getEleTy().isa(); + return type.isa(); } /// Return a fir.box or fir.class if the type is polymorphic. If the type @@ -429,16 +428,16 @@ inline mlir::Type wrapInClassOrBoxType(mlir::Type eleTy, /// !fir.array<2xf32> -> !fir.array<2xnone> /// !fir.heap> -> !fir.heap> inline mlir::Type updateTypeForUnlimitedPolymorphic(mlir::Type ty) { - if (auto seqTy = mlir::dyn_cast(ty)) + if (auto seqTy = ty.dyn_cast()) return fir::SequenceType::get( seqTy.getShape(), updateTypeForUnlimitedPolymorphic(seqTy.getEleTy())); - if (auto heapTy = mlir::dyn_cast(ty)) + if (auto heapTy = ty.dyn_cast()) return fir::HeapType::get( updateTypeForUnlimitedPolymorphic(heapTy.getEleTy())); - if (auto pointerTy = mlir::dyn_cast(ty)) + if (auto pointerTy = ty.dyn_cast()) return fir::PointerType::get( updateTypeForUnlimitedPolymorphic(pointerTy.getEleTy())); - if (!mlir::isa(ty)) + if (!ty.isa()) return mlir::NoneType::get(ty.getContext()); return ty; } @@ -452,19 +451,18 @@ mlir::Type changeElementType(mlir::Type type, mlir::Type newElementType, /// Is `t` an address to fir.box or class type? inline bool isBoxAddress(mlir::Type t) { - return fir::isa_ref_type(t) && - mlir::isa(fir::unwrapRefType(t)); + return fir::isa_ref_type(t) && fir::unwrapRefType(t).isa(); } /// Is `t` a fir.box or class address or value type? inline bool isBoxAddressOrValue(mlir::Type t) { - return mlir::isa(fir::unwrapRefType(t)); + return fir::unwrapRefType(t).isa(); } /// Is this a fir.boxproc address type? inline bool isBoxProcAddressType(mlir::Type t) { t = fir::dyn_cast_ptrEleTy(t); - return t && mlir::isa(t); + return t && t.isa(); } /// Return a string representation of `ty`. diff --git a/flang/include/flang/Optimizer/Dialect/FIRTypes.td b/flang/include/flang/Optimizer/Dialect/FIRTypes.td index 7378ed93944c..3b876e4642da 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRTypes.td +++ b/flang/include/flang/Optimizer/Dialect/FIRTypes.td @@ -578,7 +578,7 @@ def fir_VoidType : FIR_Type<"Void", "void"> { // Whether a type is a BaseBoxType def IsBaseBoxTypePred - : CPred<"mlir::isa<::fir::BaseBoxType>($_self)">; + : CPred<"$_self.isa<::fir::BaseBoxType>()">; def fir_BaseBoxType : Type; // Generalized FIR and standard dialect types representing intrinsic types diff --git a/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td b/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td index 3f78a93a2515..6405afbf1bfb 100644 --- a/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td +++ b/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td @@ -75,7 +75,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// variable. mlir::Type getElementOrSequenceType() { mlir::Type type = fir::unwrapPassByRefType(fir::unwrapRefType(getBase().getType())); - if (auto boxCharType = mlir::dyn_cast(type)) + if (auto boxCharType = type.dyn_cast()) return boxCharType.getEleTy(); return type; } @@ -87,13 +87,13 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is the variable an array? bool isArray() { - return mlir::isa(getElementOrSequenceType()); + return getElementOrSequenceType().isa(); } /// Return the rank of the entity if it is known at compile time. std::optional getRank() { if (auto sequenceType = - mlir::dyn_cast(getElementOrSequenceType())) { + getElementOrSequenceType().dyn_cast()) { if (sequenceType.hasUnknownShape()) return {}; return sequenceType.getDimension(); @@ -133,7 +133,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is this a Fortran character variable? bool isCharacter() { - return mlir::isa(getElementType()); + return getElementType().isa(); } /// Is this a Fortran character variable with an explicit length? @@ -149,7 +149,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is this variable represented as a fir.box or fir.class value? bool isBoxValue() { - return mlir::isa(getBase().getType()); + return getBase().getType().isa(); } /// Is this variable represented as a fir.box or fir.class address? diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h index 3830237f96f3..aa68d0811c48 100644 --- a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h +++ b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h @@ -40,9 +40,9 @@ namespace hlfir { inline mlir::Type getFortranElementType(mlir::Type type) { type = fir::unwrapSequenceType( fir::unwrapPassByRefType(fir::unwrapRefType(type))); - if (auto exprType = mlir::dyn_cast(type)) + if (auto exprType = type.dyn_cast()) return exprType.getEleTy(); - if (auto boxCharType = mlir::dyn_cast(type)) + if (auto boxCharType = type.dyn_cast()) return boxCharType.getEleTy(); return type; } @@ -51,12 +51,12 @@ inline mlir::Type getFortranElementType(mlir::Type type) { /// fir.array type. Otherwise, returns the Fortran element typeof the entity. inline mlir::Type getFortranElementOrSequenceType(mlir::Type type) { type = fir::unwrapPassByRefType(fir::unwrapRefType(type)); - if (auto exprType = mlir::dyn_cast(type)) { + if (auto exprType = type.dyn_cast()) { if (exprType.isArray()) return fir::SequenceType::get(exprType.getShape(), exprType.getEleTy()); return exprType.getEleTy(); } - if (auto boxCharType = mlir::dyn_cast(type)) + if (auto boxCharType = type.dyn_cast()) return boxCharType.getEleTy(); return type; } @@ -64,16 +64,16 @@ inline mlir::Type getFortranElementOrSequenceType(mlir::Type type) { /// Is this a fir.box or fir.class address type? inline bool isBoxAddressType(mlir::Type type) { type = fir::dyn_cast_ptrEleTy(type); - return type && mlir::isa(type); + return type && type.isa(); } /// Is this a fir.box or fir.class address or value type? inline bool isBoxAddressOrValueType(mlir::Type type) { - return mlir::isa(fir::unwrapRefType(type)); + return fir::unwrapRefType(type).isa(); } inline bool isPolymorphicType(mlir::Type type) { - if (auto exprType = mlir::dyn_cast(type)) + if (auto exprType = type.dyn_cast()) return exprType.isPolymorphic(); return fir::isPolymorphicType(type); } @@ -81,14 +81,14 @@ inline bool isPolymorphicType(mlir::Type type) { /// Is this an SSA value type for the value of a Fortran procedure /// designator ? inline bool isFortranProcedureValue(mlir::Type type) { - return mlir::isa(type) || - (mlir::isa(type) && + return type.isa() || + (type.isa() && fir::isCharacterProcedureTuple(type, /*acceptRawFunc=*/false)); } /// Is this an SSA value type for the value of a Fortran expression? inline bool isFortranValueType(mlir::Type type) { - return mlir::isa(type) || fir::isa_trivial(type) || + return type.isa() || fir::isa_trivial(type) || isFortranProcedureValue(type); } diff --git a/flang/include/flang/Optimizer/Support/Utils.h b/flang/include/flang/Optimizer/Support/Utils.h index 2da6f24da40e..2b4fa50e0e42 100644 --- a/flang/include/flang/Optimizer/Support/Utils.h +++ b/flang/include/flang/Optimizer/Support/Utils.h @@ -29,9 +29,7 @@ namespace fir { /// Return the integer value of a arith::ConstantOp. inline std::int64_t toInt(mlir::arith::ConstantOp cop) { - return mlir::cast(cop.getValue()) - .getValue() - .getSExtValue(); + return cop.getValue().cast().getValue().getSExtValue(); } // Reconstruct binding tables for dynamic dispatch. diff --git a/flang/include/flang/Tools/PointerModels.h b/flang/include/flang/Tools/PointerModels.h index c3c0977d6e54..7acaf2f9fda5 100644 --- a/flang/include/flang/Tools/PointerModels.h +++ b/flang/include/flang/Tools/PointerModels.h @@ -20,7 +20,7 @@ struct OpenMPPointerLikeModel : public mlir::omp::PointerLikeType::ExternalModel< OpenMPPointerLikeModel, T> { mlir::Type getElementType(mlir::Type pointer) const { - return mlir::cast(pointer).getElementType(); + return pointer.cast().getElementType(); } }; @@ -29,7 +29,7 @@ struct OpenACCPointerLikeModel : public mlir::acc::PointerLikeType::ExternalModel< OpenACCPointerLikeModel, T> { mlir::Type getElementType(mlir::Type pointer) const { - return mlir::cast(pointer).getElementType(); + return pointer.cast().getElementType(); } }; diff --git a/flang/lib/Lower/Allocatable.cpp b/flang/lib/Lower/Allocatable.cpp index a1957c0eb1bb..8e84ea2fc5d5 100644 --- a/flang/lib/Lower/Allocatable.cpp +++ b/flang/lib/Lower/Allocatable.cpp @@ -162,7 +162,7 @@ static void genRuntimeInitCharacter(fir::FirOpBuilder &builder, args.push_back(builder.createConvert(loc, inputTypes[0], box.getAddr())); args.push_back(builder.createConvert(loc, inputTypes[1], len)); if (kind == 0) - kind = mlir::cast(box.getEleTy()).getFKind(); + kind = box.getEleTy().cast().getFKind(); args.push_back(builder.createIntegerConstant(loc, inputTypes[2], kind)); int rank = box.rank(); args.push_back(builder.createIntegerConstant(loc, inputTypes[3], rank)); @@ -879,7 +879,7 @@ void Fortran::lower::genDeallocateIfAllocated( builder.genIfThen(loc, isAllocated) .genThen([&]() { if (mlir::Type eleType = box.getEleTy(); - mlir::isa(eleType) && box.isPolymorphic()) { + eleType.isa() && box.isPolymorphic()) { mlir::Value declaredTypeDesc = builder.create( loc, mlir::TypeAttr::get(eleType)); genDeallocateBox(converter, box, loc, sym, declaredTypeDesc); @@ -918,7 +918,7 @@ void Fortran::lower::genDeallocateStmt( mlir::Value declaredTypeDesc = {}; if (box.isPolymorphic()) { mlir::Type eleType = box.getEleTy(); - if (mlir::isa(eleType)) + if (eleType.isa()) if (const Fortran::semantics::DerivedTypeSpec *derivedTypeSpec = symbol.GetType()->AsDerived()) { declaredTypeDesc = @@ -1007,7 +1007,7 @@ createMutableProperties(Fortran::lower::AbstractConverter &converter, fir::MutableProperties mutableProperties; std::string name = converter.mangleName(sym); mlir::Type baseAddrTy = converter.genType(sym); - if (auto boxType = mlir::dyn_cast(baseAddrTy)) + if (auto boxType = baseAddrTy.dyn_cast()) baseAddrTy = boxType.getEleTy(); // Allocate and set a variable to hold the address. // It will be set to null in setUnallocatedStatus. @@ -1032,9 +1032,9 @@ createMutableProperties(Fortran::lower::AbstractConverter &converter, mlir::Type eleTy = baseAddrTy; if (auto newTy = fir::dyn_cast_ptrEleTy(eleTy)) eleTy = newTy; - if (auto seqTy = mlir::dyn_cast(eleTy)) + if (auto seqTy = eleTy.dyn_cast()) eleTy = seqTy.getEleTy(); - if (auto record = mlir::dyn_cast(eleTy)) + if (auto record = eleTy.dyn_cast()) if (record.getNumLenParams() != 0) TODO(loc, "deferred length type parameters."); if (fir::isa_char(eleTy) && nonDeferredParams.empty()) { diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index 19c00884bd1b..f66607dfa22f 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -683,7 +683,7 @@ public: auto if_builder = builder->genIfThenElse(loc, isAllocated); if_builder.genThen([&]() { std::string name = mangleName(sym) + ".alloc"; - if (auto seqTy = mlir::dyn_cast(symType)) { + if (auto seqTy = symType.dyn_cast()) { fir::ExtendedValue read = fir::factory::genMutableBoxRead( *builder, loc, box, /*mayBePolymorphic=*/false); if (auto read_arr_box = read.getBoxOf()) { @@ -1132,7 +1132,7 @@ private: fir::ExtendedValue lhs = symBoxToExtendedValue(lhs_sb); fir::ExtendedValue rhs = symBoxToExtendedValue(rhs_sb); mlir::Type symType = genType(sym); - if (auto seqTy = mlir::dyn_cast(symType)) { + if (auto seqTy = symType.dyn_cast()) { Fortran::lower::StatementContext stmtCtx; Fortran::lower::createSomeArrayAssignment(*this, lhs, rhs, localSymbols, stmtCtx); @@ -1355,7 +1355,7 @@ private: return; } mlir::Type selectorType = selector.getType(); - bool realSelector = mlir::isa(selectorType); + bool realSelector = selectorType.isa(); assert((inArithmeticIfContext || !realSelector) && "invalid selector type"); mlir::Value zero; if (inArithmeticIfContext) @@ -1630,7 +1630,7 @@ private: stmtCtx); stmtCtx.finalizeAndReset(); // Raise an exception if REAL expr is a NaN. - if (mlir::isa(expr.getType())) + if (expr.getType().isa()) expr = builder->create(toLocation(), expr, expr); // An empty valueList indicates to genMultiwayBranch that the branch is // an ArithmeticIfStmt that has two branches on value 0 or 0.0. @@ -2807,7 +2807,7 @@ private: auto caseValue = valueList.begin(); auto caseBlock = blockList.begin(); for (mlir::Attribute attr : attrList) { - if (mlir::isa(attr)) { + if (attr.isa()) { genBranch(*caseBlock++); break; } @@ -2825,7 +2825,7 @@ private: rhsVal.second); }; mlir::Block *newBlock = insertBlock(*caseBlock); - if (mlir::isa(attr)) { + if (attr.isa()) { mlir::Block *newBlock2 = insertBlock(*caseBlock); mlir::Value cond = genCond(*caseValue++, mlir::arith::CmpIPredicate::sge); @@ -2838,12 +2838,12 @@ private: continue; } mlir::arith::CmpIPredicate pred; - if (mlir::isa(attr)) { + if (attr.isa()) { pred = mlir::arith::CmpIPredicate::eq; - } else if (mlir::isa(attr)) { + } else if (attr.isa()) { pred = mlir::arith::CmpIPredicate::sge; } else { - assert(mlir::isa(attr) && "unexpected predicate"); + assert(attr.isa() && "unexpected predicate"); pred = mlir::arith::CmpIPredicate::sle; } mlir::Value cond = genCond(*caseValue++, pred); @@ -3105,7 +3105,7 @@ private: bool isPointer = fir::isPointerType(baseTy); bool isAllocatable = fir::isAllocatableType(baseTy); bool isArray = - mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(baseTy)); + fir::dyn_cast_ptrOrBoxEleTy(baseTy).isa(); const fir::BoxValue *selectorBox = selector.getBoxOf(); if (std::holds_alternative(guard.u)) { // CLASS DEFAULT @@ -3114,12 +3114,12 @@ private: std::get_if(&guard.u)) { // TYPE IS fir::ExactTypeAttr attr = - mlir::dyn_cast(typeGuardAttr); + typeGuardAttr.dyn_cast(); mlir::Value exactValue; mlir::Type addrTy = attr.getType(); if (isArray) { - auto seqTy = mlir::dyn_cast( - fir::dyn_cast_ptrOrBoxEleTy(baseTy)); + auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(baseTy) + .dyn_cast(); addrTy = fir::SequenceType::get(seqTy.getShape(), attr.getType()); } if (isPointer) @@ -3141,7 +3141,7 @@ private: addAssocEntitySymbol(selectorBox->clone(exact)); } else if (intrinsic->category() == Fortran::common::TypeCategory::Character) { - auto charTy = mlir::dyn_cast(attr.getType()); + auto charTy = attr.getType().dyn_cast(); mlir::Value charLen = fir::factory::CharacterExprHelper(*builder, loc) .readLengthFromBox(fir::getBase(selector), charTy); @@ -3158,12 +3158,11 @@ private: } else if (std::holds_alternative( guard.u)) { // CLASS IS - fir::SubclassAttr attr = - mlir::dyn_cast(typeGuardAttr); + fir::SubclassAttr attr = typeGuardAttr.dyn_cast(); mlir::Type addrTy = attr.getType(); if (isArray) { - auto seqTy = mlir::dyn_cast( - fir::dyn_cast_ptrOrBoxEleTy(baseTy)); + auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(baseTy) + .dyn_cast(); addrTy = fir::SequenceType::get(seqTy.getShape(), attr.getType()); } if (isPointer) @@ -4140,7 +4139,7 @@ private: } else if (isDerivedCategory(lhsType->category())) { // Handle parent component. if (Fortran::lower::isParentComponent(assign.lhs)) { - if (!mlir::isa(fir::getBase(lhs).getType())) + if (!fir::getBase(lhs).getType().isa()) lhs = fir::getBase(builder->createBox(loc, lhs)); lhs = Fortran::lower::updateBoxForParentComponent(*this, lhs, assign.lhs); @@ -5491,7 +5490,7 @@ Fortran::lower::LoweringBridge::LoweringBridge( default: break; } - if (!mlir::isa(diag.getLocation())) + if (!diag.getLocation().isa()) os << diag.getLocation() << ": "; os << diag << '\n'; os.flush(); diff --git a/flang/lib/Lower/CallInterface.cpp b/flang/lib/Lower/CallInterface.cpp index c1f54ad39287..5ad244600328 100644 --- a/flang/lib/Lower/CallInterface.cpp +++ b/flang/lib/Lower/CallInterface.cpp @@ -1182,7 +1182,7 @@ private: Property prop = Property::BaseAddress; if (isValueAttr) { bool isBuiltinCptrType = fir::isa_builtin_cptr_type(type); - if (isBindC || (!mlir::isa(type) && + if (isBindC || (!type.isa() && !obj.attrs.test(Attrs::Optional) && (dynamicType.category() != Fortran::common::TypeCategory::Derived || @@ -1190,7 +1190,7 @@ private: passBy = PassEntityBy::Value; prop = Property::Value; if (isBuiltinCptrType) { - auto recTy = mlir::dyn_cast(type); + auto recTy = type.dyn_cast(); mlir::Type fieldTy = recTy.getTypeList()[0].second; passType = fir::ReferenceType::get(fieldTy); } else { @@ -1714,7 +1714,7 @@ mlir::Type Fortran::lower::getDummyProcedureType( } bool Fortran::lower::isCPtrArgByValueType(mlir::Type ty) { - return mlir::isa(ty) && + return ty.isa() && fir::isa_integer(fir::unwrapRefType(ty)); } diff --git a/flang/lib/Lower/ConvertArrayConstructor.cpp b/flang/lib/Lower/ConvertArrayConstructor.cpp index a5b5838fe6b6..24aa9beba6bf 100644 --- a/flang/lib/Lower/ConvertArrayConstructor.cpp +++ b/flang/lib/Lower/ConvertArrayConstructor.cpp @@ -336,7 +336,7 @@ public: if (!extent) extent = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (missingLengthParameters) { - if (mlir::isa(declaredType.getEleTy())) + if (declaredType.getEleTy().isa()) emboxLengths.push_back(builder.createIntegerConstant( loc, builder.getCharacterLengthType(), 0)); else @@ -357,7 +357,7 @@ public: bool useSimplePushRuntime(hlfir::Entity value) { return value.isScalar() && - !mlir::isa(arrayConstructorElementType) && + !arrayConstructorElementType.isa() && !fir::isRecordWithAllocatableMember(arrayConstructorElementType) && !fir::isRecordWithTypeParameters(arrayConstructorElementType); } @@ -370,7 +370,7 @@ public: auto [addrExv, cleanUp] = hlfir::convertToAddress( loc, builder, value, arrayConstructorElementType); mlir::Value addr = fir::getBase(addrExv); - if (mlir::isa(addr.getType())) + if (addr.getType().isa()) addr = builder.create(loc, addr); fir::runtime::genPushArrayConstructorSimpleScalar( loc, builder, arrayConstructorVector, addr); @@ -564,7 +564,7 @@ struct LengthAndTypeCollector> { /// lowering an ac-value and must be delayed? static bool missingLengthParameters(mlir::Type elementType, llvm::ArrayRef lengths) { - return (mlir::isa(elementType) || + return (elementType.isa() || fir::isRecordWithTypeParameters(elementType)) && lengths.empty(); } @@ -702,8 +702,7 @@ static ArrayCtorLoweringStrategy selectArrayCtorLoweringStrategy( // Based on what was gathered and the result of the analysis, select and // instantiate the right lowering strategy for the array constructor. if (!extent || needToEvaluateOneExprToGetLengthParameters || - analysis.anyArrayExpr || - mlir::isa(declaredType.getEleTy())) + analysis.anyArrayExpr || declaredType.getEleTy().isa()) return RuntimeTempStrategy( loc, builder, stmtCtx, symMap, declaredType, extent ? std::optional(extent) : std::nullopt, lengths, diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp index e4a0cc8d4730..c6f7d3410ad5 100644 --- a/flang/lib/Lower/ConvertCall.cpp +++ b/flang/lib/Lower/ConvertCall.cpp @@ -49,15 +49,15 @@ static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, llvm::ArrayRef extents, llvm::ArrayRef lengths) { mlir::Type type = base.getType(); - if (mlir::isa(type)) + if (type.isa()) return fir::BoxValue(base, /*lbounds=*/{}, lengths, extents); type = fir::unwrapRefType(type); - if (mlir::isa(type)) + if (type.isa()) return fir::MutableBoxValue(base, lengths, /*mutableProperties*/ {}); - if (auto seqTy = mlir::dyn_cast(type)) { + if (auto seqTy = type.dyn_cast()) { if (seqTy.getDimension() != extents.size()) fir::emitFatalError(loc, "incorrect number of extents for array"); - if (mlir::isa(seqTy.getEleTy())) { + if (seqTy.getEleTy().isa()) { if (lengths.empty()) fir::emitFatalError(loc, "missing length for character"); assert(lengths.size() == 1); @@ -65,7 +65,7 @@ static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, } return fir::ArrayBoxValue(base, extents); } - if (mlir::isa(type)) { + if (type.isa()) { if (lengths.empty()) fir::emitFatalError(loc, "missing length for character"); assert(lengths.size() == 1); @@ -193,7 +193,7 @@ static mlir::Value remapActualToDummyDescriptor( llvm::SmallVector lengths; mlir::Type dummyBoxType = caller.getDummyArgumentType(arg); mlir::Type dummyBaseType = fir::unwrapPassByRefType(dummyBoxType); - if (mlir::isa(dummyBaseType)) + if (dummyBaseType.isa()) caller.walkDummyArgumentExtents( arg, [&](const Fortran::lower::SomeExpr &e, bool isAssumedSizeExtent) { extents.emplace_back(lowerSpecExpr(e, isAssumedSizeExtent)); @@ -338,7 +338,7 @@ std::pair Fortran::lower::genCallOpAndResult( if (!caller.callerAllocateResult()) return {}; mlir::Type type = caller.getResultStorageType(); - if (mlir::isa(type)) + if (type.isa()) caller.walkResultExtents( [&](const Fortran::lower::SomeExpr &e, bool isAssumedSizeExtent) { assert(!isAssumedSizeExtent && "result cannot be assumed-size"); @@ -353,7 +353,7 @@ std::pair Fortran::lower::genCallOpAndResult( // Result length parameters should not be provided to box storage // allocation and save_results, but they are still useful information to // keep in the ExtendedValue if non-deferred. - if (!mlir::isa(type)) { + if (!type.isa()) { if (fir::isa_char(fir::unwrapSequenceType(type)) && lengths.empty()) { // Calling an assumed length function. This is only possible if this // is a call to a character dummy procedure. @@ -478,7 +478,7 @@ std::pair Fortran::lower::genCallOpAndResult( // FIR. if (funcPointer) { operands.push_back( - mlir::isa(funcPointer.getType()) + funcPointer.getType().isa() ? builder.create(loc, funcType, funcPointer) : builder.createConvert(loc, funcType, funcPointer)); } @@ -492,8 +492,8 @@ std::pair Fortran::lower::genCallOpAndResult( // arguments of any type and vice versa. mlir::Value cast; auto *context = builder.getContext(); - if (mlir::isa(snd) && - mlir::isa(fst.getType())) { + if (snd.isa() && + fst.getType().isa()) { auto funcTy = mlir::FunctionType::get(context, std::nullopt, std::nullopt); auto boxProcTy = builder.getBoxProcType(funcTy); @@ -734,9 +734,9 @@ std::pair Fortran::lower::genCallOpAndResult( // Call a BIND(C) function that return a char. if (caller.characterize().IsBindC() && - mlir::isa(funcType.getResults()[0])) { + funcType.getResults()[0].isa()) { fir::CharacterType charTy = - mlir::dyn_cast(funcType.getResults()[0]); + funcType.getResults()[0].dyn_cast(); mlir::Value len = builder.createIntegerConstant( loc, builder.getCharacterLengthType(), charTy.getLen()); return {fir::CharBoxValue{callResult, len}, /*resultIsFinalized=*/false}; @@ -890,7 +890,7 @@ extendedValueToHlfirEntity(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type firBaseTy = firBase.getType(); if (fir::isa_trivial(firBaseTy)) return hlfir::EntityWithAttributes{firBase}; - if (auto charTy = mlir::dyn_cast(firBase.getType())) { + if (auto charTy = firBase.getType().dyn_cast()) { // CHAR() intrinsic and BIND(C) procedures returning CHARACTER(1) // are lowered to a fir.char that is not in memory. // This tends to cause a lot of bugs because the rest of the @@ -1061,7 +1061,7 @@ static hlfir::Entity fixProcedureDummyMismatch(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity actual, mlir::Type dummyType) { - if (mlir::isa(actual.getType()) && + if (actual.getType().isa() && fir::isCharacterProcedureTuple(dummyType)) { mlir::Value length = builder.create(loc, builder.getCharacterLengthType()); @@ -1070,7 +1070,7 @@ static hlfir::Entity fixProcedureDummyMismatch(mlir::Location loc, return hlfir::Entity{tuple}; } assert(fir::isCharacterProcedureTuple(actual.getType()) && - mlir::isa(dummyType) && + dummyType.isa() && "unsupported dummy procedure mismatch with the actual argument"); mlir::Value boxProc = fir::factory::extractCharacterProcedureTuple( builder, loc, actual, /*openBoxProc=*/false) @@ -1143,7 +1143,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( assert(actual.isProcedure()); // Do nothing if this is a procedure argument. It is already a // fir.boxproc/fir.tuple as it should. - if (!mlir::isa(actual.getType()) && + if (!actual.getType().isa() && actual.getType() != dummyType) // The actual argument may be a procedure that returns character (a // fir.tuple) while the dummy is not. Extract the tuple @@ -1164,7 +1164,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( // dynamic type matters to determine the contiguity. const bool mustSetDynamicTypeToDummyType = passingPolymorphicToNonPolymorphic && - (actual.isArray() || mlir::isa(dummyType)); + (actual.isArray() || dummyType.isa()); // The simple contiguity of the actual is "lost" when passing a polymorphic // to a non polymorphic entity because the dummy dynamic type matters for @@ -1236,7 +1236,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( preparedDummy.pushExprAssociateCleanUp(associate); } else if (mustDoCopyInOut) { // Copy-in non contiguous variables. - assert(mlir::isa(entity.getType()) && + assert(entity.getType().isa() && "expect non simply contiguous variables to be boxes"); if (actualIsAssumedRank) TODO(loc, "copy-in and copy-out of assumed-rank arguments"); @@ -1294,14 +1294,13 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( // Step 3: now that the dummy argument storage has been prepared, package // it according to the interface. mlir::Value addr; - if (mlir::isa(dummyTypeWithActualRank)) { + if (dummyTypeWithActualRank.isa()) { addr = hlfir::genVariableBoxChar(loc, builder, entity); - } else if (mlir::isa(dummyTypeWithActualRank)) { + } else if (dummyTypeWithActualRank.isa()) { entity = hlfir::genVariableBox(loc, builder, entity); // Ensures the box has the right attributes and that it holds an // addendum if needed. - fir::BaseBoxType actualBoxType = - mlir::cast(entity.getType()); + fir::BaseBoxType actualBoxType = entity.getType().cast(); mlir::Type boxEleType = actualBoxType.getEleTy(); // For now, assume it is not OK to pass the allocatable/pointer // descriptor to a non pointer/allocatable dummy. That is a strict @@ -1568,7 +1567,7 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, // callee side, and it is illegal to use NULL without a MOLD if any // dummy length parameters are assumed. mlir::Type boxTy = fir::dyn_cast_ptrEleTy(argTy); - assert(boxTy && mlir::isa(boxTy) && + assert(boxTy && boxTy.isa() && "must be a fir.box type"); mlir::Value boxStorage = fir::factory::genNullBoxStorage(builder, loc, boxTy); @@ -1636,8 +1635,7 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, caller, callSiteType, callContext.resultType, callContext.isElementalProcWithArrayArgs()); // For procedure pointer function result, just return the call. - if (callContext.resultType && - mlir::isa(*callContext.resultType)) + if (callContext.resultType && callContext.resultType->isa()) return hlfir::EntityWithAttributes(fir::getBase(result)); /// Clean-up associations and copy-in. @@ -2117,9 +2115,9 @@ public: hlfir::getFortranElementType(*callContext.resultType); // Get result length parameters. llvm::SmallVector typeParams; - if (mlir::isa(elementType) || + if (elementType.isa() || fir::isRecordWithTypeParameters(elementType)) { - auto charType = mlir::dyn_cast(elementType); + auto charType = elementType.dyn_cast(); if (charType && charType.hasConstantLen()) typeParams.push_back(builder.createIntegerConstant( loc, builder.getIndexType(), charType.getLen())); @@ -2525,7 +2523,7 @@ genIntrinsicRef(const Fortran::evaluate::SpecificIntrinsic *intrinsic, } std::optional result = genHLFIRIntrinsicRefCore( loweredActuals, intrinsic, argLowering, callContext); - if (result && mlir::isa(result->getType())) { + if (result && result->getType().isa()) { fir::FirOpBuilder *bldr = &callContext.getBuilder(); callContext.stmtCtx.attachCleanup( [=]() { bldr->create(loc, *result); }); diff --git a/flang/lib/Lower/ConvertConstant.cpp b/flang/lib/Lower/ConvertConstant.cpp index 653e874a969c..ed389bbe4ae5 100644 --- a/flang/lib/Lower/ConvertConstant.cpp +++ b/flang/lib/Lower/ConvertConstant.cpp @@ -184,8 +184,8 @@ private: if (!attributeElementType || attributes.empty()) return {}; - assert(mlir::isa(symTy) && "expecting an array global"); - auto arrTy = mlir::cast(symTy); + assert(symTy.isa() && "expecting an array global"); + auto arrTy = symTy.cast(); llvm::SmallVector tensorShape(arrTy.getShape()); std::reverse(tensorShape.begin(), tensorShape.end()); auto tensorTy = @@ -423,14 +423,14 @@ static mlir::Value genStructureComponentInit( // address field, which ought to be an intptr_t on the target. mlir::Value addr = fir::getBase( Fortran::lower::genExtAddrInInitializer(converter, loc, expr)); - if (mlir::isa(addr.getType())) + if (addr.getType().isa()) addr = builder.create(loc, addr); assert((fir::isa_ref_type(addr.getType()) || - mlir::isa(addr.getType())) && + addr.getType().isa()) && "expect reference type for address field"); assert(fir::isa_derived(componentTy) && "expect C_PTR, C_FUNPTR to be a record"); - auto cPtrRecTy = mlir::cast(componentTy); + auto cPtrRecTy = componentTy.cast(); llvm::StringRef addrFieldName = Fortran::lower::builtin::cptrFieldName; mlir::Type addrFieldTy = cPtrRecTy.getType(addrFieldName); auto addrField = builder.create( @@ -460,7 +460,7 @@ static mlir::Value genInlinedStructureCtorLitImpl( Fortran::lower::AbstractConverter &converter, mlir::Location loc, const Fortran::evaluate::StructureConstructor &ctor, mlir::Type type) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - auto recTy = mlir::cast(type); + auto recTy = type.cast(); if (!converter.getLoweringOptions().getLowerToHighLevelFIR()) { mlir::Value res = builder.create(loc, recTy); @@ -587,7 +587,7 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, } while (con.IncrementSubscripts(subscripts)); } else if constexpr (T::category == Fortran::common::TypeCategory::Derived) { do { - mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); + mlir::Type eleTy = arrayTy.cast().getEleTy(); mlir::Value elementVal = genScalarLit(converter, loc, con.At(subscripts), eleTy, /*outlineInReadOnlyMemory=*/false); @@ -597,7 +597,7 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, } else { llvm::SmallVector rangeStartIdx; uint64_t rangeSize = 0; - mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); + mlir::Type eleTy = arrayTy.cast().getEleTy(); do { auto getElementVal = [&]() { return builder.createConvert(loc, eleTy, @@ -620,11 +620,12 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, llvm::SmallVector rangeBounds; llvm::SmallVector idx = createIdx(); for (size_t i = 0; i < idx.size(); ++i) { - rangeBounds.push_back(mlir::cast(rangeStartIdx[i]) + rangeBounds.push_back(rangeStartIdx[i] + .cast() .getValue() .getSExtValue()); rangeBounds.push_back( - mlir::cast(idx[i]).getValue().getSExtValue()); + idx[i].cast().getValue().getSExtValue()); } array = builder.create( loc, arrayTy, array, getElementVal(), @@ -646,7 +647,7 @@ genOutlineArrayLit(Fortran::lower::AbstractConverter &converter, mlir::Location loc, mlir::Type arrayTy, const Fortran::evaluate::Constant &constant) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); + mlir::Type eleTy = arrayTy.cast().getEleTy(); llvm::StringRef globalName = converter.getUniqueLitName( loc, std::make_unique(toEvExpr(constant)), eleTy); diff --git a/flang/lib/Lower/ConvertExpr.cpp b/flang/lib/Lower/ConvertExpr.cpp index 9567685aa3d2..fb7807718ff8 100644 --- a/flang/lib/Lower/ConvertExpr.cpp +++ b/flang/lib/Lower/ConvertExpr.cpp @@ -267,7 +267,7 @@ arrayLoadExtValue(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type ty = fir::applyPathToType(arrTy, path); if (!ty) fir::emitFatalError(loc, "path does not apply to type"); - if (!mlir::isa(ty)) { + if (!ty.isa()) { if (fir::isa_char(ty)) { mlir::Value len = newLen; if (!len) @@ -282,7 +282,7 @@ arrayLoadExtValue(fir::FirOpBuilder &builder, mlir::Location loc, } return newBase; } - arrTy = mlir::cast(ty); + arrTy = ty.cast(); } auto arrayToExtendedValue = @@ -412,15 +412,15 @@ static fir::ExtendedValue genLoad(fir::FirOpBuilder &builder, return addr.match( [](const fir::CharBoxValue &box) -> fir::ExtendedValue { return box; }, [&](const fir::PolymorphicValue &p) -> fir::ExtendedValue { - if (mlir::isa( - fir::unwrapRefType(fir::getBase(p).getType()))) + if (fir::unwrapRefType(fir::getBase(p).getType()) + .isa()) return p; mlir::Value load = builder.create(loc, fir::getBase(p)); return fir::PolymorphicValue(load, p.getSourceBox()); }, [&](const fir::UnboxedValue &v) -> fir::ExtendedValue { - if (mlir::isa( - fir::unwrapRefType(fir::getBase(v).getType()))) + if (fir::unwrapRefType(fir::getBase(v).getType()) + .isa()) return v; return builder.create(loc, fir::getBase(v)); }, @@ -536,8 +536,8 @@ static mlir::Value createBoxProcCharTuple(Fortran::lower::AbstractConverter &converter, mlir::Type argTy, mlir::Value funcAddr, mlir::Value charLen) { - auto boxTy = mlir::cast( - mlir::cast(argTy).getType(0)); + auto boxTy = + argTy.cast().getType(0).cast(); mlir::Location loc = converter.getCurrentLocation(); auto &builder = converter.getFirOpBuilder(); @@ -549,7 +549,7 @@ createBoxProcCharTuple(Fortran::lower::AbstractConverter &converter, mlir::Type toTy = boxTy.getEleTy(); if (fir::isa_ref_type(fromTy)) funcAddr = builder.createConvert(loc, toTy, funcAddr); - else if (mlir::isa(fromTy)) + else if (fromTy.isa()) funcAddr = builder.create(loc, toTy, funcAddr); auto boxProc = [&]() -> mlir::Value { @@ -575,7 +575,7 @@ absentBoxToUnallocatedBox(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value isPresent) { mlir::Value box = fir::getBase(exv); mlir::Type boxType = box.getType(); - assert(mlir::isa(boxType) && "argument must be a fir.box"); + assert(boxType.isa() && "argument must be a fir.box"); mlir::Value emptyBox = fir::factory::createUnallocatedBox(builder, loc, boxType, std::nullopt); auto safeToReadBox = @@ -915,7 +915,7 @@ public: if (inInitializer) return Fortran::lower::genInlinedStructureCtorLit(converter, loc, ctor); mlir::Type ty = translateSomeExprToFIRType(converter, toEvExpr(ctor)); - auto recTy = mlir::cast(ty); + auto recTy = ty.cast(); auto fieldTy = fir::FieldType::get(ty.getContext()); mlir::Value res = builder.createTemporary(loc, recTy); mlir::Value box = builder.createBox(loc, fir::ExtendedValue{res}); @@ -1172,8 +1172,8 @@ public: if (!charBox) fir::emitFatalError(loc, "expected scalar character"); mlir::Value charAddr = charBox->getAddr(); - auto charType = mlir::cast( - fir::unwrapPassByRefType(charAddr.getType())); + auto charType = + fir::unwrapPassByRefType(charAddr.getType()).cast(); if (charType.hasConstantLen()) { // Erase previous constant length from the base type. fir::CharacterType::LenType newLen = fir::CharacterType::unknownLen(); @@ -1441,7 +1441,7 @@ public: auto fldTy = fir::FieldType::get(&converter.getMLIRContext()); // FIXME: need to thread the LEN type parameters here. for (const Fortran::evaluate::Component *field : list) { - auto recTy = mlir::cast(ty); + auto recTy = ty.cast(); const Fortran::semantics::Symbol &sym = getLastSym(*field); std::string name = converter.getRecordTypeFieldName(sym); coorArgs.push_back(builder.create( @@ -1478,7 +1478,7 @@ public: mlir::Type genSubType(mlir::Type arrTy, unsigned dims) { mlir::Type unwrapTy = fir::dyn_cast_ptrOrBoxEleTy(arrTy); assert(unwrapTy && "must be a pointer or box type"); - auto seqTy = mlir::cast(unwrapTy); + auto seqTy = unwrapTy.cast(); llvm::ArrayRef shape = seqTy.getShape(); assert(shape.size() > 0 && "removing columns for sequence sans shape"); assert(dims <= shape.size() && "removing more columns than exist"); @@ -1550,9 +1550,9 @@ public: } mlir::Type eleTy = fir::dyn_cast_ptrOrBoxEleTy(base.getType()); - if (auto classTy = mlir::dyn_cast(eleTy)) + if (auto classTy = eleTy.dyn_cast()) eleTy = classTy.getEleTy(); - auto seqTy = mlir::cast(eleTy); + auto seqTy = eleTy.cast(); assert(args.size() == seqTy.getDimension()); mlir::Type ty = builder.getRefType(seqTy.getEleTy()); auto addr = builder.create(loc, ty, base, args); @@ -1571,7 +1571,7 @@ public: mlir::Location loc = getLoc(); mlir::Value addr = fir::getBase(array); mlir::Type arrTy = fir::dyn_cast_ptrEleTy(addr.getType()); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); mlir::Type seqTy = builder.getRefType(builder.getVarLenSeqTy(eleTy)); mlir::Type refTy = builder.getRefType(eleTy); mlir::Value base = builder.createConvert(loc, seqTy, addr); @@ -1656,7 +1656,7 @@ public: mlir::Location loc = getLoc(); mlir::Value addr = fir::getBase(exv); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(addr.getType()); - mlir::Type eleTy = mlir::cast(arrTy).getEleTy(); + mlir::Type eleTy = arrTy.cast().getEleTy(); mlir::Type refTy = builder.getRefType(eleTy); mlir::IndexType idxTy = builder.getIndexType(); llvm::SmallVector arrayCoorArgs; @@ -1766,9 +1766,8 @@ public: mlir::Location loc = getLoc(); ExtValue exv = genBoxArg(expr); auto exvTy = fir::getBase(exv).getType(); - if (mlir::isa(exvTy)) { - auto boxProcTy = - builder.getBoxProcType(mlir::cast(exvTy)); + if (exvTy.isa()) { + auto boxProcTy = builder.getBoxProcType(exvTy.cast()); return builder.create(loc, boxProcTy, fir::getBase(exv)); } @@ -1862,7 +1861,7 @@ public: // IS_CONTIGUOUS may require an assumed size TYPE(*) to be passed to // the intrinsic library utility as a fir.box. if (argRules.lowerAs == fir::LowerIntrinsicArgAs::Box && - !mlir::isa(fir::getBase(exv).getType())) { + !fir::getBase(exv).getType().isa()) { operands.emplace_back( fir::factory::createBoxValue(builder, loc, exv)); continue; @@ -2006,7 +2005,7 @@ public: fir::getTypeParams(mold); mlir::Value charLen; mlir::Type elementType = fir::unwrapSequenceType(type); - if (auto charType = mlir::dyn_cast(elementType)) { + if (auto charType = elementType.dyn_cast()) { charLen = allocMemTypeParams.empty() ? fir::factory::readCharLen(builder, loc, mold) : allocMemTypeParams[0]; @@ -2018,7 +2017,7 @@ public: mlir::Value temp = builder.create( loc, type, tempName, allocMemTypeParams, extents); - if (mlir::isa(fir::unwrapSequenceType(type))) + if (fir::unwrapSequenceType(type).isa()) return fir::CharArrayBoxValue{temp, charLen, extents}; return fir::ArrayBoxValue{temp, extents}; } @@ -2167,7 +2166,7 @@ public: // We have to initialize the temp if it may have components // that need initialization. If there are no components // requiring initialization, then the call is a no-op. - if (mlir::isa(getElementTypeOf(temp))) { + if (getElementTypeOf(temp).isa()) { mlir::Value tempBox = fir::getBase(builder.createBox(loc, temp)); fir::runtime::genDerivedTypeInitialize(builder, loc, tempBox); } @@ -2313,7 +2312,7 @@ public: if (!copyOutPair.restrictCopyAndFreeAtRuntime) { doCopyOut(); - if (mlir::isa(fir::getElementTypeOf(copyOutPair.temp))) { + if (fir::getElementTypeOf(copyOutPair.temp).isa()) { // Destroy components of the temporary (if any). // If there are no components requiring destruction, then the call // is a no-op. @@ -2331,8 +2330,7 @@ public: builder.genIfThen(loc, *copyOutPair.restrictCopyAndFreeAtRuntime) .genThen([&]() { doCopyOut(); - if (mlir::isa( - fir::getElementTypeOf(copyOutPair.temp))) { + if (fir::getElementTypeOf(copyOutPair.temp).isa()) { // Destroy components of the temporary (if any). // If there are no components requiring destruction, then the call // is a no-op. @@ -2383,7 +2381,7 @@ public: mlir::Value actualArgBase = fir::getBase(actualArg); mlir::Value isPresent = builder.create( loc, builder.getI1Type(), actualArgBase); - if (!mlir::isa(actualArgBase.getType())) + if (!actualArgBase.getType().isa()) return {actualArg, isPresent}; ExtValue safeToReadBox = absentBoxToUnallocatedBox(builder, loc, actualArg, isPresent); @@ -2410,7 +2408,7 @@ public: fir::getAdaptToByRefAttr(builder)}); return fir::CharBoxValue{temp, len}; } - assert((fir::isa_trivial(type) || mlir::isa(type)) && + assert((fir::isa_trivial(type) || type.isa()) && "must be simple scalar"); return builder.createTemporary(loc, type, llvm::ArrayRef{ @@ -2587,7 +2585,7 @@ public: // callee side, and it is illegal to use NULL without a MOLD if any // dummy length parameters are assumed. mlir::Type boxTy = fir::dyn_cast_ptrEleTy(argTy); - assert(boxTy && mlir::isa(boxTy) && + assert(boxTy && boxTy.isa() && "must be a fir.box type"); mlir::Value boxStorage = builder.createTemporary(loc, boxTy); mlir::Value nullBox = fir::factory::createUnallocatedBox( @@ -2645,11 +2643,10 @@ public: // If a character procedure was passed instead, handle the // mismatch. auto funcTy = - mlir::dyn_cast(x.getAddr().getType()); + x.getAddr().getType().dyn_cast(); if (funcTy && funcTy.getNumResults() == 1 && - mlir::isa(funcTy.getResult(0))) { - auto boxTy = - mlir::cast(funcTy.getResult(0)); + funcTy.getResult(0).isa()) { + auto boxTy = funcTy.getResult(0).cast(); mlir::Value ref = builder.createConvert( loc, builder.getRefType(boxTy.getEleTy()), x.getAddr()); auto len = builder.create( @@ -2670,7 +2667,7 @@ public: // free-casting the base address to be a !fir.char reference and // setting the LEN argument to undefined. What could go wrong? auto dataPtr = fir::getBase(x); - assert(!mlir::isa(dataPtr.getType())); + assert(!dataPtr.getType().template isa()); return builder.convertWithSemantics( loc, argTy, dataPtr, /*allowCharacterConversion=*/true); @@ -2745,7 +2742,7 @@ public: loc, fir::ClassType::get(mlir::NoneType::get(builder.getContext())), box); - } else if (mlir::isa(box.getType()) && + } else if (box.getType().isa() && fir::isPolymorphicType(argTy)) { box = builder.create(loc, argTy, box, mlir::Value{}, /*slice=*/mlir::Value{}); @@ -2794,7 +2791,7 @@ public: : builder.createBox(getLoc(), genTempExtAddr(*expr), fir::isPolymorphicType(argTy), fir::isAssumedType(argTy)); - if (mlir::isa(box.getType()) && + if (box.getType().isa() && fir::isPolymorphicType(argTy) && !fir::isAssumedType(argTy)) { mlir::Type actualTy = argTy; if (Fortran::lower::isParentComponent(*expr)) @@ -3033,11 +3030,10 @@ private: Fortran::common::ScopedSet(semant, PushVal); static bool isAdjustedArrayElementType(mlir::Type t) { - return fir::isa_char(t) || fir::isa_derived(t) || - mlir::isa(t); + return fir::isa_char(t) || fir::isa_derived(t) || t.isa(); } static bool elementTypeWasAdjusted(mlir::Type t) { - if (auto ty = mlir::dyn_cast(t)) + if (auto ty = t.dyn_cast()) return isAdjustedArrayElementType(ty.getEleTy()); return false; } @@ -3054,15 +3050,15 @@ static void genScalarUserDefinedAssignmentCall(fir::FirOpBuilder &builder, auto prepareUserDefinedArg = [](fir::FirOpBuilder &builder, mlir::Location loc, const fir::ExtendedValue &value, mlir::Type argType) -> mlir::Value { - if (mlir::isa(argType)) { + if (argType.isa()) { const fir::CharBoxValue *charBox = value.getCharBox(); assert(charBox && "argument type mismatch in elemental user assignment"); return fir::factory::CharacterExprHelper{builder, loc}.createEmbox( *charBox); } - if (mlir::isa(argType)) { + if (argType.isa()) { mlir::Value box = - builder.createBox(loc, value, mlir::isa(argType)); + builder.createBox(loc, value, argType.isa()); return builder.createConvert(loc, argType, box); } // Simple pass by address. @@ -3174,7 +3170,7 @@ convertToArrayBoxValue(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value val, mlir::Value len) { mlir::Type ty = fir::unwrapRefType(val.getType()); mlir::IndexType idxTy = builder.getIndexType(); - auto seqTy = mlir::cast(ty); + auto seqTy = ty.cast(); auto undef = builder.create(loc, idxTy); llvm::SmallVector extents(seqTy.getDimension(), undef); if (fir::isa_char(seqTy.getEleTy())) @@ -3466,7 +3462,7 @@ public: [&](const auto &e) { auto f = genarr(e); ExtValue exv = f(IterationSpace{}); - if (mlir::isa(fir::getBase(exv).getType())) + if (fir::getBase(exv).getType().template isa()) return exv; fir::emitFatalError(getLoc(), "array must be emboxed"); }, @@ -3491,9 +3487,10 @@ public: tempRes, dest.getSlice(), dest.getTypeparams()); - auto arrTy = mlir::cast( - fir::dyn_cast_ptrEleTy(tempRes.getType())); - if (auto charTy = mlir::dyn_cast(arrTy.getEleTy())) { + auto arrTy = + fir::dyn_cast_ptrEleTy(tempRes.getType()).cast(); + if (auto charTy = + arrTy.getEleTy().template dyn_cast()) { if (fir::characterWithDynamicLen(charTy)) TODO(loc, "CHARACTER does not have constant LEN"); mlir::Value len = builder.createIntegerConstant( @@ -3915,18 +3912,17 @@ private: mlir::Value convertElementForUpdate(mlir::Location loc, mlir::Type eleTy, mlir::Value origVal) { if (auto origEleTy = fir::dyn_cast_ptrEleTy(origVal.getType())) - if (mlir::isa(origEleTy)) { + if (origEleTy.isa()) { // If origVal is a box variable, load it so it is in the value domain. origVal = builder.create(loc, origVal); } - if (mlir::isa(origVal.getType()) && - !mlir::isa(eleTy)) { + if (origVal.getType().isa() && !eleTy.isa()) { if (isPointerAssignment()) TODO(loc, "lhs of pointer assignment returned unexpected value"); TODO(loc, "invalid box conversion in elemental computation"); } - if (isPointerAssignment() && mlir::isa(eleTy) && - !mlir::isa(origVal.getType())) { + if (isPointerAssignment() && eleTy.isa() && + !origVal.getType().isa()) { // This is a pointer assignment and the rhs is a raw reference to a TARGET // in memory. Embox the reference so it can be stored to the boxed // POINTER variable. @@ -3934,7 +3930,7 @@ private: if (auto eleTy = fir::dyn_cast_ptrEleTy(origVal.getType()); fir::hasDynamicSize(eleTy)) TODO(loc, "TARGET of pointer assignment with runtime size/shape"); - auto memrefTy = fir::boxMemRefType(mlir::cast(eleTy)); + auto memrefTy = fir::boxMemRefType(eleTy.cast()); auto castTo = builder.createConvert(loc, memrefTy, origVal); origVal = builder.create(loc, eleTy, castTo); } @@ -3986,7 +3982,7 @@ private: auto arrayOp = builder.create( loc, resRefTy, innerArg, iterSpace.iterVec(), fir::factory::getTypeParams(loc, builder, destination)); - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { llvm::SmallVector substringBounds; populateBounds(substringBounds, substring); mlir::Value dstLen = fir::factory::genLenOfCharacter( @@ -4000,7 +3996,7 @@ private: loc, destination, builder, arrayOp, exv, eleTy, innerArg); return abstractArrayExtValue(amend /*FIXME: typeparams?*/); } - assert(mlir::isa(eleTy) && "must be an array"); + assert(eleTy.isa() && "must be an array"); TODO(loc, "array (as element) assignment"); } // By value semantics. The element is being assigned by value. @@ -4064,7 +4060,7 @@ private: llvm::SmallVector getShape(ArrayOperand array) { if (array.slice) return computeSliceShape(array.slice); - if (mlir::isa(array.memref.getType())) + if (array.memref.getType().isa()) return fir::factory::readExtents(builder, getLoc(), fir::BoxValue{array.memref}); return fir::factory::getExtents(array.shape); @@ -4137,7 +4133,7 @@ private: mlir::Location loc = getLoc(); return [=, builder = &converter.getFirOpBuilder()](IterSpace iters) { mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(tmp.getType()); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); mlir::Type eleRefTy = builder->getRefType(eleTy); mlir::IntegerType i1Ty = builder->getI1Type(); // Adjust indices for any shift of the origin of the array. @@ -4446,15 +4442,15 @@ private: TODO(loc, "polymorphic array temporary"); if (ccLoadDest) return (*ccLoadDest)(shape); - auto seqTy = mlir::dyn_cast(type); + auto seqTy = type.dyn_cast(); assert(seqTy && "must be an array"); // TODO: Need to thread the LEN parameters here. For character, they may // differ from the operands length (e.g concatenation). So the array loads // type parameters are not enough. - if (auto charTy = mlir::dyn_cast(seqTy.getEleTy())) + if (auto charTy = seqTy.getEleTy().dyn_cast()) if (charTy.hasDynamicLen()) TODO(loc, "character array expression temp with dynamic length"); - if (auto recTy = mlir::dyn_cast(seqTy.getEleTy())) + if (auto recTy = seqTy.getEleTy().dyn_cast()) if (recTy.getNumLenParams() > 0) TODO(loc, "derived type array expression temp with LEN parameters"); if (mlir::Type eleTy = fir::unwrapSequenceType(type); @@ -4831,7 +4827,7 @@ private: }); } else { ExtValue exv = asScalarRef(*expr); - if (mlir::isa(fir::getBase(exv).getType())) { + if (fir::getBase(exv).getType().isa()) { operands.emplace_back( [=](IterSpace iters) -> ExtValue { return exv; }); } else { @@ -5569,7 +5565,7 @@ private: } static mlir::Type unwrapBoxEleTy(mlir::Type ty) { - if (auto boxTy = mlir::dyn_cast(ty)) + if (auto boxTy = ty.dyn_cast()) return fir::unwrapRefType(boxTy.getEleTy()); return ty; } @@ -5579,7 +5575,7 @@ private: ty = unwrapBoxEleTy(ty); mlir::Location loc = getLoc(); mlir::IndexType idxTy = builder.getIndexType(); - for (auto extent : mlir::cast(ty).getShape()) { + for (auto extent : ty.cast().getShape()) { auto v = extent == fir::SequenceType::getUnknownExtent() ? builder.create(loc, idxTy).getResult() : builder.createIntegerConstant(loc, idxTy, extent); @@ -5642,8 +5638,7 @@ private: mlir::Location loc = getLoc(); mlir::Value memref = fir::getBase(extMemref); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(memref.getType()); - assert(mlir::isa(arrTy) && - "memory ref must be an array"); + assert(arrTy.isa() && "memory ref must be an array"); mlir::Value shape = builder.createShape(loc, extMemref); mlir::Value slice; if (components.isSlice()) { @@ -5693,12 +5688,12 @@ private: components.suffixComponents); } if (components.hasComponents()) { - auto seqTy = mlir::cast(arrTy); + auto seqTy = arrTy.cast(); mlir::Type eleTy = fir::applyPathToType(seqTy.getEleTy(), components.suffixComponents); if (!eleTy) fir::emitFatalError(loc, "slicing path is ill-formed"); - if (auto realTy = mlir::dyn_cast(eleTy)) + if (auto realTy = eleTy.dyn_cast()) eleTy = Fortran::lower::convertReal(realTy.getContext(), realTy.getFKind()); @@ -5718,14 +5713,13 @@ private: // value. The value of the box is forwarded in the continuation. mlir::Type reduceTy = reduceRank(arrTy, slice); mlir::Type boxTy = fir::BoxType::get(reduceTy); - if (mlir::isa(memref.getType()) && - !components.hasComponents()) + if (memref.getType().isa() && !components.hasComponents()) boxTy = fir::ClassType::get(reduceTy); if (components.substring) { // Adjust char length to substring size. fir::CharacterType charTy = fir::factory::CharacterExprHelper::getCharType(reduceTy); - auto seqTy = mlir::cast(reduceTy); + auto seqTy = reduceTy.cast(); // TODO: Use a constant for fir.char LEN if we can compute it. boxTy = fir::BoxType::get( fir::SequenceType::get(fir::CharacterType::getUnknownLen( @@ -5740,7 +5734,7 @@ private: nonDeferredLenParams = fir::factory::getNonDeferredLenParams(extMemref); } mlir::Value embox = - mlir::isa(memref.getType()) + memref.getType().isa() ? builder.create(loc, boxTy, memref, shape, slice) .getResult() : builder @@ -5751,7 +5745,7 @@ private: return fir::BoxValue(embox, lbounds, nonDeferredLenParams); }; } - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); if (isReferentiallyOpaque()) { // Semantics are an opaque reference to an array. // This case forwards a continuation that will generate the address @@ -5766,12 +5760,12 @@ private: mlir::Value coor = builder.create( loc, refEleTy, memref, shape, slice, indices, fir::getTypeParams(extMemref)); - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { llvm::SmallVector substringBounds; populateBounds(substringBounds, components.substring); if (!substringBounds.empty()) { mlir::Value dstLen = fir::factory::genLenOfCharacter( - builder, loc, mlir::cast(arrTy), memref, + builder, loc, arrTy.cast(), memref, fir::getTypeParams(extMemref), iters.iterVec(), substringBounds); fir::CharBoxValue dstChar(coor, dstLen); @@ -5869,7 +5863,7 @@ private: mlir::Type eleRefTy = builder.getRefType(eleTy); mlir::Value arrayOp = builder.create( loc, eleRefTy, arrLd, iters.iterVec(), arrLdTypeParams); - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { llvm::SmallVector substringBounds; populateBounds(substringBounds, components.substring); if (!substringBounds.empty()) { @@ -5902,7 +5896,7 @@ private: const bool hasOptionalAttr = fir::valueHasFirAttribute(base, fir::getOptionalAttrName()); mlir::Type baseType = fir::unwrapRefType(base.getType()); - const bool isBox = mlir::isa(baseType); + const bool isBox = baseType.isa(); const bool isAllocOrPtr = Fortran::evaluate::IsAllocatableOrPointerObject(expr); mlir::Type arrType = fir::unwrapPassByRefType(baseType); @@ -5995,7 +5989,7 @@ private: if (slice) { auto slOp = mlir::dyn_cast(slice.getDefiningOp()); assert(slOp && "expected slice op"); - auto seqTy = mlir::dyn_cast(arrTy); + auto seqTy = arrTy.dyn_cast(); assert(seqTy && "expected array type"); mlir::Operation::operand_range triples = slOp.getTriples(); fir::SequenceType::Shape shape; @@ -6059,7 +6053,7 @@ private: mlir::IndexType idxTy = builder.getIndexType(); mlir::Value multiplier = builder.createIntegerConstant(loc, idxTy, 1); if (fir::hasDynamicSize(eleTy)) { - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { // Array of char with dynamic LEN parameter. Downcast to an array // of singleton char, and scale by the len type parameter from // `exv`. @@ -6080,7 +6074,7 @@ private: }); fir::CharacterType newEleTy = fir::CharacterType::getSingleton( eleTy.getContext(), charTy.getFKind()); - if (auto seqTy = mlir::dyn_cast(resTy)) { + if (auto seqTy = resTy.dyn_cast()) { assert(eleTy == seqTy.getEleTy()); resTy = fir::SequenceType::get(seqTy.getShape(), newEleTy); } @@ -6167,7 +6161,7 @@ private: if (!eleSz) { // Compute the element size at runtime. assert(fir::hasDynamicSize(eleTy)); - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { auto charBytes = builder.getKindMap().getCharacterBitsize(charTy.getFKind()) / 8; mlir::Value bytes = @@ -6187,7 +6181,7 @@ private: auto computeCoordinate = [&](mlir::Value buff, mlir::Value off) { mlir::Type refTy = eleRefTy; if (fir::hasDynamicSize(eleTy)) { - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { // Scale a simple pointer using dynamic length and offset values. auto chTy = fir::CharacterType::getSingleton(charTy.getContext(), charTy.getFKind()); @@ -6314,7 +6308,7 @@ private: builder.createConvert(loc, idxTy, fir::getBase(asScalar(x.upper()))); mlir::Value step = builder.createConvert(loc, idxTy, fir::getBase(asScalar(x.stride()))); - auto seqTy = mlir::cast(resTy); + auto seqTy = resTy.template cast(); mlir::Type eleTy = fir::unwrapSequenceType(seqTy); auto loop = builder.create(loc, lo, up, step, /*unordered=*/false, @@ -6381,7 +6375,7 @@ private: auto evExpr = toEvExpr(x); mlir::Type resTy = translateSomeExprToFIRType(converter, evExpr); mlir::IndexType idxTy = builder.getIndexType(); - auto seqTy = mlir::cast(resTy); + auto seqTy = resTy.template cast(); mlir::Type eleTy = fir::unwrapSequenceType(resTy); mlir::Value buffSize = builder.createTemporary(loc, idxTy, ".buff.size"); mlir::Value zero = builder.createIntegerConstant(loc, idxTy, 0); @@ -6725,7 +6719,7 @@ private: auto fieldTy = fir::FieldType::get(builder.getContext()); std::string name = converter.getRecordTypeFieldName(getLastSym(*x)); - if (auto recTy = mlir::dyn_cast(ty)) { + if (auto recTy = ty.dyn_cast()) { ty = recTy.getType(name); auto fld = builder.create( loc, fieldTy, name, recTy, fir::getTypeParams(arrayExv)); @@ -6734,7 +6728,7 @@ private: // Need an intermediate dereference if the boxed value // appears in the middle of the component path or if it is // on the right and this is not a pointer assignment. - if (auto boxTy = mlir::dyn_cast(ty)) { + if (auto boxTy = ty.dyn_cast()) { auto currentFunc = components.getExtendCoorRef(); auto loc = getLoc(); auto *bldr = &converter.getFirOpBuilder(); @@ -6745,9 +6739,9 @@ private: deref = true; } } - } else if (auto boxTy = mlir::dyn_cast(ty)) { + } else if (auto boxTy = ty.dyn_cast()) { ty = fir::unwrapRefType(boxTy.getEleTy()); - auto recTy = mlir::cast(ty); + auto recTy = ty.cast(); ty = recTy.getType(name); auto fld = builder.create( loc, fieldTy, name, recTy, fir::getTypeParams(arrayExv)); @@ -6796,7 +6790,7 @@ private: auto arrayOp = builder.create( loc, eleRefTy, innerArg, iters.iterVec(), fir::factory::getTypeParams(loc, builder, load)); - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { mlir::Value dstLen = fir::factory::genLenOfCharacter( builder, loc, load, iters.iterVec(), substringBounds); fir::ArrayAmendOp amend = createCharArrayAmend( @@ -6812,13 +6806,13 @@ private: return arrayLoadExtValue(builder, loc, load, iters.iterVec(), amend); } - assert(mlir::isa(eleTy)); + assert(eleTy.isa()); TODO(loc, "array (as element) assignment"); } if (components.hasExtendCoorRef()) { auto eleBoxTy = fir::applyPathToType(innerArg.getType(), iters.iterVec()); - if (!eleBoxTy || !mlir::isa(eleBoxTy)) + if (!eleBoxTy || !eleBoxTy.isa()) TODO(loc, "assignment in a FORALL involving a designator with a " "POINTER or ALLOCATABLE component part-ref"); auto arrayOp = builder.create( @@ -6830,7 +6824,7 @@ private: // assignment, then insert the dereference of the box before any // conversion and store. if (!isPointerAssignment()) { - if (auto boxTy = mlir::dyn_cast(eleTy)) { + if (auto boxTy = eleTy.dyn_cast()) { eleTy = fir::boxMemRefType(boxTy); addr = builder.create(loc, eleTy, addr); eleTy = fir::unwrapRefType(eleTy); @@ -6891,7 +6885,7 @@ private: } if (components.hasExtendCoorRef()) { auto eleBoxTy = fir::applyPathToType(load.getType(), iters.iterVec()); - if (!eleBoxTy || !mlir::isa(eleBoxTy)) + if (!eleBoxTy || !eleBoxTy.isa()) TODO(loc, "assignment in a FORALL involving a designator with a " "POINTER or ALLOCATABLE component part-ref"); auto access = builder.create( @@ -6903,7 +6897,7 @@ private: } if (isPointerAssignment()) { auto eleTy = fir::applyPathToType(load.getType(), iters.iterVec()); - if (!mlir::isa(eleTy)) { + if (!eleTy.isa()) { // Rhs is a regular expression that will need to be boxed before // assigning to the boxed variable. auto typeParams = fir::factory::getTypeParams(loc, builder, load); @@ -7621,7 +7615,7 @@ mlir::Value Fortran::lower::addCrayPointerInst(mlir::Location loc, auto box = builder.create(loc, boxTy, ptrVal, empty, empty, emptyRange); mlir::Value addrof = - (mlir::isa(ptrTy)) + (ptrTy.isa()) ? builder.create(loc, ptrTy, box) : builder.create(loc, builder.getRefType(ptrTy), box); diff --git a/flang/lib/Lower/ConvertExprToHLFIR.cpp b/flang/lib/Lower/ConvertExprToHLFIR.cpp index 93bdf650f9ff..6e57b31d022b 100644 --- a/flang/lib/Lower/ConvertExprToHLFIR.cpp +++ b/flang/lib/Lower/ConvertExprToHLFIR.cpp @@ -138,8 +138,8 @@ public: mlir::Location loc = getLoc(); mlir::Type idxTy = builder.getIndexType(); llvm::SmallVector extents; - auto seqTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(fieldType)); + auto seqTy = hlfir::getFortranElementOrSequenceType(fieldType) + .cast(); for (auto extent : seqTy.getShape()) { if (extent == fir::SequenceType::getUnknownExtent()) { // We have already generated invalid hlfir.declare @@ -199,7 +199,7 @@ private: const T &designatorNode) { // Get base's shape if its a sequence type with no previously computed // result shape - if (partInfo.base && mlir::isa(resultValueType) && + if (partInfo.base && resultValueType.isa() && !partInfo.resultShape) partInfo.resultShape = hlfir::genShape(getLoc(), getBuilder(), *partInfo.base); @@ -209,7 +209,7 @@ private: return fir::ClassType::get(resultValueType); // Character scalar with dynamic length needs a fir.boxchar to hold the // designator length. - auto charType = mlir::dyn_cast(resultValueType); + auto charType = resultValueType.dyn_cast(); if (charType && charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); // Arrays with non default lower bounds or dynamic length or dynamic extent @@ -218,7 +218,7 @@ private: hasNonDefaultLowerBounds(partInfo)) return fir::BoxType::get(resultValueType); // Non simply contiguous ref require a fir.box to carry the byte stride. - if (mlir::isa(resultValueType) && + if (resultValueType.isa() && !Fortran::evaluate::IsSimplyContiguous( designatorNode, getConverter().getFoldingContext())) return fir::BoxType::get(resultValueType); @@ -398,8 +398,8 @@ private: partInfo.typeParams[0] = fir::factory::genMaxWithZero(builder, loc, rawLen); } - auto kind = mlir::cast( - hlfir::getFortranElementType(baseStringType)) + auto kind = hlfir::getFortranElementType(baseStringType) + .cast() .getFKind(); auto newCharTy = fir::CharacterType::get( baseStringType.getContext(), kind, @@ -579,7 +579,7 @@ private: return createVectorSubscriptElementAddrOp(partInfo, baseType, resultExtents); - mlir::Type resultType = mlir::cast(baseType).getEleTy(); + mlir::Type resultType = baseType.cast().getEleTy(); if (!resultTypeShape.empty()) { // Ranked array section. The result shape comes from the array section // subscripts. @@ -612,8 +612,8 @@ private: } static bool hasNonDefaultLowerBounds(const PartInfo &partInfo) { return partInfo.resultShape && - mlir::isa( - partInfo.resultShape.getType()); + (partInfo.resultShape.getType().isa() || + partInfo.resultShape.getType().isa()); } mlir::Type visit(const Fortran::evaluate::Component &component, @@ -705,7 +705,7 @@ private: const Fortran::semantics::Symbol &componentSym = component.GetLastSymbol(); partInfo.componentName = converter.getRecordTypeFieldName(componentSym); auto recordType = - mlir::cast(hlfir::getFortranElementType(baseType)); + hlfir::getFortranElementType(baseType).cast(); if (recordType.isDependentType()) TODO(getLoc(), "Designate derived type with length parameters in HLFIR"); mlir::Type fieldType = recordType.getType(partInfo.componentName); @@ -718,7 +718,7 @@ private: if (fir::isRecordWithTypeParameters(fieldEleType)) TODO(loc, "lower a component that is a parameterized derived type to HLFIR"); - if (auto charTy = mlir::dyn_cast(fieldEleType)) { + if (auto charTy = fieldEleType.dyn_cast()) { mlir::Location loc = getLoc(); mlir::Type idxTy = builder.getIndexType(); if (charTy.hasConstantLen()) @@ -811,7 +811,7 @@ private: } } builder.setInsertionPoint(elementalAddrOp); - return mlir::cast(baseType).getEleTy(); + return baseType.cast().getEleTy(); } /// Yield the designator for the final part-ref inside the @@ -1665,7 +1665,7 @@ private: mlir::Location loc = getLoc(); fir::FirOpBuilder &builder = getBuilder(); mlir::Type ty = translateSomeExprToFIRType(converter, toEvExpr(ctor)); - auto recTy = mlir::cast(ty); + auto recTy = ty.cast(); if (recTy.isDependentType()) TODO(loc, "structure constructor for derived type with length parameters " diff --git a/flang/lib/Lower/ConvertProcedureDesignator.cpp b/flang/lib/Lower/ConvertProcedureDesignator.cpp index aa0d7ce54788..2446be3a1908 100644 --- a/flang/lib/Lower/ConvertProcedureDesignator.cpp +++ b/flang/lib/Lower/ConvertProcedureDesignator.cpp @@ -107,11 +107,11 @@ static hlfir::EntityWithAttributes designateProcedurePointerComponent( procComponentSym); /// Passed argument may be a descriptor. This is a scalar reference, so the /// base address can be directly addressed. - if (mlir::isa(base.getType())) + if (base.getType().isa()) base = builder.create(loc, base); std::string fieldName = converter.getRecordTypeFieldName(procComponentSym); auto recordType = - mlir::cast(hlfir::getFortranElementType(base.getType())); + hlfir::getFortranElementType(base.getType()).cast(); mlir::Type fieldType = recordType.getType(fieldName); // Note: semantics turns x%p() into x%t%p() when the procedure pointer // component is part of parent component t. @@ -164,7 +164,7 @@ hlfir::EntityWithAttributes Fortran::lower::convertProcedureDesignatorToHLFIR( fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Value funcAddr = fir::getBase(procExv); - if (!mlir::isa(funcAddr.getType())) { + if (!funcAddr.getType().isa()) { mlir::Type boxTy = Fortran::lower::getUntypedBoxProcType(&converter.getMLIRContext()); if (auto host = Fortran::lower::argumentHostAssocs(converter, funcAddr)) diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index edf1f24a08e5..21db0cac11bf 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -389,13 +389,13 @@ static mlir::Value genDefaultInitializerValue( fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Type scalarType = symTy; fir::SequenceType sequenceType; - if (auto ty = mlir::dyn_cast(symTy)) { + if (auto ty = symTy.dyn_cast()) { sequenceType = ty; scalarType = ty.getEleTy(); } // Build a scalar default value of the symbol type, looping through the // components to build each component initial value. - auto recTy = mlir::cast(scalarType); + auto recTy = scalarType.cast(); mlir::Value initialValue = builder.create(loc, scalarType); const Fortran::semantics::DeclTypeSpec *declTy = sym.GetType(); assert(declTy && "var with default initialization must have a type"); @@ -493,9 +493,9 @@ static fir::GlobalOp defineGlobal(Fortran::lower::AbstractConverter &converter, // with a tensor mlir type. This optimization currently only supports // Fortran arrays of integer, real, complex, or logical. The tensor // type does not support nested structures. - if (mlir::isa(symTy) && + if (symTy.isa() && !Fortran::semantics::IsAllocatableOrPointer(sym)) { - mlir::Type eleTy = mlir::cast(symTy).getEleTy(); + mlir::Type eleTy = symTy.cast().getEleTy(); if (eleTy.isa()) { const auto *details = @@ -1292,7 +1292,7 @@ static void finalizeCommonBlockDefinition( fir::GlobalOp global, const Fortran::semantics::MutableSymbolVector &cmnBlkMems) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - mlir::TupleType commonTy = mlir::cast(global.getType()); + mlir::TupleType commonTy = global.getType().cast(); auto initFunc = [&](fir::FirOpBuilder &builder) { mlir::IndexType idxTy = builder.getIndexType(); mlir::Value cb = builder.create(loc, commonTy); @@ -1407,7 +1407,7 @@ static bool lowerToBoxValue(const Fortran::semantics::Symbol &sym, mlir::Value dummyArg, Fortran::lower::AbstractConverter &converter) { // Only dummy arguments coming as fir.box can be tracked in an BoxValue. - if (!dummyArg || !mlir::isa(dummyArg.getType())) + if (!dummyArg || !dummyArg.getType().isa()) return false; // Non contiguous arrays must be tracked in an BoxValue. if (sym.Rank() > 0 && !Fortran::evaluate::IsSimplyContiguous( @@ -1905,7 +1905,7 @@ void Fortran::lower::mapSymbolAttributes( // Do not keep scalar characters as fir.box (even when optional). // Lowering and FIR is not meant to deal with scalar characters as // fir.box outside of calls. - auto boxTy = mlir::dyn_cast(dummyArg.getType()); + auto boxTy = dummyArg.getType().dyn_cast(); mlir::Type refTy = builder.getRefType(boxTy.getEleTy()); mlir::Type lenType = builder.getCharacterLengthType(); mlir::Value addr, len; @@ -1984,8 +1984,8 @@ void Fortran::lower::mapSymbolAttributes( // a non pointer/allocatable symbol to be mapped to a MutableBox. mlir::Type ty = converter.genType(var); bool isPolymorphic = false; - if (auto boxTy = mlir::dyn_cast(ty)) { - isPolymorphic = mlir::isa(ty); + if (auto boxTy = ty.dyn_cast()) { + isPolymorphic = ty.isa(); ty = boxTy.getEleTy(); } Fortran::lower::genDeclareSymbol( @@ -2092,7 +2092,7 @@ void Fortran::lower::mapSymbolAttributes( mlir::Value addr = preAlloc; if (arg) - if (auto boxTy = mlir::dyn_cast(arg.getType())) { + if (auto boxTy = arg.getType().dyn_cast()) { // Contiguous assumed shape that can be tracked without a fir.box. mlir::Type refTy = builder.getRefType(boxTy.getEleTy()); addr = builder.create(loc, refTy, arg); @@ -2134,7 +2134,7 @@ void Fortran::lower::mapSymbolAttributes( } else if (!len) { // Assumed length fir.box (possible for contiguous assumed shapes). // Read length from box. - assert(arg && mlir::isa(arg.getType()) && + assert(arg && arg.getType().isa() && "must be character dummy fir.box"); len = charHelp.readLengthFromBox(arg); } diff --git a/flang/lib/Lower/CustomIntrinsicCall.cpp b/flang/lib/Lower/CustomIntrinsicCall.cpp index 30c6ce7f53b3..439fc3d915b4 100644 --- a/flang/lib/Lower/CustomIntrinsicCall.cpp +++ b/flang/lib/Lower/CustomIntrinsicCall.cpp @@ -227,23 +227,22 @@ lowerIshftc(fir::FirOpBuilder &builder, mlir::Location loc, args.push_back(getOperand(1, loadOperand)); auto iPC = isPresentCheck(2); assert(iPC.has_value()); - args.push_back( - builder - .genIfOp(loc, {resultType}, *iPC, - /*withElseRegion=*/true) - .genThen([&]() { - fir::ExtendedValue sizeExv = getOperand(2, loadOperand); - mlir::Value size = - builder.createConvert(loc, resultType, fir::getBase(sizeExv)); - builder.create(loc, size); - }) - .genElse([&]() { - mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, - mlir::cast(resultType).getWidth()); - builder.create(loc, bitSize); - }) - .getResults()[0]); + args.push_back(builder + .genIfOp(loc, {resultType}, *iPC, + /*withElseRegion=*/true) + .genThen([&]() { + fir::ExtendedValue sizeExv = getOperand(2, loadOperand); + mlir::Value size = builder.createConvert( + loc, resultType, fir::getBase(sizeExv)); + builder.create(loc, size); + }) + .genElse([&]() { + mlir::Value bitSize = builder.createIntegerConstant( + loc, resultType, + resultType.cast().getWidth()); + builder.create(loc, bitSize); + }) + .getResults()[0]); return genIntrinsicCall(builder, loc, name, resultType, args, stmtCtx); } @@ -283,7 +282,7 @@ lowerAssociated(fir::FirOpBuilder &builder, mlir::Location loc, builder.create(loc, builder.getI1Type(), targetBase); mlir::Type targetType = fir::unwrapRefType(targetBase.getType()); mlir::Type targetValueType = fir::unwrapPassByRefType(targetType); - mlir::Type boxType = mlir::isa(targetType) + mlir::Type boxType = targetType.isa() ? targetType : fir::BoxType::get(targetValueType); fir::BoxValue targetBox = diff --git a/flang/lib/Lower/DirectivesCommon.h b/flang/lib/Lower/DirectivesCommon.h index 42bd3868196b..3ebf3fd965da 100644 --- a/flang/lib/Lower/DirectivesCommon.h +++ b/flang/lib/Lower/DirectivesCommon.h @@ -642,14 +642,14 @@ getDataOperandBaseAddr(Fortran::lower::AbstractConverter &converter, isPresent = builder.create(loc, builder.getI1Type(), rawInput); - if (auto boxTy = mlir::dyn_cast( - fir::unwrapRefType(symAddr.getType()))) { - if (mlir::isa(boxTy.getEleTy())) + if (auto boxTy = + fir::unwrapRefType(symAddr.getType()).dyn_cast()) { + if (boxTy.getEleTy().isa()) TODO(loc, "derived type"); // Load the box when baseAddr is a `fir.ref>` or a // `fir.ref>` type. - if (mlir::isa(symAddr.getType())) { + if (symAddr.getType().isa()) { if (Fortran::semantics::IsOptional(sym)) { mlir::Value addr = builder.genIfOp(loc, {boxTy}, isPresent, /*withElseRegion=*/true) @@ -722,7 +722,7 @@ genBoundsOpsFromBox(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type idxTy = builder.getIndexType(); mlir::Type boundTy = builder.getType(); - assert(mlir::isa(info.addr.getType()) && + assert(info.addr.getType().isa() && "expect fir.box or fir.class"); if (info.isPresent) { @@ -909,8 +909,7 @@ genBoundsOps(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value stride = one; bool strideInBytes = false; - if (mlir::isa( - fir::unwrapRefType(info.addr.getType()))) { + if (fir::unwrapRefType(info.addr.getType()).isa()) { if (info.isPresent) { stride = builder @@ -1021,8 +1020,8 @@ genBoundsOps(fir::FirOpBuilder &builder, mlir::Location loc, } } - if (info.isPresent && mlir::isa( - fir::unwrapRefType(info.addr.getType()))) { + if (info.isPresent && + fir::unwrapRefType(info.addr.getType()).isa()) { extent = builder .genIfOp(loc, idxTy, info.isPresent, /*withElseRegion=*/true) @@ -1158,7 +1157,7 @@ AddrAndBoundsInfo gatherDataOperandAddrAndBounds( converter.genExprAddr(operandLocation, designator, stmtCtx); info.addr = fir::getBase(compExv); info.rawInput = info.addr; - if (mlir::isa(fir::unwrapRefType(info.addr.getType()))) + if (fir::unwrapRefType(info.addr.getType()).isa()) bounds = genBaseBoundsOps(builder, operandLocation, converter, compExv, /*isAssumedSize=*/false); @@ -1200,14 +1199,13 @@ AddrAndBoundsInfo gatherDataOperandAddrAndBounds( fir::ExtendedValue dataExv = converter.getSymbolExtendedValue(*symRef); info = getDataOperandBaseAddr(converter, builder, *symRef, operandLocation); - if (mlir::isa( - fir::unwrapRefType(info.addr.getType()))) { + if (fir::unwrapRefType(info.addr.getType()).isa()) { bounds = genBoundsOpsFromBox( builder, operandLocation, converter, dataExv, info); } bool dataExvIsAssumedSize = Fortran::semantics::IsAssumedSizeArray(symRef->get().GetUltimate()); - if (mlir::isa(fir::unwrapRefType(info.addr.getType()))) + if (fir::unwrapRefType(info.addr.getType()).isa()) bounds = genBaseBoundsOps( builder, operandLocation, converter, dataExv, dataExvIsAssumedSize); asFortran << symRef->get().name().ToString(); diff --git a/flang/lib/Lower/HlfirIntrinsics.cpp b/flang/lib/Lower/HlfirIntrinsics.cpp index 310b62697f71..bda04fa9689b 100644 --- a/flang/lib/Lower/HlfirIntrinsics.cpp +++ b/flang/lib/Lower/HlfirIntrinsics.cpp @@ -265,7 +265,7 @@ HlfirTransformationalIntrinsic::computeResultType(mlir::Value argArray, mlir::Type stmtResultType) { mlir::Type normalisedResult = hlfir::getFortranElementOrSequenceType(stmtResultType); - if (auto array = mlir::dyn_cast(normalisedResult)) { + if (auto array = normalisedResult.dyn_cast()) { hlfir::ExprType::Shape resultShape = hlfir::ExprType::Shape{array.getShape()}; mlir::Type elementType = array.getEleTy(); @@ -341,7 +341,7 @@ mlir::Value HlfirTransposeLowering::lowerImpl( hlfir::ExprType::Shape resultShape; mlir::Type normalisedResult = hlfir::getFortranElementOrSequenceType(stmtResultType); - auto array = mlir::cast(normalisedResult); + auto array = normalisedResult.cast(); llvm::ArrayRef arrayShape = array.getShape(); assert(arrayShape.size() == 2 && "arguments to transpose have a rank of 2"); mlir::Type elementType = array.getEleTy(); diff --git a/flang/lib/Lower/HostAssociations.cpp b/flang/lib/Lower/HostAssociations.cpp index 75a5bed56655..2e2656356719 100644 --- a/flang/lib/Lower/HostAssociations.cpp +++ b/flang/lib/Lower/HostAssociations.cpp @@ -219,7 +219,7 @@ public: static mlir::Type getType(Fortran::lower::AbstractConverter &converter, const Fortran::semantics::Symbol &sym) { fir::KindTy kind = - mlir::cast(converter.genType(sym)).getFKind(); + converter.genType(sym).cast().getFKind(); return fir::BoxCharType::get(&converter.getMLIRContext(), kind); } @@ -293,7 +293,7 @@ public: mlir::Location loc = args.loc; mlir::Value box = args.valueInTuple; if (Fortran::semantics::IsOptional(sym)) { - auto boxTy = mlir::cast(box.getType()); + auto boxTy = box.getType().cast(); auto eleTy = boxTy.getEleTy(); if (!fir::isa_ref_type(eleTy)) eleTy = builder.getRefType(eleTy); @@ -381,8 +381,8 @@ public: const Fortran::semantics::Symbol &sym) { mlir::Type type = converter.genType(sym); bool isPolymorphic = Fortran::semantics::IsPolymorphic(sym); - assert((mlir::isa(type) || - (isPolymorphic && mlir::isa(type))) && + assert((type.isa() || + (isPolymorphic && type.isa())) && "must be a sequence type"); if (isPolymorphic) return type; @@ -459,7 +459,7 @@ public: // (absent boxes are null descriptor addresses, not descriptors containing // a null base address). if (Fortran::semantics::IsOptional(sym)) { - auto boxTy = mlir::cast(box.getType()); + auto boxTy = box.getType().cast(); auto eleTy = boxTy.getEleTy(); if (!fir::isa_ref_type(eleTy)) eleTy = builder.getRefType(eleTy); @@ -527,7 +527,7 @@ walkCaptureCategories(T visitor, Fortran::lower::AbstractConverter &converter, // `t` should be the result of getArgumentType, which has a type of // `!fir.ref>`. static mlir::TupleType unwrapTupleTy(mlir::Type t) { - return mlir::cast(fir::dyn_cast_ptrEleTy(t)); + return fir::dyn_cast_ptrEleTy(t).cast(); } static mlir::Value genTupleCoor(fir::FirOpBuilder &builder, mlir::Location loc, @@ -535,7 +535,7 @@ static mlir::Value genTupleCoor(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value offset) { // fir.ref and fir.ptr are forbidden. Use // fir.llvm_ptr if needed. - auto ty = mlir::isa(varTy) + auto ty = varTy.isa() ? mlir::Type(fir::LLVMPointerType::get(varTy)) : mlir::Type(builder.getRefType(varTy)); return builder.create(loc, ty, tupleArg, offset); diff --git a/flang/lib/Lower/IO.cpp b/flang/lib/Lower/IO.cpp index ed0afad9197d..ac82276bcddb 100644 --- a/flang/lib/Lower/IO.cpp +++ b/flang/lib/Lower/IO.cpp @@ -168,7 +168,7 @@ static constexpr fir::runtime::FuncTypeBuilderFunc getTypeModel() { } inline int64_t getLength(mlir::Type argTy) { - return mlir::cast(argTy).getShape()[0]; + return argTy.cast().getShape()[0]; } /// Get (or generate) the MLIR FuncOp for a given IO runtime function. @@ -656,11 +656,11 @@ static void genNamelistIO(Fortran::lower::AbstractConverter &converter, static mlir::func::FuncOp getOutputFunc(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type type, bool isFormatted) { - if (mlir::isa(fir::unwrapPassByRefType(type))) + if (fir::unwrapPassByRefType(type).isa()) return getIORuntimeFunc(loc, builder); if (!isFormatted) return getIORuntimeFunc(loc, builder); - if (auto ty = mlir::dyn_cast(type)) { + if (auto ty = type.dyn_cast()) { switch (ty.getWidth()) { case 1: return getIORuntimeFunc(loc, builder); @@ -677,14 +677,14 @@ static mlir::func::FuncOp getOutputFunc(mlir::Location loc, } llvm_unreachable("unknown OutputInteger kind"); } - if (auto ty = mlir::dyn_cast(type)) { + if (auto ty = type.dyn_cast()) { if (auto width = ty.getWidth(); width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } auto kindMap = fir::getKindMapping(builder.getModule()); - if (auto ty = mlir::dyn_cast(type)) { + if (auto ty = type.dyn_cast()) { // COMPLEX(KIND=k) corresponds to a pair of REAL(KIND=k). auto width = kindMap.getRealBitsize(ty.getFKind()); if (width == 32) @@ -692,7 +692,7 @@ static mlir::func::FuncOp getOutputFunc(mlir::Location loc, else if (width == 64) return getIORuntimeFunc(loc, builder); } - if (mlir::isa(type)) + if (type.isa()) return getIORuntimeFunc(loc, builder); if (fir::factory::CharacterExprHelper::isCharacterScalar(type)) { // TODO: What would it mean if the default CHARACTER KIND is set to a wide @@ -731,14 +731,14 @@ static void genOutputItemList( mlir::func::FuncOp outputFunc = getOutputFunc(loc, builder, itemTy, isFormatted); mlir::Type argType = outputFunc.getFunctionType().getInput(1); - assert((isFormatted || mlir::isa(argType)) && + assert((isFormatted || argType.isa()) && "expect descriptor for unformatted IO runtime"); llvm::SmallVector outputFuncArgs = {cookie}; fir::factory::CharacterExprHelper helper{builder, loc}; - if (mlir::isa(argType)) { + if (argType.isa()) { mlir::Value box = fir::getBase(converter.genExprBox(loc, *expr, stmtCtx)); outputFuncArgs.push_back(builder.createConvert(loc, argType, box)); - if (mlir::isa(fir::unwrapPassByRefType(itemTy))) + if (fir::unwrapPassByRefType(itemTy).isa()) outputFuncArgs.push_back(getNonTbpDefinedIoTableAddr(converter)); } else if (helper.isCharacterScalar(itemTy)) { fir::ExtendedValue exv = converter.genExprAddr(loc, expr, stmtCtx); @@ -773,29 +773,29 @@ static void genOutputItemList( static mlir::func::FuncOp getInputFunc(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type type, bool isFormatted) { - if (mlir::isa(fir::unwrapPassByRefType(type))) + if (fir::unwrapPassByRefType(type).isa()) return getIORuntimeFunc(loc, builder); if (!isFormatted) return getIORuntimeFunc(loc, builder); - if (auto ty = mlir::dyn_cast(type)) + if (auto ty = type.dyn_cast()) return ty.getWidth() == 1 ? getIORuntimeFunc(loc, builder) : getIORuntimeFunc(loc, builder); - if (auto ty = mlir::dyn_cast(type)) { + if (auto ty = type.dyn_cast()) { if (auto width = ty.getWidth(); width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } auto kindMap = fir::getKindMapping(builder.getModule()); - if (auto ty = mlir::dyn_cast(type)) { + if (auto ty = type.dyn_cast()) { auto width = kindMap.getRealBitsize(ty.getFKind()); if (width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } - if (mlir::isa(type)) + if (type.isa()) return getIORuntimeFunc(loc, builder); if (fir::factory::CharacterExprHelper::isCharacterScalar(type)) { auto asciiKind = kindMap.defaultCharacterKind(); @@ -830,12 +830,12 @@ createIoRuntimeCallForItem(Fortran::lower::AbstractConverter &converter, fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Type argType = inputFunc.getFunctionType().getInput(1); llvm::SmallVector inputFuncArgs = {cookie}; - if (mlir::isa(argType)) { + if (argType.isa()) { mlir::Value box = fir::getBase(item); - auto boxTy = mlir::dyn_cast(box.getType()); + auto boxTy = box.getType().dyn_cast(); assert(boxTy && "must be previously emboxed"); inputFuncArgs.push_back(builder.createConvert(loc, argType, box)); - if (mlir::isa(fir::unwrapPassByRefType(boxTy))) + if (fir::unwrapPassByRefType(boxTy).isa()) inputFuncArgs.push_back(getNonTbpDefinedIoTableAddr(converter)); } else { mlir::Value itemAddr = fir::getBase(item); @@ -846,16 +846,16 @@ createIoRuntimeCallForItem(Fortran::lower::AbstractConverter &converter, mlir::Value len = fir::getLen(item); inputFuncArgs.push_back(builder.createConvert( loc, inputFunc.getFunctionType().getInput(2), len)); - } else if (mlir::isa(itemTy)) { + } else if (itemTy.isa()) { inputFuncArgs.push_back(builder.create( loc, builder.getI32IntegerAttr( - mlir::cast(itemTy).getWidth() / 8))); + itemTy.cast().getWidth() / 8))); } } auto call = builder.create(loc, inputFunc, inputFuncArgs); auto itemAddr = fir::getBase(item); auto itemTy = fir::unwrapRefType(itemAddr.getType()); - if (mlir::isa(itemTy)) + if (itemTy.isa()) boolRefToLogical(loc, builder, itemAddr); return call.getResult(0); } @@ -886,7 +886,7 @@ static void genInputItemList(Fortran::lower::AbstractConverter &converter, mlir::func::FuncOp inputFunc = getInputFunc( loc, builder, vectorSubscriptBox.getElementType(), isFormatted); const bool mustBox = - mlir::isa(inputFunc.getFunctionType().getInput(1)); + inputFunc.getFunctionType().getInput(1).isa(); if (!checkResult) { auto elementalGenerator = [&](const fir::ExtendedValue &element) { createIoRuntimeCallForItem(converter, loc, inputFunc, cookie, @@ -911,10 +911,9 @@ static void genInputItemList(Fortran::lower::AbstractConverter &converter, mlir::Type itemTy = converter.genType(*expr); mlir::func::FuncOp inputFunc = getInputFunc(loc, builder, itemTy, isFormatted); - auto itemExv = - mlir::isa(inputFunc.getFunctionType().getInput(1)) - ? converter.genExprBox(loc, *expr, stmtCtx) - : converter.genExprAddr(loc, expr, stmtCtx); + auto itemExv = inputFunc.getFunctionType().getInput(1).isa() + ? converter.genExprBox(loc, *expr, stmtCtx) + : converter.genExprAddr(loc, expr, stmtCtx); ok = createIoRuntimeCallForItem(converter, loc, inputFunc, cookie, itemExv); } } @@ -1773,8 +1772,8 @@ static mlir::Value genIOUnitNumber(Fortran::lower::AbstractConverter &converter, auto &builder = converter.getFirOpBuilder(); auto rawUnit = fir::getBase(converter.genExprValue(loc, iounit, stmtCtx)); unsigned rawUnitWidth = - mlir::cast(rawUnit.getType()).getWidth(); - unsigned runtimeArgWidth = mlir::cast(ty).getWidth(); + rawUnit.getType().cast().getWidth(); + unsigned runtimeArgWidth = ty.cast().getWidth(); // The IO runtime supports `int` unit numbers, if the unit number may // overflow when passed to the IO runtime, check that the unit number is // in range before calling the BeginXXX. @@ -2332,7 +2331,7 @@ mlir::Value genInquireSpec( if (!eleTy) fir::emitFatalError(loc, "internal error: expected a memory reference type"); - auto width = mlir::cast(eleTy).getWidth(); + auto width = eleTy.cast().getWidth(); mlir::IndexType idxTy = builder.getIndexType(); mlir::Value kind = builder.createIntegerConstant(loc, idxTy, width / 8); llvm::SmallVector args = { diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index eae2afc760e6..b56bdedc07bf 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -65,7 +65,7 @@ static Op createDataEntryOp(fir::FirOpBuilder &builder, mlir::Location loc, mlir::acc::DataClause dataClause, mlir::Type retTy, mlir::Value isPresent = {}) { mlir::Value varPtrPtr; - if (auto boxTy = mlir::dyn_cast(baseAddr.getType())) { + if (auto boxTy = baseAddr.getType().dyn_cast()) { if (isPresent) { mlir::Type ifRetTy = boxTy.getEleTy(); if (!fir::isa_ref_type(ifRetTy)) @@ -2658,7 +2658,7 @@ genACCHostDataOp(Fortran::lower::AbstractConverter &converter, if (ifCond) { if (auto cst = mlir::dyn_cast(ifCond.getDefiningOp())) - if (auto boolAttr = mlir::dyn_cast(cst.getValue())) { + if (auto boolAttr = cst.getValue().dyn_cast()) { if (boolAttr.getValue()) { // get rid of the if condition if it is always true. ifCond = mlir::Value(); diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 79525d6dfe7a..4c51b61f6bf0 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -23,10 +23,10 @@ namespace omp { /// Check for unsupported map operand types. static void checkMapType(mlir::Location location, mlir::Type type) { - if (auto refType = mlir::dyn_cast(type)) + if (auto refType = type.dyn_cast()) type = refType.getElementType(); - if (auto boxType = mlir::dyn_cast_or_null(type)) - if (!mlir::isa(boxType.getElementType())) + if (auto boxType = type.dyn_cast_or_null()) + if (!boxType.getElementType().isa()) TODO(location, "OMPD_target_data MapOperand BoxType"); } @@ -814,7 +814,7 @@ createMapInfoOp(fir::FirOpBuilder &builder, mlir::Location loc, llvm::ArrayRef members, uint64_t mapType, mlir::omp::VariableCaptureKind mapCaptureType, mlir::Type retTy, bool isVal) { - if (auto boxTy = mlir::dyn_cast(baseAddr.getType())) { + if (auto boxTy = baseAddr.getType().dyn_cast()) { baseAddr = builder.create(loc, baseAddr); retTy = baseAddr.getType(); } diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index 64ec5ae65c82..f454f5a45a51 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -84,7 +84,7 @@ static fir::GlobalOp globalInitialization( // Create default initialization for non-character scalar. if (Fortran::semantics::IsAllocatableOrObjectPointer(&sym)) { - mlir::Type baseAddrType = mlir::dyn_cast(ty).getEleTy(); + mlir::Type baseAddrType = ty.dyn_cast().getEleTy(); Fortran::lower::createGlobalInitialization( firOpBuilder, global, [&](fir::FirOpBuilder &b) { mlir::Value nullAddr = @@ -778,7 +778,7 @@ static void genBodyOfTargetDataOp( for (auto [argIndex, argSymbol] : llvm::enumerate(useDeviceSymbols)) { const mlir::BlockArgument &arg = region.front().getArgument(argIndex); fir::ExtendedValue extVal = converter.getSymbolExtendedValue(*argSymbol); - if (auto refType = mlir::dyn_cast(arg.getType())) { + if (auto refType = arg.getType().dyn_cast()) { if (fir::isa_builtin_cptr_type(refType.getElementType())) { converter.bindSymbol(*argSymbol, arg); } else { @@ -1570,15 +1570,13 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::AddrAndBoundsInfo info = getDataOperandBaseAddr( converter, firOpBuilder, sym, converter.getCurrentLocation()); - if (mlir::isa( - fir::unwrapRefType(info.addr.getType()))) + if (fir::unwrapRefType(info.addr.getType()).isa()) bounds = Fortran::lower::genBoundsOpsFromBox( firOpBuilder, converter.getCurrentLocation(), converter, dataExv, info); - if (mlir::isa( - fir::unwrapRefType(info.addr.getType()))) { + if (fir::unwrapRefType(info.addr.getType()).isa()) { bool dataExvIsAssumedSize = Fortran::semantics::IsAssumedSizeArray(sym.GetUltimate()); bounds = Fortran::lower::genBaseBoundsOps(baseOp.getType())) + if (auto refType = baseOp.getType().dyn_cast()) eleType = refType.getElementType(); // If a variable is specified in declare target link and if device diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp index 38edd1b46821..895340549f7c 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp @@ -138,7 +138,7 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, TODO(loc, "Reduction of some types is not supported"); switch (redId) { case ReductionIdentifier::MAX: { - if (auto ty = mlir::dyn_cast(type)) { + if (auto ty = type.dyn_cast()) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, type, llvm::APFloat::getLargest(sem, /*Negative=*/true)); @@ -148,7 +148,7 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, return builder.createIntegerConstant(loc, type, minInt); } case ReductionIdentifier::MIN: { - if (auto ty = mlir::dyn_cast(type)) { + if (auto ty = type.dyn_cast()) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, type, llvm::APFloat::getLargest(sem, /*Negative=*/false)); @@ -188,12 +188,12 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, return fir::factory::Complex{builder, loc}.createComplex(type, initRe, initIm); } - if (mlir::isa(type)) + if (type.isa()) return builder.create( loc, type, builder.getFloatAttr(type, (double)getOperationIdentity(redId, loc))); - if (mlir::isa(type)) { + if (type.isa()) { mlir::Value intConst = builder.create( loc, builder.getI1Type(), builder.getIntegerAttr(builder.getI1Type(), @@ -474,11 +474,11 @@ createReductionCleanupRegion(fir::FirOpBuilder &builder, mlir::Location loc, // like fir::unwrapSeqOrBoxedSeqType except it also works for non-sequence boxes static mlir::Type unwrapSeqOrBoxedType(mlir::Type ty) { - if (auto seqTy = mlir::dyn_cast(ty)) + if (auto seqTy = ty.dyn_cast()) return seqTy.getEleTy(); - if (auto boxTy = mlir::dyn_cast(ty)) { + if (auto boxTy = ty.dyn_cast()) { auto eleTy = fir::unwrapRefType(boxTy.getEleTy()); - if (auto seqTy = mlir::dyn_cast(eleTy)) + if (auto seqTy = eleTy.dyn_cast()) return seqTy.getEleTy(); return eleTy; } @@ -790,7 +790,7 @@ void ReductionProcessor::addDeclareReduction( for (mlir::Value symVal : reductionVars) { auto redType = mlir::cast(symVal.getType()); const auto &kindMap = firOpBuilder.getKindMap(); - if (mlir::isa(redType.getEleTy())) + if (redType.getEleTy().isa()) decl = createDeclareReduction(firOpBuilder, getReductionName(intrinsicOp, kindMap, firOpBuilder.getI1Type(), @@ -816,7 +816,7 @@ void ReductionProcessor::addDeclareReduction( mlir::Value symVal = converter.getSymbolAddress(*symbol); if (auto declOp = symVal.getDefiningOp()) symVal = declOp.getBase(); - auto redType = mlir::cast(symVal.getType()); + auto redType = symVal.getType().cast(); if (!redType.getEleTy().isIntOrIndexOrFloat()) TODO(currentLocation, "User Defined Reduction on non-trivial type"); decl = createDeclareReduction( diff --git a/flang/lib/Lower/VectorSubscripts.cpp b/flang/lib/Lower/VectorSubscripts.cpp index d7a311d32d59..7439b9f7df8f 100644 --- a/flang/lib/Lower/VectorSubscripts.cpp +++ b/flang/lib/Lower/VectorSubscripts.cpp @@ -105,7 +105,7 @@ private: } mlir::Type gen(const Fortran::evaluate::Component &component) { - auto recTy = mlir::cast(gen(component.base())); + auto recTy = gen(component.base()).cast(); const Fortran::semantics::Symbol &componentSymbol = component.GetLastSymbol(); // Parent components will not be found here, they are not part diff --git a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp index f723e8f66e3e..c403b9effbfa 100644 --- a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp +++ b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp @@ -68,7 +68,7 @@ bool AliasAnalysis::Source::isPointerReference(mlir::Type ty) { if (!eleTy) return false; - return fir::isPointerType(eleTy) || mlir::isa(eleTy); + return fir::isPointerType(eleTy) || eleTy.isa(); } bool AliasAnalysis::Source::isTargetOrPointer() const { @@ -81,7 +81,7 @@ bool AliasAnalysis::Source::isRecordWithPointerComponent() const { if (!eleTy) return false; // TO DO: Look for pointer components - return mlir::isa(eleTy); + return eleTy.isa(); } AliasResult AliasAnalysis::alias(Value lhs, Value rhs) { diff --git a/flang/lib/Optimizer/Builder/BoxValue.cpp b/flang/lib/Optimizer/Builder/BoxValue.cpp index a90ce5570de7..361fa59e2040 100644 --- a/flang/lib/Optimizer/Builder/BoxValue.cpp +++ b/flang/lib/Optimizer/Builder/BoxValue.cpp @@ -191,7 +191,7 @@ bool fir::MutableBoxValue::verify() const { mlir::Type type = fir::dyn_cast_ptrEleTy(getAddr().getType()); if (!type) return false; - auto box = mlir::dyn_cast(type); + auto box = type.dyn_cast(); if (!box) return false; // A boxed value always takes a memory reference, @@ -210,7 +210,7 @@ bool fir::MutableBoxValue::verify() const { /// Debug verifier for BoxValue ctor. There is no guarantee this will /// always be called. bool fir::BoxValue::verify() const { - if (!mlir::isa(addr.getType())) + if (!addr.getType().isa()) return false; if (!lbounds.empty() && lbounds.size() != rank()) return false; diff --git a/flang/lib/Optimizer/Builder/Character.cpp b/flang/lib/Optimizer/Builder/Character.cpp index b7a7453efdb3..af0786809cc2 100644 --- a/flang/lib/Optimizer/Builder/Character.cpp +++ b/flang/lib/Optimizer/Builder/Character.cpp @@ -26,11 +26,11 @@ /// Unwrap all the ref and box types and return the inner element type. static mlir::Type unwrapBoxAndRef(mlir::Type type) { - if (auto boxType = mlir::dyn_cast(type)) + if (auto boxType = type.dyn_cast()) return boxType.getEleTy(); while (true) { type = fir::unwrapRefType(type); - if (auto boxTy = mlir::dyn_cast(type)) + if (auto boxTy = type.dyn_cast()) type = boxTy.getEleTy(); else break; @@ -41,19 +41,19 @@ static mlir::Type unwrapBoxAndRef(mlir::Type type) { /// Unwrap base fir.char type. static fir::CharacterType recoverCharacterType(mlir::Type type) { type = fir::unwrapSequenceType(unwrapBoxAndRef(type)); - if (auto charTy = mlir::dyn_cast(type)) + if (auto charTy = type.dyn_cast()) return charTy; llvm::report_fatal_error("expected a character type"); } bool fir::factory::CharacterExprHelper::isCharacterScalar(mlir::Type type) { type = unwrapBoxAndRef(type); - return !mlir::isa(type) && fir::isa_char(type); + return !type.isa() && fir::isa_char(type); } bool fir::factory::CharacterExprHelper::isArray(mlir::Type type) { type = unwrapBoxAndRef(type); - if (auto seqTy = mlir::dyn_cast(type)) + if (auto seqTy = type.dyn_cast()) return fir::isa_char(seqTy.getEleTy()); return false; } @@ -92,8 +92,7 @@ getCompileTimeLength(const fir::CharBoxValue &box) { /// Detect the precondition that the value `str` does not reside in memory. Such /// values will have a type `!fir.array<...x!fir.char>` or `!fir.char`. LLVM_ATTRIBUTE_UNUSED static bool needToMaterialize(mlir::Value str) { - return mlir::isa(str.getType()) || - fir::isa_char(str.getType()); + return str.getType().isa() || fir::isa_char(str.getType()); } /// This is called only if `str` does not reside in memory. Such a bare string @@ -104,7 +103,7 @@ fir::factory::CharacterExprHelper::materializeValue(mlir::Value str) { assert(needToMaterialize(str)); auto ty = str.getType(); assert(isCharacterScalar(ty) && "expected scalar character"); - auto charTy = mlir::dyn_cast(ty); + auto charTy = ty.dyn_cast(); if (!charTy || charTy.getLen() == fir::CharacterType::unknownLen()) { LLVM_DEBUG(llvm::dbgs() << "cannot materialize: " << str << '\n'); llvm_unreachable("must be a !fir.char type"); @@ -130,7 +129,7 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, if (auto eleType = fir::dyn_cast_ptrEleTy(type)) type = eleType; - if (auto arrayType = mlir::dyn_cast(type)) { + if (auto arrayType = type.dyn_cast()) { type = arrayType.getEleTy(); auto indexType = builder.getIndexType(); for (auto extent : arrayType.getShape()) { @@ -146,10 +145,10 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, mlir::emitError(loc, "cannot retrieve array extents from type"); } - if (auto charTy = mlir::dyn_cast(type)) { + if (auto charTy = type.dyn_cast()) { if (!resultLen && charTy.getLen() != fir::CharacterType::unknownLen()) resultLen = builder.createIntegerConstant(loc, lenType, charTy.getLen()); - } else if (auto boxCharType = mlir::dyn_cast(type)) { + } else if (auto boxCharType = type.dyn_cast()) { auto refType = builder.getRefType(boxCharType.getEleTy()); // If the embox is accessible, use its operand to avoid filling // the generated fir with embox/unbox. @@ -169,7 +168,7 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, if (!resultLen) { resultLen = boxCharLen; } - } else if (mlir::isa(type)) { + } else if (type.isa()) { mlir::emitError(loc, "descriptor or derived type not yet handled"); } else { llvm_unreachable("Cannot translate mlir::Value to character ExtendedValue"); @@ -222,7 +221,7 @@ fir::factory::CharacterExprHelper::createEmbox(const fir::CharBoxValue &box) { fir::CharBoxValue fir::factory::CharacterExprHelper::toScalarCharacter( const fir::CharArrayBoxValue &box) { - if (mlir::isa(box.getBuffer().getType())) + if (box.getBuffer().getType().isa()) TODO(loc, "concatenating non contiguous character array into a scalar"); // TODO: add a fast path multiplying new length at compile time if the info is @@ -656,7 +655,7 @@ fir::factory::CharacterExprHelper::createUnboxChar(mlir::Value boxChar) { } bool fir::factory::CharacterExprHelper::isCharacterLiteral(mlir::Type type) { - if (auto seqType = mlir::dyn_cast(type)) + if (auto seqType = type.dyn_cast()) return (seqType.getShape().size() == 1) && fir::isa_char(seqType.getEleTy()); return false; @@ -729,9 +728,9 @@ mlir::Value fir::factory::CharacterExprHelper::getLength(mlir::Value memref) { if (charType.hasConstantLen()) return builder.createIntegerConstant(loc, builder.getCharacterLengthType(), charType.getLen()); - if (mlir::isa(memrefType)) + if (memrefType.isa()) return readLengthFromBox(memref); - if (mlir::isa(memrefType)) + if (memrefType.isa()) return createUnboxChar(memref).second; // Length cannot be deduced from memref. @@ -743,14 +742,14 @@ fir::factory::extractCharacterProcedureTuple(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value tuple, bool openBoxProc) { - mlir::TupleType tupleType = mlir::cast(tuple.getType()); + mlir::TupleType tupleType = tuple.getType().cast(); mlir::Value addr = builder.create( loc, tupleType.getType(0), tuple, builder.getArrayAttr( {builder.getIntegerAttr(builder.getIndexType(), 0)})); mlir::Value proc = [&]() -> mlir::Value { if (openBoxProc) - if (auto addrTy = mlir::dyn_cast(addr.getType())) + if (auto addrTy = addr.getType().dyn_cast()) return builder.create(loc, addrTy.getEleTy(), addr); return addr; }(); @@ -764,7 +763,7 @@ fir::factory::extractCharacterProcedureTuple(fir::FirOpBuilder &builder, mlir::Value fir::factory::createCharacterProcedureTuple( fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type argTy, mlir::Value addr, mlir::Value len) { - mlir::TupleType tupleType = mlir::cast(argTy); + mlir::TupleType tupleType = argTy.cast(); addr = builder.createConvert(loc, tupleType.getType(0), addr); if (len) len = builder.createConvert(loc, tupleType.getType(1), len); @@ -867,7 +866,7 @@ fir::factory::convertCharacterKind(fir::FirOpBuilder &builder, auto kindMap = builder.getKindMap(); mlir::Value boxCharAddr = srcBoxChar.getAddr(); auto fromTy = boxCharAddr.getType(); - if (auto charTy = mlir::dyn_cast(fromTy)) { + if (auto charTy = fromTy.dyn_cast()) { // boxchar is a value, not a variable. Turn it into a temporary. // As a value, it ought to have a constant LEN value. assert(charTy.hasConstantLen() && "must have constant length"); @@ -876,7 +875,7 @@ fir::factory::convertCharacterKind(fir::FirOpBuilder &builder, boxCharAddr = tmp; } auto fromBits = kindMap.getCharacterBitsize( - mlir::cast(fir::unwrapRefType(fromTy)).getFKind()); + fir::unwrapRefType(fromTy).cast().getFKind()); auto toBits = kindMap.getCharacterBitsize(toKind); if (toBits < fromBits) { // Scale by relative ratio to give a buffer of the same length. diff --git a/flang/lib/Optimizer/Builder/Complex.cpp b/flang/lib/Optimizer/Builder/Complex.cpp index cbcd4f850014..e97cb3067808 100644 --- a/flang/lib/Optimizer/Builder/Complex.cpp +++ b/flang/lib/Optimizer/Builder/Complex.cpp @@ -14,8 +14,7 @@ mlir::Type fir::factory::Complex::getComplexPartType(mlir::Type complexType) const { - return builder.getRealType( - mlir::cast(complexType).getFKind()); + return builder.getRealType(complexType.cast().getFKind()); } mlir::Type fir::factory::Complex::getComplexPartType(mlir::Value cplx) const { diff --git a/flang/lib/Optimizer/Builder/FIRBuilder.cpp b/flang/lib/Optimizer/Builder/FIRBuilder.cpp index a6da38763726..a0fbae5b614c 100644 --- a/flang/lib/Optimizer/Builder/FIRBuilder.cpp +++ b/flang/lib/Optimizer/Builder/FIRBuilder.cpp @@ -90,7 +90,7 @@ fir::FirOpBuilder::getNamedGlobal(mlir::ModuleOp modOp, } mlir::Type fir::FirOpBuilder::getRefType(mlir::Type eleTy) { - assert(!mlir::isa(eleTy) && "cannot be a reference type"); + assert(!eleTy.isa() && "cannot be a reference type"); return fir::ReferenceType::get(eleTy); } @@ -147,7 +147,7 @@ mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, llvm::APFloat::integerPart val) { auto apf = [&]() -> llvm::APFloat { - if (auto ty = mlir::dyn_cast(fltTy)) + if (auto ty = fltTy.dyn_cast()) return llvm::APFloat(kindMap.getFloatSemantics(ty.getFKind()), val); if (fltTy.isF16()) return llvm::APFloat(llvm::APFloat::IEEEhalf(), val); @@ -169,7 +169,7 @@ fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, const llvm::APFloat &value) { - if (mlir::isa(fltTy)) { + if (fltTy.isa()) { auto attr = getFloatAttr(fltTy, value); return create(loc, fltTy, attr); } @@ -178,7 +178,7 @@ mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, static llvm::SmallVector elideExtentsAlreadyInType(mlir::Type type, mlir::ValueRange shape) { - auto arrTy = mlir::dyn_cast(type); + auto arrTy = type.dyn_cast(); if (shape.empty() || !arrTy) return {}; // elide the constant dimensions before construction @@ -195,7 +195,7 @@ static llvm::SmallVector elideLengthsAlreadyInType(mlir::Type type, mlir::ValueRange lenParams) { if (lenParams.empty()) return {}; - if (auto arrTy = mlir::dyn_cast(type)) + if (auto arrTy = type.dyn_cast()) type = arrTy.getEleTy(); if (fir::hasDynamicSize(type)) return lenParams; @@ -264,7 +264,7 @@ mlir::Value fir::FirOpBuilder::createTemporaryAlloc( mlir::Location loc, mlir::Type type, llvm::StringRef name, mlir::ValueRange lenParams, mlir::ValueRange shape, llvm::ArrayRef attrs) { - assert(!mlir::isa(type) && "cannot be a reference"); + assert(!type.isa() && "cannot be a reference"); // If the alloca is inside an OpenMP Op which will be outlined then pin // the alloca here. const bool pinned = @@ -310,7 +310,7 @@ mlir::Value fir::FirOpBuilder::createHeapTemporary( llvm::SmallVector dynamicLength = elideLengthsAlreadyInType(type, lenParams); - assert(!mlir::isa(type) && "cannot be a reference"); + assert(!type.isa() && "cannot be a reference"); return create(loc, type, /*unique_name=*/llvm::StringRef{}, name, dynamicLength, dynamicShape, attrs); } @@ -376,9 +376,8 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( // imaginary part is zero auto eleTy = helper.getComplexPartType(toTy); auto cast = createConvert(loc, eleTy, val); - llvm::APFloat zero{kindMap.getFloatSemantics( - mlir::cast(toTy).getFKind()), - 0}; + llvm::APFloat zero{ + kindMap.getFloatSemantics(toTy.cast().getFKind()), 0}; auto imag = createRealConstant(loc, eleTy, zero); return helper.createComplex(toTy, cast, imag); } @@ -389,14 +388,14 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( return createConvert(loc, toTy, rp); } if (allowCharacterConversion) { - if (mlir::isa(fromTy)) { + if (fromTy.isa()) { // Extract the address of the character string and pass it fir::factory::CharacterExprHelper charHelper{*this, loc}; std::pair unboxchar = charHelper.createUnboxChar(val); return createConvert(loc, toTy, unboxchar.first); } - if (auto boxType = mlir::dyn_cast(toTy)) { + if (auto boxType = toTy.dyn_cast()) { // Extract the address of the actual argument and create a boxed // character value with an undefined length // TODO: We should really calculate the total size of the actual @@ -416,10 +415,10 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( "element types expected to match")); return create(loc, toTy, val); } - if (fir::isa_ref_type(fromTy) && mlir::isa(toTy)) { + if (fir::isa_ref_type(fromTy) && toTy.isa()) { // Call is expecting a boxed procedure, not a reference to other data type. // Convert the reference to a procedure and embox it. - mlir::Type procTy = mlir::cast(toTy).getEleTy(); + mlir::Type procTy = toTy.cast().getEleTy(); mlir::Value proc = createConvert(loc, procTy, val); return create(loc, toTy, proc); } @@ -429,7 +428,7 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( if (((fir::isPolymorphicType(fromTy) && (fir::isAllocatableType(fromTy) || fir::isPointerType(fromTy)) && fir::isPolymorphicType(toTy)) || - (fir::isPolymorphicType(fromTy) && mlir::isa(toTy))) && + (fir::isPolymorphicType(fromTy) && toTy.isa())) && !(fir::isUnlimitedPolymorphicType(fromTy) && fir::isAssumedType(toTy))) return create(loc, toTy, val, mlir::Value{}, /*slice=*/mlir::Value{}); @@ -582,7 +581,7 @@ mlir::Value fir::FirOpBuilder::createBox(mlir::Location loc, bool isPolymorphic, bool isAssumedType) { mlir::Value itemAddr = fir::getBase(exv); - if (mlir::isa(itemAddr.getType())) + if (itemAddr.getType().isa()) return itemAddr; auto elementType = fir::dyn_cast_ptrEleTy(itemAddr.getType()); if (!elementType) { @@ -593,7 +592,7 @@ mlir::Value fir::FirOpBuilder::createBox(mlir::Location loc, mlir::Type boxTy; mlir::Value tdesc; // Avoid to wrap a box/class with box/class. - if (mlir::isa(elementType)) { + if (elementType.isa()) { boxTy = elementType; } else { boxTy = fir::BoxType::get(elementType); @@ -710,7 +709,7 @@ mlir::Value fir::FirOpBuilder::genAbsentOp(mlir::Location loc, return create(loc, argTy); auto boxProc = - create(loc, mlir::cast(argTy).getType(0)); + create(loc, argTy.cast().getType(0)); mlir::Value charLen = create(loc, getCharacterLengthType()); return fir::factory::createCharacterProcedureTuple(*this, loc, argTy, boxProc, charLen); @@ -959,14 +958,14 @@ static llvm::SmallVector getFromBox(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type valTy, mlir::Value boxVal) { - if (auto boxTy = mlir::dyn_cast(valTy)) { + if (auto boxTy = valTy.dyn_cast()) { auto eleTy = fir::unwrapAllRefAndSeqType(boxTy.getEleTy()); - if (auto recTy = mlir::dyn_cast(eleTy)) { + if (auto recTy = eleTy.dyn_cast()) { if (recTy.getNumLenParams() > 0) { // Walk each type parameter in the record and get the value. TODO(loc, "generate code to get LEN type parameters"); } - } else if (auto charTy = mlir::dyn_cast(eleTy)) { + } else if (auto charTy = eleTy.dyn_cast()) { if (charTy.hasDynamicLen()) { auto idxTy = builder.getIndexType(); auto eleSz = builder.create(loc, idxTy, boxVal); @@ -1013,7 +1012,7 @@ llvm::SmallVector fir::factory::getTypeParams(mlir::Location loc, fir::FirOpBuilder &builder, fir::ArrayLoadOp load) { mlir::Type memTy = load.getMemref().getType(); - if (auto boxTy = mlir::dyn_cast(memTy)) + if (auto boxTy = memTy.dyn_cast()) return getFromBox(loc, builder, boxTy, load.getMemref()); return load.getTypeparams(); } @@ -1040,7 +1039,7 @@ std::string fir::factory::uniqueCGIdent(llvm::StringRef prefix, mlir::Value fir::factory::locationToFilename(fir::FirOpBuilder &builder, mlir::Location loc) { - if (auto flc = mlir::dyn_cast(loc)) { + if (auto flc = loc.dyn_cast()) { // must be encoded as asciiz, C string auto fn = flc.getFilename().str() + '\0'; return fir::getBase(createStringLiteral(builder, loc, fn)); @@ -1051,7 +1050,7 @@ mlir::Value fir::factory::locationToFilename(fir::FirOpBuilder &builder, mlir::Value fir::factory::locationToLineNo(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type type) { - if (auto flc = mlir::dyn_cast(loc)) + if (auto flc = loc.dyn_cast()) return builder.createIntegerConstant(loc, type, flc.getLine()); return builder.createIntegerConstant(loc, type, 0); } @@ -1109,10 +1108,10 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( auto fieldTy = component.getType(); if (auto ty = fir::dyn_cast_ptrEleTy(fieldTy)) fieldTy = ty; - if (mlir::isa(fieldTy)) { + if (fieldTy.isa()) { llvm::SmallVector nonDeferredTypeParams; auto eleTy = fir::unwrapSequenceType(fir::dyn_cast_ptrOrBoxEleTy(fieldTy)); - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { auto lenTy = builder.getCharacterLengthType(); if (charTy.hasConstantLen()) nonDeferredTypeParams.emplace_back( @@ -1121,7 +1120,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( // on a PDT length parameter. There is no way to make a difference with // deferred length here yet. } - if (auto recTy = mlir::dyn_cast(eleTy)) + if (auto recTy = eleTy.dyn_cast()) if (recTy.getNumLenParams() > 0) TODO(loc, "allocatable and pointer components non deferred length " "parameters"); @@ -1130,7 +1129,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( /*mutableProperties=*/{}); } llvm::SmallVector extents; - if (auto seqTy = mlir::dyn_cast(fieldTy)) { + if (auto seqTy = fieldTy.dyn_cast()) { fieldTy = seqTy.getEleTy(); auto idxTy = builder.getIndexType(); for (auto extent : seqTy.getShape()) { @@ -1139,7 +1138,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( extents.emplace_back(builder.createIntegerConstant(loc, idxTy, extent)); } } - if (auto charTy = mlir::dyn_cast(fieldTy)) { + if (auto charTy = fieldTy.dyn_cast()) { auto cstLen = charTy.getLen(); if (cstLen == fir::CharacterType::unknownLen()) TODO(loc, "get character component length from length type parameters"); @@ -1149,7 +1148,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( return fir::CharArrayBoxValue{component, len, extents}; return fir::CharBoxValue{component, len}; } - if (auto recordTy = mlir::dyn_cast(fieldTy)) + if (auto recordTy = fieldTy.dyn_cast()) if (recordTy.getNumLenParams() != 0) TODO(loc, "lower component ref that is a derived type with length parameter"); @@ -1212,14 +1211,14 @@ void fir::factory::genScalarAssignment(fir::FirOpBuilder &builder, assert(lhs.rank() == 0 && rhs.rank() == 0 && "must be scalars"); auto type = fir::unwrapSequenceType( fir::unwrapPassByRefType(fir::getBase(lhs).getType())); - if (mlir::isa(type)) { + if (type.isa()) { const fir::CharBoxValue *toChar = lhs.getCharBox(); const fir::CharBoxValue *fromChar = rhs.getCharBox(); assert(toChar && fromChar); fir::factory::CharacterExprHelper helper{builder, loc}; helper.createAssign(fir::ExtendedValue{*toChar}, fir::ExtendedValue{*fromChar}); - } else if (mlir::isa(type)) { + } else if (type.isa()) { fir::factory::genRecordAssignment(builder, loc, lhs, rhs, needFinalization, isTemporaryLHS); } else { @@ -1240,10 +1239,10 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, const fir::ExtendedValue &rhs, bool isTemporaryLHS) { auto lbaseType = fir::unwrapPassByRefType(fir::getBase(lhs).getType()); - auto lhsType = mlir::dyn_cast(lbaseType); + auto lhsType = lbaseType.dyn_cast(); assert(lhsType && "lhs must be a scalar record type"); auto rbaseType = fir::unwrapPassByRefType(fir::getBase(rhs).getType()); - auto rhsType = mlir::dyn_cast(rbaseType); + auto rhsType = rbaseType.dyn_cast(); assert(rhsType && "rhs must be a scalar record type"); auto fieldIndexType = fir::FieldType::get(lhsType.getContext()); for (auto [lhsPair, rhsPair] : @@ -1262,7 +1261,7 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, mlir::Value toCoor = builder.create( loc, fieldRefType, fir::getBase(lhs), field); std::optional outerLoop; - if (auto sequenceType = mlir::dyn_cast(lFieldTy)) { + if (auto sequenceType = lFieldTy.dyn_cast()) { // Create loops to assign array components elements by elements. // Note that, since these are components, they either do not overlap, // or are the same and exactly overlap. They also have compile time @@ -1289,9 +1288,10 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, fromCoor, indices); } if (auto fieldEleTy = fir::unwrapSequenceType(lFieldTy); - mlir::isa(fieldEleTy)) { - assert(mlir::isa( - mlir::cast(fieldEleTy).getEleTy()) && + fieldEleTy.isa()) { + assert(fieldEleTy.cast() + .getEleTy() + .isa() && "allocatable members require deep copy"); auto fromPointerValue = builder.create(loc, fromCoor); auto castTo = builder.createConvert(loc, fieldEleTy, fromPointerValue); @@ -1320,11 +1320,11 @@ static bool recordTypeCanBeMemCopied(fir::RecordType recordType) { for (auto [_, fieldType] : recordType.getTypeList()) { // Derived type component may have user assignment (so far, we cannot tell // in FIR, so assume it is always the case, TODO: get the actual info). - if (mlir::isa(fir::unwrapSequenceType(fieldType))) + if (fir::unwrapSequenceType(fieldType).isa()) return false; // Allocatable components need deep copy. - if (auto boxType = mlir::dyn_cast(fieldType)) - if (mlir::isa(boxType.getEleTy())) + if (auto boxType = fieldType.dyn_cast()) + if (boxType.getEleTy().isa()) return false; } // Constant size components without user defined assignment and pointers can @@ -1353,10 +1353,9 @@ void fir::factory::genRecordAssignment(fir::FirOpBuilder &builder, // Box operands may be polymorphic, it is not entirely clear from 10.2.1.3 // if the assignment is performed on the dynamic of declared type. Use the // runtime assuming it is performed on the dynamic type. - bool hasBoxOperands = - mlir::isa(fir::getBase(lhs).getType()) || - mlir::isa(fir::getBase(rhs).getType()); - auto recTy = mlir::dyn_cast(baseTy); + bool hasBoxOperands = fir::getBase(lhs).getType().isa() || + fir::getBase(rhs).getType().isa(); + auto recTy = baseTy.dyn_cast(); assert(recTy && "must be a record type"); if ((needFinalization && mayHaveFinalizer(recTy, builder)) || hasBoxOperands || !recordTypeCanBeMemCopied(recTy)) { @@ -1402,7 +1401,7 @@ mlir::Value fir::factory::genLenOfCharacter( llvm::ArrayRef path, llvm::ArrayRef substring) { llvm::SmallVector typeParams(arrLoad.getTypeparams()); return genLenOfCharacter(builder, loc, - mlir::cast(arrLoad.getType()), + arrLoad.getType().cast(), arrLoad.getMemref(), typeParams, path, substring); } @@ -1430,7 +1429,7 @@ mlir::Value fir::factory::genLenOfCharacter( lower = builder.createConvert(loc, idxTy, substring.front()); auto eleTy = fir::applyPathToType(seqTy, path); if (!fir::hasDynamicSize(eleTy)) { - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { // Use LEN from the type. return builder.createIntegerConstant(loc, idxTy, charTy.getLen()); } @@ -1439,9 +1438,9 @@ mlir::Value fir::factory::genLenOfCharacter( "application of path did not result in a !fir.char"); } if (fir::isa_box_type(memref.getType())) { - if (mlir::isa(memref.getType())) + if (memref.getType().isa()) return builder.create(loc, idxTy, memref); - if (mlir::isa(memref.getType())) + if (memref.getType().isa()) return CharacterExprHelper(builder, loc).readLengthFromBox(memref); fir::emitFatalError(loc, "memref has wrong type"); } @@ -1458,7 +1457,7 @@ mlir::Value fir::factory::genLenOfCharacter( mlir::Value fir::factory::createZeroValue(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type type) { mlir::Type i1 = builder.getIntegerType(1); - if (mlir::isa(type) || type == i1) + if (type.isa() || type == i1) return builder.createConvert(loc, type, builder.createBool(loc, false)); if (fir::isa_integer(type)) return builder.createIntegerConstant(loc, type, 0); @@ -1508,7 +1507,7 @@ mlir::Value fir::factory::genMaxWithZero(fir::FirOpBuilder &builder, mlir::Value zero = builder.createIntegerConstant(loc, value.getType(), 0); if (mlir::Operation *definingOp = value.getDefiningOp()) if (auto cst = mlir::dyn_cast(definingOp)) - if (auto intAttr = mlir::dyn_cast(cst.getValue())) + if (auto intAttr = cst.getValue().dyn_cast()) return intAttr.getInt() > 0 ? value : zero; mlir::Value valueIsGreater = builder.create( loc, mlir::arith::CmpIPredicate::sgt, value, zero); @@ -1520,8 +1519,8 @@ mlir::Value fir::factory::genCPtrOrCFunptrAddr(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value cPtr, mlir::Type ty) { - assert(mlir::isa(ty)); - auto recTy = mlir::dyn_cast(ty); + assert(ty.isa()); + auto recTy = ty.dyn_cast(); assert(recTy.getTypeList().size() == 1); auto fieldName = recTy.getTypeList()[0].first; mlir::Type fieldTy = recTy.getTypeList()[0].second; @@ -1583,7 +1582,7 @@ mlir::Value fir::factory::genCPtrOrCFunptrValue(fir::FirOpBuilder &builder, mlir::Value fir::factory::createNullBoxProc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type boxType) { - auto boxTy{mlir::dyn_cast(boxType)}; + auto boxTy{boxType.dyn_cast()}; if (!boxTy) fir::emitFatalError(loc, "Procedure pointer must be of BoxProcType"); auto boxEleTy{fir::unwrapRefType(boxTy.getEleTy())}; diff --git a/flang/lib/Optimizer/Builder/HLFIRTools.cpp b/flang/lib/Optimizer/Builder/HLFIRTools.cpp index 44779427ab55..db638ceb4070 100644 --- a/flang/lib/Optimizer/Builder/HLFIRTools.cpp +++ b/flang/lib/Optimizer/Builder/HLFIRTools.cpp @@ -38,10 +38,10 @@ hlfir::getExplicitExtentsFromShape(mlir::Value shape, } else if (mlir::dyn_cast_or_null(shapeOp)) { return {}; } else if (auto s = mlir::dyn_cast_or_null(shapeOp)) { - hlfir::ExprType expr = mlir::cast(s.getExpr().getType()); + hlfir::ExprType expr = s.getExpr().getType().cast(); llvm::ArrayRef exprShape = expr.getShape(); mlir::Type indexTy = builder.getIndexType(); - fir::ShapeType shapeTy = mlir::cast(shape.getType()); + fir::ShapeType shapeTy = shape.getType().cast(); result.reserve(shapeTy.getRank()); for (unsigned i = 0; i < shapeTy.getRank(); ++i) { int64_t extent = exprShape[i]; @@ -99,7 +99,7 @@ genLboundsAndExtentsFromBox(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity boxEntity, llvm::SmallVectorImpl &lbounds, llvm::SmallVectorImpl *extents) { - assert(mlir::isa(boxEntity.getType()) && "must be a box"); + assert(boxEntity.getType().isa() && "must be a box"); mlir::Type idxTy = builder.getIndexType(); const int rank = boxEntity.getRank(); for (int i = 0; i < rank; ++i) { @@ -154,7 +154,7 @@ static mlir::Value genCharacterVariableLength(mlir::Location loc, hlfir::Entity var) { if (mlir::Value len = tryGettingNonDeferredCharLen(var)) return len; - auto charType = mlir::cast(var.getFortranElementType()); + auto charType = var.getFortranElementType().cast(); if (charType.hasConstantLen()) return builder.createIntegerConstant(loc, builder.getIndexType(), charType.getLen()); @@ -172,7 +172,7 @@ static fir::CharBoxValue genUnboxChar(mlir::Location loc, if (auto emboxChar = boxChar.getDefiningOp()) return {emboxChar.getMemref(), emboxChar.getLen()}; mlir::Type refType = fir::ReferenceType::get( - mlir::cast(boxChar.getType()).getEleTy()); + boxChar.getType().cast().getEleTy()); auto unboxed = builder.create( loc, refType, builder.getIndexType(), boxChar); mlir::Value addr = unboxed.getResult(0); @@ -252,8 +252,8 @@ hlfir::genAssociateExpr(mlir::Location loc, fir::FirOpBuilder &builder, // and the other static). mlir::Type varEleTy = getFortranElementType(variableType); mlir::Type valueEleTy = getFortranElementType(value.getType()); - if (varEleTy != valueEleTy && !(mlir::isa(valueEleTy) && - mlir::isa(varEleTy))) { + if (varEleTy != valueEleTy && !(valueEleTy.isa() && + varEleTy.isa())) { assert(value.isScalar() && fir::isa_trivial(value.getType())); source = builder.createConvert(loc, fir::unwrapPassByRefType(variableType), value); @@ -278,9 +278,9 @@ mlir::Value hlfir::genVariableRawAddress(mlir::Location loc, if (var.isMutableBox()) baseAddr = builder.create(loc, baseAddr); // Get raw address. - if (mlir::isa(var.getType())) + if (var.getType().isa()) baseAddr = genUnboxChar(loc, builder, var.getBase()).getAddr(); - if (mlir::isa(baseAddr.getType())) + if (baseAddr.getType().isa()) baseAddr = builder.create(loc, baseAddr); return baseAddr; } @@ -289,13 +289,13 @@ mlir::Value hlfir::genVariableBoxChar(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity var) { assert(var.isVariable() && "only address of variables can be taken"); - if (mlir::isa(var.getType())) + if (var.getType().isa()) return var; mlir::Value addr = genVariableRawAddress(loc, builder, var); llvm::SmallVector lengths; genLengthParameters(loc, builder, var, lengths); assert(lengths.size() == 1); - auto charType = mlir::cast(var.getFortranElementType()); + auto charType = var.getFortranElementType().cast(); auto boxCharType = fir::BoxCharType::get(builder.getContext(), charType.getFKind()); auto scalarAddr = @@ -309,7 +309,7 @@ hlfir::Entity hlfir::genVariableBox(mlir::Location loc, hlfir::Entity var) { assert(var.isVariable() && "must be a variable"); var = hlfir::derefPointersAndAllocatables(loc, builder, var); - if (mlir::isa(var.getType())) + if (var.getType().isa()) return var; // Note: if the var is not a fir.box/fir.class at that point, it has default // lower bounds and is not polymorphic. @@ -317,11 +317,11 @@ hlfir::Entity hlfir::genVariableBox(mlir::Location loc, var.isArray() ? hlfir::genShape(loc, builder, var) : mlir::Value{}; llvm::SmallVector typeParams; auto maybeCharType = - mlir::dyn_cast(var.getFortranElementType()); + var.getFortranElementType().dyn_cast(); if (!maybeCharType || maybeCharType.hasDynamicLen()) hlfir::genLengthParameters(loc, builder, var, typeParams); mlir::Value addr = var.getBase(); - if (mlir::isa(var.getType())) + if (var.getType().isa()) addr = genVariableRawAddress(loc, builder, var); mlir::Type boxType = fir::BoxType::get(var.getElementOrSequenceType()); auto embox = @@ -348,7 +348,7 @@ hlfir::Entity hlfir::getElementAt(mlir::Location loc, return entity; llvm::SmallVector lenParams; genLengthParameters(loc, builder, entity, lenParams); - if (mlir::isa(entity.getType())) + if (entity.getType().isa()) return hlfir::Entity{builder.create( loc, entity, oneBasedIndices, lenParams)}; // Build hlfir.designate. The lower bounds may need to be added to @@ -394,7 +394,7 @@ static mlir::Value genUBound(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVector> hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, Entity entity) { - if (mlir::isa(entity.getType())) + if (entity.getType().isa()) TODO(loc, "bounds of expressions in hlfir"); auto [exv, cleanup] = translateToExtendedValue(loc, builder, entity); assert(!cleanup && "translation of entity should not yield cleanup"); @@ -415,8 +415,8 @@ hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVector> hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value shape) { - assert((mlir::isa(shape.getType()) || - mlir::isa(shape.getType())) && + assert((shape.getType().isa() || + shape.getType().isa()) && "shape must contain extents"); auto extents = hlfir::getExplicitExtentsFromShape(shape, builder); auto lowers = getExplicitLboundsFromShape(shape); @@ -474,7 +474,7 @@ static mlir::Value computeVariableExtent(mlir::Location loc, if (typeExtent != fir::SequenceType::getUnknownExtent()) return builder.createIntegerConstant(loc, idxTy, typeExtent); } - assert(mlir::isa(variable.getType()) && + assert(variable.getType().isa() && "array variable with dynamic extent must be boxed"); mlir::Value dimVal = builder.createIntegerConstant(loc, idxTy, dim); auto dimInfo = builder.create(loc, idxTy, idxTy, idxTy, @@ -496,8 +496,9 @@ llvm::SmallVector getVariableExtents(mlir::Location loc, variable = hlfir::derefPointersAndAllocatables(loc, builder, variable); // Use the type shape information, and/or the fir.box/fir.class shape // information if any extents are not static. - fir::SequenceType seqTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(variable.getType())); + fir::SequenceType seqTy = + hlfir::getFortranElementOrSequenceType(variable.getType()) + .cast(); unsigned rank = seqTy.getShape().size(); for (unsigned dim = 0; dim < rank; ++dim) extents.push_back( @@ -506,7 +507,7 @@ llvm::SmallVector getVariableExtents(mlir::Location loc, } static mlir::Value tryRetrievingShapeOrShift(hlfir::Entity entity) { - if (mlir::isa(entity.getType())) { + if (entity.getType().isa()) { if (auto elemental = entity.getDefiningOp()) return elemental.getShape(); return mlir::Value{}; @@ -522,13 +523,13 @@ mlir::Value hlfir::genShape(mlir::Location loc, fir::FirOpBuilder &builder, entity = followShapeInducingSource(entity); assert(entity && "what?"); if (auto shape = tryRetrievingShapeOrShift(entity)) { - if (mlir::isa(shape.getType())) + if (shape.getType().isa()) return shape; - if (mlir::isa(shape.getType())) + if (shape.getType().isa()) if (auto s = shape.getDefiningOp()) return builder.create(loc, s.getExtents()); } - if (mlir::isa(entity.getType())) + if (entity.getType().isa()) return builder.create(loc, entity.getBase()); // There is no shape lying around for this entity. Retrieve the extents and // build a new fir.shape. @@ -562,8 +563,9 @@ mlir::Value hlfir::genExtent(mlir::Location loc, fir::FirOpBuilder &builder, entity = hlfir::derefPointersAndAllocatables(loc, builder, entity); // Use the type shape information, and/or the fir.box/fir.class shape // information if any extents are not static. - fir::SequenceType seqTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(entity.getType())); + fir::SequenceType seqTy = + hlfir::getFortranElementOrSequenceType(entity.getType()) + .cast(); return computeVariableExtent(loc, builder, entity, seqTy, dim); } TODO(loc, "get extent from HLFIR expr without producer holding the shape"); @@ -582,7 +584,7 @@ mlir::Value hlfir::genLBound(mlir::Location loc, fir::FirOpBuilder &builder, } if (entity.isMutableBox()) entity = hlfir::derefPointersAndAllocatables(loc, builder, entity); - assert(mlir::isa(entity.getType()) && "must be a box"); + assert(entity.getType().isa() && "must be a box"); mlir::Type idxTy = builder.getIndexType(); mlir::Value dimVal = builder.createIntegerConstant(loc, idxTy, dim); auto dimInfo = @@ -595,7 +597,7 @@ void hlfir::genLengthParameters(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVectorImpl &result) { if (!entity.hasLengthParameters()) return; - if (mlir::isa(entity.getType())) { + if (entity.getType().isa()) { mlir::Value expr = entity; if (auto reassoc = expr.getDefiningOp()) expr = reassoc.getVal(); @@ -652,8 +654,8 @@ static mlir::Value asEmboxShape(mlir::Location loc, fir::FirOpBuilder &builder, // fir.shape_shift) since this information is already in the input fir.box, // it only accepts fir.shift because local lower bounds may not be reflected // in the fir.box. - if (mlir::isa(fir::getBase(exv).getType()) && - !mlir::isa(shape.getType())) + if (fir::getBase(exv).getType().isa() && + !shape.getType().isa()) return builder.createShape(loc, exv); return shape; } @@ -684,7 +686,7 @@ hlfir::Entity hlfir::derefPointersAndAllocatables(mlir::Location loc, if (!entity.isPolymorphic() && !entity.hasLengthParameters()) return hlfir::Entity{builder.create(loc, boxLoad)}; mlir::Type elementType = boxLoad.getFortranElementType(); - if (auto charType = mlir::dyn_cast(elementType)) { + if (auto charType = elementType.dyn_cast()) { mlir::Value base = builder.create(loc, boxLoad); if (charType.hasConstantLen()) return hlfir::Entity{base}; @@ -714,7 +716,7 @@ mlir::Type hlfir::getVariableElementType(hlfir::Entity variable) { mlir::Type eleTy = variable.getFortranElementType(); if (variable.isPolymorphic()) return fir::ClassType::get(eleTy); - if (auto charType = mlir::dyn_cast(eleTy)) { + if (auto charType = eleTy.dyn_cast()) { if (charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); } else if (fir::isRecordWithTypeParameters(eleTy)) { @@ -735,7 +737,7 @@ mlir::Type hlfir::getEntityElementType(hlfir::Entity entity) { static hlfir::ExprType getArrayExprType(mlir::Type elementType, mlir::Value shape, bool isPolymorphic) { - unsigned rank = mlir::cast(shape.getType()).getRank(); + unsigned rank = shape.getType().cast().getRank(); hlfir::ExprType::Shape typeShape(rank, hlfir::ExprType::getUnknownExtent()); if (auto shapeOp = shape.getDefiningOp()) for (auto extent : llvm::enumerate(shapeOp.getExtents())) @@ -857,7 +859,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, return fir::MutableBoxValue(base, getExplicitTypeParams(variable), fir::MutableProperties{}); - if (mlir::isa(base.getType())) { + if (base.getType().isa()) { if (!variable.isSimplyContiguous() || variable.isPolymorphic() || variable.isDerivedWithLengthParameters() || variable.isOptional()) { llvm::SmallVector nonDefaultLbounds = @@ -872,7 +874,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, if (variable.isScalar()) { if (variable.isCharacter()) { - if (mlir::isa(base.getType())) + if (base.getType().isa()) return genUnboxChar(loc, builder, base); mlir::Value len = genCharacterVariableLength(loc, builder, variable); return fir::CharBoxValue{base, len}; @@ -881,7 +883,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, } llvm::SmallVector extents; llvm::SmallVector nonDefaultLbounds; - if (mlir::isa(variable.getType()) && + if (variable.getType().isa() && !variable.getIfVariableInterface()) { // This special case avoids generating two sets of identical // fir.box_dim to get both the lower bounds and extents. @@ -921,7 +923,7 @@ hlfir::translateToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, return {static_cast(entity), std::nullopt}; } - if (mlir::isa(entity.getType())) { + if (entity.getType().isa()) { mlir::NamedAttribute byRefAttr = fir::getAdaptToByRefAttr(builder); hlfir::AssociateOp associate = hlfir::genAssociateExpr( loc, builder, entity, entity.getType(), "", byRefAttr); diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index 9d72e76e2369..e28d14cd318d 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -786,7 +786,7 @@ mlir::Value genLibSplitComplexArgsCall(fir::FirOpBuilder &builder, auto getSplitComplexArgsType = [&builder, &args]() -> mlir::FunctionType { mlir::Type ctype = args[0].getType(); - auto fKind = mlir::cast(ctype).getFKind(); + auto fKind = ctype.cast().getFKind(); mlir::Type ftype; if (fKind == 2) @@ -894,8 +894,8 @@ mlir::Value genComplexMathOp(fir::FirOpBuilder &builder, mlir::Location loc, LLVM_DEBUG(llvm::dbgs() << "Generating '" << mathLibFuncName << "' operation with type "; mathLibFuncType.dump(); llvm::dbgs() << "\n"); - auto type = mlir::cast(mathLibFuncType.getInput(0)); - auto kind = mlir::cast(type.getElementType()).getFKind(); + auto type = mathLibFuncType.getInput(0).cast(); + auto kind = type.getElementType().cast().getFKind(); auto realTy = builder.getRealType(kind); auto mComplexTy = mlir::ComplexType::get(realTy); @@ -1394,14 +1394,14 @@ private: // Floating point can be mlir::FloatType or fir::real static unsigned getFloatingPointWidth(mlir::Type t) { - if (auto f{mlir::dyn_cast(t)}) + if (auto f{t.dyn_cast()}) return f.getWidth(); // FIXME: Get width another way for fir.real/complex // - use fir/KindMapping.h and llvm::Type // - or use evaluate/type.h - if (auto r{mlir::dyn_cast(t)}) + if (auto r{t.dyn_cast()}) return r.getFKind() * 4; - if (auto cplx{mlir::dyn_cast(t)}) + if (auto cplx{t.dyn_cast()}) return cplx.getFKind() * 4; llvm_unreachable("not a floating-point type"); } @@ -1410,8 +1410,8 @@ private: if (from == to) return Conversion::None; - if (auto fromIntTy{mlir::dyn_cast(from)}) { - if (auto toIntTy{mlir::dyn_cast(to)}) { + if (auto fromIntTy{from.dyn_cast()}) { + if (auto toIntTy{to.dyn_cast()}) { return fromIntTy.getWidth() > toIntTy.getWidth() ? Conversion::Narrow : Conversion::Extend; } @@ -1423,8 +1423,8 @@ private: : Conversion::Extend; } - if (auto fromCplxTy{mlir::dyn_cast(from)}) { - if (auto toCplxTy{mlir::dyn_cast(to)}) { + if (auto fromCplxTy{from.dyn_cast()}) { + if (auto toCplxTy{to.dyn_cast()}) { return getFloatingPointWidth(fromCplxTy) > getFloatingPointWidth(toCplxTy) ? Conversion::Narrow @@ -1550,10 +1550,10 @@ fir::ExtendedValue toExtendedValue(mlir::Value val, fir::FirOpBuilder &builder, if (charHelper.isCharacterScalar(type)) return charHelper.toExtendedValue(val); - if (auto refType = mlir::dyn_cast(type)) + if (auto refType = type.dyn_cast()) type = refType.getEleTy(); - if (auto arrayType = mlir::dyn_cast(type)) { + if (auto arrayType = type.dyn_cast()) { type = arrayType.getEleTy(); for (fir::SequenceType::Extent extent : arrayType.getShape()) { if (extent == fir::SequenceType::getUnknownExtent()) @@ -1566,8 +1566,7 @@ fir::ExtendedValue toExtendedValue(mlir::Value val, fir::FirOpBuilder &builder, // have been used in the interface). if (extents.size() + 1 < arrayType.getShape().size()) mlir::emitError(loc, "cannot retrieve array extents from type"); - } else if (mlir::isa(type) || - mlir::isa(type)) { + } else if (type.isa() || type.isa()) { fir::emitFatalError(loc, "not yet implemented: descriptor or derived type"); } @@ -1581,10 +1580,10 @@ mlir::Value toValue(const fir::ExtendedValue &val, fir::FirOpBuilder &builder, if (const fir::CharBoxValue *charBox = val.getCharBox()) { mlir::Value buffer = charBox->getBuffer(); auto buffTy = buffer.getType(); - if (mlir::isa(buffTy)) + if (buffTy.isa()) fir::emitFatalError( loc, "A character's buffer type cannot be a function type."); - if (mlir::isa(buffTy)) + if (buffTy.isa()) return buffer; return fir::factory::CharacterExprHelper{builder, loc}.createEmboxChar( buffer, charBox->getLen()); @@ -1828,27 +1827,27 @@ IntrinsicLibrary::invokeGenerator(SubroutineGenerator generator, /// Note: mlir has Type::dump(ostream) methods but it may add "!" that is not /// suitable for function names. static std::string typeToString(mlir::Type t) { - if (auto refT{mlir::dyn_cast(t)}) + if (auto refT{t.dyn_cast()}) return "ref_" + typeToString(refT.getEleTy()); - if (auto i{mlir::dyn_cast(t)}) { + if (auto i{t.dyn_cast()}) { return "i" + std::to_string(i.getWidth()); } - if (auto cplx{mlir::dyn_cast(t)}) { + if (auto cplx{t.dyn_cast()}) { return "z" + std::to_string(cplx.getFKind()); } - if (auto real{mlir::dyn_cast(t)}) { + if (auto real{t.dyn_cast()}) { return "r" + std::to_string(real.getFKind()); } - if (auto f{mlir::dyn_cast(t)}) { + if (auto f{t.dyn_cast()}) { return "f" + std::to_string(f.getWidth()); } - if (auto logical{mlir::dyn_cast(t)}) { + if (auto logical{t.dyn_cast()}) { return "l" + std::to_string(logical.getFKind()); } - if (auto character{mlir::dyn_cast(t)}) { + if (auto character{t.dyn_cast()}) { return "c" + std::to_string(character.getFKind()); } - if (auto boxCharacter{mlir::dyn_cast(t)}) { + if (auto boxCharacter{t.dyn_cast()}) { return "bc" + std::to_string(boxCharacter.getEleTy().getFKind()); } llvm_unreachable("no mangling for type"); @@ -1908,7 +1907,7 @@ mlir::func::FuncOp IntrinsicLibrary::getWrapper(GeneratorType generator, mlir::Location localLoc = localBuilder->getUnknownLoc(); llvm::SmallVector localArguments; for (mlir::BlockArgument bArg : function.front().getArguments()) { - auto refType = mlir::dyn_cast(bArg.getType()); + auto refType = bArg.getType().dyn_cast(); if (loadRefArguments && refType) { auto loaded = localBuilder->create(localLoc, bArg); localArguments.push_back(loaded); @@ -2061,7 +2060,7 @@ mlir::SymbolRefAttr IntrinsicLibrary::getUnrestrictedIntrinsicSymbolRefAttr( if (!funcOp) { llvm::SmallVector argTypes; for (mlir::Type type : signature.getInputs()) { - if (auto refType = mlir::dyn_cast(type)) + if (auto refType = type.dyn_cast()) argTypes.push_back(refType.getEleTy()); else argTypes.push_back(type); @@ -2146,7 +2145,7 @@ mlir::Value IntrinsicLibrary::genAbs(mlir::Type resultType, // math::AbsFOp but it does not support all fir floating point types. return genRuntimeCall("abs", resultType, args); } - if (auto intType = mlir::dyn_cast(type)) { + if (auto intType = type.dyn_cast()) { // At the time of this implementation there is no abs op in mlir. // So, implement abs here without branching. mlir::Value shift = @@ -2380,8 +2379,8 @@ IntrinsicLibrary::genAssociated(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); mlir::Type ptrTy = fir::getBase(args[0]).getType(); - if (ptrTy && (fir::isBoxProcAddressType(ptrTy) || - mlir::isa(ptrTy))) { + if (ptrTy && + (fir::isBoxProcAddressType(ptrTy) || ptrTy.isa())) { mlir::Value pointerBoxProc = fir::isBoxProcAddressType(ptrTy) ? builder.create(loc, fir::getBase(args[0])) @@ -2393,7 +2392,7 @@ IntrinsicLibrary::genAssociated(mlir::Type resultType, mlir::Value target = fir::getBase(args[1]); if (fir::isBoxProcAddressType(target.getType())) target = builder.create(loc, target); - if (mlir::isa(target.getType())) + if (target.getType().isa()) target = builder.create(loc, target); mlir::Type intPtrTy = builder.getIntPtrType(); mlir::Value pointerInt = @@ -2650,7 +2649,7 @@ static mlir::Value getAddrFromBox(fir::FirOpBuilder &builder, mlir::Value argValue = fir::getBase(arg); mlir::Value addr{nullptr}; if (isFunc) { - auto funcTy = mlir::cast(argValue.getType()).getEleTy(); + auto funcTy = argValue.getType().cast().getEleTy(); addr = builder.create(loc, funcTy, argValue); } else { const auto *box = arg.getBoxOf(); @@ -3030,7 +3029,7 @@ void IntrinsicLibrary::genDateAndTime(llvm::ArrayRef args) { mlir::Value IntrinsicLibrary::genDim(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (mlir::isa(resultType)) { + if (resultType.isa()) { mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); auto diff = builder.create(loc, args[0], args[1]); auto cmp = builder.create( @@ -3575,7 +3574,7 @@ IntrinsicLibrary::genReduction(FN func, FD funcDim, llvm::StringRef errMsg, if (absentDim || rank == 1) { mlir::Type ty = array.getType(); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); if (fir::isa_complex(eleTy)) { mlir::Value result = builder.createTemporary(loc, eleTy); func(builder, loc, array, mask, result); @@ -3647,7 +3646,7 @@ mlir::Value IntrinsicLibrary::genIbits(mlir::Type resultType, mlir::Value pos = builder.createConvert(loc, resultType, args[1]); mlir::Value len = builder.createConvert(loc, resultType, args[2]); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, mlir::cast(resultType).getWidth()); + loc, resultType, resultType.cast().getWidth()); auto shiftCount = builder.create(loc, bitSize, len); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value ones = builder.createAllOnesInteger(loc, resultType); @@ -3687,7 +3686,7 @@ IntrinsicLibrary::genIchar(mlir::Type resultType, mlir::Value buffer = charBox->getBuffer(); mlir::Type bufferTy = buffer.getType(); mlir::Value charVal; - if (auto charTy = mlir::dyn_cast(bufferTy)) { + if (auto charTy = bufferTy.dyn_cast()) { assert(charTy.singleton()); charVal = buffer; } else { @@ -3760,7 +3759,7 @@ void IntrinsicLibrary::genRaiseExcept(int except, mlir::Value cond) { static std::pair getFieldRef(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value rec) { auto recType = - mlir::dyn_cast(fir::unwrapPassByRefType(rec.getType())); + fir::unwrapPassByRefType(rec.getType()).dyn_cast(); assert(recType.getTypeList().size() == 1 && "expected exactly one component"); auto [fieldName, fieldTy] = recType.getTypeList().front(); mlir::Value field = builder.create( @@ -3809,7 +3808,7 @@ mlir::Value IntrinsicLibrary::genIeeeClass(mlir::Type resultType, assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); + mlir::FloatType realType = realVal.getType().dyn_cast(); const unsigned intWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(intWidth); mlir::Value intVal = @@ -4057,10 +4056,8 @@ IntrinsicLibrary::genIeeeCopySign(mlir::Type resultType, assert(args.size() == 2); mlir::Value xRealVal = args[0]; mlir::Value yRealVal = args[1]; - mlir::FloatType xRealType = - mlir::dyn_cast(xRealVal.getType()); - mlir::FloatType yRealType = - mlir::dyn_cast(yRealVal.getType()); + mlir::FloatType xRealType = xRealVal.getType().dyn_cast(); + mlir::FloatType yRealType = yRealVal.getType().dyn_cast(); if (yRealType == mlir::FloatType::getBF16(builder.getContext())) { // Workaround: CopySignOp and BitcastOp don't work for kind 3 arg Y. @@ -4109,7 +4106,7 @@ void IntrinsicLibrary::genIeeeGetFlag(llvm::ArrayRef args) { mlir::Value flag = fir::getBase(args[0]); mlir::Value flagValue = fir::getBase(args[1]); mlir::Type resultTy = - mlir::dyn_cast(flagValue.getType()).getEleTy(); + flagValue.getType().dyn_cast().getEleTy(); mlir::Type i32Ty = builder.getIntegerType(32); mlir::Value zero = builder.createIntegerConstant(loc, i32Ty, 0); auto [fieldRef, ignore] = getFieldRef(builder, loc, flag); @@ -4133,7 +4130,7 @@ void IntrinsicLibrary::genIeeeGetHaltingMode( mlir::Value flag = fir::getBase(args[0]); mlir::Value halting = fir::getBase(args[1]); mlir::Type resultTy = - mlir::dyn_cast(halting.getType()).getEleTy(); + halting.getType().dyn_cast().getEleTy(); mlir::Type i32Ty = builder.getIntegerType(32); mlir::Value zero = builder.createIntegerConstant(loc, i32Ty, 0); auto [fieldRef, ignore] = getFieldRef(builder, loc, flag); @@ -4251,7 +4248,7 @@ mlir::Value IntrinsicLibrary::genIeeeLogb(mlir::Type resultType, // : ieee_copy_sign(X, 1.0) // +infinity or NaN assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); + mlir::FloatType realType = realVal.getType().dyn_cast(); int bitWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(realType.getWidth()); mlir::Value intVal = @@ -4548,7 +4545,7 @@ mlir::Value IntrinsicLibrary::genIeeeSignbit(mlir::Type resultType, // Check if the sign bit of arg X is set. assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); + mlir::FloatType realType = realVal.getType().dyn_cast(); int bitWidth = realType.getWidth(); if (realType == mlir::FloatType::getBF16(builder.getContext())) { // Workaround: can't bitcast or convert real(3) to integer(2) or real(2). @@ -4645,7 +4642,7 @@ mlir::Value IntrinsicLibrary::genIeeeValue(mlir::Type resultType, // A compiler generated call has one argument: // - arg[0] is an index constant assert(args.size() == 1 || args.size() == 2); - mlir::FloatType realType = mlir::dyn_cast(resultType); + mlir::FloatType realType = resultType.dyn_cast(); int bitWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(bitWidth); mlir::Type valueTy = bitWidth <= 64 ? intType : builder.getIntegerType(64); @@ -4887,7 +4884,7 @@ mlir::Value IntrinsicLibrary::genIshft(mlir::Type resultType, // : I << abs(SHIFT) assert(args.size() == 2); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, mlir::cast(resultType).getWidth()); + loc, resultType, resultType.cast().getWidth()); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value shift = builder.createConvert(loc, resultType, args[1]); mlir::Value absShift = genAbs(resultType, {shift}); @@ -4923,7 +4920,7 @@ mlir::Value IntrinsicLibrary::genIshftc(mlir::Type resultType, // Return: SHIFT == 0 || SIZE == abs(SHIFT) ? I : (unchanged | left | right) assert(args.size() == 3); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, mlir::cast(resultType).getWidth()); + loc, resultType, resultType.cast().getWidth()); mlir::Value I = args[0]; mlir::Value shift = builder.createConvert(loc, resultType, args[1]); mlir::Value size = @@ -5030,7 +5027,7 @@ IntrinsicLibrary::genLoc(mlir::Type resultType, mlir::Value box = fir::getBase(args[0]); assert(fir::isa_box_type(box.getType()) && "argument must have been lowered to box type"); - bool isFunc = mlir::isa(box.getType()); + bool isFunc = box.getType().isa(); if (!isOptional(box)) { mlir::Value argAddr = getAddrFromBox(builder, loc, args[0], isFunc); return builder.createConvert(loc, resultType, argAddr); @@ -5159,7 +5156,7 @@ IntrinsicLibrary::genMerge(mlir::Type, auto convertToStaticType = [&](mlir::Value polymorphic, mlir::Value other) -> mlir::Value { mlir::Type otherType = other.getType(); - if (mlir::isa(otherType)) + if (otherType.isa()) return builder.create(loc, otherType, polymorphic, /*shape*/ mlir::Value{}, /*slice=*/mlir::Value{}); @@ -5212,7 +5209,7 @@ mlir::Value IntrinsicLibrary::genMergeBits(mlir::Type resultType, mlir::Value IntrinsicLibrary::genMod(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (mlir::isa(resultType)) + if (resultType.isa()) return builder.create(loc, args[0], args[1]); // Use runtime. @@ -5234,7 +5231,7 @@ mlir::Value IntrinsicLibrary::genModulo(mlir::Type resultType, // - Otherwise, when A/P < 0 and MOD(A,P) !=0, then MODULO(A, P) = // A-FLOOR(A/P)*P = A-(INT(A/P)-1)*P = A-INT(A/P)*P+P = MOD(A,P)+P // Note that A/P < 0 if and only if A and P signs are different. - if (mlir::isa(resultType)) { + if (resultType.isa()) { auto remainder = builder.create(loc, args[0], args[1]); auto argXor = builder.create(loc, args[0], args[1]); @@ -5347,7 +5344,7 @@ void IntrinsicLibrary::genMvbits(llvm::ArrayRef args) { mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value ones = builder.createAllOnesInteger(loc, resultType); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, mlir::cast(resultType).getWidth()); + loc, resultType, resultType.cast().getWidth()); auto shiftCount = builder.create(loc, bitSize, len); auto mask = builder.create(loc, ones, shiftCount); auto unchangedTmp1 = builder.create(loc, mask, topos); @@ -5631,7 +5628,7 @@ IntrinsicLibrary::genReshape(mlir::Type resultType, assert(fir::BoxValue(shape).rank() == 1); mlir::Type shapeTy = shape.getType(); mlir::Type shapeArrTy = fir::dyn_cast_ptrOrBoxEleTy(shapeTy); - auto resultRank = mlir::cast(shapeArrTy).getShape()[0]; + auto resultRank = shapeArrTy.cast().getShape()[0]; if (resultRank == fir::SequenceType::getUnknownExtent()) TODO(loc, "intrinsic: reshape requires computing rank of result"); @@ -5924,7 +5921,7 @@ void IntrinsicLibrary::genSignalSubroutine( mlir::Value IntrinsicLibrary::genSign(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (mlir::isa(resultType)) { + if (resultType.isa()) { mlir::Value abs = genAbs(resultType, {args[0]}); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); auto neg = builder.create(loc, zero, abs); diff --git a/flang/lib/Optimizer/Builder/MutableBox.cpp b/flang/lib/Optimizer/Builder/MutableBox.cpp index 76b920dba869..d4012e9c3d9d 100644 --- a/flang/lib/Optimizer/Builder/MutableBox.cpp +++ b/flang/lib/Optimizer/Builder/MutableBox.cpp @@ -28,7 +28,7 @@ createNewFirBox(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, mlir::Value addr, mlir::ValueRange lbounds, mlir::ValueRange extents, mlir::ValueRange lengths, mlir::Value tdesc = {}) { - if (mlir::isa(addr.getType())) + if (addr.getType().isa()) // The entity is already boxed. return builder.createConvert(loc, box.getBoxTy(), addr); @@ -53,21 +53,20 @@ createNewFirBox(fir::FirOpBuilder &builder, mlir::Location loc, // error in the embox). llvm::SmallVector cleanedLengths; auto cleanedAddr = addr; - if (auto charTy = mlir::dyn_cast(box.getEleTy())) { + if (auto charTy = box.getEleTy().dyn_cast()) { // Cast address to box type so that both input and output type have // unknown or constant lengths. auto bt = box.getBaseTy(); auto addrTy = addr.getType(); - auto type = mlir::isa(addrTy) ? fir::HeapType::get(bt) - : mlir::isa(addrTy) - ? fir::PointerType::get(bt) - : builder.getRefType(bt); + auto type = addrTy.isa() ? fir::HeapType::get(bt) + : addrTy.isa() ? fir::PointerType::get(bt) + : builder.getRefType(bt); cleanedAddr = builder.createConvert(loc, type, addr); if (charTy.getLen() == fir::CharacterType::unknownLen()) cleanedLengths.append(lengths.begin(), lengths.end()); } else if (fir::isUnlimitedPolymorphicType(box.getBoxTy())) { - if (auto charTy = mlir::dyn_cast( - fir::dyn_cast_ptrEleTy(addr.getType()))) { + if (auto charTy = fir::dyn_cast_ptrEleTy(addr.getType()) + .dyn_cast()) { if (charTy.getLen() == fir::CharacterType::unknownLen()) cleanedLengths.append(lengths.begin(), lengths.end()); } @@ -329,18 +328,18 @@ private: mlir::Value fir::factory::createUnallocatedBox( fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type boxType, mlir::ValueRange nonDeferredParams, mlir::Value typeSourceBox) { - auto baseAddrType = mlir::dyn_cast(boxType).getEleTy(); + auto baseAddrType = boxType.dyn_cast().getEleTy(); if (!fir::isa_ref_type(baseAddrType)) baseAddrType = builder.getRefType(baseAddrType); auto type = fir::unwrapRefType(baseAddrType); auto eleTy = fir::unwrapSequenceType(type); - if (auto recTy = mlir::dyn_cast(eleTy)) + if (auto recTy = eleTy.dyn_cast()) if (recTy.getNumLenParams() > 0) TODO(loc, "creating unallocated fir.box of derived type with length " "parameters"); auto nullAddr = builder.createNullConstant(loc, baseAddrType); mlir::Value shape; - if (auto seqTy = mlir::dyn_cast(type)) { + if (auto seqTy = type.dyn_cast()) { auto zero = builder.createIntegerConstant(loc, builder.getIndexType(), 0); llvm::SmallVector extents(seqTy.getDimension(), zero); shape = builder.createShape( @@ -349,7 +348,7 @@ mlir::Value fir::factory::createUnallocatedBox( // Provide dummy length parameters if they are dynamic. If a length parameter // is deferred. It is set to zero here and will be set on allocation. llvm::SmallVector lenParams; - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { if (charTy.getLen() == fir::CharacterType::unknownLen()) { if (!nonDeferredParams.empty()) { lenParams.push_back(nonDeferredParams[0]); @@ -593,7 +592,7 @@ void fir::factory::associateMutableBoxWithRemap( auto cast = [&](mlir::Value addr) -> mlir::Value { // Cast base addr to new sequence type. auto ty = fir::dyn_cast_ptrEleTy(addr.getType()); - if (auto seqTy = mlir::dyn_cast(ty)) { + if (auto seqTy = ty.dyn_cast()) { fir::SequenceType::Shape shape(newRank, fir::SequenceType::getUnknownExtent()); ty = fir::SequenceType::get(shape, seqTy.getEleTy()); @@ -674,10 +673,10 @@ void fir::factory::disassociateMutableBox(fir::FirOpBuilder &builder, if (box.isPolymorphic() && polymorphicSetType) { // 7.3.2.3 point 7. The dynamic type of a disassociated pointer is the // same as its declared type. - auto boxTy = mlir::dyn_cast(box.getBoxTy()); + auto boxTy = box.getBoxTy().dyn_cast(); auto eleTy = fir::unwrapPassByRefType(boxTy.getEleTy()); mlir::Type derivedType = fir::getDerivedType(eleTy); - if (auto recTy = mlir::dyn_cast(derivedType)) { + if (auto recTy = derivedType.dyn_cast()) { fir::runtime::genNullifyDerivedType(builder, loc, box.getAddr(), recTy, box.rank()); return; @@ -691,7 +690,7 @@ getNewLengths(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, mlir::ValueRange lenParams) { llvm::SmallVector lengths; auto idxTy = builder.getIndexType(); - if (auto charTy = mlir::dyn_cast(box.getEleTy())) { + if (auto charTy = box.getEleTy().dyn_cast()) { if (charTy.getLen() == fir::CharacterType::unknownLen()) { if (box.hasNonDeferredLenParams()) { lengths.emplace_back( @@ -718,7 +717,7 @@ static mlir::Value allocateAndInitNewStorage(fir::FirOpBuilder &builder, auto lengths = getNewLengths(builder, loc, box, lenParams); auto newStorage = builder.create( loc, box.getBaseTy(), allocName, lengths, extents); - if (mlir::isa(box.getEleTy())) { + if (box.getEleTy().isa()) { // TODO: skip runtime initialization if this is not required. Currently, // there is no way to know here if a derived type needs it or not. But the // information is available at compile time and could be reflected here @@ -743,7 +742,7 @@ void fir::factory::genInlinedAllocation( lengths, safeExtents); MutablePropertyWriter{builder, loc, box}.updateMutableBox( heap, lbounds, safeExtents, lengths); - if (mlir::isa(box.getEleTy())) { + if (box.getEleTy().isa()) { // TODO: skip runtime initialization if this is not required. Currently, // there is no way to know here if a derived type needs it or not. But the // information is available at compile time and could be reflected here diff --git a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp index 7f09e8822844..160118e2c050 100644 --- a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp @@ -1119,7 +1119,7 @@ PPCIntrinsicLibrary::genVecAbs(mlir::Type resultType, funcOp = builder.createFunction(loc, fname, ftype); auto callOp{builder.create(loc, funcOp, argBases[0])}; return callOp.getResult(0); - } else if (auto eleTy = mlir::dyn_cast(vTypeInfo.eleTy)) { + } else if (auto eleTy = vTypeInfo.eleTy.dyn_cast()) { // vec_abs(arg1) = max(0 - arg1, arg1) auto newVecTy{mlir::VectorType::get(vTypeInfo.len, eleTy)}; @@ -1173,13 +1173,12 @@ fir::ExtendedValue PPCIntrinsicLibrary::genVecAddAndMulSubXor( assert(args.size() == 2); auto argBases{getBasesForArgs(args)}; auto argsTy{getTypesForArgs(argBases)}; - assert(mlir::isa(argsTy[0]) && - mlir::isa(argsTy[1])); + assert(argsTy[0].isa() && argsTy[1].isa()); auto vecTyInfo{getVecTypeFromFir(argBases[0])}; - const auto isInteger{mlir::isa(vecTyInfo.eleTy)}; - const auto isFloat{mlir::isa(vecTyInfo.eleTy)}; + const auto isInteger{vecTyInfo.eleTy.isa()}; + const auto isFloat{vecTyInfo.eleTy.isa()}; assert((isInteger || isFloat) && "unknown vector type"); auto vargs{convertVecArgs(builder, loc, vecTyInfo, argBases)}; @@ -1213,7 +1212,7 @@ fir::ExtendedValue PPCIntrinsicLibrary::genVecAddAndMulSubXor( arg2 = vargs[1]; } else if (isFloat) { // bitcast the arguments to integer - auto wd{mlir::dyn_cast(vecTyInfo.eleTy).getWidth()}; + auto wd{vecTyInfo.eleTy.dyn_cast().getWidth()}; auto ftype{builder.getIntegerType(wd)}; auto bcVecTy{mlir::VectorType::get(vecTyInfo.len, ftype)}; arg1 = builder.create(loc, bcVecTy, vargs[0]); @@ -1451,7 +1450,7 @@ PPCIntrinsicLibrary::genVecCmp(mlir::Type resultType, mlir::Value res{nullptr}; - if (auto eTy = mlir::dyn_cast(vecTyInfo.eleTy)) { + if (auto eTy = vecTyInfo.eleTy.dyn_cast()) { constexpr int firstArg{0}; constexpr int secondArg{1}; std::map> argOrder{ @@ -1560,7 +1559,7 @@ PPCIntrinsicLibrary::genVecConvert(mlir::Type resultType, case VecOp::Ctf: { assert(args.size() == 2); auto convArg{builder.createConvert(loc, i32Ty, argBases[1])}; - auto eTy{mlir::dyn_cast(vecTyInfo.eleTy)}; + auto eTy{vecTyInfo.eleTy.dyn_cast()}; assert(eTy && "Unsupported vector type"); const auto isUnsigned{eTy.isUnsignedInteger()}; const auto width{eTy.getWidth()}; @@ -1588,9 +1587,10 @@ PPCIntrinsicLibrary::genVecConvert(mlir::Type resultType, : builder.create(loc, ty, vArg1)}; // construct vector<1./(1< - auto constInt{mlir::dyn_cast_or_null( + auto constInt{ mlir::dyn_cast(argBases[1].getDefiningOp()) - .getValue())}; + .getValue() + .dyn_cast_or_null()}; assert(constInt && "expected integer constant argument"); double f{1.0 / (1 << constInt.getInt())}; llvm::SmallVector vals{f, f}; @@ -1815,7 +1815,7 @@ static mlir::Value addOffsetToAddress(fir::FirOpBuilder &builder, static mlir::Value reverseVectorElements(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value v, int64_t len) { - assert(mlir::isa(v.getType())); + assert(v.getType().isa()); assert(len > 0); llvm::SmallVector mask; for (int64_t i = 0; i < len; ++i) { @@ -2144,9 +2144,10 @@ PPCIntrinsicLibrary::genVecPerm(mlir::Type resultType, } case VecOp::Permi: { // arg3 is a constant - auto constIntOp{mlir::dyn_cast_or_null( + auto constIntOp{ mlir::dyn_cast(argBases[2].getDefiningOp()) - .getValue())}; + .getValue() + .dyn_cast_or_null()}; assert(constIntOp && "expected integer constant argument"); auto constInt{constIntOp.getInt()}; // arg1, arg2, and result type share same VecTypeInfo @@ -2320,9 +2321,10 @@ PPCIntrinsicLibrary::genVecShift(mlir::Type resultType, } } else if (vop == VecOp::Sld || vop == VecOp::Sldw) { assert(args.size() == 3); - auto constIntOp = mlir::dyn_cast_or_null( + auto constIntOp = mlir::dyn_cast(argBases[2].getDefiningOp()) - .getValue()); + .getValue() + .dyn_cast_or_null(); assert(constIntOp && "expected integer constant argument"); // Bitcast to vector<16xi8> @@ -2795,16 +2797,16 @@ void PPCIntrinsicLibrary::genMmaIntr(llvm::ArrayRef args) { auto vType{v.getType()}; mlir::Type targetType{intrFuncType.getInput(j)}; if (vType != targetType) { - if (mlir::isa(targetType)) { + if (targetType.isa()) { // Perform vector type conversion for arguments passed by value. - auto eleTy{mlir::dyn_cast(vType).getEleTy()}; - auto len{mlir::dyn_cast(vType).getLen()}; + auto eleTy{vType.dyn_cast().getEleTy()}; + auto len{vType.dyn_cast().getLen()}; mlir::VectorType mlirType = mlir::VectorType::get(len, eleTy); auto v0{builder.createConvert(loc, mlirType, v)}; auto v1{builder.create(loc, targetType, v0)}; intrArgs.push_back(v1); - } else if (mlir::isa(targetType) && - mlir::isa(vType)) { + } else if (targetType.isa() && + vType.isa()) { auto v0{builder.createConvert(loc, targetType, v)}; intrArgs.push_back(v0); } else { @@ -2859,7 +2861,7 @@ void PPCIntrinsicLibrary::genVecStore(llvm::ArrayRef args) { if (arg1TyInfo.isFloat32()) { stTy = mlir::VectorType::get(len, i32ty); fname = "llvm.ppc.altivec.stvewx"; - } else if (mlir::isa(arg1TyInfo.eleTy)) { + } else if (arg1TyInfo.eleTy.isa()) { stTy = mlir::VectorType::get(len, mlir::IntegerType::get(context, width)); switch (width) { diff --git a/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp b/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp index 70a88ff18cb1..abff0e150ab4 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp @@ -27,7 +27,7 @@ mlir::Value fir::runtime::genMoveAlloc(fir::FirOpBuilder &builder, if (fir::isPolymorphicType(from.getType()) && !fir::isUnlimitedPolymorphicType(from.getType())) { fir::ClassType clTy = - mlir::dyn_cast(fir::dyn_cast_ptrEleTy(from.getType())); + fir::dyn_cast_ptrEleTy(from.getType()).dyn_cast(); mlir::Type derivedType = fir::unwrapInnerType(clTy.getEleTy()); declaredTypeDesc = builder.create(loc, mlir::TypeAttr::get(derivedType)); diff --git a/flang/lib/Optimizer/Builder/Runtime/Character.cpp b/flang/lib/Optimizer/Builder/Runtime/Character.cpp index b16819915d5a..f3663439fdd5 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Character.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Character.cpp @@ -39,15 +39,15 @@ static void genCharacterSearch(FN func, fir::FirOpBuilder &builder, /// Helper function to recover the KIND from the FIR type. static int discoverKind(mlir::Type ty) { - if (auto charTy = mlir::dyn_cast(ty)) + if (auto charTy = ty.dyn_cast()) return charTy.getFKind(); if (auto eleTy = fir::dyn_cast_ptrEleTy(ty)) return discoverKind(eleTy); - if (auto arrTy = mlir::dyn_cast(ty)) + if (auto arrTy = ty.dyn_cast()) return discoverKind(arrTy.getEleTy()); - if (auto boxTy = mlir::dyn_cast(ty)) + if (auto boxTy = ty.dyn_cast()) return discoverKind(boxTy.getEleTy()); - if (auto boxTy = mlir::dyn_cast(ty)) + if (auto boxTy = ty.dyn_cast()) return discoverKind(boxTy.getEleTy()); llvm_unreachable("unexpected character type"); } diff --git a/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp b/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp index 8b78a1688c73..57c47da0f3f8 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp @@ -228,8 +228,7 @@ void fir::runtime::genSystemClock(fir::FirOpBuilder &builder, fir::IfOp ifOp{}; const bool isOptionalArg = fir::valueHasFirAttribute(arg, fir::getOptionalAttrName()); - if (mlir::dyn_cast(type) || - mlir::dyn_cast(type)) { + if (type.dyn_cast() || type.dyn_cast()) { // Check for a disassociated pointer or an unallocated allocatable. assert(!isOptionalArg && "invalid optional argument"); ifOp = builder.create(loc, builder.genIsNotNullAddr(loc, arg), @@ -243,8 +242,7 @@ void fir::runtime::genSystemClock(fir::FirOpBuilder &builder, builder.setInsertionPointToStart(&ifOp.getThenRegion().front()); mlir::Type kindTy = func.getFunctionType().getInput(0); int integerKind = 8; - if (auto intType = - mlir::dyn_cast(fir::unwrapRefType(type))) + if (auto intType = fir::unwrapRefType(type).dyn_cast()) integerKind = intType.getWidth() / 8; mlir::Value kind = builder.createIntegerConstant(loc, kindTy, integerKind); mlir::Value res = diff --git a/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp b/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp index e5d0fb0fb27a..4d33282a35d9 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp @@ -32,8 +32,7 @@ void fir::runtime::genRaggedArrayAllocate(mlir::Location loc, // Position of the bufferPointer in the header struct. auto one = builder.createIntegerConstant(loc, i32Ty, 1); auto eleTy = fir::unwrapSequenceType(fir::unwrapRefType(header.getType())); - auto ptrTy = - builder.getRefType(mlir::cast(eleTy).getType(1)); + auto ptrTy = builder.getRefType(eleTy.cast().getType(1)); auto ptr = builder.create(loc, ptrTy, header, one); auto heap = builder.create(loc, ptr); auto cmp = builder.genIsNullAddr(loc, heap); diff --git a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp index d4076067bf10..66fbaddcbda1 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp @@ -666,7 +666,7 @@ void fir::runtime::genMaxloc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); fir::factory::CharacterExprHelper charHelper{builder, loc}; if (eleTy.isF32()) func = fir::runtime::getRuntimeFunc(loc, builder); @@ -713,7 +713,7 @@ mlir::Value fir::runtime::genMaxval(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -781,7 +781,7 @@ void fir::runtime::genMinloc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); fir::factory::CharacterExprHelper charHelper{builder, loc}; if (eleTy.isF32()) func = fir::runtime::getRuntimeFunc(loc, builder); @@ -853,7 +853,7 @@ mlir::Value fir::runtime::genMinval(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -895,7 +895,7 @@ void fir::runtime::genNorm2Dim(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); if (eleTy.isF128()) func = fir::runtime::getRuntimeFunc(loc, builder); else @@ -917,7 +917,7 @@ mlir::Value fir::runtime::genNorm2(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -968,7 +968,7 @@ mlir::Value fir::runtime::genProduct(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -1069,7 +1069,7 @@ mlir::Value fir::runtime::genDotProduct(fir::FirOpBuilder &builder, else if (eleTy.isInteger(builder.getKindMap().getIntegerBitsize(16))) func = fir::runtime::getRuntimeFunc(loc, builder); - else if (mlir::isa(eleTy)) + else if (eleTy.isa()) func = fir::runtime::getRuntimeFunc(loc, builder); else @@ -1111,7 +1111,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = mlir::cast(arrTy).getEleTy(); + auto eleTy = arrTy.cast().getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -1173,7 +1173,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; \ auto ty = arrayBox.getType(); \ auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); \ - auto eleTy = mlir::cast(arrTy).getEleTy(); \ + auto eleTy = arrTy.cast().getEleTy(); \ auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); \ \ if (eleTy.isInteger(builder.getKindMap().getIntegerBitsize(1))) \ diff --git a/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp b/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp index 5229d40f2250..48173033ecbe 100644 --- a/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp +++ b/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp @@ -51,9 +51,9 @@ public: /// not at all depending on the implementation target's characteristics and /// preference. bool needsConversion(mlir::Type ty) { - if (mlir::isa(ty)) + if (ty.isa()) return true; - if (auto funcTy = mlir::dyn_cast(ty)) { + if (auto funcTy = ty.dyn_cast()) { for (auto t : funcTy.getInputs()) if (needsConversion(t)) return true; @@ -62,13 +62,13 @@ public: return true; return false; } - if (auto tupleTy = mlir::dyn_cast(ty)) { + if (auto tupleTy = ty.dyn_cast()) { for (auto t : tupleTy.getTypes()) if (needsConversion(t)) return true; return false; } - if (auto recTy = mlir::dyn_cast(ty)) { + if (auto recTy = ty.dyn_cast()) { auto visited = visitedTypes.find(ty); if (visited != visitedTypes.end()) return visited->second; @@ -97,11 +97,11 @@ public: visitedTypes.find(ty)->second = result; return result; } - if (auto boxTy = mlir::dyn_cast(ty)) + if (auto boxTy = ty.dyn_cast()) return needsConversion(boxTy.getEleTy()); if (isa_ref_type(ty)) return needsConversion(unwrapRefType(ty)); - if (auto t = mlir::dyn_cast(ty)) + if (auto t = ty.dyn_cast()) return needsConversion(unwrapSequenceType(ty)); return false; } @@ -246,7 +246,7 @@ public: if (typeConverter.needsConversion(ty)) { rewriter.startOpModification(func); auto toTy = - mlir::cast(typeConverter.convertType(ty)); + typeConverter.convertType(ty).cast(); if (!func.empty()) for (auto e : llvm::enumerate(toTy.getInputs())) { unsigned i = e.index(); @@ -263,7 +263,7 @@ public: // Rewrite all `fir.emboxproc` ops to either `fir.convert` or a thunk // as required. mlir::Type toTy = typeConverter.convertType( - mlir::cast(embox.getType()).getEleTy()); + embox.getType().cast().getEleTy()); rewriter.setInsertionPoint(embox); if (embox.getHost()) { // Create the thunk. diff --git a/flang/lib/Optimizer/CodeGen/CGOps.cpp b/flang/lib/Optimizer/CodeGen/CGOps.cpp index 44d07d26dd2b..c3bcdeaf86db 100644 --- a/flang/lib/Optimizer/CodeGen/CGOps.cpp +++ b/flang/lib/Optimizer/CodeGen/CGOps.cpp @@ -41,24 +41,24 @@ unsigned fir::cg::XEmboxOp::getOutRank() { } unsigned fir::cg::XReboxOp::getOutRank() { - if (auto seqTy = mlir::dyn_cast( - fir::dyn_cast_ptrOrBoxEleTy(getType()))) + if (auto seqTy = + fir::dyn_cast_ptrOrBoxEleTy(getType()).dyn_cast()) return seqTy.getDimension(); return 0; } unsigned fir::cg::XReboxOp::getRank() { - if (auto seqTy = mlir::dyn_cast( - fir::dyn_cast_ptrOrBoxEleTy(getBox().getType()))) + if (auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(getBox().getType()) + .dyn_cast()) return seqTy.getDimension(); return 0; } unsigned fir::cg::XArrayCoorOp::getRank() { auto memrefTy = getMemref().getType(); - if (mlir::isa(memrefTy)) - if (auto seqty = mlir::dyn_cast( - fir::dyn_cast_ptrOrBoxEleTy(memrefTy))) + if (memrefTy.isa()) + if (auto seqty = + fir::dyn_cast_ptrOrBoxEleTy(memrefTy).dyn_cast()) return seqty.getDimension(); return getShape().size(); } diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp index 19628ac71b0b..921eac2f8f4b 100644 --- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp +++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp @@ -101,7 +101,7 @@ static int64_t getConstantIntValue(mlir::Value val) { } static unsigned getTypeDescFieldId(mlir::Type ty) { - auto isArray = mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(ty)); + auto isArray = fir::dyn_cast_ptrOrBoxEleTy(ty).isa(); return isArray ? kOptTypePtrPosInBox : kDimsPosInBox; } static unsigned getLenParamFieldId(mlir::Type ty) { @@ -147,7 +147,7 @@ genAllocationScaleSize(OP op, mlir::Type ity, mlir::ConversionPatternRewriter &rewriter) { mlir::Location loc = op.getLoc(); mlir::Type dataTy = op.getInType(); - auto seqTy = mlir::dyn_cast(dataTy); + auto seqTy = dataTy.dyn_cast(); fir::SequenceType::Extent constSize = 1; if (seqTy) { int constRows = seqTy.getConstantRows(); @@ -191,13 +191,13 @@ struct AllocaOpConversion : public fir::FIROpConversion { for (; i < end; ++i) lenParams.push_back(operands[i]); mlir::Type scalarType = fir::unwrapSequenceType(alloc.getInType()); - if (auto chrTy = mlir::dyn_cast(scalarType)) { + if (auto chrTy = scalarType.dyn_cast()) { fir::CharacterType rawCharTy = fir::CharacterType::getUnknownLen( chrTy.getContext(), chrTy.getFKind()); llvmObjectType = convertType(rawCharTy); assert(end == 1); size = integerCast(loc, rewriter, ity, lenParams[0]); - } else if (auto recTy = mlir::dyn_cast(scalarType)) { + } else if (auto recTy = scalarType.dyn_cast()) { mlir::LLVM::LLVMFuncOp memSizeFn = getDependentTypeMemSizeFn(recTy, alloc, rewriter); if (!memSizeFn) @@ -265,8 +265,7 @@ struct BoxAddrOpConversion : public fir::FIROpConversion { mlir::ConversionPatternRewriter &rewriter) const override { mlir::Value a = adaptor.getOperands()[0]; auto loc = boxaddr.getLoc(); - if (auto argty = - mlir::dyn_cast(boxaddr.getVal().getType())) { + if (auto argty = boxaddr.getVal().getType().dyn_cast()) { TypePair boxTyPair = getBoxTypePair(argty); rewriter.replaceOp(boxaddr, getBaseAddrFromBox(loc, boxTyPair, a, rewriter)); @@ -477,25 +476,24 @@ struct StringLitOpConversion : public fir::FIROpConversion { mlir::ConversionPatternRewriter &rewriter) const override { auto ty = convertType(constop.getType()); auto attr = constop.getValue(); - if (mlir::isa(attr)) { + if (attr.isa()) { rewriter.replaceOpWithNewOp(constop, ty, attr); return mlir::success(); } - auto charTy = mlir::cast(constop.getType()); + auto charTy = constop.getType().cast(); unsigned bits = lowerTy().characterBitsize(charTy); mlir::Type intTy = rewriter.getIntegerType(bits); mlir::Location loc = constop.getLoc(); mlir::Value cst = rewriter.create(loc, ty); - if (auto arr = mlir::dyn_cast(attr)) { + if (auto arr = attr.dyn_cast()) { cst = rewriter.create(loc, ty, arr); - } else if (auto arr = mlir::dyn_cast(attr)) { + } else if (auto arr = attr.dyn_cast()) { for (auto a : llvm::enumerate(arr.getValue())) { // convert each character to a precise bitsize auto elemAttr = mlir::IntegerAttr::get( intTy, - mlir::cast(a.value()).getValue().zextOrTrunc( - bits)); + a.value().cast().getValue().zextOrTrunc(bits)); auto elemCst = rewriter.create(loc, intTy, elemAttr); cst = rewriter.create(loc, cst, elemCst, @@ -530,9 +528,9 @@ struct CallOpConversion : public fir::FIROpConversion { } // namespace static mlir::Type getComplexEleTy(mlir::Type complex) { - if (auto cc = mlir::dyn_cast(complex)) + if (auto cc = complex.dyn_cast()) return cc.getElementType(); - return mlir::cast(complex).getElementType(); + return complex.cast().getElementType(); } namespace { @@ -601,7 +599,7 @@ struct ConstcOpConversion : public fir::FIROpConversion { } inline llvm::APFloat getValue(mlir::Attribute attr) const { - return mlir::cast(attr).getValue(); + return attr.cast().getValue(); } }; @@ -610,7 +608,7 @@ struct ConvertOpConversion : public fir::FIROpConversion { using FIROpConversion::FIROpConversion; static bool isFloatingPointTy(mlir::Type ty) { - return mlir::isa(ty); + return ty.isa(); } mlir::LogicalResult @@ -630,8 +628,7 @@ struct ConvertOpConversion : public fir::FIROpConversion { auto loc = convert.getLoc(); auto i1Type = mlir::IntegerType::get(convert.getContext(), 1); - if (mlir::isa(fromFirTy) || - mlir::isa(toFirTy)) { + if (fromFirTy.isa() || toFirTy.isa()) { // By specification fir::LogicalType value may be any number, // where non-zero value represents .true. and zero value represents // .false. @@ -644,8 +641,7 @@ struct ConvertOpConversion : public fir::FIROpConversion { // Conversion from narrow logical to wide logical may be implemented // as a zero or sign extension of the input, but it may use value // normalization as well. - if (!mlir::isa(fromTy) || - !mlir::isa(toTy)) + if (!fromTy.isa() || !toTy.isa()) return mlir::emitError(loc) << "unsupported types for logical conversion: " << fromTy << " -> " << toTy; @@ -726,13 +722,13 @@ struct ConvertOpConversion : public fir::FIROpConversion { rewriter.replaceOp(convert, v); return mlir::success(); } - if (mlir::isa(toTy)) { + if (toTy.isa()) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } - } else if (mlir::isa(fromTy)) { + } else if (fromTy.isa()) { // Integer to integer conversion. - if (mlir::isa(toTy)) { + if (toTy.isa()) { auto fromBits = mlir::LLVM::getPrimitiveTypeSizeInBits(fromTy); auto toBits = mlir::LLVM::getPrimitiveTypeSizeInBits(toTy); assert(fromBits != toBits); @@ -753,18 +749,18 @@ struct ConvertOpConversion : public fir::FIROpConversion { return mlir::success(); } // Integer to pointer conversion. - if (mlir::isa(toTy)) { + if (toTy.isa()) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } - } else if (mlir::isa(fromTy)) { + } else if (fromTy.isa()) { // Pointer to integer conversion. - if (mlir::isa(toTy)) { + if (toTy.isa()) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } // Pointer to pointer conversion. - if (mlir::isa(toTy)) { + if (toTy.isa()) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } @@ -846,11 +842,11 @@ struct EmboxCharOpConversion : public fir::FIROpConversion { auto llvmStruct = rewriter.create(loc, llvmStructTy); mlir::Type lenTy = - mlir::cast(llvmStructTy).getBody()[1]; + llvmStructTy.cast().getBody()[1]; mlir::Value lenAfterCast = integerCast(loc, rewriter, lenTy, charBufferLen); mlir::Type addrTy = - mlir::cast(llvmStructTy).getBody()[0]; + llvmStructTy.cast().getBody()[0]; if (addrTy != charBuffer.getType()) charBuffer = rewriter.create(loc, addrTy, charBuffer); @@ -983,10 +979,9 @@ static mlir::SymbolRefAttr getFree(fir::FreeMemOp op, static unsigned getDimension(mlir::LLVM::LLVMArrayType ty) { unsigned result = 1; - for (auto eleTy = - mlir::dyn_cast(ty.getElementType()); - eleTy; eleTy = mlir::dyn_cast( - eleTy.getElementType())) + for (auto eleTy = ty.getElementType().dyn_cast(); + eleTy; + eleTy = eleTy.getElementType().dyn_cast()) ++result; return result; } @@ -1057,9 +1052,9 @@ struct EmboxCommonConversion : public fir::FIROpConversion { static int getCFIAttr(fir::BaseBoxType boxTy) { auto eleTy = boxTy.getEleTy(); - if (mlir::isa(eleTy)) + if (eleTy.isa()) return CFI_attribute_pointer; - if (mlir::isa(eleTy)) + if (eleTy.isa()) return CFI_attribute_allocatable; return CFI_attribute_other; } @@ -1087,29 +1082,27 @@ struct EmboxCommonConversion : public fir::FIROpConversion { auto i64Ty = mlir::IntegerType::get(rewriter.getContext(), 64); if (auto eleTy = fir::dyn_cast_ptrEleTy(boxEleTy)) boxEleTy = eleTy; - if (auto seqTy = mlir::dyn_cast(boxEleTy)) + if (auto seqTy = boxEleTy.dyn_cast()) return getSizeAndTypeCode(loc, rewriter, seqTy.getEleTy(), lenParams); - if (mlir::isa( - boxEleTy)) // unlimited polymorphic or assumed type + if (boxEleTy.isa()) // unlimited polymorphic or assumed type return {rewriter.create(loc, i64Ty, 0), this->genConstantOffset(loc, rewriter, CFI_type_other)}; mlir::Value typeCodeVal = this->genConstantOffset( loc, rewriter, fir::getTypeCode(boxEleTy, this->lowerTy().getKindMap())); - if (fir::isa_integer(boxEleTy) || - mlir::dyn_cast(boxEleTy) || fir::isa_real(boxEleTy) || - fir::isa_complex(boxEleTy)) + if (fir::isa_integer(boxEleTy) || boxEleTy.dyn_cast() || + fir::isa_real(boxEleTy) || fir::isa_complex(boxEleTy)) return {genTypeStrideInBytes(loc, i64Ty, rewriter, this->convertType(boxEleTy)), typeCodeVal}; - if (auto charTy = mlir::dyn_cast(boxEleTy)) + if (auto charTy = boxEleTy.dyn_cast()) return {getCharacterByteSize(loc, rewriter, charTy, lenParams), typeCodeVal}; if (fir::isa_ref_type(boxEleTy)) { auto ptrTy = ::getLlvmPtrType(rewriter.getContext()); return {genTypeStrideInBytes(loc, i64Ty, rewriter, ptrTy), typeCodeVal}; } - if (mlir::isa(boxEleTy)) + if (boxEleTy.isa()) return {genTypeStrideInBytes(loc, i64Ty, rewriter, this->convertType(boxEleTy)), typeCodeVal}; @@ -1218,8 +1211,8 @@ struct EmboxCommonConversion : public fir::FIROpConversion { if (!typeDesc) { if (useInputType) { mlir::Type innerType = fir::unwrapInnerType(inputType); - if (innerType && mlir::isa(innerType)) { - auto recTy = mlir::dyn_cast(innerType); + if (innerType && innerType.template isa()) { + auto recTy = innerType.template dyn_cast(); typeDesc = getTypeDescriptor(mod, rewriter, loc, recTy); } else { // Unlimited polymorphic type descriptor with no record type. Set @@ -1257,7 +1250,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::ValueRange lenParams, mlir::Value sourceBox = {}, mlir::Type sourceBoxType = {}) const { auto loc = box.getLoc(); - auto boxTy = mlir::dyn_cast(box.getType()); + auto boxTy = box.getType().template dyn_cast(); bool useInputType = fir::isPolymorphicType(boxTy) && !fir::isUnlimitedPolymorphicType(inputType); llvm::SmallVector typeparams = lenParams; @@ -1300,8 +1293,8 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::ValueRange lenParams, mlir::Value typeDesc = {}) const { auto loc = box.getLoc(); - auto boxTy = mlir::dyn_cast(box.getType()); - auto inputBoxTy = mlir::dyn_cast(box.getBox().getType()); + auto boxTy = box.getType().dyn_cast(); + auto inputBoxTy = box.getBox().getType().dyn_cast(); auto inputBoxTyPair = this->getBoxTypePair(inputBoxTy); llvm::SmallVector typeparams = lenParams; if (!box.getSubstr().empty() && fir::hasDynamicSize(boxTy.getEleTy())) @@ -1350,7 +1343,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::Type resultTy = llvmBaseObjectType; // Fortran is column major, llvm GEP is row major: reverse the indices here. for (mlir::Value interiorIndex : llvm::reverse(cstInteriorIndices)) { - auto arrayTy = mlir::dyn_cast(resultTy); + auto arrayTy = resultTy.dyn_cast(); if (!arrayTy) fir::emitFatalError( loc, @@ -1362,7 +1355,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { convertSubcomponentIndices(loc, resultTy, componentIndices, &resultTy); gepArgs.append(gepIndices.begin(), gepIndices.end()); if (substringOffset) { - if (auto arrayTy = mlir::dyn_cast(resultTy)) { + if (auto arrayTy = resultTy.dyn_cast()) { gepArgs.push_back(*substringOffset); resultTy = arrayTy.getElementType(); } else { @@ -1511,18 +1504,18 @@ struct XEmboxOpConversion : public EmboxCommonConversion { unsigned constRows = 0; mlir::Value ptrOffset = zero; mlir::Type memEleTy = fir::dyn_cast_ptrEleTy(xbox.getMemref().getType()); - assert(mlir::isa(memEleTy)); - auto seqTy = mlir::cast(memEleTy); + assert(memEleTy.isa()); + auto seqTy = memEleTy.cast(); mlir::Type seqEleTy = seqTy.getEleTy(); // Adjust the element scaling factor if the element is a dependent type. if (fir::hasDynamicSize(seqEleTy)) { - if (auto charTy = mlir::dyn_cast(seqEleTy)) { + if (auto charTy = seqEleTy.dyn_cast()) { // The GEP pointer type decays to llvm.ptr. // The scaling factor is the runtime value of the length. assert(!adaptor.getLenParams().empty()); prevPtrOff = FIROpConversion::integerCast( loc, rewriter, i64Ty, adaptor.getLenParams().back()); - } else if (mlir::isa(seqEleTy)) { + } else if (seqEleTy.isa()) { // prevPtrOff = ; TODO(loc, "generate call to calculate size of PDT"); } else { @@ -1547,7 +1540,7 @@ struct XEmboxOpConversion : public EmboxCommonConversion { } else if (hasSubstr) { // We have a substring. The step value needs to be the number of bytes // per CHARACTER element. - auto charTy = mlir::cast(seqEleTy); + auto charTy = seqEleTy.cast(); if (fir::hasDynamicSize(charTy)) { prevDimByteStride = getCharacterByteSize(loc, rewriter, charTy, adaptor.getLenParams()); @@ -1596,7 +1589,7 @@ struct XEmboxOpConversion : public EmboxCommonConversion { // Lower bound is normalized to 0 for BIND(C) interoperability. mlir::Value lb = zero; const bool isaPointerOrAllocatable = - mlir::isa(eleTy); + eleTy.isa() || eleTy.isa(); // Lower bound is defaults to 1 for POINTER, ALLOCATABLE, and // denormalized descriptors. if (isaPointerOrAllocatable || !normalizedLowerBound(xbox)) @@ -1702,7 +1695,7 @@ struct XReboxOpConversion : public EmboxCommonConversion { // Create new descriptor and fill its non-shape related data. llvm::SmallVector lenParams; mlir::Type inputEleTy = getInputEleTy(rebox); - if (auto charTy = mlir::dyn_cast(inputEleTy)) { + if (auto charTy = inputEleTy.dyn_cast()) { if (charTy.hasConstantLen()) { mlir::Value len = genConstantIndex(loc, idxTy, rewriter, charTy.getLen()); @@ -1719,15 +1712,15 @@ struct XReboxOpConversion : public EmboxCommonConversion { } lenParams.emplace_back(len); } - } else if (auto recTy = mlir::dyn_cast(inputEleTy)) { + } else if (auto recTy = inputEleTy.dyn_cast()) { if (recTy.getNumLenParams() != 0) TODO(loc, "reboxing descriptor of derived type with length parameters"); } // Rebox on polymorphic entities needs to carry over the dynamic type. mlir::Value typeDescAddr; - if (mlir::isa(inputBoxTyPair.fir) && - mlir::isa(rebox.getType())) + if (inputBoxTyPair.fir.isa() && + rebox.getType().isa()) typeDescAddr = loadTypeDescAddress(loc, inputBoxTyPair, loweredBox, rewriter); @@ -1915,7 +1908,7 @@ private: /// Return scalar element type of the input box. static mlir::Type getInputEleTy(fir::cg::XReboxOp rebox) { auto ty = fir::dyn_cast_ptrOrBoxEleTy(rebox.getBox().getType()); - if (auto seqTy = mlir::dyn_cast(ty)) + if (auto seqTy = ty.dyn_cast()) return seqTy.getEleTy(); return ty; } @@ -1943,7 +1936,7 @@ struct ValueOpCommon { assert(ty && "type is null"); const auto end = indices.size(); for (std::remove_const_t i = 0; i < end; ++i) { - if (auto seq = mlir::dyn_cast(ty)) { + if (auto seq = ty.dyn_cast()) { const auto dim = getDimension(seq); if (dim > 1) { auto ub = std::min(i + dim, end); @@ -1951,7 +1944,7 @@ struct ValueOpCommon { i += dim - 1; } ty = getArrayElementType(seq); - } else if (auto st = mlir::dyn_cast(ty)) { + } else if (auto st = ty.dyn_cast()) { ty = st.getBody()[indices[i]]; } else { llvm_unreachable("index into invalid type"); @@ -1970,7 +1963,7 @@ struct ValueOpCommon { auto fieldName = i->cast().getValue(); ++i; auto ty = i->cast().getValue(); - auto index = mlir::cast(ty).getFieldIndex(fieldName); + auto index = ty.cast().getFieldIndex(fieldName); indices.push_back(index); } } @@ -1980,7 +1973,7 @@ struct ValueOpCommon { private: static mlir::Type getArrayElementType(mlir::LLVM::LLVMArrayType ty) { auto eleTy = ty.getElementType(); - while (auto arrTy = mlir::dyn_cast(eleTy)) + while (auto arrTy = eleTy.dyn_cast()) eleTy = arrTy.getElementType(); return eleTy; } @@ -2048,7 +2041,7 @@ struct InsertOnRangeOpConversion auto type = adaptor.getOperands()[0].getType(); // Iteratively extract the array dimensions from the type. - while (auto t = mlir::dyn_cast(type)) { + while (auto t = type.dyn_cast()) { dims.push_back(t.getNumElements()); type = t.getElementType(); } @@ -2114,8 +2107,7 @@ struct XArrayCoorOpConversion mlir::Value offset = genConstantIndex(loc, idxTy, rewriter, 0); const bool isShifted = !coor.getShift().empty(); const bool isSliced = !coor.getSlice().empty(); - const bool baseIsBoxed = - mlir::isa(coor.getMemref().getType()); + const bool baseIsBoxed = coor.getMemref().getType().isa(); TypePair baseBoxTyPair = baseIsBoxed ? getBoxTypePair(coor.getMemref().getType()) : TypePair{}; mlir::LLVM::IntegerOverflowFlags nsw = @@ -2193,8 +2185,7 @@ struct XArrayCoorOpConversion // components. mlir::Type elementType = getLlvmObjectTypeFromBoxType(coor.getMemref().getType()); - while (auto arrayTy = - mlir::dyn_cast(elementType)) + while (auto arrayTy = elementType.dyn_cast()) elementType = arrayTy.getElementType(); args.clear(); args.push_back(0); @@ -2284,12 +2275,11 @@ struct CoordinateOpConversion } // Boxed type - get the base pointer from the box - if (mlir::dyn_cast(baseObjectTy)) + if (baseObjectTy.dyn_cast()) return doRewriteBox(coor, operands, loc, rewriter); // Reference, pointer or a heap type - if (mlir::isa( - baseObjectTy)) + if (baseObjectTy.isa()) return doRewriteRefOrPtr(coor, llvmObjectTy, operands, loc, rewriter); return rewriter.notifyMatchFailure( @@ -2305,7 +2295,7 @@ struct CoordinateOpConversion } static bool hasSubDimensions(mlir::Type type) { - return mlir::isa(type); + return type.isa(); } /// Check whether this form of `!fir.coordinate_of` is supported. These @@ -2320,14 +2310,14 @@ struct CoordinateOpConversion bool ptrEle = false; for (; i < numOfCoors; ++i) { mlir::Value nxtOpnd = coors[i]; - if (auto arrTy = mlir::dyn_cast(type)) { + if (auto arrTy = type.dyn_cast()) { subEle = true; i += arrTy.getDimension() - 1; type = arrTy.getEleTy(); - } else if (auto recTy = mlir::dyn_cast(type)) { + } else if (auto recTy = type.dyn_cast()) { subEle = true; type = recTy.getType(getFieldNumber(recTy, nxtOpnd)); - } else if (auto tupTy = mlir::dyn_cast(type)) { + } else if (auto tupTy = type.dyn_cast()) { subEle = true; type = tupTy.getType(getConstantIntValue(nxtOpnd)); } else { @@ -2345,14 +2335,14 @@ struct CoordinateOpConversion static bool arraysHaveKnownShape(mlir::Type type, mlir::ValueRange coors) { for (std::size_t i = 0, sz = coors.size(); i < sz; ++i) { mlir::Value nxtOpnd = coors[i]; - if (auto arrTy = mlir::dyn_cast(type)) { + if (auto arrTy = type.dyn_cast()) { if (fir::sequenceWithNonConstantShape(arrTy)) return false; i += arrTy.getDimension() - 1; type = arrTy.getEleTy(); - } else if (auto strTy = mlir::dyn_cast(type)) { + } else if (auto strTy = type.dyn_cast()) { type = strTy.getType(getFieldNumber(strTy, nxtOpnd)); - } else if (auto strTy = mlir::dyn_cast(type)) { + } else if (auto strTy = type.dyn_cast()) { type = strTy.getType(getConstantIntValue(nxtOpnd)); } else { return true; @@ -2367,8 +2357,7 @@ private: mlir::Location loc, mlir::ConversionPatternRewriter &rewriter) const { mlir::Type boxObjTy = coor.getBaseType(); - assert(mlir::dyn_cast(boxObjTy) && - "This is not a `fir.box`"); + assert(boxObjTy.dyn_cast() && "This is not a `fir.box`"); TypePair boxTyPair = getBoxTypePair(boxObjTy); mlir::Value boxBaseAddr = operands[0]; @@ -2410,7 +2399,7 @@ private: mlir::LLVM::IntegerOverflowFlags::nsw; for (unsigned i = 1, last = operands.size(); i < last; ++i) { - if (auto arrTy = mlir::dyn_cast(cpnTy)) { + if (auto arrTy = cpnTy.dyn_cast()) { if (i != 1) TODO(loc, "fir.array nested inside other array and/or derived type"); // Applies byte strides from the box. Ignore lower bound from box @@ -2432,7 +2421,7 @@ private: llvm::ArrayRef{off}); i += arrTy.getDimension() - 1; cpnTy = arrTy.getEleTy(); - } else if (auto recTy = mlir::dyn_cast(cpnTy)) { + } else if (auto recTy = cpnTy.dyn_cast()) { mlir::Value nxtOpnd = operands[i]; cpnTy = recTy.getType(getFieldNumber(recTy, nxtOpnd)); auto llvmRecTy = lowerTy().convertType(recTy); @@ -2467,7 +2456,7 @@ private: // If only the column is `?`, then we can simply place the column value in // the 0-th GEP position. - if (auto arrTy = mlir::dyn_cast(cpnTy)) { + if (auto arrTy = cpnTy.dyn_cast()) { if (!hasKnownShape) { const unsigned sz = arrTy.getDimension(); if (arraysHaveKnownShape(arrTy.getEleTy(), @@ -2511,29 +2500,29 @@ private: dims = dimsLeft - 1; continue; } - cpnTy = mlir::cast(cpnTy).getEleTy(); + cpnTy = cpnTy.cast().getEleTy(); // append array range in reverse (FIR arrays are column-major) offs.append(arrIdx.rbegin(), arrIdx.rend()); arrIdx.clear(); dims.reset(); continue; } - if (auto arrTy = mlir::dyn_cast(cpnTy)) { + if (auto arrTy = cpnTy.dyn_cast()) { int d = arrTy.getDimension() - 1; if (d > 0) { dims = d; arrIdx.push_back(nxtOpnd); continue; } - cpnTy = mlir::cast(cpnTy).getEleTy(); + cpnTy = cpnTy.cast().getEleTy(); offs.push_back(nxtOpnd); continue; } // check if the i-th coordinate relates to a field - if (auto recTy = mlir::dyn_cast(cpnTy)) + if (auto recTy = cpnTy.dyn_cast()) cpnTy = recTy.getType(getFieldNumber(recTy, nxtOpnd)); - else if (auto tupTy = mlir::dyn_cast(cpnTy)) + else if (auto tupTy = cpnTy.dyn_cast()) cpnTy = tupTy.getType(getConstantIntValue(nxtOpnd)); else cpnTy = nullptr; @@ -2562,7 +2551,7 @@ struct FieldIndexOpConversion : public fir::FIROpConversion { mlir::LogicalResult matchAndRewrite(fir::FieldIndexOp field, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { - auto recTy = mlir::cast(field.getOnType()); + auto recTy = field.getOnType().cast(); unsigned index = recTy.getFieldIndex(field.getFieldId()); if (!fir::hasDynamicSize(recTy)) { @@ -2615,8 +2604,8 @@ struct TypeDescOpConversion : public fir::FIROpConversion { matchAndRewrite(fir::TypeDescOp typeDescOp, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { mlir::Type inTy = typeDescOp.getInType(); - assert(mlir::isa(inTy) && "expecting fir.type"); - auto recordType = mlir::dyn_cast(inTy); + assert(inTy.isa() && "expecting fir.type"); + auto recordType = inTy.dyn_cast(); auto module = typeDescOp.getOperation()->getParentOfType(); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recordType.getName()); @@ -2743,7 +2732,7 @@ struct GlobalOpConversion : public fir::FIROpConversion { mlir::Type vecType = mlir::VectorType::get( insertOp.getType().getShape(), constant.getType()); auto denseAttr = mlir::DenseElementsAttr::get( - mlir::cast(vecType), constant.getValue()); + vecType.cast(), constant.getValue()); rewriter.setInsertionPointAfter(insertOp); rewriter.replaceOpWithNewOp( insertOp, seqTyAttr, denseAttr); @@ -2819,7 +2808,7 @@ struct LoadOpConversion : public fir::FIROpConversion { matchAndRewrite(fir::LoadOp load, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { mlir::Type llvmLoadTy = convertObjectType(load.getType()); - if (auto boxTy = mlir::dyn_cast(load.getType())) { + if (auto boxTy = load.getType().dyn_cast()) { // fir.box is a special case because it is considered as an ssa values in // fir, but it is lowered as a pointer to a descriptor. So // fir.ref and fir.box end up being the same llvm types and @@ -2932,7 +2921,7 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { llvm::ArrayRef cases = caseOp.getCases().getValue(); // Type can be CHARACTER, INTEGER, or LOGICAL (C1145) auto ty = caseOp.getSelector().getType(); - if (mlir::isa(ty)) { + if (ty.isa()) { TODO(caseOp.getLoc(), "fir.select_case codegen with character type"); return mlir::failure(); } @@ -2946,25 +2935,25 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { *caseOp.getCompareOperands(adaptor.getOperands(), t); mlir::Value caseArg = *(cmpOps.value().begin()); mlir::Attribute attr = cases[t]; - if (mlir::isa(attr)) { + if (attr.isa()) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::eq, selector, caseArg); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (mlir::isa(attr)) { + if (attr.isa()) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, caseArg, selector); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (mlir::isa(attr)) { + if (attr.isa()) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, selector, caseArg); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (mlir::isa(attr)) { + if (attr.isa()) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, caseArg, selector); auto *thisBlock = rewriter.getInsertionBlock(); @@ -2980,7 +2969,7 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { rewriter.setInsertionPointToEnd(newBlock2); continue; } - assert(mlir::isa(attr)); + assert(attr.isa()); assert((t + 1 == conds) && "unit must be last"); genBrOp(caseOp, dest, destOps, rewriter); } @@ -3008,7 +2997,7 @@ static void selectMatchAndRewrite(const fir::LLVMTypeConverter &lowering, mlir::Block *dest = select.getSuccessor(t); auto destOps = select.getSuccessorOperands(adaptor.getOperands(), t); const mlir::Attribute &attr = cases[t]; - if (auto intAttr = mlir::dyn_cast(attr)) { + if (auto intAttr = attr.template dyn_cast()) { destinations.push_back(dest); destinationsOperands.push_back(destOps ? *destOps : mlir::ValueRange{}); caseValues.push_back(intAttr.getInt()); @@ -3082,7 +3071,7 @@ struct StoreOpConversion : public fir::FIROpConversion { mlir::Location loc = store.getLoc(); mlir::Type storeTy = store.getValue().getType(); mlir::LLVM::StoreOp newStoreOp; - if (auto boxTy = mlir::dyn_cast(storeTy)) { + if (auto boxTy = storeTy.dyn_cast()) { // fir.box value is actually in memory, load it first before storing it. mlir::Type llvmBoxTy = lowerTy().convertBoxTypeAsStruct(boxTy); auto val = rewriter.create(loc, llvmBoxTy, @@ -3197,9 +3186,9 @@ struct IsPresentOpConversion : public fir::FIROpConversion { mlir::Location loc = isPresent.getLoc(); auto ptr = adaptor.getOperands()[0]; - if (mlir::isa(isPresent.getVal().getType())) { + if (isPresent.getVal().getType().isa()) { [[maybe_unused]] auto structTy = - mlir::cast(ptr.getType()); + ptr.getType().cast(); assert(!structTy.isOpaque() && !structTy.getBody().empty()); ptr = rewriter.create(loc, ptr, 0); @@ -3225,8 +3214,8 @@ struct AbsentOpConversion : public fir::FIROpConversion { mlir::Type ty = convertType(absent.getType()); mlir::Location loc = absent.getLoc(); - if (mlir::isa(absent.getType())) { - auto structTy = mlir::cast(ty); + if (absent.getType().isa()) { + auto structTy = ty.cast(); assert(!structTy.isOpaque() && !structTy.getBody().empty()); auto undefStruct = rewriter.create(loc, ty); auto nullField = diff --git a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp index 00c5f77cde7c..26871d888815 100644 --- a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp +++ b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp @@ -20,7 +20,7 @@ static inline mlir::Type getLlvmPtrType(mlir::MLIRContext *context, } static unsigned getTypeDescFieldId(mlir::Type ty) { - auto isArray = mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(ty)); + auto isArray = fir::dyn_cast_ptrOrBoxEleTy(ty).isa(); return isArray ? kOptTypePtrPosInBox : kDimsPosInBox; } @@ -37,7 +37,7 @@ ConvertFIRToLLVMPattern::ConvertFIRToLLVMPattern( // reference. mlir::Type ConvertFIRToLLVMPattern::convertObjectType(mlir::Type firType) const { - if (auto boxTy = mlir::dyn_cast(firType)) + if (auto boxTy = firType.dyn_cast()) return lowerTy().convertBoxTypeAsStruct(boxTy); return lowerTy().convertType(firType); } @@ -69,7 +69,7 @@ ConvertFIRToLLVMPattern::integerCast(mlir::Location loc, auto valTy = val.getType(); // If the value was not yet lowered, lower its type so that it can // be used in getPrimitiveTypeSizeInBits. - if (!mlir::isa(valTy)) + if (!valTy.isa()) valTy = convertType(valTy); auto toSize = mlir::LLVM::getPrimitiveTypeSizeInBits(ty); auto fromSize = mlir::LLVM::getPrimitiveTypeSizeInBits(valTy); @@ -91,7 +91,7 @@ ConvertFIRToLLVMPattern::getBoxTypePair(mlir::Type firBoxTy) const { mlir::Value ConvertFIRToLLVMPattern::getValueFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, mlir::Type resultTy, mlir::ConversionPatternRewriter &rewriter, int boxValue) const { - if (mlir::isa(box.getType())) { + if (box.getType().isa()) { auto pty = getLlvmPtrType(resultTy.getContext()); auto p = rewriter.create( loc, pty, boxTy.llvm, box, @@ -133,7 +133,7 @@ llvm::SmallVector ConvertFIRToLLVMPattern::getDimsFromBox( mlir::Value ConvertFIRToLLVMPattern::loadDimFieldFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, mlir::Value dim, int off, mlir::Type ty, mlir::ConversionPatternRewriter &rewriter) const { - assert(mlir::isa(box.getType()) && + assert(box.getType().isa() && "descriptor inquiry with runtime dim can only be done on descriptor " "in memory"); mlir::LLVM::GEPOp p = genGEP(loc, boxTy.llvm, rewriter, box, 0, @@ -146,7 +146,7 @@ mlir::Value ConvertFIRToLLVMPattern::loadDimFieldFromBox( mlir::Value ConvertFIRToLLVMPattern::getDimFieldFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, int dim, int off, mlir::Type ty, mlir::ConversionPatternRewriter &rewriter) const { - if (mlir::isa(box.getType())) { + if (box.getType().isa()) { mlir::LLVM::GEPOp p = genGEP(loc, boxTy.llvm, rewriter, box, 0, static_cast(kDimsPosInBox), dim, off); auto loadOp = rewriter.create(loc, ty, p); @@ -184,12 +184,12 @@ mlir::Value ConvertFIRToLLVMPattern::getElementSizeFromBox( mlir::Type ConvertFIRToLLVMPattern::getBoxEleTy( mlir::Type type, llvm::ArrayRef indexes) const { for (unsigned i : indexes) { - if (auto t = mlir::dyn_cast(type)) { + if (auto t = type.dyn_cast()) { assert(!t.isOpaque() && i < t.getBody().size()); type = t.getBody()[i]; - } else if (auto t = mlir::dyn_cast(type)) { + } else if (auto t = type.dyn_cast()) { type = t.getElementType(); - } else if (auto t = mlir::dyn_cast(type)) { + } else if (auto t = type.dyn_cast()) { type = t.getElementType(); } else { fir::emitFatalError(mlir::UnknownLoc::get(type.getContext()), diff --git a/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp b/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp index ce7ee22d5d77..665bf09b8fc3 100644 --- a/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp +++ b/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp @@ -86,10 +86,10 @@ public: // If the embox does not include a shape, then do not convert it if (auto shapeVal = embox.getShape()) return rewriteDynamicShape(embox, rewriter, shapeVal); - if (mlir::isa(embox.getType())) + if (embox.getType().isa()) TODO(embox.getLoc(), "embox conversion for fir.class type"); - if (auto boxTy = mlir::dyn_cast(embox.getType())) - if (auto seqTy = mlir::dyn_cast(boxTy.getEleTy())) + if (auto boxTy = embox.getType().dyn_cast()) + if (auto seqTy = boxTy.getEleTy().dyn_cast()) if (!seqTy.hasDynamicExtents()) return rewriteStaticShape(embox, rewriter, seqTy); return mlir::failure(); @@ -294,9 +294,10 @@ public: target.addIllegalOp(); target.addIllegalOp(); target.addDynamicallyLegalOp([](fir::EmboxOp embox) { - return !(embox.getShape() || - mlir::isa( - mlir::cast(embox.getType()).getEleTy())); + return !(embox.getShape() || embox.getType() + .cast() + .getEleTy() + .isa()); }); mlir::RewritePatternSet patterns(&context); fir::populatePreCGRewritePatterns(patterns); diff --git a/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp b/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp index a21384e8d594..b1b0e9b766a6 100644 --- a/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp +++ b/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp @@ -120,7 +120,7 @@ void TBAABuilder::attachTBAATag(AliasAnalysisOpInterface op, Type baseFIRType, // with both data and descriptor accesses. // Conservatively set any-access tag if there is any descriptor member. tbaaTagSym = getAnyAccessTag(func); - } else if (mlir::isa(baseFIRType)) { + } else if (baseFIRType.isa()) { tbaaTagSym = getBoxAccessTag(baseFIRType, accessFIRType, gep, func); } else { tbaaTagSym = getDataAccessTag(baseFIRType, accessFIRType, gep, func); diff --git a/flang/lib/Optimizer/CodeGen/Target.cpp b/flang/lib/Optimizer/CodeGen/Target.cpp index 652e2bddc1b8..cea7a1f97f41 100644 --- a/flang/lib/Optimizer/CodeGen/Target.cpp +++ b/flang/lib/Optimizer/CodeGen/Target.cpp @@ -41,9 +41,9 @@ llvm::StringRef Attributes::getIntExtensionAttrName() const { static const llvm::fltSemantics &floatToSemantics(const KindMapping &kindMap, mlir::Type type) { assert(isa_real(type)); - if (auto ty = mlir::dyn_cast(type)) + if (auto ty = type.dyn_cast()) return kindMap.getFloatSemantics(ty.getFKind()); - return mlir::cast(type).getFloatSemantics(); + return type.cast().getFloatSemantics(); } static void typeTodo(const llvm::fltSemantics *sem, mlir::Location loc, diff --git a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp index 616de78d0026..7bf31ec38695 100644 --- a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp +++ b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp @@ -137,7 +137,7 @@ public: if (!hasPortableSignature(dispatch.getFunctionType(), op)) convertCallOp(dispatch); } else if (auto addr = mlir::dyn_cast(op)) { - if (mlir::isa(addr.getType()) && + if (addr.getType().isa() && !hasPortableSignature(addr.getType(), op)) convertAddrOp(addr); } @@ -601,7 +601,7 @@ public: /// Taking the address of a function. Modify the signature as needed. void convertAddrOp(fir::AddrOfOp addrOp) { rewriter->setInsertionPoint(addrOp); - auto addrTy = mlir::cast(addrOp.getType()); + auto addrTy = addrOp.getType().cast(); fir::CodeGenSpecifics::Marshalling newInTyAndAttrs; llvm::SmallVector newResTys; auto loc = addrOp.getLoc(); @@ -705,23 +705,22 @@ public: /// return `true`. Otherwise, the signature is not portable and `false` is /// returned. bool hasPortableSignature(mlir::Type signature, mlir::Operation *op) { - assert(mlir::isa(signature)); - auto func = mlir::dyn_cast(signature); + assert(signature.isa()); + auto func = signature.dyn_cast(); bool hasCCallingConv = isFuncWithCCallingConvention(op); for (auto ty : func.getResults()) - if ((mlir::isa(ty) && !noCharacterConversion) || + if ((ty.isa() && !noCharacterConversion) || (fir::isa_complex(ty) && !noComplexConversion) || - (mlir::isa(ty) && hasCCallingConv)) { + (ty.isa() && hasCCallingConv)) { LLVM_DEBUG(llvm::dbgs() << "rewrite " << signature << " for target\n"); return false; } for (auto ty : func.getInputs()) - if (((mlir::isa(ty) || - fir::isCharacterProcedureTuple(ty)) && + if (((ty.isa() || fir::isCharacterProcedureTuple(ty)) && !noCharacterConversion) || (fir::isa_complex(ty) && !noComplexConversion) || - (mlir::isa(ty) && hasCCallingConv) || - (mlir::isa(ty) && !noStructConversion)) { + (ty.isa() && hasCCallingConv) || + (ty.isa() && !noStructConversion)) { LLVM_DEBUG(llvm::dbgs() << "rewrite " << signature << " for target\n"); return false; } @@ -741,7 +740,7 @@ public: /// Rewrite the signatures and body of the `FuncOp`s in the module for /// the immediately subsequent target code gen. void convertSignature(mlir::func::FuncOp func) { - auto funcTy = mlir::cast(func.getFunctionType()); + auto funcTy = func.getFunctionType().cast(); if (hasPortableSignature(funcTy, func) && !hasHostAssociations(func)) return; llvm::SmallVector newResTys; diff --git a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp index fb2ec3f0b2f5..8fa423f35806 100644 --- a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp +++ b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp @@ -103,10 +103,10 @@ LLVMTypeConverter::LLVMTypeConverter(mlir::ModuleOp module, bool applyTBAA, for (auto mem : tuple.getTypes()) { // Prevent fir.box from degenerating to a pointer to a descriptor in the // context of a tuple type. - if (auto box = mlir::dyn_cast(mem)) + if (auto box = mem.dyn_cast()) members.push_back(convertBoxTypeAsStruct(box)); else - members.push_back(mlir::cast(convertType(mem))); + members.push_back(convertType(mem).cast()); } return mlir::LLVM::LLVMStructType::getLiteral(&getContext(), members, /*isPacked=*/false); @@ -181,10 +181,10 @@ std::optional LLVMTypeConverter::convertRecordType( for (auto mem : derived.getTypeList()) { // Prevent fir.box from degenerating to a pointer to a descriptor in the // context of a record type. - if (auto box = mlir::dyn_cast(mem.second)) + if (auto box = mem.second.dyn_cast()) members.push_back(convertBoxTypeAsStruct(box)); else - members.push_back(mlir::cast(convertType(mem.second))); + members.push_back(convertType(mem.second).cast()); } if (mlir::failed(st.setBody(members, /*isPacked=*/false))) return mlir::failure(); @@ -196,7 +196,7 @@ std::optional LLVMTypeConverter::convertRecordType( // Extended descriptors are required for derived types. bool LLVMTypeConverter::requiresExtendedDesc(mlir::Type boxElementType) const { auto eleTy = fir::unwrapSequenceType(boxElementType); - return mlir::isa(eleTy); + return eleTy.isa(); } // This corresponds to the descriptor as defined in ISO_Fortran_binding.h and @@ -211,8 +211,7 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, ele = removeIndirection; auto eleTy = convertType(ele); // base_addr* - if (mlir::isa(ele) && - mlir::isa(eleTy)) + if (ele.isa() && eleTy.isa()) dataDescFields.push_back(eleTy); else dataDescFields.push_back( @@ -237,7 +236,7 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, getDescFieldTypeModel()(&getContext())); // [dims] if (rank == unknownRank()) { - if (auto seqTy = mlir::dyn_cast(ele)) + if (auto seqTy = ele.dyn_cast()) rank = seqTy.getDimension(); else rank = 0; @@ -253,8 +252,7 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, auto rowTy = getExtendedDescFieldTypeModel()(&getContext()); dataDescFields.push_back(mlir::LLVM::LLVMArrayType::get(rowTy, 1)); - if (auto recTy = - mlir::dyn_cast(fir::unwrapSequenceType(ele))) + if (auto recTy = fir::unwrapSequenceType(ele).dyn_cast()) if (recTy.getNumLenParams() > 0) { // The descriptor design needs to be clarified regarding the number of // length parameters in the addendum. Since it can change for diff --git a/flang/lib/Optimizer/Dialect/FIRAttr.cpp b/flang/lib/Optimizer/Dialect/FIRAttr.cpp index 9ea3a0568f69..e43710f5627e 100644 --- a/flang/lib/Optimizer/Dialect/FIRAttr.cpp +++ b/flang/lib/Optimizer/Dialect/FIRAttr.cpp @@ -264,23 +264,23 @@ void fir::FortranVariableFlagsAttr::print(mlir::AsmPrinter &printer) const { void fir::printFirAttribute(FIROpsDialect *dialect, mlir::Attribute attr, mlir::DialectAsmPrinter &p) { auto &os = p.getStream(); - if (auto exact = mlir::dyn_cast(attr)) { + if (auto exact = attr.dyn_cast()) { os << fir::ExactTypeAttr::getAttrName() << '<'; p.printType(exact.getType()); os << '>'; - } else if (auto sub = mlir::dyn_cast(attr)) { + } else if (auto sub = attr.dyn_cast()) { os << fir::SubclassAttr::getAttrName() << '<'; p.printType(sub.getType()); os << '>'; - } else if (mlir::dyn_cast_or_null(attr)) { + } else if (attr.dyn_cast_or_null()) { os << fir::PointIntervalAttr::getAttrName(); - } else if (mlir::dyn_cast_or_null(attr)) { + } else if (attr.dyn_cast_or_null()) { os << fir::ClosedIntervalAttr::getAttrName(); - } else if (mlir::dyn_cast_or_null(attr)) { + } else if (attr.dyn_cast_or_null()) { os << fir::LowerBoundAttr::getAttrName(); - } else if (mlir::dyn_cast_or_null(attr)) { + } else if (attr.dyn_cast_or_null()) { os << fir::UpperBoundAttr::getAttrName(); - } else if (auto a = mlir::dyn_cast_or_null(attr)) { + } else if (auto a = attr.dyn_cast_or_null()) { os << fir::RealAttr::getAttrName() << '<' << a.getFKind() << ", i x"; llvm::SmallString<40> ss; a.getValue().bitcastToAPInt().toStringUnsigned(ss, 16); diff --git a/flang/lib/Optimizer/Dialect/FIROps.cpp b/flang/lib/Optimizer/Dialect/FIROps.cpp index a39087aeb358..24af94f9b90a 100644 --- a/flang/lib/Optimizer/Dialect/FIROps.cpp +++ b/flang/lib/Optimizer/Dialect/FIROps.cpp @@ -57,7 +57,7 @@ static void propagateAttributes(mlir::Operation *fromOp, static bool verifyInType(mlir::Type inType, llvm::SmallVectorImpl &visited, unsigned dynamicExtents = 0) { - if (auto st = mlir::dyn_cast(inType)) { + if (auto st = inType.dyn_cast()) { auto shape = st.getShape(); if (shape.size() == 0) return true; @@ -67,7 +67,7 @@ static bool verifyInType(mlir::Type inType, if (dynamicExtents-- == 0) return true; } - } else if (auto rt = mlir::dyn_cast(inType)) { + } else if (auto rt = inType.dyn_cast()) { // don't recurse if we're already visiting this one if (llvm::is_contained(visited, rt.getName())) return false; @@ -84,13 +84,13 @@ static bool verifyInType(mlir::Type inType, static bool verifyTypeParamCount(mlir::Type inType, unsigned numParams) { auto ty = fir::unwrapSequenceType(inType); if (numParams > 0) { - if (auto recTy = mlir::dyn_cast(ty)) + if (auto recTy = ty.dyn_cast()) return numParams != recTy.getNumLenParams(); - if (auto chrTy = mlir::dyn_cast(ty)) + if (auto chrTy = ty.dyn_cast()) return !(numParams == 1 && chrTy.hasDynamicLen()); return true; } - if (auto chrTy = mlir::dyn_cast(ty)) + if (auto chrTy = ty.dyn_cast()) return !chrTy.hasConstantLen(); return false; } @@ -171,13 +171,13 @@ static void printAllocatableOp(mlir::OpAsmPrinter &p, OP &op) { /// Create a legal memory reference as return type static mlir::Type wrapAllocaResultType(mlir::Type intype) { // FIR semantics: memory references to memory references are disallowed - if (mlir::isa(intype)) + if (intype.isa()) return {}; return fir::ReferenceType::get(intype); } mlir::Type fir::AllocaOp::getAllocatedType() { - return mlir::cast(getType()).getEleTy(); + return getType().cast().getEleTy(); } mlir::Type fir::AllocaOp::getRefTy(mlir::Type ty) { @@ -270,7 +270,7 @@ mlir::LogicalResult fir::AllocaOp::verify() { if (verifyTypeParamCount(getInType(), numLenParams())) return emitOpError("LEN params do not correspond to type"); mlir::Type outType = getType(); - if (!mlir::isa(outType)) + if (!outType.isa()) return emitOpError("must be a !fir.ref type"); if (fir::isa_unknown_size_box(fir::dyn_cast_ptrEleTy(outType))) return emitOpError("cannot allocate !fir.box of unknown rank or type"); @@ -286,14 +286,14 @@ static mlir::Type wrapAllocMemResultType(mlir::Type intype) { // Fortran semantics: C852 an entity cannot be both ALLOCATABLE and POINTER // 8.5.3 note 1 prohibits ALLOCATABLE procedures as well // FIR semantics: one may not allocate a memory reference value - if (mlir::isa(intype)) + if (intype.isa()) return {}; return fir::HeapType::get(intype); } mlir::Type fir::AllocMemOp::getAllocatedType() { - return mlir::cast(getType()).getEleTy(); + return getType().cast().getEleTy(); } mlir::Type fir::AllocMemOp::getRefTy(mlir::Type ty) { @@ -348,7 +348,7 @@ mlir::LogicalResult fir::AllocMemOp::verify() { if (verifyTypeParamCount(getInType(), numLenParams())) return emitOpError("LEN params do not correspond to type"); mlir::Type outType = getType(); - if (!mlir::dyn_cast(outType)) + if (!outType.dyn_cast()) return emitOpError("must be a !fir.heap type"); if (fir::isa_unknown_size_box(fir::dyn_cast_ptrEleTy(outType))) return emitOpError("cannot allocate !fir.box of unknown rank or type"); @@ -364,13 +364,13 @@ mlir::LogicalResult fir::AllocMemOp::verify() { static bool validTypeParams(mlir::Type dynTy, mlir::ValueRange typeParams) { dynTy = fir::unwrapAllRefAndSeqType(dynTy); // A box value will contain type parameter values itself. - if (mlir::isa(dynTy)) + if (dynTy.isa()) return typeParams.size() == 0; // Derived type must have all type parameters satisfied. - if (auto recTy = mlir::dyn_cast(dynTy)) + if (auto recTy = dynTy.dyn_cast()) return typeParams.size() == recTy.getNumLenParams(); // Characters with non-constant LEN must have a type parameter value. - if (auto charTy = mlir::dyn_cast(dynTy)) + if (auto charTy = dynTy.dyn_cast()) if (charTy.hasDynamicLen()) return typeParams.size() == 1; // Otherwise, any type parameters are invalid. @@ -379,7 +379,7 @@ static bool validTypeParams(mlir::Type dynTy, mlir::ValueRange typeParams) { mlir::LogicalResult fir::ArrayCoorOp::verify() { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - auto arrTy = mlir::dyn_cast(eleTy); + auto arrTy = eleTy.dyn_cast(); if (!arrTy) return emitOpError("must be a reference to an array"); auto arrDim = arrTy.getDimension(); @@ -387,14 +387,14 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { if (auto shapeOp = getShape()) { auto shapeTy = shapeOp.getType(); unsigned shapeTyRank = 0; - if (auto s = mlir::dyn_cast(shapeTy)) { + if (auto s = shapeTy.dyn_cast()) { shapeTyRank = s.getRank(); - } else if (auto ss = mlir::dyn_cast(shapeTy)) { + } else if (auto ss = shapeTy.dyn_cast()) { shapeTyRank = ss.getRank(); } else { - auto s = mlir::cast(shapeTy); + auto s = shapeTy.cast(); shapeTyRank = s.getRank(); - if (!mlir::isa(getMemref().getType())) + if (!getMemref().getType().isa()) return emitOpError("shift can only be provided with fir.box memref"); } if (arrDim && arrDim != shapeTyRank) @@ -407,7 +407,7 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { if (auto sl = mlir::dyn_cast_or_null(sliceOp.getDefiningOp())) if (!sl.getSubstr().empty()) return emitOpError("array_coor cannot take a slice with substring"); - if (auto sliceTy = mlir::dyn_cast(sliceOp.getType())) + if (auto sliceTy = sliceOp.getType().dyn_cast()) if (sliceTy.getRank() != arrDim) return emitOpError("rank of dimension in slice mismatched"); } @@ -422,13 +422,13 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { //===----------------------------------------------------------------------===// static mlir::Type adjustedElementType(mlir::Type t) { - if (auto ty = mlir::dyn_cast(t)) { + if (auto ty = t.dyn_cast()) { auto eleTy = ty.getEleTy(); if (fir::isa_char(eleTy)) return eleTy; if (fir::isa_derived(eleTy)) return eleTy; - if (mlir::isa(eleTy)) + if (eleTy.isa()) return eleTy; } return t; @@ -448,7 +448,7 @@ std::vector fir::ArrayLoadOp::getExtents() { mlir::LogicalResult fir::ArrayLoadOp::verify() { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - auto arrTy = mlir::dyn_cast(eleTy); + auto arrTy = eleTy.dyn_cast(); if (!arrTy) return emitOpError("must be a reference to an array"); auto arrDim = arrTy.getDimension(); @@ -456,14 +456,14 @@ mlir::LogicalResult fir::ArrayLoadOp::verify() { if (auto shapeOp = getShape()) { auto shapeTy = shapeOp.getType(); unsigned shapeTyRank = 0u; - if (auto s = mlir::dyn_cast(shapeTy)) { + if (auto s = shapeTy.dyn_cast()) { shapeTyRank = s.getRank(); - } else if (auto ss = mlir::dyn_cast(shapeTy)) { + } else if (auto ss = shapeTy.dyn_cast()) { shapeTyRank = ss.getRank(); } else { - auto s = mlir::cast(shapeTy); + auto s = shapeTy.cast(); shapeTyRank = s.getRank(); - if (!mlir::isa(getMemref().getType())) + if (!getMemref().getType().isa()) return emitOpError("shift can only be provided with fir.box memref"); } if (arrDim && arrDim != shapeTyRank) @@ -474,7 +474,7 @@ mlir::LogicalResult fir::ArrayLoadOp::verify() { if (auto sl = mlir::dyn_cast_or_null(sliceOp.getDefiningOp())) if (!sl.getSubstr().empty()) return emitOpError("array_load cannot take a slice with substring"); - if (auto sliceTy = mlir::dyn_cast(sliceOp.getType())) + if (auto sliceTy = sliceOp.getType().dyn_cast()) if (sliceTy.getRank() != arrDim) return emitOpError("rank of dimension in slice mismatched"); } @@ -502,7 +502,7 @@ mlir::LogicalResult fir::ArrayMergeStoreOp::verify() { // This is an intra-object merge, where the slice is projecting the // subfields that are to be overwritten by the merge operation. auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - if (auto seqTy = mlir::dyn_cast(eleTy)) { + if (auto seqTy = eleTy.dyn_cast()) { auto projTy = fir::applyPathToType(seqTy.getEleTy(), sliceOp.getFields()); if (fir::unwrapSequenceType(getOriginal().getType()) != projTy) @@ -540,7 +540,7 @@ mlir::Type validArraySubobject(A op) { } mlir::LogicalResult fir::ArrayFetchOp::verify() { - auto arrTy = mlir::cast(getSequence().getType()); + auto arrTy = getSequence().getType().cast(); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -562,7 +562,7 @@ mlir::LogicalResult fir::ArrayFetchOp::verify() { //===----------------------------------------------------------------------===// mlir::LogicalResult fir::ArrayAccessOp::verify() { - auto arrTy = mlir::cast(getSequence().getType()); + auto arrTy = getSequence().getType().cast(); std::size_t indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -584,7 +584,7 @@ mlir::LogicalResult fir::ArrayAccessOp::verify() { mlir::LogicalResult fir::ArrayUpdateOp::verify() { if (fir::isa_ref_type(getMerge().getType())) return emitOpError("does not support reference type for merge"); - auto arrTy = mlir::cast(getSequence().getType()); + auto arrTy = getSequence().getType().cast(); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -604,7 +604,7 @@ mlir::LogicalResult fir::ArrayUpdateOp::verify() { //===----------------------------------------------------------------------===// mlir::LogicalResult fir::ArrayModifyOp::verify() { - auto arrTy = mlir::cast(getSequence().getType()); + auto arrTy = getSequence().getType().cast(); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices must match array dimension"); @@ -740,7 +740,7 @@ mlir::ParseResult fir::CallOp::parse(mlir::OpAsmParser &parser, parser.parseType(type)) return mlir::failure(); - auto funcType = mlir::dyn_cast(type); + auto funcType = type.dyn_cast(); if (!funcType) return parser.emitError(parser.getNameLoc(), "expected function type"); if (isDirect) { @@ -785,7 +785,7 @@ void fir::CallOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, mlir::LogicalResult fir::CharConvertOp::verify() { auto unwrap = [&](mlir::Type t) { t = fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t)); - return mlir::dyn_cast(t); + return t.dyn_cast(); }; auto inTy = unwrap(getFrom().getType()); auto outTy = unwrap(getTo().getType()); @@ -832,13 +832,13 @@ static mlir::ParseResult parseCmpOp(mlir::OpAsmParser &parser, parser.resolveOperands(ops, type, result.operands)) return mlir::failure(); - if (!mlir::isa(predicateNameAttr)) + if (!predicateNameAttr.isa()) return parser.emitError(parser.getNameLoc(), "expected string comparison predicate attribute"); // Rewrite string attribute to an enum value. llvm::StringRef predicateName = - mlir::cast(predicateNameAttr).getValue(); + predicateNameAttr.cast().getValue(); auto predicate = fir::CmpcOp::getPredicateByName(predicateName); auto builder = parser.getBuilder(); mlir::Type i1Type = builder.getI1Type(); @@ -906,7 +906,7 @@ void fir::ConstcOp::print(mlir::OpAsmPrinter &p) { } mlir::LogicalResult fir::ConstcOp::verify() { - if (!mlir::isa(getType())) + if (!getType().isa()) return emitOpError("must be a !fir.complex type"); return mlir::success(); } @@ -929,16 +929,15 @@ mlir::OpFoldResult fir::ConvertOp::fold(FoldAdaptor adaptor) { if (matchPattern(getValue(), mlir::m_Op())) { auto inner = mlir::cast(getValue().getDefiningOp()); // (convert (convert 'a : logical -> i1) : i1 -> logical) ==> forward 'a - if (auto toTy = mlir::dyn_cast(getType())) - if (auto fromTy = - mlir::dyn_cast(inner.getValue().getType())) - if (mlir::isa(inner.getType()) && (toTy == fromTy)) + if (auto toTy = getType().dyn_cast()) + if (auto fromTy = inner.getValue().getType().dyn_cast()) + if (inner.getType().isa() && (toTy == fromTy)) return inner.getValue(); // (convert (convert 'a : i1 -> logical) : logical -> i1) ==> forward 'a - if (auto toTy = mlir::dyn_cast(getType())) + if (auto toTy = getType().dyn_cast()) if (auto fromTy = - mlir::dyn_cast(inner.getValue().getType())) - if (mlir::isa(inner.getType()) && (toTy == fromTy) && + inner.getValue().getType().dyn_cast()) + if (inner.getType().isa() && (toTy == fromTy) && (fromTy.getWidth() == 1)) return inner.getValue(); } @@ -946,7 +945,7 @@ mlir::OpFoldResult fir::ConvertOp::fold(FoldAdaptor adaptor) { } bool fir::ConvertOp::isInteger(mlir::Type ty) { - return mlir::isa(ty); + return ty.isa(); } bool fir::ConvertOp::isIntegerCompatible(mlir::Type ty) { @@ -954,13 +953,13 @@ bool fir::ConvertOp::isIntegerCompatible(mlir::Type ty) { } bool fir::ConvertOp::isFloatCompatible(mlir::Type ty) { - return mlir::isa(ty); + return ty.isa(); } bool fir::ConvertOp::isPointerCompatible(mlir::Type ty) { - return mlir::isa(ty); + return ty.isa(); } static std::optional getVectorElementType(mlir::Type ty) { @@ -1027,14 +1026,12 @@ bool fir::ConvertOp::canBeConverted(mlir::Type inType, mlir::Type outType) { (isFloatCompatible(inType) && isFloatCompatible(outType)) || (isIntegerCompatible(inType) && isPointerCompatible(outType)) || (isPointerCompatible(inType) && isIntegerCompatible(outType)) || - (mlir::isa(inType) && - mlir::isa(outType)) || - (mlir::isa(inType) && - mlir::isa(outType)) || + (inType.isa() && outType.isa()) || + (inType.isa() && outType.isa()) || (fir::isa_complex(inType) && fir::isa_complex(outType)) || (fir::isBoxedRecordType(inType) && fir::isPolymorphicType(outType)) || (fir::isPolymorphicType(inType) && fir::isPolymorphicType(outType)) || - (fir::isPolymorphicType(inType) && mlir::isa(outType)) || + (fir::isPolymorphicType(inType) && outType.isa()) || areVectorsCompatible(inType, outType); } @@ -1082,7 +1079,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { const mlir::Type refTy = getRef().getType(); if (fir::isa_ref_type(refTy)) { auto eleTy = fir::dyn_cast_ptrEleTy(refTy); - if (auto arrTy = mlir::dyn_cast(eleTy)) { + if (auto arrTy = eleTy.dyn_cast()) { if (arrTy.hasUnknownShape()) return emitOpError("cannot find coordinate in unknown shape"); if (arrTy.getConstantRows() < arrTy.getDimension() - 1) @@ -1097,8 +1094,8 @@ mlir::LogicalResult fir::CoordinateOp::verify() { const unsigned numCoors = getCoor().size(); for (auto coorOperand : llvm::enumerate(getCoor())) { auto co = coorOperand.value(); - if (dimension == 0 && mlir::isa(eleTy)) { - dimension = mlir::cast(eleTy).getDimension(); + if (dimension == 0 && eleTy.isa()) { + dimension = eleTy.cast().getDimension(); if (dimension == 0) return emitOpError("cannot apply to array of unknown rank"); } @@ -1107,7 +1104,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { // Recovering a LEN type parameter only makes sense from a boxed // value. For a bare reference, the LEN type parameters must be // passed as additional arguments to `index`. - if (mlir::isa(refTy)) { + if (refTy.isa()) { if (coorOperand.index() != numCoors - 1) return emitOpError("len_param_index must be last argument"); if (getNumOperands() != 2) @@ -1120,7 +1117,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { } else if (auto index = mlir::dyn_cast(defOp)) { if (eleTy != index.getOnType()) emitOpError("field_index type not compatible with reference type"); - if (auto recTy = mlir::dyn_cast(eleTy)) { + if (auto recTy = eleTy.dyn_cast()) { eleTy = recTy.getType(index.getFieldName()); continue; } @@ -1129,21 +1126,21 @@ mlir::LogicalResult fir::CoordinateOp::verify() { } if (dimension) { if (--dimension == 0) - eleTy = mlir::cast(eleTy).getEleTy(); + eleTy = eleTy.cast().getEleTy(); } else { - if (auto t = mlir::dyn_cast(eleTy)) { + if (auto t = eleTy.dyn_cast()) { // FIXME: Generally, we don't know which field of the tuple is being // referred to unless the operand is a constant. Just assume everything // is good in the tuple case for now. return mlir::success(); - } else if (auto t = mlir::dyn_cast(eleTy)) { + } else if (auto t = eleTy.dyn_cast()) { // FIXME: This is the same as the tuple case. return mlir::success(); - } else if (auto t = mlir::dyn_cast(eleTy)) { + } else if (auto t = eleTy.dyn_cast()) { eleTy = t.getElementType(); - } else if (auto t = mlir::dyn_cast(eleTy)) { + } else if (auto t = eleTy.dyn_cast()) { eleTy = t.getElementType(); - } else if (auto t = mlir::dyn_cast(eleTy)) { + } else if (auto t = eleTy.dyn_cast()) { if (t.getLen() == fir::CharacterType::singleton()) return emitOpError("cannot apply to character singleton"); eleTy = fir::CharacterType::getSingleton(t.getContext(), t.getFKind()); @@ -1219,17 +1216,17 @@ mlir::LogicalResult fir::TypeInfoOp::verify() { mlir::LogicalResult fir::EmboxOp::verify() { auto eleTy = fir::dyn_cast_ptrEleTy(getMemref().getType()); bool isArray = false; - if (auto seqTy = mlir::dyn_cast(eleTy)) { + if (auto seqTy = eleTy.dyn_cast()) { eleTy = seqTy.getEleTy(); isArray = true; } if (hasLenParams()) { auto lenPs = numLenParams(); - if (auto rt = mlir::dyn_cast(eleTy)) { + if (auto rt = eleTy.dyn_cast()) { if (lenPs != rt.getNumLenParams()) return emitOpError("number of LEN params does not correspond" " to the !fir.type type"); - } else if (auto strTy = mlir::dyn_cast(eleTy)) { + } else if (auto strTy = eleTy.dyn_cast()) { if (strTy.getLen() != fir::CharacterType::unknownLen()) return emitOpError("CHARACTER already has static LEN"); } else { @@ -1243,7 +1240,7 @@ mlir::LogicalResult fir::EmboxOp::verify() { return emitOpError("shape must not be provided for a scalar"); if (getSlice() && !isArray) return emitOpError("slice must not be provided for a scalar"); - if (getSourceBox() && !mlir::isa(getResult().getType())) + if (getSourceBox() && !getResult().getType().isa()) return emitOpError("source_box must be used with fir.class result type"); return mlir::success(); } @@ -1254,7 +1251,7 @@ mlir::LogicalResult fir::EmboxOp::verify() { mlir::LogicalResult fir::EmboxCharOp::verify() { auto eleTy = fir::dyn_cast_ptrEleTy(getMemref().getType()); - if (!mlir::dyn_cast_or_null(eleTy)) + if (!eleTy.dyn_cast_or_null()) return mlir::failure(); return mlir::success(); } @@ -1266,8 +1263,8 @@ mlir::LogicalResult fir::EmboxCharOp::verify() { mlir::LogicalResult fir::EmboxProcOp::verify() { // host bindings (optional) must be a reference to a tuple if (auto h = getHost()) { - if (auto r = mlir::dyn_cast(h.getType())) - if (mlir::isa(r.getEleTy())) + if (auto r = h.getType().dyn_cast()) + if (r.getEleTy().isa()) return mlir::success(); return mlir::failure(); } @@ -1303,7 +1300,7 @@ void fir::TypeDescOp::print(mlir::OpAsmPrinter &p) { mlir::LogicalResult fir::TypeDescOp::verify() { mlir::Type resultTy = getType(); - if (auto tdesc = mlir::dyn_cast(resultTy)) { + if (auto tdesc = resultTy.dyn_cast()) { if (tdesc.getOfTy() != getInType()) return emitOpError("wrapped type mismatched"); return mlir::success(); @@ -1530,7 +1527,7 @@ mlir::ParseResult parseFieldLikeOp(mlir::OpAsmParser &parser, return mlir::failure(); result.addAttribute(fir::FieldIndexOp::getFieldAttrName(), builder.getStringAttr(fieldName)); - if (!mlir::dyn_cast(recty)) + if (!recty.dyn_cast()) return mlir::failure(); result.addAttribute(fir::FieldIndexOp::getTypeAttrName(), mlir::TypeAttr::get(recty)); @@ -1674,7 +1671,7 @@ mlir::LogicalResult fir::InsertOnRangeOp::verify() { //===----------------------------------------------------------------------===// static bool checkIsIntegerConstant(mlir::Attribute attr, std::int64_t conVal) { - if (auto iattr = mlir::dyn_cast(attr)) + if (auto iattr = attr.dyn_cast()) return iattr.getInt() == conVal; return false; } @@ -1693,7 +1690,7 @@ struct UndoComplexPattern : public mlir::RewritePattern { matchAndRewrite(mlir::Operation *op, mlir::PatternRewriter &rewriter) const override { auto insval = mlir::dyn_cast_or_null(op); - if (!insval || !mlir::isa(insval.getType())) + if (!insval || !insval.getType().isa()) return mlir::failure(); auto insval2 = mlir::dyn_cast_or_null( insval.getAdt().getDefiningOp()); @@ -1822,7 +1819,7 @@ mlir::ParseResult fir::IterWhileOp::parse(mlir::OpAsmParser &parser, parser.parseRParen()) return mlir::failure(); // Type list must be "(index, i1)". - if (typeList.size() != 2 || !mlir::isa(typeList[0]) || + if (typeList.size() != 2 || !typeList[0].isa() || !typeList[1].isSignlessInteger(1)) return mlir::failure(); result.addTypes(typeList); @@ -1876,7 +1873,7 @@ mlir::LogicalResult fir::IterWhileOp::verify() { auto opNumResults = getNumResults(); if (getFinalValue()) { // Result type must be "(index, i1, ...)". - if (!mlir::isa(getResult(0).getType())) + if (!getResult(0).getType().isa()) return emitOpError("result #0 expected to be index"); if (!getResult(1).getType().isSignlessInteger(1)) return emitOpError("result #1 expected to be i1"); @@ -2319,7 +2316,7 @@ void fir::DTEntryOp::print(mlir::OpAsmPrinter &p) { /// Example: return f32 for !fir.box>. static mlir::Type getBoxScalarEleTy(mlir::Type boxTy) { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(boxTy); - if (auto seqTy = mlir::dyn_cast(eleTy)) + if (auto seqTy = eleTy.dyn_cast()) return seqTy.getEleTy(); return eleTy; } @@ -2327,8 +2324,8 @@ static mlir::Type getBoxScalarEleTy(mlir::Type boxTy) { /// Test if \p t1 and \p t2 are compatible character types (if they can /// represent the same type at runtime). static bool areCompatibleCharacterTypes(mlir::Type t1, mlir::Type t2) { - auto c1 = mlir::dyn_cast(t1); - auto c2 = mlir::dyn_cast(t2); + auto c1 = t1.dyn_cast(); + auto c2 = t2.dyn_cast(); if (!c1 || !c2) return false; if (c1.hasDynamicLen() || c2.hasDynamicLen()) @@ -2350,10 +2347,10 @@ mlir::LogicalResult fir::ReboxOp::verify() { if (auto sliceVal = getSlice()) { // Slicing case - if (mlir::cast(sliceVal.getType()).getRank() != inputRank) + if (sliceVal.getType().cast().getRank() != inputRank) return emitOpError("slice operand rank must match box operand rank"); if (auto shapeVal = getShape()) { - if (auto shiftTy = mlir::dyn_cast(shapeVal.getType())) { + if (auto shiftTy = shapeVal.getType().dyn_cast()) { if (shiftTy.getRank() != inputRank) return emitOpError("shape operand and input box ranks must match " "when there is a slice"); @@ -2373,12 +2370,12 @@ mlir::LogicalResult fir::ReboxOp::verify() { unsigned shapeRank = inputRank; if (auto shapeVal = getShape()) { auto ty = shapeVal.getType(); - if (auto shapeTy = mlir::dyn_cast(ty)) { + if (auto shapeTy = ty.dyn_cast()) { shapeRank = shapeTy.getRank(); - } else if (auto shapeShiftTy = mlir::dyn_cast(ty)) { + } else if (auto shapeShiftTy = ty.dyn_cast()) { shapeRank = shapeShiftTy.getRank(); } else { - auto shiftTy = mlir::cast(ty); + auto shiftTy = ty.cast(); shapeRank = shiftTy.getRank(); if (shapeRank != inputRank) return emitOpError("shape operand and input box ranks must match " @@ -2397,13 +2394,11 @@ mlir::LogicalResult fir::ReboxOp::verify() { // the types is a character with dynamic length, the other type can be any // character type. const bool typeCanMismatch = - mlir::isa(inputEleTy) || - mlir::isa(outEleTy) || - (mlir::isa(inputEleTy) && - mlir::isa(outEleTy)) || - (getSlice() && mlir::isa(inputEleTy)) || + inputEleTy.isa() || outEleTy.isa() || + (inputEleTy.isa() && outEleTy.isa()) || + (getSlice() && inputEleTy.isa()) || (getSlice() && fir::isa_complex(inputEleTy) && - mlir::isa(outEleTy)) || + outEleTy.isa()) || areCompatibleCharacterTypes(inputEleTy, outEleTy); if (!typeCanMismatch) return emitOpError( @@ -2440,7 +2435,7 @@ mlir::LogicalResult fir::SaveResultOp::verify() { if (fir::isa_unknown_size_box(resultType)) return emitOpError("cannot save !fir.box of unknown rank or type"); - if (mlir::isa(resultType)) { + if (resultType.isa()) { if (getShape() || !getTypeparams().empty()) return emitOpError( "must not have shape or length operands if the value is a fir.box"); @@ -2451,14 +2446,14 @@ mlir::LogicalResult fir::SaveResultOp::verify() { unsigned shapeTyRank = 0; if (auto shapeVal = getShape()) { auto shapeTy = shapeVal.getType(); - if (auto s = mlir::dyn_cast(shapeTy)) + if (auto s = shapeTy.dyn_cast()) shapeTyRank = s.getRank(); else - shapeTyRank = mlir::cast(shapeTy).getRank(); + shapeTyRank = shapeTy.cast().getRank(); } auto eleTy = resultType; - if (auto seqTy = mlir::dyn_cast(resultType)) { + if (auto seqTy = resultType.dyn_cast()) { if (seqTy.getDimension() != shapeTyRank) emitOpError("shape operand must be provided and have the value rank " "when the value is a fir.array"); @@ -2469,11 +2464,11 @@ mlir::LogicalResult fir::SaveResultOp::verify() { "shape operand should only be provided if the value is a fir.array"); } - if (auto recTy = mlir::dyn_cast(eleTy)) { + if (auto recTy = eleTy.dyn_cast()) { if (recTy.getNumLenParams() != getTypeparams().size()) emitOpError("length parameters number must match with the value type " "length parameters"); - } else if (auto charTy = mlir::dyn_cast(eleTy)) { + } else if (auto charTy = eleTy.dyn_cast()) { if (getTypeparams().size() > 1) emitOpError("no more than one length parameter must be provided for " "character value"); @@ -2513,7 +2508,7 @@ static mlir::LogicalResult verifyIntegralSwitchTerminator(OpT op) { if (op.targetOffsetSize() != count) return op.emitOpError("incorrect number of successor operand groups"); for (decltype(count) i = 0; i != count; ++i) { - if (!mlir::isa(cases[i])) + if (!cases[i].template isa()) return op.emitOpError("invalid case alternative"); } return mlir::success(); @@ -2625,7 +2620,7 @@ getMutableSuccessorOperands(unsigned pos, mlir::MutableOperandRange operands, *owner->getAttrDictionary().getNamed(offsetAttr); return getSubOperands( pos, operands, - mlir::cast(targetOffsetAttr.getValue()), + targetOffsetAttr.getValue().cast(), mlir::MutableOperandRange::OperandSegment(pos, targetOffsetAttr)); } @@ -2747,9 +2742,9 @@ mlir::ParseResult fir::SelectCaseOp::parse(mlir::OpAsmParser &parser, parser.parseComma()) return mlir::failure(); attrs.push_back(attr); - if (mlir::dyn_cast_or_null(attr)) { + if (attr.dyn_cast_or_null()) { argOffs.push_back(0); - } else if (mlir::dyn_cast_or_null(attr)) { + } else if (attr.dyn_cast_or_null()) { mlir::OpAsmParser::UnresolvedOperand oper1; mlir::OpAsmParser::UnresolvedOperand oper2; if (parser.parseOperand(oper1) || parser.parseComma() || @@ -2811,11 +2806,11 @@ void fir::SelectCaseOp::print(mlir::OpAsmPrinter &p) { if (i) p << ", "; p << cases[i] << ", "; - if (!mlir::isa(cases[i])) { + if (!cases[i].isa()) { auto caseArgs = *getCompareOperands(i); p.printOperand(*caseArgs.begin()); p << ", "; - if (mlir::isa(cases[i])) { + if (cases[i].isa()) { p.printOperand(*(++caseArgs.begin())); p << ", "; } @@ -2853,10 +2848,10 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, llvm::SmallVector operOffs; int32_t operSize = 0; for (auto attr : compareAttrs) { - if (mlir::isa(attr)) { + if (attr.isa()) { operOffs.push_back(2); operSize += 2; - } else if (mlir::isa(attr)) { + } else if (attr.isa()) { operOffs.push_back(0); } else { operOffs.push_back(1); @@ -2905,10 +2900,10 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, llvm::SmallVector cmpOpers; auto iter = cmpOpList.begin(); for (auto &attr : compareAttrs) { - if (mlir::isa(attr)) { + if (attr.isa()) { cmpOpers.push_back(mlir::ValueRange({iter, iter + 2})); iter += 2; - } else if (mlir::isa(attr)) { + } else if (attr.isa()) { cmpOpers.push_back(mlir::ValueRange{}); } else { cmpOpers.push_back(mlir::ValueRange({iter, iter + 1})); @@ -2920,8 +2915,10 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, } mlir::LogicalResult fir::SelectCaseOp::verify() { - if (!mlir::isa(getSelector().getType())) + if (!getSelector() + .getType() + .isa()) return emitOpError("must be an integer, character, or logical"); auto cases = getOperation()->getAttrOfType(getCasesAttr()).getValue(); @@ -2936,11 +2933,9 @@ mlir::LogicalResult fir::SelectCaseOp::verify() { return emitOpError("incorrect number of successor operand groups"); for (decltype(count) i = 0; i != count; ++i) { auto &attr = cases[i]; - if (!(mlir::isa(attr) || - mlir::isa(attr) || - mlir::isa(attr) || - mlir::isa(attr) || - mlir::isa(attr))) + if (!(attr.isa() || + attr.isa() || attr.isa() || + attr.isa() || attr.isa())) return emitOpError("incorrect select case attribute type"); } return mlir::success(); @@ -3116,14 +3111,14 @@ void fir::SelectTypeOp::print(mlir::OpAsmPrinter &p) { } mlir::LogicalResult fir::SelectTypeOp::verify() { - if (!mlir::isa(getSelector().getType())) + if (!(getSelector().getType().isa())) return emitOpError("must be a fir.class or fir.box type"); - if (auto boxType = mlir::dyn_cast(getSelector().getType())) - if (!mlir::isa(boxType.getEleTy())) + if (auto boxType = getSelector().getType().dyn_cast()) + if (!boxType.getEleTy().isa()) return emitOpError("selector must be polymorphic"); auto typeGuardAttr = getCases(); for (unsigned idx = 0; idx < typeGuardAttr.size(); ++idx) - if (mlir::isa(typeGuardAttr[idx]) && + if (typeGuardAttr[idx].isa() && idx != typeGuardAttr.size() - 1) return emitOpError("default must be the last attribute"); auto count = getNumDest(); @@ -3134,8 +3129,9 @@ mlir::LogicalResult fir::SelectTypeOp::verify() { if (targetOffsetSize() != count) return emitOpError("incorrect number of successor operand groups"); for (unsigned i = 0; i != count; ++i) { - if (!mlir::isa( - typeGuardAttr[i])) + if (!(typeGuardAttr[i].isa() || + typeGuardAttr[i].isa() || + typeGuardAttr[i].isa())) return emitOpError("invalid type-case alternative"); } return mlir::success(); @@ -3179,7 +3175,7 @@ void fir::SelectTypeOp::build(mlir::OpBuilder &builder, mlir::LogicalResult fir::ShapeOp::verify() { auto size = getExtents().size(); - auto shapeTy = mlir::dyn_cast(getType()); + auto shapeTy = getType().dyn_cast(); assert(shapeTy && "must be a shape type"); if (shapeTy.getRank() != size) return emitOpError("shape type rank mismatch"); @@ -3202,7 +3198,7 @@ mlir::LogicalResult fir::ShapeShiftOp::verify() { return emitOpError("incorrect number of args"); if (size % 2 != 0) return emitOpError("requires a multiple of 2 args"); - auto shapeTy = mlir::dyn_cast(getType()); + auto shapeTy = getType().dyn_cast(); assert(shapeTy && "must be a shape shift type"); if (shapeTy.getRank() * 2 != size) return emitOpError("shape type rank mismatch"); @@ -3215,7 +3211,7 @@ mlir::LogicalResult fir::ShapeShiftOp::verify() { mlir::LogicalResult fir::ShiftOp::verify() { auto size = getOrigins().size(); - auto shiftTy = mlir::dyn_cast(getType()); + auto shiftTy = getType().dyn_cast(); assert(shiftTy && "must be a shift type"); if (shiftTy.getRank() != size) return emitOpError("shift type rank mismatch"); @@ -3255,7 +3251,7 @@ mlir::LogicalResult fir::SliceOp::verify() { return emitOpError("incorrect number of args for triple"); if (size % 3 != 0) return emitOpError("requires a multiple of 3 args"); - auto sliceTy = mlir::dyn_cast(getType()); + auto sliceTy = getType().dyn_cast(); assert(sliceTy && "must be a slice type"); if (sliceTy.getRank() * 3 != size) return emitOpError("slice type rank mismatch"); @@ -3313,8 +3309,8 @@ void fir::StoreOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, //===----------------------------------------------------------------------===// inline fir::CharacterType::KindTy stringLitOpGetKind(fir::StringLitOp op) { - auto eleTy = mlir::cast(op.getType()).getEleTy(); - return mlir::cast(eleTy).getFKind(); + auto eleTy = op.getType().cast().getEleTy(); + return eleTy.cast().getFKind(); } bool fir::StringLitOp::isWideValue() { return stringLitOpGetKind(*this) != 1; } @@ -3394,13 +3390,13 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, llvm::SMLoc trailingTypeLoc; if (parser.parseAttribute(val, "fake", attrs)) return mlir::failure(); - if (auto v = mlir::dyn_cast(val)) + if (auto v = val.dyn_cast()) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::value(), v)); - else if (auto v = mlir::dyn_cast(val)) + else if (auto v = val.dyn_cast()) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::xlist(), v)); - else if (auto v = mlir::dyn_cast(val)) + else if (auto v = val.dyn_cast()) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::xlist(), v)); else @@ -3413,7 +3409,7 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, parser.parseRParen() || parser.getCurrentLocation(&trailingTypeLoc) || parser.parseColonType(type)) return mlir::failure(); - auto charTy = mlir::dyn_cast(type); + auto charTy = type.dyn_cast(); if (!charTy) return parser.emitError(trailingTypeLoc, "must have character type"); type = fir::CharacterType::get(builder.getContext(), charTy.getFKind(), @@ -3425,19 +3421,19 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, void fir::StringLitOp::print(mlir::OpAsmPrinter &p) { p << ' ' << getValue() << '('; - p << mlir::cast(getSize()).getValue() << ") : "; + p << getSize().cast().getValue() << ") : "; p.printType(getType()); } mlir::LogicalResult fir::StringLitOp::verify() { - if (mlir::cast(getSize()).getValue().isNegative()) + if (getSize().cast().getValue().isNegative()) return emitOpError("size must be non-negative"); if (auto xl = getOperation()->getAttr(fir::StringLitOp::xlist())) { - if (auto xList = mlir::dyn_cast(xl)) { + if (auto xList = xl.dyn_cast()) { for (auto a : xList) - if (!mlir::isa(a)) + if (!a.isa()) return emitOpError("values in initializer must be integers"); - } else if (mlir::isa(xl)) { + } else if (xl.isa()) { // do nothing } else { return emitOpError("has unexpected attribute"); @@ -3452,7 +3448,7 @@ mlir::LogicalResult fir::StringLitOp::verify() { mlir::LogicalResult fir::UnboxProcOp::verify() { if (auto eleTy = fir::dyn_cast_ptrEleTy(getRefTuple().getType())) - if (mlir::isa(eleTy)) + if (eleTy.isa()) return mlir::success(); return emitOpError("second output argument has bad type"); } @@ -3531,7 +3527,7 @@ void fir::IfOp::getEntrySuccessorRegions( void fir::IfOp::getRegionInvocationBounds( llvm::ArrayRef operands, llvm::SmallVectorImpl &invocationBounds) { - if (auto cond = mlir::dyn_cast_or_null(operands[0])) { + if (auto cond = operands[0].dyn_cast_or_null()) { // If the condition is known, then one region is known to be executed once // and the other zero times. invocationBounds.emplace_back(0, cond.getValue() ? 1 : 0); @@ -3650,8 +3646,8 @@ void fir::BoxOffsetOp::build(mlir::OpBuilder &builder, //===----------------------------------------------------------------------===// mlir::ParseResult fir::isValidCaseAttr(mlir::Attribute attr) { - if (mlir::isa(attr)) + if (attr.isa()) return mlir::success(); return mlir::failure(); } @@ -3661,9 +3657,9 @@ unsigned fir::getCaseArgumentOffset(llvm::ArrayRef cases, unsigned o = 0; for (unsigned i = 0; i < dest; ++i) { auto &attr = cases[i]; - if (!mlir::dyn_cast_or_null(attr)) { + if (!attr.dyn_cast_or_null()) { ++o; - if (mlir::dyn_cast_or_null(attr)) + if (attr.dyn_cast_or_null()) ++o; } } @@ -3726,7 +3722,7 @@ fir::GlobalOp fir::createGlobalOp(mlir::Location loc, mlir::ModuleOp module, bool fir::hasHostAssociationArgument(mlir::func::FuncOp func) { if (auto allArgAttrs = func.getAllArgAttrs()) for (auto attr : allArgAttrs) - if (auto dict = mlir::dyn_cast_or_null(attr)) + if (auto dict = attr.template dyn_cast_or_null()) if (dict.get(fir::getHostAssocAttrName())) return true; return false; @@ -3776,7 +3772,7 @@ valueCheckFirAttributes(mlir::Value value, }; // If this is a fir.box that was loaded, the fir attributes will be on the // related fir.ref creation. - if (mlir::isa(value.getType())) + if (value.getType().isa()) if (auto definingOp = value.getDefiningOp()) if (auto loadOp = mlir::dyn_cast(definingOp)) value = loadOp.getMemref(); @@ -3841,10 +3837,10 @@ bool fir::anyFuncArgsHaveAttr(mlir::func::FuncOp func, llvm::StringRef attr) { std::optional fir::getIntIfConstant(mlir::Value value) { if (auto *definingOp = value.getDefiningOp()) { if (auto cst = mlir::dyn_cast(definingOp)) - if (auto intAttr = mlir::dyn_cast(cst.getValue())) + if (auto intAttr = cst.getValue().dyn_cast()) return intAttr.getInt(); if (auto llConstOp = mlir::dyn_cast(definingOp)) - if (auto attr = mlir::dyn_cast(llConstOp.getValue())) + if (auto attr = llConstOp.getValue().dyn_cast()) return attr.getValue().getSExtValue(); } return {}; @@ -4006,15 +4002,15 @@ mlir::LogicalResult fir::CUDAKernelOp::verify() { mlir::LogicalResult fir::CUDAAllocateOp::verify() { if (getPinned() && getStream()) return emitOpError("pinned and stream cannot appears at the same time"); - if (!mlir::isa(fir::unwrapRefType(getBox().getType()))) + if (!fir::unwrapRefType(getBox().getType()).isa()) return emitOpError( "expect box to be a reference to a class or box type value"); if (getSource() && - !mlir::isa(fir::unwrapRefType(getSource().getType()))) + !fir::unwrapRefType(getSource().getType()).isa()) return emitOpError( "expect source to be a reference to/or a class or box type value"); if (getErrmsg() && - !mlir::isa(fir::unwrapRefType(getErrmsg().getType()))) + !fir::unwrapRefType(getErrmsg().getType()).isa()) return emitOpError( "expect errmsg to be a reference to/or a box type value"); if (getErrmsg() && !getHasStat()) @@ -4023,11 +4019,11 @@ mlir::LogicalResult fir::CUDAAllocateOp::verify() { } mlir::LogicalResult fir::CUDADeallocateOp::verify() { - if (!mlir::isa(fir::unwrapRefType(getBox().getType()))) + if (!fir::unwrapRefType(getBox().getType()).isa()) return emitOpError( "expect box to be a reference to class or box type value"); if (getErrmsg() && - !mlir::isa(fir::unwrapRefType(getErrmsg().getType()))) + !fir::unwrapRefType(getErrmsg().getType()).isa()) return emitOpError( "expect errmsg to be a reference to/or a box type value"); if (getErrmsg() && !getHasStat()) diff --git a/flang/lib/Optimizer/Dialect/FIRType.cpp b/flang/lib/Optimizer/Dialect/FIRType.cpp index 38a6a09d1808..5c4cad6d2083 100644 --- a/flang/lib/Optimizer/Dialect/FIRType.cpp +++ b/flang/lib/Optimizer/Dialect/FIRType.cpp @@ -61,13 +61,14 @@ TYPE parseTypeSingleton(mlir::AsmParser &parser) { /// Is `ty` a standard or FIR integer type? static bool isaIntegerType(mlir::Type ty) { // TODO: why aren't we using isa_integer? investigatation required. - return mlir::isa(ty); + return ty.isa() || ty.isa(); } bool verifyRecordMemberType(mlir::Type ty) { - return !mlir::isa( - ty); + return !(ty.isa() || ty.isa() || + ty.isa() || ty.isa() || + ty.isa() || ty.isa() || ty.isa() || + ty.isa() || ty.isa()); } bool verifySameLists(llvm::ArrayRef a1, @@ -193,7 +194,7 @@ bool isa_std_type(mlir::Type t) { } bool isa_fir_or_std_type(mlir::Type t) { - if (auto funcType = mlir::dyn_cast(t)) + if (auto funcType = t.dyn_cast()) return llvm::all_of(funcType.getInputs(), isa_fir_or_std_type) && llvm::all_of(funcType.getResults(), isa_fir_or_std_type); return isa_fir_type(t) || isa_std_type(t); @@ -202,7 +203,7 @@ bool isa_fir_or_std_type(mlir::Type t) { mlir::Type getDerivedType(mlir::Type ty) { return llvm::TypeSwitch(ty) .Case([](auto p) { - if (auto seq = mlir::dyn_cast(p.getEleTy())) + if (auto seq = p.getEleTy().template dyn_cast()) return seq.getEleTy(); return p.getEleTy(); }) @@ -227,12 +228,12 @@ mlir::Type dyn_cast_ptrOrBoxEleTy(mlir::Type t) { static bool hasDynamicSize(fir::RecordType recTy) { for (auto field : recTy.getTypeList()) { - if (auto arr = mlir::dyn_cast(field.second)) { + if (auto arr = field.second.dyn_cast()) { if (sequenceWithNonConstantShape(arr)) return true; } else if (characterWithDynamicLen(field.second)) { return true; - } else if (auto rec = mlir::dyn_cast(field.second)) { + } else if (auto rec = field.second.dyn_cast()) { if (hasDynamicSize(rec)) return true; } @@ -241,14 +242,14 @@ static bool hasDynamicSize(fir::RecordType recTy) { } bool hasDynamicSize(mlir::Type t) { - if (auto arr = mlir::dyn_cast(t)) { + if (auto arr = t.dyn_cast()) { if (sequenceWithNonConstantShape(arr)) return true; t = arr.getEleTy(); } if (characterWithDynamicLen(t)) return true; - if (auto rec = mlir::dyn_cast(t)) + if (auto rec = t.dyn_cast()) return hasDynamicSize(rec); return false; } @@ -268,33 +269,33 @@ mlir::Type extractSequenceType(mlir::Type ty) { bool isPointerType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = mlir::dyn_cast(ty)) - return mlir::isa(boxTy.getEleTy()); + if (auto boxTy = ty.dyn_cast()) + return boxTy.getEleTy().isa(); return false; } bool isAllocatableType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = mlir::dyn_cast(ty)) - return mlir::isa(boxTy.getEleTy()); + if (auto boxTy = ty.dyn_cast()) + return boxTy.getEleTy().isa(); return false; } bool isBoxNone(mlir::Type ty) { - if (auto box = mlir::dyn_cast(ty)) - return mlir::isa(box.getEleTy()); + if (auto box = ty.dyn_cast()) + return box.getEleTy().isa(); return false; } bool isBoxedRecordType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = mlir::dyn_cast(ty)) { - if (mlir::isa(boxTy.getEleTy())) + if (auto boxTy = ty.dyn_cast()) { + if (boxTy.getEleTy().isa()) return true; mlir::Type innerType = boxTy.unwrapInnerType(); - return innerType && mlir::isa(innerType); + return innerType && innerType.isa(); } return false; } @@ -302,13 +303,13 @@ bool isBoxedRecordType(mlir::Type ty) { bool isScalarBoxedRecordType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = mlir::dyn_cast(ty)) { - if (mlir::isa(boxTy.getEleTy())) + if (auto boxTy = ty.dyn_cast()) { + if (boxTy.getEleTy().isa()) return true; - if (auto heapTy = mlir::dyn_cast(boxTy.getEleTy())) - return mlir::isa(heapTy.getEleTy()); - if (auto ptrTy = mlir::dyn_cast(boxTy.getEleTy())) - return mlir::isa(ptrTy.getEleTy()); + if (auto heapTy = boxTy.getEleTy().dyn_cast()) + return heapTy.getEleTy().isa(); + if (auto ptrTy = boxTy.getEleTy().dyn_cast()) + return ptrTy.getEleTy().isa(); } return false; } @@ -362,10 +363,10 @@ bool isPolymorphicType(mlir::Type ty) { bool isUnlimitedPolymorphicType(mlir::Type ty) { // CLASS(*) if (auto clTy = mlir::dyn_cast(fir::unwrapRefType(ty))) { - if (mlir::isa(clTy.getEleTy())) + if (clTy.getEleTy().isa()) return true; mlir::Type innerType = clTy.unwrapInnerType(); - return innerType && mlir::isa(innerType); + return innerType && innerType.isa(); } // TYPE(*) return isAssumedType(ty); @@ -375,7 +376,7 @@ mlir::Type unwrapInnerType(mlir::Type ty) { return llvm::TypeSwitch(ty) .Case([](auto t) { mlir::Type eleTy = t.getEleTy(); - if (auto seqTy = mlir::dyn_cast(eleTy)) + if (auto seqTy = eleTy.dyn_cast()) return seqTy.getEleTy(); return eleTy; }) @@ -384,14 +385,13 @@ mlir::Type unwrapInnerType(mlir::Type ty) { } bool isRecordWithAllocatableMember(mlir::Type ty) { - if (auto recTy = mlir::dyn_cast(ty)) + if (auto recTy = ty.dyn_cast()) for (auto [field, memTy] : recTy.getTypeList()) { if (fir::isAllocatableType(memTy)) return true; // A record type cannot recursively include itself as a direct member. // There must be an intervening `ptr` type, so recursion is safe here. - if (mlir::isa(memTy) && - isRecordWithAllocatableMember(memTy)) + if (memTy.isa() && isRecordWithAllocatableMember(memTy)) return true; } return false; @@ -399,12 +399,11 @@ bool isRecordWithAllocatableMember(mlir::Type ty) { bool isRecordWithDescriptorMember(mlir::Type ty) { ty = unwrapSequenceType(ty); - if (auto recTy = mlir::dyn_cast(ty)) + if (auto recTy = ty.dyn_cast()) for (auto [field, memTy] : recTy.getTypeList()) { if (mlir::isa(memTy)) return true; - if (mlir::isa(memTy) && - isRecordWithDescriptorMember(memTy)) + if (memTy.isa() && isRecordWithDescriptorMember(memTy)) return true; } return false; @@ -413,7 +412,7 @@ bool isRecordWithDescriptorMember(mlir::Type ty) { mlir::Type unwrapAllRefAndSeqType(mlir::Type ty) { while (true) { mlir::Type nt = unwrapSequenceType(unwrapRefType(ty)); - if (auto vecTy = mlir::dyn_cast(nt)) + if (auto vecTy = nt.dyn_cast()) nt = vecTy.getEleTy(); if (nt == ty) return ty; @@ -422,11 +421,11 @@ mlir::Type unwrapAllRefAndSeqType(mlir::Type ty) { } mlir::Type unwrapSeqOrBoxedSeqType(mlir::Type ty) { - if (auto seqTy = mlir::dyn_cast(ty)) + if (auto seqTy = ty.dyn_cast()) return seqTy.getEleTy(); - if (auto boxTy = mlir::dyn_cast(ty)) { + if (auto boxTy = ty.dyn_cast()) { auto eleTy = unwrapRefType(boxTy.getEleTy()); - if (auto seqTy = mlir::dyn_cast(eleTy)) + if (auto seqTy = eleTy.dyn_cast()) return seqTy.getEleTy(); } return ty; @@ -434,7 +433,7 @@ mlir::Type unwrapSeqOrBoxedSeqType(mlir::Type ty) { unsigned getBoxRank(mlir::Type boxTy) { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(boxTy); - if (auto seqTy = mlir::dyn_cast(eleTy)) + if (auto seqTy = eleTy.dyn_cast()) return seqTy.getDimension(); return 0; } @@ -442,7 +441,7 @@ unsigned getBoxRank(mlir::Type boxTy) { /// Return the ISO_C_BINDING intrinsic module value of type \p ty. int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { unsigned width = 0; - if (mlir::IntegerType intTy = mlir::dyn_cast(ty)) { + if (mlir::IntegerType intTy = ty.dyn_cast()) { switch (intTy.getWidth()) { case 8: return CFI_type_int8_t; @@ -457,7 +456,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported integer type"); } - if (fir::LogicalType logicalTy = mlir::dyn_cast(ty)) { + if (fir::LogicalType logicalTy = ty.dyn_cast()) { switch (kindMap.getLogicalBitsize(logicalTy.getFKind())) { case 8: return CFI_type_Bool; @@ -470,7 +469,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported logical type"); } - if (mlir::FloatType floatTy = mlir::dyn_cast(ty)) { + if (mlir::FloatType floatTy = ty.dyn_cast()) { switch (floatTy.getWidth()) { case 16: return floatTy.isBF16() ? CFI_type_bfloat : CFI_type_half_float; @@ -486,14 +485,13 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { llvm_unreachable("unsupported real type"); } if (fir::isa_complex(ty)) { - if (mlir::ComplexType complexTy = mlir::dyn_cast(ty)) { + if (mlir::ComplexType complexTy = ty.dyn_cast()) { mlir::FloatType floatTy = - mlir::cast(complexTy.getElementType()); + complexTy.getElementType().cast(); if (floatTy.isBF16()) return CFI_type_bfloat_Complex; width = floatTy.getWidth(); - } else if (fir::ComplexType complexTy = - mlir::dyn_cast(ty)) { + } else if (fir::ComplexType complexTy = ty.dyn_cast()) { auto FKind = complexTy.getFKind(); if (FKind == 3) return CFI_type_bfloat_Complex; @@ -513,7 +511,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported complex size"); } - if (fir::CharacterType charTy = mlir::dyn_cast(ty)) { + if (fir::CharacterType charTy = ty.dyn_cast()) { switch (kindMap.getCharacterBitsize(charTy.getFKind())) { case 8: return CFI_type_char; @@ -526,7 +524,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } if (fir::isa_ref_type(ty)) return CFI_type_cptr; - if (mlir::isa(ty)) + if (ty.isa()) return CFI_type_struct; llvm_unreachable("unsupported type"); } @@ -544,12 +542,12 @@ std::string getTypeAsString(mlir::Type ty, const fir::KindMapping &kindMap, name << "idx"; } else if (ty.isIntOrIndex()) { name << 'i' << ty.getIntOrFloatBitWidth(); - } else if (mlir::isa(ty)) { + } else if (ty.isa()) { name << 'f' << ty.getIntOrFloatBitWidth(); } else if (fir::isa_complex(ty)) { name << 'z'; if (auto cplxTy = mlir::dyn_cast_or_null(ty)) { - auto floatTy = mlir::cast(cplxTy.getElementType()); + auto floatTy = cplxTy.getElementType().cast(); name << floatTy.getWidth(); } else if (auto cplxTy = mlir::dyn_cast_or_null(ty)) { name << kindMap.getRealBitsize(cplxTy.getFKind()); @@ -646,7 +644,7 @@ static llvm::SmallPtrSet } // namespace void fir::verifyIntegralType(mlir::Type type) { - if (isaIntegerType(type) || mlir::isa(type)) + if (isaIntegerType(type) || type.isa()) return; llvm::report_fatal_error("expected integral type"); } @@ -658,9 +656,9 @@ void fir::printFirType(FIROpsDialect *, mlir::Type ty, } bool fir::isa_unknown_size_box(mlir::Type t) { - if (auto boxTy = mlir::dyn_cast(t)) { + if (auto boxTy = t.dyn_cast()) { auto valueType = fir::unwrapPassByRefType(boxTy); - if (auto seqTy = mlir::dyn_cast(valueType)) + if (auto seqTy = valueType.dyn_cast()) if (seqTy.hasUnknownShape()) return true; } @@ -686,10 +684,10 @@ void fir::BoxProcType::print(mlir::AsmPrinter &printer) const { mlir::LogicalResult BoxProcType::verify(llvm::function_ref emitError, mlir::Type eleTy) { - if (mlir::isa(eleTy)) + if (eleTy.isa()) return mlir::success(); - if (auto refTy = mlir::dyn_cast(eleTy)) - if (mlir::isa(refTy)) + if (auto refTy = eleTy.dyn_cast()) + if (refTy.isa()) return mlir::success(); return emitError() << "invalid type for boxproc" << eleTy << '\n'; } @@ -707,7 +705,7 @@ static bool cannotBePointerOrHeapElementType(mlir::Type eleTy) { mlir::LogicalResult fir::BoxType::verify(llvm::function_ref emitError, mlir::Type eleTy) { - if (mlir::isa(eleTy)) + if (eleTy.isa()) return emitError() << "invalid element type\n"; // TODO return mlir::success(); @@ -1238,10 +1236,10 @@ bool fir::VectorType::isValidElementType(mlir::Type t) { } bool fir::isCharacterProcedureTuple(mlir::Type ty, bool acceptRawFunc) { - mlir::TupleType tuple = mlir::dyn_cast(ty); + mlir::TupleType tuple = ty.dyn_cast(); return tuple && tuple.size() == 2 && - (mlir::isa(tuple.getType(0)) || - (acceptRawFunc && mlir::isa(tuple.getType(0)))) && + (tuple.getType(0).isa() || + (acceptRawFunc && tuple.getType(0).isa())) && fir::isa_integer(tuple.getType(1)); } @@ -1249,8 +1247,7 @@ bool fir::hasAbstractResult(mlir::FunctionType ty) { if (ty.getNumResults() == 0) return false; auto resultType = ty.getResult(0); - return mlir::isa( - resultType); + return resultType.isa(); } /// Convert llvm::Type::TypeID to mlir::Type. \p kind is provided for error diff --git a/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp b/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp index 70b1a2f3d844..94f1689dfb05 100644 --- a/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp +++ b/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp @@ -18,7 +18,7 @@ mlir::LogicalResult fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { const unsigned numExplicitTypeParams = getExplicitTypeParams().size(); mlir::Type memType = memref.getType(); - const bool sourceIsBoxValue = mlir::isa(memType); + const bool sourceIsBoxValue = memType.isa(); const bool sourceIsBoxAddress = fir::isBoxAddress(memType); const bool sourceIsBox = sourceIsBoxValue || sourceIsBoxAddress; if (isCharacter()) { @@ -29,8 +29,7 @@ fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { return emitOpError("must be provided exactly one type parameter when its " "base is a character that is not a box"); - } else if (auto recordType = - mlir::dyn_cast(getElementType())) { + } else if (auto recordType = getElementType().dyn_cast()) { if (numExplicitTypeParams < recordType.getNumLenParams() && !sourceIsBox) return emitOpError("must be provided all the derived type length " "parameters when the base is not a box"); @@ -46,16 +45,16 @@ fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { if (sourceIsBoxAddress) return emitOpError("for box address must not have a shape operand"); unsigned shapeRank = 0; - if (auto shapeType = mlir::dyn_cast(shape.getType())) { + if (auto shapeType = shape.getType().dyn_cast()) { shapeRank = shapeType.getRank(); } else if (auto shapeShiftType = - mlir::dyn_cast(shape.getType())) { + shape.getType().dyn_cast()) { shapeRank = shapeShiftType.getRank(); } else { if (!sourceIsBoxValue) emitOpError("of array entity with a raw address base must have a " "shape operand that is a shape or shapeshift"); - shapeRank = mlir::cast(shape.getType()).getRank(); + shapeRank = shape.getType().cast().getRank(); } std::optional rank = getRank(); diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp index 0b61c0edce62..08b2b0538c73 100644 --- a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp @@ -84,8 +84,7 @@ bool hlfir::isFortranVariableType(mlir::Type type) { return llvm::TypeSwitch(type) .Case([](auto p) { mlir::Type eleType = p.getEleTy(); - return mlir::isa(eleType) || - !fir::hasDynamicSize(eleType); + return eleType.isa() || !fir::hasDynamicSize(eleType); }) .Case([](auto) { return true; }) .Case([](auto) { return true; }) @@ -94,15 +93,15 @@ bool hlfir::isFortranVariableType(mlir::Type type) { bool hlfir::isFortranScalarCharacterType(mlir::Type type) { return isFortranScalarCharacterExprType(type) || - mlir::isa(type) || - mlir::isa( - fir::unwrapPassByRefType(fir::unwrapRefType(type))); + type.isa() || + fir::unwrapPassByRefType(fir::unwrapRefType(type)) + .isa(); } bool hlfir::isFortranScalarCharacterExprType(mlir::Type type) { - if (auto exprType = mlir::dyn_cast(type)) + if (auto exprType = type.dyn_cast()) return exprType.isScalar() && - mlir::isa(exprType.getElementType()); + exprType.getElementType().isa(); return false; } @@ -122,8 +121,8 @@ bool hlfir::isFortranScalarNumericalType(mlir::Type type) { bool hlfir::isFortranNumericalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = mlir::dyn_cast( - getFortranElementOrSequenceType(type))) + if (auto arrayTy = + getFortranElementOrSequenceType(type).dyn_cast()) return isFortranScalarNumericalType(arrayTy.getEleTy()); return false; } @@ -131,8 +130,8 @@ bool hlfir::isFortranNumericalArrayObject(mlir::Type type) { bool hlfir::isFortranNumericalOrLogicalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = mlir::dyn_cast( - getFortranElementOrSequenceType(type))) { + if (auto arrayTy = + getFortranElementOrSequenceType(type).dyn_cast()) { mlir::Type eleTy = arrayTy.getEleTy(); return isFortranScalarNumericalType(eleTy) || mlir::isa(eleTy); @@ -143,8 +142,7 @@ bool hlfir::isFortranNumericalOrLogicalArrayObject(mlir::Type type) { bool hlfir::isFortranArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - return !!mlir::dyn_cast( - getFortranElementOrSequenceType(type)); + return !!getFortranElementOrSequenceType(type).dyn_cast(); } bool hlfir::isPassByRefOrIntegerType(mlir::Type type) { @@ -153,7 +151,7 @@ bool hlfir::isPassByRefOrIntegerType(mlir::Type type) { } bool hlfir::isI1Type(mlir::Type type) { - if (mlir::IntegerType integer = mlir::dyn_cast(type)) + if (mlir::IntegerType integer = type.dyn_cast()) if (integer.getWidth() == 1) return true; return false; @@ -162,8 +160,8 @@ bool hlfir::isI1Type(mlir::Type type) { bool hlfir::isFortranLogicalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = mlir::dyn_cast( - getFortranElementOrSequenceType(type))) { + if (auto arrayTy = + getFortranElementOrSequenceType(type).dyn_cast()) { mlir::Type eleTy = arrayTy.getEleTy(); return mlir::isa(eleTy); } diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp index 0d62ca4954e6..8bad4e445082 100644 --- a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp @@ -74,8 +74,8 @@ getIntrinsicEffects(mlir::Operation *self, /// Is this a fir.[ref/ptr/heap]>> type? static bool isAllocatableBoxRef(mlir::Type type) { fir::BaseBoxType boxType = - mlir::dyn_cast_or_null(fir::dyn_cast_ptrEleTy(type)); - return boxType && mlir::isa(boxType.getEleTy()); + fir::dyn_cast_ptrEleTy(type).dyn_cast_or_null(); + return boxType && boxType.getEleTy().isa(); } mlir::LogicalResult hlfir::AssignOp::verify() { @@ -84,7 +84,7 @@ mlir::LogicalResult hlfir::AssignOp::verify() { return emitOpError("lhs must be an allocatable when `realloc` is set"); if (mustKeepLhsLengthInAllocatableAssignment() && !(isAllocatableAssignment() && - mlir::isa(hlfir::getFortranElementType(lhsType)))) + hlfir::getFortranElementType(lhsType).isa())) return emitOpError("`realloc` must be set and lhs must be a character " "allocatable when `keep_lhs_length_if_realloc` is set"); return mlir::success(); @@ -99,13 +99,13 @@ mlir::LogicalResult hlfir::AssignOp::verify() { mlir::Type hlfir::DeclareOp::getHLFIRVariableType(mlir::Type inputType, bool hasExplicitLowerBounds) { mlir::Type type = fir::unwrapRefType(inputType); - if (mlir::isa(type)) + if (type.isa()) return inputType; - if (auto charType = mlir::dyn_cast(type)) + if (auto charType = type.dyn_cast()) if (charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); - auto seqType = mlir::dyn_cast(type); + auto seqType = type.dyn_cast(); bool hasDynamicExtents = seqType && fir::sequenceWithNonConstantShape(seqType); mlir::Type eleType = seqType ? seqType.getEleTy() : type; @@ -117,8 +117,7 @@ mlir::Type hlfir::DeclareOp::getHLFIRVariableType(mlir::Type inputType, } static bool hasExplicitLowerBounds(mlir::Value shape) { - return shape && - mlir::isa(shape.getType()); + return shape && shape.getType().isa(); } void hlfir::DeclareOp::build(mlir::OpBuilder &builder, @@ -289,7 +288,7 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { bool hasBoxComponent; if (getComponent()) { auto component = getComponent().value(); - auto recType = mlir::dyn_cast(baseElementType); + auto recType = baseElementType.dyn_cast(); if (!recType) return emitOpError( "component must be provided only when the memref is a derived type"); @@ -301,14 +300,14 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { } mlir::Type fieldType = recType.getType(fieldIdx); mlir::Type componentBaseType = getFortranElementOrSequenceType(fieldType); - hasBoxComponent = mlir::isa(fieldType); - if (mlir::isa(componentBaseType) && - mlir::isa(baseType) && + hasBoxComponent = fieldType.isa(); + if (componentBaseType.isa() && + baseType.isa() && (numSubscripts == 0 || subscriptsRank > 0)) return emitOpError("indices must be provided and must not contain " "triplets when both memref and component are arrays"); if (numSubscripts != 0) { - if (!mlir::isa(componentBaseType)) + if (!componentBaseType.isa()) return emitOpError("indices must not be provided if component appears " "and is not an array component"); if (!getComponentShape()) @@ -316,9 +315,9 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { "component_shape must be provided when indexing a component"); mlir::Type compShapeType = getComponentShape().getType(); unsigned componentRank = - mlir::cast(componentBaseType).getDimension(); - auto shapeType = mlir::dyn_cast(compShapeType); - auto shapeShiftType = mlir::dyn_cast(compShapeType); + componentBaseType.cast().getDimension(); + auto shapeType = compShapeType.dyn_cast(); + auto shapeShiftType = compShapeType.dyn_cast(); if (!((shapeType && shapeType.getRank() == componentRank) || (shapeShiftType && shapeShiftType.getRank() == componentRank))) return emitOpError("component_shape must be a fir.shape or " @@ -326,33 +325,33 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { if (numSubscripts > componentRank) return emitOpError("indices number must match array component rank"); } - if (auto baseSeqType = mlir::dyn_cast(baseType)) + if (auto baseSeqType = baseType.dyn_cast()) // This case must come first to cover "array%array_comp(i, j)" that has // subscripts for the component but whose rank come from the base. outputRank = baseSeqType.getDimension(); else if (numSubscripts != 0) outputRank = subscriptsRank; else if (auto componentSeqType = - mlir::dyn_cast(componentBaseType)) + componentBaseType.dyn_cast()) outputRank = componentSeqType.getDimension(); outputElementType = fir::unwrapSequenceType(componentBaseType); } else { outputElementType = baseElementType; unsigned baseTypeRank = - mlir::isa(baseType) - ? mlir::cast(baseType).getDimension() + baseType.isa() + ? baseType.cast().getDimension() : 0; if (numSubscripts != 0) { if (baseTypeRank != numSubscripts) return emitOpError("indices number must match memref rank"); outputRank = subscriptsRank; - } else if (auto baseSeqType = mlir::dyn_cast(baseType)) { + } else if (auto baseSeqType = baseType.dyn_cast()) { outputRank = baseSeqType.getDimension(); } } if (!getSubstring().empty()) { - if (!mlir::isa(outputElementType)) + if (!outputElementType.isa()) return emitOpError("memref or component must have character type if " "substring indices are provided"); if (getSubstring().size() != 2) @@ -362,16 +361,16 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { if (!fir::isa_complex(outputElementType)) return emitOpError("memref or component must have complex type if " "complex_part is provided"); - if (auto firCplx = mlir::dyn_cast(outputElementType)) + if (auto firCplx = outputElementType.dyn_cast()) outputElementType = firCplx.getElementType(); else outputElementType = - mlir::cast(outputElementType).getElementType(); + outputElementType.cast().getElementType(); } mlir::Type resultBaseType = getFortranElementOrSequenceType(getResult().getType()); unsigned resultRank = 0; - if (auto resultSeqType = mlir::dyn_cast(resultBaseType)) + if (auto resultSeqType = resultBaseType.dyn_cast()) resultRank = resultSeqType.getDimension(); if (resultRank != outputRank) return emitOpError("result type rank is not consistent with operands, " @@ -381,10 +380,10 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { // result type must match the one that was inferred here, except the character // length may differ because of substrings. if (resultElementType != outputElementType && - !(mlir::isa(resultElementType) && - mlir::isa(outputElementType)) && - !(mlir::isa(resultElementType) && - mlir::isa(outputElementType))) + !(resultElementType.isa() && + outputElementType.isa()) && + !(resultElementType.isa() && + outputElementType.isa())) return emitOpError( "result element type is not consistent with operands, expected ") << outputElementType; @@ -402,22 +401,22 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { return emitOpError("shape must be provided if and only if the result is " "an array that is not a box address"); if (resultRank != 0) { - auto shapeType = mlir::dyn_cast(getShape().getType()); + auto shapeType = getShape().getType().dyn_cast(); auto shapeShiftType = - mlir::dyn_cast(getShape().getType()); + getShape().getType().dyn_cast(); if (!((shapeType && shapeType.getRank() == resultRank) || (shapeShiftType && shapeShiftType.getRank() == resultRank))) return emitOpError("shape must be a fir.shape or fir.shapeshift with " "the rank of the result"); } auto numLenParam = getTypeparams().size(); - if (mlir::isa(outputElementType)) { + if (outputElementType.isa()) { if (numLenParam != 1) return emitOpError("must be provided one length parameter when the " "result is a character"); } else if (fir::isRecordWithTypeParameters(outputElementType)) { if (numLenParam != - mlir::cast(outputElementType).getNumLenParams()) + outputElementType.cast().getNumLenParams()) return emitOpError("must be provided the same number of length " "parameters as in the result derived type"); } else if (numLenParam != 0) { @@ -435,18 +434,18 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { mlir::LogicalResult hlfir::ParentComponentOp::verify() { mlir::Type baseType = hlfir::getFortranElementOrSequenceType(getMemref().getType()); - auto maybeInputSeqType = mlir::dyn_cast(baseType); + auto maybeInputSeqType = baseType.dyn_cast(); unsigned inputTypeRank = maybeInputSeqType ? maybeInputSeqType.getDimension() : 0; unsigned shapeRank = 0; if (mlir::Value shape = getShape()) - if (auto shapeType = mlir::dyn_cast(shape.getType())) + if (auto shapeType = shape.getType().dyn_cast()) shapeRank = shapeType.getRank(); if (inputTypeRank != shapeRank) return emitOpError( "must be provided a shape if and only if the base is an array"); mlir::Type outputBaseType = hlfir::getFortranElementOrSequenceType(getType()); - auto maybeOutputSeqType = mlir::dyn_cast(outputBaseType); + auto maybeOutputSeqType = outputBaseType.dyn_cast(); unsigned outputTypeRank = maybeOutputSeqType ? maybeOutputSeqType.getDimension() : 0; if (inputTypeRank != outputTypeRank) @@ -460,23 +459,23 @@ mlir::LogicalResult hlfir::ParentComponentOp::verify() { return emitOpError( "result type extents are inconsistent with memref type"); fir::RecordType baseRecType = - mlir::dyn_cast(hlfir::getFortranElementType(baseType)); - fir::RecordType outRecType = mlir::dyn_cast( - hlfir::getFortranElementType(outputBaseType)); + hlfir::getFortranElementType(baseType).dyn_cast(); + fir::RecordType outRecType = + hlfir::getFortranElementType(outputBaseType).dyn_cast(); if (!baseRecType || !outRecType) return emitOpError("result type and input type must be derived types"); // Note: result should not be a fir.class: its dynamic type is being set to // the parent type and allowing fir.class would break the operation codegen: // it would keep the input dynamic type. - if (mlir::isa(getType())) + if (getType().isa()) return emitOpError("result type must not be polymorphic"); // The array results are known to not be dis-contiguous in most cases (the // exception being if the parent type was extended by a type without any // components): require a fir.box to be used for the result to carry the // strides. - if (!mlir::isa(getType()) && + if (!getType().isa() && (outputTypeRank != 0 || fir::isRecordWithTypeParameters(outRecType))) return emitOpError("result type must be a fir.box if the result is an " "array or has length parameters"); @@ -497,8 +496,9 @@ verifyLogicalReductionOp(LogicalReductionOp reductionOp) { mlir::Value mask = reductionOp->getMask(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType maskTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(mask.getType())); + fir::SequenceType maskTy = + hlfir::getFortranElementOrSequenceType(mask.getType()) + .cast(); mlir::Type logicalTy = maskTy.getEleTy(); llvm::ArrayRef maskShape = maskTy.getShape(); @@ -576,8 +576,9 @@ mlir::LogicalResult hlfir::CountOp::verify() { mlir::Value mask = getMask(); mlir::Value dim = getDim(); - fir::SequenceType maskTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(mask.getType())); + fir::SequenceType maskTy = + hlfir::getFortranElementOrSequenceType(mask.getType()) + .cast(); llvm::ArrayRef maskShape = maskTy.getShape(); mlir::Type resultType = results[0]; @@ -612,14 +613,13 @@ void hlfir::CountOp::getEffects( //===----------------------------------------------------------------------===// static unsigned getCharacterKind(mlir::Type t) { - return mlir::cast(hlfir::getFortranElementType(t)) - .getFKind(); + return hlfir::getFortranElementType(t).cast().getFKind(); } static std::optional getCharacterLengthIfStatic(mlir::Type t) { if (auto charType = - mlir::dyn_cast(hlfir::getFortranElementType(t))) + hlfir::getFortranElementType(t).dyn_cast()) if (charType.hasConstantLen()) return charType.getLen(); return std::nullopt; @@ -672,13 +672,15 @@ verifyArrayAndMaskForReductionOp(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value mask = reductionOp->getMask(); - fir::SequenceType arrayTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(array.getType())); + fir::SequenceType arrayTy = + hlfir::getFortranElementOrSequenceType(array.getType()) + .cast(); llvm::ArrayRef arrayShape = arrayTy.getShape(); if (mask) { - fir::SequenceType maskSeq = mlir::dyn_cast( - hlfir::getFortranElementOrSequenceType(mask.getType())); + fir::SequenceType maskSeq = + hlfir::getFortranElementOrSequenceType(mask.getType()) + .dyn_cast(); llvm::ArrayRef maskShape; if (maskSeq) @@ -718,8 +720,9 @@ verifyNumericalReductionOp(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(array.getType())); + fir::SequenceType arrayTy = + hlfir::getFortranElementOrSequenceType(array.getType()) + .cast(); mlir::Type numTy = arrayTy.getEleTy(); llvm::ArrayRef arrayShape = arrayTy.getShape(); @@ -787,12 +790,13 @@ verifyCharacterReductionOp(CharacterReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(array.getType())); + fir::SequenceType arrayTy = + hlfir::getFortranElementOrSequenceType(array.getType()) + .cast(); mlir::Type numTy = arrayTy.getEleTy(); llvm::ArrayRef arrayShape = arrayTy.getShape(); - auto resultExpr = mlir::cast(results[0]); + auto resultExpr = results[0].cast(); mlir::Type resultType = resultExpr.getEleTy(); assert(mlir::isa(resultType) && "result must be character"); @@ -877,8 +881,9 @@ verifyResultForMinMaxLoc(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(array.getType())); + fir::SequenceType arrayTy = + hlfir::getFortranElementOrSequenceType(array.getType()) + .cast(); llvm::ArrayRef arrayShape = arrayTy.getShape(); mlir::Type resultType = results[0]; @@ -988,10 +993,12 @@ void hlfir::SumOp::getEffects( mlir::LogicalResult hlfir::DotProductOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(lhs.getType())); - fir::SequenceType rhsTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(rhs.getType())); + fir::SequenceType lhsTy = + hlfir::getFortranElementOrSequenceType(lhs.getType()) + .cast(); + fir::SequenceType rhsTy = + hlfir::getFortranElementOrSequenceType(rhs.getType()) + .cast(); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); @@ -1044,17 +1051,19 @@ void hlfir::DotProductOp::getEffects( mlir::LogicalResult hlfir::MatmulOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(lhs.getType())); - fir::SequenceType rhsTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(rhs.getType())); + fir::SequenceType lhsTy = + hlfir::getFortranElementOrSequenceType(lhs.getType()) + .cast(); + fir::SequenceType rhsTy = + hlfir::getFortranElementOrSequenceType(rhs.getType()) + .cast(); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); std::size_t rhsRank = rhsShape.size(); mlir::Type lhsEleTy = lhsTy.getEleTy(); mlir::Type rhsEleTy = rhsTy.getEleTy(); - hlfir::ExprType resultTy = mlir::cast(getResult().getType()); + hlfir::ExprType resultTy = getResult().getType().cast(); llvm::ArrayRef resultShape = resultTy.getShape(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1171,12 +1180,13 @@ void hlfir::MatmulOp::getEffects( mlir::LogicalResult hlfir::TransposeOp::verify() { mlir::Value array = getArray(); - fir::SequenceType arrayTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(array.getType())); + fir::SequenceType arrayTy = + hlfir::getFortranElementOrSequenceType(array.getType()) + .cast(); llvm::ArrayRef inShape = arrayTy.getShape(); std::size_t rank = inShape.size(); mlir::Type eleTy = arrayTy.getEleTy(); - hlfir::ExprType resultTy = mlir::cast(getResult().getType()); + hlfir::ExprType resultTy = getResult().getType().cast(); llvm::ArrayRef resultShape = resultTy.getShape(); std::size_t resultRank = resultShape.size(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1214,17 +1224,19 @@ void hlfir::TransposeOp::getEffects( mlir::LogicalResult hlfir::MatmulTransposeOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(lhs.getType())); - fir::SequenceType rhsTy = mlir::cast( - hlfir::getFortranElementOrSequenceType(rhs.getType())); + fir::SequenceType lhsTy = + hlfir::getFortranElementOrSequenceType(lhs.getType()) + .cast(); + fir::SequenceType rhsTy = + hlfir::getFortranElementOrSequenceType(rhs.getType()) + .cast(); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); std::size_t rhsRank = rhsShape.size(); mlir::Type lhsEleTy = lhsTy.getEleTy(); mlir::Type rhsEleTy = rhsTy.getEleTy(); - hlfir::ExprType resultTy = mlir::cast(getResult().getType()); + hlfir::ExprType resultTy = getResult().getType().cast(); llvm::ArrayRef resultShape = resultTy.getShape(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1369,7 +1381,7 @@ void hlfir::AsExprOp::build(mlir::OpBuilder &builder, hlfir::ExprType::Shape typeShape; bool isPolymorphic = fir::isPolymorphicType(var.getType()); mlir::Type type = getFortranElementOrSequenceType(var.getType()); - if (auto seqType = mlir::dyn_cast(type)) { + if (auto seqType = type.dyn_cast()) { typeShape.append(seqType.getShape().begin(), seqType.getShape().end()); type = seqType.getEleTy(); } @@ -1415,7 +1427,7 @@ static void buildElemental(mlir::OpBuilder &builder, isUnordered ? builder.getUnitAttr() : nullptr); mlir::Region *bodyRegion = odsState.addRegion(); bodyRegion->push_back(new mlir::Block{}); - if (auto shapeType = mlir::dyn_cast(shape.getType())) { + if (auto shapeType = shape.getType().dyn_cast()) { unsigned dim = shapeType.getRank(); mlir::Type indexType = builder.getIndexType(); for (unsigned d = 0; d < dim; ++d) @@ -1456,7 +1468,7 @@ void hlfir::ApplyOp::build(mlir::OpBuilder &builder, mlir::ValueRange indices, mlir::ValueRange typeparams) { mlir::Type resultType = expr.getType(); - if (auto exprType = mlir::dyn_cast(resultType)) + if (auto exprType = resultType.dyn_cast()) resultType = exprType.getElementExprType(); build(builder, odsState, resultType, expr, indices, typeparams); } @@ -1505,20 +1517,20 @@ void hlfir::CopyInOp::build(mlir::OpBuilder &builder, void hlfir::ShapeOfOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, mlir::Value expr) { - hlfir::ExprType exprTy = mlir::cast(expr.getType()); + hlfir::ExprType exprTy = expr.getType().cast(); mlir::Type type = fir::ShapeType::get(builder.getContext(), exprTy.getRank()); build(builder, result, type, expr); } std::size_t hlfir::ShapeOfOp::getRank() { mlir::Type resTy = getResult().getType(); - fir::ShapeType shape = mlir::cast(resTy); + fir::ShapeType shape = resTy.cast(); return shape.getRank(); } mlir::LogicalResult hlfir::ShapeOfOp::verify() { mlir::Value expr = getExpr(); - hlfir::ExprType exprTy = mlir::cast(expr.getType()); + hlfir::ExprType exprTy = expr.getType().cast(); std::size_t exprRank = exprTy.getShape().size(); if (exprRank == 0) @@ -1537,8 +1549,7 @@ hlfir::ShapeOfOp::canonicalize(ShapeOfOp shapeOf, // if extent information is available at compile time, immediately fold the // hlfir.shape_of into a fir.shape mlir::Location loc = shapeOf.getLoc(); - hlfir::ExprType expr = - mlir::cast(shapeOf.getExpr().getType()); + hlfir::ExprType expr = shapeOf.getExpr().getType().cast(); mlir::Value shape = hlfir::genExprShape(rewriter, loc, expr); if (!shape) @@ -1563,7 +1574,7 @@ void hlfir::GetExtentOp::build(mlir::OpBuilder &builder, } mlir::LogicalResult hlfir::GetExtentOp::verify() { - fir::ShapeType shapeTy = mlir::cast(getShape().getType()); + fir::ShapeType shapeTy = getShape().getType().cast(); std::uint64_t rank = shapeTy.getRank(); llvm::APInt dim = getDim(); if (dim.sge(rank)) @@ -1698,11 +1709,10 @@ mlir::LogicalResult hlfir::ElementalAddrOp::verify() { return emitOpError("body region must be terminated by an hlfir.yield"); mlir::Type elementAddrType = yieldOp.getEntity().getType(); if (!hlfir::isFortranVariableType(elementAddrType) || - mlir::isa( - hlfir::getFortranElementOrSequenceType(elementAddrType))) + hlfir::getFortranElementOrSequenceType(elementAddrType) + .isa()) return emitOpError("body must compute the address of a scalar entity"); - unsigned shapeRank = - mlir::cast(getShape().getType()).getRank(); + unsigned shapeRank = getShape().getType().cast().getRank(); if (shapeRank != getIndices().size()) return emitOpError("body number of indices must match shape rank"); return mlir::success(); @@ -1807,8 +1817,8 @@ static bool yieldsLogical(mlir::Region ®ion, bool mustBeScalarI1) { if (mustBeScalarI1) return hlfir::isI1Type(yieldType); return hlfir::isMaskArgument(yieldType) && - mlir::isa( - hlfir::getFortranElementOrSequenceType(yieldType)); + hlfir::getFortranElementOrSequenceType(yieldType) + .isa(); } mlir::LogicalResult hlfir::ForallMaskOp::verify() { diff --git a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp index d4e4835ee726..1c4f82e2de81 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp @@ -77,7 +77,7 @@ static mlir::Value packageBufferizedExpr(mlir::Location loc, /// currently enforced by the verifiers that only accept HLFIR value or /// variable types which do not include tuples. static hlfir::Entity getBufferizedExprStorage(mlir::Value bufferizedExpr) { - auto tupleType = mlir::dyn_cast(bufferizedExpr.getType()); + auto tupleType = bufferizedExpr.getType().dyn_cast(); if (!tupleType) return hlfir::Entity{bufferizedExpr}; assert(tupleType.size() == 2 && "unexpected tuple type"); @@ -90,7 +90,7 @@ static hlfir::Entity getBufferizedExprStorage(mlir::Value bufferizedExpr) { /// Helper to extract the clean-up flag from a tuple created by /// packageBufferizedExpr. static mlir::Value getBufferizedExprMustFreeFlag(mlir::Value bufferizedExpr) { - auto tupleType = mlir::dyn_cast(bufferizedExpr.getType()); + auto tupleType = bufferizedExpr.getType().dyn_cast(); if (!tupleType) return bufferizedExpr; assert(tupleType.size() == 2 && "unexpected tuple type"); @@ -218,7 +218,7 @@ struct ShapeOfOpConversion } else { // everything else failed so try to create a shape from static type info hlfir::ExprType exprTy = - mlir::dyn_cast_or_null(adaptor.getExpr().getType()); + adaptor.getExpr().getType().dyn_cast_or_null(); if (exprTy) shape = hlfir::genExprShape(builder, loc, exprTy); } @@ -480,10 +480,10 @@ struct AssociateOpConversion assert(mlir::isa(sourceVar.getType()) && fir::isAllocatableType(sourceVar.getType())); assert(sourceVar.getType() == assocType); - } else if ((mlir::isa(sourceVar.getType()) && - !mlir::isa(assocType)) || - ((mlir::isa(sourceVar.getType()) && - !mlir::isa(assocType)))) { + } else if ((sourceVar.getType().isa() && + !assocType.isa()) || + ((sourceVar.getType().isa() && + !assocType.isa()))) { sourceVar = builder.create(loc, assocType, sourceVar); } else { sourceVar = builder.createConvert(loc, assocType, sourceVar); @@ -590,13 +590,13 @@ static void genBufferDestruction(mlir::Location loc, fir::FirOpBuilder &builder, // for MERGE with polymorphic results. if (mustFinalize) TODO(loc, "finalizing polymorphic temporary in HLFIR"); - } else if (mlir::isa(var.getType())) { + } else if (var.getType().isa()) { if (mustFinalize && !mlir::isa(var.getType())) fir::emitFatalError(loc, "non-finalizable variable"); addr = builder.create(loc, heapType, var); } else { - if (!mlir::isa(var.getType())) + if (!var.getType().isa()) addr = builder.create(loc, heapType, var); if (mustFinalize || deallocComponents) { @@ -831,7 +831,7 @@ struct ElementalOpConversion // the assign, insert an hlfir.destroy to mark the expression end-of-life. // If the expression creation allocated a buffer on the heap inside the // loop, this will ensure the buffer properly deallocated. - if (mlir::isa(elementValue.getType()) && + if (elementValue.getType().isa() && wasCreatedInCurrentBlock(elementValue, builder)) builder.create(loc, elementValue); } @@ -926,12 +926,11 @@ public: hlfir::EndAssociateOp, hlfir::SetLengthOp>(); target.markUnknownOpDynamicallyLegal([](mlir::Operation *op) { - return llvm::all_of(op->getResultTypes(), - [](mlir::Type ty) { - return !mlir::isa(ty); - }) && + return llvm::all_of( + op->getResultTypes(), + [](mlir::Type ty) { return !ty.isa(); }) && llvm::all_of(op->getOperandTypes(), [](mlir::Type ty) { - return !mlir::isa(ty); + return !ty.isa(); }); }); if (mlir::failed( diff --git a/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp index 517285dce133..cd534bae4ad2 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp @@ -34,7 +34,7 @@ using namespace mlir; static mlir::Value genAllocatableTempFromSourceBox(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value sourceBox) { - assert(mlir::isa(sourceBox.getType()) && + assert(sourceBox.getType().isa() && "must be a base box type"); // Use the runtime to make a quick and dirty temp with the rhs value. // Overkill for scalar rhs that could be done in much more clever ways. @@ -44,7 +44,7 @@ static mlir::Value genAllocatableTempFromSourceBox(mlir::Location loc, // This has the huge benefit of dealing with all cases, including // polymorphic entities. mlir::Type fromHeapType = fir::HeapType::get(fir::unwrapRefType( - mlir::cast(sourceBox.getType()).getEleTy())); + sourceBox.getType().cast().getEleTy())); mlir::Type fromBoxHeapType = fir::BoxType::get(fromHeapType); mlir::Value fromMutableBox = fir::factory::genNullBoxStorage(builder, loc, fromBoxHeapType); @@ -69,7 +69,7 @@ public: auto module = assignOp->getParentOfType(); fir::FirOpBuilder builder(rewriter, module); - if (mlir::isa(rhs.getType())) { + if (rhs.getType().isa()) { mlir::emitError(loc, "hlfir must be bufferized with --bufferize-hlfir " "pass before being converted to FIR"); return mlir::failure(); @@ -343,15 +343,16 @@ public: auto firBase = firDeclareOp.getResult(); mlir::Value hlfirBase; mlir::Type hlfirBaseType = declareOp.getBase().getType(); - if (mlir::isa(hlfirBaseType)) { + if (hlfirBaseType.isa()) { fir::FirOpBuilder builder(rewriter, declareOp.getOperation()); // Helper to generate the hlfir fir.box with the local lower bounds and // type parameters. auto genHlfirBox = [&]() -> mlir::Value { - if (!mlir::isa(firBase.getType())) { + if (!firBase.getType().isa()) { llvm::SmallVector typeParams; - auto maybeCharType = mlir::dyn_cast( - fir::unwrapSequenceType(fir::unwrapPassByRefType(hlfirBaseType))); + auto maybeCharType = + fir::unwrapSequenceType(fir::unwrapPassByRefType(hlfirBaseType)) + .dyn_cast(); if (!maybeCharType || maybeCharType.hasDynamicLen()) typeParams.append(declareOp.getTypeparams().begin(), declareOp.getTypeparams().end()); @@ -398,7 +399,7 @@ public: }) .getResults()[0]; } - } else if (mlir::isa(hlfirBaseType)) { + } else if (hlfirBaseType.isa()) { assert(declareOp.getTypeparams().size() == 1 && "must contain character length"); hlfirBase = rewriter.create( @@ -479,12 +480,11 @@ public: // - scalar%scalar_component [substring|complex_part] or // - scalar%static_size_array_comp // - scalar%array(indices) [substring| complex part] - mlir::Type componentType = - mlir::cast(baseEleTy).getType( - designate.getComponent().value()); + mlir::Type componentType = baseEleTy.cast().getType( + designate.getComponent().value()); mlir::Type coorTy = fir::ReferenceType::get(componentType); base = builder.create(loc, coorTy, base, fieldIndex); - if (mlir::isa(componentType)) { + if (componentType.isa()) { auto variableInterface = mlir::cast( designate.getOperation()); if (variableInterface.isAllocatable() || @@ -500,14 +500,14 @@ public: } else { // array%component[(indices) substring|complex part] cases. // Component ref of array bases are dealt with below in embox/rebox. - assert(mlir::isa(designateResultType)); + assert(designateResultType.isa()); } } - if (mlir::isa(designateResultType)) { + if (designateResultType.isa()) { // Generate embox or rebox. mlir::Type eleTy = fir::unwrapPassByRefType(designateResultType); - bool isScalarDesignator = !mlir::isa(eleTy); + bool isScalarDesignator = !eleTy.isa(); mlir::Value sourceBox; if (isScalarDesignator) { // The base box will be used for emboxing the scalar element. @@ -583,7 +583,7 @@ public: assert(sliceFields.empty() && substring.empty()); llvm::SmallVector resultType{designateResultType}; mlir::Value resultBox; - if (mlir::isa(base.getType())) + if (base.getType().isa()) resultBox = builder.create(loc, resultType, base, shape, slice); else @@ -598,8 +598,7 @@ public: // first element of a contiguous array section with compile time constant // shape. The base may be an array, or a scalar. mlir::Type resultAddressType = designateResultType; - if (auto boxCharType = - mlir::dyn_cast(designateResultType)) + if (auto boxCharType = designateResultType.dyn_cast()) resultAddressType = fir::ReferenceType::get(boxCharType.getEleTy()); // Array element indexing. @@ -621,7 +620,7 @@ public: // Scalar complex part ref if (designate.getComplexPart()) { // Sequence types should have already been handled by this point - assert(!mlir::isa(designateResultType)); + assert(!designateResultType.isa()); auto index = builder.createIntegerConstant(loc, builder.getIndexType(), *designate.getComplexPart()); auto coorTy = fir::ReferenceType::get(resultEleTy); @@ -629,7 +628,7 @@ public: } // Cast/embox the computed scalar address if needed. - if (mlir::isa(designateResultType)) { + if (designateResultType.isa()) { assert(designate.getTypeparams().size() == 1 && "must have character length"); auto emboxChar = builder.create( @@ -672,13 +671,13 @@ public: mlir::PatternRewriter &rewriter) const override { mlir::Location loc = parentComponent.getLoc(); mlir::Type resultType = parentComponent.getType(); - if (!mlir::isa(parentComponent.getType())) { + if (!parentComponent.getType().isa()) { mlir::Value baseAddr = parentComponent.getMemref(); // Scalar parent component ref without any length type parameters. The // input may be a fir.class if it is polymorphic, since this is a scalar // and the output will be monomorphic, the base address can be extracted // from the fir.class. - if (mlir::isa(baseAddr.getType())) + if (baseAddr.getType().isa()) baseAddr = rewriter.create(loc, baseAddr); rewriter.replaceOpWithNewOp(parentComponent, resultType, baseAddr); @@ -687,7 +686,7 @@ public: // Array parent component ref or PDTs. hlfir::Entity base{parentComponent.getMemref()}; mlir::Value baseAddr = base.getBase(); - if (!mlir::isa(baseAddr.getType())) { + if (!baseAddr.getType().isa()) { // Embox cannot directly be used to address parent components: it expects // the output type to match the input type when there are no slices. When // the types have at least one component, a slice to the first element can @@ -749,7 +748,7 @@ public: // the hlfir.shape_of operation which led to the creation of this get_extent // operation should now have been lowered to a fir.shape operation if (auto s = mlir::dyn_cast_or_null(shapeOp)) { - fir::ShapeType shapeTy = mlir::cast(shape.getType()); + fir::ShapeType shapeTy = shape.getType().cast(); llvm::APInt dim = getExtentOp.getDim(); uint64_t dimVal = dim.getLimitedValue(shapeTy.getRank()); mlir::Value extent = s.getExtents()[dimVal]; diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp index e9dbb7095d0e..0142fb0cfb0b 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp @@ -185,7 +185,7 @@ protected: // the width for use in runtime intrinsic calls. static unsigned getKindForType(mlir::Type ty) { mlir::Type eltty = hlfir::getFortranElementType(ty); - unsigned width = mlir::cast(eltty).getWidth(); + unsigned width = eltty.cast().getWidth(); return width / 8; } diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp index 63b52c0cd0bc..84101353a740 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp @@ -1090,7 +1090,7 @@ void OrderedAssignmentRewriter::generateSaveEntity( mlir::Value loopExtent = computeLoopNestIterationNumber(loc, builder, loopNest); auto sequenceType = - mlir::cast(builder.getVarLenSeqTy(entityType)); + builder.getVarLenSeqTy(entityType).cast(); temp = insertSavedEntity(region, fir::factory::HomogeneousScalarStack{ loc, builder, sequenceType, loopExtent, diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp index 8d68c7021608..685c73d67625 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp @@ -249,7 +249,7 @@ static bool areIdenticalOrDisjointSlices(mlir::Value ref1, mlir::Value ref2) { auto isPositiveConstant = [](mlir::Value v) -> bool { if (auto conOp = mlir::dyn_cast(v.getDefiningOp())) - if (auto iattr = mlir::dyn_cast(conOp.getValue())) + if (auto iattr = conOp.getValue().dyn_cast()) return iattr.getInt() > 0; return false; }; @@ -601,7 +601,7 @@ mlir::LogicalResult VariableAssignBufferization::matchAndRewrite( // TODO: ExprType check is here to avoid conflicts with // ElementalAssignBufferization pattern. We need to combine // these matchers into a single one that applies to AssignOp. - if (mlir::isa(rhs.getType())) + if (rhs.getType().isa()) return rewriter.notifyMatchFailure(assign, "RHS is not in memory"); if (!rhs.isArray()) @@ -834,7 +834,7 @@ public: unsigned rank = mlir::cast(mloc.getType()).getShape()[0]; mlir::Type arrayType = array.getType(); - if (!mlir::isa(arrayType)) + if (!arrayType.isa()) return rewriter.notifyMatchFailure( mloc, "Currently requires a boxed type input"); mlir::Type elementType = hlfir::getFortranElementType(arrayType); @@ -850,7 +850,7 @@ public: auto init = [isMax](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = mlir::dyn_cast(elementType)) { + if (auto ty = elementType.dyn_cast()) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); llvm::APFloat limit = llvm::APFloat::getInf(sem, /*Negative=*/isMax); return builder.createRealConstant(loc, elementType, limit); @@ -901,7 +901,7 @@ public: // Compare with the max reduction value mlir::Value cmp; - if (mlir::isa(elementType)) { + if (elementType.isa()) { // For FP reductions we want the first smallest value to be used, that // is not NaN. A OGL/OLT condition will usually work for this unless all // the values are Nan or Inf. This follows the same logic as @@ -918,7 +918,7 @@ public: loc, mlir::arith::CmpFPredicate::OEQ, elem, elem); cmpNan = builder.create(loc, cmpNan, cmpNan2); cmp = builder.create(loc, cmp, cmpNan); - } else if (mlir::isa(elementType)) { + } else if (elementType.isa()) { cmp = builder.create( loc, isMax ? mlir::arith::CmpIPredicate::sgt diff --git a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp index b761563eba0f..2751575ce982 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp @@ -103,8 +103,7 @@ public: // by hlfir.elemental) target.addDynamicallyLegalOp( [](hlfir::TransposeOp transpose) { - return mlir::cast(transpose.getType()) - .isPolymorphic(); + return transpose.getType().cast().isPolymorphic(); }); target.markUnknownOpDynamicallyLegal( [](mlir::Operation *) { return true; }); diff --git a/flang/lib/Optimizer/Transforms/AbstractResult.cpp b/flang/lib/Optimizer/Transforms/AbstractResult.cpp index 85472cdc5103..eb4dd637bb16 100644 --- a/flang/lib/Optimizer/Transforms/AbstractResult.cpp +++ b/flang/lib/Optimizer/Transforms/AbstractResult.cpp @@ -65,14 +65,14 @@ static mlir::FunctionType getCPtrFunctionType(mlir::FunctionType funcTy) { auto resultType = funcTy.getResult(0); assert(fir::isa_builtin_cptr_type(resultType)); llvm::SmallVector outputTypes; - auto recTy = mlir::dyn_cast(resultType); + auto recTy = resultType.dyn_cast(); outputTypes.emplace_back(recTy.getTypeList()[0].second); return mlir::FunctionType::get(funcTy.getContext(), funcTy.getInputs(), outputTypes); } static bool mustEmboxResult(mlir::Type resultType, bool shouldBoxResult) { - return mlir::isa(resultType) && + return resultType.isa() && shouldBoxResult; } @@ -114,7 +114,7 @@ public: bool isResultBuiltinCPtr = fir::isa_builtin_cptr_type(result.getType()); Op newOp; if (isResultBuiltinCPtr) { - auto recTy = mlir::dyn_cast(result.getType()); + auto recTy = result.getType().template dyn_cast(); newResultTypes.emplace_back(recTy.getTypeList()[0].second); } @@ -261,7 +261,7 @@ public: mlir::LogicalResult matchAndRewrite(fir::AddrOfOp addrOf, mlir::PatternRewriter &rewriter) const override { - auto oldFuncTy = mlir::cast(addrOf.getType()); + auto oldFuncTy = addrOf.getType().cast(); mlir::FunctionType newFuncTy; // TODO: This should be generalized for derived types, and it is // architecture and OS dependent. @@ -296,7 +296,7 @@ public: auto loc = func.getLoc(); auto *context = &getContext(); // Convert function type itself if it has an abstract result. - auto funcTy = mlir::cast(func.getFunctionType()); + auto funcTy = func.getFunctionType().cast(); if (hasAbstractResult(funcTy)) { // TODO: This should be generalized for derived types, and it is // architecture and OS dependent. @@ -343,11 +343,11 @@ public: return mlir::TypeSwitch(type) .Case([](fir::BoxProcType boxProc) { return fir::hasAbstractResult( - mlir::cast(boxProc.getEleTy())); + boxProc.getEleTy().cast()); }) .Case([](fir::PointerType pointer) { return fir::hasAbstractResult( - mlir::cast(pointer.getEleTy())); + pointer.getEleTy().cast()); }) .Default([](auto &&) { return false; }); } @@ -411,7 +411,7 @@ public: return !hasAbstractResult(call.getFunctionType()); }); target.addDynamicallyLegalOp([](fir::AddrOfOp addrOf) { - if (auto funTy = mlir::dyn_cast(addrOf.getType())) + if (auto funTy = addrOf.getType().dyn_cast()) return !hasAbstractResult(funTy); return true; }); diff --git a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp index 18d98a11ef3c..68584bef055b 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp @@ -69,7 +69,7 @@ void AddDebugInfoPass::runOnOperation() { // In that case, 'inputFilename' may be empty. Location embedded in the // module will be used to get file name and its directory. if (inputFilename.empty()) { - if (auto fileLoc = mlir::dyn_cast(module.getLoc())) { + if (auto fileLoc = module.getLoc().dyn_cast()) { fileName = llvm::sys::path::filename(fileLoc.getFilename().getValue()); filePath = llvm::sys::path::parent_path(fileLoc.getFilename().getValue()); } else @@ -94,14 +94,14 @@ void AddDebugInfoPass::runOnOperation() { mlir::Location l = funcOp->getLoc(); // If fused location has already been created then nothing to do // Otherwise, create a fused location. - if (mlir::dyn_cast(l)) + if (l.dyn_cast()) return; unsigned int CC = (funcOp.getName() == fir::NameUniquer::doProgramEntry()) ? llvm::dwarf::getCallingConvention("DW_CC_program") : llvm::dwarf::getCallingConvention("DW_CC_normal"); - if (auto funcLoc = mlir::dyn_cast(l)) { + if (auto funcLoc = l.dyn_cast()) { fileName = llvm::sys::path::filename(funcLoc.getFilename().getValue()); filePath = llvm::sys::path::parent_path(funcLoc.getFilename().getValue()); } diff --git a/flang/lib/Optimizer/Transforms/AffineDemotion.cpp b/flang/lib/Optimizer/Transforms/AffineDemotion.cpp index b4523a060f5a..da29ae880700 100644 --- a/flang/lib/Optimizer/Transforms/AffineDemotion.cpp +++ b/flang/lib/Optimizer/Transforms/AffineDemotion.cpp @@ -98,15 +98,14 @@ public: mlir::LogicalResult matchAndRewrite(fir::ConvertOp op, mlir::PatternRewriter &rewriter) const override { - if (mlir::isa(op.getRes().getType())) { + if (op.getRes().getType().isa()) { // due to index calculation moving to affine maps we still need to // add converts for sequence types this has a side effect of losing // some information about arrays with known dimensions by creating: // fir.convert %arg0 : (!fir.ref>) -> // !fir.ref> - if (auto refTy = - mlir::dyn_cast(op.getValue().getType())) - if (auto arrTy = mlir::dyn_cast(refTy.getEleTy())) { + if (auto refTy = op.getValue().getType().dyn_cast()) + if (auto arrTy = refTy.getEleTy().dyn_cast()) { fir::SequenceType::Shape flatShape = { fir::SequenceType::getUnknownExtent()}; auto flatArrTy = fir::SequenceType::get(flatShape, arrTy.getEleTy()); @@ -159,7 +158,7 @@ public: mlir::ConversionTarget target(*context); target.addIllegalOp(); target.addDynamicallyLegalOp([](fir::ConvertOp op) { - if (mlir::isa(op.getRes().getType())) + if (op.getRes().getType().isa()) return false; return true; }); diff --git a/flang/lib/Optimizer/Transforms/AffinePromotion.cpp b/flang/lib/Optimizer/Transforms/AffinePromotion.cpp index 7d0131ac6fa4..64531cb1868e 100644 --- a/flang/lib/Optimizer/Transforms/AffinePromotion.cpp +++ b/flang/lib/Optimizer/Transforms/AffinePromotion.cpp @@ -111,7 +111,7 @@ private: bool analyzeReference(mlir::Value memref, mlir::Operation *op) { if (auto acoOp = memref.getDefiningOp()) { - if (mlir::isa(acoOp.getMemref().getType())) { + if (acoOp.getMemref().getType().isa()) { // TODO: Look if and how fir.box can be promoted to affine. LLVM_DEBUG(llvm::dbgs() << "AffineLoopAnalysis: cannot promote loop, " "array memory operation uses fir.box\n"; @@ -222,7 +222,7 @@ private: return affineBinaryOp(mlir::AffineExprKind::Mod, op.getLhs(), op.getRhs()); if (auto op = value.getDefiningOp()) - if (auto intConstant = mlir::dyn_cast(op.getValue())) + if (auto intConstant = op.getValue().dyn_cast()) return toAffineExpr(intConstant.getInt()); if (auto blockArg = mlir::dyn_cast(value)) { affineArgs.push_back(value); @@ -331,16 +331,15 @@ static mlir::AffineMap createArrayIndexAffineMap(unsigned dimensions, static std::optional constantIntegerLike(const mlir::Value value) { if (auto definition = value.getDefiningOp()) - if (auto stepAttr = mlir::dyn_cast(definition.getValue())) + if (auto stepAttr = definition.getValue().dyn_cast()) return stepAttr.getInt(); return {}; } static mlir::Type coordinateArrayElement(fir::ArrayCoorOp op) { if (auto refType = - mlir::dyn_cast_or_null(op.getMemref().getType())) { - if (auto seqType = - mlir::dyn_cast_or_null(refType.getEleTy())) { + op.getMemref().getType().dyn_cast_or_null()) { + if (auto seqType = refType.getEleTy().dyn_cast_or_null()) { return seqType.getEleTy(); } } diff --git a/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp b/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp index ebc186222525..a08d58383d3a 100644 --- a/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp +++ b/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp @@ -461,9 +461,9 @@ void ArrayCopyAnalysisBase::arrayMentions( } static bool hasPointerType(mlir::Type type) { - if (auto boxTy = mlir::dyn_cast(type)) + if (auto boxTy = type.dyn_cast()) type = boxTy.getEleTy(); - return mlir::isa(type); + return type.isa(); } // This is a NF performance hack. It makes a simple test that the slices of the @@ -512,7 +512,7 @@ static bool mutuallyExclusiveSliceRange(ArrayLoadOp ld, ArrayMergeStoreOp st) { auto isPositiveConstant = [](mlir::Value v) -> bool { if (auto conOp = mlir::dyn_cast(v.getDefiningOp())) - if (auto iattr = mlir::dyn_cast(conOp.getValue())) + if (auto iattr = conOp.getValue().dyn_cast()) return iattr.getInt() > 0; return false; }; @@ -725,8 +725,8 @@ static bool conservativeCallConflict(llvm::ArrayRef reaches) { return llvm::any_of(reaches, [](mlir::Operation *op) { if (auto call = mlir::dyn_cast(op)) - if (auto callee = mlir::dyn_cast( - call.getCallableForCallee())) { + if (auto callee = + call.getCallableForCallee().dyn_cast()) { auto module = op->getParentOfType(); return isInternalProcedure( module.lookupSymbol(callee)); @@ -891,9 +891,9 @@ static mlir::Value getOrReadExtentsAndShapeOp( if (arrLoad->hasAttr(fir::getOptionalAttrName())) fir::emitFatalError( loc, "shapes from array load of OPTIONAL arrays must not be used"); - if (auto boxTy = mlir::dyn_cast(arrLoad.getMemref().getType())) { + if (auto boxTy = arrLoad.getMemref().getType().dyn_cast()) { auto rank = - mlir::cast(dyn_cast_ptrOrBoxEleTy(boxTy)).getDimension(); + dyn_cast_ptrOrBoxEleTy(boxTy).cast().getDimension(); auto idxTy = rewriter.getIndexType(); for (decltype(rank) dim = 0; dim < rank; ++dim) { auto dimVal = rewriter.create(loc, dim); @@ -929,7 +929,7 @@ static mlir::Type toRefType(mlir::Type ty) { static llvm::SmallVector getTypeParamsIfRawData(mlir::Location loc, FirOpBuilder &builder, ArrayLoadOp arrLoad, mlir::Type ty) { - if (mlir::isa(ty)) + if (ty.isa()) return {}; return fir::factory::getTypeParams(loc, builder, arrLoad); } @@ -947,8 +947,8 @@ static mlir::Value genCoorOp(mlir::PatternRewriter &rewriter, originated = factory::originateIndices(loc, rewriter, alloc.getType(), shape, indices); auto seqTy = dyn_cast_ptrOrBoxEleTy(alloc.getType()); - assert(seqTy && mlir::isa(seqTy)); - const auto dimension = mlir::cast(seqTy).getDimension(); + assert(seqTy && seqTy.isa()); + const auto dimension = seqTy.cast().getDimension(); auto module = load->getParentOfType(); FirOpBuilder builder(rewriter, module); auto typeparams = getTypeParamsIfRawData(loc, builder, load, alloc.getType()); @@ -967,7 +967,7 @@ static mlir::Value getCharacterLen(mlir::Location loc, FirOpBuilder &builder, ArrayLoadOp load, CharacterType charTy) { auto charLenTy = builder.getCharacterLengthType(); if (charTy.hasDynamicLen()) { - if (mlir::isa(load.getMemref().getType())) { + if (load.getMemref().getType().isa()) { // The loaded array is an emboxed value. Get the CHARACTER length from // the box value. auto eleSzInBytes = @@ -1027,7 +1027,7 @@ void genArrayCopy(mlir::Location loc, mlir::PatternRewriter &rewriter, getTypeParamsIfRawData(loc, builder, arrLoad, dst.getType())); auto eleTy = unwrapSequenceType(unwrapPassByRefType(dst.getType())); // Copy from (to) object to (from) temp copy of same object. - if (auto charTy = mlir::dyn_cast(eleTy)) { + if (auto charTy = eleTy.dyn_cast()) { auto len = getCharacterLen(loc, builder, arrLoad, charTy); CharBoxValue toChar(toAddr, len); CharBoxValue fromChar(fromAddr, len); @@ -1049,8 +1049,8 @@ genArrayLoadTypeParameters(mlir::Location loc, mlir::PatternRewriter &rewriter, auto eleTy = unwrapSequenceType(unwrapPassByRefType(load.getMemref().getType())); if (hasDynamicSize(eleTy)) { - if (auto charTy = mlir::dyn_cast(eleTy)) { - assert(mlir::isa(load.getMemref().getType())); + if (auto charTy = eleTy.dyn_cast()) { + assert(load.getMemref().getType().isa()); auto module = load->getParentOfType(); FirOpBuilder builder(rewriter, module); return {getCharacterLen(loc, builder, load, charTy)}; @@ -1067,7 +1067,7 @@ findNonconstantExtents(mlir::Type memrefTy, llvm::ArrayRef extents) { llvm::SmallVector nce; auto arrTy = unwrapPassByRefType(memrefTy); - auto seqTy = mlir::cast(arrTy); + auto seqTy = arrTy.cast(); for (auto [s, x] : llvm::zip(seqTy.getShape(), extents)) if (s == SequenceType::getUnknownExtent()) nce.emplace_back(x); diff --git a/flang/lib/Optimizer/Transforms/CharacterConversion.cpp b/flang/lib/Optimizer/Transforms/CharacterConversion.cpp index 44baad73aa25..87ea72dbca9b 100644 --- a/flang/lib/Optimizer/Transforms/CharacterConversion.cpp +++ b/flang/lib/Optimizer/Transforms/CharacterConversion.cpp @@ -60,8 +60,8 @@ public: // For each code point in the `from` string, convert naively to the `to` // string code point. Conversion is done blindly on size only, not value. auto getCharBits = [&](mlir::Type t) { - auto chrTy = mlir::cast( - fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t))); + auto chrTy = fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t)) + .cast(); return kindMap.getCharacterBitsize(chrTy.getFKind()); }; auto fromBits = getCharBits(conv.getFrom().getType()); diff --git a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp index 38cdc2b1388d..0afc9c24b45b 100644 --- a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp +++ b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp @@ -147,7 +147,7 @@ struct ArgsUsageInLoop { static fir::SequenceType getAsSequenceType(mlir::Value *v) { mlir::Type argTy = fir::unwrapPassByRefType(fir::unwrapRefType(v->getType())); - return mlir::dyn_cast(argTy); + return argTy.dyn_cast(); } /// if a value comes from a fir.declare, follow it to the original source, diff --git a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp index ada67b4201e1..40b452a6202b 100644 --- a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp +++ b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp @@ -65,7 +65,7 @@ keepStackAllocation(fir::AllocaOp alloca, mlir::Block *entry, // TODO: Generalize the algorithm and placement of the freemem nodes. if (alloca->getBlock() != entry) return true; - if (auto seqTy = mlir::dyn_cast(alloca.getInType())) { + if (auto seqTy = alloca.getInType().dyn_cast()) { if (fir::hasDynamicSize(seqTy)) { // Move all arrays with runtime determined size to the heap. if (options.dynamicArrayOnHeap) diff --git a/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp b/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp index d933dc58f375..93efea434cb1 100644 --- a/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp +++ b/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp @@ -97,8 +97,8 @@ struct DispatchOpConv : public OpConversionPattern { // Get derived type information. mlir::Type declaredType = fir::getDerivedType(dispatch.getObject().getType().getEleTy()); - assert(mlir::isa(declaredType) && "expecting fir.type"); - auto recordType = mlir::dyn_cast(declaredType); + assert(declaredType.isa() && "expecting fir.type"); + auto recordType = declaredType.dyn_cast(); // Lookup for the binding table. auto bindingsIter = bindingTables.find(recordType.getName()); @@ -157,7 +157,7 @@ struct DispatchOpConv : public OpConversionPattern { // Load the bindings descriptor. auto bindingsCompName = Fortran::semantics::bindingDescCompName; - fir::RecordType typeDescRecTy = mlir::cast(typeDescTy); + fir::RecordType typeDescRecTy = typeDescTy.cast(); mlir::Value field = rewriter.create( loc, fieldTy, bindingsCompName, typeDescRecTy, mlir::ValueRange{}); mlir::Type coorTy = @@ -168,8 +168,8 @@ struct DispatchOpConv : public OpConversionPattern { // Load the correct binding. mlir::Value bindings = rewriter.create(loc, bindingBox); - fir::RecordType bindingTy = fir::unwrapIfDerived( - mlir::cast(bindingBox.getType())); + fir::RecordType bindingTy = + fir::unwrapIfDerived(bindingBox.getType().cast()); mlir::Type bindingAddrTy = fir::ReferenceType::get(bindingTy); mlir::Value bindingIdxVal = rewriter.create( loc, rewriter.getIndexType(), rewriter.getIndexAttr(bindingIdx)); @@ -181,7 +181,7 @@ struct DispatchOpConv : public OpConversionPattern { mlir::Value procField = rewriter.create( loc, fieldTy, procCompName, bindingTy, mlir::ValueRange{}); fir::RecordType procTy = - mlir::cast(bindingTy.getType(procCompName)); + bindingTy.getType(procCompName).cast(); mlir::Type procRefTy = fir::ReferenceType::get(procTy); mlir::Value procRef = rewriter.create( loc, procRefTy, bindingAddr, procField); @@ -298,13 +298,13 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( // before in the list to respect point 3. above. Otherwise it is just // added in order at the end. for (unsigned t = 0; t < typeGuardNum; ++t) { - if (auto a = mlir::dyn_cast(typeGuards[t])) { + if (auto a = typeGuards[t].dyn_cast()) { orderedTypeGuards.push_back(t); continue; } - if (auto a = mlir::dyn_cast(typeGuards[t])) { - if (auto recTy = mlir::dyn_cast(a.getType())) { + if (auto a = typeGuards[t].dyn_cast()) { + if (auto recTy = a.getType().dyn_cast()) { auto dt = mod.lookupSymbol(recTy.getName()); assert(dt && "dispatch table not found"); llvm::SmallSet ancestors = @@ -313,8 +313,8 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( auto it = orderedClassIsGuards.begin(); while (it != orderedClassIsGuards.end()) { fir::SubclassAttr sAttr = - mlir::dyn_cast(typeGuards[*it]); - if (auto ty = mlir::dyn_cast(sAttr.getType())) { + typeGuards[*it].dyn_cast(); + if (auto ty = sAttr.getType().dyn_cast()) { if (ancestors.contains(ty.getName())) break; } @@ -339,7 +339,7 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( auto *dest = selectType.getSuccessor(idx); std::optional destOps = selectType.getSuccessorOperands(operands, idx); - if (mlir::dyn_cast(typeGuards[idx])) + if (typeGuards[idx].dyn_cast()) rewriter.replaceOpWithNewOp( selectType, dest, destOps.value_or(mlir::ValueRange{})); else if (mlir::failed(genTypeLadderStep(loc, selector, typeGuards[idx], @@ -357,9 +357,9 @@ mlir::LogicalResult SelectTypeConv::genTypeLadderStep( fir::KindMapping &kindMap) const { mlir::Value cmp; // TYPE IS type guard comparison are all done inlined. - if (auto a = mlir::dyn_cast(attr)) { + if (auto a = attr.dyn_cast()) { if (fir::isa_trivial(a.getType()) || - mlir::isa(a.getType())) { + a.getType().isa()) { // For type guard statement with Intrinsic type spec the type code of // the descriptor is compared. int code = fir::getTypeCode(a.getType(), kindMap); @@ -383,10 +383,10 @@ mlir::LogicalResult SelectTypeConv::genTypeLadderStep( cmp = res; } // CLASS IS type guard statement is done with a runtime call. - } else if (auto a = mlir::dyn_cast(attr)) { + } else if (auto a = attr.dyn_cast()) { // Retrieve the type descriptor from the type guard statement record type. - assert(mlir::isa(a.getType()) && "expect fir.record type"); - fir::RecordType recTy = mlir::dyn_cast(a.getType()); + assert(a.getType().isa() && "expect fir.record type"); + fir::RecordType recTy = a.getType().dyn_cast(); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recTy.getName()); auto typeDescGlobal = mod.lookupSymbol(typeDescName); @@ -438,8 +438,8 @@ mlir::Value SelectTypeConv::genTypeDescCompare(mlir::Location loc, mlir::Value selector, mlir::Type ty, mlir::ModuleOp mod, mlir::PatternRewriter &rewriter) const { - assert(mlir::isa(ty) && "expect fir.record type"); - fir::RecordType recTy = mlir::dyn_cast(ty); + assert(ty.isa() && "expect fir.record type"); + fir::RecordType recTy = ty.dyn_cast(); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recTy.getName()); auto typeDescGlobal = mod.lookupSymbol(typeDescName); diff --git a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp index 601bf04ce5e9..a4f2f5238e40 100644 --- a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp +++ b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp @@ -215,8 +215,8 @@ static unsigned getDimCount(mlir::Value val) { // the first ConvertOp that has non-opaque box type that we meet // going through the ConvertOp chain. if (mlir::Value emboxVal = findBoxDef(val)) - if (auto boxTy = mlir::dyn_cast(emboxVal.getType())) - if (auto seqTy = mlir::dyn_cast(boxTy.getEleTy())) + if (auto boxTy = emboxVal.getType().dyn_cast()) + if (auto seqTy = boxTy.getEleTy().dyn_cast()) return seqTy.getDimension(); return 0; } @@ -237,9 +237,9 @@ static std::optional getArgElementType(mlir::Value val) { val = defOp->getOperand(0); // The convert operation is expected to convert from one // box type to another box type. - auto boxType = mlir::cast(val.getType()); + auto boxType = val.getType().cast(); auto elementType = fir::unwrapSeqOrBoxedSeqType(boxType); - if (!mlir::isa(elementType)) + if (!elementType.isa()) return elementType; } while (true); } @@ -381,7 +381,7 @@ static void genRuntimeSumBody(fir::FirOpBuilder &builder, // end function RTNAME(Sum)x_simplified auto zero = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = mlir::dyn_cast(elementType)) { + if (auto ty = elementType.dyn_cast()) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant(loc, elementType, llvm::APFloat::getZero(sem)); @@ -392,9 +392,9 @@ static void genRuntimeSumBody(fir::FirOpBuilder &builder, auto genBodyOp = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType, mlir::Value elem1, mlir::Value elem2) -> mlir::Value { - if (mlir::isa(elementType)) + if (elementType.isa()) return builder.create(loc, elem1, elem2); - if (mlir::isa(elementType)) + if (elementType.isa()) return builder.create(loc, elem1, elem2); llvm_unreachable("unsupported type"); @@ -414,7 +414,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, mlir::Type elementType) { auto init = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = mlir::dyn_cast(elementType)) { + if (auto ty = elementType.dyn_cast()) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, elementType, llvm::APFloat::getLargest(sem, /*Negative=*/true)); @@ -427,7 +427,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, auto genBodyOp = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType, mlir::Value elem1, mlir::Value elem2) -> mlir::Value { - if (mlir::isa(elementType)) { + if (elementType.isa()) { // arith.maxf later converted to llvm.intr.maxnum does not work // correctly for NaNs and -0.0 (see maxnum/minnum pattern matching // in LLVM's InstCombine pass). Moreover, llvm.intr.maxnum @@ -439,7 +439,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, loc, mlir::arith::CmpFPredicate::OGT, elem1, elem2); return builder.create(loc, compare, elem1, elem2); } - if (mlir::isa(elementType)) + if (elementType.isa()) return builder.create(loc, elem1, elem2); llvm_unreachable("unsupported type"); @@ -662,7 +662,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, mlir::Type resultElemTy, bool isDim) { auto init = [isMax](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = mlir::dyn_cast(elementType)) { + if (auto ty = elementType.dyn_cast()) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); llvm::APFloat limit = llvm::APFloat::getInf(sem, /*Negative=*/isMax); return builder.createRealConstant(loc, elementType, limit); @@ -744,7 +744,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, mlir::Value elem = builder.create(loc, addr); mlir::Value cmp; - if (mlir::isa(elementType)) { + if (elementType.isa()) { // For FP reductions we want the first smallest value to be used, that // is not NaN. A OGL/OLT condition will usually work for this unless all // the values are Nan or Inf. This follows the same logic as @@ -761,7 +761,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, loc, mlir::arith::CmpFPredicate::OEQ, elem, elem); cmpNan = builder.create(loc, cmpNan, cmpNan2); cmp = builder.create(loc, cmp, cmpNan); - } else if (mlir::isa(elementType)) { + } else if (elementType.isa()) { cmp = builder.create( loc, isMax ? mlir::arith::CmpIPredicate::sgt @@ -839,7 +839,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, builder.setInsertionPointToStart(&ifOp.getElseRegion().front()); mlir::Value basicValue; - if (mlir::isa(elementType)) { + if (elementType.isa()) { basicValue = builder.createIntegerConstant(loc, elementType, 0); } else { basicValue = builder.createRealConstant(loc, elementType, 0); @@ -921,7 +921,7 @@ static void genRuntimeDotBody(fir::FirOpBuilder &builder, mlir::IndexType idxTy = builder.getIndexType(); mlir::Value zero = - mlir::isa(resultElementType) + resultElementType.isa() ? builder.createRealConstant(loc, resultElementType, 0.0) : builder.createIntegerConstant(loc, resultElementType, 0); @@ -978,10 +978,10 @@ static void genRuntimeDotBody(fir::FirOpBuilder &builder, // Convert to the result type. elem2 = builder.create(loc, resultElementType, elem2); - if (mlir::isa(resultElementType)) + if (resultElementType.isa()) sumVal = builder.create( loc, builder.create(loc, elem1, elem2), sumVal); - else if (mlir::isa(resultElementType)) + else if (resultElementType.isa()) sumVal = builder.create( loc, builder.create(loc, elem1, elem2), sumVal); else @@ -1056,8 +1056,8 @@ void SimplifyIntrinsicsPass::simplifyIntOrFloatReduction( mlir::Type resultType = call.getResult(0).getType(); - if (!mlir::isa(resultType) && - !mlir::isa(resultType)) + if (!resultType.isa() && + !resultType.isa()) return; auto argType = getArgElementType(args[0]); @@ -1103,8 +1103,7 @@ void SimplifyIntrinsicsPass::simplifyLogicalDim0Reduction( fir::FirOpBuilder builder{getSimplificationBuilder(call, kindMap)}; // Treating logicals as integers makes things a lot easier - fir::LogicalType logicalType = { - mlir::dyn_cast(elementType)}; + fir::LogicalType logicalType = {elementType.dyn_cast()}; fir::KindTy kind = logicalType.getFKind(); mlir::Type intElementType = builder.getIntegerType(kind * 8); @@ -1139,8 +1138,7 @@ void SimplifyIntrinsicsPass::simplifyLogicalDim1Reduction( fir::FirOpBuilder builder{getSimplificationBuilder(call, kindMap)}; // Treating logicals as integers makes things a lot easier - fir::LogicalType logicalType = { - mlir::dyn_cast(elementType)}; + fir::LogicalType logicalType = {elementType.dyn_cast()}; fir::KindTy kind = logicalType.getFKind(); mlir::Type intElementType = builder.getIntegerType(kind * 8); @@ -1184,7 +1182,7 @@ void SimplifyIntrinsicsPass::simplifyMinMaxlocReduction( auto inputBox = findBoxDef(args[1]); mlir::Type inputType = hlfir::getFortranElementType(inputBox.getType()); - if (mlir::isa(inputType)) + if (inputType.isa()) return; int maskRank; @@ -1195,8 +1193,7 @@ void SimplifyIntrinsicsPass::simplifyMinMaxlocReduction( } else { maskRank = getDimCount(mask); mlir::Type maskElemTy = hlfir::getFortranElementType(maskDef.getType()); - fir::LogicalType logicalFirType = { - mlir::dyn_cast(maskElemTy)}; + fir::LogicalType logicalFirType = {maskElemTy.dyn_cast()}; kind = logicalFirType.getFKind(); // Convert fir::LogicalType to mlir::Type logicalElemType = logicalFirType; @@ -1305,8 +1302,7 @@ void SimplifyIntrinsicsPass::runOnOperation() { std::string fmfString{builder.getFastMathFlagsString()}; mlir::Type type = call.getResult(0).getType(); - if (!mlir::isa(type) && - !mlir::isa(type)) + if (!type.isa() && !type.isa()) return; // Try to find the element types of the boxed arguments. diff --git a/flang/lib/Optimizer/Transforms/StackArrays.cpp b/flang/lib/Optimizer/Transforms/StackArrays.cpp index 16bbb1c35646..c81524dd16a7 100644 --- a/flang/lib/Optimizer/Transforms/StackArrays.cpp +++ b/flang/lib/Optimizer/Transforms/StackArrays.cpp @@ -351,7 +351,7 @@ void AllocationAnalysis::visitOperation(mlir::Operation *op, } auto retTy = allocmem.getAllocatedType(); - if (!mlir::isa(retTy)) { + if (!retTy.isa()) { LLVM_DEBUG(llvm::dbgs() << "--Allocation is not for an array: skipping\n"); return; diff --git a/flang/unittests/Optimizer/Builder/ComplexTest.cpp b/flang/unittests/Optimizer/Builder/ComplexTest.cpp index 17171512470a..5364eec904ff 100644 --- a/flang/unittests/Optimizer/Builder/ComplexTest.cpp +++ b/flang/unittests/Optimizer/Builder/ComplexTest.cpp @@ -96,6 +96,6 @@ TEST_F(ComplexTest, verifyConvertWithSemantics) { // Convert complex to integer mlir::Value v2 = firBuilder->convertWithSemantics(loc, integerTy1, v1); - EXPECT_TRUE(mlir::isa(v2.getType())); + EXPECT_TRUE(v2.getType().isa()); EXPECT_TRUE(mlir::dyn_cast(v2.getDefiningOp())); } diff --git a/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp b/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp index d0a9342914a3..7e7206dbf934 100644 --- a/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp +++ b/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp @@ -34,7 +34,7 @@ public: void checkConstantValue(const mlir::Value &value, int64_t v) { EXPECT_TRUE(mlir::isa(value.getDefiningOp())); auto cstOp = dyn_cast(value.getDefiningOp()); - auto valueAttr = dyn_cast_or_null(cstOp.getValue()); + auto valueAttr = cstOp.getValue().dyn_cast_or_null(); EXPECT_EQ(v, valueAttr.getInt()); } diff --git a/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp b/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp index e5e5454ee88a..b6a1f9c9db8f 100644 --- a/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp +++ b/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp @@ -54,7 +54,7 @@ static void checkIntegerConstant(mlir::Value value, mlir::Type ty, int64_t v) { EXPECT_TRUE(mlir::isa(value.getDefiningOp())); auto cstOp = dyn_cast(value.getDefiningOp()); EXPECT_EQ(ty, cstOp.getType()); - auto valueAttr = mlir::dyn_cast_or_null(cstOp.getValue()); + auto valueAttr = cstOp.getValue().dyn_cast_or_null(); EXPECT_EQ(v, valueAttr.getInt()); } @@ -151,7 +151,7 @@ TEST_F(FIRBuilderTest, createRealZeroConstant) { auto cstOp = dyn_cast(cst.getDefiningOp()); EXPECT_EQ(realTy, cstOp.getType()); EXPECT_EQ( - 0u, mlir::cast(cstOp.getValue()).getValue().convertToDouble()); + 0u, cstOp.getValue().cast().getValue().convertToDouble()); } TEST_F(FIRBuilderTest, createBool) { @@ -164,8 +164,8 @@ TEST_F(FIRBuilderTest, createBool) { TEST_F(FIRBuilderTest, getVarLenSeqTy) { auto builder = getBuilder(); auto ty = builder.getVarLenSeqTy(builder.getI64Type()); - EXPECT_TRUE(mlir::isa(ty)); - fir::SequenceType seqTy = mlir::dyn_cast(ty); + EXPECT_TRUE(ty.isa()); + fir::SequenceType seqTy = ty.dyn_cast(); EXPECT_EQ(1u, seqTy.getDimension()); EXPECT_TRUE(fir::unwrapSequenceType(ty).isInteger(64)); } @@ -216,9 +216,9 @@ TEST_F(FIRBuilderTest, createGlobal2) { EXPECT_FALSE(global.getConstant().has_value()); EXPECT_EQ(i32Type, global.getType()); EXPECT_TRUE(global.getInitVal().has_value()); - EXPECT_TRUE(mlir::isa(global.getInitVal().value())); - EXPECT_EQ(16, - mlir::cast(global.getInitVal().value()).getValue()); + EXPECT_TRUE(global.getInitVal().value().isa()); + EXPECT_EQ( + 16, global.getInitVal().value().cast().getValue()); EXPECT_TRUE(global.getLinkName().has_value()); EXPECT_EQ( builder.createLinkOnceLinkage().getValue(), global.getLinkName().value()); @@ -271,12 +271,12 @@ TEST_F(FIRBuilderTest, locationToFilename) { auto stringLitOps = global.getRegion().front().getOps(); EXPECT_TRUE(llvm::hasSingleElement(stringLitOps)); for (auto stringLit : stringLitOps) { - EXPECT_EQ( - 10, mlir::cast(stringLit.getSize()).getValue()); - EXPECT_TRUE(mlir::isa(stringLit.getValue())); + EXPECT_EQ(10, stringLit.getSize().cast().getValue()); + EXPECT_TRUE(stringLit.getValue().isa()); EXPECT_EQ(0, strcmp("file1.f90\0", - mlir::dyn_cast(stringLit.getValue()) + stringLit.getValue() + .dyn_cast() .getValue() .str() .c_str())); @@ -288,9 +288,9 @@ TEST_F(FIRBuilderTest, createStringLitOp) { llvm::StringRef data("mystringlitdata"); auto loc = builder.getUnknownLoc(); auto op = builder.createStringLitOp(loc, data); - EXPECT_EQ(15, mlir::cast(op.getSize()).getValue()); - EXPECT_TRUE(mlir::isa(op.getValue())); - EXPECT_EQ(data, mlir::dyn_cast(op.getValue()).getValue()); + EXPECT_EQ(15, op.getSize().cast().getValue()); + EXPECT_TRUE(op.getValue().isa()); + EXPECT_EQ(data, op.getValue().dyn_cast().getValue()); } TEST_F(FIRBuilderTest, createStringLiteral) { @@ -318,11 +318,9 @@ TEST_F(FIRBuilderTest, createStringLiteral) { auto stringLitOps = global.getRegion().front().getOps(); EXPECT_TRUE(llvm::hasSingleElement(stringLitOps)); for (auto stringLit : stringLitOps) { - EXPECT_EQ( - 16, mlir::cast(stringLit.getSize()).getValue()); - EXPECT_TRUE(mlir::isa(stringLit.getValue())); - EXPECT_EQ( - strValue, mlir::dyn_cast(stringLit.getValue()).getValue()); + EXPECT_EQ(16, stringLit.getSize().cast().getValue()); + EXPECT_TRUE(stringLit.getValue().isa()); + EXPECT_EQ(strValue, stringLit.getValue().dyn_cast().getValue()); } } @@ -346,7 +344,7 @@ TEST_F(FIRBuilderTest, allocateLocal) { static void checkShapeOp(mlir::Value shape, mlir::Value c10, mlir::Value c100) { EXPECT_TRUE(mlir::isa(shape.getDefiningOp())); fir::ShapeOp op = dyn_cast(shape.getDefiningOp()); - auto shapeTy = mlir::dyn_cast(op.getType()); + auto shapeTy = op.getType().dyn_cast(); EXPECT_EQ(2u, shapeTy.getRank()); EXPECT_EQ(2u, op.getExtents().size()); EXPECT_EQ(c10, op.getExtents()[0]); @@ -374,7 +372,7 @@ TEST_F(FIRBuilderTest, genShapeWithExtentsAndShapeShift) { auto shape = builder.genShape(loc, shifts, extents); EXPECT_TRUE(mlir::isa(shape.getDefiningOp())); fir::ShapeShiftOp op = dyn_cast(shape.getDefiningOp()); - auto shapeTy = mlir::dyn_cast(op.getType()); + auto shapeTy = op.getType().dyn_cast(); EXPECT_EQ(2u, shapeTy.getRank()); EXPECT_EQ(2u, op.getExtents().size()); EXPECT_EQ(2u, op.getOrigins().size()); @@ -430,7 +428,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst = mlir::dyn_cast_or_null(zeroInt.getDefiningOp()); EXPECT_TRUE(cst); - auto intAttr = mlir::dyn_cast(cst.getValue()); + auto intAttr = cst.getValue().dyn_cast(); EXPECT_TRUE(intAttr && intAttr.getInt() == 0); mlir::Type f32Ty = mlir::FloatType::getF32(builder.getContext()); @@ -439,7 +437,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst2 = mlir::dyn_cast_or_null( zeroFloat.getDefiningOp()); EXPECT_TRUE(cst2); - auto floatAttr = mlir::dyn_cast(cst2.getValue()); + auto floatAttr = cst2.getValue().dyn_cast(); EXPECT_TRUE(floatAttr && floatAttr.getValueAsDouble() == 0.); mlir::Type boolTy = mlir::IntegerType::get(builder.getContext(), 1); @@ -448,7 +446,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst3 = mlir::dyn_cast_or_null( flaseBool.getDefiningOp()); EXPECT_TRUE(cst3); - auto intAttr2 = mlir::dyn_cast(cst.getValue()); + auto intAttr2 = cst.getValue().dyn_cast(); EXPECT_TRUE(intAttr2 && intAttr2.getInt() == 0); } @@ -484,7 +482,7 @@ TEST_F(FIRBuilderTest, getBaseTypeOf) { llvm::SmallVector arrays; auto extent = builder.create(loc, builder.getIndexType()); llvm::SmallVector extents( - mlir::dyn_cast(arrayType).getDimension(), + arrayType.dyn_cast().getDimension(), extent.getResult()); arrays.emplace_back(fir::ArrayBoxValue(ptrValArray, extents)); arrays.emplace_back(fir::BoxValue(boxValArray)); diff --git a/flang/unittests/Optimizer/RTBuilder.cpp b/flang/unittests/Optimizer/RTBuilder.cpp index d6cf96c4351c..7fff7f71fc3b 100644 --- a/flang/unittests/Optimizer/RTBuilder.cpp +++ b/flang/unittests/Optimizer/RTBuilder.cpp @@ -27,7 +27,7 @@ TEST(RTBuilderTest, ComplexRuntimeInterface) { mlir::Type c99_cacosf_signature{ fir::runtime::RuntimeTableKey::getTypeModel()( &ctx)}; - auto c99_cacosf_funcTy = mlir::cast(c99_cacosf_signature); + auto c99_cacosf_funcTy = c99_cacosf_signature.cast(); EXPECT_EQ(c99_cacosf_funcTy.getNumInputs(), 1u); EXPECT_EQ(c99_cacosf_funcTy.getNumResults(), 1u); auto cplx_ty = fir::ComplexType::get(&ctx, 4); diff --git a/llvm/include/llvm/ADT/TypeSwitch.h b/llvm/include/llvm/ADT/TypeSwitch.h index 14ad56ad575f..10a2d48e918d 100644 --- a/llvm/include/llvm/ADT/TypeSwitch.h +++ b/llvm/include/llvm/ADT/TypeSwitch.h @@ -74,10 +74,7 @@ protected: ValueT &&value, std::enable_if_t::value> * = nullptr) { - // Silence warnings about MLIR's deprecated dyn_cast member functions. - LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_PUSH return value.template dyn_cast(); - LLVM_SUPPRESS_DEPRECATED_DECLARATIONS_POP } /// Attempt to dyn_cast the given `value` to `CastT`. This overload is diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td index 64c538367267..da12e7c83b22 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td @@ -138,10 +138,10 @@ def Linalg_SoftmaxOp : Linalg_Op<"softmax", let extraClassDeclaration = [{ ShapedType getInputOperandType() { - return cast(getInput().getType()); + return getInput().getType().cast(); } ShapedType getOutputOperandType() { - return cast(getOutput().getType()); + return getOutput().getType().cast(); } int64_t getInputOperandRank() { return getInputOperandType().getRank(); diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td index d9569d9d294d..ab9b78e755d9 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td @@ -234,8 +234,8 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getIsTargetDevice", (ins), [{}], [{ if (Attribute isTargetDevice = $_op->getAttr("omp.is_target_device")) - if (::llvm::isa(isTargetDevice)) - return ::llvm::dyn_cast(isTargetDevice).getValue(); + if (isTargetDevice.isa()) + return isTargetDevice.dyn_cast().getValue(); return false; }]>, InterfaceMethod< @@ -259,7 +259,7 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getIsGPU", (ins), [{}], [{ if (Attribute isTargetCGAttr = $_op->getAttr("omp.is_gpu")) - if (auto isTargetCGVal = ::llvm::dyn_cast(isTargetCGAttr)) + if (auto isTargetCGVal = isTargetCGAttr.dyn_cast()) return isTargetCGVal.getValue(); return false; }]>, @@ -332,7 +332,7 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getRequires", (ins), [{}], [{ if (Attribute requiresAttr = $_op->getAttr("omp.requires")) - if (auto requiresVal = ::llvm::dyn_cast(requiresAttr)) + if (auto requiresVal = requiresAttr.dyn_cast()) return requiresVal.getValue(); return mlir::omp::ClauseRequires::none; }]>, diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td index e477d9a0ca3f..88f2e1acfeeb 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td @@ -164,10 +164,10 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// source operand. They overide static shape from source memref type. ArrayRef getStaticSizes() { auto attr = getConstShapeAttr(); - if (llvm::isa(getSourceType()) || attr) + if (getSourceType().isa() || attr) return attr; - auto memrefType = llvm::dyn_cast(getSourceType()); + auto memrefType = getSourceType().dyn_cast(); assert(memrefType && "Incorrect use of getStaticSizes"); return memrefType.getShape(); } @@ -179,10 +179,10 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// source operand. They overide static strides from source memref type. ArrayRef getStaticStrides() { auto attr = getConstStridesAttr(); - if (llvm::isa(getSourceType()) || attr) + if (getSourceType().isa() || attr) return attr; - auto memrefType = llvm::dyn_cast(getSourceType()); + auto memrefType = getSourceType().dyn_cast(); assert(memrefType && "Incorrect use of getStaticStrides"); auto [strides, offset] = getStridesAndOffset(memrefType); // reuse the storage of ConstStridesAttr since strides from @@ -196,7 +196,7 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// `static_shape` and `static_strides` attributes. std::array getArrayAttrMaxRanks() { unsigned rank; - if (auto ty = llvm::dyn_cast(getSourceType())) { + if (auto ty = getSourceType().dyn_cast()) { rank = ty.getRank(); } else { rank = (unsigned)getMixedOffsets().size(); diff --git a/mlir/include/mlir/IR/Attributes.h b/mlir/include/mlir/IR/Attributes.h index 8a077865b51b..cc0cee6a3118 100644 --- a/mlir/include/mlir/IR/Attributes.h +++ b/mlir/include/mlir/IR/Attributes.h @@ -50,19 +50,14 @@ public: /// Casting utility functions. These are deprecated and will be removed, /// please prefer using the `llvm` namespace variants instead. template - [[deprecated("Use mlir::isa() instead")]] bool isa() const; template - [[deprecated("Use mlir::isa_and_nonnull() instead")]] bool isa_and_nonnull() const; template - [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const; template - [[deprecated("Use mlir::dyn_cast_or_null() instead")]] U dyn_cast_or_null() const; template - [[deprecated("Use mlir::cast() instead")]] U cast() const; /// Return a unique identifier for the concrete attribute type. This is used diff --git a/mlir/include/mlir/IR/BuiltinLocationAttributes.td b/mlir/include/mlir/IR/BuiltinLocationAttributes.td index 5a72404dea15..dfcc180071f7 100644 --- a/mlir/include/mlir/IR/BuiltinLocationAttributes.td +++ b/mlir/include/mlir/IR/BuiltinLocationAttributes.td @@ -228,8 +228,7 @@ def OpaqueLoc : Builtin_LocationAttr<"OpaqueLoc"> { template static T getUnderlyingLocation(Location location) { assert(isa(location)); return reinterpret_cast( - mlir::cast(static_cast(location)) - .getUnderlyingLocation()); + location.cast().getUnderlyingLocation()); } /// Returns a pointer to some data structure that opaque location stores. @@ -238,17 +237,15 @@ def OpaqueLoc : Builtin_LocationAttr<"OpaqueLoc"> { template static T getUnderlyingLocationOrNull(Location location) { return isa(location) - ? reinterpret_cast(mlir::cast( - static_cast(location)) - .getUnderlyingLocation()) - : T(nullptr); + ? reinterpret_cast( + location.cast().getUnderlyingLocation()) + : T(nullptr); } /// Checks whether provided location is opaque location and contains a /// pointer to an object of particular type. template static bool isa(Location location) { - auto opaque_loc = - mlir::dyn_cast(static_cast(location)); + auto opaque_loc = location.dyn_cast(); return opaque_loc && opaque_loc.getUnderlyingTypeID() == TypeID::get(); } }]; diff --git a/mlir/include/mlir/IR/Location.h b/mlir/include/mlir/IR/Location.h index 423b4d19b5b9..aa8314f38cdf 100644 --- a/mlir/include/mlir/IR/Location.h +++ b/mlir/include/mlir/IR/Location.h @@ -78,17 +78,14 @@ public: /// Type casting utilities on the underlying location. template - [[deprecated("Use mlir::isa() instead")]] bool isa() const { return llvm::isa(*this); } template - [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const { return llvm::dyn_cast(*this); } template - [[deprecated("Use mlir::cast() instead")]] U cast() const { return llvm::cast(*this); } diff --git a/mlir/include/mlir/IR/Types.h b/mlir/include/mlir/IR/Types.h index 65824531fdc9..a89e13b625bf 100644 --- a/mlir/include/mlir/IR/Types.h +++ b/mlir/include/mlir/IR/Types.h @@ -97,19 +97,14 @@ public: bool operator!() const { return impl == nullptr; } template - [[deprecated("Use mlir::isa() instead")]] bool isa() const; template - [[deprecated("Use mlir::isa_and_nonnull() instead")]] bool isa_and_nonnull() const; template - [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const; template - [[deprecated("Use mlir::dyn_cast_or_null() instead")]] U dyn_cast_or_null() const; template - [[deprecated("Use mlir::cast() instead")]] U cast() const; /// Return a unique identifier for the concrete type. This is used to support diff --git a/mlir/include/mlir/IR/Value.h b/mlir/include/mlir/IR/Value.h index a7344c64e673..cdbc6cc37436 100644 --- a/mlir/include/mlir/IR/Value.h +++ b/mlir/include/mlir/IR/Value.h @@ -98,25 +98,25 @@ public: constexpr Value(detail::ValueImpl *impl = nullptr) : impl(impl) {} template - [[deprecated("Use mlir::isa() instead")]] + [[deprecated("Use isa() instead")]] bool isa() const { return llvm::isa(*this); } template - [[deprecated("Use mlir::dyn_cast() instead")]] + [[deprecated("Use dyn_cast() instead")]] U dyn_cast() const { return llvm::dyn_cast(*this); } template - [[deprecated("Use mlir::dyn_cast_or_null() instead")]] + [[deprecated("Use dyn_cast_or_null() instead")]] U dyn_cast_or_null() const { return llvm::dyn_cast_or_null(*this); } template - [[deprecated("Use mlir::cast() instead")]] + [[deprecated("Use cast() instead")]] U cast() const { return llvm::cast(*this); } diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index c2a83f90bcbe..4a15976d40c7 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -857,7 +857,7 @@ struct SqrtOpConversion : public OpConversionPattern { ImplicitLocOpBuilder b(op.getLoc(), rewriter); auto type = cast(op.getType()); - auto elementType = cast(type.getElementType()); + auto elementType = type.getElementType().cast(); arith::FastMathFlags fmf = op.getFastMathFlagsAttr().getValue(); auto cst = [&](APFloat v) { diff --git a/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp b/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp index f1ec2be72a33..ee09c73bb3c4 100644 --- a/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp +++ b/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp @@ -172,7 +172,7 @@ Attribute RingAttr::parse(AsmParser &parser, Type type) { if (failed(parser.parseEqual())) return {}; - IntegerType iType = mlir::dyn_cast(ty); + IntegerType iType = ty.dyn_cast(); if (!iType) { parser.emitError(parser.getCurrentLocation(), "coefficientType must specify an integer type"); diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp index 802a64b0805e..69999f0918c1 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp @@ -140,7 +140,7 @@ struct LinearizeVectorExtractStridedSlice final ConversionPatternRewriter &rewriter) const override { Type dstType = getTypeConverter()->convertType(extractOp.getType()); assert(!(extractOp.getVector().getType().isScalable() || - cast(dstType).isScalable()) && + dstType.cast().isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(extractOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -172,7 +172,7 @@ struct LinearizeVectorExtractStridedSlice final // Get total number of extracted slices. int64_t nExtractedSlices = 1; for (Attribute size : sizes) { - nExtractedSlices *= cast(size).getInt(); + nExtractedSlices *= size.cast().getInt(); } // Compute the strides of the source vector considering first k dimensions. llvm::SmallVector sourceStrides(kD, extractGranularitySize); @@ -189,7 +189,7 @@ struct LinearizeVectorExtractStridedSlice final // Compute extractedStrides. for (int i = kD - 2; i >= 0; --i) { extractedStrides[i] = - extractedStrides[i + 1] * cast(sizes[i + 1]).getInt(); + extractedStrides[i + 1] * sizes[i + 1].cast().getInt(); } // Iterate over all extracted slices from 0 to nExtractedSlices - 1 // and compute the multi-dimensional index and the corresponding linearized @@ -207,7 +207,7 @@ struct LinearizeVectorExtractStridedSlice final int64_t linearizedIndex = 0; for (int64_t j = 0; j < kD; ++j) { linearizedIndex += - (cast(offsets[j]).getInt() + multiDimIndex[j]) * + (offsets[j].cast().getInt() + multiDimIndex[j]) * sourceStrides[j]; } // Fill the indices array form linearizedIndex to linearizedIndex + @@ -254,7 +254,7 @@ struct LinearizeVectorShuffle final Type dstType = getTypeConverter()->convertType(shuffleOp.getType()); assert(!(shuffleOp.getV1VectorType().isScalable() || shuffleOp.getV2VectorType().isScalable() || - cast(dstType).isScalable()) && + dstType.cast().isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(shuffleOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -324,7 +324,7 @@ struct LinearizeVectorExtract final ConversionPatternRewriter &rewriter) const override { Type dstTy = getTypeConverter()->convertType(extractOp.getType()); assert(!(extractOp.getVector().getType().isScalable() || - cast(dstTy).isScalable()) && + dstTy.cast().isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(extractOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -405,7 +405,9 @@ void mlir::vector::populateVectorLinearizeShuffleLikeOpsPatterns( [=](vector::ShuffleOp shuffleOp) -> bool { return isLessThanTargetBitWidth(shuffleOp, targetBitWidth) ? (typeConverter.isLegal(shuffleOp) && - cast(shuffleOp.getResult().getType()) + shuffleOp.getResult() + .getType() + .cast() .getRank() == 1) : true; }); -- GitLab From 5dd46d93fb9d7e7f8c9774433d60fd16dc659eb6 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 26 Apr 2024 12:04:47 -0700 Subject: [PATCH 093/301] [RISCV] Fix off by 1 typo in decodeVMaskReg. NFC We're decoding a 1 bit field, but checked that the value was <= 2 instead of <= 1. This isn't a functional change because the generated disassembler code that calls this only extracts 1 bit. --- llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 3cd6e7434183..497283ceea1e 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -258,9 +258,9 @@ static DecodeStatus DecodeVRM8RegisterClass(MCInst &Inst, uint32_t RegNo, static DecodeStatus decodeVMaskReg(MCInst &Inst, uint32_t RegNo, uint64_t Address, const MCDisassembler *Decoder) { - if (RegNo > 2) { + if (RegNo >= 2) return MCDisassembler::Fail; - } + MCRegister Reg = (RegNo == 0) ? RISCV::V0 : RISCV::NoRegister; Inst.addOperand(MCOperand::createReg(Reg)); -- GitLab From 300340f656d762afa8bde5fc398757d2951560bf Mon Sep 17 00:00:00 2001 From: Adrian Prantl Date: Fri, 26 Apr 2024 12:25:39 -0700 Subject: [PATCH 094/301] Implement the DWARF 6 language and version attributes. (#89980) This patch adds DWARF constants for DW_AT_language_name and DW_AT_language_version to Dwarf.def and Dwarf.h. While the DWARF 6 spec is not finalized, the constants are published on the DWARF website and considered stable, with idea being that the list published on dwarfstd.org is the authoritative source that is being continuously updated between DWARF revisions, as new languages are being developed. https://dwarfstd.org/languages-v6.html My main motivation for adding this is to use in https://github.com/llvm/llvm-project/pull/89981 --- llvm/include/llvm-c/DebugInfo.h | 13 + llvm/include/llvm/BinaryFormat/Dwarf.def | 101 ++++++- llvm/include/llvm/BinaryFormat/Dwarf.h | 314 ++++++++++++++++++++++ llvm/lib/BinaryFormat/Dwarf.cpp | 10 + llvm/unittests/BinaryFormat/DwarfTest.cpp | 15 ++ 5 files changed, 440 insertions(+), 13 deletions(-) diff --git a/llvm/include/llvm-c/DebugInfo.h b/llvm/include/llvm-c/DebugInfo.h index dab1d697761b..2c3c75e246c0 100644 --- a/llvm/include/llvm-c/DebugInfo.h +++ b/llvm/include/llvm-c/DebugInfo.h @@ -125,7 +125,20 @@ typedef enum { LLVMDWARFSourceLanguageFortran18, LLVMDWARFSourceLanguageAda2005, LLVMDWARFSourceLanguageAda2012, + LLVMDWARFSourceLanguageHIP, + LLVMDWARFSourceLanguageAssembly, + LLVMDWARFSourceLanguageC_sharp, LLVMDWARFSourceLanguageMojo, + LLVMDWARFSourceLanguageGLSL, + LLVMDWARFSourceLanguageGLSL_ES, + LLVMDWARFSourceLanguageHLSL, + LLVMDWARFSourceLanguageOpenCL_CPP, + LLVMDWARFSourceLanguageCPP_for_OpenCL, + LLVMDWARFSourceLanguageSYCL, + LLVMDWARFSourceLanguageRuby, + LLVMDWARFSourceLanguageMove, + LLVMDWARFSourceLanguageHylo, + // Vendor extensions: LLVMDWARFSourceLanguageMips_Assembler, LLVMDWARFSourceLanguageGOOGLE_RenderScript, diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.def b/llvm/include/llvm/BinaryFormat/Dwarf.def index 460a9264536b..adcf24eb83b0 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.def +++ b/llvm/include/llvm/BinaryFormat/Dwarf.def @@ -11,19 +11,20 @@ //===----------------------------------------------------------------------===// // TODO: Add other DW-based macros. -#if !( \ - defined HANDLE_DW_TAG || defined HANDLE_DW_AT || defined HANDLE_DW_FORM || \ - defined HANDLE_DW_OP || defined HANDLE_DW_OP_LLVM_USEROP || \ - defined HANDLE_DW_LANG || defined HANDLE_DW_ATE || \ - defined HANDLE_DW_VIRTUALITY || defined HANDLE_DW_DEFAULTED || \ - defined HANDLE_DW_CC || defined HANDLE_DW_LNS || defined HANDLE_DW_LNE || \ - defined HANDLE_DW_LNCT || defined HANDLE_DW_MACRO || \ - defined HANDLE_DW_MACRO_GNU || defined HANDLE_MACRO_FLAG || \ - defined HANDLE_DW_RLE || defined HANDLE_DW_LLE || \ - (defined HANDLE_DW_CFA && defined HANDLE_DW_CFA_PRED) || \ - defined HANDLE_DW_APPLE_PROPERTY || defined HANDLE_DW_UT || \ - defined HANDLE_DWARF_SECTION || defined HANDLE_DW_IDX || \ - defined HANDLE_DW_END || defined HANDLE_DW_SECT) +#if !(defined HANDLE_DW_TAG || defined HANDLE_DW_AT || \ + defined HANDLE_DW_FORM || defined HANDLE_DW_OP || \ + defined HANDLE_DW_OP_LLVM_USEROP || defined HANDLE_DW_LANG || \ + defined HANDLE_DW_LNAME || defined HANDLE_DW_ATE || \ + defined HANDLE_DW_VIRTUALITY || defined HANDLE_DW_DEFAULTED || \ + defined HANDLE_DW_CC || defined HANDLE_DW_LNS || \ + defined HANDLE_DW_LNE || defined HANDLE_DW_LNCT || \ + defined HANDLE_DW_MACRO || defined HANDLE_DW_MACRO_GNU || \ + defined HANDLE_MACRO_FLAG || defined HANDLE_DW_RLE || \ + defined HANDLE_DW_LLE || \ + (defined HANDLE_DW_CFA && defined HANDLE_DW_CFA_PRED) || \ + defined HANDLE_DW_APPLE_PROPERTY || defined HANDLE_DW_UT || \ + defined HANDLE_DWARF_SECTION || defined HANDLE_DW_IDX || \ + defined HANDLE_DW_END || defined HANDLE_DW_SECT) #error "Missing macro definition of HANDLE_DW*" #endif @@ -61,6 +62,10 @@ #define HANDLE_DW_LANG(ID, NAME, LOWER_BOUND, VERSION, VENDOR) #endif +#ifndef HANDLE_DW_LNAME +#define HANDLE_DW_LNAME(ID, NAME, DESC, LOWER_BOUND) +#endif + #ifndef HANDLE_DW_ATE #define HANDLE_DW_ATE(ID, NAME, VERSION, VENDOR) #endif @@ -950,12 +955,81 @@ HANDLE_DW_LANG(0x002c, C17, 0, 0, DWARF) HANDLE_DW_LANG(0x002d, Fortran18, 0, 0, DWARF) HANDLE_DW_LANG(0x002e, Ada2005, 0, 0, DWARF) HANDLE_DW_LANG(0x002f, Ada2012, 0, 0, DWARF) +HANDLE_DW_LANG(0x0030, HIP, 0, 0, DWARF) +HANDLE_DW_LANG(0x0031, Assembly, 0, 0, DWARF) +HANDLE_DW_LANG(0x0032, C_sharp, 0, 0, DWARF) HANDLE_DW_LANG(0x0033, Mojo, 0, 0, DWARF) +HANDLE_DW_LANG(0x0034, GLSL, 0, 0, DWARF) +HANDLE_DW_LANG(0x0035, GLSL_ES, 0, 0, DWARF) +HANDLE_DW_LANG(0x0036, HLSL, 0, 0, DWARF) +HANDLE_DW_LANG(0x0037, OpenCL_CPP, 0, 0, DWARF) +HANDLE_DW_LANG(0x0038, CPP_for_OpenCL, 0, 0, DWARF) +HANDLE_DW_LANG(0x0039, SYCL, 0, 0, DWARF) +HANDLE_DW_LANG(0x0040, Ruby, 0, 0, DWARF) +HANDLE_DW_LANG(0x0041, Move, 0, 0, DWARF) +HANDLE_DW_LANG(0x0042, Hylo, 0, 0, DWARF) + // Vendor extensions: HANDLE_DW_LANG(0x8001, Mips_Assembler, std::nullopt, 0, MIPS) HANDLE_DW_LANG(0x8e57, GOOGLE_RenderScript, 0, 0, GOOGLE) HANDLE_DW_LANG(0xb000, BORLAND_Delphi, 0, 0, BORLAND) +// Tentative DWARF 6 language codes. This list is subject to change. +HANDLE_DW_LNAME(0x0001, Ada, "ISO Ada", 1) // YYYY +HANDLE_DW_LNAME(0x0002, BLISS, "BLISS", 0) +// YYYYMM +// K&R 000000 +// C89 198912 +// C99 199901 +// C11 201112 +// C17 201710 +// C23 202311 +HANDLE_DW_LNAME(0x0003, C, "C (K&R and ISO)", 0) +// YYYYMM +// C++98 199711 +// C++03 200310 +// C++11 201103 +// C++14 201402 +// C++17 201703 +// C++20 202002 +HANDLE_DW_LNAME(0x0004, C_plus_plus, "ISO C++", 0) +HANDLE_DW_LNAME(0x0005, Cobol, "ISO Cobol", 1) // YYYY +HANDLE_DW_LNAME(0x0006, Crystal, "Crystal", 0) +HANDLE_DW_LNAME(0x0007, D, "D", 0) +HANDLE_DW_LNAME(0x0008, Dylan, "Dylan", 0) +HANDLE_DW_LNAME(0x0009, Fortran, "ISO Fortran", 1) // YYYY +HANDLE_DW_LNAME(0x000a, Go, "Go", 0) +HANDLE_DW_LNAME(0x000b, Haskell, "Haskell", 0) +HANDLE_DW_LNAME(0x000c, Java, "Java", 0) +HANDLE_DW_LNAME(0x000d, Julia, "Julia", 1) +HANDLE_DW_LNAME(0x000e, Kotlin, "Kotlin", 0) +HANDLE_DW_LNAME(0x000f, Modula2, "Modula 2", 1) +HANDLE_DW_LNAME(0x0010, Modula3, "Modula 3", 1) +HANDLE_DW_LNAME(0x0011, ObjC, "Objective C", 0) // YYYYMM +HANDLE_DW_LNAME(0x0012, ObjC_plus_plus, "Objective C++", 0) // YYYYMM +HANDLE_DW_LNAME(0x0013, OCaml, "OCaml", 0) +HANDLE_DW_LNAME(0x0014, OpenCL_C, "OpenCL C", 0) +HANDLE_DW_LNAME(0x0015, Pascal, "ISO Pascal", 1) // YYYY +HANDLE_DW_LNAME(0x0016, PLI, "ANSI PL/I", 1) +HANDLE_DW_LNAME(0x0017, Python, "Python", 0) +HANDLE_DW_LNAME(0x0018, RenderScript, "RenderScript Kernel Language", 0) +HANDLE_DW_LNAME(0x0019, Rust, "Rust", 0) +HANDLE_DW_LNAME(0x001a, Swift, "Swift", 0) // VVMM +HANDLE_DW_LNAME(0x001b, UPC, "Unified Parallel C (UPC)", 0) +HANDLE_DW_LNAME(0x001c, Zig, "Zig", 0) +HANDLE_DW_LNAME(0x001d, Assembly, "Assembly", 0) +// Conflict: HANDLE_DW_LNAME(0x001d, HIP, "HIP", 0) +HANDLE_DW_LNAME(0x001e, C_sharp, "C#", 0) +HANDLE_DW_LNAME(0x001f, Mojo, "Mojo", 0) +HANDLE_DW_LNAME(0x0020, GLSL, "OpenGL Shading Language", 0) // VVMMPP +HANDLE_DW_LNAME(0x0021, GLSL_ES, "OpenGL ES Shading Language", 0) // VVMMPP +HANDLE_DW_LNAME(0x0022, HLSL, "High Level Shading Language", 0) // YYYY +HANDLE_DW_LNAME(0x0023, OpenCL_CPP, "OpenCL C++", 0) // VVMM +HANDLE_DW_LNAME(0x0024, CPP_for_OpenCL, "C++ for OpenCL", 0) // VVMM +HANDLE_DW_LNAME(0x0025, SYCL, "SYCL", 0) // YYYYRR +HANDLE_DW_LNAME(0x0026, Ruby, "Ruby", 0) // VVMMPP +HANDLE_DW_LNAME(0x0027, Move, "Move", 0) // YYYYMM +HANDLE_DW_LNAME(0x0028, Hylo, "Hylo", 0) // DWARF attribute type encodings. HANDLE_DW_ATE(0x01, address, 2, DWARF) @@ -1267,6 +1341,7 @@ HANDLE_DW_SECT(8, RNGLISTS) #undef HANDLE_DW_OP #undef HANDLE_DW_OP_LLVM_USEROP #undef HANDLE_DW_LANG +#undef HANDLE_DW_LNAME #undef HANDLE_DW_ATE #undef HANDLE_DW_VIRTUALITY #undef HANDLE_DW_DEFAULTED diff --git a/llvm/include/llvm/BinaryFormat/Dwarf.h b/llvm/include/llvm/BinaryFormat/Dwarf.h index 298700c8941e..74c4d6ff3a71 100644 --- a/llvm/include/llvm/BinaryFormat/Dwarf.h +++ b/llvm/include/llvm/BinaryFormat/Dwarf.h @@ -209,6 +209,284 @@ enum SourceLanguage { DW_LANG_hi_user = 0xffff }; +enum SourceLanguageName : uint16_t { +#define HANDLE_DW_LNAME(ID, NAME, DESC, LOWER_BOUND) DW_LNAME_##NAME = ID, +#include "llvm/BinaryFormat/Dwarf.def" +}; + +/// Convert a DWARF 6 pair of language name and version to a DWARF 5 DW_LANG. +/// If the version number doesn't exactly match a known version it is +/// rounded up to the next-highest known version number. +inline std::optional toDW_LANG(SourceLanguageName name, + uint32_t version) { + switch (name) { + case DW_LNAME_Ada: // YYYY + if (version <= 1983) + return DW_LANG_Ada83; + if (version <= 1995) + return DW_LANG_Ada95; + if (version <= 2005) + return DW_LANG_Ada2005; + if (version <= 2012) + return DW_LANG_Ada2012; + return {}; + case DW_LNAME_BLISS: + return DW_LANG_BLISS; + case DW_LNAME_C: // YYYYMM, K&R 000000 + if (version == 0) + return DW_LANG_C; + if (version <= 198912) + return DW_LANG_C89; + if (version <= 199901) + return DW_LANG_C99; + if (version <= 201112) + return DW_LANG_C11; + if (version <= 201710) + return DW_LANG_C17; + return {}; + case DW_LNAME_C_plus_plus: // YYYYMM + if (version == 0) + return DW_LANG_C_plus_plus; + if (version <= 199711) + return DW_LANG_C_plus_plus; + if (version <= 200310) + return DW_LANG_C_plus_plus_03; + if (version <= 201103) + return DW_LANG_C_plus_plus_11; + if (version <= 201402) + return DW_LANG_C_plus_plus_14; + if (version <= 201703) + return DW_LANG_C_plus_plus_17; + if (version <= 202002) + return DW_LANG_C_plus_plus_20; + return {}; + case DW_LNAME_Cobol: // YYYY + if (version <= 1974) + return DW_LANG_Cobol74; + if (version <= 1985) + return DW_LANG_Cobol85; + return {}; + case DW_LNAME_Crystal: + return DW_LANG_Crystal; + case DW_LNAME_D: + return DW_LANG_D; + case DW_LNAME_Dylan: + return DW_LANG_Dylan; + case DW_LNAME_Fortran: // YYYY + if (version <= 1977) + return DW_LANG_Fortran77; + if (version <= 1990) + return DW_LANG_Fortran90; + if (version <= 1995) + return DW_LANG_Fortran95; + if (version <= 2003) + return DW_LANG_Fortran03; + if (version <= 2008) + return DW_LANG_Fortran08; + if (version <= 2018) + return DW_LANG_Fortran18; + return {}; + case DW_LNAME_Go: + return DW_LANG_Go; + case DW_LNAME_Haskell: + return DW_LANG_Haskell; + // case DW_LNAME_HIP: + // return DW_LANG_HIP; + case DW_LNAME_Java: + return DW_LANG_Java; + case DW_LNAME_Julia: + return DW_LANG_Julia; + case DW_LNAME_Kotlin: + return DW_LANG_Kotlin; + case DW_LNAME_Modula2: + return DW_LANG_Modula2; + case DW_LNAME_Modula3: + return DW_LANG_Modula3; + case DW_LNAME_ObjC: + return DW_LANG_ObjC; + case DW_LNAME_ObjC_plus_plus: + return DW_LANG_ObjC_plus_plus; + case DW_LNAME_OCaml: + return DW_LANG_OCaml; + case DW_LNAME_OpenCL_C: + return DW_LANG_OpenCL; + case DW_LNAME_Pascal: + return DW_LANG_Pascal83; + case DW_LNAME_PLI: + return DW_LANG_PLI; + case DW_LNAME_Python: + return DW_LANG_Python; + case DW_LNAME_RenderScript: + return DW_LANG_RenderScript; + case DW_LNAME_Rust: + return DW_LANG_Rust; + case DW_LNAME_Swift: + return DW_LANG_Swift; + case DW_LNAME_UPC: + return DW_LANG_UPC; + case DW_LNAME_Zig: + return DW_LANG_Zig; + case DW_LNAME_Assembly: + return DW_LANG_Assembly; + case DW_LNAME_C_sharp: + return DW_LANG_C_sharp; + case DW_LNAME_Mojo: + return DW_LANG_Mojo; + case DW_LNAME_GLSL: + return DW_LANG_GLSL; + case DW_LNAME_GLSL_ES: + return DW_LANG_GLSL_ES; + case DW_LNAME_HLSL: + return DW_LANG_HLSL; + case DW_LNAME_OpenCL_CPP: + return DW_LANG_OpenCL_CPP; + case DW_LNAME_CPP_for_OpenCL: + return {}; + case DW_LNAME_SYCL: + return DW_LANG_SYCL; + case DW_LNAME_Ruby: + return DW_LANG_Ruby; + case DW_LNAME_Move: + return DW_LANG_Move; + case DW_LNAME_Hylo: + return DW_LANG_Hylo; + } + return {}; +} + +/// Convert a DWARF 5 DW_LANG to a DWARF 6 pair of language name and version. +inline std::optional> +toDW_LNAME(SourceLanguage language) { + switch (language) { + case DW_LANG_Ada83: + return {{DW_LNAME_Ada, 1983}}; + case DW_LANG_Ada95: + return {{DW_LNAME_Ada, 1995}}; + case DW_LANG_Ada2005: + return {{DW_LNAME_Ada, 2005}}; + case DW_LANG_Ada2012: + return {{DW_LNAME_Ada, 2012}}; + case DW_LANG_BLISS: + return {{DW_LNAME_BLISS, 0}}; + case DW_LANG_C: + return {{DW_LNAME_C, 0}}; + case DW_LANG_C89: + return {{DW_LNAME_C, 198912}}; + case DW_LANG_C99: + return {{DW_LNAME_C, 199901}}; + case DW_LANG_C11: + return {{DW_LNAME_C, 201112}}; + case DW_LANG_C17: + return {{DW_LNAME_C, 201712}}; + case DW_LANG_C_plus_plus: + return {{DW_LNAME_C_plus_plus, 0}}; + case DW_LANG_C_plus_plus_03: + return {{DW_LNAME_C_plus_plus, 200310}}; + case DW_LANG_C_plus_plus_11: + return {{DW_LNAME_C_plus_plus, 201103}}; + case DW_LANG_C_plus_plus_14: + return {{DW_LNAME_C_plus_plus, 201402}}; + case DW_LANG_C_plus_plus_17: + return {{DW_LNAME_C_plus_plus, 201703}}; + case DW_LANG_C_plus_plus_20: + return {{DW_LNAME_C_plus_plus, 202002}}; + case DW_LANG_Cobol74: + return {{DW_LNAME_Cobol, 1974}}; + case DW_LANG_Cobol85: + return {{DW_LNAME_Cobol, 1985}}; + case DW_LANG_Crystal: + return {{DW_LNAME_Crystal, 0}}; + case DW_LANG_D: + return {{DW_LNAME_D, 0}}; + case DW_LANG_Dylan: + return {{DW_LNAME_Dylan, 0}}; + case DW_LANG_Fortran77: + return {{DW_LNAME_Fortran, 1977}}; + case DW_LANG_Fortran90: + return {{DW_LNAME_Fortran, 1990}}; + case DW_LANG_Fortran95: + return {{DW_LNAME_Fortran, 1995}}; + case DW_LANG_Fortran03: + return {{DW_LNAME_Fortran, 2003}}; + case DW_LANG_Fortran08: + return {{DW_LNAME_Fortran, 2008}}; + case DW_LANG_Fortran18: + return {{DW_LNAME_Fortran, 2018}}; + case DW_LANG_Go: + return {{DW_LNAME_Go, 0}}; + case DW_LANG_Haskell: + return {{DW_LNAME_Haskell, 0}}; + case DW_LANG_HIP: + return {}; // return {{DW_LNAME_HIP, 0}}; + case DW_LANG_Java: + return {{DW_LNAME_Java, 0}}; + case DW_LANG_Julia: + return {{DW_LNAME_Julia, 0}}; + case DW_LANG_Kotlin: + return {{DW_LNAME_Kotlin, 0}}; + case DW_LANG_Modula2: + return {{DW_LNAME_Modula2, 0}}; + case DW_LANG_Modula3: + return {{DW_LNAME_Modula3, 0}}; + case DW_LANG_ObjC: + return {{DW_LNAME_ObjC, 0}}; + case DW_LANG_ObjC_plus_plus: + return {{DW_LNAME_ObjC_plus_plus, 0}}; + case DW_LANG_OCaml: + return {{DW_LNAME_OCaml, 0}}; + case DW_LANG_OpenCL: + return {{DW_LNAME_OpenCL_C, 0}}; + case DW_LANG_Pascal83: + return {{DW_LNAME_Pascal, 1983}}; + case DW_LANG_PLI: + return {{DW_LNAME_PLI, 0}}; + case DW_LANG_Python: + return {{DW_LNAME_Python, 0}}; + case DW_LANG_RenderScript: + case DW_LANG_GOOGLE_RenderScript: + return {{DW_LNAME_RenderScript, 0}}; + case DW_LANG_Rust: + return {{DW_LNAME_Rust, 0}}; + case DW_LANG_Swift: + return {{DW_LNAME_Swift, 0}}; + case DW_LANG_UPC: + return {{DW_LNAME_UPC, 0}}; + case DW_LANG_Zig: + return {{DW_LNAME_Zig, 0}}; + case DW_LANG_Assembly: + case DW_LANG_Mips_Assembler: + return {{DW_LNAME_Assembly, 0}}; + case DW_LANG_C_sharp: + return {{DW_LNAME_C_sharp, 0}}; + case DW_LANG_Mojo: + return {{DW_LNAME_Mojo, 0}}; + case DW_LANG_GLSL: + return {{DW_LNAME_GLSL, 0}}; + case DW_LANG_GLSL_ES: + return {{DW_LNAME_GLSL_ES, 0}}; + case DW_LANG_HLSL: + return {{DW_LNAME_HLSL, 0}}; + case DW_LANG_OpenCL_CPP: + return {{DW_LNAME_OpenCL_CPP, 0}}; + case DW_LANG_SYCL: + return {{DW_LNAME_SYCL, 0}}; + case DW_LANG_Ruby: + return {{DW_LNAME_Ruby, 0}}; + case DW_LANG_Move: + return {{DW_LNAME_Move, 0}}; + case DW_LANG_Hylo: + return {{DW_LNAME_Hylo, 0}}; + case DW_LANG_BORLAND_Delphi: + case DW_LANG_CPP_for_OpenCL: + case DW_LANG_lo_user: + case DW_LANG_hi_user: + return {}; + } + return {}; +} + +llvm::StringRef LanguageDescription(SourceLanguageName name); + inline bool isCPlusPlus(SourceLanguage S) { bool result = false; // Deliberately enumerate all the language options so we get a warning when @@ -268,7 +546,19 @@ inline bool isCPlusPlus(SourceLanguage S) { case DW_LANG_Fortran18: case DW_LANG_Ada2005: case DW_LANG_Ada2012: + case DW_LANG_HIP: + case DW_LANG_Assembly: + case DW_LANG_C_sharp: case DW_LANG_Mojo: + case DW_LANG_GLSL: + case DW_LANG_GLSL_ES: + case DW_LANG_HLSL: + case DW_LANG_OpenCL_CPP: + case DW_LANG_CPP_for_OpenCL: + case DW_LANG_SYCL: + case DW_LANG_Ruby: + case DW_LANG_Move: + case DW_LANG_Hylo: result = false; break; } @@ -335,7 +625,19 @@ inline bool isFortran(SourceLanguage S) { case DW_LANG_C17: case DW_LANG_Ada2005: case DW_LANG_Ada2012: + case DW_LANG_HIP: + case DW_LANG_Assembly: + case DW_LANG_C_sharp: case DW_LANG_Mojo: + case DW_LANG_GLSL: + case DW_LANG_GLSL_ES: + case DW_LANG_HLSL: + case DW_LANG_OpenCL_CPP: + case DW_LANG_CPP_for_OpenCL: + case DW_LANG_SYCL: + case DW_LANG_Ruby: + case DW_LANG_Move: + case DW_LANG_Hylo: result = false; break; } @@ -400,7 +702,19 @@ inline bool isC(SourceLanguage S) { case DW_LANG_Fortran18: case DW_LANG_Ada2005: case DW_LANG_Ada2012: + case DW_LANG_HIP: + case DW_LANG_Assembly: + case DW_LANG_C_sharp: case DW_LANG_Mojo: + case DW_LANG_GLSL: + case DW_LANG_GLSL_ES: + case DW_LANG_HLSL: + case DW_LANG_OpenCL_CPP: + case DW_LANG_CPP_for_OpenCL: + case DW_LANG_SYCL: + case DW_LANG_Ruby: + case DW_LANG_Move: + case DW_LANG_Hylo: return false; } llvm_unreachable("Unknown language kind."); diff --git a/llvm/lib/BinaryFormat/Dwarf.cpp b/llvm/lib/BinaryFormat/Dwarf.cpp index e4e5b5dd8c0e..732426617268 100644 --- a/llvm/lib/BinaryFormat/Dwarf.cpp +++ b/llvm/lib/BinaryFormat/Dwarf.cpp @@ -411,6 +411,16 @@ llvm::dwarf::LanguageLowerBound(dwarf::SourceLanguage Lang) { } } +StringRef llvm::dwarf::LanguageDescription(dwarf::SourceLanguageName lname) { + switch (lname) { +#define HANDLE_DW_LNAME(ID, NAME, DESC, LOWER_BOUND) \ + case DW_LNAME_##NAME: \ + return DESC; +#include "llvm/BinaryFormat/Dwarf.def" + } + return "Unknown"; +} + StringRef llvm::dwarf::CaseString(unsigned Case) { switch (Case) { case DW_ID_case_sensitive: diff --git a/llvm/unittests/BinaryFormat/DwarfTest.cpp b/llvm/unittests/BinaryFormat/DwarfTest.cpp index 2fff8657939b..684e59fa2785 100644 --- a/llvm/unittests/BinaryFormat/DwarfTest.cpp +++ b/llvm/unittests/BinaryFormat/DwarfTest.cpp @@ -204,4 +204,19 @@ TEST(DwarfTest, format_provider) { EXPECT_EQ("DW_OP_lit0", formatv("{0}", DW_OP_lit0).str()); EXPECT_EQ("DW_OP_unknown_ff", formatv("{0}", DW_OP_hi_user).str()); } + +TEST(DwarfTest, lname) { + auto roundtrip = [](llvm::dwarf::SourceLanguage sl) { + auto name_version = toDW_LNAME(sl); + // Ignore ones without a defined mapping. + if (sl == DW_LANG_Mips_Assembler || sl == DW_LANG_GOOGLE_RenderScript || + !name_version.has_value()) + return sl; + return dwarf::toDW_LANG(name_version->first, name_version->second) + .value_or(sl); + }; +#define HANDLE_DW_LANG(ID, NAME, LOWER_BOUND, VERSION, VENDOR) \ + EXPECT_EQ(roundtrip(DW_LANG_##NAME), DW_LANG_##NAME); +#include "llvm/BinaryFormat/Dwarf.def" +} } // end namespace -- GitLab From 6e722bbe30bd7d44f8b1dbf70e9f341a7c7e65ff Mon Sep 17 00:00:00 2001 From: Stanislav Mekhanoshin Date: Fri, 26 Apr 2024 13:02:57 -0700 Subject: [PATCH 095/301] [AMDGPU] Support byte_sel modifier on v_cvt_sr_fp8_f32 and v_cvt_sr_bf8_f32 (#90244) --- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 36 ++++++++++++--- .../Disassembler/AMDGPUDisassembler.cpp | 8 ---- llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp | 5 ++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp | 10 ++++ .../AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h | 2 + llvm/lib/Target/AMDGPU/SIInstrInfo.td | 17 ++++--- llvm/lib/Target/AMDGPU/VOP3Instructions.td | 46 ++++++++++++++++--- llvm/lib/Target/AMDGPU/VOPInstructions.td | 23 ++++++++-- .../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll | 8 +--- .../CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll | 12 ++--- llvm/test/MC/AMDGPU/gfx12_asm_vop3.s | 24 ++++++++++ llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s | 24 ++++++++++ llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s | 24 ++++++++++ llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s | 5 ++ .../Disassembler/AMDGPU/gfx12_dasm_vop3.txt | 18 ++++++++ .../AMDGPU/gfx12_dasm_vop3_dpp16.txt | 18 ++++++++ .../AMDGPU/gfx12_dasm_vop3_dpp8.txt | 18 ++++++++ 17 files changed, 256 insertions(+), 42 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index 386672352114..c4ec7a7befd4 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -172,6 +172,7 @@ public: ImmTyWaitEXP, ImmTyWaitVAVDst, ImmTyWaitVMVSrc, + ImmTyByteSel, }; // Immediate operand kind. @@ -410,6 +411,9 @@ public: bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); } bool isNegLo() const { return isImmTy(ImmTyNegLo); } bool isNegHi() const { return isImmTy(ImmTyNegHi); } + bool isByteSel() const { + return isImmTy(ImmTyByteSel) && isUInt<2>(getImm()); + } bool isRegOrImm() const { return isReg() || isImm(); @@ -1139,6 +1143,7 @@ public: case ImmTyWaitEXP: OS << "WaitEXP"; break; case ImmTyWaitVAVDst: OS << "WaitVAVDst"; break; case ImmTyWaitVMVSrc: OS << "WaitVMVSrc"; break; + case ImmTyByteSel: OS << "ByteSel" ; break; } // clang-format on } @@ -8644,6 +8649,13 @@ void AMDGPUAsmParser::cvtVOP3(MCInst &Inst, const OperandVector &Operands, } } + if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::byte_sel)) { + assert(AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::vdst_in)); + Inst.addOperand(Inst.getOperand(0)); + addOptionalImmOperand(Inst, Operands, OptionalIdx, + AMDGPUOperand::ImmTyByteSel); + } + if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp)) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); @@ -8680,8 +8692,8 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands, if (Opc == AMDGPU::V_CVT_SR_BF8_F32_vi || Opc == AMDGPU::V_CVT_SR_FP8_F32_vi || - Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_gfx12 || - Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_gfx12) { + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_gfx12 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_gfx12) { Inst.addOperand(MCOperand::createImm(0)); // Placeholder for src2_mods Inst.addOperand(Inst.getOperand(0)); } @@ -8692,7 +8704,11 @@ void AMDGPUAsmParser::cvtVOP3P(MCInst &Inst, const OperandVector &Operands, !(Opc == AMDGPU::V_CVT_PK_BF8_F32_e64_dpp_gfx12 || Opc == AMDGPU::V_CVT_PK_FP8_F32_e64_dpp_gfx12 || Opc == AMDGPU::V_CVT_PK_BF8_F32_e64_dpp8_gfx12 || - Opc == AMDGPU::V_CVT_PK_FP8_F32_e64_dpp8_gfx12)) { + Opc == AMDGPU::V_CVT_PK_FP8_F32_e64_dpp8_gfx12 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx12 || + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx12 || + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx12)) { assert(!IsPacked); Inst.addOperand(Inst.getOperand(0)); } @@ -9207,10 +9223,11 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, Inst.addOperand(Inst.getOperand(0)); } - bool IsVOP3CvtSrDpp = Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || - Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12 || - Opc == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || - Opc == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12; + bool IsVOP3CvtSrDpp = + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp8_gfx12 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp8_gfx12 || + Opc == AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64_dpp_gfx12 || + Opc == AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64_dpp_gfx12; if (IsVOP3CvtSrDpp) { if (Src2ModIdx == static_cast(Inst.getNumOperands())) { Inst.addOperand(MCOperand::createImm(0)); @@ -9243,6 +9260,11 @@ void AMDGPUAsmParser::cvtVOP3DPP(MCInst &Inst, const OperandVector &Operands, llvm_unreachable("unhandled operand type"); } } + + if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::byte_sel)) + addOptionalImmOperand(Inst, Operands, OptionalIdx, + AMDGPUOperand::ImmTyByteSel); + if (AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::clamp)) addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyClampSI); diff --git a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp index dc1bf92771b4..8fd36b84a00c 100644 --- a/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp +++ b/llvm/lib/Target/AMDGPU/Disassembler/AMDGPUDisassembler.cpp @@ -869,10 +869,6 @@ void AMDGPUDisassembler::convertDPP8Inst(MCInst &MI) const { if (VDstInIdx != -1) insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); - if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp8_gfx12 || - MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp8_gfx12) - insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); - unsigned DescNumOps = MCII->get(Opc).getNumOperands(); if (MI.getNumOperands() < DescNumOps && AMDGPU::hasNamedOperand(Opc, AMDGPU::OpName::op_sel)) { @@ -902,10 +898,6 @@ void AMDGPUDisassembler::convertVOP3DPPInst(MCInst &MI) const { if (VDstInIdx != -1) insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::vdst_in); - if (MI.getOpcode() == AMDGPU::V_CVT_SR_BF8_F32_e64_dpp_gfx12 || - MI.getOpcode() == AMDGPU::V_CVT_SR_FP8_F32_e64_dpp_gfx12) - insertNamedMCOperand(MI, MI.getOperand(0), AMDGPU::OpName::src2); - unsigned Opc = MI.getOpcode(); unsigned DescNumOps = MCII->get(Opc).getNumOperands(); if (MI.getNumOperands() < DescNumOps && diff --git a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp index 5090b0a07da4..91733c2933b4 100644 --- a/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp +++ b/llvm/lib/Target/AMDGPU/GCNDPPCombine.cpp @@ -409,6 +409,11 @@ MachineInstr *GCNDPPCombine::createDPPInst(MachineInstr &OrigMI, if (NegHiOpr && AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::neg_hi)) { DPPInst.addImm(NegHiOpr->getImm()); } + auto *ByteSelOpr = TII->getNamedOperand(OrigMI, AMDGPU::OpName::byte_sel); + if (ByteSelOpr && + AMDGPU::hasNamedOperand(DPPOp, AMDGPU::OpName::byte_sel)) { + DPPInst.addImm(ByteSelOpr->getImm()); + } } DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::row_mask)); diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp index b6a95906bc45..883b6c4407fe 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.cpp @@ -1806,4 +1806,14 @@ void AMDGPUInstPrinter::printEndpgm(const MCInst *MI, unsigned OpNo, O << ' ' << formatDec(Imm); } +void AMDGPUInstPrinter::printByteSel(const MCInst *MI, unsigned OpNo, + const MCSubtargetInfo &STI, + raw_ostream &O) { + uint8_t Imm = MI->getOperand(OpNo).getImm(); + if (!Imm) + return; + + O << " byte_sel:" << formatDec(Imm); +} + #include "AMDGPUGenAsmWriter.inc" diff --git a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h index c801eaf1111e..d6d7fd34b68c 100644 --- a/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h +++ b/llvm/lib/Target/AMDGPU/MCTargetDesc/AMDGPUInstPrinter.h @@ -186,6 +186,8 @@ private: const MCSubtargetInfo &STI, raw_ostream &O); void printExpTgt(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, raw_ostream &O); + void printByteSel(const MCInst *MI, unsigned OpNo, const MCSubtargetInfo &STI, + raw_ostream &O); public: static void printIfSet(const MCInst *MI, unsigned OpNo, raw_ostream &O, diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index f1afbcc060b2..bf6cfe90ebfb 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1123,6 +1123,8 @@ def WaitEXP : NamedIntOperand; def WaitVAVDst : NamedIntOperand; def WaitVMVSrc : NamedIntOperand; +def ByteSel : NamedIntOperand; + class KImmFPOperand : ImmOperand { let OperandNamespace = "AMDGPU"; let OperandType = "OPERAND_KIMM"#vt.Size; @@ -1700,9 +1702,9 @@ class getIns64 { + bit Src1HasMods, bit Src2HasMods, ValueType DstVT = i32, + bit HasByteSel = 0> { string dst = !if(HasDst, !if(!eq(DstVT.Size, 1), "$sdst", @@ -2058,6 +2061,7 @@ class getAsmVOP3Base _ArgVT, bit _EnableClamp = 0> { field bit IsSWMMAC = 0; field bit IsFP8 = 0; + field bit IsFP8DstByteSel = 0; field bit HasDst = !ne(DstVT.Value, untyped.Value); field bit HasDst32 = HasDst; @@ -2401,7 +2406,7 @@ class VOPProfile _ArgVT, bit _EnableClamp = 0> { field string AsmDPP8 = getAsmDPP8.ret; field string AsmVOP3Base = getAsmVOP3Base.ret; + HasModifiers, DstVT, IsFP8DstByteSel>.ret; field string Asm64 = AsmVOP3Base; field string AsmVOP3P = getAsmVOP3P.ret; field string AsmVOP3OpSel = getAsmVOP3OpSel, HasSrc2FloatMods>.ret>.ret); } +class VOP3_CVT_SR_F8_ByteSel_Profile : + VOP3_Profile> { + let IsFP8DstByteSel = 1; + let HasClamp = 0; + defvar bytesel = (ins VGPR_32:$vdst_in, ByteSel:$byte_sel); + let Ins64 = !con(getIns64.ret, + bytesel); + let InsVOP3Base = !con( + getInsVOP3Base.ret, + bytesel); +} + def IsPow2Plus1: PatLeaf<(i32 imm), [{ uint32_t V = N->getZExtValue(); return isPowerOf2_32(V - 1); @@ -645,12 +661,17 @@ let OtherPredicates = [HasFP8ConversionInsts], mayRaiseFPException = 0, let Constraints = "$vdst = $vdst_in", DisableEncoding = "$vdst_in" in { defm V_CVT_PK_FP8_F32 : VOP3Inst<"v_cvt_pk_fp8_f32", VOP3_CVT_PK_F8_F32_Profile>; defm V_CVT_PK_BF8_F32 : VOP3Inst<"v_cvt_pk_bf8_f32", VOP3_CVT_PK_F8_F32_Profile>; + + let SubtargetPredicate = isGFX12Plus in { + defm V_CVT_SR_FP8_F32_gfx12 : VOP3Inst<"v_cvt_sr_fp8_f32_gfx12", VOP3_CVT_SR_F8_ByteSel_Profile>; + defm V_CVT_SR_BF8_F32_gfx12 : VOP3Inst<"v_cvt_sr_bf8_f32_gfx12", VOP3_CVT_SR_F8_ByteSel_Profile>; + } } // These instructions have non-standard use of op_sel. In particular they are // using op_sel bits 2 and 3 while only having two sources. Therefore dummy // src2 is used to hold the op_sel value. - let Constraints = "$vdst = $src2", DisableEncoding = "$src2" in { + let Constraints = "$vdst = $src2", DisableEncoding = "$src2", SubtargetPredicate = isGFX940Plus in { defm V_CVT_SR_FP8_F32 : VOP3Inst<"v_cvt_sr_fp8_f32", VOP3_CVT_SR_F8_F32_Profile>; defm V_CVT_SR_BF8_F32 : VOP3Inst<"v_cvt_sr_bf8_f32", VOP3_CVT_SR_F8_F32_Profile>; } @@ -667,15 +688,28 @@ class Cvt_SR_F8_F32_Pat index, VOP3_Pseudo inst> !if(index{0}, SRCMODS.OP_SEL_0, 0), $old, 0) >; +class Cvt_SR_F8_ByteSel_Pat : GCNPat< + (i32 (node (VOP3Mods SrcVT:$src0, i32:$src0_modifiers), (VOP3Mods i32:$src1, i32:$src1_modifiers), + i32:$old, timm:$byte_sel)), + (inst $src0_modifiers, $src0, $src1_modifiers, $src1, $old, (as_i32timm $byte_sel)) +>; + let OtherPredicates = [HasFP8ConversionInsts] in { foreach Index = [0, -1] in { def : Cvt_PK_F8_F32_Pat; def : Cvt_PK_F8_F32_Pat; } -foreach Index = [0, 1, 2, 3] in { - def : Cvt_SR_F8_F32_Pat; - def : Cvt_SR_F8_F32_Pat; +let SubtargetPredicate = isGFX940Plus in { + foreach Index = [0, 1, 2, 3] in { + def : Cvt_SR_F8_F32_Pat; + def : Cvt_SR_F8_F32_Pat; + } +} + +let SubtargetPredicate = isGFX12Plus in { + def : Cvt_SR_F8_ByteSel_Pat; + def : Cvt_SR_F8_ByteSel_Pat; } } @@ -1040,8 +1074,8 @@ defm V_PERMLANEX16_VAR_B32 : VOP3Only_Real_Base_gfx12<0x310>; defm V_CVT_PK_FP8_F32 : VOP3Only_Realtriple_gfx12<0x369>; defm V_CVT_PK_BF8_F32 : VOP3Only_Realtriple_gfx12<0x36a>; -defm V_CVT_SR_FP8_F32 : VOP3Only_Realtriple_gfx12<0x36b>; -defm V_CVT_SR_BF8_F32 : VOP3Only_Realtriple_gfx12<0x36c>; +defm V_CVT_SR_FP8_F32_gfx12 : VOP3_Realtriple_with_name_gfx12<0x36b, "V_CVT_SR_FP8_F32_gfx12", "v_cvt_sr_fp8_f32" >; +defm V_CVT_SR_BF8_F32_gfx12 : VOP3_Realtriple_with_name_gfx12<0x36c, "V_CVT_SR_BF8_F32_gfx12", "v_cvt_sr_bf8_f32">; //===----------------------------------------------------------------------===// // GFX11, GFX12 diff --git a/llvm/lib/Target/AMDGPU/VOPInstructions.td b/llvm/lib/Target/AMDGPU/VOPInstructions.td index da16178cb58b..7cdb5cbfe297 100644 --- a/llvm/lib/Target/AMDGPU/VOPInstructions.td +++ b/llvm/lib/Target/AMDGPU/VOPInstructions.td @@ -311,6 +311,14 @@ class VOP3FP8OpSel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10 { let Inst{12} = !if(p.HasSrc0, src0_modifiers{3}, 0); } + class VOP3FP8OpSel_dst_bytesel_gfx11_gfx12 op, VOPProfile p> : VOP3e_gfx10 { + bits<2> byte_sel; + + let Inst{11} = 0; // op_sel0 + let Inst{12} = 0; // op_sel1 + let Inst{14-13} = byte_sel; // op_sel2/3 + } + class VOP3DotOpSel_gfx11_gfx12 op, VOPProfile p> : VOP3OpSel_gfx11_gfx12{ let Inst{11} = ?; let Inst{12} = ?; @@ -741,6 +749,7 @@ class VOP3_DPPe_Common_Base op, VOPProfile P> : Enc96 { bits<3> src2_modifiers; bits<1> clamp; bits<2> omod; + bits<2> byte_sel; let Inst{8} = !if(P.HasSrc0Mods, src0_modifiers{1}, 0); let Inst{9} = !if(P.HasSrc1Mods, src1_modifiers{1}, 0); @@ -748,8 +757,8 @@ class VOP3_DPPe_Common_Base op, VOPProfile P> : Enc96 { // OPSEL must be set such that the low result only uses low inputs, and the high result only uses high inputs. let Inst{11} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{2}, 0),?); let Inst{12} = !if(P.HasOpSel,!if(P.HasSrc1Mods, src1_modifiers{2}, !if((P.IsFP8), src0_modifiers{3}, 0)), ?); - let Inst{13} = !if(P.HasOpSel,!if(P.HasSrc2Mods, src2_modifiers{2}, 0),?); - let Inst{14} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{3}, 0),?); + let Inst{13} = !if(P.HasOpSel,!if(P.HasSrc2Mods, src2_modifiers{2}, 0),!if(P.IsFP8DstByteSel, byte_sel{0}, ?)); + let Inst{14} = !if(P.HasOpSel,!if(P.HasSrc0Mods, src0_modifiers{3}, 0),!if(P.IsFP8DstByteSel, byte_sel{1}, ?)); let Inst{15} = !if(P.HasClamp, clamp, 0); let Inst{25-16} = op; let Inst{31-26} = 0x35; @@ -1388,7 +1397,11 @@ multiclass VOP3_Real_Base op, string opName = NAME, bit isSingle = 0> { defvar ps = !cast(opName#"_e64"); let IsSingle = !or(isSingle, ps.Pfl.IsSingle) in { - if ps.Pfl.HasOpSel then { + if ps.Pfl.IsFP8DstByteSel then { + def _e64#Gen.Suffix : + VOP3_Real_Gen, + VOP3FP8OpSel_dst_bytesel_gfx11_gfx12; + } if ps.Pfl.HasOpSel then { def _e64#Gen.Suffix : VOP3_Real_Gen, VOP3OpSel_gfx11_gfx12; @@ -1419,6 +1432,10 @@ multiclass VOP3_Real_with_name op, string opName, def _e64#Gen.Suffix : VOP3_Real_Gen, VOP3FP8OpSel_gfx11_gfx12; + } else if ps.Pfl.IsFP8DstByteSel then { + def _e64#Gen.Suffix : + VOP3_Real_Gen, + VOP3FP8OpSel_dst_bytesel_gfx11_gfx12; } else if ps.Pfl.HasOpSel then { def _e64#Gen.Suffix : VOP3_Real_Gen, diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll index e21d61036375..ffedde9416bb 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.dpp.ll @@ -97,9 +97,7 @@ define amdgpu_cs void @test_cvt_sr_bf8_f32_byte0(i32 %a, i32 %r, i32 %old, ptr a define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) { ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte1: ; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 op_sel:[0,0,1,0] +; GFX12-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:1 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX12-NEXT: global_store_b32 v[3:4], v2, off ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) @@ -114,9 +112,7 @@ define amdgpu_cs void @test_cvt_sr_fp8_f32_byte1(i32 %a, i32 %r, i32 %old, ptr a define amdgpu_cs void @test_cvt_sr_fp8_f32_byte2(i32 %a, i32 %r, i32 %old, ptr addrspace(1) %out) { ; GFX12-LABEL: test_cvt_sr_fp8_f32_byte2: ; GFX12: ; %bb.0: -; GFX12-NEXT: v_mov_b32_dpp v0, v0 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 -; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) -; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 op_sel:[0,0,0,1] +; GFX12-NEXT: v_cvt_sr_fp8_f32_e64_dpp v2, v0, v1 byte_sel:2 quad_perm:[0,1,2,3] row_mask:0xf bank_mask:0xf bound_ctrl:1 ; GFX12-NEXT: global_store_b32 v[3:4], v2, off ; GFX12-NEXT: s_nop 0 ; GFX12-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS) diff --git a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll index 9b8fdf901704..7662a3b78dea 100644 --- a/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll +++ b/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.cvt.fp8.ll @@ -385,7 +385,7 @@ define i32 @test_cvt_sr_bf8_f32_byte1(float %x, i32 %r, i32 %old) { ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 op_sel:[0,0,1,0] +; GFX12-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 byte_sel:1 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: s_setpc_b64 s[30:31] @@ -409,7 +409,7 @@ define i32 @test_cvt_sr_bf8_f32_byte2(float %x, i32 %r, i32 %old) { ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 op_sel:[0,0,0,1] +; GFX12-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 byte_sel:2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: s_setpc_b64 s[30:31] @@ -433,7 +433,7 @@ define i32 @test_cvt_sr_bf8_f32_byte3(float %x, i32 %r, i32 %old) { ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 op_sel:[0,0,1,1] +; GFX12-NEXT: v_cvt_sr_bf8_f32 v2, v0, v1 byte_sel:3 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: s_setpc_b64 s[30:31] @@ -479,7 +479,7 @@ define i32 @test_cvt_sr_fp8_f32_byte1(float %x, i32 %r, i32 %old) { ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 op_sel:[0,0,1,0] +; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:1 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: s_setpc_b64 s[30:31] @@ -503,7 +503,7 @@ define i32 @test_cvt_sr_fp8_f32_byte2(float %x, i32 %r, i32 %old) { ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 op_sel:[0,0,0,1] +; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:2 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: s_setpc_b64 s[30:31] @@ -527,7 +527,7 @@ define i32 @test_cvt_sr_fp8_f32_byte3(float %x, i32 %r, i32 %old) { ; GFX12-NEXT: s_wait_samplecnt 0x0 ; GFX12-NEXT: s_wait_bvhcnt 0x0 ; GFX12-NEXT: s_wait_kmcnt 0x0 -; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 op_sel:[0,0,1,1] +; GFX12-NEXT: v_cvt_sr_fp8_f32 v2, v0, v1 byte_sel:3 ; GFX12-NEXT: s_delay_alu instid0(VALU_DEP_1) ; GFX12-NEXT: v_mov_b32_e32 v0, v2 ; GFX12-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s index be9edc3e019e..b0854881d428 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3.s @@ -1126,6 +1126,18 @@ v_cvt_sr_fp8_f32 v10, s2, v5 v_cvt_sr_fp8_f32 v5, -|v255|, v4 // GFX12: encoding: [0x05,0x01,0x6b,0xd7,0xff,0x09,0x02,0x20] +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 +// GFX12: v_cvt_sr_fp8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6b,0xd7,0x02,0x07,0x02,0x00] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 +// GFX12: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6b,0xd7,0x02,0x07,0x02,0x00] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 +// GFX12: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6b,0xd7,0x02,0x07,0x02,0x00] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 +// GFX12: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6b,0xd7,0x02,0x07,0x02,0x00] + v_cvt_sr_bf8_f32 v1, v2, v3 // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x00] @@ -1135,6 +1147,18 @@ v_cvt_sr_bf8_f32 v10, s2, v5 v_cvt_sr_bf8_f32 v5, -|v255|, v4 // GFX12: encoding: [0x05,0x01,0x6c,0xd7,0xff,0x09,0x02,0x20] +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 +// GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x00] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 +// GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6c,0xd7,0x02,0x07,0x02,0x00] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 +// GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6c,0xd7,0x02,0x07,0x02,0x00] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 +// GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6c,0xd7,0x02,0x07,0x02,0x00] + v_cvt_pk_i16_f32 v5, v1, v2 // GFX12: encoding: [0x05,0x00,0x06,0xd7,0x01,0x05,0x02,0x00] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s index d0e309adce41..16cd8d5aa5e9 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp16.s @@ -1192,6 +1192,18 @@ v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 // GFX12: encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] @@ -1219,6 +1231,18 @@ v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 // GFX12: encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] + v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] // GFX12: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s index 25b13ac62e4a..d6ef14cff5fa 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_dpp8.s @@ -698,6 +698,18 @@ v_cvt_sr_fp8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] v_cvt_sr_fp8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] // GFX12: encoding: [0xff,0x01,0x6b,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + v_cvt_sr_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // GFX12: encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] @@ -710,6 +722,18 @@ v_cvt_sr_bf8_f32_e64_dpp v5, -v1, v2 dpp8:[7,6,5,4,3,2,1,0] v_cvt_sr_bf8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] // GFX12: encoding: [0xff,0x01,0x6c,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:0 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x00,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] +// GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] + v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] // GFX12: [0x05,0x00,0x06,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s index 55c5fcabea73..31ed577ac0a2 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s @@ -101,3 +101,8 @@ v_permlane16_var_b32 v5, v1, v2 op_sel:[0, 0, 1] // GFX12: error: invalid op_sel operand // GFX12-NEXT:{{^}}v_permlane16_var_b32 v5, v1, v2 op_sel:[0, 0, 1] // GFX12-NEXT:{{^}} ^ + +v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4 +// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// GFX12-NEXT:{{^}}v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4 +// GFX12-NEXT:{{^}} ^ diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt index 6acaa8152720..2c911777ef97 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3.txt @@ -1020,6 +1020,15 @@ # GFX12: v_cvt_sr_fp8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6b,0xd7,0xff,0x09,0x02,0x20] 0x05,0x01,0x6b,0xd7,0xff,0x09,0x02,0x20 +# GFX12: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6b,0xd7,0x02,0x07,0x02,0x00] +0x01,0x20,0x6b,0xd7,0x02,0x07,0x02,0x00 + +# GFX12: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6b,0xd7,0x02,0x07,0x02,0x00] +0x01,0x40,0x6b,0xd7,0x02,0x07,0x02,0x00 + +# GFX12: v_cvt_sr_fp8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6b,0xd7,0x02,0x07,0x02,0x00] +0x01,0x60,0x6b,0xd7,0x02,0x07,0x02,0x00 + # GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 ; encoding: [0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x00] 0x01,0x00,0x6c,0xd7,0x02,0x07,0x02,0x00 @@ -1029,6 +1038,15 @@ # GFX12: v_cvt_sr_bf8_f32 v5, -|v255|, v4 ; encoding: [0x05,0x01,0x6c,0xd7,0xff,0x09,0x02,0x20] 0x05,0x01,0x6c,0xd7,0xff,0x09,0x02,0x20 +# GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:1 ; encoding: [0x01,0x20,0x6c,0xd7,0x02,0x07,0x02,0x00] +0x01,0x20,0x6c,0xd7,0x02,0x07,0x02,0x00 + +# GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:2 ; encoding: [0x01,0x40,0x6c,0xd7,0x02,0x07,0x02,0x00] +0x01,0x40,0x6c,0xd7,0x02,0x07,0x02,0x00 + +# GFX12: v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:3 ; encoding: [0x01,0x60,0x6c,0xd7,0x02,0x07,0x02,0x00] +0x01,0x60,0x6c,0xd7,0x02,0x07,0x02,0x00 + # GFX12: v_cvt_pk_i16_f32 v5, v1, v2 ; encoding: [0x05,0x00,0x06,0xd7,0x01,0x05,0x02,0x00] 0x05,0x00,0x06,0xd7,0x01,0x05,0x02,0x00 diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt index 0771e6449b62..f9b6c1b73ddc 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp16.txt @@ -945,6 +945,15 @@ # GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] 0x01,0x00,0x6c,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed +# GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] +0x01,0x20,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff + +# GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] +0x01,0x40,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff + +# GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] +0x01,0x60,0x6c,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff + # GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed] 0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x00,0xed @@ -972,6 +981,15 @@ # GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, -v2, v3 quad_perm:[3,2,1,0] row_mask:0xe bank_mask:0xd fi:1 ; encoding: [0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed] 0x01,0x00,0x6b,0xd7,0xfa,0x06,0x02,0x20,0x02,0x1b,0x04,0xed +# GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] +0x01,0x20,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff + +# GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] +0x01,0x40,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff + +# GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff] +0x01,0x60,0x6b,0xd7,0xfa,0x06,0x02,0x00,0x02,0x1b,0x00,0xff + # GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 quad_perm:[3,2,1,0] row_mask:0xf bank_mask:0xf ; encoding: [0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff] 0x05,0x00,0x06,0xd7,0xfa,0x04,0x02,0x00,0x01,0x1b,0x00,0xff diff --git a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt index a836adafb31e..eedc6d491087 100644 --- a/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt +++ b/llvm/test/MC/Disassembler/AMDGPU/gfx12_dasm_vop3_dpp8.txt @@ -570,6 +570,15 @@ # GFX12: v_cvt_sr_fp8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6b,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] 0xff,0x01,0x6b,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 +# GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] +0x01,0x20,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 + +# GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] +0x01,0x40,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 + +# GFX12: v_cvt_sr_fp8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] +0x01,0x60,0x6b,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 + # GFX12: v_cvt_sr_bf8_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x05,0x00,0x6c,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 @@ -582,6 +591,15 @@ # GFX12: v_cvt_sr_bf8_f32_e64_dpp v255, -|v255|, v255 dpp8:[0,0,0,0,0,0,0,0] ; encoding: [0xff,0x01,0x6c,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00] 0xff,0x01,0x6c,0xd7,0xe9,0xfe,0x03,0x20,0xff,0x00,0x00,0x00 +# GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:1 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x20,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] +0x01,0x20,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 + +# GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x40,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] +0x01,0x40,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 + +# GFX12: v_cvt_sr_bf8_f32_e64_dpp v1, v2, v3 byte_sel:3 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x01,0x60,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05] +0x01,0x60,0x6c,0xd7,0xe9,0x06,0x02,0x00,0x02,0x77,0x39,0x05 + # GFX12: v_cvt_pk_i16_f32_e64_dpp v5, v1, v2 dpp8:[7,6,5,4,3,2,1,0] ; encoding: [0x05,0x00,0x06,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05] 0x05,0x00,0x06,0xd7,0xe9,0x04,0x02,0x00,0x01,0x77,0x39,0x05 -- GitLab From ced8497970aec5a153211d352ff01c624e03abd6 Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Fri, 26 Apr 2024 22:06:24 +0200 Subject: [PATCH 096/301] [ci] Add clang project dependency for bolt testing (#90262) --- .ci/generate-buildkite-pipeline-premerge | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/.ci/generate-buildkite-pipeline-premerge b/.ci/generate-buildkite-pipeline-premerge index 81e9246de9b5..78a9cb77ff7d 100755 --- a/.ci/generate-buildkite-pipeline-premerge +++ b/.ci/generate-buildkite-pipeline-premerge @@ -91,7 +91,7 @@ function add-dependencies() { echo "${project}" case ${project} in bolt) - for p in lld llvm; do + for p in clang lld llvm; do echo $p done ;; -- GitLab From 022dc6bab5c47dfd18cde87f36e8fece43328fdf Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Fri, 26 Apr 2024 13:11:12 -0700 Subject: [PATCH 097/301] [NFC] [HWASan] factor out debug record annotation (#90252) This will also be used by stack MTE --- .../Transforms/Utils/MemoryTaggingSupport.h | 2 ++ .../Instrumentation/HWAddressSanitizer.cpp | 31 +---------------- .../Transforms/Utils/MemoryTaggingSupport.cpp | 33 +++++++++++++++++++ 3 files changed, 36 insertions(+), 30 deletions(-) diff --git a/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h b/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h index fb3ab33a0629..16589a605e60 100644 --- a/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h +++ b/llvm/include/llvm/Transforms/Utils/MemoryTaggingSupport.h @@ -86,6 +86,8 @@ Value *getFP(IRBuilder<> &IRB); Value *getPC(const Triple &TargetTriple, IRBuilder<> &IRB); Value *getAndroidSlotPtr(IRBuilder<> &IRB, int Slot); +void annotateDebugRecords(AllocaInfo &Info, unsigned int Tag); + } // namespace memtag } // namespace llvm diff --git a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp index 88b852340340..fa661b17c13a 100644 --- a/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/HWAddressSanitizer.cpp @@ -1385,14 +1385,6 @@ bool HWAddressSanitizer::instrumentLandingPads( return true; } -static DbgAssignIntrinsic *DynCastToDbgAssign(DbgVariableIntrinsic *DVI) { - return dyn_cast(DVI); -} - -static DbgVariableRecord *DynCastToDbgAssign(DbgVariableRecord *DVR) { - return DVR->isDbgAssign() ? DVR : nullptr; -} - bool HWAddressSanitizer::instrumentStack(memtag::StackInfo &SInfo, Value *StackTag, Value *UARTag, const DominatorTree &DT, @@ -1448,28 +1440,7 @@ bool HWAddressSanitizer::instrumentStack(memtag::StackInfo &SInfo, !memtag::isLifetimeIntrinsic(User); }); - // Helper utility for adding DW_OP_LLVM_tag_offset to debug-info records, - // abstracted over whether they're intrinsic-stored or DbgVariableRecord - // stored. - auto AnnotateDbgRecord = [&](auto *DPtr) { - // Prepend "tag_offset, N" to the dwarf expression. - // Tag offset logically applies to the alloca pointer, and it makes sense - // to put it at the beginning of the expression. - SmallVector NewOps = {dwarf::DW_OP_LLVM_tag_offset, - retagMask(N)}; - for (size_t LocNo = 0; LocNo < DPtr->getNumVariableLocationOps(); ++LocNo) - if (DPtr->getVariableLocationOp(LocNo) == AI) - DPtr->setExpression(DIExpression::appendOpsToArg( - DPtr->getExpression(), NewOps, LocNo)); - if (auto *DAI = DynCastToDbgAssign(DPtr)) { - if (DAI->getAddress() == AI) - DAI->setAddressExpression(DIExpression::prependOpcodes( - DAI->getAddressExpression(), NewOps)); - } - }; - - llvm::for_each(Info.DbgVariableIntrinsics, AnnotateDbgRecord); - llvm::for_each(Info.DbgVariableRecords, AnnotateDbgRecord); + memtag::annotateDebugRecords(Info, retagMask(N)); auto TagEnd = [&](Instruction *Node) { IRB.SetInsertPoint(Node); diff --git a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp index 7b1eb70168d8..0464ba5e1811 100644 --- a/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp +++ b/llvm/lib/Transforms/Utils/MemoryTaggingSupport.cpp @@ -17,6 +17,7 @@ #include "llvm/Analysis/PostDominators.h" #include "llvm/Analysis/StackSafetyAnalysis.h" #include "llvm/Analysis/ValueTracking.h" +#include "llvm/BinaryFormat/Dwarf.h" #include "llvm/IR/BasicBlock.h" #include "llvm/IR/IRBuilder.h" #include "llvm/IR/IntrinsicInst.h" @@ -283,5 +284,37 @@ Value *getAndroidSlotPtr(IRBuilder<> &IRB, int Slot) { IRB.CreateCall(ThreadPointerFunc), 8 * Slot); } +static DbgAssignIntrinsic *DynCastToDbgAssign(DbgVariableIntrinsic *DVI) { + return dyn_cast(DVI); +} + +static DbgVariableRecord *DynCastToDbgAssign(DbgVariableRecord *DVR) { + return DVR->isDbgAssign() ? DVR : nullptr; +} + +void annotateDebugRecords(AllocaInfo &Info, unsigned int Tag) { + // Helper utility for adding DW_OP_LLVM_tag_offset to debug-info records, + // abstracted over whether they're intrinsic-stored or DbgVariableRecord + // stored. + auto AnnotateDbgRecord = [&](auto *DPtr) { + // Prepend "tag_offset, N" to the dwarf expression. + // Tag offset logically applies to the alloca pointer, and it makes sense + // to put it at the beginning of the expression. + SmallVector NewOps = {dwarf::DW_OP_LLVM_tag_offset, Tag}; + for (size_t LocNo = 0; LocNo < DPtr->getNumVariableLocationOps(); ++LocNo) + if (DPtr->getVariableLocationOp(LocNo) == Info.AI) + DPtr->setExpression( + DIExpression::appendOpsToArg(DPtr->getExpression(), NewOps, LocNo)); + if (auto *DAI = DynCastToDbgAssign(DPtr)) { + if (DAI->getAddress() == Info.AI) + DAI->setAddressExpression( + DIExpression::prependOpcodes(DAI->getAddressExpression(), NewOps)); + } + }; + + llvm::for_each(Info.DbgVariableIntrinsics, AnnotateDbgRecord); + llvm::for_each(Info.DbgVariableRecords, AnnotateDbgRecord); +} + } // namespace memtag } // namespace llvm -- GitLab From a4c21d17fe187feb9e666ae8290b6d318014e9c8 Mon Sep 17 00:00:00 2001 From: Chelsea Cassanova Date: Fri, 26 Apr 2024 13:18:45 -0700 Subject: [PATCH 098/301] [lldb][sbapi] Fix API break in SBDebugger broadcast bits (#90261) https://github.com/llvm/llvm-project/pull/87409 removed the broadcast bits from SBDebugger and placed them in `lldb-enumerations.h`. This is API-breaking so this commits places the enum back into `SBDebugger.h` and references the bits from `lldb-enumerations.h`. rdar://127128536 --- lldb/include/lldb/API/SBDebugger.h | 7 +++++++ .../diagnostic_reporting/TestDiagnosticReporting.py | 2 +- .../progress_reporting/TestProgressReporting.py | 2 +- .../clang_modules/TestClangModuleBuildProgress.py | 2 +- lldb/test/API/macosx/rosetta/TestRosetta.py | 2 +- lldb/tools/lldb-dap/lldb-dap.cpp | 4 ++-- 6 files changed, 13 insertions(+), 6 deletions(-) diff --git a/lldb/include/lldb/API/SBDebugger.h b/lldb/include/lldb/API/SBDebugger.h index cf5409a12a05..7333cd57ad31 100644 --- a/lldb/include/lldb/API/SBDebugger.h +++ b/lldb/include/lldb/API/SBDebugger.h @@ -42,6 +42,13 @@ public: class LLDB_API SBDebugger { public: + FLAGS_ANONYMOUS_ENUM(){ + eBroadcastBitProgress = lldb::DebuggerBroadcastBit::eBroadcastBitProgress, + eBroadcastBitWarning = lldb::DebuggerBroadcastBit::eBroadcastBitWarning, + eBroadcastBitError = lldb::DebuggerBroadcastBit::eBroadcastBitError, + eBroadcastBitProgressCategory = + lldb::DebuggerBroadcastBit::eBroadcastBitProgressCategory, + }; SBDebugger(); SBDebugger(const lldb::SBDebugger &rhs); diff --git a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py index 6353e3e8cbed..36a3be695628 100644 --- a/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py +++ b/lldb/test/API/functionalities/diagnostic_reporting/TestDiagnosticReporting.py @@ -15,7 +15,7 @@ class TestDiagnosticReporting(TestBase): self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( self.broadcaster, - lldb.eBroadcastBitWarning | lldb.eBroadcastBitError, + lldb.SBDebugger.eBroadcastBitWarning | lldb.SBDebugger.eBroadcastBitError, ) def test_dwarf_symbol_loading_diagnostic_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py index 98988d7624da..9af53845ca1b 100644 --- a/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py +++ b/lldb/test/API/functionalities/progress_reporting/TestProgressReporting.py @@ -13,7 +13,7 @@ class TestProgressReporting(TestBase): TestBase.setUp(self) self.broadcaster = self.dbg.GetBroadcaster() self.listener = lldbutil.start_listening_from( - self.broadcaster, lldb.eBroadcastBitProgress + self.broadcaster, lldb.SBDebugger.eBroadcastBitProgress ) def test_dwarf_symbol_loading_progress_report(self): diff --git a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py index 33c7c269c081..228f676aedf6 100644 --- a/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py +++ b/lldb/test/API/functionalities/progress_reporting/clang_modules/TestClangModuleBuildProgress.py @@ -34,7 +34,7 @@ class TestCase(TestBase): # other unrelated progress events. broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.eBroadcastBitProgress + broadcaster, lldb.SBDebugger.eBroadcastBitProgress ) # Trigger module builds. diff --git a/lldb/test/API/macosx/rosetta/TestRosetta.py b/lldb/test/API/macosx/rosetta/TestRosetta.py index 669db95a1624..ce40de475ef1 100644 --- a/lldb/test/API/macosx/rosetta/TestRosetta.py +++ b/lldb/test/API/macosx/rosetta/TestRosetta.py @@ -49,7 +49,7 @@ class TestRosetta(TestBase): if rosetta_debugserver_installed(): broadcaster = self.dbg.GetBroadcaster() listener = lldbutil.start_listening_from( - broadcaster, lldb.eBroadcastBitWarning + broadcaster, lldb.SBDebugger.eBroadcastBitWarning ) target, process, thread, bkpt = lldbutil.run_to_source_breakpoint( diff --git a/lldb/tools/lldb-dap/lldb-dap.cpp b/lldb/tools/lldb-dap/lldb-dap.cpp index d0fbb9155715..8000d68dea7e 100644 --- a/lldb/tools/lldb-dap/lldb-dap.cpp +++ b/lldb/tools/lldb-dap/lldb-dap.cpp @@ -421,8 +421,8 @@ void SendStdOutStdErr(lldb::SBProcess &process) { void ProgressEventThreadFunction() { lldb::SBListener listener("lldb-dap.progress.listener"); - g_dap.debugger.GetBroadcaster().AddListener(listener, - lldb::eBroadcastBitProgress); + g_dap.debugger.GetBroadcaster().AddListener( + listener, lldb::SBDebugger::eBroadcastBitProgress); g_dap.broadcaster.AddListener(listener, eBroadcastBitStopProgressThread); lldb::SBEvent event; bool done = false; -- GitLab From 9ee8e38cdcc6925a4127d44a0360dc8de23dfb5f Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Fri, 26 Apr 2024 21:29:42 +0100 Subject: [PATCH 099/301] [VPlan] Also propagate versioned strides to users via sext/zext. The versioned value may not be used in the loop directly but through a sext/zext. Add new live-ins in those cases. --- .../Transforms/Vectorize/LoopVectorize.cpp | 22 +++++++--- llvm/lib/Transforms/Vectorize/VPlan.h | 3 ++ .../LoopVectorize/runtime-checks-hoist.ll | 6 +-- .../version-stride-with-integer-casts.ll | 42 ++++++------------- 4 files changed, 35 insertions(+), 38 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 33c4decd58a6..74ceb9eecf21 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -8817,12 +8817,24 @@ LoopVectorizationPlanner::tryToBuildVPlanWithVPRecipes(VFRange &Range) { // Only handle constant strides for now. if (!ScevStride) continue; - Constant *CI = ConstantInt::get(Stride->getType(), ScevStride->getAPInt()); - auto *ConstVPV = Plan->getOrAddLiveIn(CI); - // The versioned value may not be used in the loop directly, so just add a - // new live-in in those cases. - Plan->getOrAddLiveIn(StrideV)->replaceAllUsesWith(ConstVPV); + auto *CI = Plan->getOrAddLiveIn( + ConstantInt::get(Stride->getType(), ScevStride->getAPInt())); + if (VPValue *StrideVPV = Plan->getLiveIn(StrideV)) + StrideVPV->replaceAllUsesWith(CI); + + // The versioned value may not be used in the loop directly but through a + // sext/zext. Add new live-ins in those cases. + for (Value *U : StrideV->users()) { + if (!isa(U)) + continue; + VPValue *StrideVPV = Plan->getLiveIn(U); + if (!StrideVPV) + continue; + VPValue *CI = Plan->getOrAddLiveIn(ConstantInt::get( + U->getType(), ScevStride->getAPInt().getSExtValue())); + StrideVPV->replaceAllUsesWith(CI); + } } VPlanTransforms::dropPoisonGeneratingRecipes(*Plan, [this](BasicBlock *BB) { diff --git a/llvm/lib/Transforms/Vectorize/VPlan.h b/llvm/lib/Transforms/Vectorize/VPlan.h index 21b088cd2386..71387bf5b7e9 100644 --- a/llvm/lib/Transforms/Vectorize/VPlan.h +++ b/llvm/lib/Transforms/Vectorize/VPlan.h @@ -3215,6 +3215,9 @@ public: return Value2VPValue[V]; } + /// Return the live-in VPValue for \p V, if there is one or nullptr otherwise. + VPValue *getLiveIn(Value *V) const { return Value2VPValue.lookup(V); } + #if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP) /// Print the live-ins of this VPlan to \p O. void printLiveIns(raw_ostream &O) const; diff --git a/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll b/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll index 0b9b592627c6..c4f9c404a926 100644 --- a/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll +++ b/llvm/test/Transforms/LoopVectorize/runtime-checks-hoist.ll @@ -1328,13 +1328,11 @@ define void @unknown_inner_stride(ptr nocapture noundef %dst, ptr nocapture noun ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP15:%.*]] = mul nsw i64 [[TMP14]], [[TMP0]] -; CHECK-NEXT: [[TMP16:%.*]] = add nsw i64 [[TMP15]], [[TMP11]] +; CHECK-NEXT: [[TMP16:%.*]] = add nsw i64 [[TMP14]], [[TMP11]] ; CHECK-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[SRC]], i64 [[TMP16]] ; CHECK-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP18]], align 4, !alias.scope [[META60:![0-9]+]] -; CHECK-NEXT: [[TMP19:%.*]] = mul nsw i64 [[TMP14]], [[TMP1]] -; CHECK-NEXT: [[TMP20:%.*]] = add nsw i64 [[TMP19]], [[TMP12]] +; CHECK-NEXT: [[TMP20:%.*]] = add nsw i64 [[TMP14]], [[TMP12]] ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr inbounds i32, ptr [[DST]], i64 [[TMP20]] ; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i32, ptr [[TMP21]], i32 0 ; CHECK-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP22]], align 4, !alias.scope [[META63:![0-9]+]], !noalias [[META60]] diff --git a/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll b/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll index 693a8b287615..d09066fa2d70 100644 --- a/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll +++ b/llvm/test/Transforms/LoopVectorize/version-stride-with-integer-casts.ll @@ -34,7 +34,7 @@ define void @test_versioned_with_sext_use(i32 %offset, ptr %dst) { ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0 ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8 -; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]] +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] @@ -110,7 +110,7 @@ define void @test_versioned_with_zext_use(i32 %offset, ptr %dst) { ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP3]] ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[TMP4]], i32 0 ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP5]], align 8 -; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]] +; CHECK-NEXT: [[TMP6:%.*]] = add i64 [[TMP3]], 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 ; CHECK-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] @@ -165,38 +165,23 @@ define void @versioned_sext_use_in_gep(i32 %scale, ptr %dst, i64 %scale.2) { ; CHECK-NEXT: [[IDENT_CHECK:%.*]] = icmp ne i32 [[SCALE]], 1 ; CHECK-NEXT: br i1 [[IDENT_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[SCALE_EXT]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <4 x i64> poison, i64 [[SCALE_2]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT1]], <4 x i64> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[TMP0:%.*]] = mul <4 x i64> [[VEC_IND]], [[BROADCAST_SPLAT]] -; CHECK-NEXT: [[TMP1:%.*]] = extractelement <4 x i64> [[TMP0]], i32 0 -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]] -; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i64> [[TMP0]], i32 1 -; CHECK-NEXT: [[TMP4:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP3]] -; CHECK-NEXT: [[TMP5:%.*]] = extractelement <4 x i64> [[TMP0]], i32 2 -; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP5]] -; CHECK-NEXT: [[TMP7:%.*]] = extractelement <4 x i64> [[TMP0]], i32 3 -; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP7]] -; CHECK-NEXT: [[TMP9:%.*]] = mul <4 x i64> [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT2]] -; CHECK-NEXT: [[TMP10:%.*]] = extractelement <4 x i64> [[TMP9]], i32 0 +; CHECK-NEXT: [[TMP10:%.*]] = add i64 [[INDEX]], 0 +; CHECK-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 1 +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP16:%.*]] = add i64 [[INDEX]], 3 ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP10]] -; CHECK-NEXT: [[TMP12:%.*]] = extractelement <4 x i64> [[TMP9]], i32 1 ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP12]] -; CHECK-NEXT: [[TMP14:%.*]] = extractelement <4 x i64> [[TMP9]], i32 2 ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP14]] -; CHECK-NEXT: [[TMP16:%.*]] = extractelement <4 x i64> [[TMP9]], i32 3 ; CHECK-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP16]] -; CHECK-NEXT: store ptr [[TMP11]], ptr [[TMP2]], align 8 -; CHECK-NEXT: store ptr [[TMP13]], ptr [[TMP4]], align 8 -; CHECK-NEXT: store ptr [[TMP15]], ptr [[TMP6]], align 8 -; CHECK-NEXT: store ptr [[TMP17]], ptr [[TMP8]], align 8 +; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[SCALE_2]] +; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP11]], align 8 +; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP13]], align 8 +; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP15]], align 8 +; CHECK-NEXT: store ptr [[TMP8]], ptr [[TMP17]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], ; CHECK-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 256 ; CHECK-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] ; CHECK: middle.block: @@ -282,7 +267,7 @@ define void @test_versioned_with_different_uses(i32 %offset, ptr noalias %dst.1, ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP3]] ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[TMP12]], i32 0 ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP13]], align 8 -; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], [[OFFSET_EXT]] +; CHECK-NEXT: [[TMP14:%.*]] = add i64 [[TMP3]], 1 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], 200 ; CHECK-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] @@ -376,8 +361,7 @@ define void @test_versioned_with_non_ex_use(i32 %offset, ptr noalias %dst.1, ptr ; CHECK-NEXT: store i32 0, ptr [[TMP14]], align 8 ; CHECK-NEXT: store i32 0, ptr [[TMP16]], align 8 ; CHECK-NEXT: store i32 0, ptr [[TMP18]], align 8 -; CHECK-NEXT: [[TMP19:%.*]] = mul i64 [[TMP9]], [[OFFSET_EXT]] -; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP19]] +; CHECK-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST_2]], i64 [[TMP9]] ; CHECK-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[TMP20]], i32 0 ; CHECK-NEXT: store <4 x i32> zeroinitializer, ptr [[TMP21]], align 8 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 -- GitLab From eb5907d06f2ffc3ed7fb8d4772bd3f8eab89c726 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Valentin=20Clement=20=28=E3=83=90=E3=83=AC=E3=83=B3?= =?UTF-8?q?=E3=82=BF=E3=82=A4=E3=83=B3=20=E3=82=AF=E3=83=AC=E3=83=A1?= =?UTF-8?q?=E3=83=B3=29?= Date: Fri, 26 Apr 2024 13:31:34 -0700 Subject: [PATCH 100/301] [flang][cuda] Avoid to issue data transfer in device context (#90247) Data transfer should not be issued in device function. --- flang/lib/Lower/Bridge.cpp | 28 ++++++++++++++++---- flang/test/Lower/CUDA/cuda-data-transfer.cuf | 18 +++++++++++++ 2 files changed, 41 insertions(+), 5 deletions(-) diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index f66607dfa22f..92a701a7b98c 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -3806,16 +3806,34 @@ private: return temps; } + // Check if the insertion point is currently in a device context. HostDevice + // subprogram are not considered fully device context so it will return false + // for it. + static bool isDeviceContext(fir::FirOpBuilder &builder) { + if (builder.getRegion().getParentOfType()) + return true; + if (auto funcOp = + builder.getRegion().getParentOfType()) { + if (auto cudaProcAttr = + funcOp.getOperation()->getAttrOfType( + fir::getCUDAAttrName())) { + return cudaProcAttr.getValue() != fir::CUDAProcAttribute::Host && + cudaProcAttr.getValue() != fir::CUDAProcAttribute::HostDevice; + } + } + return false; + } + void genDataAssignment( const Fortran::evaluate::Assignment &assign, const Fortran::evaluate::ProcedureRef *userDefinedAssignment) { mlir::Location loc = getCurrentLocation(); fir::FirOpBuilder &builder = getFirOpBuilder(); - bool isInDeviceContext = - builder.getRegion().getParentOfType(); - bool isCUDATransfer = Fortran::evaluate::HasCUDAAttrs(assign.lhs) || - Fortran::evaluate::HasCUDAAttrs(assign.rhs); + bool isInDeviceContext = isDeviceContext(builder); + bool isCUDATransfer = (Fortran::evaluate::HasCUDAAttrs(assign.lhs) || + Fortran::evaluate::HasCUDAAttrs(assign.rhs)) && + !isInDeviceContext; bool hasCUDAImplicitTransfer = Fortran::evaluate::HasCUDAImplicitTransfer(assign.rhs); llvm::SmallVector implicitTemps; @@ -3878,7 +3896,7 @@ private: Fortran::lower::StatementContext localStmtCtx; hlfir::Entity rhs = evaluateRhs(localStmtCtx); hlfir::Entity lhs = evaluateLhs(localStmtCtx); - if (isCUDATransfer && !hasCUDAImplicitTransfer && !isInDeviceContext) + if (isCUDATransfer && !hasCUDAImplicitTransfer) genCUDADataTransfer(builder, loc, assign, lhs, rhs); else builder.create(loc, rhs, lhs, diff --git a/flang/test/Lower/CUDA/cuda-data-transfer.cuf b/flang/test/Lower/CUDA/cuda-data-transfer.cuf index 70483685d200..0a2608639bce 100644 --- a/flang/test/Lower/CUDA/cuda-data-transfer.cuf +++ b/flang/test/Lower/CUDA/cuda-data-transfer.cuf @@ -141,3 +141,21 @@ end subroutine ! CHECK: fir.cuda_kernel<<<*, *>>> ! CHECK-NOT: fir.cuda_data_transfer ! CHECK: hlfir.assign + +attributes(global) subroutine sub5(a) + integer, device :: a + integer :: i + a = i +end subroutine + +! CHECK-LABEL: func.func @_QPsub5 +! CHECK-NOT: fir.cuda_data_transfer + +attributes(host,device) subroutine sub6(a) + integer, device :: a + integer :: i + a = i +end subroutine + +! CHECK-LABEL: func.func @_QPsub6 +! CHECK: fir.cuda_data_transfer -- GitLab From d9fd0ddef38bb9d5cce7300ff820272183c09fcd Mon Sep 17 00:00:00 2001 From: Brendan Dahl Date: Fri, 26 Apr 2024 14:03:21 -0700 Subject: [PATCH 101/301] [WebAssembly] Add half-precision feature (#90248) This currently only defines a constant, but in the future will be used to gate builtins for experimenting and prototyping half-precision proposal (https://github.com/WebAssembly/half-precision). --- clang/include/clang/Driver/Options.td | 2 ++ clang/lib/Basic/Targets/WebAssembly.cpp | 11 +++++++++++ clang/lib/Basic/Targets/WebAssembly.h | 1 + clang/test/Driver/wasm-features.c | 6 ++++++ llvm/lib/Target/WebAssembly/WebAssembly.td | 3 +++ llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td | 4 ++++ llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h | 2 ++ 7 files changed, 29 insertions(+) diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 5a6526b0592f..41f713a47c2e 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -4881,6 +4881,8 @@ def msimd128 : Flag<["-"], "msimd128">, Group; def mno_simd128 : Flag<["-"], "mno-simd128">, Group; def mrelaxed_simd : Flag<["-"], "mrelaxed-simd">, Group; def mno_relaxed_simd : Flag<["-"], "mno-relaxed-simd">, Group; +def mhalf_precision : Flag<["-"], "mhalf-precision">, Group; +def mno_half_precision : Flag<["-"], "mno-half-precision">, Group; def mnontrapping_fptoint : Flag<["-"], "mnontrapping-fptoint">, Group; def mno_nontrapping_fptoint : Flag<["-"], "mno-nontrapping-fptoint">, Group; def msign_ext : Flag<["-"], "msign-ext">, Group; diff --git a/clang/lib/Basic/Targets/WebAssembly.cpp b/clang/lib/Basic/Targets/WebAssembly.cpp index d473fd190864..3d76411f890a 100644 --- a/clang/lib/Basic/Targets/WebAssembly.cpp +++ b/clang/lib/Basic/Targets/WebAssembly.cpp @@ -47,6 +47,7 @@ bool WebAssemblyTargetInfo::hasFeature(StringRef Feature) const { return llvm::StringSwitch(Feature) .Case("simd128", SIMDLevel >= SIMD128) .Case("relaxed-simd", SIMDLevel >= RelaxedSIMD) + .Case("half-precision", HasHalfPrecision) .Case("nontrapping-fptoint", HasNontrappingFPToInt) .Case("sign-ext", HasSignExt) .Case("exception-handling", HasExceptionHandling) @@ -156,6 +157,7 @@ bool WebAssemblyTargetInfo::initFeatureMap( Features["reference-types"] = true; Features["sign-ext"] = true; Features["tail-call"] = true; + Features["half-precision"] = true; setSIMDLevel(Features, SIMD128, true); } else if (CPU == "generic") { Features["mutable-globals"] = true; @@ -216,6 +218,15 @@ bool WebAssemblyTargetInfo::handleTargetFeatures( HasBulkMemory = false; continue; } + if (Feature == "+half-precision") { + SIMDLevel = std::max(SIMDLevel, SIMD128); + HasHalfPrecision = true; + continue; + } + if (Feature == "-half-precision") { + HasHalfPrecision = false; + continue; + } if (Feature == "+atomics") { HasAtomics = true; continue; diff --git a/clang/lib/Basic/Targets/WebAssembly.h b/clang/lib/Basic/Targets/WebAssembly.h index 5568aa28eaef..e4c18879182e 100644 --- a/clang/lib/Basic/Targets/WebAssembly.h +++ b/clang/lib/Basic/Targets/WebAssembly.h @@ -64,6 +64,7 @@ class LLVM_LIBRARY_VISIBILITY WebAssemblyTargetInfo : public TargetInfo { bool HasReferenceTypes = false; bool HasExtendedConst = false; bool HasMultiMemory = false; + bool HasHalfPrecision = false; std::string ABI; diff --git a/clang/test/Driver/wasm-features.c b/clang/test/Driver/wasm-features.c index 5dae5dbc89b9..1f7fb2134982 100644 --- a/clang/test/Driver/wasm-features.c +++ b/clang/test/Driver/wasm-features.c @@ -77,6 +77,12 @@ // RELAXED-SIMD: "-target-feature" "+relaxed-simd" // NO-RELAXED-SIMD: "-target-feature" "-relaxed-simd" +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mhalf-precision 2>&1 | FileCheck %s -check-prefix=HALF-PRECISION +// RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-half-precision 2>&1 | FileCheck %s -check-prefix=NO-HALF-PRECISION + +// HALF-PRECISION: "-target-feature" "+half-precision" +// NO-HALF-PRECISION: "-target-feature" "-half-precision" + // RUN: %clang --target=wasm32-unknown-unknown -### %s -mexception-handling 2>&1 | FileCheck %s -check-prefix=EXCEPTION-HANDLING // RUN: %clang --target=wasm32-unknown-unknown -### %s -mno-exception-handling 2>&1 | FileCheck %s -check-prefix=NO-EXCEPTION-HANDLING diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.td b/llvm/lib/Target/WebAssembly/WebAssembly.td index d538197450b6..f00974531209 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.td +++ b/llvm/lib/Target/WebAssembly/WebAssembly.td @@ -28,6 +28,9 @@ def FeatureSIMD128 : SubtargetFeature<"simd128", "SIMDLevel", "SIMD128", def FeatureRelaxedSIMD : SubtargetFeature<"relaxed-simd", "SIMDLevel", "RelaxedSIMD", "Enable relaxed-simd instructions">; +def FeatureHalfPrecision : SubtargetFeature<"half-precision", "HasHalfPrecision", "true", + "Enable half precision instructions">; + def FeatureAtomics : SubtargetFeature<"atomics", "HasAtomics", "true", "Enable Atomics">; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td index 59ea9247bd86..7b57f8ce90e0 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td +++ b/llvm/lib/Target/WebAssembly/WebAssemblyInstrInfo.td @@ -30,6 +30,10 @@ def HasRelaxedSIMD : Predicate<"Subtarget->hasRelaxedSIMD()">, AssemblerPredicate<(all_of FeatureRelaxedSIMD), "relaxed-simd">; +def HasHalfPrecision : + Predicate<"Subtarget->hasHalfPrecision()">, + AssemblerPredicate<(all_of FeatureHalfPrecision), "half-precision">; + def HasAtomics : Predicate<"Subtarget->hasAtomics()">, AssemblerPredicate<(all_of FeatureAtomics), "atomics">; diff --git a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h index 85d02b087c78..8b0d9fa12de8 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h +++ b/llvm/lib/Target/WebAssembly/WebAssemblySubtarget.h @@ -50,6 +50,7 @@ class WebAssemblySubtarget final : public WebAssemblyGenSubtargetInfo { bool HasReferenceTypes = false; bool HasExtendedConst = false; bool HasMultiMemory = false; + bool HasHalfPrecision = false; /// What processor and OS we're targeting. Triple TargetTriple; @@ -93,6 +94,7 @@ public: bool hasAddr64() const { return TargetTriple.isArch64Bit(); } bool hasSIMD128() const { return SIMDLevel >= SIMD128; } bool hasRelaxedSIMD() const { return SIMDLevel >= RelaxedSIMD; } + bool hasHalfPrecision() const { return HasHalfPrecision; } bool hasAtomics() const { return HasAtomics; } bool hasNontrappingFPToInt() const { return HasNontrappingFPToInt; } bool hasSignExt() const { return HasSignExt; } -- GitLab From 12d322db46952d15e36f5ce5863a2c70eee7857d Mon Sep 17 00:00:00 2001 From: Maksim Panchenko Date: Fri, 26 Apr 2024 14:13:23 -0700 Subject: [PATCH 102/301] [BOLT][NFC] Use getEHFrameHdrSectionName() (#90257) Reference section name via wrapper. --- bolt/include/bolt/Rewrite/RewriteInstance.h | 1 + bolt/lib/Rewrite/RewriteInstance.cpp | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 8 deletions(-) diff --git a/bolt/include/bolt/Rewrite/RewriteInstance.h b/bolt/include/bolt/Rewrite/RewriteInstance.h index 2561468a0f99..f4bffba96b1d 100644 --- a/bolt/include/bolt/Rewrite/RewriteInstance.h +++ b/bolt/include/bolt/Rewrite/RewriteInstance.h @@ -424,6 +424,7 @@ private: /// Common section names. static StringRef getEHFrameSectionName() { return ".eh_frame"; } + static StringRef getEHFrameHdrSectionName() { return ".eh_frame_hdr"; } static StringRef getRelaDynSectionName() { return ".rela.dyn"; } /// FILE symbol name used for local fragments of global functions. diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index 3cf0e749f9d6..409835537fde 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -3978,8 +3978,8 @@ void RewriteInstance::patchELFPHDRTable() { NewPhdr.p_filesz = sizeof(NewPhdr) * Phnum; NewPhdr.p_memsz = sizeof(NewPhdr) * Phnum; } else if (Phdr.p_type == ELF::PT_GNU_EH_FRAME) { - ErrorOr EHFrameHdrSec = - BC->getUniqueSectionByName(getNewSecPrefix() + ".eh_frame_hdr"); + ErrorOr EHFrameHdrSec = BC->getUniqueSectionByName( + getNewSecPrefix() + getEHFrameHdrSectionName()); if (EHFrameHdrSec && EHFrameHdrSec->isAllocatable() && EHFrameHdrSec->isFinalized()) { NewPhdr.p_offset = EHFrameHdrSec->getOutputFileOffset(); @@ -5692,7 +5692,8 @@ void RewriteInstance::writeEHFrameHeader() { BC->AsmInfo->getCodePointerSize())); check_error(std::move(Er), "failed to parse EH frame"); - LLVM_DEBUG(dbgs() << "BOLT: writing a new .eh_frame_hdr\n"); + LLVM_DEBUG(dbgs() << "BOLT: writing a new " << getEHFrameHdrSectionName() + << '\n'); NextAvailableAddress = appendPadding(Out->os(), NextAvailableAddress, EHFrameHdrAlign); @@ -5710,16 +5711,17 @@ void RewriteInstance::writeEHFrameHeader() { const unsigned Flags = BinarySection::getFlags(/*IsReadOnly=*/true, /*IsText=*/false, /*IsAllocatable=*/true); - BinarySection *OldEHFrameHdrSection = getSection(".eh_frame_hdr"); + BinarySection *OldEHFrameHdrSection = getSection(getEHFrameHdrSectionName()); if (OldEHFrameHdrSection) - OldEHFrameHdrSection->setOutputName(getOrgSecPrefix() + ".eh_frame_hdr"); + OldEHFrameHdrSection->setOutputName(getOrgSecPrefix() + + getEHFrameHdrSectionName()); BinarySection &EHFrameHdrSec = BC->registerOrUpdateSection( - getNewSecPrefix() + ".eh_frame_hdr", ELF::SHT_PROGBITS, Flags, nullptr, - NewEHFrameHdr.size(), /*Alignment=*/1); + getNewSecPrefix() + getEHFrameHdrSectionName(), ELF::SHT_PROGBITS, Flags, + nullptr, NewEHFrameHdr.size(), /*Alignment=*/1); EHFrameHdrSec.setOutputFileOffset(EHFrameHdrFileOffset); EHFrameHdrSec.setOutputAddress(EHFrameHdrOutputAddress); - EHFrameHdrSec.setOutputName(".eh_frame_hdr"); + EHFrameHdrSec.setOutputName(getEHFrameHdrSectionName()); NextAvailableAddress += EHFrameHdrSec.getOutputSize(); -- GitLab From 3d5e9ab6d89bfe3454e2b6f80b4babaa69413a87 Mon Sep 17 00:00:00 2001 From: Ryosuke Niwa Date: Fri, 26 Apr 2024 14:28:27 -0700 Subject: [PATCH 103/301] [alpha.webkit.UncountedCallArgsChecker] Avoid emitting warnings for Ref, RefPtr, and their variants. (#90153) Skip the analysis of Ref, RefPtr, and their variant classes in UncountedCallArgsChecker since these classes are "trusted" to not do anything dangerous. --- .../Checkers/WebKit/PtrTypesSemantics.h | 3 + .../WebKit/UncountedCallArgsChecker.cpp | 6 ++ .../Analysis/Checkers/WebKit/call-args.cpp | 2 +- .../Analysis/Checkers/WebKit/mock-types.h | 67 ++++++++++++++----- 4 files changed, 62 insertions(+), 16 deletions(-) diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h index 9ed8e7cab6ab..ec1db1cc3358 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/PtrTypesSemantics.h @@ -50,6 +50,9 @@ std::optional isUncounted(const clang::CXXRecordDecl* Class); /// class, false if not, std::nullopt if inconclusive. std::optional isUncountedPtr(const clang::Type* T); +/// \returns true if Name is a RefPtr, Ref, or its variant, false if not. +bool isRefType(const std::string &Name); + /// \returns true if \p F creates ref-countable object from uncounted parameter, /// false if not. bool isCtorOfRefCounted(const clang::FunctionDecl *F); diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp index 8b41a949fd67..741f33676158 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp @@ -53,6 +53,12 @@ public: bool shouldVisitTemplateInstantiations() const { return true; } bool shouldVisitImplicitCode() const { return false; } + bool TraverseDecl(Decl *D) { + if (isa(D) && isRefType(safeGetName(D))) + return true; + return RecursiveASTVisitor::TraverseDecl(D); + } + bool VisitCallExpr(const CallExpr *CE) { Checker->visitCallExpr(CE); return true; diff --git a/clang/test/Analysis/Checkers/WebKit/call-args.cpp b/clang/test/Analysis/Checkers/WebKit/call-args.cpp index f2e1f9bc5a24..2a4b6bb1f106 100644 --- a/clang/test/Analysis/Checkers/WebKit/call-args.cpp +++ b/clang/test/Analysis/Checkers/WebKit/call-args.cpp @@ -32,7 +32,7 @@ namespace ref_counted { void consume_ref_counted(Ref) {} void foo() { - consume_refcntbl(provide_ref_counted().get()); + consume_refcntbl(provide_ref_counted().ptr()); // no warning } } diff --git a/clang/test/Analysis/Checkers/WebKit/mock-types.h b/clang/test/Analysis/Checkers/WebKit/mock-types.h index aab99197dfa4..c27ea9baaf3b 100644 --- a/clang/test/Analysis/Checkers/WebKit/mock-types.h +++ b/clang/test/Analysis/Checkers/WebKit/mock-types.h @@ -1,24 +1,61 @@ #ifndef mock_types_1103988513531 #define mock_types_1103988513531 -template struct Ref { - T *t; +template +struct RawPtrTraits { + using StorageType = T*; - Ref() : t{} {}; - Ref(T &t) - : t(t) { - if (t) - t->ref(); + template + static T* exchange(StorageType& ptr, U&& newValue) + { + StorageType oldValue = static_cast(ptr); + ptr = static_cast(newValue); + return oldValue; } - ~Ref() { - if (t) - t->deref(); + + static void swap(StorageType& a, StorageType& b) + { + StorageType temp = static_cast(a); + a = static_cast(b); + b = static_cast(temp); } - T *get() { return t; } - T *ptr() { return t; } - T *operator->() { return t; } - operator const T &() const { return *t; } - operator T &() { return *t; } + static T* unwrap(const StorageType& ptr) { return ptr; } +}; + +template struct DefaultRefDerefTraits { + static T* refIfNotNull(T* ptr) + { + if (ptr) + ptr->ref(); + return ptr; + } + + static T& ref(T& ref) + { + ref.ref(); + return ref; + } + + static void derefIfNotNull(T* ptr) + { + if (ptr) + ptr->deref(); + } +}; + +template , typename RefDerefTraits = DefaultRefDerefTraits> struct Ref { + typename PtrTraits::StorageType t; + + Ref() : t{} {}; + Ref(T &t) : t(RefDerefTraits::refIfNotNull(t)) { } + Ref(const Ref& o) : t(RefDerefTraits::refIfNotNull(PtrTraits::unwrap(o.t))) { } + ~Ref() { RefDerefTraits::derefIfNotNull(PtrTraits::exchange(t, nullptr)); } + T &get() { return *PtrTraits::unwrap(t); } + T *ptr() { return PtrTraits::unwrap(t); } + T *operator->() { return PtrTraits::unwrap(t); } + operator const T &() const { return *PtrTraits::unwrap(t); } + operator T &() { return *PtrTraits::unwrap(t); } + T* leakRef() { PtrTraits::exchange(t, nullptr); } }; template struct RefPtr { -- GitLab From fefac5d5458a00b28860e0193928b30be85413cd Mon Sep 17 00:00:00 2001 From: Usama Hameed Date: Fri, 26 Apr 2024 14:53:44 -0700 Subject: [PATCH 104/301] [ASan][Test] Remove hardcoded linker version from test (#90147) This is not needed as the correct linker version is detected at configure time and passed to all tests on Darwin. rdar://125052667 --- compiler-rt/test/asan/TestCases/Darwin/odr-lto.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/compiler-rt/test/asan/TestCases/Darwin/odr-lto.cpp b/compiler-rt/test/asan/TestCases/Darwin/odr-lto.cpp index 90c16776a63b..8d400800fe93 100644 --- a/compiler-rt/test/asan/TestCases/Darwin/odr-lto.cpp +++ b/compiler-rt/test/asan/TestCases/Darwin/odr-lto.cpp @@ -5,7 +5,7 @@ // RUN: %clangxx_asan -DPART=0 -c %s -o %t-1.o -flto -mllvm -asan-use-private-alias // RUN: %clangxx_asan -DPART=1 -c %s -o %t-2.o -flto -mllvm -asan-use-private-alias -// RUN: %clangxx_asan_lto %t-1.o %t-2.o -o %t -flto -mlinker-version=133 +// RUN: %clangxx_asan_lto %t-1.o %t-2.o -o %t -flto // RUN: %run %t 2>&1 | FileCheck %s #include -- GitLab From eb3030acd0bd3eaea85707cf00872e88d20f4664 Mon Sep 17 00:00:00 2001 From: Amara Emerson Date: Fri, 26 Apr 2024 15:23:03 -0700 Subject: [PATCH 105/301] [AArch64][GlobalISel] Fix legalizer crash trying to legalize <16 x i32> = G_BITCAST i512 Trying to do fewerElements on this results in an assert. rdar://126373053 --- .../AArch64/GISel/AArch64LegalizerInfo.cpp | 3 ++ .../AArch64/GlobalISel/legalize-bitcast.mir | 50 +++++++++++++++++++ 2 files changed, 53 insertions(+) create mode 100644 llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index f42c415a9e44..f654065c735d 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -740,6 +740,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST) .legalForCartesianProduct({s32, v2s16, v4s8}) .legalForCartesianProduct({s64, v8s8, v4s16, v2s32}) .legalForCartesianProduct({s128, v16s8, v8s16, v4s32, v2s64, v2p0}) + .lowerIf([=](const LegalityQuery &Query) { + return Query.Types[0].isVector() != Query.Types[1].isVector(); + }) .moreElementsToNextPow2(0) .clampNumElements(0, v8s8, v16s8) .clampNumElements(0, v4s16, v8s16) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir new file mode 100644 index 000000000000..e3a633c9e035 --- /dev/null +++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-bitcast.mir @@ -0,0 +1,50 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# RUN: llc -mtriple=aarch64 -run-pass=legalizer -global-isel-abort=1 %s -o - | FileCheck %s +--- +name: scalar_to_oversize_vector +tracksRegLiveness: true +body: | + ; CHECK-LABEL: name: scalar_to_oversize_vector + ; CHECK: bb.0: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: G_BR %bb.1 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: bb.1: + ; CHECK-NEXT: successors: %bb.1(0x80000000) + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 0 + ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s32), [[UV1:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(s32), [[UV3:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV4:%[0-9]+]]:_(s32), [[UV5:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV6:%[0-9]+]]:_(s32), [[UV7:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV8:%[0-9]+]]:_(s32), [[UV9:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV10:%[0-9]+]]:_(s32), [[UV11:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV12:%[0-9]+]]:_(s32), [[UV13:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[UV14:%[0-9]+]]:_(s32), [[UV15:%[0-9]+]]:_(s32) = G_UNMERGE_VALUES [[C]](s64) + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV]](s32), [[UV1]](s32), [[UV2]](s32), [[UV3]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR1:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV4]](s32), [[UV5]](s32), [[UV6]](s32), [[UV7]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR2:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV8]](s32), [[UV9]](s32), [[UV10]](s32), [[UV11]](s32) + ; CHECK-NEXT: [[BUILD_VECTOR3:%[0-9]+]]:_(<4 x s32>) = G_BUILD_VECTOR [[UV12]](s32), [[UV13]](s32), [[UV14]](s32), [[UV15]](s32) + ; CHECK-NEXT: [[C1:%[0-9]+]]:_(p0) = G_CONSTANT i64 0 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<4 x s32>), [[C1]](p0) :: (store (<4 x s32>), align 64) + ; CHECK-NEXT: [[C2:%[0-9]+]]:_(p0) = G_CONSTANT i64 16 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR1]](<4 x s32>), [[C2]](p0) :: (store (<4 x s32>) into unknown-address + 16) + ; CHECK-NEXT: [[C3:%[0-9]+]]:_(p0) = G_CONSTANT i64 32 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR2]](<4 x s32>), [[C3]](p0) :: (store (<4 x s32>) into unknown-address + 32, align 32) + ; CHECK-NEXT: [[C4:%[0-9]+]]:_(p0) = G_CONSTANT i64 48 + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR3]](<4 x s32>), [[C4]](p0) :: (store (<4 x s32>) into unknown-address + 48) + ; CHECK-NEXT: G_BR %bb.1 + bb.1: + %0:_(s512) = G_CONSTANT i512 0 + %2:_(p0) = G_CONSTANT i64 0 + G_BR %bb.2 + + bb.2: + %4:_(s512) = G_CONSTANT i512 0 + %1:_(<16 x s32>) = G_BITCAST %4(s512) + %3:_(p0) = G_CONSTANT i64 0 + G_STORE %1(<16 x s32>), %3(p0) :: (store (<16 x s32>)) + G_BR %bb.2 + +... -- GitLab From 8cf0f9ab2f32114afd615def833f66ebeeede7d5 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Fri, 26 Apr 2024 15:26:57 -0700 Subject: [PATCH 106/301] [msan] Add conservative handling of vscale params (#90167) Msan uses `__msan_param_tls` to pass shadow of arguments. Position of arguments is expected to be available during compile time, if size of the argument is know. This is not true for vscale. As work around we require that vscale parameters are always initialized, then we don't need to pass shadow. Ret val should work out of the box as we don't need to know size compile time. --- .../Instrumentation/MemorySanitizer.cpp | 19 ++++- .../Instrumentation/MemorySanitizer/vscale.ll | 81 +++++++++++++++++++ 2 files changed, 98 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp index 66ee2fce8313..cc2295c44023 100644 --- a/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp +++ b/llvm/lib/Transforms/Instrumentation/MemorySanitizer.cpp @@ -1955,8 +1955,15 @@ struct MemorySanitizerVisitor : public InstVisitor { unsigned ArgOffset = 0; const DataLayout &DL = F->getParent()->getDataLayout(); for (auto &FArg : F->args()) { - if (!FArg.getType()->isSized()) { - LLVM_DEBUG(dbgs() << "Arg is not sized\n"); + if (!FArg.getType()->isSized() || FArg.getType()->isScalableTy()) { + LLVM_DEBUG(dbgs() << (FArg.getType()->isScalableTy() + ? "vscale not fully supported\n" + : "Arg is not sized\n")); + if (A == &FArg) { + ShadowPtr = getCleanShadow(V); + setOrigin(A, getCleanOrigin()); + break; + } continue; } @@ -4198,6 +4205,14 @@ struct MemorySanitizerVisitor : public InstVisitor { LLVM_DEBUG(dbgs() << "Arg " << i << " is not sized: " << CB << "\n"); continue; } + + if (A->getType()->isScalableTy()) { + LLVM_DEBUG(dbgs() << "Arg " << i << " is vscale: " << CB << "\n"); + // Handle as noundef, but don't reserve tls slots. + insertShadowCheck(A, &CB); + continue; + } + unsigned Size = 0; const DataLayout &DL = F.getParent()->getDataLayout(); diff --git a/llvm/test/Instrumentation/MemorySanitizer/vscale.ll b/llvm/test/Instrumentation/MemorySanitizer/vscale.ll index b1c641881570..e1a4a9b7aa68 100644 --- a/llvm/test/Instrumentation/MemorySanitizer/vscale.ll +++ b/llvm/test/Instrumentation/MemorySanitizer/vscale.ll @@ -105,3 +105,84 @@ define void @test_load_store_add_float(ptr %a, ptr %b) sanitize_memory { store %2, ptr %b ret void } + +define @fn_ret(ptr %a) sanitize_memory { +; CHECK-LABEL: define @fn_ret( +; CHECK-SAME: ptr [[A:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP1:%.*]] = load , ptr [[A]], align 8 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load , ptr [[TMP4]], align 8 +; CHECK-NEXT: store [[_MSLD]], ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: ret [[TMP1]] +; + %1 = load , ptr %a + ret %1 +} + +define void @test_ret(ptr %a, ptr %b) sanitize_memory { +; CHECK-LABEL: define void @test_ret( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr @__msan_param_tls, align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_param_tls, align 8 +; CHECK-NEXT: store zeroinitializer, ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: [[TMP5:%.*]] = call @fn_ret(ptr [[A]]) +; CHECK-NEXT: [[_MSRET:%.*]] = load , ptr @__msan_retval_tls, align 8 +; CHECK-NEXT: [[TMP2:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP3:%.*]] = xor i64 [[TMP2]], 87960930222080 +; CHECK-NEXT: [[TMP4:%.*]] = inttoptr i64 [[TMP3]] to ptr +; CHECK-NEXT: store [[_MSRET]], ptr [[TMP4]], align 8 +; CHECK-NEXT: store [[TMP5]], ptr [[B]], align 8 +; CHECK-NEXT: ret void +; + %1 = call @fn_ret(ptr %a) + store %1, ptr %b + ret void +} + +define void @fn_param( %a, ptr %b) sanitize_memory { +; CHECK-LABEL: define void @fn_param( +; CHECK-SAME: [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP1:%.*]] = ptrtoint ptr [[B]] to i64 +; CHECK-NEXT: [[TMP2:%.*]] = xor i64 [[TMP1]], 87960930222080 +; CHECK-NEXT: [[TMP3:%.*]] = inttoptr i64 [[TMP2]] to ptr +; CHECK-NEXT: store zeroinitializer, ptr [[TMP3]], align 8 +; CHECK-NEXT: store [[A]], ptr [[B]], align 8 +; CHECK-NEXT: ret void +; + store %a, ptr %b + ret void +} + +define void @test_param(ptr %a, ptr %b) sanitize_memory { +; CHECK-LABEL: define void @test_param( +; CHECK-SAME: ptr [[A:%.*]], ptr [[B:%.*]]) #[[ATTR0]] { +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr inttoptr (i64 add (i64 ptrtoint (ptr @__msan_param_tls to i64), i64 8) to ptr), align 8 +; CHECK-NEXT: call void @llvm.donothing() +; CHECK-NEXT: [[TMP2:%.*]] = load , ptr [[A]], align 8 +; CHECK-NEXT: [[TMP3:%.*]] = ptrtoint ptr [[A]] to i64 +; CHECK-NEXT: [[TMP4:%.*]] = xor i64 [[TMP3]], 87960930222080 +; CHECK-NEXT: [[TMP5:%.*]] = inttoptr i64 [[TMP4]] to ptr +; CHECK-NEXT: [[_MSLD:%.*]] = load , ptr [[TMP5]], align 8 +; CHECK-NEXT: store i64 [[TMP1]], ptr @__msan_param_tls, align 8 +; CHECK-NEXT: [[TMP6:%.*]] = call i32 @llvm.vector.reduce.or.nxv2i32( [[_MSLD]]) +; CHECK-NEXT: [[_MSCMP:%.*]] = icmp ne i32 [[TMP6]], 0 +; CHECK-NEXT: br i1 [[_MSCMP]], label [[TMP7:%.*]], label [[TMP8:%.*]], !prof [[PROF0:![0-9]+]] +; CHECK: 7: +; CHECK-NEXT: call void @__msan_warning_noreturn() #[[ATTR4:[0-9]+]] +; CHECK-NEXT: unreachable +; CHECK: 8: +; CHECK-NEXT: call void @fn_param( [[TMP2]], ptr [[B]]) +; CHECK-NEXT: ret void +; + %1 = load , ptr %a + call void @fn_param( %1, ptr %b) + ret void +} +;. +; CHECK: [[PROF0]] = !{!"branch_weights", i32 1, i32 1048575} +;. -- GitLab From 176ab5e9de540f4abcae4a232541f8493de11fc6 Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Fri, 26 Apr 2024 15:50:44 -0700 Subject: [PATCH 107/301] [llvm-lto2] Simplify SymbolResolutions loop and avoid expensive std::string copy. NFC --- llvm/tools/llvm-lto2/llvm-lto2.cpp | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/llvm/tools/llvm-lto2/llvm-lto2.cpp b/llvm/tools/llvm-lto2/llvm-lto2.cpp index faed9ff9939b..5dd961a603c9 100644 --- a/llvm/tools/llvm-lto2/llvm-lto2.cpp +++ b/llvm/tools/llvm-lto2/llvm-lto2.cpp @@ -251,10 +251,9 @@ static int run(int argc, char **argv) { // resolutions and apply them in the order observed. std::map, std::list> CommandLineResolutions; - for (std::string R : SymbolResolutions) { - StringRef Rest = R; - StringRef FileName, SymbolName; - std::tie(FileName, Rest) = Rest.split(','); + for (StringRef R : SymbolResolutions) { + StringRef Rest, FileName, SymbolName; + std::tie(FileName, Rest) = R.split(','); if (Rest.empty()) { llvm::errs() << "invalid resolution: " << R << '\n'; return 1; -- GitLab From 5569c219d35c78ad60aea127a06a51e202ae5b6f Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 26 Apr 2024 15:52:05 -0700 Subject: [PATCH 108/301] [RISCV] Split RISCVDisassembler::getInstruction into a 16-bit and 32-bit version. (#90254) This reduces nesting of the common 32-bit case and makes it easier to add longer instruction lengths in the future. --- .../RISCV/Disassembler/RISCVDisassembler.cpp | 218 ++++++++++-------- 1 file changed, 119 insertions(+), 99 deletions(-) diff --git a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp index 497283ceea1e..7ca20190731a 100644 --- a/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp +++ b/llvm/lib/Target/RISCV/Disassembler/RISCVDisassembler.cpp @@ -44,6 +44,13 @@ public: private: void addSPOperands(MCInst &MI) const; + + DecodeStatus getInstruction32(MCInst &Instr, uint64_t &Size, + ArrayRef Bytes, uint64_t Address, + raw_ostream &CStream) const; + DecodeStatus getInstruction16(MCInst &Instr, uint64_t &Size, + ArrayRef Bytes, uint64_t Address, + raw_ostream &CStream) const; }; } // end anonymous namespace @@ -502,21 +509,13 @@ void RISCVDisassembler::addSPOperands(MCInst &MI) const { MI.insert(MI.begin() + i, MCOperand::createReg(RISCV::X2)); } -DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, - ArrayRef Bytes, - uint64_t Address, - raw_ostream &CS) const { - // TODO: This will need modification when supporting instruction set - // extensions with instructions > 32-bits (up to 176 bits wide). - uint32_t Insn; - DecodeStatus Result; - #define TRY_TO_DECODE_WITH_ADDITIONAL_OPERATION(FEATURE_CHECKS, DECODER_TABLE, \ DESC, ADDITIONAL_OPERATION) \ do { \ if (FEATURE_CHECKS) { \ LLVM_DEBUG(dbgs() << "Trying " DESC ":\n"); \ - Result = decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \ + DecodeStatus Result = \ + decodeInstruction(DECODER_TABLE, MI, Insn, Address, this, STI); \ if (Result != MCDisassembler::Fail) { \ ADDITIONAL_OPERATION; \ return Result; \ @@ -532,104 +531,111 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, #define TRY_TO_DECODE_FEATURE(FEATURE, DECODER_TABLE, DESC) \ TRY_TO_DECODE(STI.hasFeature(FEATURE), DECODER_TABLE, DESC) - // It's a 32 bit instruction if bit 0 and 1 are 1. - if ((Bytes[0] & 0x3) == 0x3) { - if (Bytes.size() < 4) { - Size = 0; - return MCDisassembler::Fail; - } - Size = 4; - - Insn = support::endian::read32le(Bytes.data()); - - TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) && - !STI.hasFeature(RISCV::Feature64Bit), - DecoderTableRV32Zdinx32, - "RV32Zdinx table (Double in Integer and rv32)"); - TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) && - !STI.hasFeature(RISCV::Feature64Bit), - DecoderTableRV32Zacas32, - "RV32Zacas table (Compare-And-Swap and rv32)"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32, - "RVZfinx table (Float in Integer)"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps, - DecoderTableXVentana32, "Ventana custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32, - "XTHeadBa custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32, - "XTHeadBb custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32, - "XTHeadBs custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov, - DecoderTableXTHeadCondMov32, - "XTHeadCondMov custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32, - "XTHeadCmo custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx, - DecoderTableXTHeadFMemIdx32, - "XTHeadFMemIdx custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32, - "XTHeadMac custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx, - DecoderTableXTHeadMemIdx32, - "XTHeadMemIdx custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair, - DecoderTableXTHeadMemPair32, - "XTHeadMemPair custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync, - DecoderTableXTHeadSync32, - "XTHeadSync custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, DecoderTableXTHeadVdot32, - "XTHeadVdot custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, - "SiFive VCIX custom opcode table"); - TRY_TO_DECODE_FEATURE( - RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32, - "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table"); - TRY_TO_DECODE_FEATURE( - RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32, - "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table"); - TRY_TO_DECODE_FEATURE( - RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32, - "SiFive Matrix Multiplication Instruction opcode table"); - TRY_TO_DECODE_FEATURE( - RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32, - "SiFive FP32-to-int8 Ranged Clip Instructions opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone, - DecoderTableXSiFivecdiscarddlone32, - "SiFive sf.cdiscard.d.l1 custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone, - DecoderTableXSiFivecflushdlone32, - "SiFive sf.cflush.d.l1 custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32, - "SiFive sf.cease custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, - DecoderTableXCVbitmanip32, - "CORE-V Bit Manipulation custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32, - "CORE-V Event load custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32, - "CORE-V MAC custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32, - "CORE-V MEM custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32, - "CORE-V ALU custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32, - "CORE-V SIMD extensions custom opcode table"); - TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32, - "CORE-V Immediate Branching custom opcode table"); - TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); - +DecodeStatus RISCVDisassembler::getInstruction32(MCInst &MI, uint64_t &Size, + ArrayRef Bytes, + uint64_t Address, + raw_ostream &CS) const { + if (Bytes.size() < 4) { + Size = 0; return MCDisassembler::Fail; } + Size = 4; + + uint32_t Insn = support::endian::read32le(Bytes.data()); + + TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZdinx) && + !STI.hasFeature(RISCV::Feature64Bit), + DecoderTableRV32Zdinx32, + "RV32Zdinx table (Double in Integer and rv32)"); + TRY_TO_DECODE(STI.hasFeature(RISCV::FeatureStdExtZacas) && + !STI.hasFeature(RISCV::Feature64Bit), + DecoderTableRV32Zacas32, + "RV32Zacas table (Compare-And-Swap and rv32)"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureStdExtZfinx, DecoderTableRVZfinx32, + "RVZfinx table (Float in Integer)"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXVentanaCondOps, + DecoderTableXVentana32, "Ventana custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBa, DecoderTableXTHeadBa32, + "XTHeadBa custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBb, DecoderTableXTHeadBb32, + "XTHeadBb custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadBs, DecoderTableXTHeadBs32, + "XTHeadBs custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCondMov, + DecoderTableXTHeadCondMov32, + "XTHeadCondMov custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadCmo, DecoderTableXTHeadCmo32, + "XTHeadCmo custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadFMemIdx, + DecoderTableXTHeadFMemIdx32, + "XTHeadFMemIdx custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMac, DecoderTableXTHeadMac32, + "XTHeadMac custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemIdx, + DecoderTableXTHeadMemIdx32, + "XTHeadMemIdx custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadMemPair, + DecoderTableXTHeadMemPair32, + "XTHeadMemPair custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadSync, + DecoderTableXTHeadSync32, + "XTHeadSync custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXTHeadVdot, + DecoderTableXTHeadVdot32, + "XTHeadVdot custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfvcp, DecoderTableXSfvcp32, + "SiFive VCIX custom opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvqmaccdod, DecoderTableXSfvqmaccdod32, + "SiFive Matrix Multiplication (2x8 and 8x2) Instruction opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvqmaccqoq, DecoderTableXSfvqmaccqoq32, + "SiFive Matrix Multiplication (4x8 and 8x4) Instruction opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvfwmaccqqq, DecoderTableXSfvfwmaccqqq32, + "SiFive Matrix Multiplication Instruction opcode table"); + TRY_TO_DECODE_FEATURE( + RISCV::FeatureVendorXSfvfnrclipxfqf, DecoderTableXSfvfnrclipxfqf32, + "SiFive FP32-to-int8 Ranged Clip Instructions opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecdiscarddlone, + DecoderTableXSiFivecdiscarddlone32, + "SiFive sf.cdiscard.d.l1 custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSiFivecflushdlone, + DecoderTableXSiFivecflushdlone32, + "SiFive sf.cflush.d.l1 custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXSfcease, DecoderTableXSfcease32, + "SiFive sf.cease custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbitmanip, + DecoderTableXCVbitmanip32, + "CORE-V Bit Manipulation custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVelw, DecoderTableXCVelw32, + "CORE-V Event load custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmac, DecoderTableXCVmac32, + "CORE-V MAC custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVmem, DecoderTableXCVmem32, + "CORE-V MEM custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCValu, DecoderTableXCValu32, + "CORE-V ALU custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVsimd, DecoderTableXCVsimd32, + "CORE-V SIMD extensions custom opcode table"); + TRY_TO_DECODE_FEATURE(RISCV::FeatureVendorXCVbi, DecoderTableXCVbi32, + "CORE-V Immediate Branching custom opcode table"); + TRY_TO_DECODE(true, DecoderTable32, "RISCV32 table"); + return MCDisassembler::Fail; +} + +DecodeStatus RISCVDisassembler::getInstruction16(MCInst &MI, uint64_t &Size, + ArrayRef Bytes, + uint64_t Address, + raw_ostream &CS) const { if (Bytes.size() < 2) { Size = 0; return MCDisassembler::Fail; } Size = 2; - Insn = support::endian::read16le(Bytes.data()); + uint32_t Insn = support::endian::read16le(Bytes.data()); TRY_TO_DECODE_AND_ADD_SP(!STI.hasFeature(RISCV::Feature64Bit), DecoderTableRISCV32Only_16, "RISCV32Only_16 table (16-bit Instruction)"); @@ -645,3 +651,17 @@ DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, return MCDisassembler::Fail; } + +DecodeStatus RISCVDisassembler::getInstruction(MCInst &MI, uint64_t &Size, + ArrayRef Bytes, + uint64_t Address, + raw_ostream &CS) const { + // TODO: This will need modification when supporting instruction set + // extensions with instructions > 32-bits (up to 176 bits wide). + + // It's a 32 bit instruction if bit 0 and 1 are 1. + if ((Bytes[0] & 0x3) == 0x3) + return getInstruction32(MI, Size, Bytes, Address, CS); + + return getInstruction16(MI, Size, Bytes, Address, CS); +} -- GitLab From ad2816e7340be71c93e60b9bb58e107fe1b76e4d Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Fri, 26 Apr 2024 23:10:20 +0000 Subject: [PATCH 109/301] [llvm-exegesis] Use const reference for range variable In the SubprocessMemory destructor, I was using a normal std::string to hold the name of the current shared memory name, but a const reference works just as well in this situation while having better performance characteristics. Fixes #90289 --- llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp b/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp index cda044050502..89d7b197079e 100644 --- a/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp +++ b/llvm/tools/llvm-exegesis/lib/SubprocessMemory.cpp @@ -143,7 +143,7 @@ Expected SubprocessMemory::setupAuxiliaryMemoryInSubprocess( } SubprocessMemory::~SubprocessMemory() { - for (std::string SharedMemoryName : SharedMemoryNames) { + for (const std::string &SharedMemoryName : SharedMemoryNames) { if (shm_unlink(SharedMemoryName.c_str()) != 0) { errs() << "Failed to unlink shared memory section: " << strerror(errno) << "\n"; -- GitLab From 3ec858bc5d45ee22ca99febd38e1ba188f71022c Mon Sep 17 00:00:00 2001 From: Maksim Panchenko Date: Fri, 26 Apr 2024 16:29:42 -0700 Subject: [PATCH 110/301] [BOLT] Refactor patchELFPHDRTable() (#90290) Mostly NFC accept for one assertion that was converted into an error. --- bolt/lib/Rewrite/RewriteInstance.cpp | 105 ++++++++++++++------------- 1 file changed, 56 insertions(+), 49 deletions(-) diff --git a/bolt/lib/Rewrite/RewriteInstance.cpp b/bolt/lib/Rewrite/RewriteInstance.cpp index 409835537fde..065260936e70 100644 --- a/bolt/lib/Rewrite/RewriteInstance.cpp +++ b/bolt/lib/Rewrite/RewriteInstance.cpp @@ -3926,11 +3926,6 @@ void RewriteInstance::patchELFPHDRTable() { OS.seek(PHDRTableOffset); - bool ModdedGnuStack = false; - (void)ModdedGnuStack; - bool AddedSegment = false; - (void)AddedSegment; - auto createNewTextPhdr = [&]() { ELF64LEPhdrTy NewPhdr; NewPhdr.p_type = ELF::PT_LOAD; @@ -3946,38 +3941,51 @@ void RewriteInstance::patchELFPHDRTable() { NewPhdr.p_filesz = NewTextSegmentSize; NewPhdr.p_memsz = NewTextSegmentSize; NewPhdr.p_flags = ELF::PF_X | ELF::PF_R; - // FIXME: Currently instrumentation is experimental and the runtime data - // is emitted with code, thus everything needs to be writable - if (opts::Instrument) + if (opts::Instrument) { + // FIXME: Currently instrumentation is experimental and the runtime data + // is emitted with code, thus everything needs to be writable. NewPhdr.p_flags |= ELF::PF_W; + } NewPhdr.p_align = BC->PageAlign; return NewPhdr; }; - auto createNewWritableSectionsPhdr = [&]() { - ELF64LEPhdrTy NewPhdr; - NewPhdr.p_type = ELF::PT_LOAD; - NewPhdr.p_offset = getFileOffsetForAddress(NewWritableSegmentAddress); - NewPhdr.p_vaddr = NewWritableSegmentAddress; - NewPhdr.p_paddr = NewWritableSegmentAddress; - NewPhdr.p_filesz = NewWritableSegmentSize; - NewPhdr.p_memsz = NewWritableSegmentSize; - NewPhdr.p_align = BC->RegularPageSize; - NewPhdr.p_flags = ELF::PF_R | ELF::PF_W; - return NewPhdr; + auto writeNewSegmentPhdrs = [&]() { + ELF64LE::Phdr NewTextPhdr = createNewTextPhdr(); + OS.write(reinterpret_cast(&NewTextPhdr), sizeof(NewTextPhdr)); + + if (NewWritableSegmentSize) { + ELF64LEPhdrTy NewPhdr; + NewPhdr.p_type = ELF::PT_LOAD; + NewPhdr.p_offset = getFileOffsetForAddress(NewWritableSegmentAddress); + NewPhdr.p_vaddr = NewWritableSegmentAddress; + NewPhdr.p_paddr = NewWritableSegmentAddress; + NewPhdr.p_filesz = NewWritableSegmentSize; + NewPhdr.p_memsz = NewWritableSegmentSize; + NewPhdr.p_align = BC->RegularPageSize; + NewPhdr.p_flags = ELF::PF_R | ELF::PF_W; + OS.write(reinterpret_cast(&NewPhdr), sizeof(NewPhdr)); + } }; + bool ModdedGnuStack = false; + bool AddedSegment = false; + // Copy existing program headers with modifications. for (const ELF64LE::Phdr &Phdr : cantFail(Obj.program_headers())) { ELF64LE::Phdr NewPhdr = Phdr; - if (PHDRTableAddress && Phdr.p_type == ELF::PT_PHDR) { - NewPhdr.p_offset = PHDRTableOffset; - NewPhdr.p_vaddr = PHDRTableAddress; - NewPhdr.p_paddr = PHDRTableAddress; - NewPhdr.p_filesz = sizeof(NewPhdr) * Phnum; - NewPhdr.p_memsz = sizeof(NewPhdr) * Phnum; - } else if (Phdr.p_type == ELF::PT_GNU_EH_FRAME) { + switch (Phdr.p_type) { + case ELF::PT_PHDR: + if (PHDRTableAddress) { + NewPhdr.p_offset = PHDRTableOffset; + NewPhdr.p_vaddr = PHDRTableAddress; + NewPhdr.p_paddr = PHDRTableAddress; + NewPhdr.p_filesz = sizeof(NewPhdr) * Phnum; + NewPhdr.p_memsz = sizeof(NewPhdr) * Phnum; + } + break; + case ELF::PT_GNU_EH_FRAME: { ErrorOr EHFrameHdrSec = BC->getUniqueSectionByName( getNewSecPrefix() + getEHFrameHdrSectionName()); if (EHFrameHdrSec && EHFrameHdrSec->isAllocatable() && @@ -3988,37 +3996,36 @@ void RewriteInstance::patchELFPHDRTable() { NewPhdr.p_filesz = EHFrameHdrSec->getOutputSize(); NewPhdr.p_memsz = EHFrameHdrSec->getOutputSize(); } - } else if (opts::UseGnuStack && Phdr.p_type == ELF::PT_GNU_STACK) { - NewPhdr = createNewTextPhdr(); - ModdedGnuStack = true; - } else if (!opts::UseGnuStack && Phdr.p_type == ELF::PT_DYNAMIC) { - // Insert the new header before DYNAMIC. - ELF64LE::Phdr NewTextPhdr = createNewTextPhdr(); - OS.write(reinterpret_cast(&NewTextPhdr), - sizeof(NewTextPhdr)); - if (NewWritableSegmentSize) { - ELF64LEPhdrTy NewWritablePhdr = createNewWritableSectionsPhdr(); - OS.write(reinterpret_cast(&NewWritablePhdr), - sizeof(NewWritablePhdr)); + break; + } + case ELF::PT_GNU_STACK: + if (opts::UseGnuStack) { + // Overwrite the header with the new text segment header. + NewPhdr = createNewTextPhdr(); + ModdedGnuStack = true; + } + break; + case ELF::PT_DYNAMIC: + if (!opts::UseGnuStack) { + // Insert new headers before DYNAMIC. + writeNewSegmentPhdrs(); + AddedSegment = true; } - AddedSegment = true; + break; } OS.write(reinterpret_cast(&NewPhdr), sizeof(NewPhdr)); } if (!opts::UseGnuStack && !AddedSegment) { - // Append the new header to the end of the table. - ELF64LE::Phdr NewTextPhdr = createNewTextPhdr(); - OS.write(reinterpret_cast(&NewTextPhdr), sizeof(NewTextPhdr)); - if (NewWritableSegmentSize) { - ELF64LEPhdrTy NewWritablePhdr = createNewWritableSectionsPhdr(); - OS.write(reinterpret_cast(&NewWritablePhdr), - sizeof(NewWritablePhdr)); - } + // Append new headers to the end of the table. + writeNewSegmentPhdrs(); } - assert((!opts::UseGnuStack || ModdedGnuStack) && - "could not find GNU_STACK program header to modify"); + if (opts::UseGnuStack && !ModdedGnuStack) { + BC->errs() + << "BOLT-ERROR: could not find PT_GNU_STACK program header to modify\n"; + exit(1); + } } namespace { -- GitLab From 2e5035aeed4a9d33ab179f6e90c68fa70588c013 Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Fri, 26 Apr 2024 17:14:43 -0700 Subject: [PATCH 111/301] Revert "[clang] Enable sized deallocation by default in C++14 onwards (#83774)" (#90299) https://lab.llvm.org/buildbot/#/builders/168/builds/20063 (should be fixed with #90292) More details in #83774 This reverts commit cf5a8b489464d09dfdd7a48ce7c8b41d3c9bf819. --- .../clangd/unittests/FindTargetTests.cpp | 4 +- .../checkers/misc/new-delete-overloads.cpp | 10 + clang/docs/ReleaseNotes.rst | 5 - clang/include/clang/Driver/Options.td | 8 +- clang/lib/Driver/ToolChains/Clang.cpp | 13 +- clang/lib/Driver/ToolChains/Darwin.cpp | 58 +---- clang/lib/Driver/ToolChains/Darwin.h | 4 - clang/lib/Driver/ToolChains/ZOS.cpp | 6 - clang/test/AST/ast-dump-expr-json.cpp | 2 +- clang/test/AST/ast-dump-expr.cpp | 2 +- clang/test/AST/ast-dump-stmt-json.cpp | 244 +----------------- clang/test/Analysis/cxxnewexpr-callback.cpp | 4 +- .../basic.stc.dynamic.deallocation/p2.cpp | 2 +- clang/test/CXX/drs/cwg292.cpp | 17 +- .../test/CXX/expr/expr.unary/expr.new/p14.cpp | 2 +- .../CodeGenCXX/cxx1y-sized-deallocation.cpp | 10 +- .../CodeGenCXX/cxx1z-aligned-allocation.cpp | 6 +- .../CodeGenCXX/cxx2a-destroying-delete.cpp | 4 +- clang/test/CodeGenCXX/delete-two-arg.cpp | 4 +- clang/test/CodeGenCXX/delete.cpp | 12 +- clang/test/CodeGenCXX/dllimport.cpp | 4 +- clang/test/CodeGenCXX/new.cpp | 6 +- .../coro-aligned-alloc-2.cpp | 2 + .../CodeGenCoroutines/coro-aligned-alloc.cpp | 6 +- clang/test/CodeGenCoroutines/coro-alloc.cpp | 6 +- clang/test/CodeGenCoroutines/coro-cleanup.cpp | 6 +- clang/test/CodeGenCoroutines/coro-dealloc.cpp | 2 + clang/test/CodeGenCoroutines/coro-gro.cpp | 3 +- clang/test/CodeGenCoroutines/pr56919.cpp | 9 +- clang/test/Lexer/cxx-features.cpp | 20 +- clang/test/PCH/cxx1z-aligned-alloc.cpp | 10 +- clang/test/SemaCXX/MicrosoftExtensions.cpp | 8 +- .../SemaCXX/builtin-operator-new-delete.cpp | 2 +- .../test/SemaCXX/cxx1y-sized-deallocation.cpp | 2 +- .../unavailable_aligned_allocation.cpp | 15 +- clang/tools/clang-repl/CMakeLists.txt | 59 ----- clang/unittests/Interpreter/CMakeLists.txt | 59 ----- .../StaticAnalyzer/CallEventTest.cpp | 2 +- clang/www/cxx_status.html | 11 +- .../support.dynamic/libcpp_deallocate.sh.cpp | 3 - .../sized_delete_array14.pass.cpp | 8 +- .../new.delete.single/sized_delete14.pass.cpp | 8 +- 42 files changed, 113 insertions(+), 555 deletions(-) diff --git a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp index 88aae2729904..799a549ff081 100644 --- a/clang-tools-extra/clangd/unittests/FindTargetTests.cpp +++ b/clang-tools-extra/clangd/unittests/FindTargetTests.cpp @@ -839,9 +839,7 @@ TEST_F(TargetDeclTest, OverloadExpr) { [[delete]] x; } )cpp"; - // Sized deallocation is enabled by default in C++14 onwards. - EXPECT_DECLS("CXXDeleteExpr", - "void operator delete(void *, unsigned long) noexcept"); + EXPECT_DECLS("CXXDeleteExpr", "void operator delete(void *) noexcept"); } TEST_F(TargetDeclTest, DependentExprs) { diff --git a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp index f86fe8a4c5b1..78f021144b2e 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp +++ b/clang-tools-extra/test/clang-tidy/checkers/misc/new-delete-overloads.cpp @@ -12,6 +12,16 @@ struct S { // CHECK-MESSAGES: :[[@LINE+1]]:7: warning: declaration of 'operator new' has no matching declaration of 'operator delete' at the same scope void *operator new(size_t size) noexcept(false); +struct T { + // Sized deallocations are not enabled by default, and so this new/delete pair + // does not match. However, we expect only one warning, for the new, because + // the operator delete is a placement delete and we do not warn on mismatching + // placement operations. + // CHECK-MESSAGES: :[[@LINE+1]]:9: warning: declaration of 'operator new' has no matching declaration of 'operator delete' at the same scope + void *operator new(size_t size) noexcept; + void operator delete(void *ptr, size_t) noexcept; // ok only if sized deallocation is enabled +}; + struct U { void *operator new(size_t size) noexcept; void operator delete(void *ptr) noexcept; diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 5d4d152b2eb5..a1390d6536b2 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -90,11 +90,6 @@ C++ Language Changes -------------------- - Implemented ``_BitInt`` literal suffixes ``__wb`` or ``__WB`` as a Clang extension with ``unsigned`` modifiers also allowed. (#GH85223). -C++14 Feature Support -^^^^^^^^^^^^^^^^^^^^^ -- Sized deallocation is enabled by default in C++14 onwards. The user may specify - ``-fno-sized-deallocation`` to disable it if there are some regressions. - C++17 Feature Support ^^^^^^^^^^^^^^^^^^^^^ - Clang now exposes ``__GCC_DESTRUCTIVE_SIZE`` and ``__GCC_CONSTRUCTIVE_SIZE`` diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 41f713a47c2e..086aedefc118 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -603,7 +603,6 @@ class MarshallingInfoVisibility // Key paths that are constant during parsing of options with the same key path prefix. defvar cplusplus = LangOpts<"CPlusPlus">; defvar cpp11 = LangOpts<"CPlusPlus11">; -defvar cpp14 = LangOpts<"CPlusPlus14">; defvar cpp17 = LangOpts<"CPlusPlus17">; defvar cpp20 = LangOpts<"CPlusPlus20">; defvar c99 = LangOpts<"C99">; @@ -3371,9 +3370,10 @@ defm relaxed_template_template_args : BoolFOption<"relaxed-template-template-arg "Enable C++17 relaxed template template argument matching">, NegFlag>; defm sized_deallocation : BoolFOption<"sized-deallocation", - LangOpts<"SizedDeallocation">, Default, - PosFlag, - NegFlag, BothFlags<[], [ClangOption, CC1Option]>>; + LangOpts<"SizedDeallocation">, DefaultFalse, + PosFlag, + NegFlag>; defm aligned_allocation : BoolFOption<"aligned-allocation", LangOpts<"AlignedAllocation">, Default, PosFlag, diff --git a/clang/lib/Driver/ToolChains/Clang.cpp b/clang/lib/Driver/ToolChains/Clang.cpp index f4fe7422cba6..651a2b5aac36 100644 --- a/clang/lib/Driver/ToolChains/Clang.cpp +++ b/clang/lib/Driver/ToolChains/Clang.cpp @@ -7262,15 +7262,10 @@ void Clang::ConstructJob(Compilation &C, const JobAction &JA, Args.addOptInFlag(CmdArgs, options::OPT_frelaxed_template_template_args, options::OPT_fno_relaxed_template_template_args); - // -fsized-deallocation is on by default in C++14 onwards and otherwise off - // by default. - if (Arg *A = Args.getLastArg(options::OPT_fsized_deallocation, - options::OPT_fno_sized_deallocation)) { - if (A->getOption().matches(options::OPT_fno_sized_deallocation)) - CmdArgs.push_back("-fno-sized-deallocation"); - else - CmdArgs.push_back("-fsized-deallocation"); - } + // -fsized-deallocation is off by default, as it is an ABI-breaking change for + // most platforms. + Args.addOptInFlag(CmdArgs, options::OPT_fsized_deallocation, + options::OPT_fno_sized_deallocation); // -faligned-allocation is on by default in C++17 onwards and otherwise off // by default. diff --git a/clang/lib/Driver/ToolChains/Darwin.cpp b/clang/lib/Driver/ToolChains/Darwin.cpp index 593b403a1e3f..caf6c4a444fd 100644 --- a/clang/lib/Driver/ToolChains/Darwin.cpp +++ b/clang/lib/Driver/ToolChains/Darwin.cpp @@ -2912,54 +2912,9 @@ static bool sdkSupportsBuiltinModules(const Darwin::DarwinPlatformKind &TargetPl } } -static inline llvm::VersionTuple -sizedDeallocMinVersion(llvm::Triple::OSType OS) { - switch (OS) { - default: - break; - case llvm::Triple::Darwin: - case llvm::Triple::MacOSX: // Earliest supporting version is 10.12. - return llvm::VersionTuple(10U, 12U); - case llvm::Triple::IOS: - case llvm::Triple::TvOS: // Earliest supporting version is 10.0.0. - return llvm::VersionTuple(10U); - case llvm::Triple::WatchOS: // Earliest supporting version is 3.0.0. - return llvm::VersionTuple(3U); - } - - llvm_unreachable("Unexpected OS"); -} - -bool Darwin::isSizedDeallocationUnavailable() const { - llvm::Triple::OSType OS; - - if (isTargetMacCatalyst()) - return TargetVersion < sizedDeallocMinVersion(llvm::Triple::MacOSX); - switch (TargetPlatform) { - case MacOS: // Earlier than 10.12. - OS = llvm::Triple::MacOSX; - break; - case IPhoneOS: - OS = llvm::Triple::IOS; - break; - case TvOS: // Earlier than 10.0. - OS = llvm::Triple::TvOS; - break; - case WatchOS: // Earlier than 3.0. - OS = llvm::Triple::WatchOS; - break; - case DriverKit: - case XROS: - // Always available. - return false; - } - - return TargetVersion < sizedDeallocMinVersion(OS); -} - -void Darwin::addClangTargetOptions( - const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, - Action::OffloadKind DeviceOffloadKind) const { +void Darwin::addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, + llvm::opt::ArgStringList &CC1Args, + Action::OffloadKind DeviceOffloadKind) const { // Pass "-faligned-alloc-unavailable" only when the user hasn't manually // enabled or disabled aligned allocations. if (!DriverArgs.hasArgNoClaim(options::OPT_faligned_allocation, @@ -2967,13 +2922,6 @@ void Darwin::addClangTargetOptions( isAlignedAllocationUnavailable()) CC1Args.push_back("-faligned-alloc-unavailable"); - // Pass "-fno-sized-deallocation" only when the user hasn't manually enabled - // or disabled sized deallocations. - if (!DriverArgs.hasArgNoClaim(options::OPT_fsized_deallocation, - options::OPT_fno_sized_deallocation) && - isSizedDeallocationUnavailable()) - CC1Args.push_back("-fno-sized-deallocation"); - addClangCC1ASTargetOptions(DriverArgs, CC1Args); // Enable compatibility mode for NSItemProviderCompletionHandler in diff --git a/clang/lib/Driver/ToolChains/Darwin.h b/clang/lib/Driver/ToolChains/Darwin.h index b45279ecedeb..10d4b69e5d5f 100644 --- a/clang/lib/Driver/ToolChains/Darwin.h +++ b/clang/lib/Driver/ToolChains/Darwin.h @@ -511,10 +511,6 @@ protected: /// targeting. bool isAlignedAllocationUnavailable() const; - /// Return true if c++14 sized deallocation functions are not implemented in - /// the c++ standard library of the deployment target we are targeting. - bool isSizedDeallocationUnavailable() const; - void addClangTargetOptions(const llvm::opt::ArgList &DriverArgs, llvm::opt::ArgStringList &CC1Args, Action::OffloadKind DeviceOffloadKind) const override; diff --git a/clang/lib/Driver/ToolChains/ZOS.cpp b/clang/lib/Driver/ToolChains/ZOS.cpp index 074e0556ecd2..d5fc7b8ef562 100644 --- a/clang/lib/Driver/ToolChains/ZOS.cpp +++ b/clang/lib/Driver/ToolChains/ZOS.cpp @@ -36,12 +36,6 @@ void ZOS::addClangTargetOptions(const ArgList &DriverArgs, if (!DriverArgs.hasArgNoClaim(options::OPT_faligned_allocation, options::OPT_fno_aligned_allocation)) CC1Args.push_back("-faligned-alloc-unavailable"); - - // Pass "-fno-sized-deallocation" only when the user hasn't manually enabled - // or disabled sized deallocations. - if (!DriverArgs.hasArgNoClaim(options::OPT_fsized_deallocation, - options::OPT_fno_sized_deallocation)) - CC1Args.push_back("-fno-sized-deallocation"); } void zos::Assembler::ConstructJob(Compilation &C, const JobAction &JA, diff --git a/clang/test/AST/ast-dump-expr-json.cpp b/clang/test/AST/ast-dump-expr-json.cpp index bdd5ea19e418..0fb07b0b434c 100644 --- a/clang/test/AST/ast-dump-expr-json.cpp +++ b/clang/test/AST/ast-dump-expr-json.cpp @@ -2333,7 +2333,7 @@ void TestNonADLCall3() { // CHECK-NEXT: "kind": "FunctionDecl", // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" +// CHECK-NEXT: "qualType": "void (void *) noexcept" // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ diff --git a/clang/test/AST/ast-dump-expr.cpp b/clang/test/AST/ast-dump-expr.cpp index de88f29bc4b0..69e65e22d61d 100644 --- a/clang/test/AST/ast-dump-expr.cpp +++ b/clang/test/AST/ast-dump-expr.cpp @@ -164,7 +164,7 @@ void UnaryExpressions(int *p) { // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue ParmVar 0x{{[^ ]*}} 'p' 'int *' ::delete p; - // CHECK: CXXDeleteExpr 0x{{[^ ]*}} 'void' global Function 0x{{[^ ]*}} 'operator delete' 'void (void *, unsigned long) noexcept' + // CHECK: CXXDeleteExpr 0x{{[^ ]*}} 'void' global Function 0x{{[^ ]*}} 'operator delete' 'void (void *) noexcept' // CHECK-NEXT: ImplicitCastExpr // CHECK-NEXT: DeclRefExpr 0x{{[^ ]*}} 'int *' lvalue ParmVar 0x{{[^ ]*}} 'p' 'int *' diff --git a/clang/test/AST/ast-dump-stmt-json.cpp b/clang/test/AST/ast-dump-stmt-json.cpp index a473d17da942..667a12a01202 100644 --- a/clang/test/AST/ast-dump-stmt-json.cpp +++ b/clang/test/AST/ast-dump-stmt-json.cpp @@ -994,7 +994,7 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "FunctionDecl", // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" +// CHECK-NEXT: "qualType": "void (void *) noexcept" // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ @@ -1369,7 +1369,7 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "kind": "FunctionDecl", // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" +// CHECK-NEXT: "qualType": "void (void *) noexcept" // CHECK-NEXT: } // CHECK-NEXT: }, // CHECK-NEXT: "inner": [ @@ -1722,6 +1722,7 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: "end": {} // CHECK-NEXT: }, // CHECK-NEXT: "isImplicit": true, +// CHECK-NEXT: "isUsed": true, // CHECK-NEXT: "name": "operator delete", // CHECK-NEXT: "mangledName": "_ZdlPv", // CHECK-NEXT: "type": { @@ -1809,126 +1810,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } -// CHECK-NOT: {{^}}Dumping -// CHECK: "kind": "FunctionDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "isUsed": true, -// CHECK-NEXT: "name": "operator delete", -// CHECK-NEXT: "mangledName": "_ZdlPvm", -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" -// CHECK-NEXT: }, -// CHECK-NEXT: "inner": [ -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void *" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "unsigned long" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "VisibilityAttr", -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "implicit": true, -// CHECK-NEXT: "visibility": "default" -// CHECK-NEXT: } -// CHECK-NEXT: ] -// CHECK-NEXT: } - -// CHECK-NOT: {{^}}Dumping -// CHECK: "kind": "FunctionDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "name": "operator delete", -// CHECK-NEXT: "mangledName": "_ZdlPvmSt11align_val_t", -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *, unsigned long, std::align_val_t) noexcept" -// CHECK-NEXT: }, -// CHECK-NEXT: "inner": [ -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void *" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "unsigned long" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "std::align_val_t" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "VisibilityAttr", -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "implicit": true, -// CHECK-NEXT: "visibility": "default" -// CHECK-NEXT: } -// CHECK-NEXT: ] -// CHECK-NEXT: } - // CHECK-NOT: {{^}}Dumping // CHECK: "kind": "FunctionDecl", // CHECK-NEXT: "loc": {}, @@ -2025,125 +1906,6 @@ void TestDependentGenericSelectionExpr(Ty T) { // CHECK-NEXT: } -// CHECK-NOT: {{^}}Dumping -// CHECK: "kind": "FunctionDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "name": "operator delete[]", -// CHECK-NEXT: "mangledName": "_ZdaPvm", -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *, unsigned long) noexcept" -// CHECK-NEXT: }, -// CHECK-NEXT: "inner": [ -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void *" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "unsigned long" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "VisibilityAttr", -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "implicit": true, -// CHECK-NEXT: "visibility": "default" -// CHECK-NEXT: } -// CHECK-NEXT: ] -// CHECK-NEXT: } - -// CHECK-NOT: {{^}}Dumping -// CHECK: "kind": "FunctionDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "name": "operator delete[]", -// CHECK-NEXT: "mangledName": "_ZdaPvmSt11align_val_t", -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void (void *, unsigned long, std::align_val_t) noexcept" -// CHECK-NEXT: }, -// CHECK-NEXT: "inner": [ -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "void *" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "unsigned long" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "ParmVarDecl", -// CHECK-NEXT: "loc": {}, -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "isImplicit": true, -// CHECK-NEXT: "type": { -// CHECK-NEXT: "qualType": "std::align_val_t" -// CHECK-NEXT: } -// CHECK-NEXT: }, -// CHECK-NEXT: { -// CHECK-NEXT: "id": "0x{{.*}}", -// CHECK-NEXT: "kind": "VisibilityAttr", -// CHECK-NEXT: "range": { -// CHECK-NEXT: "begin": {}, -// CHECK-NEXT: "end": {} -// CHECK-NEXT: }, -// CHECK-NEXT: "implicit": true, -// CHECK-NEXT: "visibility": "default" -// CHECK-NEXT: } -// CHECK-NEXT: ] -// CHECK-NEXT: } - // CHECK-NOT: {{^}}Dumping // CHECK: "kind": "FunctionTemplateDecl", // CHECK-NEXT: "loc": { diff --git a/clang/test/Analysis/cxxnewexpr-callback.cpp b/clang/test/Analysis/cxxnewexpr-callback.cpp index 7df58cfa9ca2..fe7a9fffad93 100644 --- a/clang/test/Analysis/cxxnewexpr-callback.cpp +++ b/clang/test/Analysis/cxxnewexpr-callback.cpp @@ -9,7 +9,7 @@ void free(void *); } // namespace std void *operator new(size_t size) { return std::malloc(size); } -void operator delete(void *ptr, size_t size) { std::free(ptr); } +void operator delete(void *ptr) { std::free(ptr); } struct S { S() {} @@ -49,7 +49,7 @@ void test() { // CHECK-NEXT: PostCall (operator delete) } -void operator delete(void *ptr, size_t size) { +void operator delete(void *ptr) { std::free(ptr); // CHECK-NO-INLINE-NEXT: PreCall (std::free) // CHECK-NO-INLINE-NEXT: PostCall (std::free) diff --git a/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp b/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp index 706549f56c52..9e3210c6650f 100644 --- a/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp +++ b/clang/test/CXX/basic/basic.stc/basic.stc.dynamic/basic.stc.dynamic.deallocation/p2.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1z -fexceptions -verify %s +// RUN: %clang_cc1 -std=c++1z -fsized-deallocation -fexceptions -verify %s using size_t = decltype(sizeof(0)); diff --git a/clang/test/CXX/drs/cwg292.cpp b/clang/test/CXX/drs/cwg292.cpp index a7bcbe6f5051..b05d3b92d627 100644 --- a/clang/test/CXX/drs/cwg292.cpp +++ b/clang/test/CXX/drs/cwg292.cpp @@ -1,10 +1,10 @@ -// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,CXX98-11 -// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,CXX98-11 -// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 -// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 -// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 -// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 -// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK,SINCE-CXX14 +// RUN: %clang_cc1 -std=c++98 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++11 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++14 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -disable-llvm-passes -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK namespace cwg292 { // cwg292: 2.9 @@ -23,8 +23,7 @@ void f() { // CHECK: invoke {{.*}} i32 @cwg292::g()() // CHECK-NEXT: to {{.*}} unwind label %lpad // CHECK-LABEL: lpad: -// CXX98-11: call void @operator delete(void*)(ptr {{.*}} %[[CALL]]) -// SINCE-CXX14: call void @operator delete(void*, unsigned long)(ptr {{.*}} %[[CALL]], i64 noundef 1) +// CHECK: call void @operator delete(void*)(ptr {{.*}} %[[CALL]]) // CHECK-LABEL: eh.resume: // CHECK-LABEL: } diff --git a/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp b/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp index d0b24c8fe47b..6537cdcfeafa 100644 --- a/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp +++ b/clang/test/CXX/expr/expr.unary/expr.new/p14.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1z -fexceptions %s -verify +// RUN: %clang_cc1 -std=c++1z -fsized-deallocation -fexceptions %s -verify using size_t = decltype(sizeof(0)); namespace std { enum class align_val_t : size_t {}; } diff --git a/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp b/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp index 55913aff9c19..4e1565725152 100644 --- a/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp +++ b/clang/test/CodeGenCXX/cxx1y-sized-deallocation.cpp @@ -1,12 +1,12 @@ // Check that delete exprs call the sized deallocation function if -// -fsized-deallocation is passed in C++11 or std >= C++14. +// -fsized-deallocation is passed in both C++11 and C++14. // RUN: %clang_cc1 -std=c++11 -fsized-deallocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++14 %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s +// RUN: %clang_cc1 -std=c++14 -fsized-deallocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// Check that we don't used sized deallocation with -fno-sized-deallocation or without C++14. +// Check that we don't used sized deallocation without -fsized-deallocation and +// C++14. // RUN: %clang_cc1 -std=c++11 %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s --check-prefix=CHECK-UNSIZED -// RUN: %clang_cc1 -std=c++14 %s -emit-llvm -triple x86_64-linux-gnu -fno-sized-deallocation -o - \ -// RUN: | FileCheck %s --check-prefix=CHECK-UNSIZED +// RUN: %clang_cc1 -std=c++14 %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s --check-prefix=CHECK-UNSIZED // CHECK-UNSIZED-NOT: _ZdlPvm // CHECK-UNSIZED-NOT: _ZdaPvm diff --git a/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp b/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp index 8823bc64a436..ab2e4b3cdbbf 100644 --- a/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp +++ b/clang/test/CodeGenCXX/cxx1z-aligned-allocation.cpp @@ -1,10 +1,10 @@ // Check that delete exprs call aligned (de)allocation functions if // -faligned-allocation is passed in both C++11 and C++14. // RUN: %clang_cc1 -std=c++11 -fexceptions -fsized-deallocation -faligned-allocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++14 -fexceptions -faligned-allocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++1z -fexceptions %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s +// RUN: %clang_cc1 -std=c++14 -fexceptions -fsized-deallocation -faligned-allocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s +// RUN: %clang_cc1 -std=c++1z -fexceptions -fsized-deallocation %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s -// RUN: %clang_cc1 -std=c++1z -fexceptions %s -emit-llvm -triple x86_64-windows-msvc -o - | FileCheck %s --check-prefix=CHECK-MS +// RUN: %clang_cc1 -std=c++1z -fexceptions -fsized-deallocation %s -emit-llvm -triple x86_64-windows-msvc -o - | FileCheck %s --check-prefix=CHECK-MS // Check that we don't used aligned (de)allocation without -faligned-allocation or C++1z. // RUN: %clang_cc1 -std=c++14 -DUNALIGNED -fexceptions %s -emit-llvm -triple x86_64-linux-gnu -o - | FileCheck %s --check-prefix=CHECK-UNALIGNED diff --git a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp index f6f4a2ff735c..20264b67353a 100644 --- a/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp +++ b/clang/test/CodeGenCXX/cxx2a-destroying-delete.cpp @@ -108,10 +108,10 @@ struct J { // CHECK-MSABI-LABEL: define {{.*}}@"?j@@ J *j() { // CHECK-ITANIUM: invoke {{.*}}@_ZN1JC1Ev( - // CHECK-ITANIUM: call {{.*}}@_ZdlPvm( + // CHECK-ITANIUM: call {{.*}}@_ZdlPv( // CHECK-NOT: } // CHECK-MSABI: invoke {{.*}}@"??0J@@Q{{AE|EAA}}@XZ"( - // CHECK-MSABI: call {{.*}}@"??3@YAXP{{E?}}AX{{I|_K}}@Z"( + // CHECK-MSABI: call {{.*}}@"??3@YAXP{{E?}}AX@Z"( return new J; // CHECK: } } diff --git a/clang/test/CodeGenCXX/delete-two-arg.cpp b/clang/test/CodeGenCXX/delete-two-arg.cpp index a0dcd03bc5a9..552634f430a8 100644 --- a/clang/test/CodeGenCXX/delete-two-arg.cpp +++ b/clang/test/CodeGenCXX/delete-two-arg.cpp @@ -43,9 +43,7 @@ namespace test2 { // CHECK-NEXT: br i1 [[T1]], // CHECK: [[T3:%.*]] = getelementptr inbounds i8, ptr [[T0]], i32 -4 // CHECK-NEXT: [[T5:%.*]] = load i32, ptr [[T3]] - // CHECK-NEXT: [[T6:%.*]] = mul i32 4, [[T5]] - // CHECK-NEXT: [[T7:%.*]] = add i32 [[T6]], 4 - // CHECK-NEXT: call void @_ZdaPvj(ptr noundef [[T3]], i32 noundef [[T7]]) + // CHECK-NEXT: call void @_ZdaPv(ptr noundef [[T3]]) // CHECK-NEXT: br label ::delete[] p; } diff --git a/clang/test/CodeGenCXX/delete.cpp b/clang/test/CodeGenCXX/delete.cpp index d5b0dc671291..1a418f48b659 100644 --- a/clang/test/CodeGenCXX/delete.cpp +++ b/clang/test/CodeGenCXX/delete.cpp @@ -16,7 +16,7 @@ void t3(S *s) { // CHECK: icmp {{.*}} null // CHECK: br i1 - // CHECK: call void @_ZdlPvm + // CHECK: call void @_ZdlPv // Check the delete is inside the 'if !null' check unless we're optimizing // for size. FIXME: We could omit the branch entirely in this case. @@ -35,7 +35,7 @@ struct T { void t4(T *t) { // CHECK: call void @_ZN1TD1Ev // CHECK-SIZE-NEXT: br - // CHECK: call void @_ZdlPvm + // CHECK: call void @_ZdlPv delete t; } @@ -93,16 +93,14 @@ namespace test1 { // CHECK-NEXT: call void @_ZN5test11AD1Ev(ptr {{[^,]*}} [[CUR]]) // CHECK-NEXT: [[ISDONE:%.*]] = icmp eq ptr [[CUR]], [[BEGIN]] // CHECK-NEXT: br i1 [[ISDONE]] - // CHECK: [[MUL:%.*]] = mul i64 4, [[COUNT]] - // CHECK-NEXT: [[SIZE:%.*]] = add i64 [[MUL]], 8 - // CHECK-NEXT: call void @_ZdaPvm(ptr noundef [[ALLOC]], i64 noundef [[SIZE]]) + // CHECK: call void @_ZdaPv(ptr noundef [[ALLOC]]) } } namespace test2 { // CHECK-LABEL: define{{.*}} void @_ZN5test21fEPb void f(bool *b) { - // CHECK: call void @_ZdlPvm(ptr{{.*}}i64 + // CHECK: call void @_ZdlPv(ptr delete b; // CHECK: call void @_ZdaPv(ptr delete [] b; @@ -139,7 +137,7 @@ namespace test4 { // CHECK-NEXT: [[DTOR:%.*]] = load ptr, ptr [[T0]] // CHECK-NEXT: call void [[DTOR]](ptr {{[^,]*}} [[OBJ:%.*]]) // Call the global operator delete. - // CHECK-NEXT: call void @_ZdlPvm(ptr noundef [[ALLOCATED]], i64 noundef 8) [[NUW:#[0-9]+]] + // CHECK-NEXT: call void @_ZdlPv(ptr noundef [[ALLOCATED]]) [[NUW:#[0-9]+]] ::delete xp; } } diff --git a/clang/test/CodeGenCXX/dllimport.cpp b/clang/test/CodeGenCXX/dllimport.cpp index 484866b45389..6fec2f2982d4 100644 --- a/clang/test/CodeGenCXX/dllimport.cpp +++ b/clang/test/CodeGenCXX/dllimport.cpp @@ -205,7 +205,7 @@ USEVAR(VarTmpl) // Functions //===----------------------------------------------------------------------===// -// GNU-DAG: declare dso_local void @_ZdlPv{{j|y}}(ptr, i{{32|64}}) +// GNU-DAG: declare dso_local void @_ZdlPv(ptr) // Import function declaration. // MSC-DAG: declare dllimport void @"?decl@@YAXXZ"() @@ -358,7 +358,7 @@ __declspec(dllimport) void operator delete(void*); __declspec(dllimport) inline int *ReferencingImportedNew() { return new int[2]; } // MO1-DAG: define available_externally dllimport ptr @"?ReferencingImportedNew@@YAPAHXZ" __declspec(dllimport) inline int *ReferencingImportedDelete() { delete (int*)nullptr; } -// MO1-DAG: declare dllimport ptr @"?ReferencingImportedDelete@@YAPAHXZ" +// MO1-DAG: define available_externally dllimport ptr @"?ReferencingImportedDelete@@YAPAHXZ" USE(ReferencingImportedNew) USE(ReferencingImportedDelete) struct ClassWithDtor { ~ClassWithDtor() {} }; diff --git a/clang/test/CodeGenCXX/new.cpp b/clang/test/CodeGenCXX/new.cpp index af225529c494..e278d9acfe9e 100644 --- a/clang/test/CodeGenCXX/new.cpp +++ b/clang/test/CodeGenCXX/new.cpp @@ -15,7 +15,7 @@ void t1() { } // CHECK: declare noundef nonnull ptr @_Znwm(i64 noundef) [[ATTR_NOBUILTIN:#[^ ]*]] -// CHECK: declare void @_ZdlPvm(ptr noundef, i64 noundef) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] +// CHECK: declare void @_ZdlPv(ptr noundef) [[ATTR_NOBUILTIN_NOUNWIND:#[^ ]*]] // CHECK: declare noundef nonnull ptr @_Znam(i64 noundef) [[ATTR_NOBUILTIN]] // CHECK: declare void @_ZdaPv(ptr noundef) [[ATTR_NOBUILTIN_NOUNWIND]] @@ -192,7 +192,7 @@ void f() { // CHECK: store i64 200 delete[] new (nothrow) Alloc[10][20]; // CHECK: call noalias noundef nonnull ptr @_Znwm - // CHECK: call void @_ZdlPvm(ptr noundef {{%.*}}, i64 noundef 1) + // CHECK: call void @_ZdlPv(ptr delete new bool; // CHECK: ret void } @@ -317,7 +317,7 @@ namespace N3664 { void f() { // CHECK: call noalias noundef nonnull ptr @_Znwm(i64 noundef 4) [[ATTR_BUILTIN_NEW:#[^ ]*]] int *p = new int; // expected-note {{allocated with 'new' here}} - // CHECK: call void @_ZdlPvm({{.*}}) [[ATTR_BUILTIN_DELETE:#[^ ]*]] + // CHECK: call void @_ZdlPv({{.*}}) [[ATTR_BUILTIN_DELETE:#[^ ]*]] delete p; // CHECK: call noalias noundef nonnull ptr @_Znam(i64 noundef 12) [[ATTR_BUILTIN_NEW]] diff --git a/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp b/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp index ecf991a2fb49..a3ee964a22a1 100644 --- a/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp +++ b/clang/test/CodeGenCoroutines/coro-aligned-alloc-2.cpp @@ -1,7 +1,9 @@ // Tests that the combination of -fcoro-aligned-allocation and -fsized-deallocation works well. // Test the compiler will chose sized deallocation correctly. +// This is only enabled with `-fsized-deallocation` which is off by default. // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -std=c++20 \ // RUN: -fcoro-aligned-allocation -S -emit-llvm %s -o - -disable-llvm-passes \ +// RUN: -fsized-deallocation \ // RUN: | FileCheck %s #include "Inputs/coroutine.h" diff --git a/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp b/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp index b50d9f8f7674..d14c3d372ddb 100644 --- a/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp +++ b/clang/test/CodeGenCoroutines/coro-aligned-alloc.cpp @@ -26,9 +26,8 @@ struct task { // CHECK: %[[aligned_new:.+]] = call{{.*}}@_ZnwmSt11align_val_t({{.*}}%[[coro_size]],{{.*}}%[[coro_align]]) // CHECK: coro.free: -// CHECK: %[[coro_size_for_free:.+]] = call{{.*}}@llvm.coro.size // CHECK: %[[coro_align_for_free:.+]] = call{{.*}}@llvm.coro.align -// CHECK: call void @_ZdlPvmSt11align_val_t({{.*}}%[[coro_size_for_free]],{{.*}}%[[coro_align_for_free]]) +// CHECK: call void @_ZdlPvSt11align_val_t({{.*}}[[coro_align_for_free]] task f() { co_return 43; @@ -59,9 +58,8 @@ void *operator new(std::size_t, std::align_val_t, std::nothrow_t) noexcept; // CHECK: %[[aligned_new:.+]] = call{{.*}}@_ZnwmSt11align_val_tSt9nothrow_t({{.*}}%[[coro_size]],{{.*}}%[[coro_align]]) // CHECK: coro.free: -// CHECK: %[[coro_size_for_free:.+]] = call{{.*}}@llvm.coro.size // CHECK: %[[coro_align_for_free:.+]] = call{{.*}}@llvm.coro.align -// CHECK: call void @_ZdlPvmSt11align_val_t({{.*}}%[[coro_size_for_free]],{{.*}}%[[coro_align_for_free]]) +// CHECK: call void @_ZdlPvSt11align_val_t({{.*}}[[coro_align_for_free]] task2 f2() { co_return 43; diff --git a/clang/test/CodeGenCoroutines/coro-alloc.cpp b/clang/test/CodeGenCoroutines/coro-alloc.cpp index 7b3be7e0b7f9..d026a0d7df22 100644 --- a/clang/test/CodeGenCoroutines/coro-alloc.cpp +++ b/clang/test/CodeGenCoroutines/coro-alloc.cpp @@ -70,8 +70,7 @@ extern "C" void f0(global_new_delete_tag) { // CHECK: br i1 %[[NeedDealloc]], label %[[FreeBB:.+]], label %[[Afterwards:.+]] // CHECK: [[FreeBB]]: - // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call void @_ZdlPvm(ptr noundef %[[MEM]], i64 noundef %[[SIZE]]) + // CHECK: call void @_ZdlPv(ptr noundef %[[MEM]]) // CHECK: br label %[[Afterwards]] // CHECK: [[Afterwards]]: @@ -100,8 +99,7 @@ extern "C" void f1(promise_new_tag ) { // CHECK: %[[FRAME:.+]] = call ptr @llvm.coro.begin( // CHECK: %[[MEM:.+]] = call ptr @llvm.coro.free(token %[[ID]], ptr %[[FRAME]]) - // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call void @_ZdlPvm(ptr noundef %[[MEM]], i64 noundef %[[SIZE]]) + // CHECK: call void @_ZdlPv(ptr noundef %[[MEM]]) co_return; } diff --git a/clang/test/CodeGenCoroutines/coro-cleanup.cpp b/clang/test/CodeGenCoroutines/coro-cleanup.cpp index 4e77ac25af1b..98f150758e2d 100644 --- a/clang/test/CodeGenCoroutines/coro-cleanup.cpp +++ b/clang/test/CodeGenCoroutines/coro-cleanup.cpp @@ -84,13 +84,11 @@ void f() { // CHECK: [[Cleanup]]: // CHECK: call void @_ZNSt16coroutine_traitsIJvEE12promise_typeD1Ev( // CHECK: %[[Mem0:.+]] = call ptr @llvm.coro.free( - // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call void @_ZdlPvm(ptr noundef %[[Mem0]], i64 noundef %[[SIZE]]) + // CHECK: call void @_ZdlPv(ptr noundef %[[Mem0]] // CHECK: [[Dealloc]]: // THROWEND: %[[Mem:.+]] = call ptr @llvm.coro.free( - // THROWEND: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // THROWEND: call void @_ZdlPvm(ptr noundef %[[Mem]], i64 noundef %[[SIZE]]) + // THROWEND: call void @_ZdlPv(ptr noundef %[[Mem]]) co_return; } diff --git a/clang/test/CodeGenCoroutines/coro-dealloc.cpp b/clang/test/CodeGenCoroutines/coro-dealloc.cpp index 656c9cbd3ef2..1f7d04b3689e 100644 --- a/clang/test/CodeGenCoroutines/coro-dealloc.cpp +++ b/clang/test/CodeGenCoroutines/coro-dealloc.cpp @@ -1,5 +1,6 @@ // RUN: %clang_cc1 -triple x86_64-unknown-linux-gnu -std=c++20 \ // RUN: -S -emit-llvm %s -o - -disable-llvm-passes \ +// RUN: -fsized-deallocation \ // RUN: | FileCheck %s #include "Inputs/coroutine.h" @@ -20,6 +21,7 @@ struct task { }; // Test the compiler will chose sized deallocation correctly. +// This is only enabled with `-fsized-deallocation` which is off by default. void operator delete(void *ptr, std::size_t size) noexcept; // CHECK: define{{.*}}@_Z1fv diff --git a/clang/test/CodeGenCoroutines/coro-gro.cpp b/clang/test/CodeGenCoroutines/coro-gro.cpp index b62134317cef..d4c3ff589e34 100644 --- a/clang/test/CodeGenCoroutines/coro-gro.cpp +++ b/clang/test/CodeGenCoroutines/coro-gro.cpp @@ -51,8 +51,7 @@ int f() { // CHECK: call void @_ZNSt16coroutine_traitsIiJEE12promise_typeD1Ev( // CHECK: %[[Mem:.+]] = call ptr @llvm.coro.free( - // CHECK: %[[SIZE:.+]] = call i64 @llvm.coro.size.i64() - // CHECK: call void @_ZdlPvm(ptr noundef %[[Mem]], i64 noundef %[[SIZE]]) + // CHECK: call void @_ZdlPv(ptr noundef %[[Mem]]) // Initialize retval from Gro and destroy Gro // Note this also tests delaying initialization when Gro and function return diff --git a/clang/test/CodeGenCoroutines/pr56919.cpp b/clang/test/CodeGenCoroutines/pr56919.cpp index baa8c27ce664..c7de08ef72d7 100644 --- a/clang/test/CodeGenCoroutines/pr56919.cpp +++ b/clang/test/CodeGenCoroutines/pr56919.cpp @@ -111,15 +111,12 @@ Task Bar() { co_await Baz(); } // CHECK: _Z3Quxv.destroy:{{.*}} // CHECK-NEXT: # -// CHECK-NEXT: movl $40, %esi -// CHECK-NEXT: jmp _ZdlPvm@PLT +// CHECK-NEXT: jmp _ZdlPv // CHECK: _Z3Bazv.destroy:{{.*}} // CHECK-NEXT: # -// CHECK-NEXT: movl $80, %esi -// CHECK-NEXT: jmp _ZdlPvm +// CHECK-NEXT: jmp _ZdlPv // CHECK: _Z3Barv.destroy:{{.*}} // CHECK-NEXT: # -// CHECK-NEXT: movl $120, %esi -// CHECK-NEXT: jmp _ZdlPvm +// CHECK-NEXT: jmp _ZdlPv diff --git a/clang/test/Lexer/cxx-features.cpp b/clang/test/Lexer/cxx-features.cpp index 738c31966606..baaa9d4434e9 100644 --- a/clang/test/Lexer/cxx-features.cpp +++ b/clang/test/Lexer/cxx-features.cpp @@ -1,17 +1,17 @@ // RUN: %clang_cc1 -std=c++98 -fcxx-exceptions -verify %s // RUN: %clang_cc1 -std=c++11 -fcxx-exceptions -verify %s -// RUN: %clang_cc1 -std=c++14 -fcxx-exceptions -verify %s -// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -verify %s -// RUN: %clang_cc1 -std=c++20 -fcxx-exceptions -verify %s -// RUN: %clang_cc1 -std=c++23 -fcxx-exceptions -verify %s -// RUN: %clang_cc1 -std=c++2c -fcxx-exceptions -verify %s +// RUN: %clang_cc1 -std=c++14 -fcxx-exceptions -fsized-deallocation -verify %s +// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -fsized-deallocation -verify %s +// RUN: %clang_cc1 -std=c++20 -fcxx-exceptions -fsized-deallocation -verify %s +// RUN: %clang_cc1 -std=c++23 -fcxx-exceptions -fsized-deallocation -verify %s +// RUN: %clang_cc1 -std=c++2c -fcxx-exceptions -fsized-deallocation -verify %s // -// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -frelaxed-template-template-args -DRELAXED_TEMPLATE_TEMPLATE_ARGS=1 -verify %s -// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -DCONCEPTS_TS=1 -verify %s -// RUN: %clang_cc1 -std=c++14 -fno-rtti -fno-threadsafe-statics -verify %s -DNO_EXCEPTIONS -DNO_RTTI -DNO_THREADSAFE_STATICS -// RUN: %clang_cc1 -std=c++14 -fchar8_t -DNO_EXCEPTIONS -DCHAR8_T -verify %s -// RUN: %clang_cc1 -std=c++2a -fno-char8_t -DNO_EXCEPTIONS -DNO_CHAR8_T -verify %s +// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -fsized-deallocation -frelaxed-template-template-args -DRELAXED_TEMPLATE_TEMPLATE_ARGS=1 -verify %s +// RUN: %clang_cc1 -std=c++17 -fcxx-exceptions -fsized-deallocation -DCONCEPTS_TS=1 -verify %s +// RUN: %clang_cc1 -std=c++14 -fno-rtti -fno-threadsafe-statics -verify %s -DNO_EXCEPTIONS -DNO_RTTI -DNO_THREADSAFE_STATICS -fsized-deallocation +// RUN: %clang_cc1 -std=c++14 -fchar8_t -DNO_EXCEPTIONS -DCHAR8_T -verify -fsized-deallocation %s +// RUN: %clang_cc1 -std=c++2a -fno-char8_t -DNO_EXCEPTIONS -DNO_CHAR8_T -verify -fsized-deallocation %s // expected-no-diagnostics diff --git a/clang/test/PCH/cxx1z-aligned-alloc.cpp b/clang/test/PCH/cxx1z-aligned-alloc.cpp index cccd62859784..c1becbde3bf2 100644 --- a/clang/test/PCH/cxx1z-aligned-alloc.cpp +++ b/clang/test/PCH/cxx1z-aligned-alloc.cpp @@ -1,12 +1,12 @@ // No PCH: -// RUN: %clang_cc1 -pedantic -std=c++1z -include %s -verify %s +// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -include %s -verify %s // // With PCH: -// RUN: %clang_cc1 -pedantic -std=c++1z -emit-pch %s -o %t -// RUN: %clang_cc1 -pedantic -std=c++1z -include-pch %t -verify %s +// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -emit-pch %s -o %t +// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -include-pch %t -verify %s -// RUN: %clang_cc1 -pedantic -std=c++1z -emit-pch -fpch-instantiate-templates %s -o %t -// RUN: %clang_cc1 -pedantic -std=c++1z -include-pch %t -verify %s +// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -emit-pch -fpch-instantiate-templates %s -o %t +// RUN: %clang_cc1 -pedantic -fsized-deallocation -std=c++1z -include-pch %t -verify %s // expected-no-diagnostics diff --git a/clang/test/SemaCXX/MicrosoftExtensions.cpp b/clang/test/SemaCXX/MicrosoftExtensions.cpp index 98c19975095b..7286217b1644 100644 --- a/clang/test/SemaCXX/MicrosoftExtensions.cpp +++ b/clang/test/SemaCXX/MicrosoftExtensions.cpp @@ -571,17 +571,11 @@ class PR34109_class { virtual ~PR34109_class() {} }; -#if !defined(__cpp_sized_deallocation) void operator delete(void *) throw(); // expected-note@-1 {{previous declaration is here}} __declspec(dllexport) void operator delete(void *) throw(); // expected-error@-1 {{redeclaration of 'operator delete' cannot add 'dllexport' attribute}} -#else -void operator delete(void *, unsigned int) throw(); -// expected-note@-1 {{previous declaration is here}} -__declspec(dllexport) void operator delete(void *, unsigned int) throw(); -// expected-error@-1 {{redeclaration of 'operator delete' cannot add 'dllexport' attribute}} -#endif + void PR34109(int* a) { delete a; } diff --git a/clang/test/SemaCXX/builtin-operator-new-delete.cpp b/clang/test/SemaCXX/builtin-operator-new-delete.cpp index db15616803e3..6fcff92dc095 100644 --- a/clang/test/SemaCXX/builtin-operator-new-delete.cpp +++ b/clang/test/SemaCXX/builtin-operator-new-delete.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1z -fno-sized-deallocation -fsyntax-only -verify %s +// RUN: %clang_cc1 -std=c++1z -fsyntax-only -verify %s // RUN: %clang_cc1 -std=c++03 -fsyntax-only -verify %s // RUN: %clang_cc1 -std=c++03 -faligned-allocation -fsyntax-only -verify %s // RUN: %clang_cc1 -std=c++11 -fsyntax-only -verify %s diff --git a/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp b/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp index 462f1725bb1c..3ec65a6a64d1 100644 --- a/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp +++ b/clang/test/SemaCXX/cxx1y-sized-deallocation.cpp @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -std=c++1y -verify %s -fexceptions -fcxx-exceptions +// RUN: %clang_cc1 -std=c++1y -verify %s -fsized-deallocation -fexceptions -fcxx-exceptions using size_t = decltype(sizeof(0)); void operator delete(void *, size_t) noexcept; // expected-note {{'operator delete' declared here}} diff --git a/clang/test/SemaCXX/unavailable_aligned_allocation.cpp b/clang/test/SemaCXX/unavailable_aligned_allocation.cpp index 45fdec606ad1..be593eafe11d 100644 --- a/clang/test/SemaCXX/unavailable_aligned_allocation.cpp +++ b/clang/test/SemaCXX/unavailable_aligned_allocation.cpp @@ -75,7 +75,7 @@ void testOveraligned() { // expected-error-re@-22 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is {{only|not}} available on}} // expected-note@-23 {{if you supply your own aligned allocation functions}} -// expected-error-re@-24 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is {{only|not}} available on}} +// expected-error-re@-24 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is {{only|not}} available on}} // expected-note@-25 {{if you supply your own aligned allocation functions}} // expected-error-re@-26 {{aligned allocation function of type 'void *(std::size_t, std::align_val_t, const std::nothrow_t &) noexcept' is {{only|not}} available on}} @@ -143,19 +143,19 @@ OveralignedS2::~OveralignedS2() {} // expected-no-diagnostics #else #if defined(IOS) -// expected-error@-6 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on iOS 11 or newer}}} +// expected-error@-6 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on iOS 11 or newer}}} // expected-note@-7 {{if you supply your own aligned allocation functions}} #elif defined(TVOS) -// expected-error@-9 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on tvOS 11 or newer}}} +// expected-error@-9 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on tvOS 11 or newer}}} // expected-note@-10 {{if you supply your own aligned allocation functions}} #elif defined(WATCHOS) -// expected-error@-12 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on watchOS 4 or newer}}} +// expected-error@-12 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on watchOS 4 or newer}}} // expected-note@-13 {{if you supply your own aligned allocation functions}} #elif defined(MACOS) -// expected-error@-15 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is only available on macOS 10.13 or newer}}} +// expected-error@-15 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is only available on macOS 10.13 or newer}}} // expected-note@-16 {{if you supply your own aligned allocation functions}} #elif defined(ZOS) -// expected-error@-18 {{aligned deallocation function of type 'void (void *, std::size_t, std::align_val_t) noexcept' is not available on z/OS}}} +// expected-error@-18 {{aligned deallocation function of type 'void (void *, enum std::align_val_t) noexcept' is not available on z/OS}}} // expected-note@-19 {{if you supply your own aligned allocation functions}} #endif #endif @@ -209,9 +209,6 @@ void *operator new(std::size_t __sz, std::align_val_t) { void operator delete(void *p, std::align_val_t) { } -void operator delete(void *p, std::size_t __sz, std::align_val_t) { -} - void testOveraligned2() { auto p = new ((std::align_val_t)8) OveralignedS; delete p; diff --git a/clang/tools/clang-repl/CMakeLists.txt b/clang/tools/clang-repl/CMakeLists.txt index 2b7d5f014189..d3dec1984b78 100644 --- a/clang/tools/clang-repl/CMakeLists.txt +++ b/clang/tools/clang-repl/CMakeLists.txt @@ -11,65 +11,6 @@ add_clang_tool(clang-repl ClangRepl.cpp ) -if(MSVC) - set_target_properties(clang-repl PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS 1) - - # RTTI/C++ symbols - set(clang_repl_exports ${clang_repl_exports} ??_7type_info@@6B@ - ?__type_info_root_node@@3U__type_info_node@@A - ?nothrow@std@@3Unothrow_t@1@B - ) - - # Compiler added symbols for static variables. NOT for VStudio < 2015 - set(clang_repl_exports ${clang_repl_exports} _Init_thread_abort _Init_thread_epoch - _Init_thread_footer _Init_thread_header _tls_index - ) - - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - # new/delete variants needed when linking to static msvc runtime (esp. Debug) - set(clang_repl_exports ${clang_repl_exports} - ??2@YAPEAX_K@Z - ??3@YAXPEAX@Z - ??_U@YAPEAX_K@Z - ??_V@YAXPEAX@Z - ??3@YAXPEAX_K@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z - ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z - ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z - ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z - ) - else() - set(clang_repl_exports ${clang_repl_exports} - ??2@YAPAXI@Z - ??3@YAXPAX@Z - ??3@YAXPAXI@Z - ??_U@YAPAXI@Z - ??_V@YAXPAX@Z - ??_V@YAXPAXI@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z - ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z - ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z - ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z - ) - endif() - - # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...' - foreach(sym ${clang_repl_exports}) - set(clang_repl_link_str "${clang_repl_link_str} /EXPORT:${sym}") - endforeach(sym ${clang_repl_exports}) - - set_property(TARGET clang-repl APPEND_STRING PROPERTY LINK_FLAGS ${clang_repl_link_str}) - -endif(MSVC) - clang_target_link_libraries(clang-repl PRIVATE clangAST clangBasic diff --git a/clang/unittests/Interpreter/CMakeLists.txt b/clang/unittests/Interpreter/CMakeLists.txt index bc831d33bf3d..e5a77e77de75 100644 --- a/clang/unittests/Interpreter/CMakeLists.txt +++ b/clang/unittests/Interpreter/CMakeLists.txt @@ -29,62 +29,3 @@ if(NOT WIN32) endif() export_executable_symbols(ClangReplInterpreterTests) - -if(MSVC) - set_target_properties(ClangReplInterpreterTests PROPERTIES WINDOWS_EXPORT_ALL_SYMBOLS 1) - - # RTTI/C++ symbols - set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} ??_7type_info@@6B@ - ?__type_info_root_node@@3U__type_info_node@@A - ?nothrow@std@@3Unothrow_t@1@B - ) - - # Compiler added symbols for static variables. NOT for VStudio < 2015 - set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} _Init_thread_abort _Init_thread_epoch - _Init_thread_footer _Init_thread_header _tls_index - ) - - if(CMAKE_SIZEOF_VOID_P EQUAL 8) - # new/delete variants needed when linking to static msvc runtime (esp. Debug) - set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} - ??2@YAPEAX_K@Z - ??3@YAXPEAX@Z - ??_U@YAPEAX_K@Z - ??_V@YAXPEAX@Z - ??3@YAXPEAX_K@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@H@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@M@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@N@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@PEBX@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QEAAAEAV01@P6AAEAV01@AEAV01@@Z@Z - ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@D@Z - ??$?6U?$char_traits@D@std@@@std@@YAAEAV?$basic_ostream@DU?$char_traits@D@std@@@0@AEAV10@PEBD@Z - ?_Facet_Register@std@@YAXPEAV_Facet_base@1@@Z - ) - else() - set(ClangReplInterpreterTests_exports ${ClangReplInterpreterTests_exports} - ??2@YAPAXI@Z - ??3@YAXPAX@Z - ??3@YAXPAXI@Z - ??_U@YAPAXI@Z - ??_V@YAXPAX@Z - ??_V@YAXPAXI@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@H@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@M@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@N@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@PBX@Z - ??6?$basic_ostream@DU?$char_traits@D@std@@@std@@QAEAAV01@P6AAAV01@AAV01@@Z@Z - ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@D@Z - ??$?6U?$char_traits@D@std@@@std@@YAAAV?$basic_ostream@DU?$char_traits@D@std@@@0@AAV10@PBD@Z - ?_Facet_Register@std@@YAXPAV_Facet_base@1@@Z - ) - endif() - - # List to '/EXPORT:sym0 /EXPORT:sym1 /EXPORT:sym2 ...' - foreach(sym ${ClangReplInterpreterTests_exports}) - set(ClangReplInterpreterTests_link_str "${ClangReplInterpreterTests_link_str} /EXPORT:${sym}") - endforeach(sym ${ClangReplInterpreterTests_exports}) - - set_property(TARGET ClangReplInterpreterTests APPEND_STRING PROPERTY LINK_FLAGS ${ClangReplInterpreterTests_link_str}) - -endif(MSVC) diff --git a/clang/unittests/StaticAnalyzer/CallEventTest.cpp b/clang/unittests/StaticAnalyzer/CallEventTest.cpp index 7c4132788ca7..adbfe02a284d 100644 --- a/clang/unittests/StaticAnalyzer/CallEventTest.cpp +++ b/clang/unittests/StaticAnalyzer/CallEventTest.cpp @@ -76,7 +76,7 @@ TEST(CXXDeallocatorCall, SimpleDestructor) { } )", Diags)); - EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 2\n"); + EXPECT_EQ(Diags, "test.CXXDeallocator: NumArgs: 1\n"); } } // namespace diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index 96705224ee4a..c233171e63c8 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -1258,11 +1258,12 @@ code. This issue is expected to be rectified soon.

-(7): The user must supply definitions of the sized deallocation - functions, either by providing them explicitly or by using a C++ standard library - that does. libstdc++ added these functions in version 5.0, and - libc++ added them in version 3.7. The user can also use the - -fno-sized-deallocation option to disable sized deallocation. +(7): In Clang 3.7 and later, sized deallocation is only enabled +if the user passes the -fsized-deallocation flag. The user must +supply definitions of the sized deallocation functions, either by providing them +explicitly or by using a C++ standard library that does. libstdc++ +added these functions in version 5.0, and libc++ added them in +version 3.7.

diff --git a/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp b/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp index aa3ce210e363..f94ceaf57dba 100644 --- a/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp +++ b/libcxx/test/libcxx/language.support/support.dynamic/libcpp_deallocate.sh.cpp @@ -21,9 +21,6 @@ // GCC doesn't support the aligned-allocation flags. // XFAIL: gcc -// TODO(mordante) fix this test after updating clang in Docker -// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18, clang-19 - // RUN: %{build} -faligned-allocation -fsized-deallocation // RUN: %{run} // RUN: %{build} -faligned-allocation -fno-sized-deallocation -DNO_SIZE diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp index 0241e7cefcac..21663cdf956d 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.array/sized_delete_array14.pass.cpp @@ -8,11 +8,11 @@ // test sized operator delete[] replacement. -// TODO(mordante) fix this test after updating clang in Docker -// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18, clang-19 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11 -// XFAIL: apple-clang -// XFAIL: using-built-library-before-llvm-11 + +// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by +// default. It is only enabled when -fsized-deallocation is given. +// XFAIL: clang, apple-clang #include #include diff --git a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp index 2ab691618ea4..a8701ce7a86c 100644 --- a/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp +++ b/libcxx/test/std/language.support/support.dynamic/new.delete/new.delete.single/sized_delete14.pass.cpp @@ -8,11 +8,11 @@ // test sized operator delete replacement. -// TODO(mordante) fix this test after updating clang in Docker -// UNSUPPORTED: clang-15, clang-16, clang-17, clang-18, clang-19 // UNSUPPORTED: sanitizer-new-delete, c++03, c++11 -// XFAIL: apple-clang -// XFAIL: using-built-library-before-llvm-11 + +// NOTE: Clang does not enable sized-deallocation in C++14 and beyond by +// default. It is only enabled when -fsized-deallocation is given. +// XFAIL: clang, apple-clang #include #include -- GitLab From de375fbc713b7c5cd0e3377a49f0773300203b63 Mon Sep 17 00:00:00 2001 From: Craig Topper Date: Fri, 26 Apr 2024 17:24:41 -0700 Subject: [PATCH 112/301] [RISCV] Move OrderedExtensionMap typedef to RISCVISAUtils.h. NFC --- clang/lib/Driver/ToolChains/Gnu.cpp | 4 +- lld/ELF/Arch/RISCV.cpp | 4 +- llvm/include/llvm/Support/RISCVISAUtils.h | 7 ++ llvm/include/llvm/TargetParser/RISCVISAInfo.h | 14 ++-- llvm/lib/TargetParser/RISCVISAInfo.cpp | 2 +- .../TargetParser/RISCVISAInfoTest.cpp | 68 ++++++++----------- llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 4 +- 7 files changed, 47 insertions(+), 56 deletions(-) diff --git a/clang/lib/Driver/ToolChains/Gnu.cpp b/clang/lib/Driver/ToolChains/Gnu.cpp index f55b8bf48c13..9849c59685cc 100644 --- a/clang/lib/Driver/ToolChains/Gnu.cpp +++ b/clang/lib/Driver/ToolChains/Gnu.cpp @@ -1796,9 +1796,7 @@ selectRISCVMultilib(const MultilibSet &RISCVMultilibSet, StringRef Arch, } auto &MLConfigISAInfo = *MLConfigParseResult; - const llvm::RISCVISAInfo::OrderedExtensionMap &MLConfigArchExts = - MLConfigISAInfo->getExtensions(); - for (auto MLConfigArchExt : MLConfigArchExts) { + for (auto &MLConfigArchExt : MLConfigISAInfo->getExtensions()) { auto ExtName = MLConfigArchExt.first; NewMultilib.flag(Twine("-", ExtName).str()); diff --git a/lld/ELF/Arch/RISCV.cpp b/lld/ELF/Arch/RISCV.cpp index 20088d92bafa..e4d63250135e 100644 --- a/lld/ELF/Arch/RISCV.cpp +++ b/lld/ELF/Arch/RISCV.cpp @@ -1057,7 +1057,7 @@ public: }; } // namespace -static void mergeArch(RISCVISAInfo::OrderedExtensionMap &mergedExts, +static void mergeArch(RISCVISAUtils::OrderedExtensionMap &mergedExts, unsigned &mergedXlen, const InputSectionBase *sec, StringRef s) { auto maybeInfo = RISCVISAInfo::parseNormalizedArchString(s); @@ -1086,7 +1086,7 @@ static void mergeArch(RISCVISAInfo::OrderedExtensionMap &mergedExts, static RISCVAttributesSection * mergeAttributesSection(const SmallVector §ions) { - RISCVISAInfo::OrderedExtensionMap exts; + RISCVISAUtils::OrderedExtensionMap exts; const InputSectionBase *firstStackAlign = nullptr; unsigned firstStackAlignValue = 0, xlen = 0; bool hasArch = false; diff --git a/llvm/include/llvm/Support/RISCVISAUtils.h b/llvm/include/llvm/Support/RISCVISAUtils.h index 94aedb75faa2..77f8c3e45f1a 100644 --- a/llvm/include/llvm/Support/RISCVISAUtils.h +++ b/llvm/include/llvm/Support/RISCVISAUtils.h @@ -14,6 +14,7 @@ #define LLVM_SUPPORT_RISCVISAUTILS_H #include "llvm/ADT/StringRef.h" +#include #include namespace llvm { @@ -35,6 +36,12 @@ struct ExtensionComparator { return compareExtension(LHS, RHS); } }; + +/// OrderedExtensionMap is std::map, it's specialized to keep entries +/// in canonical order of extension. +typedef std::map + OrderedExtensionMap; + } // namespace RISCVISAUtils } // namespace llvm diff --git a/llvm/include/llvm/TargetParser/RISCVISAInfo.h b/llvm/include/llvm/TargetParser/RISCVISAInfo.h index 83c4f1e620fc..0d5637155daa 100644 --- a/llvm/include/llvm/TargetParser/RISCVISAInfo.h +++ b/llvm/include/llvm/TargetParser/RISCVISAInfo.h @@ -26,13 +26,7 @@ public: RISCVISAInfo(const RISCVISAInfo &) = delete; RISCVISAInfo &operator=(const RISCVISAInfo &) = delete; - /// OrderedExtensionMap is std::map, it's specialized to keep entries - /// in canonical order of extension. - typedef std::map - OrderedExtensionMap; - - RISCVISAInfo(unsigned XLen, OrderedExtensionMap &Exts) + RISCVISAInfo(unsigned XLen, RISCVISAUtils::OrderedExtensionMap &Exts) : XLen(XLen), FLen(0), MinVLen(0), MaxELen(0), MaxELenFp(0), Exts(Exts) {} /// Parse RISC-V ISA info from arch string. @@ -59,7 +53,9 @@ public: std::vector toFeatures(bool AddAllExtensions = false, bool IgnoreUnknown = true) const; - const OrderedExtensionMap &getExtensions() const { return Exts; } + const RISCVISAUtils::OrderedExtensionMap &getExtensions() const { + return Exts; + } unsigned getXLen() const { return XLen; } unsigned getFLen() const { return FLen; } @@ -90,7 +86,7 @@ private: unsigned MinVLen; unsigned MaxELen, MaxELenFp; - OrderedExtensionMap Exts; + RISCVISAUtils::OrderedExtensionMap Exts; void addExtension(StringRef ExtName, RISCVISAUtils::ExtensionVersion Version); diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index ac0f958dbb26..14d7c6ec8a4a 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -112,7 +112,7 @@ void llvm::riscvExtensionsHelp(StringMap DescMap) { outs() << "All available -march extensions for RISC-V\n\n"; PrintExtension("Name", "Version", (DescMap.empty() ? "" : "Description")); - RISCVISAInfo::OrderedExtensionMap ExtMap; + RISCVISAUtils::OrderedExtensionMap ExtMap; for (const auto &E : SupportedExtensions) ExtMap[E.Name] = {E.Version.Major, E.Version.Minor}; for (const auto &E : ExtMap) { diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index 81b7e2e527d9..c945c4fbcf63 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -137,7 +137,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { auto MaybeRV32I = RISCVISAInfo::parseArchString("rv32i", true); ASSERT_THAT_EXPECTED(MaybeRV32I, Succeeded()); RISCVISAInfo &InfoRV32I = **MaybeRV32I; - RISCVISAInfo::OrderedExtensionMap ExtsRV32I = InfoRV32I.getExtensions(); + const auto &ExtsRV32I = InfoRV32I.getExtensions(); EXPECT_EQ(ExtsRV32I.size(), 1UL); EXPECT_TRUE(ExtsRV32I.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_EQ(InfoRV32I.getXLen(), 32U); @@ -146,7 +146,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { auto MaybeRV32E = RISCVISAInfo::parseArchString("rv32e", true); ASSERT_THAT_EXPECTED(MaybeRV32E, Succeeded()); RISCVISAInfo &InfoRV32E = **MaybeRV32E; - RISCVISAInfo::OrderedExtensionMap ExtsRV32E = InfoRV32E.getExtensions(); + const auto &ExtsRV32E = InfoRV32E.getExtensions(); EXPECT_EQ(ExtsRV32E.size(), 1UL); EXPECT_TRUE(ExtsRV32E.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV32E.getXLen(), 32U); @@ -155,7 +155,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { auto MaybeRV32G = RISCVISAInfo::parseArchString("rv32g", true); ASSERT_THAT_EXPECTED(MaybeRV32G, Succeeded()); RISCVISAInfo &InfoRV32G = **MaybeRV32G; - RISCVISAInfo::OrderedExtensionMap ExtsRV32G = InfoRV32G.getExtensions(); + const auto &ExtsRV32G = InfoRV32G.getExtensions(); EXPECT_EQ(ExtsRV32G.size(), 7UL); EXPECT_TRUE(ExtsRV32G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV32G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); @@ -171,7 +171,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { auto MaybeRV64I = RISCVISAInfo::parseArchString("rv64i", true); ASSERT_THAT_EXPECTED(MaybeRV64I, Succeeded()); RISCVISAInfo &InfoRV64I = **MaybeRV64I; - RISCVISAInfo::OrderedExtensionMap ExtsRV64I = InfoRV64I.getExtensions(); + const auto &ExtsRV64I = InfoRV64I.getExtensions(); EXPECT_EQ(ExtsRV64I.size(), 1UL); EXPECT_TRUE(ExtsRV64I.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_EQ(InfoRV64I.getXLen(), 64U); @@ -180,7 +180,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { auto MaybeRV64E = RISCVISAInfo::parseArchString("rv64e", true); ASSERT_THAT_EXPECTED(MaybeRV64E, Succeeded()); RISCVISAInfo &InfoRV64E = **MaybeRV64E; - RISCVISAInfo::OrderedExtensionMap ExtsRV64E = InfoRV64E.getExtensions(); + const auto &ExtsRV64E = InfoRV64E.getExtensions(); EXPECT_EQ(ExtsRV64E.size(), 1UL); EXPECT_TRUE(ExtsRV64E.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0})); EXPECT_EQ(InfoRV64E.getXLen(), 64U); @@ -189,7 +189,7 @@ TEST(ParseArchString, AcceptsSupportedBaseISAsAndSetsXLenAndFLen) { auto MaybeRV64G = RISCVISAInfo::parseArchString("rv64g", true); ASSERT_THAT_EXPECTED(MaybeRV64G, Succeeded()); RISCVISAInfo &InfoRV64G = **MaybeRV64G; - RISCVISAInfo::OrderedExtensionMap ExtsRV64G = InfoRV64G.getExtensions(); + const auto &ExtsRV64G = InfoRV64G.getExtensions(); EXPECT_EQ(ExtsRV64G.size(), 7UL); EXPECT_TRUE(ExtsRV64G.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); EXPECT_TRUE(ExtsRV64G.at("m") == (RISCVISAUtils::ExtensionVersion{2, 0})); @@ -241,7 +241,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); RISCVISAInfo &Info = **MaybeISAInfo; - RISCVISAInfo::OrderedExtensionMap Exts = Info.getExtensions(); + const auto &Exts = Info.getExtensions(); EXPECT_EQ(Exts.size(), 1UL); EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } @@ -251,7 +251,7 @@ TEST(ParseArchString, IgnoresUnrecognizedExtensionNamesWithIgnoreUnknown) { auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv32i_zbc1p0_xmadeup", true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_TRUE(Exts.at("zbc") == (RISCVISAUtils::ExtensionVersion{1, 0})); } @@ -259,13 +259,13 @@ TEST(ParseArchString, AcceptsVersionInLongOrShortForm) { for (StringRef Input : {"rv64i2p1"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } for (StringRef Input : {"rv32i_zfinx1", "rv32i_zfinx1p0"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_TRUE(Exts.at("zfinx") == (RISCVISAUtils::ExtensionVersion{1, 0})); } } @@ -293,14 +293,14 @@ TEST(ParseArchString, for (StringRef Input : {"rv32i0p1", "rv32i99p99", "rv64i0p1", "rv64i99p99"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } for (StringRef Input : {"rv32e0p1", "rv32e99p99", "rv64e0p1", "rv64e99p99"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); EXPECT_TRUE(Exts.at("e") == (RISCVISAUtils::ExtensionVersion{2, 0})); } @@ -311,7 +311,7 @@ TEST(ParseArchString, for (StringRef Input : {"rv32im1p1", "rv64i_svnapot10p9", "rv32i_zicsr0p5"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true, false, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 1UL); EXPECT_TRUE(Exts.at("i") == (RISCVISAUtils::ExtensionVersion{2, 1})); } @@ -321,7 +321,7 @@ TEST(ParseArchString, AcceptsUnderscoreSplittingExtensions) { for (StringRef Input : {"rv32imafdczifencei", "rv32i_m_a_f_d_c_zifencei"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 8UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); @@ -339,7 +339,7 @@ TEST(ParseArchString, AcceptsRelaxSingleLetterExtensions) { {"rv32imfad", "rv32im_fa_d", "rv32im2p0fad", "rv32i2p1m2p0fad"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 6UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); @@ -356,7 +356,7 @@ TEST(ParseArchString, AcceptsRelaxMixedLetterExtensions) { "rv32i_zihintntl_mafd_svinval"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 8UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("m"), 1U); @@ -373,7 +373,7 @@ TEST(ParseArchString, AcceptsAmbiguousFromRelaxExtensions) { for (StringRef Input : {"rv32i_zba_m", "rv32izba_m", "rv32izba1p0_m2p0"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 3UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("zba"), 1U); @@ -383,7 +383,7 @@ TEST(ParseArchString, AcceptsAmbiguousFromRelaxExtensions) { {"rv32ia_zba_m", "rv32iazba_m", "rv32ia2p1zba1p0_m2p0"}) { auto MaybeISAInfo = RISCVISAInfo::parseArchString(Input, true); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 4UL); EXPECT_EQ(Exts.count("i"), 1U); EXPECT_EQ(Exts.count("zba"), 1U); @@ -457,12 +457,12 @@ TEST(ParseArchString, // hopefully serve as a reminder to update. auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv64iztso", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); EXPECT_EQ(Exts.count("ztso"), 1U); auto MaybeISAInfo2 = RISCVISAInfo::parseArchString("rv64iztso0p1", true); ASSERT_THAT_EXPECTED(MaybeISAInfo2, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts2 = (*MaybeISAInfo2)->getExtensions(); + const auto &Exts2 = (*MaybeISAInfo2)->getExtensions(); EXPECT_EQ(Exts2.size(), 2UL); EXPECT_EQ(Exts2.count("ztso"), 1U); } @@ -479,7 +479,7 @@ TEST(ParseArchString, auto MaybeISAInfo = RISCVISAInfo::parseArchString("rv64iztso9p9", true, false); ASSERT_THAT_EXPECTED(MaybeISAInfo, Succeeded()); - RISCVISAInfo::OrderedExtensionMap Exts = (*MaybeISAInfo)->getExtensions(); + const auto &Exts = (*MaybeISAInfo)->getExtensions(); EXPECT_EQ(Exts.size(), 2UL); EXPECT_TRUE(Exts.at("ztso") == (RISCVISAUtils::ExtensionVersion{9, 9})); } @@ -502,8 +502,7 @@ TEST(ParseArchString, AddsImpliedExtensions) { // Does not attempt to exhaustively test all implications. auto MaybeRV64ID = RISCVISAInfo::parseArchString("rv64id", true); ASSERT_THAT_EXPECTED(MaybeRV64ID, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV64ID = - (*MaybeRV64ID)->getExtensions(); + const auto &ExtsRV64ID = (*MaybeRV64ID)->getExtensions(); EXPECT_EQ(ExtsRV64ID.size(), 4UL); EXPECT_EQ(ExtsRV64ID.count("i"), 1U); EXPECT_EQ(ExtsRV64ID.count("f"), 1U); @@ -512,8 +511,7 @@ TEST(ParseArchString, AddsImpliedExtensions) { auto MaybeRV32IZKN = RISCVISAInfo::parseArchString("rv64izkn", true); ASSERT_THAT_EXPECTED(MaybeRV32IZKN, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV32IZKN = - (*MaybeRV32IZKN)->getExtensions(); + const auto &ExtsRV32IZKN = (*MaybeRV32IZKN)->getExtensions(); EXPECT_EQ(ExtsRV32IZKN.size(), 8UL); EXPECT_EQ(ExtsRV32IZKN.count("i"), 1U); EXPECT_EQ(ExtsRV32IZKN.count("zbkb"), 1U); @@ -603,7 +601,7 @@ TEST(ToFeatures, AddAllExtensionsAddsNegativeExtensions) { } TEST(OrderedExtensionMap, ExtensionsAreCorrectlyOrdered) { - RISCVISAInfo::OrderedExtensionMap Exts; + RISCVISAUtils::OrderedExtensionMap Exts; for (auto ExtName : {"y", "l", "m", "c", "i", "xfoo", "xbar", "sfoo", "sbar", "zmfoo", "zzfoo", "zfinx", "zicsr"}) Exts[ExtName] = {1, 0}; @@ -621,8 +619,7 @@ TEST(OrderedExtensionMap, ExtensionsAreCorrectlyOrdered) { TEST(ParseArchString, ZceImplication) { auto MaybeRV32IZce = RISCVISAInfo::parseArchString("rv32izce", true); ASSERT_THAT_EXPECTED(MaybeRV32IZce, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV32IZce = - (*MaybeRV32IZce)->getExtensions(); + const auto &ExtsRV32IZce = (*MaybeRV32IZce)->getExtensions(); EXPECT_EQ(ExtsRV32IZce.size(), 7UL); EXPECT_EQ(ExtsRV32IZce.count("i"), 1U); EXPECT_EQ(ExtsRV32IZce.count("zicsr"), 1U); @@ -634,8 +631,7 @@ TEST(ParseArchString, ZceImplication) { auto MaybeRV32IFZce = RISCVISAInfo::parseArchString("rv32ifzce", true); ASSERT_THAT_EXPECTED(MaybeRV32IFZce, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV32IFZce = - (*MaybeRV32IFZce)->getExtensions(); + const auto &ExtsRV32IFZce = (*MaybeRV32IFZce)->getExtensions(); EXPECT_EQ(ExtsRV32IFZce.size(), 9UL); EXPECT_EQ(ExtsRV32IFZce.count("i"), 1U); EXPECT_EQ(ExtsRV32IFZce.count("zicsr"), 1U); @@ -649,8 +645,7 @@ TEST(ParseArchString, ZceImplication) { auto MaybeRV32IDZce = RISCVISAInfo::parseArchString("rv32idzce", true); ASSERT_THAT_EXPECTED(MaybeRV32IDZce, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV32IDZce = - (*MaybeRV32IDZce)->getExtensions(); + const auto &ExtsRV32IDZce = (*MaybeRV32IDZce)->getExtensions(); EXPECT_EQ(ExtsRV32IDZce.size(), 10UL); EXPECT_EQ(ExtsRV32IDZce.count("i"), 1U); EXPECT_EQ(ExtsRV32IDZce.count("zicsr"), 1U); @@ -665,8 +660,7 @@ TEST(ParseArchString, ZceImplication) { auto MaybeRV64IZce = RISCVISAInfo::parseArchString("rv64izce", true); ASSERT_THAT_EXPECTED(MaybeRV64IZce, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV64IZce = - (*MaybeRV64IZce)->getExtensions(); + const auto &ExtsRV64IZce = (*MaybeRV64IZce)->getExtensions(); EXPECT_EQ(ExtsRV64IZce.size(), 7UL); EXPECT_EQ(ExtsRV64IZce.count("i"), 1U); EXPECT_EQ(ExtsRV64IZce.count("zicsr"), 1U); @@ -678,8 +672,7 @@ TEST(ParseArchString, ZceImplication) { auto MaybeRV64IFZce = RISCVISAInfo::parseArchString("rv64ifzce", true); ASSERT_THAT_EXPECTED(MaybeRV64IFZce, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV64IFZce = - (*MaybeRV64IFZce)->getExtensions(); + const auto &ExtsRV64IFZce = (*MaybeRV64IFZce)->getExtensions(); EXPECT_EQ(ExtsRV64IFZce.size(), 8UL); EXPECT_EQ(ExtsRV64IFZce.count("i"), 1U); EXPECT_EQ(ExtsRV64IFZce.count("zicsr"), 1U); @@ -698,8 +691,7 @@ TEST(ParseArchString, ZceImplication) { auto MaybeRV64IDZce = RISCVISAInfo::parseArchString("rv64idzce", true); ASSERT_THAT_EXPECTED(MaybeRV64IDZce, Succeeded()); - RISCVISAInfo::OrderedExtensionMap ExtsRV64IDZce = - (*MaybeRV64IDZce)->getExtensions(); + const auto &ExtsRV64IDZce = (*MaybeRV64IDZce)->getExtensions(); EXPECT_EQ(ExtsRV64IDZce.size(), 9UL); EXPECT_EQ(ExtsRV64IDZce.count("i"), 1U); EXPECT_EQ(ExtsRV64IDZce.count("zicsr"), 1U); diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index c34c4b3f1881..18c5be20244e 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -90,9 +90,7 @@ static void emitRISCVExtensions(RecordKeeper &Records, raw_ostream &OS) { // This is almost the same as RISCVFeatures::parseFeatureBits, except that we // get feature name from feature records instead of feature bits. static void printMArch(raw_ostream &OS, const Record &Rec) { - std::map - Extensions; + RISCVISAUtils::OrderedExtensionMap Extensions; unsigned XLen = 0; // Convert features to FeatureVector. -- GitLab From d6bf04f4760b0dff3c3d3ff9b560c04438cc25ac Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Fri, 26 Apr 2024 18:38:15 -0700 Subject: [PATCH 113/301] [LTO] Remove extraneous ArrayRef (NFC) (#90306) We don't need to explicitly create these instances of ArrayRef because Hasher::update takes ArrayRef, and ArrayRef can be implicitly constructed from C arrays. --- llvm/lib/LTO/LTO.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/LTO/LTO.cpp b/llvm/lib/LTO/LTO.cpp index 53060df7f503..21cad1de0ced 100644 --- a/llvm/lib/LTO/LTO.cpp +++ b/llvm/lib/LTO/LTO.cpp @@ -114,12 +114,12 @@ void llvm::computeLTOCacheKey( auto AddUnsigned = [&](unsigned I) { uint8_t Data[4]; support::endian::write32le(Data, I); - Hasher.update(ArrayRef{Data, 4}); + Hasher.update(Data); }; auto AddUint64 = [&](uint64_t I) { uint8_t Data[8]; support::endian::write64le(Data, I); - Hasher.update(ArrayRef{Data, 8}); + Hasher.update(Data); }; AddString(Conf.CPU); // FIXME: Hash more of Options. For now all clients initialize Options from -- GitLab From e04df693bf5b38099ef1d7ab8e6ce6a1469597e2 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Fri, 26 Apr 2024 19:22:17 -0700 Subject: [PATCH 114/301] [memprof] Introduce FrameIdConverter and CallStackIdConverter (#90307) Currently, we convert FrameId to Frame and CallStackId to a call stack at several places. This patch unifies those into function objects -- FrameIdConverter and CallStackIdConverter. The existing implementation of CallStackIdConverter, being removed in this patch, handles both FrameId and CallStackId conversions. This patch splits it into two phases for flexibility (but make them composable) because some places only require the FrameId conversion. --- llvm/include/llvm/ProfileData/MemProf.h | 58 +++++++++++++++++ llvm/include/llvm/ProfileData/MemProfReader.h | 14 ++--- llvm/lib/ProfileData/InstrProfReader.cpp | 44 ++++--------- llvm/unittests/ProfileData/InstrProfTest.cpp | 62 +++++-------------- llvm/unittests/ProfileData/MemProfTest.cpp | 36 +++-------- 5 files changed, 97 insertions(+), 117 deletions(-) diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index d378c3696f8d..8b00faf2a219 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -737,6 +737,64 @@ public: // Compute a CallStackId for a given call stack. CallStackId hashCallStack(ArrayRef CS); +namespace detail { +// "Dereference" the iterator from DenseMap or OnDiskChainedHashTable. We have +// to do so in one of two different ways depending on the type of the hash +// table. +template +value_type DerefIterator(IterTy Iter) { + using deref_type = llvm::remove_cvref_t; + if constexpr (std::is_same_v) + return *Iter; + else + return Iter->second; +} +} // namespace detail + +// A function object that returns a frame for a given FrameId. +template struct FrameIdConverter { + std::optional LastUnmappedId; + MapTy ⤅ + + FrameIdConverter() = delete; + FrameIdConverter(MapTy &Map) : Map(Map) {} + + Frame operator()(FrameId Id) { + auto Iter = Map.find(Id); + if (Iter == Map.end()) { + LastUnmappedId = Id; + return Frame(0, 0, 0, false); + } + return detail::DerefIterator(Iter); + } +}; + +// A function object that returns a call stack for a given CallStackId. +template struct CallStackIdConverter { + std::optional LastUnmappedId; + MapTy ⤅ + std::function FrameIdToFrame; + + CallStackIdConverter() = delete; + CallStackIdConverter(MapTy &Map, std::function FrameIdToFrame) + : Map(Map), FrameIdToFrame(FrameIdToFrame) {} + + llvm::SmallVector operator()(CallStackId CSId) { + llvm::SmallVector Frames; + auto CSIter = Map.find(CSId); + if (CSIter == Map.end()) { + LastUnmappedId = CSId; + } else { + llvm::SmallVector CS = + detail::DerefIterator>(CSIter); + Frames.reserve(CS.size()); + for (FrameId Id : CS) + Frames.push_back(FrameIdToFrame(Id)); + } + return Frames; + } +}; + // Verify that each CallStackId is computed with hashCallStack. This function // is intended to help transition from CallStack to CSId in // IndexedAllocationInfo. diff --git a/llvm/include/llvm/ProfileData/MemProfReader.h b/llvm/include/llvm/ProfileData/MemProfReader.h index 444c58e8bdc8..b42e4f597774 100644 --- a/llvm/include/llvm/ProfileData/MemProfReader.h +++ b/llvm/include/llvm/ProfileData/MemProfReader.h @@ -76,20 +76,16 @@ public: Callback = std::bind(&MemProfReader::idToFrame, this, std::placeholders::_1); - auto CallStackCallback = [&](CallStackId CSId) { - llvm::SmallVector CallStack; - auto Iter = CSIdToCallStack.find(CSId); - assert(Iter != CSIdToCallStack.end()); - for (FrameId Id : Iter->second) - CallStack.push_back(Callback(Id)); - return CallStack; - }; + memprof::CallStackIdConverter CSIdConv( + CSIdToCallStack, Callback); const IndexedMemProfRecord &IndexedRecord = Iter->second; GuidRecord = { Iter->first, - IndexedRecord.toMemProfRecord(CallStackCallback), + IndexedRecord.toMemProfRecord(CSIdConv), }; + if (CSIdConv.LastUnmappedId) + return make_error(instrprof_error::hash_mismatch); Iter++; return Error::success(); } diff --git a/llvm/lib/ProfileData/InstrProfReader.cpp b/llvm/lib/ProfileData/InstrProfReader.cpp index cefb6af12d00..440be2f255d3 100644 --- a/llvm/lib/ProfileData/InstrProfReader.cpp +++ b/llvm/lib/ProfileData/InstrProfReader.cpp @@ -1520,53 +1520,35 @@ IndexedMemProfReader::getMemProfRecord(const uint64_t FuncNameHash) const { // Setup a callback to convert from frame ids to frame using the on-disk // FrameData hash table. - std::optional LastUnmappedFrameId; - auto IdToFrameCallback = [&](const memprof::FrameId Id) { - auto FrIter = MemProfFrameTable->find(Id); - if (FrIter == MemProfFrameTable->end()) { - LastUnmappedFrameId = Id; - return memprof::Frame(0, 0, 0, false); - } - return *FrIter; - }; + memprof::FrameIdConverter FrameIdConv( + *MemProfFrameTable.get()); // Setup a callback to convert call stack ids to call stacks using the on-disk // hash table. - std::optional LastUnmappedCSId; - auto CSIdToCallStackCallback = [&](memprof::CallStackId CSId) { - llvm::SmallVector Frames; - auto CSIter = MemProfCallStackTable->find(CSId); - if (CSIter == MemProfCallStackTable->end()) { - LastUnmappedCSId = CSId; - } else { - const llvm::SmallVector &CS = *CSIter; - Frames.reserve(CS.size()); - for (memprof::FrameId Id : CS) - Frames.push_back(IdToFrameCallback(Id)); - } - return Frames; - }; + memprof::CallStackIdConverter CSIdConv( + *MemProfCallStackTable.get(), FrameIdConv); const memprof::IndexedMemProfRecord IndexedRecord = *Iter; memprof::MemProfRecord Record; if (MemProfCallStackTable) - Record = IndexedRecord.toMemProfRecord(CSIdToCallStackCallback); + Record = IndexedRecord.toMemProfRecord(CSIdConv); else - Record = memprof::MemProfRecord(IndexedRecord, IdToFrameCallback); + Record = memprof::MemProfRecord(IndexedRecord, FrameIdConv); // Check that all frame ids were successfully converted to frames. - if (LastUnmappedFrameId) { - return make_error(instrprof_error::hash_mismatch, - "memprof frame not found for frame id " + - Twine(*LastUnmappedFrameId)); + if (FrameIdConv.LastUnmappedId) { + return make_error( + instrprof_error::hash_mismatch, + "memprof frame not found for frame id " + + Twine(*FrameIdConv.LastUnmappedId)); } // Check that all call stack ids were successfully converted to call stacks. - if (LastUnmappedCSId) { + if (CSIdConv.LastUnmappedId) { return make_error( instrprof_error::hash_mismatch, "memprof call stack not found for call stack id " + - Twine(*LastUnmappedCSId)); + Twine(*CSIdConv.LastUnmappedId)); } return Record; } diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index edc427dcbc45..acc633de11b6 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -495,44 +495,6 @@ TEST_F(InstrProfTest, test_memprof_v0) { EXPECT_THAT(WantRecord, EqualsRecord(Record)); } -struct CallStackIdConverter { - std::optional LastUnmappedFrameId; - std::optional LastUnmappedCSId; - - const FrameIdMapTy &IdToFrameMap; - const CallStackIdMapTy &CSIdToCallStackMap; - - CallStackIdConverter() = delete; - CallStackIdConverter(const FrameIdMapTy &IdToFrameMap, - const CallStackIdMapTy &CSIdToCallStackMap) - : IdToFrameMap(IdToFrameMap), CSIdToCallStackMap(CSIdToCallStackMap) {} - - llvm::SmallVector - operator()(::llvm::memprof::CallStackId CSId) { - auto IdToFrameCallback = [&](const memprof::FrameId Id) { - auto Iter = IdToFrameMap.find(Id); - if (Iter == IdToFrameMap.end()) { - LastUnmappedFrameId = Id; - return memprof::Frame(0, 0, 0, false); - } - return Iter->second; - }; - - llvm::SmallVector Frames; - auto CSIter = CSIdToCallStackMap.find(CSId); - if (CSIter == CSIdToCallStackMap.end()) { - LastUnmappedCSId = CSId; - } else { - const ::llvm::SmallVector<::llvm::memprof::FrameId> &CS = - CSIter->getSecond(); - Frames.reserve(CS.size()); - for (::llvm::memprof::FrameId Id : CS) - Frames.push_back(IdToFrameCallback(Id)); - } - return Frames; - } -}; - TEST_F(InstrProfTest, test_memprof_v2_full_schema) { const MemInfoBlock MIB = makeFullMIB(); @@ -562,14 +524,16 @@ TEST_F(InstrProfTest, test_memprof_v2_full_schema) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); + memprof::FrameIdConverter FrameIdConv(IdToFrameMap); + memprof::CallStackIdConverter CSIdConv( + CSIdToCallStackMap, FrameIdConv); const ::llvm::memprof::MemProfRecord WantRecord = IndexedMR.toMemProfRecord(CSIdConv); - ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) - << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; - ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) - << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; + ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt) + << "could not map frame id: " << *FrameIdConv.LastUnmappedId; + ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } @@ -602,14 +566,16 @@ TEST_F(InstrProfTest, test_memprof_v2_partial_schema) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); + memprof::FrameIdConverter FrameIdConv(IdToFrameMap); + memprof::CallStackIdConverter CSIdConv( + CSIdToCallStackMap, FrameIdConv); const ::llvm::memprof::MemProfRecord WantRecord = IndexedMR.toMemProfRecord(CSIdConv); - ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) - << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; - ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) - << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; + ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt) + << "could not map frame id: " << *FrameIdConv.LastUnmappedId; + ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } diff --git a/llvm/unittests/ProfileData/MemProfTest.cpp b/llvm/unittests/ProfileData/MemProfTest.cpp index 98dacd3511e1..d031049cea14 100644 --- a/llvm/unittests/ProfileData/MemProfTest.cpp +++ b/llvm/unittests/ProfileData/MemProfTest.cpp @@ -502,37 +502,15 @@ TEST(MemProf, IndexedMemProfRecordToMemProfRecord) { IndexedRecord.CallSiteIds.push_back(llvm::memprof::hashCallStack(CS3)); IndexedRecord.CallSiteIds.push_back(llvm::memprof::hashCallStack(CS4)); - bool CSIdMissing = false; - bool FrameIdMissing = false; - - auto Callback = [&](CallStackId CSId) -> llvm::SmallVector { - llvm::SmallVector CallStack; - llvm::SmallVector FrameIds; - - auto Iter = CallStackIdMap.find(CSId); - if (Iter == CallStackIdMap.end()) - CSIdMissing = true; - else - FrameIds = Iter->second; - - for (FrameId Id : FrameIds) { - Frame F(0, 0, 0, false); - auto Iter = FrameIdMap.find(Id); - if (Iter == FrameIdMap.end()) - FrameIdMissing = true; - else - F = Iter->second; - CallStack.push_back(F); - } - - return CallStack; - }; - - MemProfRecord Record = IndexedRecord.toMemProfRecord(Callback); + llvm::memprof::FrameIdConverter FrameIdConv(FrameIdMap); + llvm::memprof::CallStackIdConverter CSIdConv( + CallStackIdMap, FrameIdConv); + + MemProfRecord Record = IndexedRecord.toMemProfRecord(CSIdConv); // Make sure that all lookups are successful. - ASSERT_FALSE(CSIdMissing); - ASSERT_FALSE(FrameIdMissing); + ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt); + ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt); // Verify the contents of Record. ASSERT_THAT(Record.AllocSites, SizeIs(2)); -- GitLab From 315dc4bbc730a3c672967c27587088cfe9752fe6 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Fri, 26 Apr 2024 19:54:36 -0700 Subject: [PATCH 115/301] [clang-format] Add a space after a word token only if required (#90161) Fixes #78166. --- clang/lib/Format/TokenAnnotator.cpp | 26 +++++++------------------- clang/unittests/Format/FormatTest.cpp | 25 +++++++++++++++++-------- 2 files changed, 24 insertions(+), 27 deletions(-) diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index cdfb4256e41d..63629fa74318 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -4834,10 +4834,8 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, Right.is(TT_TemplateOpener)) { return true; } - if (Left.is(tok::identifier) && Right.is(tok::numeric_constant) && - Right.TokenText[0] == '.') { - return false; - } + if (Left.Tok.getIdentifierInfo() && Right.is(tok::numeric_constant)) + return Right.TokenText[0] != '.'; } else if (Style.isProto()) { if (Right.is(tok::period) && Left.isOneOf(Keywords.kw_optional, Keywords.kw_required, @@ -5266,21 +5264,11 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, return true; } if (Left.is(TT_UnaryOperator)) { - if (Right.isNot(tok::l_paren)) { - // The alternative operators for ~ and ! are "compl" and "not". - // If they are used instead, we do not want to combine them with - // the token to the right, unless that is a left paren. - if (Left.is(tok::exclaim) && Left.TokenText == "not") - return true; - if (Left.is(tok::tilde) && Left.TokenText == "compl") - return true; - // Lambda captures allow for a lone &, so "&]" needs to be properly - // handled. - if (Left.is(tok::amp) && Right.is(tok::r_square)) - return Style.SpacesInSquareBrackets; - } - return (Style.SpaceAfterLogicalNot && Left.is(tok::exclaim)) || - Right.is(TT_BinaryOperator); + // Lambda captures allow for a lone &, so "&]" needs to be properly + // handled. + if (Left.is(tok::amp) && Right.is(tok::r_square)) + return Style.SpacesInSquareBrackets; + return Style.SpaceAfterLogicalNot && Left.is(tok::exclaim); } // If the next token is a binary operator or a selector name, we have diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index bc61b9c089e9..8ecc1188a127 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -24507,16 +24507,25 @@ TEST_F(FormatTest, AlternativeOperators) { verifyFormat("int a compl(5);"); verifyFormat("int a not(5);"); - /* FIXME handle alternate tokens - * https://en.cppreference.com/w/cpp/language/operator_alternative - // alternative tokens - verifyFormat("compl foo();"); // ~foo(); - verifyFormat("foo() <%%>;"); // foo(); - verifyFormat("void foo() <%%>;"); // void foo(){} - verifyFormat("int a <:1:>;"); // int a[1];[ + verifyFormat("compl foo();"); // ~foo(); + verifyFormat("foo() <%%>"); // foo() {} + verifyFormat("void foo() <%%>"); // void foo() {} + verifyFormat("int a<:1:>;"); // int a[1]; verifyFormat("%:define ABC abc"); // #define ABC abc verifyFormat("%:%:"); // ## - */ + + verifyFormat("a = v(not;);\n" + "b = v(not+);\n" + "c = v(not x);\n" + "d = v(not 1);\n" + "e = v(not 123.f);"); + + verifyNoChange("#define ASSEMBLER_INSTRUCTION_LIST(V) \\\n" + " V(and) \\\n" + " V(not) \\\n" + " V(not!) \\\n" + " V(other)", + getLLVMStyleWithColumns(40)); } TEST_F(FormatTest, STLWhileNotDefineChed) { -- GitLab From cb508a0032eb2d11391214864f408261158361bf Mon Sep 17 00:00:00 2001 From: Perry MacMurray Date: Fri, 26 Apr 2024 22:08:45 -0500 Subject: [PATCH 116/301] [Hexagon] Add Hexagon Copy Hoisting pass (#89313) Adds the HexagonCopyHoisting pass, which moves a common copy instruction into a basic block if it is present in all successor basic blocks. --------- Co-authored-by: Jyotsna Verma --- llvm/lib/Target/Hexagon/CMakeLists.txt | 1 + .../Target/Hexagon/HexagonCopyHoisting.cpp | 272 ++++++++++++++++++ .../Target/Hexagon/HexagonTargetMachine.cpp | 187 ++++++------ .../CodeGen/Hexagon/hexagon-copy-hoisting.mir | 53 ++++ 4 files changed, 428 insertions(+), 85 deletions(-) create mode 100644 llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp create mode 100644 llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir diff --git a/llvm/lib/Target/Hexagon/CMakeLists.txt b/llvm/lib/Target/Hexagon/CMakeLists.txt index cdc062eee72b..9e4ca08aea40 100644 --- a/llvm/lib/Target/Hexagon/CMakeLists.txt +++ b/llvm/lib/Target/Hexagon/CMakeLists.txt @@ -26,6 +26,7 @@ add_llvm_target(HexagonCodeGen HexagonCommonGEP.cpp HexagonConstExtenders.cpp HexagonConstPropagation.cpp + HexagonCopyHoisting.cpp HexagonCopyToCombine.cpp HexagonEarlyIfConv.cpp HexagonExpandCondsets.cpp diff --git a/llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp b/llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp new file mode 100644 index 000000000000..97917270601b --- /dev/null +++ b/llvm/lib/Target/Hexagon/HexagonCopyHoisting.cpp @@ -0,0 +1,272 @@ +//===--------- HexagonCopyHoisting.cpp - Hexagon Copy Hoisting ----------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// The purpose of this pass is to move the copy instructions that are +// present in all the successor of a basic block (BB) to the end of BB. +//===----------------------------------------------------------------------===// + +#include "HexagonTargetMachine.h" +#include "llvm/ADT/DenseMap.h" +#include "llvm/ADT/PostOrderIterator.h" +#include "llvm/ADT/StringRef.h" +#include "llvm/ADT/Twine.h" +#include "llvm/CodeGen/LiveInterval.h" +#include "llvm/CodeGen/LiveIntervals.h" +#include "llvm/CodeGen/MachineDominators.h" +#include "llvm/CodeGen/MachineRegisterInfo.h" +#include "llvm/Support/CommandLine.h" +#include "llvm/Support/Debug.h" + +#define DEBUG_TYPE "CopyHoist" + +using namespace llvm; + +static cl::opt CPHoistFn("cphoistfn", cl::Hidden, cl::desc(""), + cl::init("")); + +namespace llvm { +void initializeHexagonCopyHoistingPass(PassRegistry &Registry); +FunctionPass *createHexagonCopyHoisting(); +} // namespace llvm + +namespace { + +class HexagonCopyHoisting : public MachineFunctionPass { + +public: + static char ID; + HexagonCopyHoisting() : MachineFunctionPass(ID), MFN(nullptr), MRI(nullptr) { + initializeHexagonCopyHoistingPass(*PassRegistry::getPassRegistry()); + } + + StringRef getPassName() const override { return "Hexagon Copy Hoisting"; } + + void getAnalysisUsage(AnalysisUsage &AU) const override { + AU.addRequired(); + AU.addRequired(); + AU.addPreserved(); + AU.addPreserved(); + AU.addRequired(); + AU.addPreserved(); + MachineFunctionPass::getAnalysisUsage(AU); + } + + bool runOnMachineFunction(MachineFunction &Fn) override; + void collectCopyInst(); + void addMItoCopyList(MachineInstr *MI); + bool analyzeCopy(MachineBasicBlock *BB); + bool isSafetoMove(MachineInstr *CandMI); + void moveCopyInstr(MachineBasicBlock *DestBB, + std::pair Key, MachineInstr *MI); + + MachineFunction *MFN; + MachineRegisterInfo *MRI; + std::vector, MachineInstr *>> + CopyMIList; +}; + +} // namespace + +char HexagonCopyHoisting::ID = 0; + +namespace llvm { +char &HexagonCopyHoistingID = HexagonCopyHoisting::ID; +} // namespace llvm + +bool HexagonCopyHoisting::runOnMachineFunction(MachineFunction &Fn) { + + if ((CPHoistFn != "") && (CPHoistFn != Fn.getFunction().getName())) + return false; + + MFN = &Fn; + MRI = &Fn.getRegInfo(); + + LLVM_DEBUG(dbgs() << "\nCopy Hoisting:" << "\'" << Fn.getName() << "\'\n"); + + CopyMIList.clear(); + CopyMIList.resize(Fn.getNumBlockIDs()); + + // Traverse through all basic blocks and collect copy instructions. + collectCopyInst(); + + // Traverse through the basic blocks again and move the COPY instructions + // that are present in all the successors of BB to BB. + bool Changed = false; + for (MachineBasicBlock *BB : post_order(&Fn)) { + if (!BB->empty()) { + if (BB->pred_size() != 1) + continue; + auto &BBCopyInst = CopyMIList[BB->getNumber()]; + if (BBCopyInst.size() > 0) + Changed |= analyzeCopy(*BB->pred_begin()); + } + } + // Re-compute liveness + if (Changed) { + LiveIntervals &LIS = getAnalysis(); + SlotIndexes *SI = LIS.getSlotIndexes(); + SI->releaseMemory(); + SI->runOnMachineFunction(Fn); + LIS.releaseMemory(); + LIS.runOnMachineFunction(Fn); + } + return Changed; +} + +//===----------------------------------------------------------------------===// +// Save all COPY instructions for each basic block in CopyMIList vector. +//===----------------------------------------------------------------------===// +void HexagonCopyHoisting::collectCopyInst() { + for (MachineBasicBlock &BB : *MFN) { +#ifndef NDEBUG + auto &BBCopyInst = CopyMIList[BB.getNumber()]; + LLVM_DEBUG(dbgs() << "Visiting BB#" << BB.getNumber() << ":\n"); +#endif + + for (MachineInstr &MI : BB) { + if (MI.getOpcode() == TargetOpcode::COPY) + addMItoCopyList(&MI); + } + LLVM_DEBUG(dbgs() << "\tNumber of copies: " << BBCopyInst.size() << "\n"); + } +} + +void HexagonCopyHoisting::addMItoCopyList(MachineInstr *MI) { + unsigned BBNum = MI->getParent()->getNumber(); + auto &BBCopyInst = CopyMIList[BBNum]; + Register DstReg = MI->getOperand(0).getReg(); + Register SrcReg = MI->getOperand(1).getReg(); + + if (!Register::isVirtualRegister(DstReg) || + !Register::isVirtualRegister(SrcReg) || + MRI->getRegClass(DstReg) != &Hexagon::IntRegsRegClass || + MRI->getRegClass(SrcReg) != &Hexagon::IntRegsRegClass) + return; + + BBCopyInst.insert(std::pair(std::pair(SrcReg, DstReg), MI)); +#ifndef NDEBUG + LLVM_DEBUG(dbgs() << "\tAdding Copy Instr to the list: " << MI << "\n"); + for (auto II : BBCopyInst) { + MachineInstr *TempMI = II.getSecond(); + LLVM_DEBUG(dbgs() << "\tIn the list: " << TempMI << "\n"); + } +#endif +} + +//===----------------------------------------------------------------------===// +// Look at the COPY instructions of all the successors of BB. If the same +// instruction is present in every successor and can be safely moved, +// pull it into BB. +//===----------------------------------------------------------------------===// +bool HexagonCopyHoisting::analyzeCopy(MachineBasicBlock *BB) { + + bool Changed = false; + if (BB->succ_size() < 2) + return false; + + for (MachineBasicBlock *SB : BB->successors()) { + if (SB->pred_size() != 1 || SB->isEHPad() || SB->hasAddressTaken()) + return false; + } + + MachineBasicBlock *SBB1 = *BB->succ_begin(); + auto &BBCopyInst1 = CopyMIList[SBB1->getNumber()]; + + for (auto II : BBCopyInst1) { + std::pair Key = II.getFirst(); + MachineInstr *MI = II.getSecond(); + bool IsSafetoMove = true; + for (MachineBasicBlock *SuccBB : BB->successors()) { + auto &SuccBBCopyInst = CopyMIList[SuccBB->getNumber()]; + if (!SuccBBCopyInst.count(Key)) { + // Same copy not present in this successor + IsSafetoMove = false; + break; + } + // If present, make sure that it's safe to pull this copy instruction + // into the predecessor. + MachineInstr *SuccMI = SuccBBCopyInst[Key]; + if (!isSafetoMove(SuccMI)) { + IsSafetoMove = false; + break; + } + } + // If we have come this far, this copy instruction can be safely + // moved to the predecessor basic block. + if (IsSafetoMove) { + LLVM_DEBUG(dbgs() << "\t\t Moving instr to BB#" << BB->getNumber() << ": " + << MI << "\n"); + moveCopyInstr(BB, Key, MI); + // Add my into BB copyMI list. + Changed = true; + } + } + +#ifndef NDEBUG + auto &BBCopyInst = CopyMIList[BB->getNumber()]; + for (auto II : BBCopyInst) { + MachineInstr *TempMI = II.getSecond(); + LLVM_DEBUG(dbgs() << "\tIn the list: " << TempMI << "\n"); + } +#endif + return Changed; +} + +bool HexagonCopyHoisting::isSafetoMove(MachineInstr *CandMI) { + // Make sure that it's safe to move this 'copy' instruction to the predecessor + // basic block. + assert(CandMI->getOperand(0).isReg() && CandMI->getOperand(1).isReg()); + Register DefR = CandMI->getOperand(0).getReg(); + Register UseR = CandMI->getOperand(1).getReg(); + + MachineBasicBlock *BB = CandMI->getParent(); + // There should not be a def/use of DefR between the start of BB and CandMI. + MachineBasicBlock::iterator MII, MIE; + for (MII = BB->begin(), MIE = CandMI; MII != MIE; ++MII) { + MachineInstr *OtherMI = &*MII; + for (const MachineOperand &Mo : OtherMI->operands()) + if (Mo.isReg() && Mo.getReg() == DefR) + return false; + } + // There should not be a def of UseR between the start of BB and CandMI. + for (MII = BB->begin(), MIE = CandMI; MII != MIE; ++MII) { + MachineInstr *OtherMI = &*MII; + for (const MachineOperand &Mo : OtherMI->operands()) + if (Mo.isReg() && Mo.isDef() && Mo.getReg() == UseR) + return false; + } + return true; +} + +void HexagonCopyHoisting::moveCopyInstr(MachineBasicBlock *DestBB, + std::pair Key, + MachineInstr *MI) { + MachineBasicBlock::iterator FirstTI = DestBB->getFirstTerminator(); + assert(FirstTI != DestBB->end()); + + DestBB->splice(FirstTI, MI->getParent(), MI); + + addMItoCopyList(MI); + for (auto I = ++(DestBB->succ_begin()), E = DestBB->succ_end(); I != E; ++I) { + MachineBasicBlock *SuccBB = *I; + auto &BBCopyInst = CopyMIList[SuccBB->getNumber()]; + MachineInstr *SuccMI = BBCopyInst[Key]; + SuccMI->eraseFromParent(); + BBCopyInst.erase(Key); + } +} + +//===----------------------------------------------------------------------===// +// Public Constructor Functions +//===----------------------------------------------------------------------===// + +INITIALIZE_PASS(HexagonCopyHoisting, "hexagon-move-phicopy", + "Hexagon move phi copy", false, false) + +FunctionPass *llvm::createHexagonCopyHoisting() { + return new HexagonCopyHoisting(); +} diff --git a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp index e64d7e52a9aa..3a792ecfd03d 100644 --- a/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp +++ b/llvm/lib/Target/Hexagon/HexagonTargetMachine.cpp @@ -43,8 +43,9 @@ cl::opt RDFFuncBlockLimit( "rdf-bb-limit", cl::Hidden, cl::init(1000), cl::desc("Basic block limit for a function for RDF optimizations")); -static cl::opt DisableHardwareLoops("disable-hexagon-hwloops", - cl::Hidden, cl::desc("Disable Hardware Loops for Hexagon target")); +static cl::opt + DisableHardwareLoops("disable-hexagon-hwloops", cl::Hidden, + cl::desc("Disable Hardware Loops for Hexagon target")); static cl::opt DisableAModeOpt("disable-hexagon-amodeopt", cl::Hidden, @@ -58,8 +59,9 @@ static cl::opt DisableHCP("disable-hcp", cl::Hidden, cl::desc("Disable Hexagon constant propagation")); -static cl::opt DisableStoreWidening("disable-store-widen", - cl::Hidden, cl::init(false), cl::desc("Disable store widening")); +static cl::opt DisableStoreWidening("disable-store-widen", cl::Hidden, + cl::init(false), + cl::desc("Disable store widening")); static cl::opt EnableExpandCondsets("hexagon-expand-condsets", cl::init(true), cl::Hidden, @@ -72,42 +74,53 @@ static cl::opt EnableTfrCleanup("hexagon-tfr-cleanup", cl::init(true), static cl::opt EnableEarlyIf("hexagon-eif", cl::init(true), cl::Hidden, cl::desc("Enable early if-conversion")); -static cl::opt EnableGenInsert("hexagon-insert", cl::init(true), - cl::Hidden, cl::desc("Generate \"insert\" instructions")); +static cl::opt EnableCopyHoist("hexagon-copy-hoist", cl::init(true), + cl::Hidden, cl::ZeroOrMore, + cl::desc("Enable Hexagon copy hoisting")); + +static cl::opt + EnableGenInsert("hexagon-insert", cl::init(true), cl::Hidden, + cl::desc("Generate \"insert\" instructions")); static cl::opt EnableCommGEP("hexagon-commgep", cl::init(true), cl::Hidden, cl::desc("Enable commoning of GEP instructions")); -static cl::opt EnableGenExtract("hexagon-extract", cl::init(true), - cl::Hidden, cl::desc("Generate \"extract\" instructions")); +static cl::opt + EnableGenExtract("hexagon-extract", cl::init(true), cl::Hidden, + cl::desc("Generate \"extract\" instructions")); -static cl::opt EnableGenMux("hexagon-mux", cl::init(true), cl::Hidden, - cl::desc("Enable converting conditional transfers into MUX instructions")); +static cl::opt EnableGenMux( + "hexagon-mux", cl::init(true), cl::Hidden, + cl::desc("Enable converting conditional transfers into MUX instructions")); -static cl::opt EnableGenPred("hexagon-gen-pred", cl::init(true), - cl::Hidden, cl::desc("Enable conversion of arithmetic operations to " - "predicate instructions")); +static cl::opt + EnableGenPred("hexagon-gen-pred", cl::init(true), cl::Hidden, + cl::desc("Enable conversion of arithmetic operations to " + "predicate instructions")); static cl::opt EnableLoopPrefetch("hexagon-loop-prefetch", cl::Hidden, cl::desc("Enable loop data prefetch on Hexagon")); -static cl::opt DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, - cl::desc("Disable splitting double registers")); +static cl::opt + DisableHSDR("disable-hsdr", cl::init(false), cl::Hidden, + cl::desc("Disable splitting double registers")); static cl::opt EnableGenMemAbs("hexagon-mem-abs", cl::init(true), cl::Hidden, cl::desc("Generate absolute set instructions")); static cl::opt EnableBitSimplify("hexagon-bit", cl::init(true), - cl::Hidden, cl::desc("Bit simplification")); + cl::Hidden, + cl::desc("Bit simplification")); static cl::opt EnableLoopResched("hexagon-loop-resched", cl::init(true), - cl::Hidden, cl::desc("Loop rescheduling")); + cl::Hidden, + cl::desc("Loop rescheduling")); -static cl::opt HexagonNoOpt("hexagon-noopt", cl::init(false), - cl::Hidden, cl::desc("Disable backend optimizations")); +static cl::opt HexagonNoOpt("hexagon-noopt", cl::init(false), cl::Hidden, + cl::desc("Disable backend optimizations")); static cl::opt EnableVectorPrint("enable-hexagon-vector-print", cl::Hidden, @@ -148,69 +161,72 @@ static ScheduleDAGInstrs *createVLIWMachineSched(MachineSchedContext *C) { } static MachineSchedRegistry -SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", - createVLIWMachineSched); + SchedCustomRegistry("hexagon", "Run Hexagon's custom scheduler", + createVLIWMachineSched); namespace llvm { - extern char &HexagonExpandCondsetsID; - extern char &HexagonTfrCleanupID; - void initializeHexagonBitSimplifyPass(PassRegistry&); - void initializeHexagonConstExtendersPass(PassRegistry&); - void initializeHexagonConstPropagationPass(PassRegistry&); - void initializeHexagonCopyToCombinePass(PassRegistry&); - void initializeHexagonEarlyIfConversionPass(PassRegistry&); - void initializeHexagonExpandCondsetsPass(PassRegistry&); - void initializeHexagonGenMemAbsolutePass(PassRegistry &); - void initializeHexagonGenMuxPass(PassRegistry&); - void initializeHexagonHardwareLoopsPass(PassRegistry&); - void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); - void initializeHexagonLoopAlignPass(PassRegistry &); - void initializeHexagonNewValueJumpPass(PassRegistry&); - void initializeHexagonOptAddrModePass(PassRegistry&); - void initializeHexagonPacketizerPass(PassRegistry&); - void initializeHexagonRDFOptPass(PassRegistry&); - void initializeHexagonSplitDoubleRegsPass(PassRegistry&); - void initializeHexagonTfrCleanupPass(PassRegistry &); - void initializeHexagonVExtractPass(PassRegistry &); - void initializeHexagonVectorCombineLegacyPass(PassRegistry&); - void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); - Pass *createHexagonLoopIdiomPass(); - Pass *createHexagonVectorLoopCarriedReuseLegacyPass(); - - FunctionPass *createHexagonBitSimplify(); - FunctionPass *createHexagonBranchRelaxation(); - FunctionPass *createHexagonCallFrameInformation(); - FunctionPass *createHexagonCFGOptimizer(); - FunctionPass *createHexagonCommonGEP(); - FunctionPass *createHexagonConstExtenders(); - FunctionPass *createHexagonConstPropagationPass(); - FunctionPass *createHexagonCopyToCombine(); - FunctionPass *createHexagonEarlyIfConversion(); - FunctionPass *createHexagonFixupHwLoops(); - FunctionPass *createHexagonGenExtract(); - FunctionPass *createHexagonGenInsert(); - FunctionPass *createHexagonGenMemAbsolute(); - FunctionPass *createHexagonGenMux(); - FunctionPass *createHexagonGenPredicate(); - FunctionPass *createHexagonHardwareLoops(); - FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, - CodeGenOptLevel OptLevel); - FunctionPass *createHexagonLoopAlign(); - FunctionPass *createHexagonLoopRescheduling(); - FunctionPass *createHexagonNewValueJump(); - FunctionPass *createHexagonOptAddrMode(); - FunctionPass *createHexagonOptimizeSZextends(); - FunctionPass *createHexagonPacketizer(bool Minimal); - FunctionPass *createHexagonPeephole(); - FunctionPass *createHexagonRDFOpt(); - FunctionPass *createHexagonSplitConst32AndConst64(); - FunctionPass *createHexagonSplitDoubleRegs(); - FunctionPass *createHexagonStoreWidening(); - FunctionPass *createHexagonTfrCleanup(); - FunctionPass *createHexagonVectorCombineLegacyPass(); - FunctionPass *createHexagonVectorPrint(); - FunctionPass *createHexagonVExtract(); -} // end namespace llvm; +extern char &HexagonCopyHoistingID; +extern char &HexagonExpandCondsetsID; +extern char &HexagonTfrCleanupID; +void initializeHexagonBitSimplifyPass(PassRegistry &); +void initializeHexagonCopyHoistingPass(PassRegistry &); +void initializeHexagonConstExtendersPass(PassRegistry &); +void initializeHexagonConstPropagationPass(PassRegistry &); +void initializeHexagonCopyToCombinePass(PassRegistry &); +void initializeHexagonEarlyIfConversionPass(PassRegistry &); +void initializeHexagonExpandCondsetsPass(PassRegistry &); +void initializeHexagonGenMemAbsolutePass(PassRegistry &); +void initializeHexagonGenMuxPass(PassRegistry &); +void initializeHexagonHardwareLoopsPass(PassRegistry &); +void initializeHexagonLoopIdiomRecognizeLegacyPassPass(PassRegistry &); +void initializeHexagonLoopAlignPass(PassRegistry &); +void initializeHexagonNewValueJumpPass(PassRegistry &); +void initializeHexagonOptAddrModePass(PassRegistry &); +void initializeHexagonPacketizerPass(PassRegistry &); +void initializeHexagonRDFOptPass(PassRegistry &); +void initializeHexagonSplitDoubleRegsPass(PassRegistry &); +void initializeHexagonTfrCleanupPass(PassRegistry &); +void initializeHexagonVExtractPass(PassRegistry &); +void initializeHexagonVectorCombineLegacyPass(PassRegistry &); +void initializeHexagonVectorLoopCarriedReuseLegacyPassPass(PassRegistry &); +Pass *createHexagonLoopIdiomPass(); +Pass *createHexagonVectorLoopCarriedReuseLegacyPass(); + +FunctionPass *createHexagonBitSimplify(); +FunctionPass *createHexagonBranchRelaxation(); +FunctionPass *createHexagonCallFrameInformation(); +FunctionPass *createHexagonCFGOptimizer(); +FunctionPass *createHexagonCommonGEP(); +FunctionPass *createHexagonConstExtenders(); +FunctionPass *createHexagonConstPropagationPass(); +FunctionPass *createHexagonCopyHoisting(); +FunctionPass *createHexagonCopyToCombine(); +FunctionPass *createHexagonEarlyIfConversion(); +FunctionPass *createHexagonFixupHwLoops(); +FunctionPass *createHexagonGenExtract(); +FunctionPass *createHexagonGenInsert(); +FunctionPass *createHexagonGenMemAbsolute(); +FunctionPass *createHexagonGenMux(); +FunctionPass *createHexagonGenPredicate(); +FunctionPass *createHexagonHardwareLoops(); +FunctionPass *createHexagonISelDag(HexagonTargetMachine &TM, + CodeGenOptLevel OptLevel); +FunctionPass *createHexagonLoopAlign(); +FunctionPass *createHexagonLoopRescheduling(); +FunctionPass *createHexagonNewValueJump(); +FunctionPass *createHexagonOptAddrMode(); +FunctionPass *createHexagonOptimizeSZextends(); +FunctionPass *createHexagonPacketizer(bool Minimal); +FunctionPass *createHexagonPeephole(); +FunctionPass *createHexagonRDFOpt(); +FunctionPass *createHexagonSplitConst32AndConst64(); +FunctionPass *createHexagonSplitDoubleRegs(); +FunctionPass *createHexagonStoreWidening(); +FunctionPass *createHexagonTfrCleanup(); +FunctionPass *createHexagonVectorCombineLegacyPass(); +FunctionPass *createHexagonVectorPrint(); +FunctionPass *createHexagonVExtract(); +} // namespace llvm static Reloc::Model getEffectiveRelocModel(std::optional RM) { return RM.value_or(Reloc::Static); @@ -260,6 +276,7 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, (HexagonNoOpt ? CodeGenOptLevel::None : OL)), TLOF(std::make_unique()), Subtarget(Triple(TT), CPU, FS, *this) { + initializeHexagonCopyHoistingPass(*PassRegistry::getPassRegistry()); initializeHexagonExpandCondsetsPass(*PassRegistry::getPassRegistry()); initializeHexagonLoopAlignPass(*PassRegistry::getPassRegistry()); initializeHexagonTfrCleanupPass(*PassRegistry::getPassRegistry()); @@ -269,10 +286,8 @@ HexagonTargetMachine::HexagonTargetMachine(const Target &T, const Triple &TT, const HexagonSubtarget * HexagonTargetMachine::getSubtargetImpl(const Function &F) const { AttributeList FnAttrs = F.getAttributes(); - Attribute CPUAttr = - FnAttrs.getFnAttr("target-cpu"); - Attribute FSAttr = - FnAttrs.getFnAttr("target-features"); + Attribute CPUAttr = FnAttrs.getFnAttr("target-cpu"); + Attribute FSAttr = FnAttrs.getFnAttr("target-features"); std::string CPU = CPUAttr.isValid() ? CPUAttr.getValueAsString().str() : TargetCPU; @@ -331,7 +346,7 @@ namespace { class HexagonPassConfig : public TargetPassConfig { public: HexagonPassConfig(HexagonTargetMachine &TM, PassManagerBase &PM) - : TargetPassConfig(TM, PM) {} + : TargetPassConfig(TM, PM) {} HexagonTargetMachine &getHexagonTargetMachine() const { return getTM(); @@ -433,6 +448,8 @@ void HexagonPassConfig::addPreRegAlloc() { addPass(createHexagonConstExtenders()); if (EnableExpandCondsets) insertPass(&RegisterCoalescerID, &HexagonExpandCondsetsID); + if (EnableCopyHoist) + insertPass(&RegisterCoalescerID, &HexagonCopyHoistingID); if (EnableTfrCleanup) insertPass(&VirtRegRewriterID, &HexagonTfrCleanupID); if (!DisableStoreWidening) diff --git a/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir b/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir new file mode 100644 index 000000000000..0836cac7f913 --- /dev/null +++ b/llvm/test/CodeGen/Hexagon/hexagon-copy-hoisting.mir @@ -0,0 +1,53 @@ +# RUN: llc -march=hexagon -run-pass hexagon-move-phicopy -o - %s | FileCheck %s + +# CHECK-COUNT-1: %4:intregs = COPY %1 + +# CHECK: bb.1 +# CHECK-NOT: %4:intregs = COPY %1 + +# CHECK: bb.2 +# CHECK-NOT: %4:intregs = COPY %1 +# CHECK: %5:intregs = COPY %0 + +--- +name: f0 +tracksRegLiveness: true +registers: + - { id: 0, class: intregs, preferred-register: '' } + - { id: 1, class: intregs, preferred-register: '' } + - { id: 2, class: predregs, preferred-register: '' } + - { id: 3, class: predregs, preferred-register: '' } + - { id: 4, class: intregs, preferred-register: '' } + - { id: 5, class: intregs, preferred-register: '' } +liveins: + - { reg: '$r0', virtual-reg: '%0' } + - { reg: '$r1', virtual-reg: '%1' } +stack: + - { id: 0, offset: 0, size: 4, alignment: 8 } +body: | + bb.0: + successors: %bb.1, %bb.2 + liveins: $r0, $r1 + + %1:intregs = COPY $r1 + %0:intregs = COPY $r0 + %2:predregs = C2_cmpgt %0, %1 + %3:predregs = C2_not %2 + J2_jumpt %3, %bb.2, implicit-def dead $pc + J2_jump %bb.1, implicit-def dead $pc + + bb.1: + successors: %bb.0 + + %4:intregs = COPY %1 + $r1 = COPY %4 + J2_jump %bb.0, implicit-def dead $pc + + bb.2: + successors: %bb.0 + + %4:intregs = COPY %1 + %5:intregs = COPY %0 + $r1 = COPY %4 + J2_jump %bb.0, implicit-def dead $pc +... -- GitLab From 338561657685c1831a53563b1bc36ffc7470239e Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Sat, 27 Apr 2024 03:09:17 +0000 Subject: [PATCH 117/301] [gn build] Port cb508a0032eb --- llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn index cae491a34331..7e873532b9ab 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/Hexagon/BUILD.gn @@ -50,6 +50,7 @@ static_library("LLVMHexagonCodeGen") { "HexagonCommonGEP.cpp", "HexagonConstExtenders.cpp", "HexagonConstPropagation.cpp", + "HexagonCopyHoisting.cpp", "HexagonCopyToCombine.cpp", "HexagonEarlyIfConv.cpp", "HexagonExpandCondsets.cpp", -- GitLab From 90a959a8c978671467041c865509a0e1823c5115 Mon Sep 17 00:00:00 2001 From: Aiden Grossman Date: Fri, 26 Apr 2024 22:09:34 -0700 Subject: [PATCH 118/301] [Bazel] Add llvm-mca unittests (#90309) This patch refactors the llvm-mca rules slightly so that the source files within the tool source directory but not the library source directory are included in a separate cc_library. This patch also adds the llvm-mca unittests. --- .../llvm-project-overlay/llvm/BUILD.bazel | 27 +++++++++++++------ .../llvm/unittests/BUILD.bazel | 26 ++++++++++++++++++ 2 files changed, 45 insertions(+), 8 deletions(-) diff --git a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel index 3223eb92d869..f45f057b63c2 100644 --- a/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/BUILD.bazel @@ -3111,12 +3111,26 @@ cc_library( ) cc_library( - name = "llvm-mca-headers", + name = "MCAApplication", + srcs = glob([ + "tools/llvm-mca/Views/*.cpp", + ]) + [ + mca_source + for mca_source in glob(["tools/llvm-mca/*.cpp"]) + if mca_source != "tools/llvm-mca/llvm-mca.cpp" + ], hdrs = glob([ "tools/llvm-mca/*.h", "tools/llvm-mca/Views/*.h", ]), strip_include_prefix = "tools/llvm-mca", + deps = [ + ":MC", + ":MCA", + ":MCParser", + ":Support", + ":TargetParser", + ], ) cc_library( @@ -4034,12 +4048,9 @@ cc_binary( cc_binary( name = "llvm-mca", - srcs = glob([ - "tools/llvm-mca/*.cpp", - "tools/llvm-mca/*.h", - "tools/llvm-mca/Views/*.cpp", - "tools/llvm-mca/Views/*.h", - ]), + srcs =[ + "tools/llvm-mca/llvm-mca.cpp", + ], copts = llvm_copts, stamp = 0, deps = [ @@ -4049,10 +4060,10 @@ cc_binary( ":AllTargetsMCAs", ":MC", ":MCA", + ":MCAApplication", ":MCParser", ":Support", ":TargetParser", - ":llvm-mca-headers", ], ) diff --git a/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel b/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel index dd42f84d16dc..9be26ab551b0 100644 --- a/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/llvm/unittests/BUILD.bazel @@ -811,3 +811,29 @@ cc_test( "//third-party/unittest:gtest_main", ], ) + +cc_test( + name = "llvm_mca_tests", + size = "small", + srcs = glob( + [ + "tools/llvm-mca/*.cpp", + "tools/llvm-mca/*.h", + "tools/llvm-mca/X86/*.cpp", + "tools/llvm-mca/X86/*.h", + ], + allow_empty = False, + ), + includes = ["tools/llvm-mca"], + deps = [ + "//llvm:MC", + "//llvm:MCA", + "//llvm:MCAApplication", + "//llvm:Support", + "//llvm:TargetParser", + "//llvm:X86CodeGen", + "//llvm:X86UtilsAndDesc", + "//third-party/unittest:gtest", + "//third-party/unittest:gtest_main", + ], +) -- GitLab From 85a9528aa1f2d54379bf972908e12ee2a6f07b4b Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Fri, 26 Apr 2024 22:27:16 -0700 Subject: [PATCH 119/301] [libcxx] Remove empty ~__no_destroy (#89882) Primary motivation: is that after #84651 msan will complain if fields accessed after ~__no_destroy. My understanding of the https://eel.is/c++draft/basic.life#10 Static object with trivial destruction has program lifetime. Static object with empty destuctor has implicit lifetime, and accessing the object after lifetime is UB. It was UB before #84651, it's just msan ignored union members. Existing code with unions uses empty destructor, so accessing after the main() can cause UB. "placement new" version can have trivial destructor, so there is no end of lifetime. Secondary motivation: empty destructor will register __cxa_atexit with -O0. https://gcc.godbolt.org/z/hce587b65 We can not remove the destructor with union where _Tp can have non-trivial destructor. But we can remove destructor if we use in-place new instead of union. https://gcc.godbolt.org/z/Yqxx57eEd - empty even with -O0. New test fails without the patch on https://lab.llvm.org/buildbot/#/builders/sanitizer-x86_64-linux-bootstrap-msan --- libcxx/include/__utility/no_destroy.h | 29 ++++++----------- .../test/libcxx/transitive_includes/cxx20.csv | 1 + .../test/libcxx/utilities/no_destroy.pass.cpp | 31 +++++++++++++++++++ 3 files changed, 42 insertions(+), 19 deletions(-) create mode 100644 libcxx/test/libcxx/utilities/no_destroy.pass.cpp diff --git a/libcxx/include/__utility/no_destroy.h b/libcxx/include/__utility/no_destroy.h index f9c1eb7bed45..8edd194577d7 100644 --- a/libcxx/include/__utility/no_destroy.h +++ b/libcxx/include/__utility/no_destroy.h @@ -12,6 +12,7 @@ #include <__config> #include <__type_traits/is_constant_evaluated.h> #include <__utility/forward.h> +#include #if !defined(_LIBCPP_HAS_NO_PRAGMA_SYSTEM_HEADER) # pragma GCC system_header @@ -29,33 +30,23 @@ struct __uninitialized_tag {}; // initialization using __emplace. template struct __no_destroy { - _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI explicit __no_destroy(__uninitialized_tag) : __dummy_() { - if (__libcpp_is_constant_evaluated()) { - __dummy_ = char(); - } - } - _LIBCPP_HIDE_FROM_ABI ~__no_destroy() { - // nothing - } + _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR explicit __no_destroy(__uninitialized_tag) : __obj_() {} template - _LIBCPP_CONSTEXPR _LIBCPP_HIDE_FROM_ABI explicit __no_destroy(_Args&&... __args) - : __obj_(std::forward<_Args>(__args)...) {} + _LIBCPP_HIDE_FROM_ABI explicit __no_destroy(_Args&&... __args) { + ::new ((void*)__obj_) _Tp(std::forward<_Args>(__args)...); + } template - _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI _Tp& __emplace(_Args&&... __args) { - new (&__obj_) _Tp(std::forward<_Args>(__args)...); - return __obj_; + _LIBCPP_HIDE_FROM_ABI _Tp& __emplace(_Args&&... __args) { + return *(::new ((void*)__obj_) _Tp(std::forward<_Args>(__args)...)); } - _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI _Tp& __get() { return __obj_; } - _LIBCPP_CONSTEXPR_SINCE_CXX14 _LIBCPP_HIDE_FROM_ABI _Tp const& __get() const { return __obj_; } + _LIBCPP_HIDE_FROM_ABI _Tp& __get() { return *reinterpret_cast<_Tp*>(__obj_); } + _LIBCPP_HIDE_FROM_ABI _Tp const& __get() const { return *reinterpret_cast(__obj_); } private: - union { - _Tp __obj_; - char __dummy_; // so we can initialize a member even with __uninitialized_tag for constexpr-friendliness - }; + _ALIGNAS_TYPE(_Tp) char __obj_[sizeof(_Tp)]; }; _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/test/libcxx/transitive_includes/cxx20.csv b/libcxx/test/libcxx/transitive_includes/cxx20.csv index 6b80790a9d19..7d31ba160ee1 100644 --- a/libcxx/test/libcxx/transitive_includes/cxx20.csv +++ b/libcxx/test/libcxx/transitive_includes/cxx20.csv @@ -129,6 +129,7 @@ chrono cwchar chrono forward_list chrono limits chrono locale +chrono new chrono optional chrono ostream chrono ratio diff --git a/libcxx/test/libcxx/utilities/no_destroy.pass.cpp b/libcxx/test/libcxx/utilities/no_destroy.pass.cpp new file mode 100644 index 000000000000..9a874a640753 --- /dev/null +++ b/libcxx/test/libcxx/utilities/no_destroy.pass.cpp @@ -0,0 +1,31 @@ +//===----------------------------------------------------------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include <__utility/no_destroy.h> +#include + +#include "test_macros.h" + +#if TEST_STD_VER > 17 +// Test constexpr-constructibility. +constinit std::__no_destroy nd_int_const(std::__uninitialized_tag{}); +#endif + +struct DestroyLast { + ~DestroyLast() { assert(*ptr == 5); } + + int* ptr; +} last; + +static std::__no_destroy nd_int(5); + +int main(int, char**) { + last.ptr = &nd_int.__get(); + + return 0; +} -- GitLab From 9145514fde484916971e6bb147c18f9235a9f2b5 Mon Sep 17 00:00:00 2001 From: Semyon Khechnev <91785625+s-khechnev@users.noreply.github.com> Date: Sat, 27 Apr 2024 08:29:11 +0300 Subject: [PATCH 120/301] [mlir][arith] fix canonicalization of mulsi_extended for i1 (#90150) There is the `MulSIExtendedRHSOne` canonicalization for arith.mulsi_extended that is defined as follows: `mulsi_extended(x, 1) -> [x, extsi(cmpi slt, x, 0)]`. In the implementation of this, there is a `IsScalarOrSplatOne` constraint for the second argument. However, this constraint does not correctly handle situation when multiplying i1 values. Therefore, an additional constraint has been added which checks the second argument for strict positivity. fix #88732 --- .../Dialect/Arith/IR/ArithCanonicalization.td | 1 + mlir/test/Dialect/Arith/canonicalize.mlir | 22 +++++++++++++++++++ 2 files changed, 23 insertions(+) diff --git a/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td b/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td index caca2ff81964..02d05780a7ac 100644 --- a/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td +++ b/mlir/lib/Dialect/Arith/IR/ArithCanonicalization.td @@ -175,6 +175,7 @@ def MulSIExtendedToMulI : def IsScalarOrSplatOne : Constraint, + CPred<"getIntOrSplatIntValue($0)->isStrictlyPositive()">, CPred<"*getIntOrSplatIntValue($0) == 1">]>>; // mulsi_extended(x, 1) -> [x, extsi(cmpi slt, x, 0)] diff --git a/mlir/test/Dialect/Arith/canonicalize.mlir b/mlir/test/Dialect/Arith/canonicalize.mlir index 79a318565e98..6c4193bc06ca 100644 --- a/mlir/test/Dialect/Arith/canonicalize.mlir +++ b/mlir/test/Dialect/Arith/canonicalize.mlir @@ -1223,6 +1223,28 @@ func.func @mulsiExtendedOneRhsSplat(%arg0: vector<3xi32>) -> (vector<3xi32>, vec return %low, %high : vector<3xi32>, vector<3xi32> } +// CHECK-LABEL: @mulsiExtendedOneRhsI1 +// CHECK-SAME: (%[[ARG:.+]]: i1) -> (i1, i1) +// CHECK-NEXT: %[[T:.+]] = arith.constant true +// CHECK-NEXT: %[[LOW:.+]], %[[HIGH:.+]] = arith.mulsi_extended %[[ARG]], %[[T]] : i1 +// CHECK-NEXT: return %[[LOW]], %[[HIGH]] : i1, i1 +func.func @mulsiExtendedOneRhsI1(%arg0: i1) -> (i1, i1) { + %one = arith.constant true + %low, %high = arith.mulsi_extended %arg0, %one: i1 + return %low, %high : i1, i1 +} + +// CHECK-LABEL: @mulsiExtendedOneRhsSplatI1 +// CHECK-SAME: (%[[ARG:.+]]: vector<3xi1>) -> (vector<3xi1>, vector<3xi1>) +// CHECK-NEXT: %[[TS:.+]] = arith.constant dense : vector<3xi1> +// CHECK-NEXT: %[[LOW:.+]], %[[HIGH:.+]] = arith.mulsi_extended %[[ARG]], %[[TS]] : vector<3xi1> +// CHECK-NEXT: return %[[LOW]], %[[HIGH]] : vector<3xi1>, vector<3xi1> +func.func @mulsiExtendedOneRhsSplatI1(%arg0: vector<3xi1>) -> (vector<3xi1>, vector<3xi1>) { + %one = arith.constant dense : vector<3xi1> + %low, %high = arith.mulsi_extended %arg0, %one: vector<3xi1> + return %low, %high : vector<3xi1>, vector<3xi1> +} + // CHECK-LABEL: @mulsiExtendedUnusedHigh // CHECK-SAME: (%[[ARG:.+]]: i32) -> i32 // CHECK-NEXT: %[[RES:.+]] = arith.muli %[[ARG]], %[[ARG]] : i32 -- GitLab From bc349cea7ad83bba9614e82f695d4b608f801102 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Thorsten=20Sch=C3=BCtt?= Date: Sat, 27 Apr 2024 08:39:35 +0200 Subject: [PATCH 121/301] [GlobalIsel] combine insert vector element (#89363) preliminary steps poison symbols --- .../llvm/CodeGen/GlobalISel/CombinerHelper.h | 3 + llvm/include/llvm/CodeGen/GlobalISel/Utils.h | 26 +++++ .../include/llvm/Target/GlobalISel/Combine.td | 33 +++++- .../GlobalISel/CombinerHelperVectorOps.cpp | 25 +++- llvm/lib/CodeGen/GlobalISel/Utils.cpp | 83 +++++++++++++ .../GlobalISel/combine-insert-vec-elt.mir | 110 ++++++++++++++++++ 6 files changed, 277 insertions(+), 3 deletions(-) diff --git a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h index 4b8aec8e8a5d..76e8d1166ae0 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/CombinerHelper.h @@ -853,6 +853,9 @@ public: bool matchExtractVectorElementWithDifferentIndices(const MachineOperand &MO, BuildFnTy &MatchInfo); + /// Combine insert vector element OOB. + bool matchInsertVectorElementOOB(MachineInstr &MI, BuildFnTy &MatchInfo); + private: /// Checks for legality of an indexed variant of \p LdSt. bool isIndexedLoadStoreLegal(GLoadStore &LdSt) const; diff --git a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h index c4174cee5e10..70421a518ab7 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/Utils.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/Utils.h @@ -559,5 +559,31 @@ void salvageDebugInfo(const MachineRegisterInfo &MRI, MachineInstr &MI); /// having only floating-point operands. bool isPreISelGenericFloatingPointOpcode(unsigned Opc); +/// Returns true if \p Reg can create undef or poison from non-undef & +/// non-poison operands. \p ConsiderFlagsAndMetadata controls whether poison +/// producing flags and metadata on the instruction are considered. This can be +/// used to see if the instruction could still introduce undef or poison even +/// without poison generating flags and metadata which might be on the +/// instruction. +bool canCreateUndefOrPoison(Register Reg, const MachineRegisterInfo &MRI, + bool ConsiderFlagsAndMetadata = true); + +/// Returns true if \p Reg can create poison from non-poison operands. +bool canCreatePoison(Register Reg, const MachineRegisterInfo &MRI, + bool ConsiderFlagsAndMetadata = true); + +/// Returns true if \p Reg cannot be poison and undef. +bool isGuaranteedNotToBeUndefOrPoison(Register Reg, + const MachineRegisterInfo &MRI, + unsigned Depth = 0); + +/// Returns true if \p Reg cannot be poison, but may be undef. +bool isGuaranteedNotToBePoison(Register Reg, const MachineRegisterInfo &MRI, + unsigned Depth = 0); + +/// Returns true if \p Reg cannot be undef, but may be poison. +bool isGuaranteedNotToBeUndef(Register Reg, const MachineRegisterInfo &MRI, + unsigned Depth = 0); + } // End namespace llvm. #endif diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td index 31b903e63d99..dbbb3abaa830 100644 --- a/llvm/include/llvm/Target/GlobalISel/Combine.td +++ b/llvm/include/llvm/Target/GlobalISel/Combine.td @@ -1525,11 +1525,39 @@ def combine_shuffle_concat : GICombineRule< [{ return Helper.matchCombineShuffleConcat(*${root}, ${matchinfo}); }]), (apply [{ Helper.applyCombineShuffleConcat(*${root}, ${matchinfo}); }])>; -// match_extract_of_element must be the first! +def insert_vector_element_idx_undef : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (G_IMPLICIT_DEF $idx), + (G_INSERT_VECTOR_ELT $root, $src, $elt, $idx)), + (apply (G_IMPLICIT_DEF $root))>; + +def insert_vector_element_elt_undef : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (G_IMPLICIT_DEF $elt), + (G_INSERT_VECTOR_ELT $root, $src, $elt, $idx), + [{ return isGuaranteedNotToBePoison(${src}.getReg(), MRI); }]), + (apply (GIReplaceReg $root, $src))>; + +def insert_vector_element_extract_vector_element : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (G_EXTRACT_VECTOR_ELT $elt, $src, $idx), + (G_INSERT_VECTOR_ELT $root, $src, $elt, $idx)), + (apply (GIReplaceReg $root, $src))>; + +def insert_vector_elt_oob : GICombineRule< + (defs root:$root, build_fn_matchinfo:$matchinfo), + (match (wip_match_opcode G_INSERT_VECTOR_ELT):$root, + [{ return Helper.matchInsertVectorElementOOB(*${root}, ${matchinfo}); }]), + (apply [{ Helper.applyBuildFn(*${root}, ${matchinfo}); }])>; + +// match_extract_of_element and insert_vector_elt_oob must be the first! def vector_ops_combines: GICombineGroup<[ match_extract_of_element_undef_vector, match_extract_of_element_undef_index, +insert_vector_element_idx_undef, +insert_vector_element_elt_undef, match_extract_of_element, +insert_vector_elt_oob, extract_vector_element_not_const, extract_vector_element_different_indices, extract_vector_element_build_vector2, @@ -1553,7 +1581,8 @@ extract_vector_element_build_vector_trunc5, extract_vector_element_build_vector_trunc6, extract_vector_element_build_vector_trunc7, extract_vector_element_build_vector_trunc8, -extract_vector_element_freeze +extract_vector_element_freeze, +insert_vector_element_extract_vector_element ]>; // FIXME: These should use the custom predicate feature once it lands. diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelperVectorOps.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelperVectorOps.cpp index 123bf21f657c..fb33801a3a33 100644 --- a/llvm/lib/CodeGen/GlobalISel/CombinerHelperVectorOps.cpp +++ b/llvm/lib/CodeGen/GlobalISel/CombinerHelperVectorOps.cpp @@ -77,7 +77,7 @@ bool CombinerHelper::matchExtractVectorElement(MachineInstr &MI, // Fold extractVectorElement(Vector, TOOLARGE) -> undef if (IndexC && VectorTy.isFixedVector() && - IndexC->getZExtValue() >= VectorTy.getNumElements() && + IndexC->uge(VectorTy.getNumElements()) && isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) { // For fixed-length vectors, it's invalid to extract out-of-range elements. MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; @@ -324,3 +324,26 @@ bool CombinerHelper::matchExtractVectorElementWithBuildVectorTrunc( return true; } + +bool CombinerHelper::matchInsertVectorElementOOB(MachineInstr &MI, + BuildFnTy &MatchInfo) { + GInsertVectorElement *Insert = cast(&MI); + + Register Dst = Insert->getReg(0); + LLT DstTy = MRI.getType(Dst); + Register Index = Insert->getIndexReg(); + + if (!DstTy.isFixedVector()) + return false; + + std::optional MaybeIndex = + getIConstantVRegValWithLookThrough(Index, MRI); + + if (MaybeIndex && MaybeIndex->Value.uge(DstTy.getNumElements()) && + isLegalOrBeforeLegalizer({TargetOpcode::G_IMPLICIT_DEF, {DstTy}})) { + MatchInfo = [=](MachineIRBuilder &B) { B.buildUndef(Dst); }; + return true; + } + + return false; +} diff --git a/llvm/lib/CodeGen/GlobalISel/Utils.cpp b/llvm/lib/CodeGen/GlobalISel/Utils.cpp index ae43e9ccf611..4e3781cb4e9d 100644 --- a/llvm/lib/CodeGen/GlobalISel/Utils.cpp +++ b/llvm/lib/CodeGen/GlobalISel/Utils.cpp @@ -12,6 +12,7 @@ #include "llvm/CodeGen/GlobalISel/Utils.h" #include "llvm/ADT/APFloat.h" #include "llvm/ADT/APInt.h" +#include "llvm/Analysis/ValueTracking.h" #include "llvm/CodeGen/CodeGenCommonISel.h" #include "llvm/CodeGen/GlobalISel/GISelChangeObserver.h" #include "llvm/CodeGen/GlobalISel/GISelKnownBits.h" @@ -28,6 +29,7 @@ #include "llvm/CodeGen/StackProtector.h" #include "llvm/CodeGen/TargetInstrInfo.h" #include "llvm/CodeGen/TargetLowering.h" +#include "llvm/CodeGen/TargetOpcodes.h" #include "llvm/CodeGen/TargetPassConfig.h" #include "llvm/CodeGen/TargetRegisterInfo.h" #include "llvm/IR/Constants.h" @@ -1709,3 +1711,84 @@ bool llvm::isPreISelGenericFloatingPointOpcode(unsigned Opc) { return false; } } + +namespace { +enum class UndefPoisonKind { + PoisonOnly = (1 << 0), + UndefOnly = (1 << 1), + UndefOrPoison = PoisonOnly | UndefOnly, +}; +} + +[[maybe_unused]] static bool includesPoison(UndefPoisonKind Kind) { + return (unsigned(Kind) & unsigned(UndefPoisonKind::PoisonOnly)) != 0; +} + +[[maybe_unused]] static bool includesUndef(UndefPoisonKind Kind) { + return (unsigned(Kind) & unsigned(UndefPoisonKind::UndefOnly)) != 0; +} + +static bool canCreateUndefOrPoison(Register Reg, const MachineRegisterInfo &MRI, + bool ConsiderFlagsAndMetadata, + UndefPoisonKind Kind) { + MachineInstr *RegDef = MRI.getVRegDef(Reg); + + switch (RegDef->getOpcode()) { + case TargetOpcode::G_FREEZE: + return false; + default: + return true; + } +} + +static bool isGuaranteedNotToBeUndefOrPoison(Register Reg, + const MachineRegisterInfo &MRI, + unsigned Depth, + UndefPoisonKind Kind) { + if (Depth >= MaxAnalysisRecursionDepth) + return false; + + MachineInstr *RegDef = MRI.getVRegDef(Reg); + + switch (RegDef->getOpcode()) { + case TargetOpcode::G_FREEZE: + return true; + case TargetOpcode::G_IMPLICIT_DEF: + return !includesUndef(Kind); + default: + return false; + } +} + +bool llvm::canCreateUndefOrPoison(Register Reg, const MachineRegisterInfo &MRI, + bool ConsiderFlagsAndMetadata) { + return ::canCreateUndefOrPoison(Reg, MRI, ConsiderFlagsAndMetadata, + UndefPoisonKind::UndefOrPoison); +} + +bool canCreatePoison(Register Reg, const MachineRegisterInfo &MRI, + bool ConsiderFlagsAndMetadata = true) { + return ::canCreateUndefOrPoison(Reg, MRI, ConsiderFlagsAndMetadata, + UndefPoisonKind::PoisonOnly); +} + +bool llvm::isGuaranteedNotToBeUndefOrPoison(Register Reg, + const MachineRegisterInfo &MRI, + unsigned Depth) { + return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth, + UndefPoisonKind::UndefOrPoison); +} + +bool llvm::isGuaranteedNotToBePoison(Register Reg, + const MachineRegisterInfo &MRI, + unsigned Depth) { + return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth, + UndefPoisonKind::PoisonOnly); +} + +bool llvm::isGuaranteedNotToBeUndef(Register Reg, + const MachineRegisterInfo &MRI, + unsigned Depth) { + return ::isGuaranteedNotToBeUndefOrPoison(Reg, MRI, Depth, + UndefPoisonKind::UndefOnly); +} diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir index 06fb2ce161c2..0c67a867580c 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir +++ b/llvm/test/CodeGen/AArch64/GlobalISel/combine-insert-vec-elt.mir @@ -201,3 +201,113 @@ body: | RET_ReallyLR ... +--- +name: test_idx_undef +body: | + bb.1: + liveins: $x0 + ; CHECK-LABEL: name: test_idx_undef + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: RET_ReallyLR + %3:_(s8) = G_CONSTANT i8 127 + %2:_(<32 x s8>) = G_BUILD_VECTOR %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8) + %4:_(s8) = G_CONSTANT i8 -128 + %5:_(s64) = G_IMPLICIT_DEF + %0:_(p0) = COPY $x0 + %1:_(<32 x s8>) = G_INSERT_VECTOR_ELT %2, %4(s8), %5(s64) + G_STORE %1(<32 x s8>), %0(p0) :: (store (<32 x s8>)) + RET_ReallyLR + +... +--- +name: test_elt_undef +body: | + bb.1: + liveins: $x0 + ; CHECK-LABEL: name: test_elt_undef + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 127 + ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s8) = G_IMPLICIT_DEF + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[DEF]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8) + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<32 x s8>), [[COPY]](p0) :: (store (<32 x s8>)) + ; CHECK-NEXT: RET_ReallyLR + %3:_(s8) = G_CONSTANT i8 127 + %2:_(<32 x s8>) = G_BUILD_VECTOR %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8) + %4:_(s8) = G_IMPLICIT_DEF + %5:_(s64) = G_CONSTANT i64 3 + %0:_(p0) = COPY $x0 + %1:_(<32 x s8>) = G_INSERT_VECTOR_ELT %2, %4(s8), %5(s64) + G_STORE %1(<32 x s8>), %0(p0) :: (store (<32 x s8>)) + RET_ReallyLR + +... +--- +name: test_elt_undef_with_freeze +body: | + bb.1: + liveins: $x0 + ; CHECK-LABEL: name: test_elt_undef_with_freeze + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 127 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8) + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[FREEZE:%[0-9]+]]:_(<32 x s8>) = G_FREEZE [[BUILD_VECTOR]] + ; CHECK-NEXT: G_STORE [[FREEZE]](<32 x s8>), [[COPY]](p0) :: (store (<32 x s8>)) + ; CHECK-NEXT: RET_ReallyLR + %3:_(s8) = G_CONSTANT i8 127 + %2:_(<32 x s8>) = G_BUILD_VECTOR %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8) + %4:_(s8) = G_IMPLICIT_DEF + %5:_(s64) = G_CONSTANT i64 3 + %0:_(p0) = COPY $x0 + %9:_(<32 x s8>) = G_FREEZE %2 + %1:_(<32 x s8>) = G_INSERT_VECTOR_ELT %9, %4(s8), %5(s64) + G_STORE %1(<32 x s8>), %0(p0) :: (store (<32 x s8>)) + RET_ReallyLR + +... +--- +name: test_insert_extract +body: | + bb.1: + liveins: $x0 + ; CHECK-LABEL: name: test_insert_extract + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[C:%[0-9]+]]:_(s8) = G_CONSTANT i8 127 + ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0 + ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<32 x s8>) = G_BUILD_VECTOR [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8), [[C]](s8) + ; CHECK-NEXT: G_STORE [[BUILD_VECTOR]](<32 x s8>), [[COPY]](p0) :: (store (<32 x s8>)) + ; CHECK-NEXT: RET_ReallyLR + %3:_(s8) = G_CONSTANT i8 127 + %2:_(<32 x s8>) = G_BUILD_VECTOR %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8) + %5:_(s64) = G_CONSTANT i64 3 + %4:_(s8) = G_EXTRACT_VECTOR_ELT %2, %5 + %0:_(p0) = COPY $x0 + %1:_(<32 x s8>) = G_INSERT_VECTOR_ELT %2, %4(s8), %5(s64) + G_STORE %1(<32 x s8>), %0(p0) :: (store (<32 x s8>)) + RET_ReallyLR + +... +--- +name: test_idx_oob +body: | + bb.1: + liveins: $x0 + ; CHECK-LABEL: name: test_idx_oob + ; CHECK: liveins: $x0 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: RET_ReallyLR + %3:_(s8) = G_CONSTANT i8 127 + %2:_(<32 x s8>) = G_BUILD_VECTOR %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8), %3(s8) + %4:_(s8) = G_CONSTANT i8 -128 + %5:_(s64) = G_CONSTANT i64 1024 + %0:_(p0) = COPY $x0 + %1:_(<32 x s8>) = G_INSERT_VECTOR_ELT %2, %4(s8), %5(s64) + G_STORE %1(<32 x s8>), %0(p0) :: (store (<32 x s8>)) + RET_ReallyLR + +... -- GitLab From 7aa6896dd7bcdcb1d09f4f98e356c43d723d9d6b Mon Sep 17 00:00:00 2001 From: Vitaly Buka Date: Sat, 27 Apr 2024 00:15:08 -0700 Subject: [PATCH 122/301] Revert "[memprof] Introduce FrameIdConverter and CallStackIdConverter" (#90318) Reverts llvm/llvm-project#90307 Breaks bots https://lab.llvm.org/buildbot/#/builders/5/builds/42943 --- llvm/include/llvm/ProfileData/MemProf.h | 58 ----------------- llvm/include/llvm/ProfileData/MemProfReader.h | 14 +++-- llvm/lib/ProfileData/InstrProfReader.cpp | 44 +++++++++---- llvm/unittests/ProfileData/InstrProfTest.cpp | 62 ++++++++++++++----- llvm/unittests/ProfileData/MemProfTest.cpp | 36 ++++++++--- 5 files changed, 117 insertions(+), 97 deletions(-) diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index 8b00faf2a219..d378c3696f8d 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -737,64 +737,6 @@ public: // Compute a CallStackId for a given call stack. CallStackId hashCallStack(ArrayRef CS); -namespace detail { -// "Dereference" the iterator from DenseMap or OnDiskChainedHashTable. We have -// to do so in one of two different ways depending on the type of the hash -// table. -template -value_type DerefIterator(IterTy Iter) { - using deref_type = llvm::remove_cvref_t; - if constexpr (std::is_same_v) - return *Iter; - else - return Iter->second; -} -} // namespace detail - -// A function object that returns a frame for a given FrameId. -template struct FrameIdConverter { - std::optional LastUnmappedId; - MapTy ⤅ - - FrameIdConverter() = delete; - FrameIdConverter(MapTy &Map) : Map(Map) {} - - Frame operator()(FrameId Id) { - auto Iter = Map.find(Id); - if (Iter == Map.end()) { - LastUnmappedId = Id; - return Frame(0, 0, 0, false); - } - return detail::DerefIterator(Iter); - } -}; - -// A function object that returns a call stack for a given CallStackId. -template struct CallStackIdConverter { - std::optional LastUnmappedId; - MapTy ⤅ - std::function FrameIdToFrame; - - CallStackIdConverter() = delete; - CallStackIdConverter(MapTy &Map, std::function FrameIdToFrame) - : Map(Map), FrameIdToFrame(FrameIdToFrame) {} - - llvm::SmallVector operator()(CallStackId CSId) { - llvm::SmallVector Frames; - auto CSIter = Map.find(CSId); - if (CSIter == Map.end()) { - LastUnmappedId = CSId; - } else { - llvm::SmallVector CS = - detail::DerefIterator>(CSIter); - Frames.reserve(CS.size()); - for (FrameId Id : CS) - Frames.push_back(FrameIdToFrame(Id)); - } - return Frames; - } -}; - // Verify that each CallStackId is computed with hashCallStack. This function // is intended to help transition from CallStack to CSId in // IndexedAllocationInfo. diff --git a/llvm/include/llvm/ProfileData/MemProfReader.h b/llvm/include/llvm/ProfileData/MemProfReader.h index b42e4f597774..444c58e8bdc8 100644 --- a/llvm/include/llvm/ProfileData/MemProfReader.h +++ b/llvm/include/llvm/ProfileData/MemProfReader.h @@ -76,16 +76,20 @@ public: Callback = std::bind(&MemProfReader::idToFrame, this, std::placeholders::_1); - memprof::CallStackIdConverter CSIdConv( - CSIdToCallStack, Callback); + auto CallStackCallback = [&](CallStackId CSId) { + llvm::SmallVector CallStack; + auto Iter = CSIdToCallStack.find(CSId); + assert(Iter != CSIdToCallStack.end()); + for (FrameId Id : Iter->second) + CallStack.push_back(Callback(Id)); + return CallStack; + }; const IndexedMemProfRecord &IndexedRecord = Iter->second; GuidRecord = { Iter->first, - IndexedRecord.toMemProfRecord(CSIdConv), + IndexedRecord.toMemProfRecord(CallStackCallback), }; - if (CSIdConv.LastUnmappedId) - return make_error(instrprof_error::hash_mismatch); Iter++; return Error::success(); } diff --git a/llvm/lib/ProfileData/InstrProfReader.cpp b/llvm/lib/ProfileData/InstrProfReader.cpp index 440be2f255d3..cefb6af12d00 100644 --- a/llvm/lib/ProfileData/InstrProfReader.cpp +++ b/llvm/lib/ProfileData/InstrProfReader.cpp @@ -1520,35 +1520,53 @@ IndexedMemProfReader::getMemProfRecord(const uint64_t FuncNameHash) const { // Setup a callback to convert from frame ids to frame using the on-disk // FrameData hash table. - memprof::FrameIdConverter FrameIdConv( - *MemProfFrameTable.get()); + std::optional LastUnmappedFrameId; + auto IdToFrameCallback = [&](const memprof::FrameId Id) { + auto FrIter = MemProfFrameTable->find(Id); + if (FrIter == MemProfFrameTable->end()) { + LastUnmappedFrameId = Id; + return memprof::Frame(0, 0, 0, false); + } + return *FrIter; + }; // Setup a callback to convert call stack ids to call stacks using the on-disk // hash table. - memprof::CallStackIdConverter CSIdConv( - *MemProfCallStackTable.get(), FrameIdConv); + std::optional LastUnmappedCSId; + auto CSIdToCallStackCallback = [&](memprof::CallStackId CSId) { + llvm::SmallVector Frames; + auto CSIter = MemProfCallStackTable->find(CSId); + if (CSIter == MemProfCallStackTable->end()) { + LastUnmappedCSId = CSId; + } else { + const llvm::SmallVector &CS = *CSIter; + Frames.reserve(CS.size()); + for (memprof::FrameId Id : CS) + Frames.push_back(IdToFrameCallback(Id)); + } + return Frames; + }; const memprof::IndexedMemProfRecord IndexedRecord = *Iter; memprof::MemProfRecord Record; if (MemProfCallStackTable) - Record = IndexedRecord.toMemProfRecord(CSIdConv); + Record = IndexedRecord.toMemProfRecord(CSIdToCallStackCallback); else - Record = memprof::MemProfRecord(IndexedRecord, FrameIdConv); + Record = memprof::MemProfRecord(IndexedRecord, IdToFrameCallback); // Check that all frame ids were successfully converted to frames. - if (FrameIdConv.LastUnmappedId) { - return make_error( - instrprof_error::hash_mismatch, - "memprof frame not found for frame id " + - Twine(*FrameIdConv.LastUnmappedId)); + if (LastUnmappedFrameId) { + return make_error(instrprof_error::hash_mismatch, + "memprof frame not found for frame id " + + Twine(*LastUnmappedFrameId)); } // Check that all call stack ids were successfully converted to call stacks. - if (CSIdConv.LastUnmappedId) { + if (LastUnmappedCSId) { return make_error( instrprof_error::hash_mismatch, "memprof call stack not found for call stack id " + - Twine(*CSIdConv.LastUnmappedId)); + Twine(*LastUnmappedCSId)); } return Record; } diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index acc633de11b6..edc427dcbc45 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -495,6 +495,44 @@ TEST_F(InstrProfTest, test_memprof_v0) { EXPECT_THAT(WantRecord, EqualsRecord(Record)); } +struct CallStackIdConverter { + std::optional LastUnmappedFrameId; + std::optional LastUnmappedCSId; + + const FrameIdMapTy &IdToFrameMap; + const CallStackIdMapTy &CSIdToCallStackMap; + + CallStackIdConverter() = delete; + CallStackIdConverter(const FrameIdMapTy &IdToFrameMap, + const CallStackIdMapTy &CSIdToCallStackMap) + : IdToFrameMap(IdToFrameMap), CSIdToCallStackMap(CSIdToCallStackMap) {} + + llvm::SmallVector + operator()(::llvm::memprof::CallStackId CSId) { + auto IdToFrameCallback = [&](const memprof::FrameId Id) { + auto Iter = IdToFrameMap.find(Id); + if (Iter == IdToFrameMap.end()) { + LastUnmappedFrameId = Id; + return memprof::Frame(0, 0, 0, false); + } + return Iter->second; + }; + + llvm::SmallVector Frames; + auto CSIter = CSIdToCallStackMap.find(CSId); + if (CSIter == CSIdToCallStackMap.end()) { + LastUnmappedCSId = CSId; + } else { + const ::llvm::SmallVector<::llvm::memprof::FrameId> &CS = + CSIter->getSecond(); + Frames.reserve(CS.size()); + for (::llvm::memprof::FrameId Id : CS) + Frames.push_back(IdToFrameCallback(Id)); + } + return Frames; + } +}; + TEST_F(InstrProfTest, test_memprof_v2_full_schema) { const MemInfoBlock MIB = makeFullMIB(); @@ -524,16 +562,14 @@ TEST_F(InstrProfTest, test_memprof_v2_full_schema) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - memprof::FrameIdConverter FrameIdConv(IdToFrameMap); - memprof::CallStackIdConverter CSIdConv( - CSIdToCallStackMap, FrameIdConv); + CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); const ::llvm::memprof::MemProfRecord WantRecord = IndexedMR.toMemProfRecord(CSIdConv); - ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt) - << "could not map frame id: " << *FrameIdConv.LastUnmappedId; - ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt) - << "could not map call stack id: " << *CSIdConv.LastUnmappedId; + ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) + << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; + ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } @@ -566,16 +602,14 @@ TEST_F(InstrProfTest, test_memprof_v2_partial_schema) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - memprof::FrameIdConverter FrameIdConv(IdToFrameMap); - memprof::CallStackIdConverter CSIdConv( - CSIdToCallStackMap, FrameIdConv); + CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); const ::llvm::memprof::MemProfRecord WantRecord = IndexedMR.toMemProfRecord(CSIdConv); - ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt) - << "could not map frame id: " << *FrameIdConv.LastUnmappedId; - ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt) - << "could not map call stack id: " << *CSIdConv.LastUnmappedId; + ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) + << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; + ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } diff --git a/llvm/unittests/ProfileData/MemProfTest.cpp b/llvm/unittests/ProfileData/MemProfTest.cpp index d031049cea14..98dacd3511e1 100644 --- a/llvm/unittests/ProfileData/MemProfTest.cpp +++ b/llvm/unittests/ProfileData/MemProfTest.cpp @@ -502,15 +502,37 @@ TEST(MemProf, IndexedMemProfRecordToMemProfRecord) { IndexedRecord.CallSiteIds.push_back(llvm::memprof::hashCallStack(CS3)); IndexedRecord.CallSiteIds.push_back(llvm::memprof::hashCallStack(CS4)); - llvm::memprof::FrameIdConverter FrameIdConv(FrameIdMap); - llvm::memprof::CallStackIdConverter CSIdConv( - CallStackIdMap, FrameIdConv); - - MemProfRecord Record = IndexedRecord.toMemProfRecord(CSIdConv); + bool CSIdMissing = false; + bool FrameIdMissing = false; + + auto Callback = [&](CallStackId CSId) -> llvm::SmallVector { + llvm::SmallVector CallStack; + llvm::SmallVector FrameIds; + + auto Iter = CallStackIdMap.find(CSId); + if (Iter == CallStackIdMap.end()) + CSIdMissing = true; + else + FrameIds = Iter->second; + + for (FrameId Id : FrameIds) { + Frame F(0, 0, 0, false); + auto Iter = FrameIdMap.find(Id); + if (Iter == FrameIdMap.end()) + FrameIdMissing = true; + else + F = Iter->second; + CallStack.push_back(F); + } + + return CallStack; + }; + + MemProfRecord Record = IndexedRecord.toMemProfRecord(Callback); // Make sure that all lookups are successful. - ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt); - ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt); + ASSERT_FALSE(CSIdMissing); + ASSERT_FALSE(FrameIdMissing); // Verify the contents of Record. ASSERT_THAT(Record.AllocSites, SizeIs(2)); -- GitLab From 9bb84cec1b5375c24e5fa9cf7700070d9d1b4184 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sat, 27 Apr 2024 00:37:06 -0700 Subject: [PATCH 123/301] [ADT] Add StringRef::{starts,ends}_with(char) (#90311) This patch adds to StringRef the equivalent of std::string_view::{starts,ends}_with(char) in C++20. --- llvm/include/llvm/ADT/StringRef.h | 6 ++++++ llvm/unittests/ADT/StringRefTest.cpp | 4 ++++ 2 files changed, 10 insertions(+) diff --git a/llvm/include/llvm/ADT/StringRef.h b/llvm/include/llvm/ADT/StringRef.h index 0360174c5231..04496c76e072 100644 --- a/llvm/include/llvm/ADT/StringRef.h +++ b/llvm/include/llvm/ADT/StringRef.h @@ -258,6 +258,9 @@ namespace llvm { return Length >= Prefix.Length && compareMemory(Data, Prefix.Data, Prefix.Length) == 0; } + [[nodiscard]] bool starts_with(char Prefix) const { + return !empty() && front() == Prefix; + } /// Check if this string starts with the given \p Prefix, ignoring case. [[nodiscard]] bool starts_with_insensitive(StringRef Prefix) const; @@ -268,6 +271,9 @@ namespace llvm { compareMemory(end() - Suffix.Length, Suffix.Data, Suffix.Length) == 0; } + [[nodiscard]] bool ends_with(char Suffix) const { + return !empty() && back() == Suffix; + } /// Check if this string ends with the given \p Suffix, ignoring case. [[nodiscard]] bool ends_with_insensitive(StringRef Suffix) const; diff --git a/llvm/unittests/ADT/StringRefTest.cpp b/llvm/unittests/ADT/StringRefTest.cpp index 8df71e8ad033..fa537e816fc8 100644 --- a/llvm/unittests/ADT/StringRefTest.cpp +++ b/llvm/unittests/ADT/StringRefTest.cpp @@ -368,6 +368,8 @@ TEST(StringRefTest, StartsWith) { EXPECT_TRUE(Str.starts_with("he")); EXPECT_FALSE(Str.starts_with("helloworld")); EXPECT_FALSE(Str.starts_with("hi")); + EXPECT_TRUE(Str.starts_with('h')); + EXPECT_FALSE(Str.starts_with('i')); } TEST(StringRefTest, StartsWithInsensitive) { @@ -421,6 +423,8 @@ TEST(StringRefTest, EndsWith) { EXPECT_FALSE(Str.ends_with("helloworld")); EXPECT_FALSE(Str.ends_with("worldhello")); EXPECT_FALSE(Str.ends_with("so")); + EXPECT_TRUE(Str.ends_with('o')); + EXPECT_FALSE(Str.ends_with('p')); } TEST(StringRefTest, EndsWithInsensitive) { -- GitLab From 840032419d3717a81e48db6c165dab006252936b Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Sat, 27 Apr 2024 09:51:59 +0200 Subject: [PATCH 124/301] [libc++][NFC] Rename __find_impl to __find (#90163) For most algorithms we've just added underscores to the detail function. This changes `std::find` to match that pattern. --- libcxx/include/__algorithm/find.h | 20 +++++++++----------- libcxx/include/__algorithm/ranges_find.h | 4 ++-- libcxx/include/__string/char_traits.h | 4 ++-- 3 files changed, 13 insertions(+), 15 deletions(-) diff --git a/libcxx/include/__algorithm/find.h b/libcxx/include/__algorithm/find.h index d60356873132..7f58dbb13a57 100644 --- a/libcxx/include/__algorithm/find.h +++ b/libcxx/include/__algorithm/find.h @@ -43,7 +43,7 @@ _LIBCPP_BEGIN_NAMESPACE_STD // generic implementation template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Iter -__find_impl(_Iter __first, _Sent __last, const _Tp& __value, _Proj& __proj) { +__find(_Iter __first, _Sent __last, const _Tp& __value, _Proj& __proj) { for (; __first != __last; ++__first) if (std::__invoke(__proj, *__first) == __value) break; @@ -57,8 +57,7 @@ template ::value && __libcpp_is_trivially_equality_comparable<_Tp, _Up>::value && sizeof(_Tp) == 1, int> = 0> -_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp* -__find_impl(_Tp* __first, _Tp* __last, const _Up& __value, _Proj&) { +_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp* __find(_Tp* __first, _Tp* __last, const _Up& __value, _Proj&) { if (auto __ret = std::__constexpr_memchr(__first, __value, __last - __first)) return __ret; return __last; @@ -71,8 +70,7 @@ template ::value && __libcpp_is_trivially_equality_comparable<_Tp, _Up>::value && sizeof(_Tp) == sizeof(wchar_t) && _LIBCPP_ALIGNOF(_Tp) >= _LIBCPP_ALIGNOF(wchar_t), int> = 0> -_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp* -__find_impl(_Tp* __first, _Tp* __last, const _Up& __value, _Proj&) { +_LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp* __find(_Tp* __first, _Tp* __last, const _Up& __value, _Proj&) { if (auto __ret = std::__constexpr_wmemchr(__first, __value, __last - __first)) return __ret; return __last; @@ -89,10 +87,10 @@ template ::value == is_signed<_Up>::value, int> = 0> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _Tp* -__find_impl(_Tp* __first, _Tp* __last, const _Up& __value, _Proj& __proj) { +__find(_Tp* __first, _Tp* __last, const _Up& __value, _Proj& __proj) { if (__value < numeric_limits<_Tp>::min() || __value > numeric_limits<_Tp>::max()) return __last; - return std::__find_impl(__first, __last, _Tp(__value), __proj); + return std::__find(__first, __last, _Tp(__value), __proj); } // __bit_iterator implementation @@ -134,7 +132,7 @@ __find_bool(__bit_iterator<_Cp, _IsConst> __first, typename _Cp::size_type __n) template ::value, int> = 0> inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 __bit_iterator<_Cp, _IsConst> -__find_impl(__bit_iterator<_Cp, _IsConst> __first, __bit_iterator<_Cp, _IsConst> __last, const _Tp& __value, _Proj&) { +__find(__bit_iterator<_Cp, _IsConst> __first, __bit_iterator<_Cp, _IsConst> __last, const _Tp& __value, _Proj&) { if (static_cast(__value)) return std::__find_bool(__first, static_cast(__last - __first)); return std::__find_bool(__first, static_cast(__last - __first)); @@ -150,7 +148,7 @@ template ::value, int> = 0> _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX14 _SegmentedIterator -__find_impl(_SegmentedIterator __first, _SegmentedIterator __last, const _Tp& __value, _Proj& __proj) { +__find(_SegmentedIterator __first, _SegmentedIterator __last, const _Tp& __value, _Proj& __proj) { return std::__find_segment_if(std::move(__first), std::move(__last), __find_segment<_Tp>(__value), __proj); } @@ -163,7 +161,7 @@ struct __find_segment { template _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR _InputIterator operator()(_InputIterator __first, _InputIterator __last, _Proj& __proj) const { - return std::__find_impl(__first, __last, __value_, __proj); + return std::__find(__first, __last, __value_, __proj); } }; @@ -173,7 +171,7 @@ _LIBCPP_NODISCARD inline _LIBCPP_HIDE_FROM_ABI _LIBCPP_CONSTEXPR_SINCE_CXX20 _In find(_InputIterator __first, _InputIterator __last, const _Tp& __value) { __identity __proj; return std::__rewrap_iter( - __first, std::__find_impl(std::__unwrap_iter(__first), std::__unwrap_iter(__last), __value, __proj)); + __first, std::__find(std::__unwrap_iter(__first), std::__unwrap_iter(__last), __value, __proj)); } _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/include/__algorithm/ranges_find.h b/libcxx/include/__algorithm/ranges_find.h index e1383eb4b071..6b0d5efe37ab 100644 --- a/libcxx/include/__algorithm/ranges_find.h +++ b/libcxx/include/__algorithm/ranges_find.h @@ -44,9 +44,9 @@ struct __fn { if constexpr (forward_iterator<_Iter>) { auto [__first_un, __last_un] = std::__unwrap_range(__first, std::move(__last)); return std::__rewrap_range<_Sent>( - std::move(__first), std::__find_impl(std::move(__first_un), std::move(__last_un), __value, __proj)); + std::move(__first), std::__find(std::move(__first_un), std::move(__last_un), __value, __proj)); } else { - return std::__find_impl(std::move(__first), std::move(__last), __value, __proj); + return std::__find(std::move(__first), std::move(__last), __value, __proj); } } diff --git a/libcxx/include/__string/char_traits.h b/libcxx/include/__string/char_traits.h index 1fd22d518e1a..9d347b188ee1 100644 --- a/libcxx/include/__string/char_traits.h +++ b/libcxx/include/__string/char_traits.h @@ -344,7 +344,7 @@ struct _LIBCPP_TEMPLATE_VIS char_traits { _LIBCPP_HIDE_FROM_ABI static _LIBCPP_CONSTEXPR_SINCE_CXX17 const char_type* find(const char_type* __s, size_t __n, const char_type& __a) _NOEXCEPT { __identity __proj; - const char_type* __match = std::__find_impl(__s, __s + __n, __a, __proj); + const char_type* __match = std::__find(__s, __s + __n, __a, __proj); if (__match == __s + __n) return nullptr; return __match; @@ -430,7 +430,7 @@ struct _LIBCPP_TEMPLATE_VIS char_traits { _LIBCPP_HIDE_FROM_ABI static _LIBCPP_CONSTEXPR_SINCE_CXX17 const char_type* find(const char_type* __s, size_t __n, const char_type& __a) _NOEXCEPT { __identity __proj; - const char_type* __match = std::__find_impl(__s, __s + __n, __a, __proj); + const char_type* __match = std::__find(__s, __s + __n, __a, __proj); if (__match == __s + __n) return nullptr; return __match; -- GitLab From 715219482b99ceef9bf83a2ff68c64c8faa930cd Mon Sep 17 00:00:00 2001 From: Cinhi Young Date: Sat, 27 Apr 2024 15:53:02 +0800 Subject: [PATCH 125/301] [MIPS] match llvm.{min,max}num with {min,max}.fmt for R6 (#89021) - The behavior is similar to UCOMISD on x86, which is also used to compare two fp values, specifically on handling of NaNs. - Update related tests regarding this change. - The further goal is to implement `llvm.minimum` and `llvm.maximum` intrinsics for MIPS R6 and Pre-R6. Part of https://github.com/llvm/llvm-project/issues/64207 --- llvm/lib/Target/Mips/Mips32r6InstrInfo.td | 16 + llvm/lib/Target/Mips/MipsISelLowering.cpp | 9 + llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll | 69 +++ llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll | 487 +++++++++++++-------- 4 files changed, 395 insertions(+), 186 deletions(-) create mode 100644 llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll diff --git a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td index bef7607118ce..f609305bfee4 100644 --- a/llvm/lib/Target/Mips/Mips32r6InstrInfo.td +++ b/llvm/lib/Target/Mips/Mips32r6InstrInfo.td @@ -1117,6 +1117,22 @@ def : MipsPat<(select i32:$cond, immz, i32:$f), ISA_MIPS32R6; } +// llvm.fmin/fmax operations. +let AdditionalPredicates = [NotInMicroMips] in { + def : MipsPat<(fmaxnum f32:$lhs, f32:$rhs), + (MAX_S f32:$lhs, f32:$rhs)>, + ISA_MIPS32R6; + def : MipsPat<(fmaxnum f64:$lhs, f64:$rhs), + (MAX_D f64:$lhs, f64:$rhs)>, + ISA_MIPS32R6; + def : MipsPat<(fminnum f32:$lhs, f32:$rhs), + (MIN_S f32:$lhs, f32:$rhs)>, + ISA_MIPS32R6; + def : MipsPat<(fminnum f64:$lhs, f64:$rhs), + (MIN_D f64:$lhs, f64:$rhs)>, + ISA_MIPS32R6; +} + // Pseudo instructions let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1, hasDelaySlot = 1, hasExtraSrcRegAllocReq = 1, isCTI = 1, Defs = [AT], hasPostISelHook = 1 in { diff --git a/llvm/lib/Target/Mips/MipsISelLowering.cpp b/llvm/lib/Target/Mips/MipsISelLowering.cpp index 7bc66b2d9f4b..8f7c47370ee5 100644 --- a/llvm/lib/Target/Mips/MipsISelLowering.cpp +++ b/llvm/lib/Target/Mips/MipsISelLowering.cpp @@ -358,6 +358,15 @@ MipsTargetLowering::MipsTargetLowering(const MipsTargetMachine &TM, setOperationAction(ISD::FCOPYSIGN, MVT::f64, Custom); setOperationAction(ISD::FP_TO_SINT, MVT::i32, Custom); + // Lower fmin and fmax operations for MIPS R6. + // Instructions are defined but never used. + if (Subtarget.hasMips32r6() || Subtarget.hasMips64r6()) { + setOperationAction(ISD::FMINNUM, MVT::f32, Legal); + setOperationAction(ISD::FMINNUM, MVT::f64, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f32, Legal); + setOperationAction(ISD::FMAXNUM, MVT::f64, Legal); + } + if (Subtarget.isGP64bit()) { setOperationAction(ISD::GlobalAddress, MVT::i64, Custom); setOperationAction(ISD::BlockAddress, MVT::i64, Custom); diff --git a/llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll b/llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll new file mode 100644 index 000000000000..e14e89916e6d --- /dev/null +++ b/llvm/test/CodeGen/Mips/mipsr6-minmaxnum.ll @@ -0,0 +1,69 @@ +; RUN: llc %s -mtriple=mipsisa32r6el-linux-gnu -o - | \ +; RUN: FileCheck %s --check-prefix=MIPS32R6EL +; RUN: llc %s -mtriple=mipsisa64r6el-linux-gnuabi64 -o - | \ +; RUN: FileCheck %s --check-prefix=MIPS64R6EL + +define float @mins(float %x, float %y) { +; MIPS32R6EL-LABEL: mins +; MIPS32R6EL: # %bb.0: +; MIPS32R6EL-NEXT: jr $ra +; MIPS32R6EL-NEXT: min.s $f0, $f12, $f14 +; +; MIPS64R6EL-LABEL: mins +; MIPS64R6EL: # %bb.0: +; MIPS64R6EL-NEXT: jr $ra +; MIPS64R6EL-NEXT: min.s $f0, $f12, $f13 + + %r = tail call float @llvm.minnum.f32(float %x, float %y) + ret float %r +} + +define float @maxs(float %x, float %y) { +; MIPS32R6EL-LABEL: maxs +; MIPS32R6EL: # %bb.0: +; MIPS32R6EL-NEXT: jr $ra +; MIPS32R6EL-NEXT: max.s $f0, $f12, $f14 +; +; MIPS64R6EL-LABEL: maxs +; MIPS64R6EL: # %bb.0: +; MIPS64R6EL-NEXT: jr $ra +; MIPS64R6EL-NEXT: max.s $f0, $f12, $f13 + + %r = tail call float @llvm.maxnum.f32(float %x, float %y) + ret float %r +} + +define double @mind(double %x, double %y) { +; MIPS32R6EL-LABEL: mind +; MIPS32R6EL: # %bb.0: +; MIPS32R6EL-NEXT: jr $ra +; MIPS32R6EL-NEXT: min.d $f0, $f12, $f14 +; +; MIPS64R6EL-LABEL: mind +; MIPS64R6EL: # %bb.0: +; MIPS64R6EL-NEXT: jr $ra +; MIPS64R6EL-NEXT: min.d $f0, $f12, $f13 + + %r = tail call double @llvm.minnum.f64(double %x, double %y) + ret double %r +} + +define double @maxd(double %x, double %y) { +; MIPS32R6EL-LABEL: maxd +; MIPS32R6EL: # %bb.0: +; MIPS32R6EL-NEXT: jr $ra +; MIPS32R6EL-NEXT: max.d $f0, $f12, $f14 +; +; MIPS64R6EL-LABEL: maxd +; MIPS64R6EL: # %bb.0: +; MIPS64R6EL-NEXT: jr $ra +; MIPS64R6EL-NEXT: max.d $f0, $f12, $f13 + + %r = tail call double @llvm.maxnum.f64(double %x, double %y) + ret double %r +} + +declare float @llvm.minnum.f32(float, float) +declare float @llvm.maxnum.f32(float, float) +declare double @llvm.minnum.f64(double, double) +declare double @llvm.maxnum.f64(double, double) diff --git a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll index 45c7ab980edd..fe68bee408fc 100644 --- a/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll +++ b/llvm/test/CodeGen/Mips/msa/f16-llvm-ir.ll @@ -2365,101 +2365,159 @@ entry: declare float @llvm.minnum.f32(float %Val, float %b) define void @fminnum(float %b) { -; MIPS32-LABEL: fminnum: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: lui $2, %hi(_gp_disp) -; MIPS32-NEXT: addiu $2, $2, %lo(_gp_disp) -; MIPS32-NEXT: addiu $sp, $sp, -24 -; MIPS32-NEXT: .cfi_def_cfa_offset 24 -; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MIPS32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill -; MIPS32-NEXT: .cfi_offset 31, -4 -; MIPS32-NEXT: .cfi_offset 16, -8 -; MIPS32-NEXT: addu $gp, $2, $25 -; MIPS32-NEXT: mov.s $f14, $f12 -; MIPS32-NEXT: lw $16, %got(g)($gp) -; MIPS32-NEXT: lh $1, 0($16) -; MIPS32-NEXT: fill.h $w0, $1 -; MIPS32-NEXT: fexupr.w $w0, $w0 -; MIPS32-NEXT: copy_s.w $1, $w0[0] -; MIPS32-NEXT: lw $25, %call16(fminf)($gp) -; MIPS32-NEXT: jalr $25 -; MIPS32-NEXT: mtc1 $1, $f12 -; MIPS32-NEXT: mfc1 $1, $f0 -; MIPS32-NEXT: fill.w $w0, $1 -; MIPS32-NEXT: fexdo.h $w0, $w0, $w0 -; MIPS32-NEXT: copy_u.h $1, $w0[0] -; MIPS32-NEXT: sh $1, 0($16) -; MIPS32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload -; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: addiu $sp, $sp, 24 +; MIPS32-O32-LABEL: fminnum: +; MIPS32-O32: # %bb.0: # %entry +; MIPS32-O32-NEXT: lui $2, %hi(_gp_disp) +; MIPS32-O32-NEXT: addiu $2, $2, %lo(_gp_disp) +; MIPS32-O32-NEXT: addiu $sp, $sp, -24 +; MIPS32-O32-NEXT: .cfi_def_cfa_offset 24 +; MIPS32-O32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; MIPS32-O32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill +; MIPS32-O32-NEXT: .cfi_offset 31, -4 +; MIPS32-O32-NEXT: .cfi_offset 16, -8 +; MIPS32-O32-NEXT: addu $gp, $2, $25 +; MIPS32-O32-NEXT: mov.s $f14, $f12 +; MIPS32-O32-NEXT: lw $16, %got(g)($gp) +; MIPS32-O32-NEXT: lh $1, 0($16) +; MIPS32-O32-NEXT: fill.h $w0, $1 +; MIPS32-O32-NEXT: fexupr.w $w0, $w0 +; MIPS32-O32-NEXT: copy_s.w $1, $w0[0] +; MIPS32-O32-NEXT: lw $25, %call16(fminf)($gp) +; MIPS32-O32-NEXT: jalr $25 +; MIPS32-O32-NEXT: mtc1 $1, $f12 +; MIPS32-O32-NEXT: mfc1 $1, $f0 +; MIPS32-O32-NEXT: fill.w $w0, $1 +; MIPS32-O32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPS32-O32-NEXT: copy_u.h $1, $w0[0] +; MIPS32-O32-NEXT: sh $1, 0($16) +; MIPS32-O32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload +; MIPS32-O32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; MIPS32-O32-NEXT: jr $ra +; MIPS32-O32-NEXT: addiu $sp, $sp, 24 ; -; MIPS64-N32-LABEL: fminnum: -; MIPS64-N32: # %bb.0: # %entry -; MIPS64-N32-NEXT: addiu $sp, $sp, -32 -; MIPS64-N32-NEXT: .cfi_def_cfa_offset 32 -; MIPS64-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill -; MIPS64-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill -; MIPS64-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill -; MIPS64-N32-NEXT: .cfi_offset 31, -8 -; MIPS64-N32-NEXT: .cfi_offset 28, -16 -; MIPS64-N32-NEXT: .cfi_offset 16, -24 -; MIPS64-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum))) -; MIPS64-N32-NEXT: addu $1, $1, $25 -; MIPS64-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fminnum))) -; MIPS64-N32-NEXT: mov.s $f13, $f12 -; MIPS64-N32-NEXT: lw $16, %got_disp(g)($gp) -; MIPS64-N32-NEXT: lh $1, 0($16) -; MIPS64-N32-NEXT: fill.h $w0, $1 -; MIPS64-N32-NEXT: fexupr.w $w0, $w0 -; MIPS64-N32-NEXT: copy_s.w $1, $w0[0] -; MIPS64-N32-NEXT: lw $25, %call16(fminf)($gp) -; MIPS64-N32-NEXT: jalr $25 -; MIPS64-N32-NEXT: mtc1 $1, $f12 -; MIPS64-N32-NEXT: mfc1 $1, $f0 -; MIPS64-N32-NEXT: fill.w $w0, $1 -; MIPS64-N32-NEXT: fexdo.h $w0, $w0, $w0 -; MIPS64-N32-NEXT: copy_u.h $1, $w0[0] -; MIPS64-N32-NEXT: sh $1, 0($16) -; MIPS64-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload -; MIPS64-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload -; MIPS64-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload -; MIPS64-N32-NEXT: jr $ra -; MIPS64-N32-NEXT: addiu $sp, $sp, 32 +; MIPS64R5-N32-LABEL: fminnum: +; MIPS64R5-N32: # %bb.0: # %entry +; MIPS64R5-N32-NEXT: addiu $sp, $sp, -32 +; MIPS64R5-N32-NEXT: .cfi_def_cfa_offset 32 +; MIPS64R5-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill +; MIPS64R5-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill +; MIPS64R5-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill +; MIPS64R5-N32-NEXT: .cfi_offset 31, -8 +; MIPS64R5-N32-NEXT: .cfi_offset 28, -16 +; MIPS64R5-N32-NEXT: .cfi_offset 16, -24 +; MIPS64R5-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum))) +; MIPS64R5-N32-NEXT: addu $1, $1, $25 +; MIPS64R5-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fminnum))) +; MIPS64R5-N32-NEXT: mov.s $f13, $f12 +; MIPS64R5-N32-NEXT: lw $16, %got_disp(g)($gp) +; MIPS64R5-N32-NEXT: lh $1, 0($16) +; MIPS64R5-N32-NEXT: fill.h $w0, $1 +; MIPS64R5-N32-NEXT: fexupr.w $w0, $w0 +; MIPS64R5-N32-NEXT: copy_s.w $1, $w0[0] +; MIPS64R5-N32-NEXT: lw $25, %call16(fminf)($gp) +; MIPS64R5-N32-NEXT: jalr $25 +; MIPS64R5-N32-NEXT: mtc1 $1, $f12 +; MIPS64R5-N32-NEXT: mfc1 $1, $f0 +; MIPS64R5-N32-NEXT: fill.w $w0, $1 +; MIPS64R5-N32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPS64R5-N32-NEXT: copy_u.h $1, $w0[0] +; MIPS64R5-N32-NEXT: sh $1, 0($16) +; MIPS64R5-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload +; MIPS64R5-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload +; MIPS64R5-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload +; MIPS64R5-N32-NEXT: jr $ra +; MIPS64R5-N32-NEXT: addiu $sp, $sp, 32 +; +; MIPS64R5-N64-LABEL: fminnum: +; MIPS64R5-N64: # %bb.0: # %entry +; MIPS64R5-N64-NEXT: daddiu $sp, $sp, -32 +; MIPS64R5-N64-NEXT: .cfi_def_cfa_offset 32 +; MIPS64R5-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill +; MIPS64R5-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill +; MIPS64R5-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill +; MIPS64R5-N64-NEXT: .cfi_offset 31, -8 +; MIPS64R5-N64-NEXT: .cfi_offset 28, -16 +; MIPS64R5-N64-NEXT: .cfi_offset 16, -24 +; MIPS64R5-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum))) +; MIPS64R5-N64-NEXT: daddu $1, $1, $25 +; MIPS64R5-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fminnum))) +; MIPS64R5-N64-NEXT: mov.s $f13, $f12 +; MIPS64R5-N64-NEXT: ld $16, %got_disp(g)($gp) +; MIPS64R5-N64-NEXT: lh $1, 0($16) +; MIPS64R5-N64-NEXT: fill.h $w0, $1 +; MIPS64R5-N64-NEXT: fexupr.w $w0, $w0 +; MIPS64R5-N64-NEXT: copy_s.w $1, $w0[0] +; MIPS64R5-N64-NEXT: ld $25, %call16(fminf)($gp) +; MIPS64R5-N64-NEXT: jalr $25 +; MIPS64R5-N64-NEXT: mtc1 $1, $f12 +; MIPS64R5-N64-NEXT: mfc1 $1, $f0 +; MIPS64R5-N64-NEXT: fill.w $w0, $1 +; MIPS64R5-N64-NEXT: fexdo.h $w0, $w0, $w0 +; MIPS64R5-N64-NEXT: copy_u.h $1, $w0[0] +; MIPS64R5-N64-NEXT: sh $1, 0($16) +; MIPS64R5-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload +; MIPS64R5-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload +; MIPS64R5-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload +; MIPS64R5-N64-NEXT: jr $ra +; MIPS64R5-N64-NEXT: daddiu $sp, $sp, 32 +; +; MIPSR6-O32-LABEL: fminnum: +; MIPSR6-O32: # %bb.0: # %entry +; MIPSR6-O32-NEXT: lui $2, %hi(_gp_disp) +; MIPSR6-O32-NEXT: addiu $2, $2, %lo(_gp_disp) +; MIPSR6-O32-NEXT: addu $1, $2, $25 +; MIPSR6-O32-NEXT: lw $1, %got(g)($1) +; MIPSR6-O32-NEXT: lh $2, 0($1) +; MIPSR6-O32-NEXT: fill.h $w0, $2 +; MIPSR6-O32-NEXT: fexupr.w $w0, $w0 +; MIPSR6-O32-NEXT: copy_s.w $2, $w0[0] +; MIPSR6-O32-NEXT: mtc1 $2, $f0 +; MIPSR6-O32-NEXT: min.s $f0, $f0, $f12 +; MIPSR6-O32-NEXT: mfc1 $2, $f0 +; MIPSR6-O32-NEXT: fill.w $w0, $2 +; MIPSR6-O32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPSR6-O32-NEXT: copy_u.h $2, $w0[0] +; MIPSR6-O32-NEXT: jr $ra +; MIPSR6-O32-NEXT: sh $2, 0($1) +; +; MIPSR6-N32-LABEL: fminnum: +; MIPSR6-N32: # %bb.0: # %entry +; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum))) +; MIPSR6-N32-NEXT: addu $1, $1, $25 +; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(fminnum))) +; MIPSR6-N32-NEXT: lw $1, %got_disp(g)($1) +; MIPSR6-N32-NEXT: lh $2, 0($1) +; MIPSR6-N32-NEXT: fill.h $w0, $2 +; MIPSR6-N32-NEXT: fexupr.w $w0, $w0 +; MIPSR6-N32-NEXT: copy_s.w $2, $w0[0] +; MIPSR6-N32-NEXT: mtc1 $2, $f0 +; MIPSR6-N32-NEXT: min.s $f0, $f0, $f12 +; MIPSR6-N32-NEXT: mfc1 $2, $f0 +; MIPSR6-N32-NEXT: fill.w $w0, $2 +; MIPSR6-N32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPSR6-N32-NEXT: copy_u.h $2, $w0[0] +; MIPSR6-N32-NEXT: jr $ra +; MIPSR6-N32-NEXT: sh $2, 0($1) +; +; MIPSR6-N64-LABEL: fminnum: +; MIPSR6-N64: # %bb.0: # %entry +; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum))) +; MIPSR6-N64-NEXT: daddu $1, $1, $25 +; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(fminnum))) +; MIPSR6-N64-NEXT: ld $1, %got_disp(g)($1) +; MIPSR6-N64-NEXT: lh $2, 0($1) +; MIPSR6-N64-NEXT: fill.h $w0, $2 +; MIPSR6-N64-NEXT: fexupr.w $w0, $w0 +; MIPSR6-N64-NEXT: copy_s.w $2, $w0[0] +; MIPSR6-N64-NEXT: mtc1 $2, $f0 +; MIPSR6-N64-NEXT: min.s $f0, $f0, $f12 +; MIPSR6-N64-NEXT: mfc1 $2, $f0 +; MIPSR6-N64-NEXT: fill.w $w0, $2 +; MIPSR6-N64-NEXT: fexdo.h $w0, $w0, $w0 +; MIPSR6-N64-NEXT: copy_u.h $2, $w0[0] +; MIPSR6-N64-NEXT: jr $ra +; MIPSR6-N64-NEXT: sh $2, 0($1) ; -; MIPS64-N64-LABEL: fminnum: -; MIPS64-N64: # %bb.0: # %entry -; MIPS64-N64-NEXT: daddiu $sp, $sp, -32 -; MIPS64-N64-NEXT: .cfi_def_cfa_offset 32 -; MIPS64-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill -; MIPS64-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill -; MIPS64-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill -; MIPS64-N64-NEXT: .cfi_offset 31, -8 -; MIPS64-N64-NEXT: .cfi_offset 28, -16 -; MIPS64-N64-NEXT: .cfi_offset 16, -24 -; MIPS64-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fminnum))) -; MIPS64-N64-NEXT: daddu $1, $1, $25 -; MIPS64-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fminnum))) -; MIPS64-N64-NEXT: mov.s $f13, $f12 -; MIPS64-N64-NEXT: ld $16, %got_disp(g)($gp) -; MIPS64-N64-NEXT: lh $1, 0($16) -; MIPS64-N64-NEXT: fill.h $w0, $1 -; MIPS64-N64-NEXT: fexupr.w $w0, $w0 -; MIPS64-N64-NEXT: copy_s.w $1, $w0[0] -; MIPS64-N64-NEXT: ld $25, %call16(fminf)($gp) -; MIPS64-N64-NEXT: jalr $25 -; MIPS64-N64-NEXT: mtc1 $1, $f12 -; MIPS64-N64-NEXT: mfc1 $1, $f0 -; MIPS64-N64-NEXT: fill.w $w0, $1 -; MIPS64-N64-NEXT: fexdo.h $w0, $w0, $w0 -; MIPS64-N64-NEXT: copy_u.h $1, $w0[0] -; MIPS64-N64-NEXT: sh $1, 0($16) -; MIPS64-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload -; MIPS64-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload -; MIPS64-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload -; MIPS64-N64-NEXT: jr $ra -; MIPS64-N64-NEXT: daddiu $sp, $sp, 32 entry: %0 = load i16, ptr @g, align 2 %1 = call float @llvm.convert.from.fp16.f32(i16 %0) @@ -2477,101 +2535,158 @@ entry: declare float @llvm.maxnum.f32(float %Val, float %b) define void @fmaxnum(float %b) { -; MIPS32-LABEL: fmaxnum: -; MIPS32: # %bb.0: # %entry -; MIPS32-NEXT: lui $2, %hi(_gp_disp) -; MIPS32-NEXT: addiu $2, $2, %lo(_gp_disp) -; MIPS32-NEXT: addiu $sp, $sp, -24 -; MIPS32-NEXT: .cfi_def_cfa_offset 24 -; MIPS32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill -; MIPS32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill -; MIPS32-NEXT: .cfi_offset 31, -4 -; MIPS32-NEXT: .cfi_offset 16, -8 -; MIPS32-NEXT: addu $gp, $2, $25 -; MIPS32-NEXT: mov.s $f14, $f12 -; MIPS32-NEXT: lw $16, %got(g)($gp) -; MIPS32-NEXT: lh $1, 0($16) -; MIPS32-NEXT: fill.h $w0, $1 -; MIPS32-NEXT: fexupr.w $w0, $w0 -; MIPS32-NEXT: copy_s.w $1, $w0[0] -; MIPS32-NEXT: lw $25, %call16(fmaxf)($gp) -; MIPS32-NEXT: jalr $25 -; MIPS32-NEXT: mtc1 $1, $f12 -; MIPS32-NEXT: mfc1 $1, $f0 -; MIPS32-NEXT: fill.w $w0, $1 -; MIPS32-NEXT: fexdo.h $w0, $w0, $w0 -; MIPS32-NEXT: copy_u.h $1, $w0[0] -; MIPS32-NEXT: sh $1, 0($16) -; MIPS32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload -; MIPS32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload -; MIPS32-NEXT: jr $ra -; MIPS32-NEXT: addiu $sp, $sp, 24 +; MIPS32-O32-LABEL: fmaxnum: +; MIPS32-O32: # %bb.0: # %entry +; MIPS32-O32-NEXT: lui $2, %hi(_gp_disp) +; MIPS32-O32-NEXT: addiu $2, $2, %lo(_gp_disp) +; MIPS32-O32-NEXT: addiu $sp, $sp, -24 +; MIPS32-O32-NEXT: .cfi_def_cfa_offset 24 +; MIPS32-O32-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill +; MIPS32-O32-NEXT: sw $16, 16($sp) # 4-byte Folded Spill +; MIPS32-O32-NEXT: .cfi_offset 31, -4 +; MIPS32-O32-NEXT: .cfi_offset 16, -8 +; MIPS32-O32-NEXT: addu $gp, $2, $25 +; MIPS32-O32-NEXT: mov.s $f14, $f12 +; MIPS32-O32-NEXT: lw $16, %got(g)($gp) +; MIPS32-O32-NEXT: lh $1, 0($16) +; MIPS32-O32-NEXT: fill.h $w0, $1 +; MIPS32-O32-NEXT: fexupr.w $w0, $w0 +; MIPS32-O32-NEXT: copy_s.w $1, $w0[0] +; MIPS32-O32-NEXT: lw $25, %call16(fmaxf)($gp) +; MIPS32-O32-NEXT: jalr $25 +; MIPS32-O32-NEXT: mtc1 $1, $f12 +; MIPS32-O32-NEXT: mfc1 $1, $f0 +; MIPS32-O32-NEXT: fill.w $w0, $1 +; MIPS32-O32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPS32-O32-NEXT: copy_u.h $1, $w0[0] +; MIPS32-O32-NEXT: sh $1, 0($16) +; MIPS32-O32-NEXT: lw $16, 16($sp) # 4-byte Folded Reload +; MIPS32-O32-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload +; MIPS32-O32-NEXT: jr $ra +; MIPS32-O32-NEXT: addiu $sp, $sp, 24 ; -; MIPS64-N32-LABEL: fmaxnum: -; MIPS64-N32: # %bb.0: # %entry -; MIPS64-N32-NEXT: addiu $sp, $sp, -32 -; MIPS64-N32-NEXT: .cfi_def_cfa_offset 32 -; MIPS64-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill -; MIPS64-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill -; MIPS64-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill -; MIPS64-N32-NEXT: .cfi_offset 31, -8 -; MIPS64-N32-NEXT: .cfi_offset 28, -16 -; MIPS64-N32-NEXT: .cfi_offset 16, -24 -; MIPS64-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum))) -; MIPS64-N32-NEXT: addu $1, $1, $25 -; MIPS64-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum))) -; MIPS64-N32-NEXT: mov.s $f13, $f12 -; MIPS64-N32-NEXT: lw $16, %got_disp(g)($gp) -; MIPS64-N32-NEXT: lh $1, 0($16) -; MIPS64-N32-NEXT: fill.h $w0, $1 -; MIPS64-N32-NEXT: fexupr.w $w0, $w0 -; MIPS64-N32-NEXT: copy_s.w $1, $w0[0] -; MIPS64-N32-NEXT: lw $25, %call16(fmaxf)($gp) -; MIPS64-N32-NEXT: jalr $25 -; MIPS64-N32-NEXT: mtc1 $1, $f12 -; MIPS64-N32-NEXT: mfc1 $1, $f0 -; MIPS64-N32-NEXT: fill.w $w0, $1 -; MIPS64-N32-NEXT: fexdo.h $w0, $w0, $w0 -; MIPS64-N32-NEXT: copy_u.h $1, $w0[0] -; MIPS64-N32-NEXT: sh $1, 0($16) -; MIPS64-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload -; MIPS64-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload -; MIPS64-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload -; MIPS64-N32-NEXT: jr $ra -; MIPS64-N32-NEXT: addiu $sp, $sp, 32 +; MIPS64R5-N32-LABEL: fmaxnum: +; MIPS64R5-N32: # %bb.0: # %entry +; MIPS64R5-N32-NEXT: addiu $sp, $sp, -32 +; MIPS64R5-N32-NEXT: .cfi_def_cfa_offset 32 +; MIPS64R5-N32-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill +; MIPS64R5-N32-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill +; MIPS64R5-N32-NEXT: sd $16, 8($sp) # 8-byte Folded Spill +; MIPS64R5-N32-NEXT: .cfi_offset 31, -8 +; MIPS64R5-N32-NEXT: .cfi_offset 28, -16 +; MIPS64R5-N32-NEXT: .cfi_offset 16, -24 +; MIPS64R5-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum))) +; MIPS64R5-N32-NEXT: addu $1, $1, $25 +; MIPS64R5-N32-NEXT: addiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum))) +; MIPS64R5-N32-NEXT: mov.s $f13, $f12 +; MIPS64R5-N32-NEXT: lw $16, %got_disp(g)($gp) +; MIPS64R5-N32-NEXT: lh $1, 0($16) +; MIPS64R5-N32-NEXT: fill.h $w0, $1 +; MIPS64R5-N32-NEXT: fexupr.w $w0, $w0 +; MIPS64R5-N32-NEXT: copy_s.w $1, $w0[0] +; MIPS64R5-N32-NEXT: lw $25, %call16(fmaxf)($gp) +; MIPS64R5-N32-NEXT: jalr $25 +; MIPS64R5-N32-NEXT: mtc1 $1, $f12 +; MIPS64R5-N32-NEXT: mfc1 $1, $f0 +; MIPS64R5-N32-NEXT: fill.w $w0, $1 +; MIPS64R5-N32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPS64R5-N32-NEXT: copy_u.h $1, $w0[0] +; MIPS64R5-N32-NEXT: sh $1, 0($16) +; MIPS64R5-N32-NEXT: ld $16, 8($sp) # 8-byte Folded Reload +; MIPS64R5-N32-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload +; MIPS64R5-N32-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload +; MIPS64R5-N32-NEXT: jr $ra +; MIPS64R5-N32-NEXT: addiu $sp, $sp, 32 ; -; MIPS64-N64-LABEL: fmaxnum: -; MIPS64-N64: # %bb.0: # %entry -; MIPS64-N64-NEXT: daddiu $sp, $sp, -32 -; MIPS64-N64-NEXT: .cfi_def_cfa_offset 32 -; MIPS64-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill -; MIPS64-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill -; MIPS64-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill -; MIPS64-N64-NEXT: .cfi_offset 31, -8 -; MIPS64-N64-NEXT: .cfi_offset 28, -16 -; MIPS64-N64-NEXT: .cfi_offset 16, -24 -; MIPS64-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum))) -; MIPS64-N64-NEXT: daddu $1, $1, $25 -; MIPS64-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum))) -; MIPS64-N64-NEXT: mov.s $f13, $f12 -; MIPS64-N64-NEXT: ld $16, %got_disp(g)($gp) -; MIPS64-N64-NEXT: lh $1, 0($16) -; MIPS64-N64-NEXT: fill.h $w0, $1 -; MIPS64-N64-NEXT: fexupr.w $w0, $w0 -; MIPS64-N64-NEXT: copy_s.w $1, $w0[0] -; MIPS64-N64-NEXT: ld $25, %call16(fmaxf)($gp) -; MIPS64-N64-NEXT: jalr $25 -; MIPS64-N64-NEXT: mtc1 $1, $f12 -; MIPS64-N64-NEXT: mfc1 $1, $f0 -; MIPS64-N64-NEXT: fill.w $w0, $1 -; MIPS64-N64-NEXT: fexdo.h $w0, $w0, $w0 -; MIPS64-N64-NEXT: copy_u.h $1, $w0[0] -; MIPS64-N64-NEXT: sh $1, 0($16) -; MIPS64-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload -; MIPS64-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload -; MIPS64-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload -; MIPS64-N64-NEXT: jr $ra -; MIPS64-N64-NEXT: daddiu $sp, $sp, 32 +; MIPS64R5-N64-LABEL: fmaxnum: +; MIPS64R5-N64: # %bb.0: # %entry +; MIPS64R5-N64-NEXT: daddiu $sp, $sp, -32 +; MIPS64R5-N64-NEXT: .cfi_def_cfa_offset 32 +; MIPS64R5-N64-NEXT: sd $ra, 24($sp) # 8-byte Folded Spill +; MIPS64R5-N64-NEXT: sd $gp, 16($sp) # 8-byte Folded Spill +; MIPS64R5-N64-NEXT: sd $16, 8($sp) # 8-byte Folded Spill +; MIPS64R5-N64-NEXT: .cfi_offset 31, -8 +; MIPS64R5-N64-NEXT: .cfi_offset 28, -16 +; MIPS64R5-N64-NEXT: .cfi_offset 16, -24 +; MIPS64R5-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum))) +; MIPS64R5-N64-NEXT: daddu $1, $1, $25 +; MIPS64R5-N64-NEXT: daddiu $gp, $1, %lo(%neg(%gp_rel(fmaxnum))) +; MIPS64R5-N64-NEXT: mov.s $f13, $f12 +; MIPS64R5-N64-NEXT: ld $16, %got_disp(g)($gp) +; MIPS64R5-N64-NEXT: lh $1, 0($16) +; MIPS64R5-N64-NEXT: fill.h $w0, $1 +; MIPS64R5-N64-NEXT: fexupr.w $w0, $w0 +; MIPS64R5-N64-NEXT: copy_s.w $1, $w0[0] +; MIPS64R5-N64-NEXT: ld $25, %call16(fmaxf)($gp) +; MIPS64R5-N64-NEXT: jalr $25 +; MIPS64R5-N64-NEXT: mtc1 $1, $f12 +; MIPS64R5-N64-NEXT: mfc1 $1, $f0 +; MIPS64R5-N64-NEXT: fill.w $w0, $1 +; MIPS64R5-N64-NEXT: fexdo.h $w0, $w0, $w0 +; MIPS64R5-N64-NEXT: copy_u.h $1, $w0[0] +; MIPS64R5-N64-NEXT: sh $1, 0($16) +; MIPS64R5-N64-NEXT: ld $16, 8($sp) # 8-byte Folded Reload +; MIPS64R5-N64-NEXT: ld $gp, 16($sp) # 8-byte Folded Reload +; MIPS64R5-N64-NEXT: ld $ra, 24($sp) # 8-byte Folded Reload +; MIPS64R5-N64-NEXT: jr $ra +; MIPS64R5-N64-NEXT: daddiu $sp, $sp, 32 +; +; MIPSR6-O32-LABEL: fmaxnum: +; MIPSR6-O32: # %bb.0: +; MIPSR6-O32-NEXT: lui $2, %hi(_gp_disp) +; MIPSR6-O32-NEXT: addiu $2, $2, %lo(_gp_disp) +; MIPSR6-O32-NEXT: addu $1, $2, $25 +; MIPSR6-O32-NEXT: lw $1, %got(g)($1) +; MIPSR6-O32-NEXT: lh $2, 0($1) +; MIPSR6-O32-NEXT: fill.h $w0, $2 +; MIPSR6-O32-NEXT: fexupr.w $w0, $w0 +; MIPSR6-O32-NEXT: copy_s.w $2, $w0[0] +; MIPSR6-O32-NEXT: mtc1 $2, $f0 +; MIPSR6-O32-NEXT: max.s $f0, $f0, $f12 +; MIPSR6-O32-NEXT: mfc1 $2, $f0 +; MIPSR6-O32-NEXT: fill.w $w0, $2 +; MIPSR6-O32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPSR6-O32-NEXT: copy_u.h $2, $w0[0] +; MIPSR6-O32-NEXT: jr $ra +; MIPSR6-O32-NEXT: sh $2, 0($1) +; +; MIPSR6-N32-LABEL: fmaxnum: +; MIPSR6-N32: # %bb.0: +; MIPSR6-N32-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum))) +; MIPSR6-N32-NEXT: addu $1, $1, $25 +; MIPSR6-N32-NEXT: addiu $1, $1, %lo(%neg(%gp_rel(fmaxnum))) +; MIPSR6-N32-NEXT: lw $1, %got_disp(g)($1) +; MIPSR6-N32-NEXT: lh $2, 0($1) +; MIPSR6-N32-NEXT: fill.h $w0, $2 +; MIPSR6-N32-NEXT: fexupr.w $w0, $w0 +; MIPSR6-N32-NEXT: copy_s.w $2, $w0[0] +; MIPSR6-N32-NEXT: mtc1 $2, $f0 +; MIPSR6-N32-NEXT: max.s $f0, $f0, $f12 +; MIPSR6-N32-NEXT: mfc1 $2, $f0 +; MIPSR6-N32-NEXT: fill.w $w0, $2 +; MIPSR6-N32-NEXT: fexdo.h $w0, $w0, $w0 +; MIPSR6-N32-NEXT: copy_u.h $2, $w0[0] +; MIPSR6-N32-NEXT: jr $ra +; MIPSR6-N32-NEXT: sh $2, 0($1) +; +; MIPSR6-N64-LABEL: fmaxnum: +; MIPSR6-N64: # %bb.0: +; MIPSR6-N64-NEXT: lui $1, %hi(%neg(%gp_rel(fmaxnum))) +; MIPSR6-N64-NEXT: daddu $1, $1, $25 +; MIPSR6-N64-NEXT: daddiu $1, $1, %lo(%neg(%gp_rel(fmaxnum))) +; MIPSR6-N64-NEXT: ld $1, %got_disp(g)($1) +; MIPSR6-N64-NEXT: lh $2, 0($1) +; MIPSR6-N64-NEXT: fill.h $w0, $2 +; MIPSR6-N64-NEXT: fexupr.w $w0, $w0 +; MIPSR6-N64-NEXT: copy_s.w $2, $w0[0] +; MIPSR6-N64-NEXT: mtc1 $2, $f0 +; MIPSR6-N64-NEXT: max.s $f0, $f0, $f12 +; MIPSR6-N64-NEXT: mfc1 $2, $f0 +; MIPSR6-N64-NEXT: fill.w $w0, $2 +; MIPSR6-N64-NEXT: fexdo.h $w0, $w0, $w0 +; MIPSR6-N64-NEXT: copy_u.h $2, $w0[0] +; MIPSR6-N64-NEXT: jr $ra +; MIPSR6-N64-NEXT: sh $2, 0($1) entry: %0 = load i16, ptr @g, align 2 %1 = call float @llvm.convert.from.fp16.f32(i16 %0) -- GitLab From c229f767e48c7190b7568e6ebd1688bb08795744 Mon Sep 17 00:00:00 2001 From: XChy Date: Sat, 27 Apr 2024 16:10:16 +0800 Subject: [PATCH 126/301] [DFAJumpThreading] Avoid exploring the paths that never come back (#85505) This patch does: - Preserve loop info when unfolding selects. - Reduce the search space for loop paths. --- .../Transforms/Scalar/DFAJumpThreading.cpp | 42 +++++++++++++++---- 1 file changed, 33 insertions(+), 9 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp index 1caed93b1b66..14cdcc956aa5 100644 --- a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp @@ -131,7 +131,7 @@ public: explicit operator bool() const { return SI && SIUse; } }; -void unfold(DomTreeUpdater *DTU, SelectInstToUnfold SIToUnfold, +void unfold(DomTreeUpdater *DTU, LoopInfo *LI, SelectInstToUnfold SIToUnfold, std::vector *NewSIsToUnfold, std::vector *NewBBs); @@ -142,6 +142,7 @@ public: : AC(AC), DT(DT), LI(LI), TTI(TTI), ORE(ORE) {} bool run(Function &F); + bool LoopInfoBroken; private: void @@ -157,7 +158,7 @@ private: std::vector NewSIsToUnfold; std::vector NewBBs; - unfold(&DTU, SIToUnfold, &NewSIsToUnfold, &NewBBs); + unfold(&DTU, LI, SIToUnfold, &NewSIsToUnfold, &NewBBs); // Put newly discovered select instructions into the work list. for (const SelectInstToUnfold &NewSIToUnfold : NewSIsToUnfold) @@ -201,7 +202,7 @@ void createBasicBlockAndSinkSelectInst( /// created basic blocks into \p NewBBs. /// /// TODO: merge it with CodeGenPrepare::optimizeSelectInst() if possible. -void unfold(DomTreeUpdater *DTU, SelectInstToUnfold SIToUnfold, +void unfold(DomTreeUpdater *DTU, LoopInfo *LI, SelectInstToUnfold SIToUnfold, std::vector *NewSIsToUnfold, std::vector *NewBBs) { SelectInst *SI = SIToUnfold.getInst(); @@ -307,6 +308,12 @@ void unfold(DomTreeUpdater *DTU, SelectInstToUnfold SIToUnfold, DTU->applyUpdates({{DominatorTree::Insert, StartBlock, TT}, {DominatorTree::Insert, StartBlock, FT}}); + // Preserve loop info + if (Loop *L = LI->getLoopFor(SI->getParent())) { + for (BasicBlock *NewBB : *NewBBs) + L->addBasicBlockToLoop(NewBB, *LI); + } + // The select is now dead. assert(SI->use_empty() && "Select must be dead now"); SI->eraseFromParent(); @@ -522,9 +529,10 @@ private: }; struct AllSwitchPaths { - AllSwitchPaths(const MainSwitch *MSwitch, OptimizationRemarkEmitter *ORE) - : Switch(MSwitch->getInstr()), SwitchBlock(Switch->getParent()), - ORE(ORE) {} + AllSwitchPaths(const MainSwitch *MSwitch, OptimizationRemarkEmitter *ORE, + LoopInfo *LI) + : Switch(MSwitch->getInstr()), SwitchBlock(Switch->getParent()), ORE(ORE), + LI(LI) {} std::vector &getThreadingPaths() { return TPaths; } unsigned getNumThreadingPaths() { return TPaths.size(); } @@ -596,6 +604,12 @@ private: Visited.insert(BB); + // Stop if we have reached the BB out of loop, since its successors have no + // impact on the DFA. + // TODO: Do we need to stop exploring if BB is the outer loop of the switch? + if (!LI->getLoopFor(BB)) + return Res; + // Some blocks have multiple edges to the same successor, and this set // is used to prevent a duplicate path from being generated SmallSet Successors; @@ -737,6 +751,7 @@ private: BasicBlock *SwitchBlock; OptimizationRemarkEmitter *ORE; std::vector TPaths; + LoopInfo *LI; }; struct TransformDFA { @@ -1283,6 +1298,7 @@ bool DFAJumpThreading::run(Function &F) { SmallVector ThreadableLoops; bool MadeChanges = false; + LoopInfoBroken = false; for (BasicBlock &BB : F) { auto *SI = dyn_cast(BB.getTerminator()); @@ -1304,7 +1320,7 @@ bool DFAJumpThreading::run(Function &F) { if (!Switch.getSelectInsts().empty()) MadeChanges = true; - AllSwitchPaths SwitchPaths(&Switch, ORE); + AllSwitchPaths SwitchPaths(&Switch, ORE, LI); SwitchPaths.run(); if (SwitchPaths.getNumThreadingPaths() > 0) { @@ -1315,10 +1331,15 @@ bool DFAJumpThreading::run(Function &F) { // strict requirement but it can cause buggy behavior if there is an // overlap of blocks in different opportunities. There is a lot of room to // experiment with catching more opportunities here. + // NOTE: To release this contraint, we must handle LoopInfo invalidation break; } } +#ifdef NDEBUG + LI->verify(*DT); +#endif + SmallPtrSet EphValues; if (ThreadableLoops.size() > 0) CodeMetrics::collectEphemeralValues(&F, AC, EphValues); @@ -1327,6 +1348,7 @@ bool DFAJumpThreading::run(Function &F) { TransformDFA Transform(&SwitchPaths, DT, AC, TTI, ORE, EphValues); Transform.run(); MadeChanges = true; + LoopInfoBroken = true; } #ifdef EXPENSIVE_CHECKS @@ -1347,11 +1369,13 @@ PreservedAnalyses DFAJumpThreadingPass::run(Function &F, LoopInfo &LI = AM.getResult(F); TargetTransformInfo &TTI = AM.getResult(F); OptimizationRemarkEmitter ORE(&F); - - if (!DFAJumpThreading(&AC, &DT, &LI, &TTI, &ORE).run(F)) + DFAJumpThreading ThreadImpl(&AC, &DT, &LI, &TTI, &ORE); + if (!ThreadImpl.run(F)) return PreservedAnalyses::all(); PreservedAnalyses PA; PA.preserve(); + if (!ThreadImpl.LoopInfoBroken) + PA.preserve(); return PA; } -- GitLab From b2c9f7d3188e41163574a83a835437955cf4b80f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Danny=20M=C3=B6sch?= Date: Sat, 27 Apr 2024 11:31:08 +0200 Subject: [PATCH 127/301] [clang-tidy] Ensure nullable variable is not accessed without validity test (#90173) --- .../readability/AvoidReturnWithVoidValueCheck.cpp | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp b/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp index 48bca41f4a3b..f077040a3529 100644 --- a/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp +++ b/clang-tools-extra/clang-tidy/readability/AvoidReturnWithVoidValueCheck.cpp @@ -64,8 +64,11 @@ void AvoidReturnWithVoidValueCheck::check( << BraceInsertionHints.closingBraceFixIt(); } Diag << FixItHint::CreateRemoval(VoidReturn->getReturnLoc()); - if (!Result.Nodes.getNodeAs("function_parent") || - SurroundingBlock->body_back() != VoidReturn) + const auto *FunctionParent = + Result.Nodes.getNodeAs("function_parent"); + if (!FunctionParent || + (SurroundingBlock && SurroundingBlock->body_back() != VoidReturn)) + // If this is not the last statement in a function body, we add a `return`. Diag << FixItHint::CreateInsertion(SemicolonPos.getLocWithOffset(1), " return;", true); } -- GitLab From 9e30c96aee5c85b4a5b7efa79cc7c94c1edb9d5b Mon Sep 17 00:00:00 2001 From: Serge Pavlov Date: Sat, 27 Apr 2024 19:01:24 +0700 Subject: [PATCH 128/301] [AArch64] Lowering of fpmode intrinsics in DAG (#80611) LLVM intrinsics `get_fpmode`, `set_fpmode` and `reset_fpmode` operate control modes, the bits of FP environment that affect FP operations. On AArch64 these bits are in FPCR. The lowering implemented to produce code close to that of GLIBC. --- .../Target/AArch64/AArch64ISelLowering.cpp | 68 +++++++++++++++++++ llvm/lib/Target/AArch64/AArch64ISelLowering.h | 6 ++ llvm/test/CodeGen/AArch64/fpmode.ll | 43 ++++++------ 3 files changed, 93 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 8e9782c1930c..409ba13b8c6a 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -842,6 +842,9 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM, setOperationAction(ISD::GET_ROUNDING, MVT::i32, Custom); setOperationAction(ISD::SET_ROUNDING, MVT::Other, Custom); + setOperationAction(ISD::GET_FPMODE, MVT::i32, Custom); + setOperationAction(ISD::SET_FPMODE, MVT::i32, Custom); + setOperationAction(ISD::RESET_FPMODE, MVT::Other, Custom); setOperationAction(ISD::ATOMIC_CMP_SWAP, MVT::i128, Custom); if (!Subtarget->hasLSE() && !Subtarget->outlineAtomics()) { @@ -4870,6 +4873,65 @@ SDValue AArch64TargetLowering::LowerSET_ROUNDING(SDValue Op, return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2); } +SDValue AArch64TargetLowering::LowerGET_FPMODE(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Chain = Op->getOperand(0); + + // Get current value of FPCR. + SDValue Ops[] = { + Chain, DAG.getTargetConstant(Intrinsic::aarch64_get_fpcr, DL, MVT::i64)}; + SDValue FPCR = + DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i64, MVT::Other}, Ops); + Chain = FPCR.getValue(1); + FPCR = FPCR.getValue(0); + + // Truncate FPCR to 32 bits. + SDValue Result = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPCR); + + return DAG.getMergeValues({Result, Chain}, DL); +} + +SDValue AArch64TargetLowering::LowerSET_FPMODE(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Chain = Op->getOperand(0); + SDValue Mode = Op->getOperand(1); + + // Extend the specified value to 64 bits. + SDValue FPCR = DAG.getZExtOrTrunc(Mode, DL, MVT::i64); + + // Set new value of FPCR. + SDValue Ops2[] = { + Chain, DAG.getConstant(Intrinsic::aarch64_set_fpcr, DL, MVT::i64), FPCR}; + return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2); +} + +SDValue AArch64TargetLowering::LowerRESET_FPMODE(SDValue Op, + SelectionDAG &DAG) const { + SDLoc DL(Op); + SDValue Chain = Op->getOperand(0); + + // Get current value of FPCR. + SDValue Ops[] = { + Chain, DAG.getTargetConstant(Intrinsic::aarch64_get_fpcr, DL, MVT::i64)}; + SDValue FPCR = + DAG.getNode(ISD::INTRINSIC_W_CHAIN, DL, {MVT::i64, MVT::Other}, Ops); + Chain = FPCR.getValue(1); + FPCR = FPCR.getValue(0); + + // Clear bits that are not reserved. + SDValue FPSCRMasked = DAG.getNode( + ISD::AND, DL, MVT::i64, FPCR, + DAG.getConstant(AArch64::ReservedFPControlBits, DL, MVT::i64)); + + // Set new value of FPCR. + SDValue Ops2[] = {Chain, + DAG.getConstant(Intrinsic::aarch64_set_fpcr, DL, MVT::i64), + FPSCRMasked}; + return DAG.getNode(ISD::INTRINSIC_VOID, DL, MVT::Other, Ops2); +} + static unsigned selectUmullSmull(SDValue &N0, SDValue &N1, SelectionDAG &DAG, SDLoc DL, bool &IsMLA) { bool IsN0SExt = isSignExtended(N0, DAG); @@ -6484,6 +6546,12 @@ SDValue AArch64TargetLowering::LowerOperation(SDValue Op, return LowerGET_ROUNDING(Op, DAG); case ISD::SET_ROUNDING: return LowerSET_ROUNDING(Op, DAG); + case ISD::GET_FPMODE: + return LowerGET_FPMODE(Op, DAG); + case ISD::SET_FPMODE: + return LowerSET_FPMODE(Op, DAG); + case ISD::RESET_FPMODE: + return LowerRESET_FPMODE(Op, DAG); case ISD::MUL: return LowerMUL(Op, DAG); case ISD::MULHS: diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.h b/llvm/lib/Target/AArch64/AArch64ISelLowering.h index 400368a5e130..fbdc4de5617f 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.h +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.h @@ -523,6 +523,9 @@ enum Rounding { // Bit position of rounding mode bits in FPCR. const unsigned RoundingBitsPos = 22; +// Reserved bits should be preserved when modifying FPCR. +const uint64_t ReservedFPControlBits = 0xfffffffff80040f8; + // Registers used to pass function arguments. ArrayRef getGPRArgRegs(); ArrayRef getFPRArgRegs(); @@ -1128,6 +1131,9 @@ private: SDValue LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const; SDValue LowerGET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; SDValue LowerSET_ROUNDING(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerGET_FPMODE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerSET_FPMODE(SDValue Op, SelectionDAG &DAG) const; + SDValue LowerRESET_FPMODE(SDValue Op, SelectionDAG &DAG) const; SDValue LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const; SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const; diff --git a/llvm/test/CodeGen/AArch64/fpmode.ll b/llvm/test/CodeGen/AArch64/fpmode.ll index ebfb0696a95a..b185d9e04941 100644 --- a/llvm/test/CodeGen/AArch64/fpmode.ll +++ b/llvm/test/CodeGen/AArch64/fpmode.ll @@ -6,17 +6,14 @@ declare i32 @llvm.get.fpmode.i32() declare void @llvm.set.fpmode.i32(i32 %fpmode) declare void @llvm.reset.fpmode() -define i32 @func_get_fpmode_soft() #0 { -; DAG-LABEL: func_get_fpmode_soft: +define i32 @func_get_fpmode() #0 { +; DAG-LABEL: func_get_fpmode: ; DAG: // %bb.0: // %entry -; DAG-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; DAG-NEXT: add x0, sp, #12 -; DAG-NEXT: bl fegetmode -; DAG-NEXT: ldr w0, [sp, #12] -; DAG-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; DAG-NEXT: mrs x0, FPCR +; DAG-NEXT: // kill: def $w0 killed $w0 killed $x0 ; DAG-NEXT: ret ; -; GIS-LABEL: func_get_fpmode_soft: +; GIS-LABEL: func_get_fpmode: ; GIS: // %bb.0: // %entry ; GIS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GIS-NEXT: add x0, sp, #12 @@ -29,17 +26,14 @@ entry: ret i32 %fpmode } -define void @func_set_fpmode_soft(i32 %fpmode) #0 { -; DAG-LABEL: func_set_fpmode_soft: +define void @func_set_fpmode(i32 %fpmode) #0 { +; DAG-LABEL: func_set_fpmode: ; DAG: // %bb.0: // %entry -; DAG-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; DAG-NEXT: str w0, [sp, #12] -; DAG-NEXT: add x0, sp, #12 -; DAG-NEXT: bl fesetmode -; DAG-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; DAG-NEXT: mov w8, w0 +; DAG-NEXT: msr FPCR, x8 ; DAG-NEXT: ret ; -; GIS-LABEL: func_set_fpmode_soft: +; GIS-LABEL: func_set_fpmode: ; GIS: // %bb.0: // %entry ; GIS-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; GIS-NEXT: str w0, [sp, #12] @@ -52,16 +46,17 @@ entry: ret void } -define void @func_reset_fpmode_soft() #0 { -; DAG-LABEL: func_reset_fpmode_soft: +define void @func_reset_fpmode() #0 { +; DAG-LABEL: func_reset_fpmode: ; DAG: // %bb.0: // %entry -; DAG-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill -; DAG-NEXT: mov x0, #-1 // =0xffffffffffffffff -; DAG-NEXT: bl fesetmode -; DAG-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload +; DAG-NEXT: mov x9, #-48904 // =0xffffffffffff40f8 +; DAG-NEXT: mrs x8, FPCR +; DAG-NEXT: movk x9, #63488, lsl #16 +; DAG-NEXT: and x8, x8, x9 +; DAG-NEXT: msr FPCR, x8 ; DAG-NEXT: ret ; -; GIS-LABEL: func_reset_fpmode_soft: +; GIS-LABEL: func_reset_fpmode: ; GIS: // %bb.0: // %entry ; GIS-NEXT: mov x0, #-1 // =0xffffffffffffffff ; GIS-NEXT: b fesetmode @@ -70,4 +65,4 @@ entry: ret void } -attributes #0 = { nounwind "use-soft-float"="true" } +attributes #0 = { nounwind } -- GitLab From b5e8555607ed39816dd05e8b6fafa2774305e825 Mon Sep 17 00:00:00 2001 From: XChy Date: Sat, 27 Apr 2024 20:17:35 +0800 Subject: [PATCH 129/301] [MemCpyOpt][NFC] Format codebase (#90225) This patch automatically formats the code. --- .../lib/Transforms/Scalar/MemCpyOptimizer.cpp | 119 +++++++++--------- 1 file changed, 62 insertions(+), 57 deletions(-) diff --git a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp index 1036b8ae963a..7ef5dceffec0 100644 --- a/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp +++ b/llvm/lib/Transforms/Scalar/MemCpyOptimizer.cpp @@ -99,7 +99,7 @@ struct MemsetRange { MaybeAlign Alignment; /// TheStores - The actual stores that make up this range. - SmallVector TheStores; + SmallVector TheStores; bool isProfitableToUseMemset(const DataLayout &DL) const; }; @@ -108,10 +108,12 @@ struct MemsetRange { bool MemsetRange::isProfitableToUseMemset(const DataLayout &DL) const { // If we found more than 4 stores to merge or 16 bytes, use memset. - if (TheStores.size() >= 4 || End-Start >= 16) return true; + if (TheStores.size() >= 4 || End - Start >= 16) + return true; // If there is nothing to merge, don't do anything. - if (TheStores.size() < 2) return false; + if (TheStores.size() < 2) + return false; // If any of the stores are a memset, then it is always good to extend the // memset. @@ -121,7 +123,8 @@ bool MemsetRange::isProfitableToUseMemset(const DataLayout &DL) const { // Assume that the code generator is capable of merging pairs of stores // together if it wants to. - if (TheStores.size() == 2) return false; + if (TheStores.size() == 2) + return false; // If we have fewer than 8 stores, it can still be worthwhile to do this. // For example, merging 4 i8 stores into an i32 store is useful almost always. @@ -133,7 +136,7 @@ bool MemsetRange::isProfitableToUseMemset(const DataLayout &DL) const { // the maximum GPR width is the same size as the largest legal integer // size. If so, check to see whether we will end up actually reducing the // number of stores used. - unsigned Bytes = unsigned(End-Start); + unsigned Bytes = unsigned(End - Start); unsigned MaxIntSize = DL.getLargestLegalIntTypeSizeInBits() / 8; if (MaxIntSize == 0) MaxIntSize = 1; @@ -145,7 +148,7 @@ bool MemsetRange::isProfitableToUseMemset(const DataLayout &DL) const { // If we will reduce the # stores (according to this heuristic), do the // transformation. This encourages merging 4 x i8 -> i32 and 2 x i16 -> i32 // etc. - return TheStores.size() > NumPointerStores+NumByteStores; + return TheStores.size() > NumPointerStores + NumByteStores; } namespace { @@ -197,7 +200,7 @@ public: /// existing ranges as appropriate. void MemsetRanges::addRange(int64_t Start, int64_t Size, Value *Ptr, MaybeAlign Alignment, Instruction *Inst) { - int64_t End = Start+Size; + int64_t End = Start + Size; range_iterator I = partition_point( Ranges, [=](const MemsetRange &O) { return O.End < Start; }); @@ -207,10 +210,10 @@ void MemsetRanges::addRange(int64_t Start, int64_t Size, Value *Ptr, // to insert a new range. Handle this now. if (I == Ranges.end() || End < I->Start) { MemsetRange &R = *Ranges.insert(I, MemsetRange()); - R.Start = Start; - R.End = End; - R.StartPtr = Ptr; - R.Alignment = Alignment; + R.Start = Start; + R.End = End; + R.StartPtr = Ptr; + R.Alignment = Alignment; R.TheStores.push_back(Inst); return; } @@ -397,7 +400,8 @@ Instruction *MemCpyOptPass::tryMergingIntoMemset(Instruction *StartInst, if (auto *NextStore = dyn_cast(BI)) { // If this is a store, see if we can merge it in. - if (!NextStore->isSimple()) break; + if (!NextStore->isSimple()) + break; Value *StoredVal = NextStore->getValueOperand(); @@ -460,7 +464,8 @@ Instruction *MemCpyOptPass::tryMergingIntoMemset(Instruction *StartInst, // emit memset's for anything big enough to be worthwhile. Instruction *AMemSet = nullptr; for (const MemsetRange &Range : Ranges) { - if (Range.TheStores.size() == 1) continue; + if (Range.TheStores.size() == 1) + continue; // If it is profitable to lower this range to memset, do so now. if (!Range.isProfitableToUseMemset(DL)) @@ -481,12 +486,10 @@ Instruction *MemCpyOptPass::tryMergingIntoMemset(Instruction *StartInst, if (!Range.TheStores.empty()) AMemSet->setDebugLoc(Range.TheStores[0]->getDebugLoc()); - auto *NewDef = - cast(MemInsertPoint->getMemoryInst() == &*BI - ? MSSAU->createMemoryAccessBefore( - AMemSet, nullptr, MemInsertPoint) - : MSSAU->createMemoryAccessAfter( - AMemSet, nullptr, MemInsertPoint)); + auto *NewDef = cast( + MemInsertPoint->getMemoryInst() == &*BI + ? MSSAU->createMemoryAccessBefore(AMemSet, nullptr, MemInsertPoint) + : MSSAU->createMemoryAccessAfter(AMemSet, nullptr, MemInsertPoint)); MSSAU->insertDef(NewDef, /*RenameUses=*/true); MemInsertPoint = NewDef; @@ -512,12 +515,13 @@ bool MemCpyOptPass::moveUp(StoreInst *SI, Instruction *P, const LoadInst *LI) { // Keep track of the arguments of all instruction we plan to lift // so we can make sure to lift them as well if appropriate. - DenseSet Args; + DenseSet Args; auto AddArg = [&](Value *Arg) { auto *I = dyn_cast(Arg); if (I && I->getParent() == SI->getParent()) { // Cannot hoist user of P above P - if (I == P) return false; + if (I == P) + return false; Args.insert(I); } return true; @@ -630,8 +634,7 @@ bool MemCpyOptPass::moveUp(StoreInst *SI, Instruction *P, const LoadInst *LI) { bool MemCpyOptPass::processStoreOfLoad(StoreInst *SI, LoadInst *LI, const DataLayout &DL, BasicBlock::iterator &BBI) { - if (!LI->isSimple() || !LI->hasOneUse() || - LI->getParent() != SI->getParent()) + if (!LI->isSimple() || !LI->hasOneUse() || LI->getParent() != SI->getParent()) return false; auto *T = LI->getType(); @@ -678,21 +681,20 @@ bool MemCpyOptPass::processStoreOfLoad(StoreInst *SI, LoadInst *LI, UseMemMove = true; IRBuilder<> Builder(P); - Value *Size = Builder.CreateTypeSize(Builder.getInt64Ty(), - DL.getTypeStoreSize(T)); + Value *Size = + Builder.CreateTypeSize(Builder.getInt64Ty(), DL.getTypeStoreSize(T)); Instruction *M; if (UseMemMove) - M = Builder.CreateMemMove( - SI->getPointerOperand(), SI->getAlign(), - LI->getPointerOperand(), LI->getAlign(), Size); + M = Builder.CreateMemMove(SI->getPointerOperand(), SI->getAlign(), + LI->getPointerOperand(), LI->getAlign(), + Size); else - M = Builder.CreateMemCpy( - SI->getPointerOperand(), SI->getAlign(), - LI->getPointerOperand(), LI->getAlign(), Size); + M = Builder.CreateMemCpy(SI->getPointerOperand(), SI->getAlign(), + LI->getPointerOperand(), LI->getAlign(), Size); M->copyMetadata(*SI, LLVMContext::MD_DIAssignID); - LLVM_DEBUG(dbgs() << "Promoting " << *LI << " to " << *SI << " => " - << *M << "\n"); + LLVM_DEBUG(dbgs() << "Promoting " << *LI << " to " << *SI << " => " << *M + << "\n"); auto *LastDef = cast(MSSAU->getMemorySSA()->getMemoryAccess(SI)); @@ -755,7 +757,8 @@ bool MemCpyOptPass::processStoreOfLoad(StoreInst *SI, LoadInst *LI, } bool MemCpyOptPass::processStore(StoreInst *SI, BasicBlock::iterator &BBI) { - if (!SI->isSimple()) return false; + if (!SI->isSimple()) + return false; // Avoid merging nontemporal stores since the resulting // memcpy/memset would not be able to preserve the nontemporal hint. @@ -794,8 +797,8 @@ bool MemCpyOptPass::processStore(StoreInst *SI, BasicBlock::iterator &BBI) { // 0xA0A0A0A0 and 0.0. auto *V = SI->getOperand(0); if (Value *ByteVal = isBytewiseValue(V, DL)) { - if (Instruction *I = tryMergingIntoMemset(SI, SI->getPointerOperand(), - ByteVal)) { + if (Instruction *I = + tryMergingIntoMemset(SI, SI->getPointerOperand(), ByteVal)) { BBI = I->getIterator(); // Don't invalidate iterator. return true; } @@ -816,8 +819,7 @@ bool MemCpyOptPass::processStore(StoreInst *SI, BasicBlock::iterator &BBI) { // The newly inserted memset is immediately overwritten by the original // store, so we do not need to rename uses. auto *StoreDef = cast(MSSA->getMemoryAccess(SI)); - auto *NewAccess = MSSAU->createMemoryAccessBefore( - M, nullptr, StoreDef); + auto *NewAccess = MSSAU->createMemoryAccessBefore(M, nullptr, StoreDef); MSSAU->insertDef(cast(NewAccess), /*RenameUses=*/false); eraseInstruction(SI); @@ -836,8 +838,8 @@ bool MemCpyOptPass::processMemSet(MemSetInst *MSI, BasicBlock::iterator &BBI) { // See if there is another memset or store neighboring this memset which // allows us to widen out the memset to do a single larger store. if (isa(MSI->getLength()) && !MSI->isVolatile()) - if (Instruction *I = tryMergingIntoMemset(MSI, MSI->getDest(), - MSI->getValue())) { + if (Instruction *I = + tryMergingIntoMemset(MSI, MSI->getDest(), MSI->getValue())) { BBI = I->getIterator(); // Don't invalidate iterator. return true; } @@ -850,7 +852,8 @@ bool MemCpyOptPass::processMemSet(MemSetInst *MSI, BasicBlock::iterator &BBI) { bool MemCpyOptPass::performCallSlotOptzn(Instruction *cpyLoad, Instruction *cpyStore, Value *cpyDest, Value *cpySrc, TypeSize cpySize, - Align cpyDestAlign, BatchAAResults &BAA, + Align cpyDestAlign, + BatchAAResults &BAA, std::function GetC) { // The general transformation to keep in mind is // @@ -898,15 +901,15 @@ bool MemCpyOptPass::performCallSlotOptzn(Instruction *cpyLoad, if (F->isIntrinsic() && F->getIntrinsicID() == Intrinsic::lifetime_start) return false; - if (C->getParent() != cpyStore->getParent()) { LLVM_DEBUG(dbgs() << "Call Slot: block local restriction\n"); return false; } - MemoryLocation DestLoc = isa(cpyStore) ? - MemoryLocation::get(cpyStore) : - MemoryLocation::getForDest(cast(cpyStore)); + MemoryLocation DestLoc = + isa(cpyStore) + ? MemoryLocation::get(cpyStore) + : MemoryLocation::getForDest(cast(cpyStore)); // Check that nothing touches the dest of the copy between // the call and the store/memcpy. @@ -1175,7 +1178,8 @@ bool MemCpyOptPass::processMemCpyMemCpyDependence(MemCpyInst *M, // If all checks passed, then we can transform M. LLVM_DEBUG(dbgs() << "MemCpyOptPass: Forwarding memcpy->memcpy src:\n" - << *MDep << '\n' << *M << '\n'); + << *MDep << '\n' + << *M << '\n'); // TODO: Is this worth it if we're creating a less aligned memcpy? For // example we could be moving from movaps -> movq on x86. @@ -1307,8 +1311,8 @@ bool MemCpyOptPass::processMemSetMemCpyDependence(MemCpyInst *MemCpy, // memcpy's defining access is the memset about to be removed. auto *LastDef = cast(MSSAU->getMemorySSA()->getMemoryAccess(MemCpy)); - auto *NewAccess = MSSAU->createMemoryAccessBefore( - NewMemSet, nullptr, LastDef); + auto *NewAccess = + MSSAU->createMemoryAccessBefore(NewMemSet, nullptr, LastDef); MSSAU->insertDef(cast(NewAccess), /*RenameUses=*/true); eraseInstruction(MemSet); @@ -1384,7 +1388,7 @@ bool MemCpyOptPass::performMemCpyToMemSetOptzn(MemCpyInst *MemCpy, return false; // A known memcpy size is also required. - auto *CCopySize = dyn_cast(CopySize); + auto *CCopySize = dyn_cast(CopySize); if (!CCopySize) return false; if (CCopySize->getZExtValue() > CMemSetSize->getZExtValue()) { @@ -1655,7 +1659,8 @@ static bool isZeroSize(Value *Size) { /// altogether. bool MemCpyOptPass::processMemCpy(MemCpyInst *M, BasicBlock::iterator &BBI) { // We can only optimize non-volatile memcpy's. - if (M->isVolatile()) return false; + if (M->isVolatile()) + return false; // If the source and destination of the memcpy are the same, then zap it. if (M->getSource() == M->getDest()) { @@ -1796,11 +1801,10 @@ bool MemCpyOptPass::processMemMove(MemMoveInst *M) { << "\n"); // If not, then we know we can transform this. - Type *ArgTys[3] = { M->getRawDest()->getType(), - M->getRawSource()->getType(), - M->getLength()->getType() }; - M->setCalledFunction(Intrinsic::getDeclaration(M->getModule(), - Intrinsic::memcpy, ArgTys)); + Type *ArgTys[3] = {M->getRawDest()->getType(), M->getRawSource()->getType(), + M->getLength()->getType()}; + M->setCalledFunction( + Intrinsic::getDeclaration(M->getModule(), Intrinsic::memcpy, ArgTys)); // For MemorySSA nothing really changes (except that memcpy may imply stricter // aliasing guarantees). @@ -1843,7 +1847,8 @@ bool MemCpyOptPass::processByValArgument(CallBase &CB, unsigned ArgNo) { // Get the alignment of the byval. If the call doesn't specify the alignment, // then it is some target specific value that we can't know. MaybeAlign ByValAlign = CB.getParamAlign(ArgNo); - if (!ByValAlign) return false; + if (!ByValAlign) + return false; // If it is greater than the memcpy, then we check to see if we can force the // source of the memcpy to the alignment we need. If we fail, we bail out. @@ -1987,7 +1992,7 @@ bool MemCpyOptPass::iterateOnFunction(Function &F) { continue; for (BasicBlock::iterator BI = BB.begin(), BE = BB.end(); BI != BE;) { - // Avoid invalidating the iterator. + // Avoid invalidating the iterator. Instruction *I = &*BI++; bool RepeatInstruction = false; -- GitLab From 7b5b5214a6f905be67e3c2ecb9b4887eaa3406c3 Mon Sep 17 00:00:00 2001 From: XChy Date: Sat, 27 Apr 2024 21:55:53 +0800 Subject: [PATCH 130/301] [DFAJumpThreading][NFC] Use const reference as range variable (#90342) Fixes #90286 --- llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp index 14cdcc956aa5..ba2546b8db0e 100644 --- a/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp +++ b/llvm/lib/Transforms/Scalar/DFAJumpThreading.cpp @@ -553,7 +553,7 @@ struct AllSwitchPaths { return; } - for (PathType Path : LoopPaths) { + for (const PathType &Path : LoopPaths) { ThreadingPath TPath; const BasicBlock *PrevBB = Path.back(); -- GitLab From ff03f23be8bc6df701efd9e1093779fbcf382d87 Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Sat, 27 Apr 2024 22:11:47 +0800 Subject: [PATCH 131/301] [WebAssembly] remove instruction after builtin trap (#90207) `llvm.trap` will be convert as `unreachable` which is terminator. Instruction after terminator will cause validation failed. This PR introduces a pass to clean instruction after terminator. Fixes: #68770. --- llvm/lib/Target/WebAssembly/CMakeLists.txt | 1 + llvm/lib/Target/WebAssembly/WebAssembly.h | 2 + .../WebAssemblyCleanCodeAfterTrap.cpp | 80 +++++++++++++++++++ .../WebAssembly/WebAssemblyTargetMachine.cpp | 4 + llvm/test/CodeGen/WebAssembly/unreachable.ll | 11 ++- llvm/test/MC/WebAssembly/global-ctor-dtor.ll | 12 +-- 6 files changed, 102 insertions(+), 8 deletions(-) create mode 100644 llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp diff --git a/llvm/lib/Target/WebAssembly/CMakeLists.txt b/llvm/lib/Target/WebAssembly/CMakeLists.txt index f430be2653b4..1e83cbeac50d 100644 --- a/llvm/lib/Target/WebAssembly/CMakeLists.txt +++ b/llvm/lib/Target/WebAssembly/CMakeLists.txt @@ -19,6 +19,7 @@ add_llvm_target(WebAssemblyCodeGen WebAssemblyArgumentMove.cpp WebAssemblyAsmPrinter.cpp WebAssemblyCFGStackify.cpp + WebAssemblyCleanCodeAfterTrap.cpp WebAssemblyCFGSort.cpp WebAssemblyDebugFixup.cpp WebAssemblyDebugValueManager.cpp diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h index 1c40addb6d6f..7fc8546248f1 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.h +++ b/llvm/lib/Target/WebAssembly/WebAssembly.h @@ -37,6 +37,7 @@ FunctionPass *createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel); FunctionPass *createWebAssemblyArgumentMove(); FunctionPass *createWebAssemblySetP2AlignOperands(); +FunctionPass *createWebAssemblyCleanCodeAfterTrap(); // Late passes. FunctionPass *createWebAssemblyReplacePhysRegs(); @@ -63,6 +64,7 @@ void initializeOptimizeReturnedPass(PassRegistry &); void initializeWebAssemblyRefTypeMem2LocalPass(PassRegistry &); void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &); void initializeWebAssemblyArgumentMovePass(PassRegistry &); +void initializeWebAssemblyCleanCodeAfterTrapPass(PassRegistry &); void initializeWebAssemblyCFGSortPass(PassRegistry &); void initializeWebAssemblyCFGStackifyPass(PassRegistry &); void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp new file mode 100644 index 000000000000..e5cba3c48547 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp @@ -0,0 +1,80 @@ +//===-- WebAssemblyCleanCodeAfterTrap.cpp - Clean Code After Trap ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file remove instruction after trap. +/// ``llvm.trap`` will be convert as ``unreachable`` which is terminator. +/// Instruction after terminator will cause validation failed. +/// +//===----------------------------------------------------------------------===// + +#include "WebAssembly.h" +#include "WebAssemblyUtilities.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +#define DEBUG_TYPE "wasm-clean-code-after-trap" + +namespace { +class WebAssemblyCleanCodeAfterTrap final : public MachineFunctionPass { +public: + static char ID; // Pass identification, replacement for typeid + WebAssemblyCleanCodeAfterTrap() : MachineFunctionPass(ID) {} + + StringRef getPassName() const override { + return "WebAssembly Clean Code After Trap"; + } + + bool runOnMachineFunction(MachineFunction &MF) override; +}; +} // end anonymous namespace + +char WebAssemblyCleanCodeAfterTrap::ID = 0; +INITIALIZE_PASS(WebAssemblyCleanCodeAfterTrap, DEBUG_TYPE, + "WebAssembly Clean Code After Trap", false, false) + +FunctionPass *llvm::createWebAssemblyCleanCodeAfterTrap() { + return new WebAssemblyCleanCodeAfterTrap(); +} + +bool WebAssemblyCleanCodeAfterTrap::runOnMachineFunction(MachineFunction &MF) { + LLVM_DEBUG({ + dbgs() << "********** CleanCodeAfterTrap **********\n" + << "********** Function: " << MF.getName() << '\n'; + }); + + bool Changed = false; + + for (MachineBasicBlock &BB : MF) { + bool HasTerminator = false; + llvm::SmallVector RemoveMI{}; + for (MachineInstr &MI : BB) { + if (HasTerminator) + RemoveMI.push_back(&MI); + if (MI.hasProperty(MCID::Trap) && MI.isTerminator()) + HasTerminator = true; + } + if (!RemoveMI.empty()) { + Changed = true; + LLVM_DEBUG({ + for (MachineInstr *MI : RemoveMI) { + llvm::dbgs() << "* remove "; + MI->print(llvm::dbgs()); + } + }); + for (MachineInstr *MI : RemoveMI) + MI->eraseFromParent(); + } + } + return Changed; +} diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index cdd39eeb6bbb..de342e896573 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -512,6 +512,10 @@ bool WebAssemblyPassConfig::addInstSelector() { // Eliminate range checks and add default targets to br_table instructions. addPass(createWebAssemblyFixBrTableDefaults()); + // unreachable is terminator, non-terminator instruction after it is not + // allowed. + addPass(createWebAssemblyCleanCodeAfterTrap()); + return false; } diff --git a/llvm/test/CodeGen/WebAssembly/unreachable.ll b/llvm/test/CodeGen/WebAssembly/unreachable.ll index 5368c2ba5b8d..ccac31a9af4a 100644 --- a/llvm/test/CodeGen/WebAssembly/unreachable.ll +++ b/llvm/test/CodeGen/WebAssembly/unreachable.ll @@ -30,7 +30,6 @@ define void @trap_ret_void() { ; CHECK: .functype trap_ret_void () -> () ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: unreachable -; CHECK-NEXT: # fallthrough-return ; CHECK-NEXT: end_function call void @llvm.trap() ret void @@ -54,7 +53,6 @@ define void @trap_unreacheable() { ; CHECK: .functype trap_unreacheable () -> () ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: unreachable -; CHECK-NEXT: unreachable ; CHECK-NEXT: end_function call void @llvm.trap() unreachable @@ -94,3 +92,12 @@ define i32 @missing_ret_noreturn_unreachable() { call void @ext_never_return() unreachable } + +define i32 @no_crash_for_other_instruction_after_trap(ptr %p, i32 %b) { +; CHECK-LABEL: no_crash_for_other_instruction_after_trap: +; CHECK: unreachable +; CHECK-NEXT: end_function + %a = load i32, ptr %p + call void @llvm.trap() + ret i32 %a +} diff --git a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll index bc1be7931349..f1ec71da1ebb 100644 --- a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll +++ b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll @@ -80,29 +80,29 @@ declare void @func3() ; CHECK-NEXT: Offset: 0x1D ; CHECK-NEXT: - Type: R_WASM_FUNCTION_INDEX_LEB ; CHECK-NEXT: Index: 6 -; CHECK-NEXT: Offset: 0x2C +; CHECK-NEXT: Offset: 0x2B ; CHECK-NEXT: - Type: R_WASM_TABLE_INDEX_SLEB ; CHECK-NEXT: Index: 5 -; CHECK-NEXT: Offset: 0x37 +; CHECK-NEXT: Offset: 0x36 ; CHECK-NEXT: - Type: R_WASM_MEMORY_ADDR_SLEB ; CHECK-NEXT: Index: 3 -; CHECK-NEXT: Offset: 0x3F +; CHECK-NEXT: Offset: 0x3E ; CHECK-NEXT: - Type: R_WASM_FUNCTION_INDEX_LEB ; CHECK-NEXT: Index: 4 -; CHECK-NEXT: Offset: 0x45 +; CHECK-NEXT: Offset: 0x44 ; CHECK-NEXT: Functions: ; CHECK-NEXT: - Index: 5 ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 1080808080000B ; CHECK-NEXT: - Index: 6 ; CHECK-NEXT: Locals: -; CHECK-NEXT: Body: 02404181808080004100418080808000108180808000450D0000000B0B +; CHECK-NEXT: Body: 02404181808080004100418080808000108180808000450D00000B0B ; CHECK-NEXT: - Index: 7 ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 1082808080000B ; CHECK-NEXT: - Index: 8 ; CHECK-NEXT: Locals: -; CHECK-NEXT: Body: 02404182808080004100418080808000108180808000450D0000000B0B +; CHECK-NEXT: Body: 02404182808080004100418080808000108180808000450D00000B0B ; CHECK-NEXT: - Type: DATA ; CHECK-NEXT: Segments: ; CHECK-NEXT: - SectionOffset: 6 -- GitLab From 738c135ee09de66a26805530d314c2f28d1eca02 Mon Sep 17 00:00:00 2001 From: Matt Arsenault Date: Sat, 27 Apr 2024 20:26:09 +0200 Subject: [PATCH 132/301] SystemZ: Add more tests for fp128 atomics (#90269) These did not have proper floating point uses so weren't representative samples. The bitcast inserted by lowering could be absorbed by the load/store on the source/use. --- llvm/test/CodeGen/SystemZ/atomic-load-08.ll | 48 ++++++++++++++++- llvm/test/CodeGen/SystemZ/atomic-store-08.ll | 51 ++++++++++++++++++- .../test/CodeGen/SystemZ/atomicrmw-xchg-07.ll | 42 +++++++++++++++ 3 files changed, 137 insertions(+), 4 deletions(-) diff --git a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll index 4d914e3ea0e1..83050ef87591 100644 --- a/llvm/test/CodeGen/SystemZ/atomic-load-08.ll +++ b/llvm/test/CodeGen/SystemZ/atomic-load-08.ll @@ -2,8 +2,8 @@ ; loads with a bitcast, and this test case gets converted into that form as ; well by the AtomicExpand pass. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefixes=CHECK,BASE %s +; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck -check-prefixes=CHECK,Z13 %s define void @f1(ptr %ret, ptr %src) { ; CHECK-LABEL: f1: @@ -17,6 +17,34 @@ define void @f1(ptr %ret, ptr %src) { ret void } +define void @f1_fpuse(ptr %ret, ptr %src) { +; CHECK-LABEL: f1_fpuse: +; CHECK: # %bb.0: +; BASE-NEXT: aghi %r15, -176 +; BASE-NEXT: .cfi_def_cfa_offset 336 + +; CHECK-NEXT: lpq %r0, 0(%r3) + +; BASE-NEXT: stg %r1, 168(%r15) +; BASE-NEXT: stg %r0, 160(%r15) +; BASE-NEXT: ld %f0, 160(%r15) +; BASE-NEXT: ld %f2, 168(%r15) + +; Z13-NEXT: vlvgp %v0, %r0, %r1 +; Z13-NEXT: vrepg %v2, %v0, 1 + +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: std %f0, 0(%r2) +; CHECK-NEXT: std %f2, 8(%r2) +; BASE-NEXT: aghi %r15, 176 +; CHECK-NEXT: br %r14 + + %val = load atomic fp128, ptr %src seq_cst, align 16 + %use = fadd fp128 %val, %val + store fp128 %use, ptr %ret, align 8 + ret void +} + define void @f2(ptr %ret, ptr %src) { ; CHECK-LABEL: f2: ; CHECK: brasl %r14, __atomic_load@PLT @@ -24,3 +52,19 @@ define void @f2(ptr %ret, ptr %src) { store fp128 %val, ptr %ret, align 8 ret void } + +define void @f2_fpuse(ptr %ret, ptr %src) { +; CHECK-LABEL: f2_fpuse: +; CHECK: brasl %r14, __atomic_load@PLT +; CHECK-NEXT: ld %f0, 160(%r15) +; CHECK-NEXT: ld %f2, 168(%r15) +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: std %f0, 0(%r13) +; CHECK-NEXT: std %f2, 8(%r13) +; CHECK-NEXT: lmg %r13, %r15, 280(%r15) +; CHECK-NEXT: br %r14 + %val = load atomic fp128, ptr %src seq_cst, align 8 + %use = fadd fp128 %val, %val + store fp128 %use, ptr %ret, align 8 + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll index f7f4f4d967db..4d1693477f01 100644 --- a/llvm/test/CodeGen/SystemZ/atomic-store-08.ll +++ b/llvm/test/CodeGen/SystemZ/atomic-store-08.ll @@ -1,8 +1,8 @@ ; Test long double atomic stores. The atomic store is converted to i128 by ; the AtomicExpand pass. ; -; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck %s -; RUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck %s +; RUN: llc < %s -mtriple=s390x-linux-gnu | FileCheck -check-prefixes=CHECK,BASE %s +; xUN: llc < %s -mtriple=s390x-linux-gnu -mcpu=z13 | FileCheck -check-prefixes=CHECK,Z13 %s define void @f1(ptr %dst, ptr %src) { ; CHECK-LABEL: f1: @@ -17,6 +17,29 @@ define void @f1(ptr %dst, ptr %src) { ret void } +define void @f1_fpsrc(ptr %dst, ptr %src) { +; CHECK-LABEL: f1_fpsrc: +; CHECK: # %bb.0: +; CHECK-NEXT: ld %f0, 0(%r3) +; CHECK-NEXT: ld %f2, 8(%r3) +; CHECK-NEXT: axbr %f0, %f0 + +; BASE-NEXT: lgdr %r1, %f2 +; BASE-NEXT: lgdr %r0, %f0 + +; Z13-NEXT: vmrhg %v0, %v0, %v2 +; Z13-NEXT: vlgvg %r1, %v0, 1 +; Z13-NEXT: vlgvg %r0, %v0, 0 + +; CHECK-NEXT: stpq %r0, 0(%r2) +; CHECK-NEXT: bcr 15, %r0 +; CHECK-NEXT: br %r14 + %val = load fp128, ptr %src, align 8 + %add = fadd fp128 %val, %val + store atomic fp128 %add, ptr %dst seq_cst, align 16 + ret void +} + define void @f2(ptr %dst, ptr %src) { ; CHECK-LABEL: f2: ; CHECK: brasl %r14, __atomic_store@PLT @@ -24,3 +47,27 @@ define void @f2(ptr %dst, ptr %src) { store atomic fp128 %val, ptr %dst seq_cst, align 8 ret void } + +define void @f2_fpuse(ptr %dst, ptr %src) { +; CHECK-LABEL: f2_fpuse: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r14, %r15, 112(%r15) +; CHECK-NEXT: .cfi_offset %r14, -48 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -176 +; CHECK-NEXT: .cfi_def_cfa_offset 336 +; CHECK-NEXT: ld %f0, 0(%r3) +; CHECK-NEXT: ld %f2, 8(%r3) +; CHECK-NEXT: lgr %r3, %r2 +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: la %r4, 160(%r15) +; CHECK-NEXT: lghi %r2, 16 +; CHECK-NEXT: lhi %r5, 5 +; CHECK-NEXT: std %f0, 160(%r15) +; CHECK-NEXT: std %f2, 168(%r15) +; CHECK-NEXT: brasl %r14, __atomic_store@PLT + %val = load fp128, ptr %src, align 8 + %add = fadd fp128 %val, %val + store atomic fp128 %add, ptr %dst seq_cst, align 8 + ret void +} diff --git a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll index 18fa89e6ca6c..f5d8dc092a7e 100644 --- a/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll +++ b/llvm/test/CodeGen/SystemZ/atomicrmw-xchg-07.ll @@ -26,3 +26,45 @@ define void @f1(ptr align 16 %ret, ptr align 16 %src, ptr align 16 %b) { store fp128 %res, ptr %ret, align 16 ret void } + +define void @f1_fpuse(ptr align 16 %ret, ptr align 16 %src, ptr align 16 %b) { +; CHECK-LABEL: f1_fpuse: +; CHECK: # %bb.0: +; CHECK-NEXT: stmg %r12, %r15, 96(%r15) +; CHECK-NEXT: .cfi_offset %r12, -64 +; CHECK-NEXT: .cfi_offset %r13, -56 +; CHECK-NEXT: .cfi_offset %r15, -40 +; CHECK-NEXT: aghi %r15, -176 +; CHECK-NEXT: .cfi_def_cfa_offset 336 +; CHECK-NEXT: ld %f0, 0(%r4) +; CHECK-NEXT: ld %f2, 8(%r4) +; CHECK-NEXT: lg %r0, 8(%r3) +; CHECK-NEXT: lg %r1, 0(%r3) +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: lgdr %r5, %f2 +; CHECK-NEXT: lgdr %r4, %f0 +; CHECK-NEXT: .LBB1_1: # %atomicrmw.start +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: lgr %r12, %r1 +; CHECK-NEXT: lgr %r13, %r0 +; CHECK-NEXT: cdsg %r12, %r4, 0(%r3) +; CHECK-NEXT: lgr %r0, %r13 +; CHECK-NEXT: lgr %r1, %r12 +; CHECK-NEXT: jl .LBB1_1 +; CHECK-NEXT: # %bb.2: # %atomicrmw.end +; CHECK-NEXT: stg %r1, 160(%r15) +; CHECK-NEXT: stg %r0, 168(%r15) +; CHECK-NEXT: ld %f0, 160(%r15) +; CHECK-NEXT: ld %f2, 168(%r15) +; CHECK-NEXT: axbr %f0, %f0 +; CHECK-NEXT: std %f0, 0(%r2) +; CHECK-NEXT: std %f2, 8(%r2) +; CHECK-NEXT: lmg %r12, %r15, 272(%r15) +; CHECK-NEXT: br %r14 + %val = load fp128, ptr %b, align 16 + %add.src = fadd fp128 %val, %val + %res = atomicrmw xchg ptr %src, fp128 %add.src seq_cst + %res.x2 = fadd fp128 %res, %res + store fp128 %res.x2, ptr %ret, align 16 + ret void +} -- GitLab From 803cbcbc4029fc65188f6c1083a230341279b2d2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Svensson?= Date: Sat, 27 Apr 2024 20:50:04 +0200 Subject: [PATCH 133/301] [clang-tidy] Enable C23 support in modernize-use-nullptr (#89990) C23 introduces the `nullptr` constant similar to C++11 which means that the checker `modernize-use-nullptr` can be used on C23 code as well. This PR enables the checker to be run on C23 and adds testcases. See N3042: https://open-std.org/JTC1/SC22/WG14/www/docs/n3042.htm --- .../clang-tidy/modernize/UseNullptrCheck.h | 2 +- clang-tools-extra/docs/ReleaseNotes.rst | 4 + .../checks/modernize/use-nullptr.rst | 2 +- .../checkers/modernize/use-nullptr-c23.c | 139 ++++++++++++++++++ .../checkers/modernize/use-nullptr.c | 2 +- 5 files changed, 146 insertions(+), 3 deletions(-) create mode 100644 clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-c23.c diff --git a/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.h b/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.h index 6c32a4edb4ff..f1591bae4465 100644 --- a/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.h +++ b/clang-tools-extra/clang-tidy/modernize/UseNullptrCheck.h @@ -19,7 +19,7 @@ public: bool isLanguageVersionSupported(const LangOptions &LangOpts) const override { // FIXME this should be CPlusPlus11 but that causes test cases to // erroneously fail. - return LangOpts.CPlusPlus; + return LangOpts.CPlusPlus || LangOpts.C23; } void storeOptions(ClangTidyOptions::OptionMap &Opts) override; void registerMatchers(ast_matchers::MatchFinder *Finder) override; diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index 2867fc958030..f59d9c3b7a57 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -281,6 +281,10 @@ Changes in existing checks don't remove parentheses used in ``sizeof`` calls when they have array index accesses as arguments. +- Improved :doc:`modernize-use-nullptr + ` check to include support for + ``C23``, which also has introduced the ``nullptr`` keyword. + - Improved :doc:`modernize-use-override ` check to also remove any trailing whitespace when deleting the ``virtual`` keyword. diff --git a/clang-tools-extra/docs/clang-tidy/checks/modernize/use-nullptr.rst b/clang-tools-extra/docs/clang-tidy/checks/modernize/use-nullptr.rst index 5e1ba858adf3..25e17fee0a3d 100644 --- a/clang-tools-extra/docs/clang-tidy/checks/modernize/use-nullptr.rst +++ b/clang-tools-extra/docs/clang-tidy/checks/modernize/use-nullptr.rst @@ -4,7 +4,7 @@ modernize-use-nullptr ===================== The check converts the usage of null pointer constants (e.g. ``NULL``, ``0``) -to use the new C++11 ``nullptr`` keyword. +to use the new C++11 and C23 ``nullptr`` keyword. Example ------- diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-c23.c b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-c23.c new file mode 100644 index 000000000000..6fb879b91e41 --- /dev/null +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr-c23.c @@ -0,0 +1,139 @@ +// RUN: %check_clang_tidy %s modernize-use-nullptr %t -- -- -std=c23 + +#define NULL 0 + +void test_assignment() { + int *p1 = 0; + // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: use nullptr [modernize-use-nullptr] + // CHECK-FIXES: int *p1 = nullptr; + p1 = 0; + // CHECK-MESSAGES: :[[@LINE-1]]:8: warning: use nullptr + // CHECK-FIXES: p1 = nullptr; + + int *p2 = NULL; + // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: use nullptr + // CHECK-FIXES: int *p2 = nullptr; + + p2 = p1; + // CHECK-FIXES: p2 = p1; + + const int null = 0; + int *p3 = &null; + + p3 = NULL; + // CHECK-MESSAGES: :[[@LINE-1]]:8: warning: use nullptr + // CHECK-FIXES: p3 = nullptr; + + int *p4 = p3; + + int i1 = 0; + + int i2 = NULL; + + int i3 = null; + + int *p5, *p6, *p7; + p5 = p6 = p7 = NULL; + // CHECK-MESSAGES: :[[@LINE-1]]:18: warning: use nullptr + // CHECK-FIXES: p5 = p6 = p7 = nullptr; +} + +void test_function(int *p) {} + +void test_function_no_ptr_param(int i) {} + +void test_function_call() { + test_function(0); + // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: use nullptr + // CHECK-FIXES: test_function(nullptr); + + test_function(NULL); + // CHECK-MESSAGES: :[[@LINE-1]]:17: warning: use nullptr + // CHECK-FIXES: test_function(nullptr); + + test_function_no_ptr_param(0); +} + +char *test_function_return1() { + return 0; + // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: use nullptr + // CHECK-FIXES: return nullptr; +} + +void *test_function_return2() { + return NULL; + // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: use nullptr + // CHECK-FIXES: return nullptr; +} + +int test_function_return4() { + return 0; +} + +int test_function_return5() { + return NULL; +} + +int *test_function_return_cast1() { + return(int)0; + // CHECK-MESSAGES: :[[@LINE-1]]:9: warning: use nullptr + // CHECK-FIXES: return nullptr; +} + +int *test_function_return_cast2() { +#define RET return + RET(int)0; + // CHECK-MESSAGES: :[[@LINE-1]]:6: warning: use nullptr + // CHECK-FIXES: RET nullptr; +#undef RET +} + +// Test parentheses expressions resulting in a nullptr. +int *test_parentheses_expression1() { + return(0); + // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: use nullptr + // CHECK-FIXES: return(nullptr); +} + +int *test_parentheses_expression2() { + return((int)(0.0f)); + // CHECK-MESSAGES: :[[@LINE-1]]:10: warning: use nullptr + // CHECK-FIXES: return(nullptr); +} + +int *test_nested_parentheses_expression() { + return((((0)))); + // CHECK-MESSAGES: :[[@LINE-1]]:13: warning: use nullptr + // CHECK-FIXES: return((((nullptr)))); +} + +void test_const_pointers() { + const int *const_p1 = 0; + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: use nullptr + // CHECK-FIXES: const int *const_p1 = nullptr; + const int *const_p2 = NULL; + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: use nullptr + // CHECK-FIXES: const int *const_p2 = nullptr; + const int *const_p3 = (int)0; + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: use nullptr + // CHECK-FIXES: const int *const_p3 = nullptr; + const int *const_p4 = (int)0.0f; + // CHECK-MESSAGES: :[[@LINE-1]]:25: warning: use nullptr + // CHECK-FIXES: const int *const_p4 = nullptr; +} + +void test_nested_implicit_cast_expr() { + int func0(void*, void*); + int func1(int, void*, void*); + + (double)func1(0, 0, 0); + // CHECK-MESSAGES: :[[@LINE-1]]:20: warning: use nullptr + // CHECK-MESSAGES: :[[@LINE-2]]:23: warning: use nullptr + // CHECK-FIXES: (double)func1(0, nullptr, nullptr); + (double)func1(func0(0, 0), 0, 0); + // CHECK-MESSAGES: :[[@LINE-1]]:23: warning: use nullptr + // CHECK-MESSAGES: :[[@LINE-2]]:26: warning: use nullptr + // CHECK-MESSAGES: :[[@LINE-3]]:30: warning: use nullptr + // CHECK-MESSAGES: :[[@LINE-4]]:33: warning: use nullptr + // CHECK-FIXES: (double)func1(func0(nullptr, nullptr), nullptr, nullptr); +} diff --git a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr.c b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr.c index c2ccbbd81171..1218b837199c 100644 --- a/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr.c +++ b/clang-tools-extra/test/clang-tidy/checkers/modernize/use-nullptr.c @@ -1,4 +1,4 @@ -// RUN: clang-tidy %s -checks=-*,modernize-use-nullptr -- | count 0 +// RUN: clang-tidy %s -checks=-*,modernize-use-nullptr -- -std=c17 | count 0 // Note: this test expects no diagnostics, but FileCheck cannot handle that, // hence the use of | count 0. -- GitLab From 0336328e970e7e809d52a33a704bb7c05f6e170e Mon Sep 17 00:00:00 2001 From: Piotr Zegar Date: Sat, 27 Apr 2024 18:49:22 +0000 Subject: [PATCH 134/301] [clang-tidy][DOC] Minor fixes to release notes Fix minor style problems in release notes. --- clang-tools-extra/docs/ReleaseNotes.rst | 24 +++++++++++++----------- 1 file changed, 13 insertions(+), 11 deletions(-) diff --git a/clang-tools-extra/docs/ReleaseNotes.rst b/clang-tools-extra/docs/ReleaseNotes.rst index f59d9c3b7a57..3038d2b125f2 100644 --- a/clang-tools-extra/docs/ReleaseNotes.rst +++ b/clang-tools-extra/docs/ReleaseNotes.rst @@ -100,13 +100,15 @@ Improvements to clang-tidy - Improved :program:`run-clang-tidy.py` script. Added argument `-source-filter` to filter source files from the compilation database, via a RegEx. In a similar fashion to what `-header-filter` does for header files. + - Improved :program:`check_clang_tidy.py` script. Added argument `-export-fixes` to aid in clang-tidy and test development. + - Fixed bug where big values for unsigned check options overflowed into negative values - when being printed with ``--dump-config``. + when being printed with `--dump-config`. -- Fixed ``--verify-config`` option not properly parsing checks when using the - literal operator in the ``.clang-tidy`` config. +- Fixed `--verify-config` option not properly parsing checks when using the + literal operator in the `.clang-tidy` config. New checks ^^^^^^^^^^ @@ -236,7 +238,7 @@ Changes in existing checks - Improved :doc:`google-explicit-constructor ` check to better handle - ``C++-20`` `explicit(bool)`. + C++20 `explicit(bool)`. - Improved :doc:`google-global-names-in-headers ` check by replacing the local @@ -249,6 +251,10 @@ Changes in existing checks check by ignoring other functions with same prefixes as the target specific functions. +- Improved :doc:`linuxkernel-must-check-errs + ` check documentation to + consistently use the check's proper name. + - Improved :doc:`llvm-header-guard ` check by replacing the local option `HeaderFileExtensions` by the global option of the same name. @@ -282,8 +288,8 @@ Changes in existing checks accesses as arguments. - Improved :doc:`modernize-use-nullptr - ` check to include support for - ``C23``, which also has introduced the ``nullptr`` keyword. + ` check to include support for C23, + which also has introduced the ``nullptr`` keyword. - Improved :doc:`modernize-use-override ` check to also remove any trailing @@ -340,13 +346,9 @@ Miscellaneous ^^^^^^^^^^^^^ - Fixed incorrect formatting in :program:`clang-apply-replacements` when no - ``--format`` option is specified. Now :program:`clang-apply-replacements` + `--format` option is specified. Now :program:`clang-apply-replacements` applies formatting only with the option. -- Fixed the :doc:`linuxkernel-must-check-errs - ` documentation to consistently - use the check's proper name. - Improvements to include-fixer ----------------------------- -- GitLab From 38a2051c5222b3e5245043a3056b3a1e89f69b22 Mon Sep 17 00:00:00 2001 From: Mehdi Amini Date: Sat, 27 Apr 2024 21:14:46 +0200 Subject: [PATCH 135/301] Revert "[WebAssembly] remove instruction after builtin trap" (#90354) Reverts llvm/llvm-project#90207 LLD Bots are broken. --- llvm/lib/Target/WebAssembly/CMakeLists.txt | 1 - llvm/lib/Target/WebAssembly/WebAssembly.h | 2 - .../WebAssemblyCleanCodeAfterTrap.cpp | 80 ------------------- .../WebAssembly/WebAssemblyTargetMachine.cpp | 4 - llvm/test/CodeGen/WebAssembly/unreachable.ll | 11 +-- llvm/test/MC/WebAssembly/global-ctor-dtor.ll | 12 +-- 6 files changed, 8 insertions(+), 102 deletions(-) delete mode 100644 llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp diff --git a/llvm/lib/Target/WebAssembly/CMakeLists.txt b/llvm/lib/Target/WebAssembly/CMakeLists.txt index 1e83cbeac50d..f430be2653b4 100644 --- a/llvm/lib/Target/WebAssembly/CMakeLists.txt +++ b/llvm/lib/Target/WebAssembly/CMakeLists.txt @@ -19,7 +19,6 @@ add_llvm_target(WebAssemblyCodeGen WebAssemblyArgumentMove.cpp WebAssemblyAsmPrinter.cpp WebAssemblyCFGStackify.cpp - WebAssemblyCleanCodeAfterTrap.cpp WebAssemblyCFGSort.cpp WebAssemblyDebugFixup.cpp WebAssemblyDebugValueManager.cpp diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h index 7fc8546248f1..1c40addb6d6f 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.h +++ b/llvm/lib/Target/WebAssembly/WebAssembly.h @@ -37,7 +37,6 @@ FunctionPass *createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel); FunctionPass *createWebAssemblyArgumentMove(); FunctionPass *createWebAssemblySetP2AlignOperands(); -FunctionPass *createWebAssemblyCleanCodeAfterTrap(); // Late passes. FunctionPass *createWebAssemblyReplacePhysRegs(); @@ -64,7 +63,6 @@ void initializeOptimizeReturnedPass(PassRegistry &); void initializeWebAssemblyRefTypeMem2LocalPass(PassRegistry &); void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &); void initializeWebAssemblyArgumentMovePass(PassRegistry &); -void initializeWebAssemblyCleanCodeAfterTrapPass(PassRegistry &); void initializeWebAssemblyCFGSortPass(PassRegistry &); void initializeWebAssemblyCFGStackifyPass(PassRegistry &); void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp deleted file mode 100644 index e5cba3c48547..000000000000 --- a/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp +++ /dev/null @@ -1,80 +0,0 @@ -//===-- WebAssemblyCleanCodeAfterTrap.cpp - Clean Code After Trap ---------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -/// -/// \file -/// This file remove instruction after trap. -/// ``llvm.trap`` will be convert as ``unreachable`` which is terminator. -/// Instruction after terminator will cause validation failed. -/// -//===----------------------------------------------------------------------===// - -#include "WebAssembly.h" -#include "WebAssemblyUtilities.h" -#include "llvm/ADT/SmallVector.h" -#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" -#include "llvm/CodeGen/Passes.h" -#include "llvm/MC/MCInstrDesc.h" -#include "llvm/Support/Debug.h" -#include "llvm/Support/raw_ostream.h" -using namespace llvm; - -#define DEBUG_TYPE "wasm-clean-code-after-trap" - -namespace { -class WebAssemblyCleanCodeAfterTrap final : public MachineFunctionPass { -public: - static char ID; // Pass identification, replacement for typeid - WebAssemblyCleanCodeAfterTrap() : MachineFunctionPass(ID) {} - - StringRef getPassName() const override { - return "WebAssembly Clean Code After Trap"; - } - - bool runOnMachineFunction(MachineFunction &MF) override; -}; -} // end anonymous namespace - -char WebAssemblyCleanCodeAfterTrap::ID = 0; -INITIALIZE_PASS(WebAssemblyCleanCodeAfterTrap, DEBUG_TYPE, - "WebAssembly Clean Code After Trap", false, false) - -FunctionPass *llvm::createWebAssemblyCleanCodeAfterTrap() { - return new WebAssemblyCleanCodeAfterTrap(); -} - -bool WebAssemblyCleanCodeAfterTrap::runOnMachineFunction(MachineFunction &MF) { - LLVM_DEBUG({ - dbgs() << "********** CleanCodeAfterTrap **********\n" - << "********** Function: " << MF.getName() << '\n'; - }); - - bool Changed = false; - - for (MachineBasicBlock &BB : MF) { - bool HasTerminator = false; - llvm::SmallVector RemoveMI{}; - for (MachineInstr &MI : BB) { - if (HasTerminator) - RemoveMI.push_back(&MI); - if (MI.hasProperty(MCID::Trap) && MI.isTerminator()) - HasTerminator = true; - } - if (!RemoveMI.empty()) { - Changed = true; - LLVM_DEBUG({ - for (MachineInstr *MI : RemoveMI) { - llvm::dbgs() << "* remove "; - MI->print(llvm::dbgs()); - } - }); - for (MachineInstr *MI : RemoveMI) - MI->eraseFromParent(); - } - } - return Changed; -} diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index de342e896573..cdd39eeb6bbb 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -512,10 +512,6 @@ bool WebAssemblyPassConfig::addInstSelector() { // Eliminate range checks and add default targets to br_table instructions. addPass(createWebAssemblyFixBrTableDefaults()); - // unreachable is terminator, non-terminator instruction after it is not - // allowed. - addPass(createWebAssemblyCleanCodeAfterTrap()); - return false; } diff --git a/llvm/test/CodeGen/WebAssembly/unreachable.ll b/llvm/test/CodeGen/WebAssembly/unreachable.ll index ccac31a9af4a..5368c2ba5b8d 100644 --- a/llvm/test/CodeGen/WebAssembly/unreachable.ll +++ b/llvm/test/CodeGen/WebAssembly/unreachable.ll @@ -30,6 +30,7 @@ define void @trap_ret_void() { ; CHECK: .functype trap_ret_void () -> () ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: unreachable +; CHECK-NEXT: # fallthrough-return ; CHECK-NEXT: end_function call void @llvm.trap() ret void @@ -53,6 +54,7 @@ define void @trap_unreacheable() { ; CHECK: .functype trap_unreacheable () -> () ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: unreachable +; CHECK-NEXT: unreachable ; CHECK-NEXT: end_function call void @llvm.trap() unreachable @@ -92,12 +94,3 @@ define i32 @missing_ret_noreturn_unreachable() { call void @ext_never_return() unreachable } - -define i32 @no_crash_for_other_instruction_after_trap(ptr %p, i32 %b) { -; CHECK-LABEL: no_crash_for_other_instruction_after_trap: -; CHECK: unreachable -; CHECK-NEXT: end_function - %a = load i32, ptr %p - call void @llvm.trap() - ret i32 %a -} diff --git a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll index f1ec71da1ebb..bc1be7931349 100644 --- a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll +++ b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll @@ -80,29 +80,29 @@ declare void @func3() ; CHECK-NEXT: Offset: 0x1D ; CHECK-NEXT: - Type: R_WASM_FUNCTION_INDEX_LEB ; CHECK-NEXT: Index: 6 -; CHECK-NEXT: Offset: 0x2B +; CHECK-NEXT: Offset: 0x2C ; CHECK-NEXT: - Type: R_WASM_TABLE_INDEX_SLEB ; CHECK-NEXT: Index: 5 -; CHECK-NEXT: Offset: 0x36 +; CHECK-NEXT: Offset: 0x37 ; CHECK-NEXT: - Type: R_WASM_MEMORY_ADDR_SLEB ; CHECK-NEXT: Index: 3 -; CHECK-NEXT: Offset: 0x3E +; CHECK-NEXT: Offset: 0x3F ; CHECK-NEXT: - Type: R_WASM_FUNCTION_INDEX_LEB ; CHECK-NEXT: Index: 4 -; CHECK-NEXT: Offset: 0x44 +; CHECK-NEXT: Offset: 0x45 ; CHECK-NEXT: Functions: ; CHECK-NEXT: - Index: 5 ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 1080808080000B ; CHECK-NEXT: - Index: 6 ; CHECK-NEXT: Locals: -; CHECK-NEXT: Body: 02404181808080004100418080808000108180808000450D00000B0B +; CHECK-NEXT: Body: 02404181808080004100418080808000108180808000450D0000000B0B ; CHECK-NEXT: - Index: 7 ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 1082808080000B ; CHECK-NEXT: - Index: 8 ; CHECK-NEXT: Locals: -; CHECK-NEXT: Body: 02404182808080004100418080808000108180808000450D00000B0B +; CHECK-NEXT: Body: 02404182808080004100418080808000108180808000450D0000000B0B ; CHECK-NEXT: - Type: DATA ; CHECK-NEXT: Segments: ; CHECK-NEXT: - SectionOffset: 6 -- GitLab From 6084dcbfce6a54f6cb88e40ef490e0dd25984f81 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sat, 27 Apr 2024 21:30:11 +0100 Subject: [PATCH 136/301] [LV] Add additional cost model coverage for loops with casted inds. Add test coverage for cost-model code-paths not covered by current unit tests in preparation for https://github.com/llvm/llvm-project/pull/67934. --- .../AArch64/conditional-branches-cost.ll | 857 ++++++++++++++++ .../AArch64/induction-costs-sve.ll | 916 ++++++++++++++++++ .../LoopVectorize/AArch64/induction-costs.ll | 258 +++++ .../AArch64/reduction-recurrence-costs-sve.ll | 482 +++++++++ .../LoopVectorize/AArch64/store-costs-sve.ll | 341 +++++++ 5 files changed, 2854 insertions(+) create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll create mode 100644 llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll new file mode 100644 index 000000000000..a78696cadaaf --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AArch64/conditional-branches-cost.ll @@ -0,0 +1,857 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefix=DEFAULT %s +; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefix=PRED %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-macosx14.0.0" + +define void @invar_cond_gep_store(ptr %dst, i32 %0) { +; DEFAULT-LABEL: define void @invar_cond_gep_store( +; DEFAULT-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE14:%.*]] ] +; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]] +; DEFAULT-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT]], zeroinitializer +; DEFAULT-NEXT: [[TMP2:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT]], zeroinitializer +; DEFAULT-NEXT: [[TMP3:%.*]] = extractelement <4 x i1> [[TMP1]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP3]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; DEFAULT: pred.store.if: +; DEFAULT-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0 +; DEFAULT-NEXT: [[TMP5:%.*]] = add i64 [[TMP4]], 1 +; DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP5]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP6]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE]] +; DEFAULT: pred.store.continue: +; DEFAULT-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP1]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP7]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] +; DEFAULT: pred.store.if1: +; DEFAULT-NEXT: [[TMP8:%.*]] = add i64 [[OFFSET_IDX]], 1 +; DEFAULT-NEXT: [[TMP9:%.*]] = add i64 [[TMP8]], 1 +; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP9]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP10]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE2]] +; DEFAULT: pred.store.continue2: +; DEFAULT-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP1]], i32 2 +; DEFAULT-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] +; DEFAULT: pred.store.if3: +; DEFAULT-NEXT: [[TMP12:%.*]] = add i64 [[OFFSET_IDX]], 2 +; DEFAULT-NEXT: [[TMP13:%.*]] = add i64 [[TMP12]], 1 +; DEFAULT-NEXT: [[TMP14:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP13]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP14]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE4]] +; DEFAULT: pred.store.continue4: +; DEFAULT-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP1]], i32 3 +; DEFAULT-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]] +; DEFAULT: pred.store.if5: +; DEFAULT-NEXT: [[TMP16:%.*]] = add i64 [[OFFSET_IDX]], 3 +; DEFAULT-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 1 +; DEFAULT-NEXT: [[TMP18:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP17]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP18]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE6]] +; DEFAULT: pred.store.continue6: +; DEFAULT-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[TMP2]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP19]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8:%.*]] +; DEFAULT: pred.store.if7: +; DEFAULT-NEXT: [[TMP20:%.*]] = add i64 [[OFFSET_IDX]], 4 +; DEFAULT-NEXT: [[TMP21:%.*]] = add i64 [[TMP20]], 1 +; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP21]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP22]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE8]] +; DEFAULT: pred.store.continue8: +; DEFAULT-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[TMP2]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP23]], label [[PRED_STORE_IF9:%.*]], label [[PRED_STORE_CONTINUE10:%.*]] +; DEFAULT: pred.store.if9: +; DEFAULT-NEXT: [[TMP24:%.*]] = add i64 [[OFFSET_IDX]], 5 +; DEFAULT-NEXT: [[TMP25:%.*]] = add i64 [[TMP24]], 1 +; DEFAULT-NEXT: [[TMP26:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP25]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP26]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE10]] +; DEFAULT: pred.store.continue10: +; DEFAULT-NEXT: [[TMP27:%.*]] = extractelement <4 x i1> [[TMP2]], i32 2 +; DEFAULT-NEXT: br i1 [[TMP27]], label [[PRED_STORE_IF11:%.*]], label [[PRED_STORE_CONTINUE12:%.*]] +; DEFAULT: pred.store.if11: +; DEFAULT-NEXT: [[TMP28:%.*]] = add i64 [[OFFSET_IDX]], 6 +; DEFAULT-NEXT: [[TMP29:%.*]] = add i64 [[TMP28]], 1 +; DEFAULT-NEXT: [[TMP30:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP29]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP30]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE12]] +; DEFAULT: pred.store.continue12: +; DEFAULT-NEXT: [[TMP31:%.*]] = extractelement <4 x i1> [[TMP2]], i32 3 +; DEFAULT-NEXT: br i1 [[TMP31]], label [[PRED_STORE_IF13:%.*]], label [[PRED_STORE_CONTINUE14]] +; DEFAULT: pred.store.if13: +; DEFAULT-NEXT: [[TMP32:%.*]] = add i64 [[OFFSET_IDX]], 7 +; DEFAULT-NEXT: [[TMP33:%.*]] = add i64 [[TMP32]], 1 +; DEFAULT-NEXT: [[TMP34:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP33]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP34]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE14]] +; DEFAULT: pred.store.continue14: +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; DEFAULT-NEXT: [[TMP35:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 +; DEFAULT-NEXT: br i1 [[TMP35]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: br i1 false, label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 97, [[MIDDLE_BLOCK]] ], [ 1, [[ENTRY:%.*]] ] +; DEFAULT-NEXT: br label [[LOOP_HEADER:%.*]] +; DEFAULT: loop.header: +; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; DEFAULT-NEXT: [[CMP9:%.*]] = icmp eq i32 [[TMP0]], 0 +; DEFAULT-NEXT: br i1 [[CMP9]], label [[THEN:%.*]], label [[LOOP_LATCH]] +; DEFAULT: then: +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_NEXT]] +; DEFAULT-NEXT: store i32 1, ptr [[GEP]], align 4 +; DEFAULT-NEXT: br label [[LOOP_LATCH]] +; DEFAULT: loop.latch: +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100 +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @invar_cond_gep_store( +; PRED-SAME: ptr [[DST:%.*]], i32 [[TMP0:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ] +; PRED-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]] +; PRED-NEXT: [[TMP1:%.*]] = icmp eq <4 x i32> [[BROADCAST_SPLAT]], zeroinitializer +; PRED-NEXT: [[TMP2:%.*]] = extractelement <4 x i1> [[TMP1]], i32 0 +; PRED-NEXT: br i1 [[TMP2]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; PRED: pred.store.if: +; PRED-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 0 +; PRED-NEXT: [[TMP4:%.*]] = add i64 [[TMP3]], 1 +; PRED-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP4]] +; PRED-NEXT: store i32 1, ptr [[TMP5]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] +; PRED: pred.store.continue: +; PRED-NEXT: [[TMP6:%.*]] = extractelement <4 x i1> [[TMP1]], i32 1 +; PRED-NEXT: br i1 [[TMP6]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] +; PRED: pred.store.if1: +; PRED-NEXT: [[TMP7:%.*]] = add i64 [[OFFSET_IDX]], 1 +; PRED-NEXT: [[TMP8:%.*]] = add i64 [[TMP7]], 1 +; PRED-NEXT: [[TMP9:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP8]] +; PRED-NEXT: store i32 1, ptr [[TMP9]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE2]] +; PRED: pred.store.continue2: +; PRED-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP1]], i32 2 +; PRED-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] +; PRED: pred.store.if3: +; PRED-NEXT: [[TMP11:%.*]] = add i64 [[OFFSET_IDX]], 2 +; PRED-NEXT: [[TMP12:%.*]] = add i64 [[TMP11]], 1 +; PRED-NEXT: [[TMP13:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP12]] +; PRED-NEXT: store i32 1, ptr [[TMP13]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE4]] +; PRED: pred.store.continue4: +; PRED-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP1]], i32 3 +; PRED-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]] +; PRED: pred.store.if5: +; PRED-NEXT: [[TMP15:%.*]] = add i64 [[OFFSET_IDX]], 3 +; PRED-NEXT: [[TMP16:%.*]] = add i64 [[TMP15]], 1 +; PRED-NEXT: [[TMP17:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP16]] +; PRED-NEXT: store i32 1, ptr [[TMP17]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE6]] +; PRED: pred.store.continue6: +; PRED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; PRED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; PRED-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 101, [[MIDDLE_BLOCK]] ], [ 1, [[ENTRY:%.*]] ] +; PRED-NEXT: br label [[LOOP_HEADER:%.*]] +; PRED: loop.header: +; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; PRED-NEXT: [[CMP9:%.*]] = icmp eq i32 [[TMP0]], 0 +; PRED-NEXT: br i1 [[CMP9]], label [[THEN:%.*]], label [[LOOP_LATCH]] +; PRED: then: +; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_NEXT]] +; PRED-NEXT: store i32 1, ptr [[GEP]], align 4 +; PRED-NEXT: br label [[LOOP_LATCH]] +; PRED: loop.latch: +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100 +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP_HEADER]], !llvm.loop [[LOOP3:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 1, %entry ], [ %iv.next, %loop.latch ] + %iv.next = add i64 %iv, 1 + %cmp9 = icmp eq i32 %0, 0 + br i1 %cmp9, label %then, label %loop.latch + +then: + %gep = getelementptr i32, ptr %dst, i64 %iv.next + store i32 1, ptr %gep, align 4 + br label %loop.latch + +loop.latch: + %ec = icmp eq i64 %iv, 100 + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} + +declare double @llvm.fabs.f64(double) #0 + +define void @loop_dependent_cond(ptr %src, ptr noalias %dst, i64 %N) { +; DEFAULT-LABEL: define void @loop_dependent_cond( +; DEFAULT-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 4 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE7:%.*]] ] +; DEFAULT-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 2 +; DEFAULT-NEXT: [[TMP3:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP1]] +; DEFAULT-NEXT: [[TMP4:%.*]] = getelementptr double, ptr [[SRC]], i64 [[TMP2]] +; DEFAULT-NEXT: [[TMP5:%.*]] = getelementptr double, ptr [[TMP3]], i32 0 +; DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr double, ptr [[TMP3]], i32 2 +; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <2 x double>, ptr [[TMP5]], align 8 +; DEFAULT-NEXT: [[WIDE_LOAD1:%.*]] = load <2 x double>, ptr [[TMP6]], align 8 +; DEFAULT-NEXT: [[TMP7:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[WIDE_LOAD]]) +; DEFAULT-NEXT: [[TMP8:%.*]] = call <2 x double> @llvm.fabs.v2f64(<2 x double> [[WIDE_LOAD1]]) +; DEFAULT-NEXT: [[TMP9:%.*]] = fcmp ogt <2 x double> [[TMP7]], +; DEFAULT-NEXT: [[TMP10:%.*]] = fcmp ogt <2 x double> [[TMP8]], +; DEFAULT-NEXT: [[TMP11:%.*]] = extractelement <2 x i1> [[TMP9]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; DEFAULT: pred.store.if: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE]] +; DEFAULT: pred.store.continue: +; DEFAULT-NEXT: [[TMP12:%.*]] = extractelement <2 x i1> [[TMP9]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP12]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3:%.*]] +; DEFAULT: pred.store.if2: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE3]] +; DEFAULT: pred.store.continue3: +; DEFAULT-NEXT: [[TMP13:%.*]] = extractelement <2 x i1> [[TMP10]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]] +; DEFAULT: pred.store.if4: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE5]] +; DEFAULT: pred.store.continue5: +; DEFAULT-NEXT: [[TMP14:%.*]] = extractelement <2 x i1> [[TMP10]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7]] +; DEFAULT: pred.store.if6: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE7]] +; DEFAULT: pred.store.continue7: +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; DEFAULT-NEXT: [[TMP15:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP15]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[FOR_END123:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; DEFAULT-NEXT: br label [[FOR_BODY112:%.*]] +; DEFAULT: loop.header: +; DEFAULT-NEXT: [[IV175:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT176:%.*]], [[FOR_INC121:%.*]] ] +; DEFAULT-NEXT: [[ARRAYIDX114:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV175]] +; DEFAULT-NEXT: [[TMP16:%.*]] = load double, ptr [[ARRAYIDX114]], align 8 +; DEFAULT-NEXT: [[TMP17:%.*]] = tail call double @llvm.fabs.f64(double [[TMP16]]) +; DEFAULT-NEXT: [[CMP115:%.*]] = fcmp ogt double [[TMP17]], 1.000000e+00 +; DEFAULT-NEXT: br i1 [[CMP115]], label [[IF_THEN117:%.*]], label [[FOR_INC121]] +; DEFAULT: then: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[FOR_INC121]] +; DEFAULT: loop.latch: +; DEFAULT-NEXT: [[IV_NEXT176]] = add i64 [[IV175]], 1 +; DEFAULT-NEXT: [[EXITCOND180_NOT:%.*]] = icmp eq i64 [[IV175]], [[N]] +; DEFAULT-NEXT: br i1 [[EXITCOND180_NOT]], label [[FOR_END123]], label [[FOR_BODY112]], !llvm.loop [[LOOP5:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @loop_dependent_cond( +; PRED-SAME: ptr [[SRC:%.*]], ptr noalias [[DST:%.*]], i64 [[N:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: br label [[FOR_BODY112:%.*]] +; PRED: loop.header: +; PRED-NEXT: [[IV175:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[IV_NEXT176:%.*]], [[FOR_INC121:%.*]] ] +; PRED-NEXT: [[ARRAYIDX114:%.*]] = getelementptr double, ptr [[SRC]], i64 [[IV175]] +; PRED-NEXT: [[TMP0:%.*]] = load double, ptr [[ARRAYIDX114]], align 8 +; PRED-NEXT: [[TMP1:%.*]] = tail call double @llvm.fabs.f64(double [[TMP0]]) +; PRED-NEXT: [[CMP115:%.*]] = fcmp ogt double [[TMP1]], 1.000000e+00 +; PRED-NEXT: br i1 [[CMP115]], label [[IF_THEN117:%.*]], label [[FOR_INC121]] +; PRED: then: +; PRED-NEXT: store i32 0, ptr [[DST]], align 4 +; PRED-NEXT: br label [[FOR_INC121]] +; PRED: loop.latch: +; PRED-NEXT: [[IV_NEXT176]] = add i64 [[IV175]], 1 +; PRED-NEXT: [[EXITCOND180_NOT:%.*]] = icmp eq i64 [[IV175]], [[N]] +; PRED-NEXT: br i1 [[EXITCOND180_NOT]], label [[FOR_END123:%.*]], label [[FOR_BODY112]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop.latch ] + %gep = getelementptr double, ptr %src, i64 %iv + %l = load double, ptr %gep, align 8 + %abs = tail call double @llvm.fabs.f64(double %l) + %cmp = fcmp ogt double %abs, 1.000000e+00 + br i1 %cmp, label %then, label %loop.latch + +then: + store i32 0, ptr %dst, align 4 + br label %loop.latch + +loop.latch: + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, %N + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} + +define void @invar_cond_chain_1(ptr %I, ptr noalias %src, i1 %c) { +; DEFAULT-LABEL: define void @invar_cond_chain_1( +; DEFAULT-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], i1 [[C:%.*]]) { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64 +; DEFAULT-NEXT: [[I1:%.*]] = ptrtoint ptr [[I]] to i64 +; DEFAULT-NEXT: [[TMP29:%.*]] = sub i64 [[I1]], [[SRC2]] +; DEFAULT-NEXT: [[TMP0:%.*]] = lshr i64 [[TMP29]], 2 +; DEFAULT-NEXT: [[TMP1:%.*]] = add nuw nsw i64 [[TMP0]], 1 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP1]], 8 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP1]], 8 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP1]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP2:%.*]] = mul i64 [[N_VEC]], 4 +; DEFAULT-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP2]] +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i1> poison, i1 [[C]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i1> [[BROADCAST_SPLATINSERT]], <4 x i1> poison, <4 x i32> zeroinitializer +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE17:%.*]] ] +; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 +; DEFAULT-NEXT: [[TMP3:%.*]] = add i64 [[OFFSET_IDX]], 0 +; DEFAULT-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 16 +; DEFAULT-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP3]] +; DEFAULT-NEXT: [[NEXT_GEP3:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP4]] +; DEFAULT-NEXT: [[TMP5:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0 +; DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 4 +; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP5]], align 4 +; DEFAULT-NEXT: [[WIDE_LOAD3:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 +; DEFAULT-NEXT: [[TMP7:%.*]] = select <4 x i1> , <4 x i1> [[BROADCAST_SPLAT]], <4 x i1> zeroinitializer +; DEFAULT-NEXT: [[TMP8:%.*]] = select <4 x i1> , <4 x i1> [[BROADCAST_SPLAT]], <4 x i1> zeroinitializer +; DEFAULT-NEXT: [[TMP9:%.*]] = or <4 x i1> [[TMP7]], zeroinitializer +; DEFAULT-NEXT: [[TMP10:%.*]] = or <4 x i1> [[TMP8]], zeroinitializer +; DEFAULT-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP9]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; DEFAULT: pred.store.if: +; DEFAULT-NEXT: [[TMP12:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 0 +; DEFAULT-NEXT: store i32 [[TMP12]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE]] +; DEFAULT: pred.store.continue: +; DEFAULT-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP9]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]] +; DEFAULT: pred.store.if5: +; DEFAULT-NEXT: [[TMP14:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 1 +; DEFAULT-NEXT: store i32 [[TMP14]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE5]] +; DEFAULT: pred.store.continue6: +; DEFAULT-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP9]], i32 2 +; DEFAULT-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]] +; DEFAULT: pred.store.if7: +; DEFAULT-NEXT: [[TMP16:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 2 +; DEFAULT-NEXT: store i32 [[TMP16]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE7]] +; DEFAULT: pred.store.continue8: +; DEFAULT-NEXT: [[TMP17:%.*]] = extractelement <4 x i1> [[TMP9]], i32 3 +; DEFAULT-NEXT: br i1 [[TMP17]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9:%.*]] +; DEFAULT: pred.store.if9: +; DEFAULT-NEXT: [[TMP18:%.*]] = extractelement <4 x i32> [[WIDE_LOAD]], i32 3 +; DEFAULT-NEXT: store i32 [[TMP18]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE9]] +; DEFAULT: pred.store.continue10: +; DEFAULT-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[TMP10]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP19]], label [[PRED_STORE_IF10:%.*]], label [[PRED_STORE_CONTINUE11:%.*]] +; DEFAULT: pred.store.if11: +; DEFAULT-NEXT: [[TMP20:%.*]] = extractelement <4 x i32> [[WIDE_LOAD3]], i32 0 +; DEFAULT-NEXT: store i32 [[TMP20]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE11]] +; DEFAULT: pred.store.continue12: +; DEFAULT-NEXT: [[TMP21:%.*]] = extractelement <4 x i1> [[TMP10]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP21]], label [[PRED_STORE_IF12:%.*]], label [[PRED_STORE_CONTINUE13:%.*]] +; DEFAULT: pred.store.if13: +; DEFAULT-NEXT: [[TMP22:%.*]] = extractelement <4 x i32> [[WIDE_LOAD3]], i32 1 +; DEFAULT-NEXT: store i32 [[TMP22]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE13]] +; DEFAULT: pred.store.continue14: +; DEFAULT-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[TMP10]], i32 2 +; DEFAULT-NEXT: br i1 [[TMP23]], label [[PRED_STORE_IF14:%.*]], label [[PRED_STORE_CONTINUE15:%.*]] +; DEFAULT: pred.store.if15: +; DEFAULT-NEXT: [[TMP24:%.*]] = extractelement <4 x i32> [[WIDE_LOAD3]], i32 2 +; DEFAULT-NEXT: store i32 [[TMP24]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE15]] +; DEFAULT: pred.store.continue16: +; DEFAULT-NEXT: [[TMP25:%.*]] = extractelement <4 x i1> [[TMP10]], i32 3 +; DEFAULT-NEXT: br i1 [[TMP25]], label [[PRED_STORE_IF16:%.*]], label [[PRED_STORE_CONTINUE17]] +; DEFAULT: pred.store.if17: +; DEFAULT-NEXT: [[TMP26:%.*]] = extractelement <4 x i32> [[WIDE_LOAD3]], i32 3 +; DEFAULT-NEXT: store i32 [[TMP26]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE17]] +; DEFAULT: pred.store.continue18: +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; DEFAULT-NEXT: [[TMP27:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP27]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP1]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP312_LOOPEXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SRC]], [[ENTRY:%.*]] ] +; DEFAULT-NEXT: br label [[FOR_BODY313:%.*]] +; DEFAULT: loop.header: +; DEFAULT-NEXT: [[__BEGIN3_011973:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INCDEC_PTR329:%.*]], [[IF_END327:%.*]] ] +; DEFAULT-NEXT: [[TMP28:%.*]] = load i32, ptr [[__BEGIN3_011973]], align 4 +; DEFAULT-NEXT: br i1 true, label [[IF_ELSE321:%.*]], label [[IF_THEN316:%.*]] +; DEFAULT: if: +; DEFAULT-NEXT: br label [[IF_END327_SINK_SPLIT:%.*]] +; DEFAULT: else.1: +; DEFAULT-NEXT: br i1 [[C]], label [[IF_THEN323:%.*]], label [[IF_END327]] +; DEFAULT: else.2: +; DEFAULT-NEXT: br label [[IF_END327_SINK_SPLIT]] +; DEFAULT: split: +; DEFAULT-NEXT: store i32 [[TMP28]], ptr [[I]], align 4 +; DEFAULT-NEXT: br label [[IF_END327]] +; DEFAULT: loop.latch: +; DEFAULT-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_011973]], i64 4 +; DEFAULT-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_011973]], [[I]] +; DEFAULT-NEXT: br i1 [[CMP311_NOT]], label [[FOR_COND_CLEANUP312_LOOPEXIT]], label [[FOR_BODY313]], !llvm.loop [[LOOP7:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @invar_cond_chain_1( +; PRED-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], i1 [[C:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: br label [[FOR_BODY313:%.*]] +; PRED: loop.header: +; PRED-NEXT: [[__BEGIN3_011973:%.*]] = phi ptr [ [[SRC]], [[ENTRY:%.*]] ], [ [[INCDEC_PTR329:%.*]], [[IF_END327:%.*]] ] +; PRED-NEXT: [[TMP0:%.*]] = load i32, ptr [[__BEGIN3_011973]], align 4 +; PRED-NEXT: br i1 true, label [[IF_ELSE321:%.*]], label [[IF_THEN316:%.*]] +; PRED: if: +; PRED-NEXT: br label [[IF_END327_SINK_SPLIT:%.*]] +; PRED: else.1: +; PRED-NEXT: br i1 [[C]], label [[IF_THEN323:%.*]], label [[IF_END327]] +; PRED: else.2: +; PRED-NEXT: br label [[IF_END327_SINK_SPLIT]] +; PRED: split: +; PRED-NEXT: store i32 [[TMP0]], ptr [[I]], align 4 +; PRED-NEXT: br label [[IF_END327]] +; PRED: loop.latch: +; PRED-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_011973]], i64 4 +; PRED-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_011973]], [[I]] +; PRED-NEXT: br i1 [[CMP311_NOT]], label [[FOR_COND_CLEANUP312_LOOPEXIT:%.*]], label [[FOR_BODY313]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop.latch ] + %l = load i32, ptr %ptr.iv, align 4 + br i1 true, label %else.1, label %if + +if: + br label %split + +else.1: + br i1 %c, label %else.2, label %loop.latch + +else.2: + br label %split + +split: + store i32 %l, ptr %I, align 4 + br label %loop.latch + +loop.latch: + %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 4 + %ec = icmp eq ptr %ptr.iv, %I + br i1 %ec, label %exit, label %loop.header + +exit: + ret void +} + +define void @invar_cond_chain_2(ptr %I, ptr noalias %src, ptr noalias %dst, i32 %a) { +; DEFAULT-LABEL: define void @invar_cond_chain_2( +; DEFAULT-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[A:%.*]]) { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64 +; DEFAULT-NEXT: [[I1:%.*]] = ptrtoint ptr [[I]] to i64 +; DEFAULT-NEXT: [[TMP0:%.*]] = sub i64 [[I1]], [[SRC2]] +; DEFAULT-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2 +; DEFAULT-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 +; DEFAULT-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP3]] +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE15:%.*]] ] +; DEFAULT-NEXT: [[TMP4:%.*]] = icmp sgt <4 x i32> [[BROADCAST_SPLAT]], zeroinitializer +; DEFAULT-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[BROADCAST_SPLAT]], zeroinitializer +; DEFAULT-NEXT: [[TMP6:%.*]] = xor <4 x i1> [[TMP4]], +; DEFAULT-NEXT: [[TMP7:%.*]] = xor <4 x i1> [[TMP5]], +; DEFAULT-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP6]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; DEFAULT: pred.store.if: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE]] +; DEFAULT: pred.store.continue: +; DEFAULT-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP6]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3:%.*]] +; DEFAULT: pred.store.if3: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE3]] +; DEFAULT: pred.store.continue4: +; DEFAULT-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP6]], i32 2 +; DEFAULT-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]] +; DEFAULT: pred.store.if5: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE5]] +; DEFAULT: pred.store.continue6: +; DEFAULT-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP6]], i32 3 +; DEFAULT-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]] +; DEFAULT: pred.store.if7: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE7]] +; DEFAULT: pred.store.continue8: +; DEFAULT-NEXT: [[TMP12:%.*]] = extractelement <4 x i1> [[TMP7]], i32 0 +; DEFAULT-NEXT: br i1 [[TMP12]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9:%.*]] +; DEFAULT: pred.store.if9: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE9]] +; DEFAULT: pred.store.continue10: +; DEFAULT-NEXT: [[TMP13:%.*]] = extractelement <4 x i1> [[TMP7]], i32 1 +; DEFAULT-NEXT: br i1 [[TMP13]], label [[PRED_STORE_IF10:%.*]], label [[PRED_STORE_CONTINUE11:%.*]] +; DEFAULT: pred.store.if11: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE11]] +; DEFAULT: pred.store.continue12: +; DEFAULT-NEXT: [[TMP14:%.*]] = extractelement <4 x i1> [[TMP7]], i32 2 +; DEFAULT-NEXT: br i1 [[TMP14]], label [[PRED_STORE_IF12:%.*]], label [[PRED_STORE_CONTINUE13:%.*]] +; DEFAULT: pred.store.if13: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE13]] +; DEFAULT: pred.store.continue14: +; DEFAULT-NEXT: [[TMP15:%.*]] = extractelement <4 x i1> [[TMP7]], i32 3 +; DEFAULT-NEXT: br i1 [[TMP15]], label [[PRED_STORE_IF14:%.*]], label [[PRED_STORE_CONTINUE15]] +; DEFAULT: pred.store.if15: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[PRED_STORE_CONTINUE15]] +; DEFAULT: pred.store.continue16: +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; DEFAULT-NEXT: [[TMP16:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP312_LOOPEXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SRC]], [[ENTRY:%.*]] ] +; DEFAULT-NEXT: br label [[FOR_BODY313:%.*]] +; DEFAULT: loop.header: +; DEFAULT-NEXT: [[__BEGIN3_01197:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INCDEC_PTR329:%.*]], [[IF_END327:%.*]] ] +; DEFAULT-NEXT: [[CMP315_NOT:%.*]] = icmp sgt i32 [[A]], 0 +; DEFAULT-NEXT: br i1 [[CMP315_NOT]], label [[IF_END327]], label [[IF_THEN316:%.*]] +; DEFAULT: if: +; DEFAULT-NEXT: br label [[IF_END327_SINK_SPLIT:%.*]] +; DEFAULT: else: +; DEFAULT-NEXT: store i32 0, ptr [[DST]], align 4 +; DEFAULT-NEXT: br label [[IF_END327]] +; DEFAULT: loop.latch: +; DEFAULT-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_01197]], i64 4 +; DEFAULT-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_01197]], [[I]] +; DEFAULT-NEXT: br i1 [[CMP311_NOT]], label [[FOR_COND_CLEANUP312_LOOPEXIT]], label [[FOR_BODY313]], !llvm.loop [[LOOP9:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @invar_cond_chain_2( +; PRED-SAME: ptr [[I:%.*]], ptr noalias [[SRC:%.*]], ptr noalias [[DST:%.*]], i32 [[A:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64 +; PRED-NEXT: [[I1:%.*]] = ptrtoint ptr [[I]] to i64 +; PRED-NEXT: [[TMP0:%.*]] = sub i64 [[I1]], [[SRC2]] +; PRED-NEXT: [[TMP1:%.*]] = lshr i64 [[TMP0]], 2 +; PRED-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP2]], 3 +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4 +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 +; PRED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP3]] +; PRED-NEXT: [[TRIP_COUNT_MINUS_1:%.*]] = sub i64 [[TMP2]], 1 +; PRED-NEXT: [[BROADCAST_SPLATINSERT2:%.*]] = insertelement <4 x i64> poison, i64 [[TRIP_COUNT_MINUS_1]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT3:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT2]], <4 x i64> poison, <4 x i32> zeroinitializer +; PRED-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT5:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT4]], <4 x i32> poison, <4 x i32> zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE11:%.*]] ] +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i64> poison, i64 [[INDEX]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i64> [[BROADCAST_SPLATINSERT]], <4 x i64> poison, <4 x i32> zeroinitializer +; PRED-NEXT: [[VEC_IV:%.*]] = add <4 x i64> [[BROADCAST_SPLAT]], +; PRED-NEXT: [[TMP4:%.*]] = icmp ule <4 x i64> [[VEC_IV]], [[BROADCAST_SPLAT3]] +; PRED-NEXT: [[TMP5:%.*]] = icmp sgt <4 x i32> [[BROADCAST_SPLAT5]], zeroinitializer +; PRED-NEXT: [[TMP6:%.*]] = xor <4 x i1> [[TMP5]], +; PRED-NEXT: [[TMP7:%.*]] = select <4 x i1> [[TMP4]], <4 x i1> [[TMP6]], <4 x i1> zeroinitializer +; PRED-NEXT: [[TMP8:%.*]] = extractelement <4 x i1> [[TMP7]], i32 0 +; PRED-NEXT: br i1 [[TMP8]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; PRED: pred.store.if: +; PRED-NEXT: store i32 0, ptr [[DST]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] +; PRED: pred.store.continue: +; PRED-NEXT: [[TMP9:%.*]] = extractelement <4 x i1> [[TMP7]], i32 1 +; PRED-NEXT: br i1 [[TMP9]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7:%.*]] +; PRED: pred.store.if7: +; PRED-NEXT: store i32 0, ptr [[DST]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE7]] +; PRED: pred.store.continue8: +; PRED-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP7]], i32 2 +; PRED-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF8:%.*]], label [[PRED_STORE_CONTINUE9:%.*]] +; PRED: pred.store.if9: +; PRED-NEXT: store i32 0, ptr [[DST]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE9]] +; PRED: pred.store.continue10: +; PRED-NEXT: [[TMP11:%.*]] = extractelement <4 x i1> [[TMP7]], i32 3 +; PRED-NEXT: br i1 [[TMP11]], label [[PRED_STORE_IF10:%.*]], label [[PRED_STORE_CONTINUE11]] +; PRED: pred.store.if11: +; PRED-NEXT: store i32 0, ptr [[DST]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE11]] +; PRED: pred.store.continue12: +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 +; PRED-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; PRED-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[FOR_COND_CLEANUP312_LOOPEXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SRC]], [[ENTRY:%.*]] ] +; PRED-NEXT: br label [[FOR_BODY313:%.*]] +; PRED: loop.header: +; PRED-NEXT: [[__BEGIN3_01197:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INCDEC_PTR329:%.*]], [[IF_END327:%.*]] ] +; PRED-NEXT: [[CMP315_NOT:%.*]] = icmp sgt i32 [[A]], 0 +; PRED-NEXT: br i1 [[CMP315_NOT]], label [[IF_END327]], label [[IF_THEN316:%.*]] +; PRED: if: +; PRED-NEXT: br label [[IF_END327_SINK_SPLIT:%.*]] +; PRED: else: +; PRED-NEXT: store i32 0, ptr [[DST]], align 4 +; PRED-NEXT: br label [[IF_END327]] +; PRED: loop.latch: +; PRED-NEXT: [[INCDEC_PTR329]] = getelementptr inbounds i8, ptr [[__BEGIN3_01197]], i64 4 +; PRED-NEXT: [[CMP311_NOT:%.*]] = icmp eq ptr [[__BEGIN3_01197]], [[I]] +; PRED-NEXT: br i1 [[CMP311_NOT]], label [[FOR_COND_CLEANUP312_LOOPEXIT]], label [[FOR_BODY313]], !llvm.loop [[LOOP5:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop.header + +loop.header: + %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop.latch ] + %cmp315.not = icmp sgt i32 %a, 0 + br i1 %cmp315.not, label %loop.latch, label %if + +if: + br label %else + +else: + store i32 0, ptr %dst, align 4 + br label %loop.latch + +loop.latch: + %ptr.iv.next = getelementptr inbounds i8, ptr %ptr.iv, i64 4 + %cmp311.not = icmp eq ptr %ptr.iv, %I + br i1 %cmp311.not, label %exit, label %loop.header + +exit: + ret void +} + +define void @latch_branch_cost(ptr %dst) { +; DEFAULT-LABEL: define void @latch_branch_cost( +; DEFAULT-SAME: ptr [[DST:%.*]]) { +; DEFAULT-NEXT: iter.check: +; DEFAULT-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.main.loop.iter.check: +; DEFAULT-NEXT: br i1 false, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH1:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH1]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP1:%.*]] = add i64 [[INDEX]], 16 +; DEFAULT-NEXT: [[TMP2:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]] +; DEFAULT-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP1]] +; DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP2]], i32 0 +; DEFAULT-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[TMP2]], i32 16 +; DEFAULT-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP6]], align 1 +; DEFAULT-NEXT: store <16 x i8> zeroinitializer, ptr [[TMP5]], align 1 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 +; DEFAULT-NEXT: [[TMP4:%.*]] = icmp eq i64 [[INDEX_NEXT]], 96 +; DEFAULT-NEXT: br i1 [[TMP4]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: br i1 false, label [[FOR_END:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] +; DEFAULT: vec.epilog.iter.check: +; DEFAULT-NEXT: br i1 false, label [[SCALAR_PH]], label [[VEC_EPILOG_PH]] +; DEFAULT: vec.epilog.ph: +; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 96, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_PH]] ] +; DEFAULT-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] +; DEFAULT: vec.epilog.vector.body: +; DEFAULT-NEXT: [[INDEX1:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT2:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP7:%.*]] = add i64 [[INDEX1]], 0 +; DEFAULT-NEXT: [[TMP8:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP7]] +; DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[TMP8]], i32 0 +; DEFAULT-NEXT: store <4 x i8> zeroinitializer, ptr [[TMP9]], align 1 +; DEFAULT-NEXT: [[INDEX_NEXT2]] = add nuw i64 [[INDEX1]], 4 +; DEFAULT-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT2]], 100 +; DEFAULT-NEXT: br i1 [[TMP10]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] +; DEFAULT: vec.epilog.middle.block: +; DEFAULT-NEXT: br i1 true, label [[FOR_END]], label [[SCALAR_PH]] +; DEFAULT: vec.epilog.scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 96, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] +; DEFAULT-NEXT: br label [[FOR_BODY:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] +; DEFAULT-NEXT: [[ARRAYIDX:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDVARS_IV]] +; DEFAULT-NEXT: store i8 0, ptr [[ARRAYIDX]], align 1 +; DEFAULT-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 +; DEFAULT-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 100 +; DEFAULT-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP12:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @latch_branch_cost( +; PRED-SAME: ptr [[DST:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE6:%.*]] ] +; PRED-NEXT: [[VEC_IND:%.*]] = phi <4 x i64> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE6]] ] +; PRED-NEXT: [[TMP0:%.*]] = icmp ule <4 x i64> [[VEC_IND]], +; PRED-NEXT: [[TMP1:%.*]] = extractelement <4 x i1> [[TMP0]], i32 0 +; PRED-NEXT: br i1 [[TMP1]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; PRED: pred.store.if: +; PRED-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0 +; PRED-NEXT: [[TMP3:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP2]] +; PRED-NEXT: store i8 0, ptr [[TMP3]], align 1 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] +; PRED: pred.store.continue: +; PRED-NEXT: [[TMP4:%.*]] = extractelement <4 x i1> [[TMP0]], i32 1 +; PRED-NEXT: br i1 [[TMP4]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2:%.*]] +; PRED: pred.store.if1: +; PRED-NEXT: [[TMP5:%.*]] = add i64 [[INDEX]], 1 +; PRED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP5]] +; PRED-NEXT: store i8 0, ptr [[TMP6]], align 1 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE2]] +; PRED: pred.store.continue2: +; PRED-NEXT: [[TMP7:%.*]] = extractelement <4 x i1> [[TMP0]], i32 2 +; PRED-NEXT: br i1 [[TMP7]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] +; PRED: pred.store.if3: +; PRED-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 2 +; PRED-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP8]] +; PRED-NEXT: store i8 0, ptr [[TMP9]], align 1 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE4]] +; PRED: pred.store.continue4: +; PRED-NEXT: [[TMP10:%.*]] = extractelement <4 x i1> [[TMP0]], i32 3 +; PRED-NEXT: br i1 [[TMP10]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6]] +; PRED: pred.store.if5: +; PRED-NEXT: [[TMP11:%.*]] = add i64 [[INDEX]], 3 +; PRED-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP11]] +; PRED-NEXT: store i8 0, ptr [[TMP12]], align 1 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE6]] +; PRED: pred.store.continue6: +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 +; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i64> [[VEC_IND]], +; PRED-NEXT: [[TMP13:%.*]] = icmp eq i64 [[INDEX_NEXT]], 100 +; PRED-NEXT: br i1 [[TMP13]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[FOR_END:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 100, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; PRED-NEXT: br label [[FOR_BODY:%.*]] +; PRED: loop: +; PRED-NEXT: [[INDVARS_IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[INDVARS_IV_NEXT:%.*]], [[FOR_BODY]] ] +; PRED-NEXT: [[ARRAYIDX:%.*]] = getelementptr i8, ptr [[DST]], i64 [[INDVARS_IV]] +; PRED-NEXT: store i8 0, ptr [[ARRAYIDX]], align 1 +; PRED-NEXT: [[INDVARS_IV_NEXT]] = add i64 [[INDVARS_IV]], 1 +; PRED-NEXT: [[EXITCOND_NOT:%.*]] = icmp eq i64 [[INDVARS_IV_NEXT]], 100 +; PRED-NEXT: br i1 [[EXITCOND_NOT]], label [[FOR_END]], label [[FOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr i8, ptr %dst, i64 %iv + store i8 0, ptr %gep, align 1 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv.next, 100 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +;. +; DEFAULT: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; DEFAULT: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; DEFAULT: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; DEFAULT: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; DEFAULT: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} +; DEFAULT: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} +; DEFAULT: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP9]] = distinct !{[[LOOP9]], [[META2]], [[META1]]} +; DEFAULT: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP12]] = distinct !{[[LOOP12]], [[META2]], [[META1]]} +;. +; PRED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; PRED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; PRED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; PRED: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; PRED: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; PRED: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} +; PRED: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} +; PRED: [[LOOP7]] = distinct !{[[LOOP7]], [[META2]], [[META1]]} +;. diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll new file mode 100644 index 000000000000..af5decb0d340 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs-sve.ll @@ -0,0 +1,916 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=DEFAULT %s +; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=PRED %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-macosx14.0.0" + +define void @iv_casts(ptr %dst, ptr %src, i32 %x, i64 %N) #0 { +; DEFAULT-LABEL: define void @iv_casts( +; DEFAULT-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; DEFAULT-NEXT: iter.check: +; DEFAULT-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64 +; DEFAULT-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64 +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; DEFAULT: vector.memcheck: +; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8 +; DEFAULT-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 2 +; DEFAULT-NEXT: [[TMP6:%.*]] = sub i64 [[DST1]], [[SRC2]] +; DEFAULT-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP6]], [[TMP5]] +; DEFAULT-NEXT: br i1 [[DIFF_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; DEFAULT: vector.main.loop.iter.check: +; DEFAULT-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 16 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK3:%.*]] = icmp ult i64 [[TMP0]], [[TMP8]] +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK3]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 16 +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP10]] +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 16 +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i32 [[X]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; DEFAULT-NEXT: [[TMP13:%.*]] = trunc [[BROADCAST_SPLAT]] to +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP14:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], 8 +; DEFAULT-NEXT: [[TMP17:%.*]] = add i64 [[TMP16]], 0 +; DEFAULT-NEXT: [[TMP18:%.*]] = mul i64 [[TMP17]], 1 +; DEFAULT-NEXT: [[TMP19:%.*]] = add i64 [[INDEX]], [[TMP18]] +; DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP14]] +; DEFAULT-NEXT: [[TMP21:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP19]] +; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr i8, ptr [[TMP20]], i32 0 +; DEFAULT-NEXT: [[TMP23:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP24:%.*]] = mul i64 [[TMP23]], 8 +; DEFAULT-NEXT: [[TMP25:%.*]] = getelementptr i8, ptr [[TMP20]], i64 [[TMP24]] +; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP22]], align 1 +; DEFAULT-NEXT: [[WIDE_LOAD4:%.*]] = load , ptr [[TMP25]], align 1 +; DEFAULT-NEXT: [[TMP26:%.*]] = zext [[WIDE_LOAD]] to +; DEFAULT-NEXT: [[TMP27:%.*]] = zext [[WIDE_LOAD4]] to +; DEFAULT-NEXT: [[TMP28:%.*]] = mul [[TMP26]], [[TMP13]] +; DEFAULT-NEXT: [[TMP29:%.*]] = mul [[TMP27]], [[TMP13]] +; DEFAULT-NEXT: [[TMP30:%.*]] = zext [[WIDE_LOAD]] to +; DEFAULT-NEXT: [[TMP31:%.*]] = zext [[WIDE_LOAD4]] to +; DEFAULT-NEXT: [[TMP32:%.*]] = or [[TMP28]], [[TMP30]] +; DEFAULT-NEXT: [[TMP33:%.*]] = or [[TMP29]], [[TMP31]] +; DEFAULT-NEXT: [[TMP34:%.*]] = lshr [[TMP32]], trunc ( shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) to ) +; DEFAULT-NEXT: [[TMP35:%.*]] = lshr [[TMP33]], trunc ( shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) to ) +; DEFAULT-NEXT: [[TMP36:%.*]] = trunc [[TMP34]] to +; DEFAULT-NEXT: [[TMP37:%.*]] = trunc [[TMP35]] to +; DEFAULT-NEXT: [[TMP38:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP14]] +; DEFAULT-NEXT: [[TMP39:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP19]] +; DEFAULT-NEXT: [[TMP40:%.*]] = getelementptr i8, ptr [[TMP38]], i32 0 +; DEFAULT-NEXT: [[TMP41:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP42:%.*]] = mul i64 [[TMP41]], 8 +; DEFAULT-NEXT: [[TMP43:%.*]] = getelementptr i8, ptr [[TMP38]], i64 [[TMP42]] +; DEFAULT-NEXT: store [[TMP36]], ptr [[TMP40]], align 1 +; DEFAULT-NEXT: store [[TMP37]], ptr [[TMP43]], align 1 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP12]] +; DEFAULT-NEXT: [[TMP44:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP44]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] +; DEFAULT: vec.epilog.iter.check: +; DEFAULT-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: [[TMP45:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP46:%.*]] = mul i64 [[TMP45]], 4 +; DEFAULT-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], [[TMP46]] +; DEFAULT-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]] +; DEFAULT: vec.epilog.ph: +; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; DEFAULT-NEXT: [[TMP47:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP48:%.*]] = mul i64 [[TMP47]], 4 +; DEFAULT-NEXT: [[N_MOD_VF5:%.*]] = urem i64 [[TMP0]], [[TMP48]] +; DEFAULT-NEXT: [[N_VEC6:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF5]] +; DEFAULT-NEXT: [[TMP49:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP50:%.*]] = mul i64 [[TMP49]], 4 +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement poison, i32 [[X]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector [[BROADCAST_SPLATINSERT8]], poison, zeroinitializer +; DEFAULT-NEXT: [[TMP51:%.*]] = trunc [[BROADCAST_SPLAT9]] to +; DEFAULT-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] +; DEFAULT: vec.epilog.vector.body: +; DEFAULT-NEXT: [[INDEX10:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT12:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP52:%.*]] = add i64 [[INDEX10]], 0 +; DEFAULT-NEXT: [[TMP53:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP52]] +; DEFAULT-NEXT: [[TMP54:%.*]] = getelementptr i8, ptr [[TMP53]], i32 0 +; DEFAULT-NEXT: [[WIDE_LOAD11:%.*]] = load , ptr [[TMP54]], align 1 +; DEFAULT-NEXT: [[TMP55:%.*]] = zext [[WIDE_LOAD11]] to +; DEFAULT-NEXT: [[TMP56:%.*]] = mul [[TMP55]], [[TMP51]] +; DEFAULT-NEXT: [[TMP57:%.*]] = zext [[WIDE_LOAD11]] to +; DEFAULT-NEXT: [[TMP58:%.*]] = or [[TMP56]], [[TMP57]] +; DEFAULT-NEXT: [[TMP59:%.*]] = lshr [[TMP58]], trunc ( shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) to ) +; DEFAULT-NEXT: [[TMP60:%.*]] = trunc [[TMP59]] to +; DEFAULT-NEXT: [[TMP61:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP52]] +; DEFAULT-NEXT: [[TMP62:%.*]] = getelementptr i8, ptr [[TMP61]], i32 0 +; DEFAULT-NEXT: store [[TMP60]], ptr [[TMP62]], align 1 +; DEFAULT-NEXT: [[INDEX_NEXT12]] = add nuw i64 [[INDEX10]], [[TMP50]] +; DEFAULT-NEXT: [[TMP63:%.*]] = icmp eq i64 [[INDEX_NEXT12]], [[N_VEC6]] +; DEFAULT-NEXT: br i1 [[TMP63]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] +; DEFAULT: vec.epilog.middle.block: +; DEFAULT-NEXT: [[CMP_N7:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC6]] +; DEFAULT-NEXT: br i1 [[CMP_N7]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] +; DEFAULT: vec.epilog.scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC6]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]] +; DEFAULT-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 +; DEFAULT-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32 +; DEFAULT-NEXT: [[MUL16_US:%.*]] = mul i32 [[L_EXT]], [[X]] +; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; DEFAULT-NEXT: [[CONV25_US:%.*]] = zext i8 [[L]] to i32 +; DEFAULT-NEXT: [[ADD34_US:%.*]] = or i32 [[MUL16_US]], [[CONV25_US]] +; DEFAULT-NEXT: [[SHR35_US:%.*]] = lshr i32 [[ADD34_US]], 1 +; DEFAULT-NEXT: [[CONV36_US:%.*]] = trunc i32 [[SHR35_US]] to i8 +; DEFAULT-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; DEFAULT-NEXT: store i8 [[CONV36_US]], ptr [[GEP_DST]], align 1 +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP4:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @iv_casts( +; PRED-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i32 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0:[0-9]+]] { +; PRED-NEXT: entry: +; PRED-NEXT: [[SRC2:%.*]] = ptrtoint ptr [[SRC]] to i64 +; PRED-NEXT: [[DST1:%.*]] = ptrtoint ptr [[DST]] to i64 +; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; PRED: vector.memcheck: +; PRED-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8 +; PRED-NEXT: [[TMP3:%.*]] = sub i64 [[DST1]], [[SRC2]] +; PRED-NEXT: [[DIFF_CHECK:%.*]] = icmp ult i64 [[TMP3]], [[TMP2]] +; PRED-NEXT: br i1 [[DIFF_CHECK]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 8 +; PRED-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 8 +; PRED-NEXT: [[TMP8:%.*]] = sub i64 [[TMP7]], 1 +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], [[TMP8]] +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP5]] +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[TMP9:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP10:%.*]] = mul i64 [[TMP9]], 8 +; PRED-NEXT: [[TMP11:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP12:%.*]] = mul i64 [[TMP11]], 8 +; PRED-NEXT: [[TMP13:%.*]] = sub i64 [[TMP0]], [[TMP12]] +; PRED-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP0]], [[TMP12]] +; PRED-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP13]], i64 0 +; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 [[TMP0]]) +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i32 [[X]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; PRED-NEXT: [[TMP16:%.*]] = trunc [[BROADCAST_SPLAT]] to +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[TMP17:%.*]] = add i64 [[INDEX]], 0 +; PRED-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP17]] +; PRED-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[TMP18]], i32 0 +; PRED-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call @llvm.masked.load.nxv8i8.p0(ptr [[TMP19]], i32 1, [[ACTIVE_LANE_MASK]], poison) +; PRED-NEXT: [[TMP20:%.*]] = zext [[WIDE_MASKED_LOAD]] to +; PRED-NEXT: [[TMP21:%.*]] = mul [[TMP20]], [[TMP16]] +; PRED-NEXT: [[TMP22:%.*]] = zext [[WIDE_MASKED_LOAD]] to +; PRED-NEXT: [[TMP23:%.*]] = or [[TMP21]], [[TMP22]] +; PRED-NEXT: [[TMP24:%.*]] = lshr [[TMP23]], trunc ( shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) to ) +; PRED-NEXT: [[TMP25:%.*]] = trunc [[TMP24]] to +; PRED-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP17]] +; PRED-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP26]], i32 0 +; PRED-NEXT: call void @llvm.masked.store.nxv8i8.p0( [[TMP25]], ptr [[TMP27]], i32 1, [[ACTIVE_LANE_MASK]]) +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP10]] +; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 [[INDEX]], i64 [[TMP15]]) +; PRED-NEXT: [[TMP28:%.*]] = xor [[ACTIVE_LANE_MASK_NEXT]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP29:%.*]] = extractelement [[TMP28]], i32 0 +; PRED-NEXT: br i1 [[TMP29]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[GEP_SRC:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[IV]] +; PRED-NEXT: [[L:%.*]] = load i8, ptr [[GEP_SRC]], align 1 +; PRED-NEXT: [[L_EXT:%.*]] = zext i8 [[L]] to i32 +; PRED-NEXT: [[MUL16_US:%.*]] = mul i32 [[L_EXT]], [[X]] +; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; PRED-NEXT: [[CONV25_US:%.*]] = zext i8 [[L]] to i32 +; PRED-NEXT: [[ADD34_US:%.*]] = or i32 [[MUL16_US]], [[CONV25_US]] +; PRED-NEXT: [[SHR35_US:%.*]] = lshr i32 [[ADD34_US]], 1 +; PRED-NEXT: [[CONV36_US:%.*]] = trunc i32 [[SHR35_US]] to i8 +; PRED-NEXT: [[GEP_DST:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; PRED-NEXT: store i8 [[CONV36_US]], ptr [[GEP_DST]], align 1 +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep.src = getelementptr i8, ptr %src, i64 %iv + %l = load i8, ptr %gep.src, align 1 + %l.ext = zext i8 %l to i32 + %mul = mul i32 %l.ext, %x + %iv.next = add i64 %iv, 1 + %l.ext.2 = zext i8 %l to i32 + %or = or i32 %mul, %l.ext.2 + %lshr = lshr i32 %or, 1 + %trunc = trunc i32 %lshr to i8 + %gep.dst = getelementptr i8, ptr %dst, i64 %iv + store i8 %trunc, ptr %gep.dst, align 1 + %ec = icmp eq i64 %iv, %N + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +define void @iv_trunc(i32 %x, ptr %dst, i64 %N) #0 { +; DEFAULT-LABEL: define void @iv_trunc( +; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[MUL_X:%.*]] = add i32 [[X]], 1 +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; DEFAULT: vector.scevcheck: +; DEFAULT-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] +; DEFAULT-NEXT: [[TMP2:%.*]] = icmp slt i32 [[MUL_X]], 0 +; DEFAULT-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[MUL_X]] +; DEFAULT-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 +; DEFAULT-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) +; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 +; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 +; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] +; DEFAULT-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 +; DEFAULT-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false +; DEFAULT-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] +; DEFAULT-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 +; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ne i32 [[MUL_X]], 0 +; DEFAULT-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] +; DEFAULT-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] +; DEFAULT-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP13:%.*]] = trunc i64 [[INDEX]] to i32 +; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[TMP13]], 0 +; DEFAULT-NEXT: [[TMP15:%.*]] = add i32 [[TMP13]], 1 +; DEFAULT-NEXT: [[TMP16:%.*]] = mul i32 [[MUL_X]], [[TMP14]] +; DEFAULT-NEXT: [[TMP17:%.*]] = mul i32 [[MUL_X]], [[TMP15]] +; DEFAULT-NEXT: [[TMP18:%.*]] = zext i32 [[TMP16]] to i64 +; DEFAULT-NEXT: [[TMP19:%.*]] = zext i32 [[TMP17]] to i64 +; DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP18]] +; DEFAULT-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP19]] +; DEFAULT-NEXT: store i32 1, ptr [[TMP20]], align 4 +; DEFAULT-NEXT: store i32 1, ptr [[TMP21]], align 4 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; DEFAULT-NEXT: [[TMP22:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP22]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: br label [[FOR_BODY:%.*]] +; DEFAULT: for.body: +; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] +; DEFAULT-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i32 +; DEFAULT-NEXT: [[ADD_I:%.*]] = mul i32 [[MUL_X]], [[TRUNC_IV]] +; DEFAULT-NEXT: [[IV_MUL:%.*]] = zext i32 [[ADD_I]] to i64 +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_MUL]] +; DEFAULT-NEXT: store i32 1, ptr [[GEP]], align 4 +; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @iv_trunc( +; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; PRED-NEXT: entry: +; PRED-NEXT: [[MUL_X:%.*]] = add i32 [[X]], 1 +; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; PRED: vector.scevcheck: +; PRED-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] +; PRED-NEXT: [[TMP2:%.*]] = icmp slt i32 [[MUL_X]], 0 +; PRED-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[MUL_X]] +; PRED-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 +; PRED-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) +; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 +; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 +; PRED-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] +; PRED-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 +; PRED-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false +; PRED-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] +; PRED-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 +; PRED-NEXT: [[TMP10:%.*]] = icmp ne i32 [[MUL_X]], 0 +; PRED-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] +; PRED-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] +; PRED-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 1 +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 2 +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[TMP13:%.*]] = sub i64 [[TMP0]], 2 +; PRED-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP0]], 2 +; PRED-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP13]], i64 0 +; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 0, i64 [[TMP0]]) +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[MUL_X]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE2:%.*]] ] +; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <2 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ] +; PRED-NEXT: [[VEC_IND:%.*]] = phi <2 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE2]] ] +; PRED-NEXT: [[TMP16:%.*]] = mul <2 x i32> [[BROADCAST_SPLAT]], [[VEC_IND]] +; PRED-NEXT: [[TMP17:%.*]] = zext <2 x i32> [[TMP16]] to <2 x i64> +; PRED-NEXT: [[TMP18:%.*]] = extractelement <2 x i1> [[ACTIVE_LANE_MASK]], i32 0 +; PRED-NEXT: br i1 [[TMP18]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; PRED: pred.store.if: +; PRED-NEXT: [[TMP19:%.*]] = extractelement <2 x i64> [[TMP17]], i32 0 +; PRED-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP19]] +; PRED-NEXT: store i32 1, ptr [[TMP20]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] +; PRED: pred.store.continue: +; PRED-NEXT: [[TMP21:%.*]] = extractelement <2 x i1> [[ACTIVE_LANE_MASK]], i32 1 +; PRED-NEXT: br i1 [[TMP21]], label [[PRED_STORE_IF1:%.*]], label [[PRED_STORE_CONTINUE2]] +; PRED: pred.store.if1: +; PRED-NEXT: [[TMP22:%.*]] = extractelement <2 x i64> [[TMP17]], i32 1 +; PRED-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP22]] +; PRED-NEXT: store i32 1, ptr [[TMP23]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE2]] +; PRED: pred.store.continue2: +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 2 +; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <2 x i1> @llvm.get.active.lane.mask.v2i1.i64(i64 [[INDEX]], i64 [[TMP15]]) +; PRED-NEXT: [[TMP24:%.*]] = xor <2 x i1> [[ACTIVE_LANE_MASK_NEXT]], +; PRED-NEXT: [[VEC_IND_NEXT]] = add <2 x i32> [[VEC_IND]], +; PRED-NEXT: [[TMP25:%.*]] = extractelement <2 x i1> [[TMP24]], i32 0 +; PRED-NEXT: br i1 [[TMP25]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; PRED-NEXT: br label [[FOR_BODY:%.*]] +; PRED: for.body: +; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[FOR_BODY]] ] +; PRED-NEXT: [[TRUNC_IV:%.*]] = trunc i64 [[IV]] to i32 +; PRED-NEXT: [[ADD_I:%.*]] = mul i32 [[MUL_X]], [[TRUNC_IV]] +; PRED-NEXT: [[IV_MUL:%.*]] = zext i32 [[ADD_I]] to i64 +; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[IV_MUL]] +; PRED-NEXT: store i32 1, ptr [[GEP]], align 4 +; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[FOR_BODY]], !llvm.loop [[LOOP5:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + %mul.x = add i32 %x, 1 + br label %for.body + +for.body: ; preds = %for.body, %entry + %iv = phi i64 [ 0, %entry ], [ %iv.next, %for.body ] + %trunc.iv = trunc i64 %iv to i32 + %add.i = mul i32 %mul.x, %trunc.iv + %iv.mul = zext i32 %add.i to i64 + %gep = getelementptr i32, ptr %dst, i64 %iv.mul + store i32 1, ptr %gep, align 4 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, %N + br i1 %ec, label %exit, label %for.body + +exit: + ret void +} + +define void @trunc_ivs_and_store(i32 %x, ptr %dst, i64 %N) #0 { +; DEFAULT-LABEL: define void @trunc_ivs_and_store( +; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[MUL:%.*]] = mul i32 [[X]], [[X]] +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; DEFAULT: vector.scevcheck: +; DEFAULT-NEXT: [[TMP1:%.*]] = mul i32 [[X]], [[X]] +; DEFAULT-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP1]] +; DEFAULT-NEXT: [[TMP3:%.*]] = icmp slt i32 [[MUL]], 0 +; DEFAULT-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 [[MUL]] +; DEFAULT-NEXT: [[TMP5:%.*]] = trunc i64 [[N]] to i32 +; DEFAULT-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP4]], i32 [[TMP5]]) +; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0 +; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1 +; DEFAULT-NEXT: [[TMP6:%.*]] = sub i32 0, [[MUL_RESULT]] +; DEFAULT-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], 0 +; DEFAULT-NEXT: [[TMP8:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 false +; DEFAULT-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]] +; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[N]], 4294967295 +; DEFAULT-NEXT: [[TMP11:%.*]] = icmp ne i32 [[MUL]], 0 +; DEFAULT-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]] +; DEFAULT-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]] +; DEFAULT-NEXT: br i1 [[TMP13]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 +; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[OFFSET_IDX]], 0 +; DEFAULT-NEXT: [[TMP15:%.*]] = add i32 [[OFFSET_IDX]], 1 +; DEFAULT-NEXT: [[TMP16:%.*]] = trunc i64 [[INDEX]] to i32 +; DEFAULT-NEXT: [[TMP17:%.*]] = add i32 [[TMP16]], 0 +; DEFAULT-NEXT: [[TMP18:%.*]] = add i32 [[TMP16]], 1 +; DEFAULT-NEXT: [[TMP19:%.*]] = mul i32 [[MUL]], [[TMP17]] +; DEFAULT-NEXT: [[TMP20:%.*]] = mul i32 [[MUL]], [[TMP18]] +; DEFAULT-NEXT: [[TMP21:%.*]] = zext i32 [[TMP19]] to i64 +; DEFAULT-NEXT: [[TMP22:%.*]] = zext i32 [[TMP20]] to i64 +; DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP21]] +; DEFAULT-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP22]] +; DEFAULT-NEXT: store i32 [[TMP14]], ptr [[TMP23]], align 4 +; DEFAULT-NEXT: store i32 [[TMP15]], ptr [[TMP24]], align 4 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; DEFAULT-NEXT: [[TMP25:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP25]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP7:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV_1_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 +; DEFAULT-NEXT: [[IV_1_MUL:%.*]] = mul i32 [[MUL]], [[IV_1_TRUNC]] +; DEFAULT-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 +; DEFAULT-NEXT: [[MUL_EXT:%.*]] = zext i32 [[IV_1_MUL]] to i64 +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[MUL_EXT]] +; DEFAULT-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 +; DEFAULT-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 +; DEFAULT-NEXT: [[EXITCOND_3_NOT:%.*]] = icmp eq i64 [[IV_1]], [[N]] +; DEFAULT-NEXT: br i1 [[EXITCOND_3_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP8:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @trunc_ivs_and_store( +; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; PRED-NEXT: entry: +; PRED-NEXT: [[MUL:%.*]] = mul i32 [[X]], [[X]] +; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; PRED: vector.scevcheck: +; PRED-NEXT: [[TMP1:%.*]] = mul i32 [[X]], [[X]] +; PRED-NEXT: [[TMP2:%.*]] = sub i32 0, [[TMP1]] +; PRED-NEXT: [[TMP3:%.*]] = icmp slt i32 [[MUL]], 0 +; PRED-NEXT: [[TMP4:%.*]] = select i1 [[TMP3]], i32 [[TMP2]], i32 [[MUL]] +; PRED-NEXT: [[TMP5:%.*]] = trunc i64 [[N]] to i32 +; PRED-NEXT: [[MUL1:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP4]], i32 [[TMP5]]) +; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL1]], 0 +; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL1]], 1 +; PRED-NEXT: [[TMP6:%.*]] = sub i32 0, [[MUL_RESULT]] +; PRED-NEXT: [[TMP7:%.*]] = icmp ugt i32 [[TMP6]], 0 +; PRED-NEXT: [[TMP8:%.*]] = select i1 [[TMP3]], i1 [[TMP7]], i1 false +; PRED-NEXT: [[TMP9:%.*]] = or i1 [[TMP8]], [[MUL_OVERFLOW]] +; PRED-NEXT: [[TMP10:%.*]] = icmp ugt i64 [[N]], 4294967295 +; PRED-NEXT: [[TMP11:%.*]] = icmp ne i32 [[MUL]], 0 +; PRED-NEXT: [[TMP12:%.*]] = and i1 [[TMP10]], [[TMP11]] +; PRED-NEXT: [[TMP13:%.*]] = or i1 [[TMP9]], [[TMP12]] +; PRED-NEXT: br i1 [[TMP13]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 3 +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4 +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 +; PRED-NEXT: [[TMP14:%.*]] = sub i64 [[TMP0]], 4 +; PRED-NEXT: [[TMP15:%.*]] = icmp ugt i64 [[TMP0]], 4 +; PRED-NEXT: [[TMP16:%.*]] = select i1 [[TMP15]], i64 [[TMP14]], i64 0 +; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 [[TMP0]]) +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[MUL]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE8:%.*]] ] +; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ] +; PRED-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE8]] ] +; PRED-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 +; PRED-NEXT: [[TMP17:%.*]] = mul <4 x i32> [[BROADCAST_SPLAT]], [[VEC_IND]] +; PRED-NEXT: [[TMP18:%.*]] = zext <4 x i32> [[TMP17]] to <4 x i64> +; PRED-NEXT: [[TMP19:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 0 +; PRED-NEXT: br i1 [[TMP19]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; PRED: pred.store.if: +; PRED-NEXT: [[TMP20:%.*]] = extractelement <4 x i64> [[TMP18]], i32 0 +; PRED-NEXT: [[TMP21:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP20]] +; PRED-NEXT: [[TMP22:%.*]] = add i32 [[OFFSET_IDX]], 0 +; PRED-NEXT: store i32 [[TMP22]], ptr [[TMP21]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] +; PRED: pred.store.continue: +; PRED-NEXT: [[TMP23:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 1 +; PRED-NEXT: br i1 [[TMP23]], label [[PRED_STORE_IF3:%.*]], label [[PRED_STORE_CONTINUE4:%.*]] +; PRED: pred.store.if3: +; PRED-NEXT: [[TMP24:%.*]] = extractelement <4 x i64> [[TMP18]], i32 1 +; PRED-NEXT: [[TMP25:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP24]] +; PRED-NEXT: [[TMP26:%.*]] = add i32 [[OFFSET_IDX]], 1 +; PRED-NEXT: store i32 [[TMP26]], ptr [[TMP25]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE4]] +; PRED: pred.store.continue4: +; PRED-NEXT: [[TMP27:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 2 +; PRED-NEXT: br i1 [[TMP27]], label [[PRED_STORE_IF5:%.*]], label [[PRED_STORE_CONTINUE6:%.*]] +; PRED: pred.store.if5: +; PRED-NEXT: [[TMP28:%.*]] = extractelement <4 x i64> [[TMP18]], i32 2 +; PRED-NEXT: [[TMP29:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP28]] +; PRED-NEXT: [[TMP30:%.*]] = add i32 [[OFFSET_IDX]], 2 +; PRED-NEXT: store i32 [[TMP30]], ptr [[TMP29]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE6]] +; PRED: pred.store.continue6: +; PRED-NEXT: [[TMP31:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 3 +; PRED-NEXT: br i1 [[TMP31]], label [[PRED_STORE_IF7:%.*]], label [[PRED_STORE_CONTINUE8]] +; PRED: pred.store.if7: +; PRED-NEXT: [[TMP32:%.*]] = extractelement <4 x i64> [[TMP18]], i32 3 +; PRED-NEXT: [[TMP33:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP32]] +; PRED-NEXT: [[TMP34:%.*]] = add i32 [[OFFSET_IDX]], 3 +; PRED-NEXT: store i32 [[TMP34]], ptr [[TMP33]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE8]] +; PRED: pred.store.continue8: +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 +; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[INDEX]], i64 [[TMP16]]) +; PRED-NEXT: [[TMP35:%.*]] = xor <4 x i1> [[ACTIVE_LANE_MASK_NEXT]], +; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], +; PRED-NEXT: [[TMP36:%.*]] = extractelement <4 x i1> [[TMP35]], i32 0 +; PRED-NEXT: br i1 [[TMP36]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; PRED-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[IV_1_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 +; PRED-NEXT: [[IV_1_MUL:%.*]] = mul i32 [[MUL]], [[IV_1_TRUNC]] +; PRED-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 +; PRED-NEXT: [[MUL_EXT:%.*]] = zext i32 [[IV_1_MUL]] to i64 +; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[MUL_EXT]] +; PRED-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 +; PRED-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 +; PRED-NEXT: [[EXITCOND_3_NOT:%.*]] = icmp eq i64 [[IV_1]], [[N]] +; PRED-NEXT: br i1 [[EXITCOND_3_NOT]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + %mul = mul i32 %x, %x + br label %loop + +loop: + %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ] + %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ] + %iv.1.trunc = trunc i64 %iv.1 to i32 + %iv.1.mul = mul i32 %mul, %iv.1.trunc + %iv.2.next = add i32 %iv.2, 1 + %mul.ext = zext i32 %iv.1.mul to i64 + %gep = getelementptr i32, ptr %dst, i64 %mul.ext + store i32 %iv.2, ptr %gep, align 4 + %iv.1.next = add i64 %iv.1, 1 + %exitcond.3.not = icmp eq i64 %iv.1, %N + br i1 %exitcond.3.not, label %exit, label %loop + +exit: + ret void +} + +define void @ivs_trunc_and_ext(i32 %x, ptr %dst, i64 %N) #0 { +; DEFAULT-LABEL: define void @ivs_trunc_and_ext( +; DEFAULT-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[ADD:%.*]] = add i32 [[X]], 1 +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], 2 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; DEFAULT: vector.scevcheck: +; DEFAULT-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] +; DEFAULT-NEXT: [[TMP2:%.*]] = icmp slt i32 [[ADD]], 0 +; DEFAULT-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[ADD]] +; DEFAULT-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 +; DEFAULT-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) +; DEFAULT-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 +; DEFAULT-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 +; DEFAULT-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] +; DEFAULT-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 +; DEFAULT-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false +; DEFAULT-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] +; DEFAULT-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 +; DEFAULT-NEXT: [[TMP10:%.*]] = icmp ne i32 [[ADD]], 0 +; DEFAULT-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] +; DEFAULT-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] +; DEFAULT-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 2 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 +; DEFAULT-NEXT: [[TMP13:%.*]] = add i32 [[OFFSET_IDX]], 0 +; DEFAULT-NEXT: [[TMP14:%.*]] = add i32 [[OFFSET_IDX]], 1 +; DEFAULT-NEXT: [[TMP15:%.*]] = trunc i64 [[INDEX]] to i32 +; DEFAULT-NEXT: [[TMP16:%.*]] = add i32 [[TMP15]], 0 +; DEFAULT-NEXT: [[TMP17:%.*]] = add i32 [[TMP15]], 1 +; DEFAULT-NEXT: [[TMP18:%.*]] = mul i32 [[ADD]], [[TMP16]] +; DEFAULT-NEXT: [[TMP19:%.*]] = mul i32 [[ADD]], [[TMP17]] +; DEFAULT-NEXT: [[TMP20:%.*]] = zext i32 [[TMP18]] to i64 +; DEFAULT-NEXT: [[TMP21:%.*]] = zext i32 [[TMP19]] to i64 +; DEFAULT-NEXT: [[TMP22:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP20]] +; DEFAULT-NEXT: [[TMP23:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP21]] +; DEFAULT-NEXT: store i32 [[TMP13]], ptr [[TMP22]], align 4 +; DEFAULT-NEXT: store i32 [[TMP14]], ptr [[TMP23]], align 4 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; DEFAULT-NEXT: [[TMP24:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP24]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 +; DEFAULT-NEXT: [[IV_MUL:%.*]] = mul i32 [[ADD]], [[IV_TRUNC]] +; DEFAULT-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 +; DEFAULT-NEXT: [[EXT:%.*]] = zext i32 [[IV_MUL]] to i64 +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[EXT]] +; DEFAULT-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 +; DEFAULT-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_1]], [[N]] +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP10:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @ivs_trunc_and_ext( +; PRED-SAME: i32 [[X:%.*]], ptr [[DST:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; PRED-NEXT: entry: +; PRED-NEXT: [[ADD:%.*]] = add i32 [[X]], 1 +; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; PRED: vector.scevcheck: +; PRED-NEXT: [[TMP1:%.*]] = sub i32 -1, [[X]] +; PRED-NEXT: [[TMP2:%.*]] = icmp slt i32 [[ADD]], 0 +; PRED-NEXT: [[TMP3:%.*]] = select i1 [[TMP2]], i32 [[TMP1]], i32 [[ADD]] +; PRED-NEXT: [[TMP4:%.*]] = trunc i64 [[N]] to i32 +; PRED-NEXT: [[MUL:%.*]] = call { i32, i1 } @llvm.umul.with.overflow.i32(i32 [[TMP3]], i32 [[TMP4]]) +; PRED-NEXT: [[MUL_RESULT:%.*]] = extractvalue { i32, i1 } [[MUL]], 0 +; PRED-NEXT: [[MUL_OVERFLOW:%.*]] = extractvalue { i32, i1 } [[MUL]], 1 +; PRED-NEXT: [[TMP5:%.*]] = sub i32 0, [[MUL_RESULT]] +; PRED-NEXT: [[TMP6:%.*]] = icmp ugt i32 [[TMP5]], 0 +; PRED-NEXT: [[TMP7:%.*]] = select i1 [[TMP2]], i1 [[TMP6]], i1 false +; PRED-NEXT: [[TMP8:%.*]] = or i1 [[TMP7]], [[MUL_OVERFLOW]] +; PRED-NEXT: [[TMP9:%.*]] = icmp ugt i64 [[N]], 4294967295 +; PRED-NEXT: [[TMP10:%.*]] = icmp ne i32 [[ADD]], 0 +; PRED-NEXT: [[TMP11:%.*]] = and i1 [[TMP9]], [[TMP10]] +; PRED-NEXT: [[TMP12:%.*]] = or i1 [[TMP8]], [[TMP11]] +; PRED-NEXT: br i1 [[TMP12]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], 3 +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], 4 +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 +; PRED-NEXT: [[TMP13:%.*]] = sub i64 [[TMP0]], 4 +; PRED-NEXT: [[TMP14:%.*]] = icmp ugt i64 [[TMP0]], 4 +; PRED-NEXT: [[TMP15:%.*]] = select i1 [[TMP14]], i64 [[TMP13]], i64 0 +; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 0, i64 [[TMP0]]) +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[ADD]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[PRED_STORE_CONTINUE7:%.*]] ] +; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi <4 x i1> [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[PRED_STORE_CONTINUE7]] ] +; PRED-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[PRED_STORE_CONTINUE7]] ] +; PRED-NEXT: [[OFFSET_IDX:%.*]] = trunc i64 [[INDEX]] to i32 +; PRED-NEXT: [[TMP16:%.*]] = mul <4 x i32> [[BROADCAST_SPLAT]], [[VEC_IND]] +; PRED-NEXT: [[TMP17:%.*]] = zext <4 x i32> [[TMP16]] to <4 x i64> +; PRED-NEXT: [[TMP18:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 0 +; PRED-NEXT: br i1 [[TMP18]], label [[PRED_STORE_IF:%.*]], label [[PRED_STORE_CONTINUE:%.*]] +; PRED: pred.store.if: +; PRED-NEXT: [[TMP19:%.*]] = extractelement <4 x i64> [[TMP17]], i32 0 +; PRED-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP19]] +; PRED-NEXT: [[TMP21:%.*]] = add i32 [[OFFSET_IDX]], 0 +; PRED-NEXT: store i32 [[TMP21]], ptr [[TMP20]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE]] +; PRED: pred.store.continue: +; PRED-NEXT: [[TMP22:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 1 +; PRED-NEXT: br i1 [[TMP22]], label [[PRED_STORE_IF2:%.*]], label [[PRED_STORE_CONTINUE3:%.*]] +; PRED: pred.store.if2: +; PRED-NEXT: [[TMP23:%.*]] = extractelement <4 x i64> [[TMP17]], i32 1 +; PRED-NEXT: [[TMP24:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP23]] +; PRED-NEXT: [[TMP25:%.*]] = add i32 [[OFFSET_IDX]], 1 +; PRED-NEXT: store i32 [[TMP25]], ptr [[TMP24]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE3]] +; PRED: pred.store.continue3: +; PRED-NEXT: [[TMP26:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 2 +; PRED-NEXT: br i1 [[TMP26]], label [[PRED_STORE_IF4:%.*]], label [[PRED_STORE_CONTINUE5:%.*]] +; PRED: pred.store.if4: +; PRED-NEXT: [[TMP27:%.*]] = extractelement <4 x i64> [[TMP17]], i32 2 +; PRED-NEXT: [[TMP28:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP27]] +; PRED-NEXT: [[TMP29:%.*]] = add i32 [[OFFSET_IDX]], 2 +; PRED-NEXT: store i32 [[TMP29]], ptr [[TMP28]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE5]] +; PRED: pred.store.continue5: +; PRED-NEXT: [[TMP30:%.*]] = extractelement <4 x i1> [[ACTIVE_LANE_MASK]], i32 3 +; PRED-NEXT: br i1 [[TMP30]], label [[PRED_STORE_IF6:%.*]], label [[PRED_STORE_CONTINUE7]] +; PRED: pred.store.if6: +; PRED-NEXT: [[TMP31:%.*]] = extractelement <4 x i64> [[TMP17]], i32 3 +; PRED-NEXT: [[TMP32:%.*]] = getelementptr i32, ptr [[DST]], i64 [[TMP31]] +; PRED-NEXT: [[TMP33:%.*]] = add i32 [[OFFSET_IDX]], 3 +; PRED-NEXT: store i32 [[TMP33]], ptr [[TMP32]], align 4 +; PRED-NEXT: br label [[PRED_STORE_CONTINUE7]] +; PRED: pred.store.continue7: +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], 4 +; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call <4 x i1> @llvm.get.active.lane.mask.v4i1.i64(i64 [[INDEX]], i64 [[TMP15]]) +; PRED-NEXT: [[TMP34:%.*]] = xor <4 x i1> [[ACTIVE_LANE_MASK_NEXT]], +; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], +; PRED-NEXT: [[TMP35:%.*]] = extractelement <4 x i1> [[TMP34]], i32 0 +; PRED-NEXT: br i1 [[TMP35]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; PRED-NEXT: [[BC_RESUME_VAL1:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[IV_1:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL1]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[IV_TRUNC:%.*]] = trunc i64 [[IV_1]] to i32 +; PRED-NEXT: [[IV_MUL:%.*]] = mul i32 [[ADD]], [[IV_TRUNC]] +; PRED-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 +; PRED-NEXT: [[EXT:%.*]] = zext i32 [[IV_MUL]] to i64 +; PRED-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[DST]], i64 [[EXT]] +; PRED-NEXT: store i32 [[IV_2]], ptr [[GEP]], align 4 +; PRED-NEXT: [[IV_1_NEXT]] = add i64 [[IV_1]], 1 +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_1]], [[N]] +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP9:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + %add = add i32 %x, 1 + br label %loop + +loop: + %iv.1 = phi i64 [ 0, %entry ], [ %iv.1.next, %loop ] + %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ] + %iv.trunc = trunc i64 %iv.1 to i32 + %iv.mul = mul i32 %add, %iv.trunc + %iv.2.next = add i32 %iv.2, 1 + %ext = zext i32 %iv.mul to i64 + %gep = getelementptr i32, ptr %dst, i64 %ext + store i32 %iv.2, ptr %gep, align 4 + %iv.1.next = add i64 %iv.1, 1 + %ec = icmp eq i64 %iv.1, %N + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +define void @exit_cond_zext_iv(ptr %dst, i64 %N) { +; DEFAULT-LABEL: define void @exit_cond_zext_iv( +; DEFAULT-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX1]], 2 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; DEFAULT: vector.scevcheck: +; DEFAULT-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1 +; DEFAULT-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 +; DEFAULT-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32 +; DEFAULT-NEXT: [[TMP3:%.*]] = add i32 1, [[TMP2]] +; DEFAULT-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 1 +; DEFAULT-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 +; DEFAULT-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]] +; DEFAULT-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX1]], 2 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX1]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1 +; DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP7]], i32 2 +; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[TMP8]], i32 2 +; DEFAULT-NEXT: store i32 0, ptr [[TMP9]], align 8 +; DEFAULT-NEXT: store i32 0, ptr [[TMP10]], align 8 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; DEFAULT-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP11:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX1]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV_CONV:%.*]] = phi i64 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_EXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[IV_CONV]], i32 2 +; DEFAULT-NEXT: store i32 0, ptr [[GEP]], align 8 +; DEFAULT-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 +; DEFAULT-NEXT: [[IV_EXT]] = zext i32 [[IV_1_NEXT]] to i64 +; DEFAULT-NEXT: [[C:%.*]] = icmp ult i64 [[IV_EXT]], [[N]] +; DEFAULT-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT]], !llvm.loop [[LOOP12:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @exit_cond_zext_iv( +; PRED-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[IV_1:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[IV_CONV:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[IV_EXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[GEP:%.*]] = getelementptr { [100 x i32], i32, i32 }, ptr [[DST]], i64 [[IV_CONV]], i32 2 +; PRED-NEXT: store i32 0, ptr [[GEP]], align 8 +; PRED-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 +; PRED-NEXT: [[IV_EXT]] = zext i32 [[IV_1_NEXT]] to i64 +; PRED-NEXT: [[C:%.*]] = icmp ult i64 [[IV_EXT]], [[N]] +; PRED-NEXT: br i1 [[C]], label [[LOOP]], label [[EXIT:%.*]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ] + %iv.conv = phi i64 [ 0, %entry ], [ %iv.ext, %loop ] + %gep = getelementptr {[100 x i32], i32, i32}, ptr %dst, i64 %iv.conv, i32 2 + store i32 0, ptr %gep, align 8 + %iv.1.next = add i32 %iv.1, 1 + %iv.ext = zext i32 %iv.1.next to i64 + %c = icmp ult i64 %iv.ext, %N + br i1 %c, label %loop, label %exit + +exit: + ret void +} + +attributes #0 = { "target-features"="+sve" } + +;. +; DEFAULT: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; DEFAULT: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; DEFAULT: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; DEFAULT: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]]} +; DEFAULT: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]]} +; DEFAULT: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]]} +; DEFAULT: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]} +; DEFAULT: [[LOOP11]] = distinct !{[[LOOP11]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP12]] = distinct !{[[LOOP12]], [[META1]]} +;. +; PRED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; PRED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; PRED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; PRED: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]]} +; PRED: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; PRED: [[LOOP5]] = distinct !{[[LOOP5]], [[META1]]} +; PRED: [[LOOP6]] = distinct !{[[LOOP6]], [[META1]], [[META2]]} +; PRED: [[LOOP7]] = distinct !{[[LOOP7]], [[META1]]} +; PRED: [[LOOP8]] = distinct !{[[LOOP8]], [[META1]], [[META2]]} +; PRED: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]]} +;. diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll index 931ab4f77618..03f8243a35af 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll @@ -285,6 +285,264 @@ loop: exit: ret void } + +define i64 @test_ptr_ivs_and_widened_ivs(ptr %src, i32 %N) { +; DEFAULT-LABEL: define i64 @test_ptr_ivs_and_widened_ivs( +; DEFAULT-SAME: ptr [[SRC:%.*]], i32 [[N:%.*]]) { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1 +; DEFAULT-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; DEFAULT-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 +; DEFAULT-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP3]] +; DEFAULT-NEXT: [[IND_END1:%.*]] = trunc i64 [[N_VEC]] to i32 +; DEFAULT-NEXT: [[IND_END3:%.*]] = trunc i64 [[N_VEC]] to i32 +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ , [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], +; DEFAULT-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 +; DEFAULT-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0 +; DEFAULT-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 16 +; DEFAULT-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP4]] +; DEFAULT-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP5]] +; DEFAULT-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0 +; DEFAULT-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 4 +; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 +; DEFAULT-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 +; DEFAULT-NEXT: [[TMP8:%.*]] = xor <4 x i32> [[WIDE_LOAD]], +; DEFAULT-NEXT: [[TMP9:%.*]] = xor <4 x i32> [[WIDE_LOAD7]], +; DEFAULT-NEXT: [[TMP10:%.*]] = zext <4 x i32> [[TMP8]] to <4 x i64> +; DEFAULT-NEXT: [[TMP11:%.*]] = zext <4 x i32> [[TMP9]] to <4 x i64> +; DEFAULT-NEXT: [[TMP12:%.*]] = zext <4 x i32> [[VEC_IND]] to <4 x i64> +; DEFAULT-NEXT: [[TMP13:%.*]] = zext <4 x i32> [[STEP_ADD]] to <4 x i64> +; DEFAULT-NEXT: [[TMP14:%.*]] = shl <4 x i64> [[TMP10]], [[TMP12]] +; DEFAULT-NEXT: [[TMP15]] = shl <4 x i64> [[TMP11]], [[TMP13]] +; DEFAULT-NEXT: [[TMP16:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[TMP14]], <4 x i32> +; DEFAULT-NEXT: [[TMP17:%.*]] = shufflevector <4 x i64> [[TMP14]], <4 x i64> [[TMP15]], <4 x i32> +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; DEFAULT-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], +; DEFAULT-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP6:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] +; DEFAULT-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP15]], i32 3 +; DEFAULT-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP15]], i32 2 +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SRC]], [[ENTRY]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END1]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[SHL:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL4]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4 +; DEFAULT-NEXT: [[NOT:%.*]] = xor i32 [[L]], 1 +; DEFAULT-NEXT: [[NOT_EXT:%.*]] = zext i32 [[NOT]] to i64 +; DEFAULT-NEXT: [[IV_EXT:%.*]] = zext i32 [[IV_1]] to i64 +; DEFAULT-NEXT: [[SHL]] = shl i64 [[NOT_EXT]], [[IV_EXT]] +; DEFAULT-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 4 +; DEFAULT-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 +; DEFAULT-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_2_NEXT]], [[N]] +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP7:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: [[P_LCSSA:%.*]] = phi i64 [ [[SCALAR_RECUR]], [[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: ret i64 [[P_LCSSA]] +; +; PRED-LABEL: define i64 @test_ptr_ivs_and_widened_ivs( +; PRED-SAME: ptr [[SRC:%.*]], i32 [[N:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: [[TMP0:%.*]] = add i32 [[N]], -1 +; PRED-NEXT: [[TMP1:%.*]] = zext i32 [[TMP0]] to i64 +; PRED-NEXT: [[TMP2:%.*]] = add nuw nsw i64 [[TMP1]], 1 +; PRED-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP2]], 8 +; PRED-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP2]], 8 +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP2]], [[N_MOD_VF]] +; PRED-NEXT: [[TMP3:%.*]] = mul i64 [[N_VEC]], 4 +; PRED-NEXT: [[IND_END:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP3]] +; PRED-NEXT: [[IND_END1:%.*]] = trunc i64 [[N_VEC]] to i32 +; PRED-NEXT: [[IND_END3:%.*]] = trunc i64 [[N_VEC]] to i32 +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[VECTOR_RECUR:%.*]] = phi <4 x i64> [ , [[VECTOR_PH]] ], [ [[TMP15:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ , [[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[STEP_ADD:%.*]] = add <4 x i32> [[VEC_IND]], +; PRED-NEXT: [[OFFSET_IDX:%.*]] = mul i64 [[INDEX]], 4 +; PRED-NEXT: [[TMP4:%.*]] = add i64 [[OFFSET_IDX]], 0 +; PRED-NEXT: [[TMP5:%.*]] = add i64 [[OFFSET_IDX]], 16 +; PRED-NEXT: [[NEXT_GEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP4]] +; PRED-NEXT: [[NEXT_GEP6:%.*]] = getelementptr i8, ptr [[SRC]], i64 [[TMP5]] +; PRED-NEXT: [[TMP6:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 0 +; PRED-NEXT: [[TMP7:%.*]] = getelementptr i32, ptr [[NEXT_GEP]], i32 4 +; PRED-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP6]], align 4 +; PRED-NEXT: [[WIDE_LOAD7:%.*]] = load <4 x i32>, ptr [[TMP7]], align 4 +; PRED-NEXT: [[TMP8:%.*]] = xor <4 x i32> [[WIDE_LOAD]], +; PRED-NEXT: [[TMP9:%.*]] = xor <4 x i32> [[WIDE_LOAD7]], +; PRED-NEXT: [[TMP10:%.*]] = zext <4 x i32> [[TMP8]] to <4 x i64> +; PRED-NEXT: [[TMP11:%.*]] = zext <4 x i32> [[TMP9]] to <4 x i64> +; PRED-NEXT: [[TMP12:%.*]] = zext <4 x i32> [[VEC_IND]] to <4 x i64> +; PRED-NEXT: [[TMP13:%.*]] = zext <4 x i32> [[STEP_ADD]] to <4 x i64> +; PRED-NEXT: [[TMP14:%.*]] = shl <4 x i64> [[TMP10]], [[TMP12]] +; PRED-NEXT: [[TMP15]] = shl <4 x i64> [[TMP11]], [[TMP13]] +; PRED-NEXT: [[TMP16:%.*]] = shufflevector <4 x i64> [[VECTOR_RECUR]], <4 x i64> [[TMP14]], <4 x i32> +; PRED-NEXT: [[TMP17:%.*]] = shufflevector <4 x i64> [[TMP14]], <4 x i64> [[TMP15]], <4 x i32> +; PRED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 +; PRED-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[STEP_ADD]], +; PRED-NEXT: [[TMP18:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; PRED-NEXT: br i1 [[TMP18]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP2]], [[N_VEC]] +; PRED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement <4 x i64> [[TMP15]], i32 3 +; PRED-NEXT: [[VECTOR_RECUR_EXTRACT_FOR_PHI:%.*]] = extractelement <4 x i64> [[TMP15]], i32 2 +; PRED-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i64 [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi ptr [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ [[SRC]], [[ENTRY]] ] +; PRED-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END1]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] +; PRED-NEXT: [[BC_RESUME_VAL4:%.*]] = phi i32 [ [[IND_END3]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[SCALAR_RECUR:%.*]] = phi i64 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[SHL:%.*]], [[LOOP]] ] +; PRED-NEXT: [[PTR_IV:%.*]] = phi ptr [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[PTR_IV_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[IV_2:%.*]] = phi i32 [ [[BC_RESUME_VAL4]], [[SCALAR_PH]] ], [ [[IV_2_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[L:%.*]] = load i32, ptr [[PTR_IV]], align 4 +; PRED-NEXT: [[NOT:%.*]] = xor i32 [[L]], 1 +; PRED-NEXT: [[NOT_EXT:%.*]] = zext i32 [[NOT]] to i64 +; PRED-NEXT: [[IV_EXT:%.*]] = zext i32 [[IV_1]] to i64 +; PRED-NEXT: [[SHL]] = shl i64 [[NOT_EXT]], [[IV_EXT]] +; PRED-NEXT: [[PTR_IV_NEXT]] = getelementptr i8, ptr [[PTR_IV]], i64 4 +; PRED-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1 +; PRED-NEXT: [[IV_2_NEXT]] = add i32 [[IV_2]], 1 +; PRED-NEXT: [[EC:%.*]] = icmp eq i32 [[IV_2_NEXT]], [[N]] +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; PRED: exit: +; PRED-NEXT: [[P_LCSSA:%.*]] = phi i64 [ [[SCALAR_RECUR]], [[LOOP]] ], [ [[VECTOR_RECUR_EXTRACT_FOR_PHI]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: ret i64 [[P_LCSSA]] +; +entry: + br label %loop + +loop: + %p = phi i64 [ 0, %entry ], [ %shl, %loop ] + %ptr.iv = phi ptr [ %src, %entry ], [ %ptr.iv.next, %loop ] + %iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop ] + %iv.2 = phi i32 [ 0, %entry ], [ %iv.2.next, %loop ] + %l = load i32, ptr %ptr.iv, align 4 + %not = xor i32 %l, 1 + %not.ext = zext i32 %not to i64 + %iv.ext = zext i32 %iv.1 to i64 + %shl = shl i64 %not.ext , %iv.ext + %ptr.iv.next = getelementptr i8, ptr %ptr.iv, i64 4 + %iv.1.next = add i32 %iv.1, 1 + %iv.2.next = add i32 %iv.2, 1 + %ec = icmp eq i32 %iv.2.next, %N + br i1 %ec, label %exit, label %loop + +exit: + ret i64 %p +} + +define void @zext_iv_increment(ptr %dst, i64 %N) { +; DEFAULT-LABEL: define void @zext_iv_increment( +; DEFAULT-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[UMAX1:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[UMAX1]], 2 +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_SCEVCHECK:%.*]] +; DEFAULT: vector.scevcheck: +; DEFAULT-NEXT: [[UMAX:%.*]] = call i64 @llvm.umax.i64(i64 [[N]], i64 1) +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[UMAX]], -1 +; DEFAULT-NEXT: [[TMP1:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 +; DEFAULT-NEXT: [[TMP2:%.*]] = trunc i64 [[TMP0]] to i32 +; DEFAULT-NEXT: [[TMP3:%.*]] = add i32 1, [[TMP2]] +; DEFAULT-NEXT: [[TMP4:%.*]] = icmp ult i32 [[TMP3]], 1 +; DEFAULT-NEXT: [[TMP5:%.*]] = icmp ugt i64 [[TMP0]], 4294967295 +; DEFAULT-NEXT: [[TMP6:%.*]] = or i1 [[TMP4]], [[TMP5]] +; DEFAULT-NEXT: br i1 [[TMP6]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[UMAX1]], 2 +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[UMAX1]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[IND_END:%.*]] = trunc i64 [[N_VEC]] to i32 +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 1 +; DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[TMP7]], i32 2 +; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[TMP8]], i32 2 +; DEFAULT-NEXT: store i32 0, ptr [[TMP9]], align 8 +; DEFAULT-NEXT: store i32 0, ptr [[TMP10]], align 8 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 2 +; DEFAULT-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP8:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[UMAX1]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[FOR_COND_CLEANUP173_LOOPEXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL2:%.*]] = phi i32 [ [[IND_END]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL3:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ], [ 0, [[VECTOR_SCEVCHECK]] ] +; DEFAULT-NEXT: br label [[FOR_BODY174:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[I167_0800:%.*]] = phi i32 [ [[BC_RESUME_VAL2]], [[SCALAR_PH]] ], [ [[INC179:%.*]], [[FOR_BODY174]] ] +; DEFAULT-NEXT: [[CONV169801:%.*]] = phi i64 [ [[BC_RESUME_VAL3]], [[SCALAR_PH]] ], [ [[CONV169:%.*]], [[FOR_BODY174]] ] +; DEFAULT-NEXT: [[PATCH_INDEX:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[CONV169801]], i32 2 +; DEFAULT-NEXT: store i32 0, ptr [[PATCH_INDEX]], align 8 +; DEFAULT-NEXT: [[INC179]] = add i32 [[I167_0800]], 1 +; DEFAULT-NEXT: [[CONV169]] = zext i32 [[INC179]] to i64 +; DEFAULT-NEXT: [[CMP172:%.*]] = icmp ult i64 [[CONV169]], [[N]] +; DEFAULT-NEXT: br i1 [[CMP172]], label [[FOR_BODY174]], label [[FOR_COND_CLEANUP173_LOOPEXIT]], !llvm.loop [[LOOP9:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @zext_iv_increment( +; PRED-SAME: ptr [[DST:%.*]], i64 [[N:%.*]]) { +; PRED-NEXT: entry: +; PRED-NEXT: br label [[FOR_BODY174:%.*]] +; PRED: loop: +; PRED-NEXT: [[I167_0800:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[INC179:%.*]], [[FOR_BODY174]] ] +; PRED-NEXT: [[CONV169801:%.*]] = phi i64 [ 0, [[ENTRY]] ], [ [[CONV169:%.*]], [[FOR_BODY174]] ] +; PRED-NEXT: [[PATCH_INDEX:%.*]] = getelementptr { i32, i32, i32 }, ptr [[DST]], i64 [[CONV169801]], i32 2 +; PRED-NEXT: store i32 0, ptr [[PATCH_INDEX]], align 8 +; PRED-NEXT: [[INC179]] = add i32 [[I167_0800]], 1 +; PRED-NEXT: [[CONV169]] = zext i32 [[INC179]] to i64 +; PRED-NEXT: [[CMP172:%.*]] = icmp ult i64 [[CONV169]], [[N]] +; PRED-NEXT: br i1 [[CMP172]], label [[FOR_BODY174]], label [[FOR_COND_CLEANUP173_LOOPEXIT:%.*]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop ] + %iv.wide = phi i64 [ 0, %entry ], [ %iv.next.ext, %loop ] + %patch_index = getelementptr { i32, i32, i32 }, ptr %dst, i64 %iv.wide, i32 2 + store i32 0, ptr %patch_index, align 8 + %iv.next = add i32 %iv, 1 + %iv.next.ext = zext i32 %iv.next to i64 + %ec = icmp ult i64 %iv.next.ext, %N + br i1 %ec, label %loop, label %exit + +exit: + ret void +} + ;. ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} ; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll new file mode 100644 index 000000000000..75250df79d17 --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll @@ -0,0 +1,482 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=DEFAULT %s +; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=PRED %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-macosx14.0.0" + +define i32 @chained_recurrences(i32 %x, i64 %y, ptr %src.1, i32 %z, ptr %src.2) #0 { +; DEFAULT-LABEL: define i32 @chained_recurrences( +; DEFAULT-SAME: i32 [[X:%.*]], i64 [[Y:%.*]], ptr [[SRC_1:%.*]], i32 [[Z:%.*]], ptr [[SRC_2:%.*]]) #[[ATTR0:[0-9]+]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[Y]], 1 +; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8 +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP4]] +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 8 +; DEFAULT-NEXT: [[TMP7:%.*]] = call i32 @llvm.vscale.i32() +; DEFAULT-NEXT: [[TMP8:%.*]] = mul i32 [[TMP7]], 4 +; DEFAULT-NEXT: [[TMP9:%.*]] = sub i32 [[TMP8]], 1 +; DEFAULT-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement poison, i32 0, i32 [[TMP9]] +; DEFAULT-NEXT: [[TMP10:%.*]] = call i32 @llvm.vscale.i32() +; DEFAULT-NEXT: [[TMP11:%.*]] = mul i32 [[TMP10]], 4 +; DEFAULT-NEXT: [[TMP12:%.*]] = sub i32 [[TMP11]], 1 +; DEFAULT-NEXT: [[VECTOR_RECUR_INIT1:%.*]] = insertelement poison, i32 0, i32 [[TMP12]] +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement poison, i32 [[X]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector [[BROADCAST_SPLATINSERT6]], poison, zeroinitializer +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT8:%.*]] = insertelement poison, i32 [[Z]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT9:%.*]] = shufflevector [[BROADCAST_SPLATINSERT8]], poison, zeroinitializer +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VECTOR_RECUR:%.*]] = phi [ [[VECTOR_RECUR_INIT]], [[VECTOR_PH]] ], [ [[BROADCAST_SPLAT5:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VECTOR_RECUR2:%.*]] = phi [ [[VECTOR_RECUR_INIT1]], [[VECTOR_PH]] ], [ [[TMP20:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VEC_PHI:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP57:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VEC_PHI3:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP58:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP13:%.*]] = add i64 [[Y]], 1 +; DEFAULT-NEXT: [[TMP14:%.*]] = add i64 [[Y]], 1 +; DEFAULT-NEXT: [[TMP15:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[TMP13]] +; DEFAULT-NEXT: [[TMP16:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[TMP14]] +; DEFAULT-NEXT: [[TMP17:%.*]] = load i32, ptr [[TMP15]], align 4 +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i32 [[TMP17]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; DEFAULT-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement poison, i32 [[TMP18]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT5]] = shufflevector [[BROADCAST_SPLATINSERT4]], poison, zeroinitializer +; DEFAULT-NEXT: [[TMP19:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR]], [[BROADCAST_SPLAT]], i32 -1) +; DEFAULT-NEXT: [[TMP20]] = call @llvm.experimental.vector.splice.nxv4i32( [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT5]], i32 -1) +; DEFAULT-NEXT: [[TMP21:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR2]], [[TMP19]], i32 -1) +; DEFAULT-NEXT: [[TMP22:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[TMP19]], [[TMP20]], i32 -1) +; DEFAULT-NEXT: [[TMP23:%.*]] = or [[TMP21]], [[BROADCAST_SPLAT7]] +; DEFAULT-NEXT: [[TMP24:%.*]] = or [[TMP22]], [[BROADCAST_SPLAT7]] +; DEFAULT-NEXT: [[TMP25:%.*]] = lshr [[BROADCAST_SPLAT7]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP26:%.*]] = lshr [[BROADCAST_SPLAT7]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP27:%.*]] = shl [[TMP23]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP28:%.*]] = shl [[TMP24]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP29:%.*]] = or [[TMP27]], shufflevector ( insertelement ( poison, i32 2, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP30:%.*]] = or [[TMP28]], shufflevector ( insertelement ( poison, i32 2, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP31:%.*]] = shl [[BROADCAST_SPLAT7]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP32:%.*]] = shl [[BROADCAST_SPLAT7]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP33:%.*]] = or [[TMP25]], [[TMP31]] +; DEFAULT-NEXT: [[TMP34:%.*]] = or [[TMP26]], [[TMP32]] +; DEFAULT-NEXT: [[TMP35:%.*]] = or [[TMP33]], [[TMP29]] +; DEFAULT-NEXT: [[TMP36:%.*]] = or [[TMP34]], [[TMP30]] +; DEFAULT-NEXT: [[TMP37:%.*]] = or [[TMP35]], [[BROADCAST_SPLAT7]] +; DEFAULT-NEXT: [[TMP38:%.*]] = or [[TMP36]], [[BROADCAST_SPLAT7]] +; DEFAULT-NEXT: [[TMP39:%.*]] = or [[BROADCAST_SPLAT9]], [[BROADCAST_SPLAT7]] +; DEFAULT-NEXT: [[TMP40:%.*]] = or [[BROADCAST_SPLAT9]], [[BROADCAST_SPLAT7]] +; DEFAULT-NEXT: [[TMP41:%.*]] = and [[TMP39]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP42:%.*]] = and [[TMP40]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP43:%.*]] = xor [[TMP41]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP44:%.*]] = xor [[TMP42]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP45:%.*]] = zext [[TMP43]] to +; DEFAULT-NEXT: [[TMP46:%.*]] = zext [[TMP44]] to +; DEFAULT-NEXT: [[TMP47:%.*]] = getelementptr i32, ptr [[SRC_2]], [[TMP45]] +; DEFAULT-NEXT: [[TMP48:%.*]] = getelementptr i32, ptr [[SRC_2]], [[TMP46]] +; DEFAULT-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP47]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison) +; DEFAULT-NEXT: [[WIDE_MASKED_GATHER10:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP48]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison) +; DEFAULT-NEXT: [[TMP49:%.*]] = lshr [[TMP37]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP50:%.*]] = lshr [[TMP38]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; DEFAULT-NEXT: [[TMP51:%.*]] = zext [[TMP49]] to +; DEFAULT-NEXT: [[TMP52:%.*]] = zext [[TMP50]] to +; DEFAULT-NEXT: [[TMP53:%.*]] = getelementptr i32, ptr [[SRC_2]], [[TMP51]] +; DEFAULT-NEXT: [[TMP54:%.*]] = getelementptr i32, ptr [[SRC_2]], [[TMP52]] +; DEFAULT-NEXT: [[WIDE_MASKED_GATHER11:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP53]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison) +; DEFAULT-NEXT: [[WIDE_MASKED_GATHER12:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP54]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison) +; DEFAULT-NEXT: [[TMP55:%.*]] = or [[WIDE_MASKED_GATHER]], [[VEC_PHI]] +; DEFAULT-NEXT: [[TMP56:%.*]] = or [[WIDE_MASKED_GATHER10]], [[VEC_PHI3]] +; DEFAULT-NEXT: [[TMP57]] = or [[TMP55]], [[WIDE_MASKED_GATHER11]] +; DEFAULT-NEXT: [[TMP58]] = or [[TMP56]], [[WIDE_MASKED_GATHER12]] +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP6]] +; DEFAULT-NEXT: [[TMP59:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP59]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[BIN_RDX:%.*]] = or [[TMP58]], [[TMP57]] +; DEFAULT-NEXT: [[TMP60:%.*]] = call i32 @llvm.vector.reduce.or.nxv4i32( [[BIN_RDX]]) +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: [[TMP61:%.*]] = call i32 @llvm.vscale.i32() +; DEFAULT-NEXT: [[TMP62:%.*]] = mul i32 [[TMP61]], 4 +; DEFAULT-NEXT: [[TMP63:%.*]] = sub i32 [[TMP62]], 1 +; DEFAULT-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[BROADCAST_SPLAT5]], i32 [[TMP63]] +; DEFAULT-NEXT: [[TMP64:%.*]] = call i32 @llvm.vscale.i32() +; DEFAULT-NEXT: [[TMP65:%.*]] = mul i32 [[TMP64]], 4 +; DEFAULT-NEXT: [[TMP66:%.*]] = sub i32 [[TMP65]], 1 +; DEFAULT-NEXT: [[VECTOR_RECUR_EXTRACT13:%.*]] = extractelement [[TMP20]], i32 [[TMP66]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[SCALAR_RECUR_INIT14:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT13]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] +; DEFAULT-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP60]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[SCALAR_RECUR:%.*]] = phi i32 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[TMP68:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[SCALAR_RECUR15:%.*]] = phi i32 [ [[SCALAR_RECUR_INIT14]], [[SCALAR_PH]] ], [ [[SCALAR_RECUR]], [[LOOP]] ] +; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[SUM_RED:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RED_2:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[TMP67:%.*]] = add i64 [[Y]], 1 +; DEFAULT-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[TMP67]] +; DEFAULT-NEXT: [[TMP68]] = load i32, ptr [[GEP_1]], align 4 +; DEFAULT-NEXT: [[OR3:%.*]] = or i32 [[SCALAR_RECUR15]], [[X]] +; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; DEFAULT-NEXT: [[SHR:%.*]] = lshr i32 [[X]], 1 +; DEFAULT-NEXT: [[TMP69:%.*]] = shl i32 [[OR3]], 1 +; DEFAULT-NEXT: [[TMP70:%.*]] = or i32 [[TMP69]], 2 +; DEFAULT-NEXT: [[SHL19:%.*]] = shl i32 [[X]], 1 +; DEFAULT-NEXT: [[TMP71:%.*]] = or i32 [[SHR]], [[SHL19]] +; DEFAULT-NEXT: [[TMP72:%.*]] = or i32 [[TMP71]], [[TMP70]] +; DEFAULT-NEXT: [[TMP73:%.*]] = or i32 [[TMP72]], [[X]] +; DEFAULT-NEXT: [[OR20:%.*]] = or i32 [[Z]], [[X]] +; DEFAULT-NEXT: [[NOT:%.*]] = and i32 [[OR20]], 1 +; DEFAULT-NEXT: [[AND:%.*]] = xor i32 [[NOT]], 1 +; DEFAULT-NEXT: [[IDX_EXT_1:%.*]] = zext i32 [[AND]] to i64 +; DEFAULT-NEXT: [[GEP_2:%.*]] = getelementptr i32, ptr [[SRC_2]], i64 [[IDX_EXT_1]] +; DEFAULT-NEXT: [[TMP74:%.*]] = load i32, ptr [[GEP_2]], align 4 +; DEFAULT-NEXT: [[SHR24:%.*]] = lshr i32 [[TMP73]], 1 +; DEFAULT-NEXT: [[IDX_EXT_2:%.*]] = zext i32 [[SHR24]] to i64 +; DEFAULT-NEXT: [[GEP_3:%.*]] = getelementptr i32, ptr [[SRC_2]], i64 [[IDX_EXT_2]] +; DEFAULT-NEXT: [[TMP75:%.*]] = load i32, ptr [[GEP_3]], align 4 +; DEFAULT-NEXT: [[RED_1:%.*]] = or i32 [[TMP74]], [[SUM_RED]] +; DEFAULT-NEXT: [[RED_2]] = or i32 [[RED_1]], [[TMP75]] +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[Y]] +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: [[RED_2_LCSSA:%.*]] = phi i32 [ [[RED_2]], [[LOOP]] ], [ [[TMP60]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: ret i32 [[RED_2_LCSSA]] +; +; PRED-LABEL: define i32 @chained_recurrences( +; PRED-SAME: i32 [[X:%.*]], i64 [[Y:%.*]], ptr [[SRC_1:%.*]], i32 [[Z:%.*]], ptr [[SRC_2:%.*]]) #[[ATTR0:[0-9]+]] { +; PRED-NEXT: entry: +; PRED-NEXT: [[TMP0:%.*]] = add i64 [[Y]], 1 +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 4 +; PRED-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 4 +; PRED-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], 1 +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], [[TMP5]] +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP2]] +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 4 +; PRED-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP9:%.*]] = mul i64 [[TMP8]], 4 +; PRED-NEXT: [[TMP10:%.*]] = sub i64 [[TMP0]], [[TMP9]] +; PRED-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP0]], [[TMP9]] +; PRED-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i64 [[TMP10]], i64 0 +; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call @llvm.get.active.lane.mask.nxv4i1.i64(i64 0, i64 [[TMP0]]) +; PRED-NEXT: [[TMP13:%.*]] = call i32 @llvm.vscale.i32() +; PRED-NEXT: [[TMP14:%.*]] = mul i32 [[TMP13]], 4 +; PRED-NEXT: [[TMP15:%.*]] = sub i32 [[TMP14]], 1 +; PRED-NEXT: [[VECTOR_RECUR_INIT:%.*]] = insertelement poison, i32 0, i32 [[TMP15]] +; PRED-NEXT: [[TMP16:%.*]] = call i32 @llvm.vscale.i32() +; PRED-NEXT: [[TMP17:%.*]] = mul i32 [[TMP16]], 4 +; PRED-NEXT: [[TMP18:%.*]] = sub i32 [[TMP17]], 1 +; PRED-NEXT: [[VECTOR_RECUR_INIT1:%.*]] = insertelement poison, i32 0, i32 [[TMP18]] +; PRED-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement poison, i32 [[X]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector [[BROADCAST_SPLATINSERT3]], poison, zeroinitializer +; PRED-NEXT: [[BROADCAST_SPLATINSERT5:%.*]] = insertelement poison, i32 [[Z]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT6:%.*]] = shufflevector [[BROADCAST_SPLATINSERT5]], poison, zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[VECTOR_RECUR:%.*]] = phi [ [[VECTOR_RECUR_INIT]], [[VECTOR_PH]] ], [ [[BROADCAST_SPLAT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[VECTOR_RECUR2:%.*]] = phi [ [[VECTOR_RECUR_INIT1]], [[VECTOR_PH]] ], [ [[TMP22:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[VEC_PHI:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP42:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[TMP19:%.*]] = add i64 [[Y]], 1 +; PRED-NEXT: [[TMP20:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[TMP19]] +; PRED-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i32 [[TMP21]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; PRED-NEXT: [[TMP22]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR]], [[BROADCAST_SPLAT]], i32 -1) +; PRED-NEXT: [[TMP23:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR2]], [[TMP22]], i32 -1) +; PRED-NEXT: [[TMP24:%.*]] = or [[TMP23]], [[BROADCAST_SPLAT4]] +; PRED-NEXT: [[TMP25:%.*]] = lshr [[BROADCAST_SPLAT4]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP26:%.*]] = shl [[TMP24]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP27:%.*]] = or [[TMP26]], shufflevector ( insertelement ( poison, i32 2, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP28:%.*]] = shl [[BROADCAST_SPLAT4]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP29:%.*]] = or [[TMP25]], [[TMP28]] +; PRED-NEXT: [[TMP30:%.*]] = or [[TMP29]], [[TMP27]] +; PRED-NEXT: [[TMP31:%.*]] = or [[TMP30]], [[BROADCAST_SPLAT4]] +; PRED-NEXT: [[TMP32:%.*]] = or [[BROADCAST_SPLAT6]], [[BROADCAST_SPLAT4]] +; PRED-NEXT: [[TMP33:%.*]] = and [[TMP32]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP34:%.*]] = xor [[TMP33]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP35:%.*]] = zext [[TMP34]] to +; PRED-NEXT: [[TMP36:%.*]] = getelementptr i32, ptr [[SRC_2]], [[TMP35]] +; PRED-NEXT: [[WIDE_MASKED_GATHER:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP36]], i32 4, [[ACTIVE_LANE_MASK]], poison) +; PRED-NEXT: [[TMP37:%.*]] = lshr [[TMP31]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP38:%.*]] = zext [[TMP37]] to +; PRED-NEXT: [[TMP39:%.*]] = getelementptr i32, ptr [[SRC_2]], [[TMP38]] +; PRED-NEXT: [[WIDE_MASKED_GATHER7:%.*]] = call @llvm.masked.gather.nxv4i32.nxv4p0( [[TMP39]], i32 4, [[ACTIVE_LANE_MASK]], poison) +; PRED-NEXT: [[TMP40:%.*]] = or [[WIDE_MASKED_GATHER]], [[VEC_PHI]] +; PRED-NEXT: [[TMP41:%.*]] = or [[TMP40]], [[WIDE_MASKED_GATHER7]] +; PRED-NEXT: [[TMP42]] = select [[ACTIVE_LANE_MASK]], [[TMP41]], [[VEC_PHI]] +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP7]] +; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv4i1.i64(i64 [[INDEX]], i64 [[TMP12]]) +; PRED-NEXT: [[TMP43:%.*]] = xor [[ACTIVE_LANE_MASK_NEXT]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP44:%.*]] = extractelement [[TMP43]], i32 0 +; PRED-NEXT: br i1 [[TMP44]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: [[TMP45:%.*]] = call i32 @llvm.vector.reduce.or.nxv4i32( [[TMP42]]) +; PRED-NEXT: [[TMP46:%.*]] = call i32 @llvm.vscale.i32() +; PRED-NEXT: [[TMP47:%.*]] = mul i32 [[TMP46]], 4 +; PRED-NEXT: [[TMP48:%.*]] = sub i32 [[TMP47]], 1 +; PRED-NEXT: [[VECTOR_RECUR_EXTRACT:%.*]] = extractelement [[BROADCAST_SPLAT]], i32 [[TMP48]] +; PRED-NEXT: [[TMP49:%.*]] = call i32 @llvm.vscale.i32() +; PRED-NEXT: [[TMP50:%.*]] = mul i32 [[TMP49]], 4 +; PRED-NEXT: [[TMP51:%.*]] = sub i32 [[TMP50]], 1 +; PRED-NEXT: [[VECTOR_RECUR_EXTRACT8:%.*]] = extractelement [[TMP22]], i32 [[TMP51]] +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[SCALAR_RECUR_INIT9:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[VECTOR_RECUR_EXTRACT8]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: [[SCALAR_RECUR_INIT:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[VECTOR_RECUR_EXTRACT]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY]] ] +; PRED-NEXT: [[BC_MERGE_RDX:%.*]] = phi i32 [ 0, [[ENTRY]] ], [ [[TMP45]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[SCALAR_RECUR:%.*]] = phi i32 [ [[SCALAR_RECUR_INIT]], [[SCALAR_PH]] ], [ [[TMP53:%.*]], [[LOOP]] ] +; PRED-NEXT: [[SCALAR_RECUR10:%.*]] = phi i32 [ [[SCALAR_RECUR_INIT9]], [[SCALAR_PH]] ], [ [[SCALAR_RECUR]], [[LOOP]] ] +; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[SUM_RED:%.*]] = phi i32 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RED_2:%.*]], [[LOOP]] ] +; PRED-NEXT: [[TMP52:%.*]] = add i64 [[Y]], 1 +; PRED-NEXT: [[GEP_1:%.*]] = getelementptr i32, ptr [[SRC_1]], i64 [[TMP52]] +; PRED-NEXT: [[TMP53]] = load i32, ptr [[GEP_1]], align 4 +; PRED-NEXT: [[OR3:%.*]] = or i32 [[SCALAR_RECUR10]], [[X]] +; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; PRED-NEXT: [[SHR:%.*]] = lshr i32 [[X]], 1 +; PRED-NEXT: [[TMP54:%.*]] = shl i32 [[OR3]], 1 +; PRED-NEXT: [[TMP55:%.*]] = or i32 [[TMP54]], 2 +; PRED-NEXT: [[SHL19:%.*]] = shl i32 [[X]], 1 +; PRED-NEXT: [[TMP56:%.*]] = or i32 [[SHR]], [[SHL19]] +; PRED-NEXT: [[TMP57:%.*]] = or i32 [[TMP56]], [[TMP55]] +; PRED-NEXT: [[TMP58:%.*]] = or i32 [[TMP57]], [[X]] +; PRED-NEXT: [[OR20:%.*]] = or i32 [[Z]], [[X]] +; PRED-NEXT: [[NOT:%.*]] = and i32 [[OR20]], 1 +; PRED-NEXT: [[AND:%.*]] = xor i32 [[NOT]], 1 +; PRED-NEXT: [[IDX_EXT_1:%.*]] = zext i32 [[AND]] to i64 +; PRED-NEXT: [[GEP_2:%.*]] = getelementptr i32, ptr [[SRC_2]], i64 [[IDX_EXT_1]] +; PRED-NEXT: [[TMP59:%.*]] = load i32, ptr [[GEP_2]], align 4 +; PRED-NEXT: [[SHR24:%.*]] = lshr i32 [[TMP58]], 1 +; PRED-NEXT: [[IDX_EXT_2:%.*]] = zext i32 [[SHR24]] to i64 +; PRED-NEXT: [[GEP_3:%.*]] = getelementptr i32, ptr [[SRC_2]], i64 [[IDX_EXT_2]] +; PRED-NEXT: [[TMP60:%.*]] = load i32, ptr [[GEP_3]], align 4 +; PRED-NEXT: [[RED_1:%.*]] = or i32 [[TMP59]], [[SUM_RED]] +; PRED-NEXT: [[RED_2]] = or i32 [[RED_1]], [[TMP60]] +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[Y]] +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; PRED: exit: +; PRED-NEXT: [[RED_2_LCSSA:%.*]] = phi i32 [ [[RED_2]], [[LOOP]] ], [ [[TMP45]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: ret i32 [[RED_2_LCSSA]] +; +entry: + br label %loop + +loop: + %2 = phi i32 [ 0, %entry ], [ %5, %loop ] + %3 = phi i32 [ 0, %entry ], [ %2, %loop ] + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %sum.red = phi i32 [ 0, %entry ], [ %red.2, %loop ] + %4 = add i64 %y, 1 + %gep.1 = getelementptr i32, ptr %src.1, i64 %4 + %5 = load i32, ptr %gep.1, align 4 + %or3 = or i32 %3, %x + %iv.next = add i64 %iv, 1 + %shr = lshr i32 %x, 1 + %6 = shl i32 %or3, 1 + %7 = or i32 %6, 2 + %shl19 = shl i32 %x, 1 + %8 = or i32 %shr, %shl19 + %9 = or i32 %8, %7 + %10 = or i32 %9, %x + %or20 = or i32 %z, %x + %not = and i32 %or20, 1 + %and = xor i32 %not, 1 + %idx.ext.1 = zext i32 %and to i64 + %gep.2 = getelementptr i32, ptr %src.2, i64 %idx.ext.1 + %11 = load i32, ptr %gep.2, align 4 + %shr24 = lshr i32 %10, 1 + %idx.ext.2 = zext i32 %shr24 to i64 + %gep.3 = getelementptr i32, ptr %src.2, i64 %idx.ext.2 + %12 = load i32, ptr %gep.3, align 4 + %red.1 = or i32 %11, %sum.red + %red.2 = or i32 %red.1, %12 + %ec = icmp eq i64 %iv, %y + br i1 %ec, label %exit, label %loop + +exit: + ret i32 %red.2 +} + +define i16 @reduce_udiv(ptr %src, i16 %x, i64 %N) #0 { +; DEFAULT-LABEL: define i16 @reduce_udiv( +; DEFAULT-SAME: ptr [[SRC:%.*]], i16 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; DEFAULT-NEXT: entry: +; DEFAULT-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; DEFAULT-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP0]], [[TMP2]] +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8 +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], [[TMP4]] +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 8 +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i16 [[X]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VEC_PHI:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP21:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[VEC_PHI1:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP22:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP7:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP9:%.*]] = mul i64 [[TMP8]], 4 +; DEFAULT-NEXT: [[TMP10:%.*]] = add i64 [[TMP9]], 0 +; DEFAULT-NEXT: [[TMP11:%.*]] = mul i64 [[TMP10]], 1 +; DEFAULT-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], [[TMP11]] +; DEFAULT-NEXT: [[TMP13:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP7]] +; DEFAULT-NEXT: [[TMP14:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP12]] +; DEFAULT-NEXT: [[TMP15:%.*]] = getelementptr i16, ptr [[TMP13]], i32 0 +; DEFAULT-NEXT: [[TMP16:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP17:%.*]] = mul i64 [[TMP16]], 4 +; DEFAULT-NEXT: [[TMP18:%.*]] = getelementptr i16, ptr [[TMP13]], i64 [[TMP17]] +; DEFAULT-NEXT: [[WIDE_LOAD:%.*]] = load , ptr [[TMP15]], align 2 +; DEFAULT-NEXT: [[WIDE_LOAD2:%.*]] = load , ptr [[TMP18]], align 2 +; DEFAULT-NEXT: [[TMP19:%.*]] = udiv [[WIDE_LOAD]], [[BROADCAST_SPLAT]] +; DEFAULT-NEXT: [[TMP20:%.*]] = udiv [[WIDE_LOAD2]], [[BROADCAST_SPLAT]] +; DEFAULT-NEXT: [[TMP21]] = or [[TMP19]], [[VEC_PHI]] +; DEFAULT-NEXT: [[TMP22]] = or [[TMP20]], [[VEC_PHI1]] +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP6]] +; DEFAULT-NEXT: [[TMP23:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP23]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[BIN_RDX:%.*]] = or [[TMP22]], [[TMP21]] +; DEFAULT-NEXT: [[TMP24:%.*]] = call i16 @llvm.vector.reduce.or.nxv4i16( [[BIN_RDX]]) +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP0]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[SCALAR_PH]] +; DEFAULT: scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; DEFAULT-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ 0, [[ENTRY]] ], [ [[TMP24]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[RED:%.*]] = phi i16 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[IV]] +; DEFAULT-NEXT: [[L:%.*]] = load i16, ptr [[GEP]], align 2 +; DEFAULT-NEXT: [[DIV:%.*]] = udiv i16 [[L]], [[X]] +; DEFAULT-NEXT: [[RED_NEXT]] = or i16 [[DIV]], [[RED]] +; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i16 [ [[RED_NEXT]], [[LOOP]] ], [ [[TMP24]], [[MIDDLE_BLOCK]] ] +; DEFAULT-NEXT: ret i16 [[RED_NEXT_LCSSA]] +; +; PRED-LABEL: define i16 @reduce_udiv( +; PRED-SAME: ptr [[SRC:%.*]], i16 [[X:%.*]], i64 [[N:%.*]]) #[[ATTR0]] { +; PRED-NEXT: entry: +; PRED-NEXT: [[TMP0:%.*]] = add i64 [[N]], 1 +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[TMP1:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP2:%.*]] = mul i64 [[TMP1]], 8 +; PRED-NEXT: [[TMP3:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP4:%.*]] = mul i64 [[TMP3]], 8 +; PRED-NEXT: [[TMP5:%.*]] = sub i64 [[TMP4]], 1 +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 [[TMP0]], [[TMP5]] +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP2]] +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 8 +; PRED-NEXT: [[TMP8:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP9:%.*]] = mul i64 [[TMP8]], 8 +; PRED-NEXT: [[TMP10:%.*]] = sub i64 [[TMP0]], [[TMP9]] +; PRED-NEXT: [[TMP11:%.*]] = icmp ugt i64 [[TMP0]], [[TMP9]] +; PRED-NEXT: [[TMP12:%.*]] = select i1 [[TMP11]], i64 [[TMP10]], i64 0 +; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 0, i64 [[TMP0]]) +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i16 [[X]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[VEC_PHI:%.*]] = phi [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP19:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[TMP13:%.*]] = add i64 [[INDEX]], 0 +; PRED-NEXT: [[TMP14:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[TMP13]] +; PRED-NEXT: [[TMP15:%.*]] = getelementptr i16, ptr [[TMP14]], i32 0 +; PRED-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call @llvm.masked.load.nxv8i16.p0(ptr [[TMP15]], i32 2, [[ACTIVE_LANE_MASK]], poison) +; PRED-NEXT: [[TMP16:%.*]] = select [[ACTIVE_LANE_MASK]], [[BROADCAST_SPLAT]], shufflevector ( insertelement ( poison, i16 1, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP17:%.*]] = udiv [[WIDE_MASKED_LOAD]], [[TMP16]] +; PRED-NEXT: [[TMP18:%.*]] = or [[TMP17]], [[VEC_PHI]] +; PRED-NEXT: [[TMP19]] = select [[ACTIVE_LANE_MASK]], [[TMP18]], [[VEC_PHI]] +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP7]] +; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv8i1.i64(i64 [[INDEX]], i64 [[TMP12]]) +; PRED-NEXT: [[TMP20:%.*]] = xor [[ACTIVE_LANE_MASK_NEXT]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP21:%.*]] = extractelement [[TMP20]], i32 0 +; PRED-NEXT: br i1 [[TMP21]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP4:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: [[TMP22:%.*]] = call i16 @llvm.vector.reduce.or.nxv8i16( [[TMP19]]) +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; PRED-NEXT: [[BC_MERGE_RDX:%.*]] = phi i16 [ 0, [[ENTRY]] ], [ [[TMP22]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[RED:%.*]] = phi i16 [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ], [ [[RED_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[GEP:%.*]] = getelementptr i16, ptr [[SRC]], i64 [[IV]] +; PRED-NEXT: [[L:%.*]] = load i16, ptr [[GEP]], align 2 +; PRED-NEXT: [[DIV:%.*]] = udiv i16 [[L]], [[X]] +; PRED-NEXT: [[RED_NEXT]] = or i16 [[DIV]], [[RED]] +; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], [[N]] +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP5:![0-9]+]] +; PRED: exit: +; PRED-NEXT: [[RED_NEXT_LCSSA:%.*]] = phi i16 [ [[RED_NEXT]], [[LOOP]] ], [ [[TMP22]], [[MIDDLE_BLOCK]] ] +; PRED-NEXT: ret i16 [[RED_NEXT_LCSSA]] +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %red = phi i16 [ 0, %entry ], [ %red.next, %loop ] + %gep = getelementptr i16, ptr %src, i64 %iv + %l = load i16, ptr %gep, align 2 + %div = udiv i16 %l, %x + %red.next = or i16 %div, %red + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, %N + br i1 %ec, label %exit, label %loop + +exit: + ret i16 %red.next +} + +attributes #0 = { "target-features"="+sve" } +;. +; DEFAULT: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; DEFAULT: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; DEFAULT: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; DEFAULT: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; DEFAULT: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} +;. +; PRED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; PRED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; PRED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; PRED: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; PRED: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]} +; PRED: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]} +;. diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll b/llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll new file mode 100644 index 000000000000..1e13d70083ff --- /dev/null +++ b/llvm/test/Transforms/LoopVectorize/AArch64/store-costs-sve.ll @@ -0,0 +1,341 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -p loop-vectorize -S %s | FileCheck --check-prefixes=DEFAULT %s +; RUN: opt -p loop-vectorize -prefer-predicate-over-epilogue=predicate-else-scalar-epilogue -S %s | FileCheck --check-prefixes=PRED %s + +target datalayout = "e-m:o-i64:64-i128:128-n32:64-S128" +target triple = "arm64-apple-macosx14.0.0" + +define void @cost_store_i8(ptr %dst) #0 { +; DEFAULT-LABEL: define void @cost_store_i8( +; DEFAULT-SAME: ptr [[DST:%.*]]) #[[ATTR0:[0-9]+]] { +; DEFAULT-NEXT: iter.check: +; DEFAULT-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 8 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 101, [[TMP1]] +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; DEFAULT: vector.main.loop.iter.check: +; DEFAULT-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 16 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK1:%.*]] = icmp ult i64 101, [[TMP3]] +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK1]], label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[TMP4:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP5:%.*]] = mul i64 [[TMP4]], 16 +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 101, [[TMP5]] +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 101, [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP6:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP7:%.*]] = mul i64 [[TMP6]], 16 +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP8:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP8]] +; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP9]], i32 0 +; DEFAULT-NEXT: store zeroinitializer, ptr [[TMP10]], align 1 +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP7]] +; DEFAULT-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP11]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 101, [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] +; DEFAULT: vec.epilog.iter.check: +; DEFAULT-NEXT: [[N_VEC_REMAINING:%.*]] = sub i64 101, [[N_VEC]] +; DEFAULT-NEXT: [[TMP12:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP13:%.*]] = mul i64 [[TMP12]], 8 +; DEFAULT-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 [[N_VEC_REMAINING]], [[TMP13]] +; DEFAULT-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]] +; DEFAULT: vec.epilog.ph: +; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; DEFAULT-NEXT: [[TMP14:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP15:%.*]] = mul i64 [[TMP14]], 8 +; DEFAULT-NEXT: [[N_MOD_VF2:%.*]] = urem i64 101, [[TMP15]] +; DEFAULT-NEXT: [[N_VEC3:%.*]] = sub i64 101, [[N_MOD_VF2]] +; DEFAULT-NEXT: [[TMP16:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP17:%.*]] = mul i64 [[TMP16]], 8 +; DEFAULT-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] +; DEFAULT: vec.epilog.vector.body: +; DEFAULT-NEXT: [[INDEX5:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT6:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP18:%.*]] = add i64 [[INDEX5]], 0 +; DEFAULT-NEXT: [[TMP19:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP18]] +; DEFAULT-NEXT: [[TMP20:%.*]] = getelementptr i8, ptr [[TMP19]], i32 0 +; DEFAULT-NEXT: store zeroinitializer, ptr [[TMP20]], align 1 +; DEFAULT-NEXT: [[INDEX_NEXT6]] = add nuw i64 [[INDEX5]], [[TMP17]] +; DEFAULT-NEXT: [[TMP21:%.*]] = icmp eq i64 [[INDEX_NEXT6]], [[N_VEC3]] +; DEFAULT-NEXT: br i1 [[TMP21]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP3:![0-9]+]] +; DEFAULT: vec.epilog.middle.block: +; DEFAULT-NEXT: [[CMP_N4:%.*]] = icmp eq i64 101, [[N_VEC3]] +; DEFAULT-NEXT: br i1 [[CMP_N4]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] +; DEFAULT: vec.epilog.scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC3]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ [[N_VEC]], [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; DEFAULT-NEXT: store i8 0, ptr [[GEP]], align 1 +; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100 +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP4:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @cost_store_i8( +; PRED-SAME: ptr [[DST:%.*]]) #[[ATTR0:[0-9]+]] { +; PRED-NEXT: entry: +; PRED-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 16 +; PRED-NEXT: [[TMP2:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP3:%.*]] = mul i64 [[TMP2]], 16 +; PRED-NEXT: [[TMP4:%.*]] = sub i64 [[TMP3]], 1 +; PRED-NEXT: [[N_RND_UP:%.*]] = add i64 101, [[TMP4]] +; PRED-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[N_RND_UP]], [[TMP1]] +; PRED-NEXT: [[N_VEC:%.*]] = sub i64 [[N_RND_UP]], [[N_MOD_VF]] +; PRED-NEXT: [[TMP5:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP6:%.*]] = mul i64 [[TMP5]], 16 +; PRED-NEXT: [[TMP7:%.*]] = call i64 @llvm.vscale.i64() +; PRED-NEXT: [[TMP8:%.*]] = mul i64 [[TMP7]], 16 +; PRED-NEXT: [[TMP9:%.*]] = sub i64 101, [[TMP8]] +; PRED-NEXT: [[TMP10:%.*]] = icmp ugt i64 101, [[TMP8]] +; PRED-NEXT: [[TMP11:%.*]] = select i1 [[TMP10]], i64 [[TMP9]], i64 0 +; PRED-NEXT: [[ACTIVE_LANE_MASK_ENTRY:%.*]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 0, i64 101) +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[ACTIVE_LANE_MASK:%.*]] = phi [ [[ACTIVE_LANE_MASK_ENTRY]], [[VECTOR_PH]] ], [ [[ACTIVE_LANE_MASK_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[TMP12:%.*]] = add i64 [[INDEX]], 0 +; PRED-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP12]] +; PRED-NEXT: [[TMP14:%.*]] = getelementptr i8, ptr [[TMP13]], i32 0 +; PRED-NEXT: call void @llvm.masked.store.nxv16i8.p0( zeroinitializer, ptr [[TMP14]], i32 1, [[ACTIVE_LANE_MASK]]) +; PRED-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP6]] +; PRED-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv16i1.i64(i64 [[INDEX]], i64 [[TMP11]]) +; PRED-NEXT: [[TMP15:%.*]] = xor [[ACTIVE_LANE_MASK_NEXT]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer) +; PRED-NEXT: [[TMP16:%.*]] = extractelement [[TMP15]], i32 0 +; PRED-NEXT: br i1 [[TMP16]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; PRED-NEXT: store i8 0, ptr [[GEP]], align 1 +; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV]], 100 +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP3:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %gep = getelementptr i8, ptr %dst, i64 %iv + store i8 0, ptr %gep, align 1 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv, 100 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +define void @trunc_store(ptr %dst, ptr %src, i16 %x) #1 { +; DEFAULT-LABEL: define void @trunc_store( +; DEFAULT-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i16 [[X:%.*]]) #[[ATTR1:[0-9]+]] { +; DEFAULT-NEXT: iter.check: +; DEFAULT-NEXT: [[TMP0:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP1:%.*]] = mul i64 [[TMP0]], 2 +; DEFAULT-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 0, [[TMP1]] +; DEFAULT-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; DEFAULT: vector.memcheck: +; DEFAULT-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 8 +; DEFAULT-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP]] +; DEFAULT-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[DST]] +; DEFAULT-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; DEFAULT-NEXT: br i1 [[FOUND_CONFLICT]], label [[VEC_EPILOG_SCALAR_PH]], label [[VECTOR_MAIN_LOOP_ITER_CHECK:%.*]] +; DEFAULT: vector.main.loop.iter.check: +; DEFAULT-NEXT: br i1 true, label [[VEC_EPILOG_PH:%.*]], label [[VECTOR_PH:%.*]] +; DEFAULT: vector.ph: +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT3:%.*]] = insertelement <16 x i16> poison, i16 [[X]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT4:%.*]] = shufflevector <16 x i16> [[BROADCAST_SPLATINSERT3]], <16 x i16> poison, <16 x i32> zeroinitializer +; DEFAULT-NEXT: br label [[VECTOR_BODY:%.*]] +; DEFAULT: vector.body: +; DEFAULT-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP2:%.*]] = add i64 [[INDEX]], 0 +; DEFAULT-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 16 +; DEFAULT-NEXT: [[TMP4:%.*]] = load i64, ptr [[SRC]], align 8, !alias.scope [[META5:![0-9]+]] +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <16 x i64> poison, i64 [[TMP4]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <16 x i64> [[BROADCAST_SPLATINSERT1]], <16 x i64> poison, <16 x i32> zeroinitializer +; DEFAULT-NEXT: [[TMP5:%.*]] = trunc <16 x i64> [[BROADCAST_SPLAT2]] to <16 x i8> +; DEFAULT-NEXT: [[TMP6:%.*]] = trunc <16 x i64> [[BROADCAST_SPLAT2]] to <16 x i8> +; DEFAULT-NEXT: [[TMP7:%.*]] = trunc <16 x i16> [[BROADCAST_SPLAT4]] to <16 x i8> +; DEFAULT-NEXT: [[TMP8:%.*]] = and <16 x i8> [[TMP5]], [[TMP7]] +; DEFAULT-NEXT: [[TMP9:%.*]] = and <16 x i8> [[TMP6]], [[TMP7]] +; DEFAULT-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP2]] +; DEFAULT-NEXT: [[TMP11:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP3]] +; DEFAULT-NEXT: [[TMP12:%.*]] = getelementptr i8, ptr [[TMP10]], i32 0 +; DEFAULT-NEXT: [[TMP13:%.*]] = getelementptr i8, ptr [[TMP10]], i32 16 +; DEFAULT-NEXT: store <16 x i8> [[TMP8]], ptr [[TMP12]], align 1, !alias.scope [[META8:![0-9]+]], !noalias [[META5]] +; DEFAULT-NEXT: store <16 x i8> [[TMP9]], ptr [[TMP13]], align 1, !alias.scope [[META8]], !noalias [[META5]] +; DEFAULT-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 32 +; DEFAULT-NEXT: [[TMP14:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0 +; DEFAULT-NEXT: br i1 [[TMP14]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP10:![0-9]+]] +; DEFAULT: middle.block: +; DEFAULT-NEXT: br i1 true, label [[EXIT:%.*]], label [[VEC_EPILOG_ITER_CHECK:%.*]] +; DEFAULT: vec.epilog.iter.check: +; DEFAULT-NEXT: [[TMP15:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP16:%.*]] = mul i64 [[TMP15]], 2 +; DEFAULT-NEXT: [[MIN_EPILOG_ITERS_CHECK:%.*]] = icmp ult i64 0, [[TMP16]] +; DEFAULT-NEXT: br i1 [[MIN_EPILOG_ITERS_CHECK]], label [[VEC_EPILOG_SCALAR_PH]], label [[VEC_EPILOG_PH]] +; DEFAULT: vec.epilog.ph: +; DEFAULT-NEXT: [[VEC_EPILOG_RESUME_VAL:%.*]] = phi i64 [ 0, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MAIN_LOOP_ITER_CHECK]] ] +; DEFAULT-NEXT: [[TMP17:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP18:%.*]] = mul i64 [[TMP17]], 2 +; DEFAULT-NEXT: [[N_MOD_VF:%.*]] = urem i64 0, [[TMP18]] +; DEFAULT-NEXT: [[N_VEC:%.*]] = sub i64 0, [[N_MOD_VF]] +; DEFAULT-NEXT: [[TMP19:%.*]] = call i64 @llvm.vscale.i64() +; DEFAULT-NEXT: [[TMP20:%.*]] = mul i64 [[TMP19]], 2 +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT6:%.*]] = insertelement poison, i16 [[X]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT7:%.*]] = shufflevector [[BROADCAST_SPLATINSERT6]], poison, zeroinitializer +; DEFAULT-NEXT: br label [[VEC_EPILOG_VECTOR_BODY:%.*]] +; DEFAULT: vec.epilog.vector.body: +; DEFAULT-NEXT: [[INDEX5:%.*]] = phi i64 [ [[VEC_EPILOG_RESUME_VAL]], [[VEC_EPILOG_PH]] ], [ [[INDEX_NEXT8:%.*]], [[VEC_EPILOG_VECTOR_BODY]] ] +; DEFAULT-NEXT: [[TMP21:%.*]] = add i64 [[INDEX5]], 0 +; DEFAULT-NEXT: [[TMP22:%.*]] = load i64, ptr [[SRC]], align 8, !alias.scope [[META11:![0-9]+]] +; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i64 [[TMP22]], i64 0 +; DEFAULT-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer +; DEFAULT-NEXT: [[TMP23:%.*]] = trunc [[BROADCAST_SPLAT]] to +; DEFAULT-NEXT: [[TMP24:%.*]] = trunc [[BROADCAST_SPLAT7]] to +; DEFAULT-NEXT: [[TMP25:%.*]] = and [[TMP23]], [[TMP24]] +; DEFAULT-NEXT: [[TMP26:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP21]] +; DEFAULT-NEXT: [[TMP27:%.*]] = getelementptr i8, ptr [[TMP26]], i32 0 +; DEFAULT-NEXT: store [[TMP25]], ptr [[TMP27]], align 1, !alias.scope [[META14:![0-9]+]], !noalias [[META11]] +; DEFAULT-NEXT: [[INDEX_NEXT8]] = add nuw i64 [[INDEX5]], [[TMP20]] +; DEFAULT-NEXT: [[TMP28:%.*]] = icmp eq i64 [[INDEX_NEXT8]], [[N_VEC]] +; DEFAULT-NEXT: br i1 [[TMP28]], label [[VEC_EPILOG_MIDDLE_BLOCK:%.*]], label [[VEC_EPILOG_VECTOR_BODY]], !llvm.loop [[LOOP16:![0-9]+]] +; DEFAULT: vec.epilog.middle.block: +; DEFAULT-NEXT: [[CMP_N:%.*]] = icmp eq i64 0, [[N_VEC]] +; DEFAULT-NEXT: br i1 [[CMP_N]], label [[EXIT]], label [[VEC_EPILOG_SCALAR_PH]] +; DEFAULT: vec.epilog.scalar.ph: +; DEFAULT-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[VEC_EPILOG_MIDDLE_BLOCK]] ], [ 0, [[VEC_EPILOG_ITER_CHECK]] ], [ 0, [[VECTOR_MEMCHECK]] ], [ 0, [[ITER_CHECK:%.*]] ] +; DEFAULT-NEXT: br label [[LOOP:%.*]] +; DEFAULT: loop: +; DEFAULT-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[VEC_EPILOG_SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; DEFAULT-NEXT: [[X_EXT:%.*]] = zext i16 [[X]] to i64 +; DEFAULT-NEXT: [[L:%.*]] = load i64, ptr [[SRC]], align 8 +; DEFAULT-NEXT: [[AND:%.*]] = and i64 [[L]], [[X_EXT]] +; DEFAULT-NEXT: [[TRUNC:%.*]] = trunc i64 [[AND]] to i8 +; DEFAULT-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; DEFAULT-NEXT: store i8 [[TRUNC]], ptr [[GEP]], align 1 +; DEFAULT-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; DEFAULT-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 0 +; DEFAULT-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP17:![0-9]+]] +; DEFAULT: exit: +; DEFAULT-NEXT: ret void +; +; PRED-LABEL: define void @trunc_store( +; PRED-SAME: ptr [[DST:%.*]], ptr [[SRC:%.*]], i16 [[X:%.*]]) #[[ATTR1:[0-9]+]] { +; PRED-NEXT: entry: +; PRED-NEXT: br i1 true, label [[SCALAR_PH:%.*]], label [[VECTOR_MEMCHECK:%.*]] +; PRED: vector.memcheck: +; PRED-NEXT: [[SCEVGEP:%.*]] = getelementptr i8, ptr [[SRC]], i64 8 +; PRED-NEXT: [[BOUND0:%.*]] = icmp ult ptr [[DST]], [[SCEVGEP]] +; PRED-NEXT: [[BOUND1:%.*]] = icmp ult ptr [[SRC]], [[DST]] +; PRED-NEXT: [[FOUND_CONFLICT:%.*]] = and i1 [[BOUND0]], [[BOUND1]] +; PRED-NEXT: br i1 [[FOUND_CONFLICT]], label [[SCALAR_PH]], label [[VECTOR_PH:%.*]] +; PRED: vector.ph: +; PRED-NEXT: [[BROADCAST_SPLATINSERT1:%.*]] = insertelement <16 x i16> poison, i16 [[X]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT2:%.*]] = shufflevector <16 x i16> [[BROADCAST_SPLATINSERT1]], <16 x i16> poison, <16 x i32> zeroinitializer +; PRED-NEXT: br label [[VECTOR_BODY:%.*]] +; PRED: vector.body: +; PRED-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] +; PRED-NEXT: [[TMP0:%.*]] = add i64 [[INDEX]], 0 +; PRED-NEXT: [[TMP1:%.*]] = load i64, ptr [[SRC]], align 8, !alias.scope [[META4:![0-9]+]] +; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <16 x i64> poison, i64 [[TMP1]], i64 0 +; PRED-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <16 x i64> [[BROADCAST_SPLATINSERT]], <16 x i64> poison, <16 x i32> zeroinitializer +; PRED-NEXT: [[TMP2:%.*]] = trunc <16 x i64> [[BROADCAST_SPLAT]] to <16 x i8> +; PRED-NEXT: [[TMP3:%.*]] = trunc <16 x i16> [[BROADCAST_SPLAT2]] to <16 x i8> +; PRED-NEXT: [[TMP4:%.*]] = and <16 x i8> [[TMP2]], [[TMP3]] +; PRED-NEXT: [[TMP5:%.*]] = getelementptr i8, ptr [[DST]], i64 [[TMP0]] +; PRED-NEXT: [[TMP6:%.*]] = getelementptr i8, ptr [[TMP5]], i32 0 +; PRED-NEXT: store <16 x i8> [[TMP4]], ptr [[TMP6]], align 1, !alias.scope [[META7:![0-9]+]], !noalias [[META4]] +; PRED-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 16 +; PRED-NEXT: [[TMP7:%.*]] = icmp eq i64 [[INDEX_NEXT]], 0 +; PRED-NEXT: br i1 [[TMP7]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP9:![0-9]+]] +; PRED: middle.block: +; PRED-NEXT: br i1 true, label [[EXIT:%.*]], label [[SCALAR_PH]] +; PRED: scalar.ph: +; PRED-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 0, [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ], [ 0, [[VECTOR_MEMCHECK]] ] +; PRED-NEXT: br label [[LOOP:%.*]] +; PRED: loop: +; PRED-NEXT: [[IV:%.*]] = phi i64 [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], [[LOOP]] ] +; PRED-NEXT: [[X_EXT:%.*]] = zext i16 [[X]] to i64 +; PRED-NEXT: [[L:%.*]] = load i64, ptr [[SRC]], align 8 +; PRED-NEXT: [[AND:%.*]] = and i64 [[L]], [[X_EXT]] +; PRED-NEXT: [[TRUNC:%.*]] = trunc i64 [[AND]] to i8 +; PRED-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[DST]], i64 [[IV]] +; PRED-NEXT: store i8 [[TRUNC]], ptr [[GEP]], align 1 +; PRED-NEXT: [[IV_NEXT]] = add i64 [[IV]], 1 +; PRED-NEXT: [[EC:%.*]] = icmp eq i64 [[IV_NEXT]], 0 +; PRED-NEXT: br i1 [[EC]], label [[EXIT]], label [[LOOP]], !llvm.loop [[LOOP10:![0-9]+]] +; PRED: exit: +; PRED-NEXT: ret void +; +entry: + br label %loop + +loop: + %iv = phi i64 [ 0, %entry ], [ %iv.next, %loop ] + %x.ext = zext i16 %x to i64 + %l = load i64, ptr %src, align 8 + %and = and i64 %l, %x.ext + %trunc = trunc i64 %and to i8 + %gep = getelementptr i8, ptr %dst, i64 %iv + store i8 %trunc, ptr %gep, align 1 + %iv.next = add i64 %iv, 1 + %ec = icmp eq i64 %iv.next, 0 + br i1 %ec, label %exit, label %loop + +exit: + ret void +} + +attributes #0 = { "target-features"="+sve" } +attributes #1 = { vscale_range(1,16) "target-features"="+sve" } + + +;. +; DEFAULT: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; DEFAULT: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; DEFAULT: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; DEFAULT: [[LOOP3]] = distinct !{[[LOOP3]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP4]] = distinct !{[[LOOP4]], [[META2]], [[META1]]} +; DEFAULT: [[META5]] = !{[[META6:![0-9]+]]} +; DEFAULT: [[META6]] = distinct !{[[META6]], [[META7:![0-9]+]]} +; DEFAULT: [[META7]] = distinct !{[[META7]], !"LVerDomain"} +; DEFAULT: [[META8]] = !{[[META9:![0-9]+]]} +; DEFAULT: [[META9]] = distinct !{[[META9]], [[META7]]} +; DEFAULT: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]], [[META2]]} +; DEFAULT: [[META11]] = !{[[META12:![0-9]+]]} +; DEFAULT: [[META12]] = distinct !{[[META12]], [[META13:![0-9]+]]} +; DEFAULT: [[META13]] = distinct !{[[META13]], !"LVerDomain"} +; DEFAULT: [[META14]] = !{[[META15:![0-9]+]]} +; DEFAULT: [[META15]] = distinct !{[[META15]], [[META13]]} +; DEFAULT: [[LOOP16]] = distinct !{[[LOOP16]], [[META1]], [[META2]]} +; DEFAULT: [[LOOP17]] = distinct !{[[LOOP17]], [[META1]]} +;. +; PRED: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]} +; PRED: [[META1]] = !{!"llvm.loop.isvectorized", i32 1} +; PRED: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"} +; PRED: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]} +; PRED: [[META4]] = !{[[META5:![0-9]+]]} +; PRED: [[META5]] = distinct !{[[META5]], [[META6:![0-9]+]]} +; PRED: [[META6]] = distinct !{[[META6]], !"LVerDomain"} +; PRED: [[META7]] = !{[[META8:![0-9]+]]} +; PRED: [[META8]] = distinct !{[[META8]], [[META6]]} +; PRED: [[LOOP9]] = distinct !{[[LOOP9]], [[META1]], [[META2]]} +; PRED: [[LOOP10]] = distinct !{[[LOOP10]], [[META1]]} +;. -- GitLab From b4af01bada0c945906d85c364e12aceaf98b0fae Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Sat, 27 Apr 2024 15:10:48 -0700 Subject: [PATCH 137/301] [clang-format][NFC] Don't repeat Changes[i]/Changes[i - 1] --- clang/lib/Format/WhitespaceManager.cpp | 39 ++++++++++++-------------- 1 file changed, 18 insertions(+), 21 deletions(-) diff --git a/clang/lib/Format/WhitespaceManager.cpp b/clang/lib/Format/WhitespaceManager.cpp index 4f822807dd98..cc9bcce6c414 100644 --- a/clang/lib/Format/WhitespaceManager.cpp +++ b/clang/lib/Format/WhitespaceManager.cpp @@ -128,11 +128,13 @@ const tooling::Replacements &WhitespaceManager::generateReplacements() { void WhitespaceManager::calculateLineBreakInformation() { Changes[0].PreviousEndOfTokenColumn = 0; Change *LastOutsideTokenChange = &Changes[0]; - for (unsigned i = 1, e = Changes.size(); i != e; ++i) { + for (unsigned I = 1, e = Changes.size(); I != e; ++I) { + auto &C = Changes[I]; + auto &P = Changes[I - 1]; SourceLocation OriginalWhitespaceStart = - Changes[i].OriginalWhitespaceRange.getBegin(); + C.OriginalWhitespaceRange.getBegin(); SourceLocation PreviousOriginalWhitespaceEnd = - Changes[i - 1].OriginalWhitespaceRange.getEnd(); + P.OriginalWhitespaceRange.getEnd(); unsigned OriginalWhitespaceStartOffset = SourceMgr.getFileOffset(OriginalWhitespaceStart); unsigned PreviousOriginalWhitespaceEndOffset = @@ -167,31 +169,26 @@ void WhitespaceManager::calculateLineBreakInformation() { // line of the token. auto NewlinePos = Text.find_first_of('\n'); if (NewlinePos == StringRef::npos) { - Changes[i - 1].TokenLength = OriginalWhitespaceStartOffset - - PreviousOriginalWhitespaceEndOffset + - Changes[i].PreviousLinePostfix.size() + - Changes[i - 1].CurrentLinePrefix.size(); + P.TokenLength = OriginalWhitespaceStartOffset - + PreviousOriginalWhitespaceEndOffset + + C.PreviousLinePostfix.size() + P.CurrentLinePrefix.size(); } else { - Changes[i - 1].TokenLength = - NewlinePos + Changes[i - 1].CurrentLinePrefix.size(); + P.TokenLength = NewlinePos + P.CurrentLinePrefix.size(); } // If there are multiple changes in this token, sum up all the changes until // the end of the line. - if (Changes[i - 1].IsInsideToken && Changes[i - 1].NewlinesBefore == 0) { - LastOutsideTokenChange->TokenLength += - Changes[i - 1].TokenLength + Changes[i - 1].Spaces; - } else { - LastOutsideTokenChange = &Changes[i - 1]; - } + if (P.IsInsideToken && P.NewlinesBefore == 0) + LastOutsideTokenChange->TokenLength += P.TokenLength + P.Spaces; + else + LastOutsideTokenChange = &P; - Changes[i].PreviousEndOfTokenColumn = - Changes[i - 1].StartOfTokenColumn + Changes[i - 1].TokenLength; + C.PreviousEndOfTokenColumn = P.StartOfTokenColumn + P.TokenLength; - Changes[i - 1].IsTrailingComment = - (Changes[i].NewlinesBefore > 0 || Changes[i].Tok->is(tok::eof) || - (Changes[i].IsInsideToken && Changes[i].Tok->is(tok::comment))) && - Changes[i - 1].Tok->is(tok::comment) && + P.IsTrailingComment = + (C.NewlinesBefore > 0 || C.Tok->is(tok::eof) || + (C.IsInsideToken && C.Tok->is(tok::comment))) && + P.Tok->is(tok::comment) && // FIXME: This is a dirty hack. The problem is that // BreakableLineCommentSection does comment reflow changes and here is // the aligning of trailing comments. Consider the case where we reflow -- GitLab From 53ff002c6f7ec64a75ab0990b1314cc6b4bb67cf Mon Sep 17 00:00:00 2001 From: Tom Stellard Date: Sat, 27 Apr 2024 15:32:58 -0700 Subject: [PATCH 138/301] [CMake][Release] Enable CMAKE_POSITION_INDEPENDENT_CODE (#90139) Set this in the cache file directly instead of via the test-release.sh script so that the release builds can be reproduced with just the cache file. --- clang/cmake/caches/Release.cmake | 1 + llvm/utils/release/test-release.sh | 3 +-- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/cmake/caches/Release.cmake b/clang/cmake/caches/Release.cmake index c164d5497275..c0bfcbdfc1c2 100644 --- a/clang/cmake/caches/Release.cmake +++ b/clang/cmake/caches/Release.cmake @@ -82,6 +82,7 @@ set(LLVM_ENABLE_PROJECTS ${STAGE1_PROJECTS} CACHE STRING "") # stage2-instrumented and Final Stage Config: # Options that need to be set in both the instrumented stage (if we are doing # a pgo build) and the final stage. +set_instrument_and_final_stage_var(CMAKE_POSITION_INDEPENDENT_CODE "ON" STRING) set_instrument_and_final_stage_var(LLVM_ENABLE_LTO "${LLVM_RELEASE_ENABLE_LTO}" STRING) if (LLVM_RELEASE_ENABLE_LTO) set_instrument_and_final_stage_var(LLVM_ENABLE_LLD "ON" BOOL) diff --git a/llvm/utils/release/test-release.sh b/llvm/utils/release/test-release.sh index 4314b565e11b..050004aa08c4 100755 --- a/llvm/utils/release/test-release.sh +++ b/llvm/utils/release/test-release.sh @@ -353,8 +353,7 @@ function build_with_cmake_cache() { env CC="$c_compiler" CXX="$cxx_compiler" \ cmake -G "$generator" -B $CMakeBuildDir -S $SrcDir/llvm \ -C $SrcDir/clang/cmake/caches/Release.cmake \ - -DCLANG_BOOTSTRAP_PASSTHROUGH="CMAKE_POSITION_INDEPENDENT_CODE;LLVM_LIT_ARGS" \ - -DCMAKE_POSITION_INDEPENDENT_CODE=ON \ + -DCLANG_BOOTSTRAP_PASSTHROUGH="LLVM_LIT_ARGS" \ -DLLVM_LIT_ARGS="-j $NumJobs $LitVerbose" \ $ExtraConfigureFlags 2>&1 | tee $LogDir/llvm.configure-$Flavor.log -- GitLab From ad1e10ae1109fa7204ab70422bb611fe88391228 Mon Sep 17 00:00:00 2001 From: Nathan Lanza Date: Sat, 27 Apr 2024 19:05:00 -0400 Subject: [PATCH 139/301] [github] Add ClangIR codeowners (#86089) --- .github/CODEOWNERS | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/CODEOWNERS b/.github/CODEOWNERS index 45da8af51bb9..0f178df1d18f 100644 --- a/.github/CODEOWNERS +++ b/.github/CODEOWNERS @@ -35,6 +35,10 @@ clang/lib/AST/Interp/ @tbaederr clang/test/AST/Interp/ @tbaederr +/clang/include/clang/CIR @lanza @bcardosolopes +/clang/lib/CIR @lanza @bcardosolopes +/clang/tools/cir-* @lanza @bcardosolopes + /lldb/ @JDevlieghere # MLIR Interfaces. -- GitLab From 1a462296360f311d4593694aefd30c6b3e969460 Mon Sep 17 00:00:00 2001 From: Congcong Cai Date: Sun, 28 Apr 2024 10:13:02 +0800 Subject: [PATCH 140/301] Revert "Revert "[WebAssembly] remove instruction after builtin trap" (#90354)" (#90366) `llvm.trap` will be convert as unreachable which is terminator. Instruction after terminator will cause validation failed. This PR introduces a pass to clean instruction after terminator. Fixes: https://github.com/llvm/llvm-project/issues/68770 Reapply: #90207 --- lld/test/wasm/init-fini.ll | 2 +- llvm/lib/Target/WebAssembly/CMakeLists.txt | 1 + llvm/lib/Target/WebAssembly/WebAssembly.h | 2 + .../WebAssemblyCleanCodeAfterTrap.cpp | 80 +++++++++++++++++++ .../WebAssembly/WebAssemblyTargetMachine.cpp | 4 + llvm/test/CodeGen/WebAssembly/unreachable.ll | 11 ++- llvm/test/MC/WebAssembly/global-ctor-dtor.ll | 12 +-- 7 files changed, 103 insertions(+), 9 deletions(-) create mode 100644 llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp diff --git a/lld/test/wasm/init-fini.ll b/lld/test/wasm/init-fini.ll index 3d2e9a78043e..ef2f41f96e89 100644 --- a/lld/test/wasm/init-fini.ll +++ b/lld/test/wasm/init-fini.ll @@ -78,7 +78,7 @@ entry: ; CHECK-NEXT: Body: 10041005100A100F1012100F10141004100C100F10161002100E0B ; CHECK: - Index: 22 ; CHECK-NEXT: Locals: -; CHECK-NEXT: Body: 02404186808080004100418088808000108080808000450D0000000B0B +; CHECK-NEXT: Body: 02404186808080004100418088808000108080808000450D00000B0B ; CHECK-NEXT: - Type: CUSTOM ; CHECK-NEXT: Name: name ; CHECK-NEXT: FunctionNames: diff --git a/llvm/lib/Target/WebAssembly/CMakeLists.txt b/llvm/lib/Target/WebAssembly/CMakeLists.txt index f430be2653b4..1e83cbeac50d 100644 --- a/llvm/lib/Target/WebAssembly/CMakeLists.txt +++ b/llvm/lib/Target/WebAssembly/CMakeLists.txt @@ -19,6 +19,7 @@ add_llvm_target(WebAssemblyCodeGen WebAssemblyArgumentMove.cpp WebAssemblyAsmPrinter.cpp WebAssemblyCFGStackify.cpp + WebAssemblyCleanCodeAfterTrap.cpp WebAssemblyCFGSort.cpp WebAssemblyDebugFixup.cpp WebAssemblyDebugValueManager.cpp diff --git a/llvm/lib/Target/WebAssembly/WebAssembly.h b/llvm/lib/Target/WebAssembly/WebAssembly.h index 1c40addb6d6f..7fc8546248f1 100644 --- a/llvm/lib/Target/WebAssembly/WebAssembly.h +++ b/llvm/lib/Target/WebAssembly/WebAssembly.h @@ -37,6 +37,7 @@ FunctionPass *createWebAssemblyISelDag(WebAssemblyTargetMachine &TM, CodeGenOptLevel OptLevel); FunctionPass *createWebAssemblyArgumentMove(); FunctionPass *createWebAssemblySetP2AlignOperands(); +FunctionPass *createWebAssemblyCleanCodeAfterTrap(); // Late passes. FunctionPass *createWebAssemblyReplacePhysRegs(); @@ -63,6 +64,7 @@ void initializeOptimizeReturnedPass(PassRegistry &); void initializeWebAssemblyRefTypeMem2LocalPass(PassRegistry &); void initializeWebAssemblyAddMissingPrototypesPass(PassRegistry &); void initializeWebAssemblyArgumentMovePass(PassRegistry &); +void initializeWebAssemblyCleanCodeAfterTrapPass(PassRegistry &); void initializeWebAssemblyCFGSortPass(PassRegistry &); void initializeWebAssemblyCFGStackifyPass(PassRegistry &); void initializeWebAssemblyDAGToDAGISelPass(PassRegistry &); diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp new file mode 100644 index 000000000000..e5cba3c48547 --- /dev/null +++ b/llvm/lib/Target/WebAssembly/WebAssemblyCleanCodeAfterTrap.cpp @@ -0,0 +1,80 @@ +//===-- WebAssemblyCleanCodeAfterTrap.cpp - Clean Code After Trap ---------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +/// +/// \file +/// This file remove instruction after trap. +/// ``llvm.trap`` will be convert as ``unreachable`` which is terminator. +/// Instruction after terminator will cause validation failed. +/// +//===----------------------------------------------------------------------===// + +#include "WebAssembly.h" +#include "WebAssemblyUtilities.h" +#include "llvm/ADT/SmallVector.h" +#include "llvm/CodeGen/MachineBlockFrequencyInfo.h" +#include "llvm/CodeGen/Passes.h" +#include "llvm/MC/MCInstrDesc.h" +#include "llvm/Support/Debug.h" +#include "llvm/Support/raw_ostream.h" +using namespace llvm; + +#define DEBUG_TYPE "wasm-clean-code-after-trap" + +namespace { +class WebAssemblyCleanCodeAfterTrap final : public MachineFunctionPass { +public: + static char ID; // Pass identification, replacement for typeid + WebAssemblyCleanCodeAfterTrap() : MachineFunctionPass(ID) {} + + StringRef getPassName() const override { + return "WebAssembly Clean Code After Trap"; + } + + bool runOnMachineFunction(MachineFunction &MF) override; +}; +} // end anonymous namespace + +char WebAssemblyCleanCodeAfterTrap::ID = 0; +INITIALIZE_PASS(WebAssemblyCleanCodeAfterTrap, DEBUG_TYPE, + "WebAssembly Clean Code After Trap", false, false) + +FunctionPass *llvm::createWebAssemblyCleanCodeAfterTrap() { + return new WebAssemblyCleanCodeAfterTrap(); +} + +bool WebAssemblyCleanCodeAfterTrap::runOnMachineFunction(MachineFunction &MF) { + LLVM_DEBUG({ + dbgs() << "********** CleanCodeAfterTrap **********\n" + << "********** Function: " << MF.getName() << '\n'; + }); + + bool Changed = false; + + for (MachineBasicBlock &BB : MF) { + bool HasTerminator = false; + llvm::SmallVector RemoveMI{}; + for (MachineInstr &MI : BB) { + if (HasTerminator) + RemoveMI.push_back(&MI); + if (MI.hasProperty(MCID::Trap) && MI.isTerminator()) + HasTerminator = true; + } + if (!RemoveMI.empty()) { + Changed = true; + LLVM_DEBUG({ + for (MachineInstr *MI : RemoveMI) { + llvm::dbgs() << "* remove "; + MI->print(llvm::dbgs()); + } + }); + for (MachineInstr *MI : RemoveMI) + MI->eraseFromParent(); + } + } + return Changed; +} diff --git a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp index cdd39eeb6bbb..de342e896573 100644 --- a/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp +++ b/llvm/lib/Target/WebAssembly/WebAssemblyTargetMachine.cpp @@ -512,6 +512,10 @@ bool WebAssemblyPassConfig::addInstSelector() { // Eliminate range checks and add default targets to br_table instructions. addPass(createWebAssemblyFixBrTableDefaults()); + // unreachable is terminator, non-terminator instruction after it is not + // allowed. + addPass(createWebAssemblyCleanCodeAfterTrap()); + return false; } diff --git a/llvm/test/CodeGen/WebAssembly/unreachable.ll b/llvm/test/CodeGen/WebAssembly/unreachable.ll index 5368c2ba5b8d..ccac31a9af4a 100644 --- a/llvm/test/CodeGen/WebAssembly/unreachable.ll +++ b/llvm/test/CodeGen/WebAssembly/unreachable.ll @@ -30,7 +30,6 @@ define void @trap_ret_void() { ; CHECK: .functype trap_ret_void () -> () ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: unreachable -; CHECK-NEXT: # fallthrough-return ; CHECK-NEXT: end_function call void @llvm.trap() ret void @@ -54,7 +53,6 @@ define void @trap_unreacheable() { ; CHECK: .functype trap_unreacheable () -> () ; CHECK-NEXT: # %bb.0: ; CHECK-NEXT: unreachable -; CHECK-NEXT: unreachable ; CHECK-NEXT: end_function call void @llvm.trap() unreachable @@ -94,3 +92,12 @@ define i32 @missing_ret_noreturn_unreachable() { call void @ext_never_return() unreachable } + +define i32 @no_crash_for_other_instruction_after_trap(ptr %p, i32 %b) { +; CHECK-LABEL: no_crash_for_other_instruction_after_trap: +; CHECK: unreachable +; CHECK-NEXT: end_function + %a = load i32, ptr %p + call void @llvm.trap() + ret i32 %a +} diff --git a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll index bc1be7931349..f1ec71da1ebb 100644 --- a/llvm/test/MC/WebAssembly/global-ctor-dtor.ll +++ b/llvm/test/MC/WebAssembly/global-ctor-dtor.ll @@ -80,29 +80,29 @@ declare void @func3() ; CHECK-NEXT: Offset: 0x1D ; CHECK-NEXT: - Type: R_WASM_FUNCTION_INDEX_LEB ; CHECK-NEXT: Index: 6 -; CHECK-NEXT: Offset: 0x2C +; CHECK-NEXT: Offset: 0x2B ; CHECK-NEXT: - Type: R_WASM_TABLE_INDEX_SLEB ; CHECK-NEXT: Index: 5 -; CHECK-NEXT: Offset: 0x37 +; CHECK-NEXT: Offset: 0x36 ; CHECK-NEXT: - Type: R_WASM_MEMORY_ADDR_SLEB ; CHECK-NEXT: Index: 3 -; CHECK-NEXT: Offset: 0x3F +; CHECK-NEXT: Offset: 0x3E ; CHECK-NEXT: - Type: R_WASM_FUNCTION_INDEX_LEB ; CHECK-NEXT: Index: 4 -; CHECK-NEXT: Offset: 0x45 +; CHECK-NEXT: Offset: 0x44 ; CHECK-NEXT: Functions: ; CHECK-NEXT: - Index: 5 ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 1080808080000B ; CHECK-NEXT: - Index: 6 ; CHECK-NEXT: Locals: -; CHECK-NEXT: Body: 02404181808080004100418080808000108180808000450D0000000B0B +; CHECK-NEXT: Body: 02404181808080004100418080808000108180808000450D00000B0B ; CHECK-NEXT: - Index: 7 ; CHECK-NEXT: Locals: ; CHECK-NEXT: Body: 1082808080000B ; CHECK-NEXT: - Index: 8 ; CHECK-NEXT: Locals: -; CHECK-NEXT: Body: 02404182808080004100418080808000108180808000450D0000000B0B +; CHECK-NEXT: Body: 02404182808080004100418080808000108180808000450D00000B0B ; CHECK-NEXT: - Type: DATA ; CHECK-NEXT: Segments: ; CHECK-NEXT: - SectionOffset: 6 -- GitLab From 679e99d6667343e32f418d249e1af1cd76f1c08a Mon Sep 17 00:00:00 2001 From: LLVM GN Syncbot Date: Sun, 28 Apr 2024 02:13:33 +0000 Subject: [PATCH 141/301] [gn build] Port 1a462296360f --- llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn | 1 + 1 file changed, 1 insertion(+) diff --git a/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn b/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn index a8d6290f1b99..2ece91331c5d 100644 --- a/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn +++ b/llvm/utils/gn/secondary/llvm/lib/Target/WebAssembly/BUILD.gn @@ -37,6 +37,7 @@ static_library("LLVMWebAssemblyCodeGen") { "WebAssemblyAsmPrinter.cpp", "WebAssemblyCFGSort.cpp", "WebAssemblyCFGStackify.cpp", + "WebAssemblyCleanCodeAfterTrap.cpp", "WebAssemblyDebugFixup.cpp", "WebAssemblyDebugValueManager.cpp", "WebAssemblyExceptionInfo.cpp", -- GitLab From 7037878d2b4afbda436ec61008ac907bd782bdd8 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Sun, 28 Apr 2024 11:16:43 +0800 Subject: [PATCH 142/301] [RISCV][TableGen] Get right experimental extension name We should remove the `experimental-` prefix when printing march string. We didn't meet this problem because there is no processor containing experimental extensions. Reviewers: fpetrogalli, asb, topperc Reviewed By: topperc, asb Pull Request: https://github.com/llvm/llvm-project/pull/90185 --- llvm/test/TableGen/riscv-target-def.td | 6 ++++-- llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 2 +- 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index 01c72e07460e..865179fb79a6 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -83,6 +83,7 @@ def ROCKET_RV32 : RISCVProcessorModel<"rocket-rv32", FeatureStdExtI, FeatureStdExtZifencei, FeatureStdExtZicsr, + FeatureStdExtZidummy, FeatureDummy]>; def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64", NoSchedModel, @@ -90,6 +91,7 @@ def ROCKET_RV64 : RISCVProcessorModel<"rocket-rv64", FeatureStdExtI, FeatureStdExtZifencei, FeatureStdExtZicsr, + FeatureStdExtZidummy, FeatureDummy]>; def ROCKET : RISCVTuneProcessorModel<"rocket", NoSchedModel>; @@ -125,8 +127,8 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", // CHECK: PROC(GENERIC_RV32, {"generic-rv32"}, {"rv32i2p1"}, 0) // CHECK-NEXT: PROC(GENERIC_RV64, {"generic-rv64"}, {"rv64i2p1"}, 0) -// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zifencei2p0"}, 0) -// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zifencei2p0"}, 0) +// CHECK-NEXT: PROC(ROCKET_RV32, {"rocket-rv32"}, {"rv32i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0) +// CHECK-NEXT: PROC(ROCKET_RV64, {"rocket-rv64"}, {"rv64i2p1_zicsr2p0_zidummy0p1_zifencei2p0"}, 0) // CHECK: #undef PROC diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 18c5be20244e..787d22f635d0 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -95,7 +95,7 @@ static void printMArch(raw_ostream &OS, const Record &Rec) { // Convert features to FeatureVector. for (auto *Feature : Rec.getValueAsListOfDefs("Features")) { - StringRef FeatureName = Feature->getValueAsString("Name"); + StringRef FeatureName = getExtensionName(Feature); if (Feature->isSubClassOf("RISCVExtension")) { unsigned Major = Feature->getValueAsInt("MajorVersion"); unsigned Minor = Feature->getValueAsInt("MinorVersion"); -- GitLab From f86d264dfdd6d1fa2fc6f933c9ae7b5db50a770b Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Sun, 28 Apr 2024 11:32:37 +0800 Subject: [PATCH 143/301] [RISCV] Add subtarget features for profiles This may simplify the usage of tools like `opt`, `llc`, etc. Reviewers: michaelmaitland, 4vtomat, preames, asb Reviewed By: michaelmaitland, preames, 4vtomat Pull Request: https://github.com/llvm/llvm-project/pull/84877 --- llvm/lib/Target/RISCV/RISCV.td | 6 + llvm/lib/Target/RISCV/RISCVProfiles.td | 204 +++++++++++++++++++++++++ llvm/test/CodeGen/RISCV/attributes.ll | 25 +++ 3 files changed, 235 insertions(+) create mode 100644 llvm/lib/Target/RISCV/RISCVProfiles.td diff --git a/llvm/lib/Target/RISCV/RISCV.td b/llvm/lib/Target/RISCV/RISCV.td index 9fb84efd5b6f..09f496574d64 100644 --- a/llvm/lib/Target/RISCV/RISCV.td +++ b/llvm/lib/Target/RISCV/RISCV.td @@ -14,6 +14,12 @@ include "llvm/Target/Target.td" include "RISCVFeatures.td" +//===----------------------------------------------------------------------===// +// RISC-V profiles supported. +//===----------------------------------------------------------------------===// + +include "RISCVProfiles.td" + //===----------------------------------------------------------------------===// // Named operands for CSR instructions. //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Target/RISCV/RISCVProfiles.td b/llvm/lib/Target/RISCV/RISCVProfiles.td new file mode 100644 index 000000000000..5c13710faf65 --- /dev/null +++ b/llvm/lib/Target/RISCV/RISCVProfiles.td @@ -0,0 +1,204 @@ +//===------ RISCVProfiles.td - RISC-V Profiles -------------*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +class RISCVProfile features> + : SubtargetFeature; + +defvar RVI20U32Features = [Feature32Bit, FeatureStdExtI]; +defvar RVI20U64Features = [Feature64Bit, FeatureStdExtI]; + +defvar RVA20U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZa128rs, + FeatureStdExtZicclsm]; + +defvar RVA20S64Features = !listconcat(RVA20U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala]); + +defvar RVA22U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihpm, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZfhmin, + FeatureStdExtZkt]; + +defvar RVA22S64Features = !listconcat(RVA22U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval]); + +defvar RVA23U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZfhmin, + FeatureStdExtZkt, + FeatureStdExtV, + FeatureStdExtZvfhmin, + FeatureStdExtZvbb, + FeatureStdExtZvkt, + FeatureStdExtZihintntl, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZcmop, + FeatureStdExtZcb, + FeatureStdExtZfa, + FeatureStdExtZawrs]; + +defvar RVA23S64Features = !listconcat(RVA23U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtSvnapot, + FeatureStdExtSstc, + FeatureStdExtSscofpmf, + FeatureStdExtSsnpm, + FeatureStdExtSsu64xl, + FeatureStdExtH, + FeatureStdExtSsstateen, + FeatureStdExtShcounterenw, + FeatureStdExtShvstvala, + FeatureStdExtShtvala, + FeatureStdExtShvstvecd, + FeatureStdExtShvsatpa, + FeatureStdExtShgatpa]); + +defvar RVB23U64Features = [Feature64Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtA, + FeatureStdExtF, + FeatureStdExtD, + FeatureStdExtC, + FeatureStdExtZicntr, + FeatureStdExtZihpm, + FeatureStdExtZiccif, + FeatureStdExtZiccrse, + FeatureStdExtZiccamoa, + FeatureStdExtZicclsm, + FeatureStdExtZa64rs, + FeatureStdExtZihintpause, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZic64b, + FeatureStdExtZicbom, + FeatureStdExtZicbop, + FeatureStdExtZicboz, + FeatureStdExtZkt, + FeatureStdExtZihintntl, + FeatureStdExtZicond, + FeatureStdExtZimop, + FeatureStdExtZcmop, + FeatureStdExtZcb, + FeatureStdExtZfa, + FeatureStdExtZawrs]; + +defvar RVB23S64Features = !listconcat(RVB23U64Features, + [FeatureStdExtZifencei, + FeatureStdExtSvnapot, + FeatureStdExtSvbare, + FeatureStdExtSvade, + FeatureStdExtSsccptr, + FeatureStdExtSstvecd, + FeatureStdExtSstvala, + FeatureStdExtSscounterenw, + FeatureStdExtSvpbmt, + FeatureStdExtSvinval, + FeatureStdExtSstc, + FeatureStdExtSscofpmf, + FeatureStdExtSsu64xl]); + +defvar RVM23U32Features = [Feature32Bit, + FeatureStdExtI, + FeatureStdExtM, + FeatureStdExtZba, + FeatureStdExtZbb, + FeatureStdExtZbs, + FeatureStdExtZicond, + FeatureStdExtZihintpause, + FeatureStdExtZihintntl, + FeatureStdExtZce, + FeatureStdExtZicbop, + FeatureStdExtZimop, + FeatureStdExtZcmop]; + +def RVI20U32 : RISCVProfile<"rvi20u32", RVI20U32Features>; +def RVI20U64 : RISCVProfile<"rvi20u64", RVI20U64Features>; +def RVA20U64 : RISCVProfile<"rva20u64", RVA20U64Features>; +def RVA20S64 : RISCVProfile<"rva20s64", RVA20S64Features>; +def RVA22U64 : RISCVProfile<"rva22u64", RVA22U64Features>; +def RVA22S64 : RISCVProfile<"rva22s64", RVA22S64Features>; +def RVA23U64 : RISCVProfile<"rva23u64", RVA23U64Features>; +def RVA23S64 : RISCVProfile<"rva23s64", RVA23S64Features>; +def RVB23U64 : RISCVProfile<"rvb23u64", RVB23U64Features>; +def RVB23S64 : RISCVProfile<"rvb23s64", RVB23S64Features>; +def RVM23U32 : RISCVProfile<"rvm23u32", RVM23U32Features>; diff --git a/llvm/test/CodeGen/RISCV/attributes.ll b/llvm/test/CodeGen/RISCV/attributes.ll index 141d5ea41828..7bd3440c9dc0 100644 --- a/llvm/test/CodeGen/RISCV/attributes.ll +++ b/llvm/test/CodeGen/RISCV/attributes.ll @@ -256,6 +256,19 @@ ; RUN: llc -mtriple=riscv64 -mattr=+experimental-supm %s -o - | FileCheck --check-prefix=RV64SUPM %s ; RUN: llc -mtriple=riscv64 -mattr=+experimental-ssqosid %s -o - | FileCheck --check-prefix=RV64SSQOSID %s +; Tests for profile features. +; RUN: llc -mtriple=riscv32 -mattr=+rvi20u32 %s -o - | FileCheck --check-prefix=RVI20U32 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvi20u64 %s -o - | FileCheck --check-prefix=RVI20U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva20u64 %s -o - | FileCheck --check-prefix=RVA20U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva20s64 %s -o - | FileCheck --check-prefix=RVA20S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva22u64 %s -o - | FileCheck --check-prefix=RVA22U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva22s64 %s -o - | FileCheck --check-prefix=RVA22S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva23u64 %s -o - | FileCheck --check-prefix=RVA23U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rva23s64 %s -o - | FileCheck --check-prefix=RVA23S64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23u64 %s -o - | FileCheck --check-prefix=RVB23U64 %s +; RUN: llc -mtriple=riscv64 -mattr=+rvb23s64 %s -o - | FileCheck --check-prefix=RVB23S64 %s +; RUN: llc -mtriple=riscv32 -mattr=+rvm23u32 %s -o - | FileCheck --check-prefix=RVM23U32 %s + ; CHECK: .attribute 4, 16 ; RV32M: .attribute 5, "rv32i2p1_m2p0" @@ -512,6 +525,18 @@ ; RV64SUPM: .attribute 5, "rv64i2p1_supm0p8" ; RV64SSQOSID: .attribute 5, "rv64i2p1_ssqosid1p0" +; RVI20U32: .attribute 5, "rv32i2p1" +; RVI20U64: .attribute 5, "rv64i2p1" +; RVA20U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_za128rs1p0" +; RVA20S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_za128rs1p0_ssccptr1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0" +; RVA22U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVA22S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicsr2p0_zifencei2p0_zihintpause2p0_zihpm2p0_za64rs1p0_zfhmin1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscounterenw1p0_sstvala1p0_sstvecd1p0_svade1p0_svbare1p0_svinval1p0_svpbmt1p0" +; RVA23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0" +; RVA23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_v1p0_h1p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zfhmin1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_zvbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvfhmin1p0_zvkb1p0_zvkt1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0_shcounterenw1p0_shgatpa1p0_shtvala1p0_shvsatpa1p0_shvstvala1p0_shvstvecd1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_ssnpm0p8_ssstateen1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVB23U64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0" +; RVB23S64: .attribute 5, "rv64i2p1_m2p0_a2p1_f2p2_d2p2_c2p0_zic64b1p0_zicbom1p0_zicbop1p0_zicboz1p0_ziccamoa1p0_ziccif1p0_zicclsm1p0_ziccrse1p0_zicntr2p0_zicond1p0_zicsr2p0_zifencei2p0_zihintntl1p0_zihintpause2p0_zihpm2p0_zimop1p0_za64rs1p0_zawrs1p0_zfa1p0_zca1p0_zcb1p0_zcmop1p0_zba1p0_zbb1p0_zbs1p0_zkt1p0_ssccptr1p0_sscofpmf1p0_sscounterenw1p0_sstc1p0_sstvala1p0_sstvecd1p0_ssu64xl1p0_svade1p0_svbare1p0_svinval1p0_svnapot1p0_svpbmt1p0" +; RVM23U32: .attribute 5, "rv32i2p1_m2p0_zicbop1p0_zicond1p0_zicsr2p0_zihintntl1p0_zihintpause2p0_zimop1p0_zca1p0_zcb1p0_zce1p0_zcmop1p0_zcmp1p0_zcmt1p0_zba1p0_zbb1p0_zbs1p0" + define i32 @addi(i32 %a) { %1 = add i32 %a, 1 ret i32 %1 -- GitLab From c705c6847633ae3ef6711f911b829521463b24b4 Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Sun, 28 Apr 2024 11:52:36 +0800 Subject: [PATCH 144/301] [RISCV] Generate profiles from RISCVProfiles.td So we can only mantain one place. Reviewers: preames, yetingk, topperc Reviewed By: topperc Pull Request: https://github.com/llvm/llvm-project/pull/90187 --- llvm/lib/TargetParser/RISCVISAInfo.cpp | 37 +---------------- llvm/test/TableGen/riscv-target-def.td | 20 ++++++++++ llvm/utils/TableGen/RISCVTargetDefEmitter.cpp | 40 ++++++++++++++----- 3 files changed, 51 insertions(+), 46 deletions(-) diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 14d7c6ec8a4a..494dc76a1852 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -50,41 +50,8 @@ static const char *RISCVGImplications[] = { #define GET_SUPPORTED_EXTENSIONS #include "llvm/TargetParser/RISCVTargetParserDef.inc" -static constexpr RISCVProfile SupportedProfiles[] = { - {"rvi20u32", "rv32i"}, - {"rvi20u64", "rv64i"}, - {"rva20u64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_za128rs"}, - {"rva20s64", "rv64imafdc_ziccamoa_ziccif_zicclsm_ziccrse_zicntr_zifencei_" - "za128rs_ssccptr_sstvala_sstvecd_svade_svbare"}, - {"rva22u64", - "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt"}, - {"rva22s64", - "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zifencei_zihintpause_zihpm_za64rs_zfhmin_zba_zbb_zbs_zkt_ssccptr_" - "sscounterenw_sstvala_sstvecd_svade_svbare_svinval_svpbmt"}, - {"rva23u64", - "rv64imafdcv_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_zfa_zfhmin_" - "zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt"}, - {"rva23s64", - "rv64imafdcvh_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" - "zfa_zfhmin_zcb_zcmop_zba_zbb_zbs_zkt_zvbb_zvfhmin_zvkt_shcounterenw_" - "shgatpa_shtvala_shvsatpa_shvstvala_shvstvecd_ssccptr_sscofpmf_" - "sscounterenw_ssnpm0p8_ssstateen_sstc_sstvala_sstvecd_ssu64xl_svade_" - "svbare_svinval_svnapot_svpbmt"}, - {"rvb23u64", "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_" - "zicclsm_ziccrse_zicntr_zicond_zihintntl_zihintpause_zihpm_" - "zimop_za64rs_zawrs_zfa_zcb_zcmop_zba_zbb_zbs_zkt"}, - {"rvb23s64", - "rv64imafdc_zic64b_zicbom_zicbop_zicboz_ziccamoa_ziccif_zicclsm_ziccrse_" - "zicntr_zicond_zifencei_zihintntl_zihintpause_zihpm_zimop_za64rs_zawrs_" - "zfa_zcb_zcmop_zba_zbb_zbs_zkt_ssccptr_sscofpmf_sscounterenw_sstc_sstvala_" - "sstvecd_ssu64xl_svade_svbare_svinval_svnapot_svpbmt"}, - {"rvm23u32", "rv32im_zicbop_zicond_zicsr_zihintntl_zihintpause_zimop_zca_" - "zcb_zce_zcmop_zcmp_zcmt_zba_zbb_zbs"}, -}; +#define GET_SUPPORTED_PROFILES +#include "llvm/TargetParser/RISCVTargetParserDef.inc" static void verifyTables() { #ifndef NDEBUG diff --git a/llvm/test/TableGen/riscv-target-def.td b/llvm/test/TableGen/riscv-target-def.td index 865179fb79a6..7f3d9bdb278c 100644 --- a/llvm/test/TableGen/riscv-target-def.td +++ b/llvm/test/TableGen/riscv-target-def.td @@ -51,6 +51,15 @@ def Feature64Bit def FeatureDummy : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">; +class RISCVProfile features> + : SubtargetFeature; + +def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>; +def RVI20U64 : RISCVProfile<"rvi20u64", [Feature64Bit, FeatureStdExtI]>; +def ProfileDummy : RISCVProfile<"dummy", [Feature64Bit, FeatureStdExtI, + FeatureStdExtF, FeatureStdExtZidummy]>; + class RISCVProcessorModel f, @@ -121,6 +130,17 @@ def ROCKET : RISCVTuneProcessorModel<"rocket", // CHECK: #endif // GET_IMPLIED_EXTENSIONS +// CHECK: #ifdef GET_SUPPORTED_PROFILES +// CHECK-NEXT: #undef GET_SUPPORTED_PROFILES + +// CHECK: static constexpr RISCVProfile SupportedProfiles[] = { +// CHECK-NEXT: {"dummy","rv64i2p1_f2p2_zidummy0p1"}, +// CHECK-NEXT: {"rvi20u32","rv32i2p1"}, +// CHECK-NEXT: {"rvi20u64","rv64i2p1"}, +// CHECK-NEXT: }; + +// CHECK: #endif // GET_SUPPORTED_PROFILES + // CHECK: #ifndef PROC // CHECK-NEXT: #define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS) // CHECK-NEXT: #endif diff --git a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp index 787d22f635d0..097e1deb3ed1 100644 --- a/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp +++ b/llvm/utils/TableGen/RISCVTargetDefEmitter.cpp @@ -89,12 +89,12 @@ static void emitRISCVExtensions(RecordKeeper &Records, raw_ostream &OS) { // // This is almost the same as RISCVFeatures::parseFeatureBits, except that we // get feature name from feature records instead of feature bits. -static void printMArch(raw_ostream &OS, const Record &Rec) { +static void printMArch(raw_ostream &OS, const std::vector &Features) { RISCVISAUtils::OrderedExtensionMap Extensions; unsigned XLen = 0; // Convert features to FeatureVector. - for (auto *Feature : Rec.getValueAsListOfDefs("Features")) { + for (auto *Feature : Features) { StringRef FeatureName = getExtensionName(Feature); if (Feature->isSubClassOf("RISCVExtension")) { unsigned Major = Feature->getValueAsInt("MajorVersion"); @@ -118,6 +118,23 @@ static void printMArch(raw_ostream &OS, const Record &Rec) { OS << LS << Ext.first << Ext.second.Major << 'p' << Ext.second.Minor; } +static void emitRISCVProfiles(RecordKeeper &Records, raw_ostream &OS) { + OS << "#ifdef GET_SUPPORTED_PROFILES\n"; + OS << "#undef GET_SUPPORTED_PROFILES\n\n"; + + OS << "static constexpr RISCVProfile SupportedProfiles[] = {\n"; + + for (const Record *Rec : Records.getAllDerivedDefinitions("RISCVProfile")) { + OS.indent(4) << "{\"" << Rec->getValueAsString("Name") << "\",\""; + printMArch(OS, Rec->getValueAsListOfDefs("Implies")); + OS << "\"},\n"; + } + + OS << "};\n\n"; + + OS << "#endif // GET_SUPPORTED_PROFILES\n\n"; +} + static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { OS << "#ifndef PROC\n" << "#define PROC(ENUM, NAME, DEFAULT_MARCH, FAST_UNALIGNED_ACCESS)\n" @@ -125,15 +142,15 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { // Iterate on all definition records. for (const Record *Rec : RK.getAllDerivedDefinitions("RISCVProcessorModel")) { - bool FastScalarUnalignedAccess = - any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) { - return Feature->getValueAsString("Name") == "unaligned-scalar-mem"; - }); + const std::vector &Features = + Rec->getValueAsListOfDefs("Features"); + bool FastScalarUnalignedAccess = any_of(Features, [&](auto &Feature) { + return Feature->getValueAsString("Name") == "unaligned-scalar-mem"; + }); - bool FastVectorUnalignedAccess = - any_of(Rec->getValueAsListOfDefs("Features"), [&](auto &Feature) { - return Feature->getValueAsString("Name") == "unaligned-vector-mem"; - }); + bool FastVectorUnalignedAccess = any_of(Features, [&](auto &Feature) { + return Feature->getValueAsString("Name") == "unaligned-vector-mem"; + }); bool FastUnalignedAccess = FastScalarUnalignedAccess && FastVectorUnalignedAccess; @@ -145,7 +162,7 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { // Compute MArch from features if we don't specify it. if (MArch.empty()) - printMArch(OS, *Rec); + printMArch(OS, Features); else OS << MArch; OS << "\"}, " << FastUnalignedAccess << ")\n"; @@ -167,6 +184,7 @@ static void emitRISCVProcs(RecordKeeper &RK, raw_ostream &OS) { static void EmitRISCVTargetDef(RecordKeeper &RK, raw_ostream &OS) { emitRISCVExtensions(RK, OS); + emitRISCVProfiles(RK, OS); emitRISCVProcs(RK, OS); } -- GitLab From 2c1c887c8e6baf39a58a2ec18a43ed4101422e2a Mon Sep 17 00:00:00 2001 From: Pengcheng Wang Date: Sun, 28 Apr 2024 12:04:09 +0800 Subject: [PATCH 145/301] [RISCV] Make fixed-point instructions commutable (#90035) This PR includes: * vsadd.vv/vsaddu.vv * vaadd.vv/vaaddu.vv * vsmul.vv --- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp | 5 + .../Target/RISCV/RISCVInstrInfoVPseudos.td | 29 +-- llvm/test/CodeGen/RISCV/rvv/commutable.ll | 173 ++++++++++++++++++ 3 files changed, 194 insertions(+), 13 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp index 3efd09aeae87..8cb9a40a98bc 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp +++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.cpp @@ -3132,6 +3132,11 @@ bool RISCVInstrInfo::findCommutedOpIndices(const MachineInstr &MI, case CASE_RVV_OPCODE_WIDEN(VWMACC_VV): case CASE_RVV_OPCODE_WIDEN(VWMACCU_VV): case CASE_RVV_OPCODE_UNMASK(VADC_VVM): + case CASE_RVV_OPCODE(VSADD_VV): + case CASE_RVV_OPCODE(VSADDU_VV): + case CASE_RVV_OPCODE(VAADD_VV): + case CASE_RVV_OPCODE(VAADDU_VV): + case CASE_RVV_OPCODE(VSMUL_VV): // Operands 2 and 3 are commutable. return fixCommutedOpIndices(SrcOpIdx1, SrcOpIdx2, 2, 3); case CASE_VFMA_SPLATS(FMADD): diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td index e9715b40adc0..fc60a9cc7cd3 100644 --- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td +++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td @@ -2146,8 +2146,9 @@ multiclass VPseudoBinaryRoundingMode { - let VLMul = MInfo.value, SEW=sew in { + int TargetConstraintType = 1, + bit Commutable = 0> { + let VLMul = MInfo.value, SEW=sew, isCommutable = Commutable in { defvar suffix = !if(sew, "_" # MInfo.MX # "_E" # sew, "_" # MInfo.MX); def suffix : VPseudoBinaryNoMaskRoundingMode; } -multiclass VPseudoBinaryV_VV_RM { - defm _VV : VPseudoBinaryRoundingMode; +multiclass VPseudoBinaryV_VV_RM { + defm _VV : VPseudoBinaryRoundingMode; } // Similar to VPseudoBinaryV_VV, but uses MxListF. @@ -2715,10 +2717,11 @@ multiclass VPseudoVGTR_VV_VX_VI } } -multiclass VPseudoVSALU_VV_VX_VI { +multiclass VPseudoVSALU_VV_VX_VI { foreach m = MxList in { defvar mx = m.MX; - defm "" : VPseudoBinaryV_VV, + defm "" : VPseudoBinaryV_VV, SchedBinary<"WriteVSALUV", "ReadVSALUV", "ReadVSALUX", mx, forceMergeOpRead=true>; defm "" : VPseudoBinaryV_VX, @@ -2788,7 +2791,7 @@ multiclass VPseudoVSALU_VV_VX { multiclass VPseudoVSMUL_VV_VX_RM { foreach m = MxList in { defvar mx = m.MX; - defm "" : VPseudoBinaryV_VV_RM, + defm "" : VPseudoBinaryV_VV_RM, SchedBinary<"WriteVSMulV", "ReadVSMulV", "ReadVSMulV", mx, forceMergeOpRead=true>; defm "" : VPseudoBinaryV_VX_RM, @@ -2797,10 +2800,10 @@ multiclass VPseudoVSMUL_VV_VX_RM { } } -multiclass VPseudoVAALU_VV_VX_RM { +multiclass VPseudoVAALU_VV_VX_RM { foreach m = MxList in { defvar mx = m.MX; - defm "" : VPseudoBinaryV_VV_RM, + defm "" : VPseudoBinaryV_VV_RM, SchedBinary<"WriteVAALUV", "ReadVAALUV", "ReadVAALUV", mx, forceMergeOpRead=true>; defm "" : VPseudoBinaryV_VX_RM, @@ -6448,8 +6451,8 @@ defm PseudoVMV_V : VPseudoUnaryVMV_V_X_I; // 12.1. Vector Single-Width Saturating Add and Subtract //===----------------------------------------------------------------------===// let Defs = [VXSAT], hasSideEffects = 1 in { - defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI; - defm PseudoVSADD : VPseudoVSALU_VV_VX_VI; + defm PseudoVSADDU : VPseudoVSALU_VV_VX_VI; + defm PseudoVSADD : VPseudoVSALU_VV_VX_VI; defm PseudoVSSUBU : VPseudoVSALU_VV_VX; defm PseudoVSSUB : VPseudoVSALU_VV_VX; } @@ -6457,8 +6460,8 @@ let Defs = [VXSAT], hasSideEffects = 1 in { //===----------------------------------------------------------------------===// // 12.2. Vector Single-Width Averaging Add and Subtract //===----------------------------------------------------------------------===// -defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM; -defm PseudoVAADD : VPseudoVAALU_VV_VX_RM; +defm PseudoVAADDU : VPseudoVAALU_VV_VX_RM; +defm PseudoVAADD : VPseudoVAALU_VV_VX_RM; defm PseudoVASUBU : VPseudoVAALU_VV_VX_RM; defm PseudoVASUB : VPseudoVAALU_VV_VX_RM; diff --git a/llvm/test/CodeGen/RISCV/rvv/commutable.ll b/llvm/test/CodeGen/RISCV/rvv/commutable.ll index b59df3b743cd..06a6327d3892 100644 --- a/llvm/test/CodeGen/RISCV/rvv/commutable.ll +++ b/llvm/test/CodeGen/RISCV/rvv/commutable.ll @@ -649,3 +649,176 @@ entry: ret %ret } +; vsadd.vv +declare @llvm.riscv.vsadd.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vsadd_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vsadd_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vsadd.vv v10, v8, v9 +; CHECK-NEXT: vsadd.vv v8, v9, v8 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vsadd.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vsadd.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vsadd.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vsadd_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vsadd_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vsadd.vv v10, v8, v9, v0.t +; CHECK-NEXT: vsadd.vv v8, v9, v8, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vsadd.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vsadd.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vsaddu.vv +declare @llvm.riscv.vsaddu.nxv1i64.nxv1i64(, , , iXLen); +define @commutable_vsaddu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vsaddu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vsaddu.vv v10, v8, v9 +; CHECK-NEXT: vsaddu.vv v8, v9, v8 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vsaddu.nxv1i64.nxv1i64( undef, %0, %1, iXLen %2) + %b = call @llvm.riscv.vsaddu.nxv1i64.nxv1i64( undef, %1, %0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vsaddu.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen); +define @commutable_vsaddu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vsaddu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: vsaddu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vsaddu.vv v8, v9, v8, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vsaddu.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vsaddu.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vaadd.vv +declare @llvm.riscv.vaadd.nxv1i64.nxv1i64(, , , iXLen, iXLen); +define @commutable_vaadd_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vaadd_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaadd.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vaadd.nxv1i64.nxv1i64( undef, %0, %1, iXLen 0, iXLen %2) + %b = call @llvm.riscv.vaadd.nxv1i64.nxv1i64( undef, %1, %0, iXLen 0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen, iXLen); +define @commutable_vaadd_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vaadd_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaadd.vv v10, v8, v9, v0.t +; CHECK-NEXT: vaadd.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen 0, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vaadd.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen 0, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vaaddu.vv +declare @llvm.riscv.vaaddu.nxv1i64.nxv1i64(, , , iXLen, iXLen); +define @commutable_vaaddu_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vaaddu_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v8, v8, v9 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v8, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vaaddu.nxv1i64.nxv1i64( undef, %0, %1, iXLen 0, iXLen %2) + %b = call @llvm.riscv.vaaddu.nxv1i64.nxv1i64( undef, %1, %0, iXLen 0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen, iXLen); +define @commutable_vaaddu_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vaaddu_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vaaddu.vv v10, v8, v9, v0.t +; CHECK-NEXT: vaaddu.vv v8, v8, v9, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen 0, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vaaddu.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen 0, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} + +; vsmul.vv +declare @llvm.riscv.vsmul.nxv1i64.nxv1i64(, , , iXLen, iXLen); +define @commutable_vsmul_vv( %0, %1, iXLen %2) nounwind { +; CHECK-LABEL: commutable_vsmul_vv: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsmul.vv v10, v8, v9 +; CHECK-NEXT: vsmul.vv v8, v9, v8 +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret +entry: + %a = call @llvm.riscv.vsmul.nxv1i64.nxv1i64( undef, %0, %1, iXLen 0, iXLen %2) + %b = call @llvm.riscv.vsmul.nxv1i64.nxv1i64( undef, %1, %0, iXLen 0, iXLen %2) + %ret = add %a, %b + ret %ret +} + +declare @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64(, , , , iXLen, iXLen, iXLen); +define @commutable_vsmul_vv_masked( %0, %1, %mask, iXLen %2) { +; CHECK-LABEL: commutable_vsmul_vv_masked: +; CHECK: # %bb.0: +; CHECK-NEXT: vsetvli zero, a0, e64, m1, ta, ma +; CHECK-NEXT: csrwi vxrm, 0 +; CHECK-NEXT: vsmul.vv v10, v8, v9, v0.t +; CHECK-NEXT: vsmul.vv v8, v9, v8, v0.t +; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma +; CHECK-NEXT: vadd.vv v8, v10, v8 +; CHECK-NEXT: ret + %a = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( undef, %0, %1, %mask, iXLen 0, iXLen %2, iXLen 1) + %b = call @llvm.riscv.vsmul.mask.nxv1i64.nxv1i64( undef, %1, %0, %mask, iXLen 0, iXLen %2, iXLen 1) + %ret = add %a, %b + ret %ret +} -- GitLab From 37eb9c9632fb5e82827d1a0559f2279e9a9f1969 Mon Sep 17 00:00:00 2001 From: Zhijin Zeng Date: Sun, 28 Apr 2024 13:28:14 +0800 Subject: [PATCH 146/301] [RISC-V][ISel] Remove redundant czero.eqz like 'czero.eqz a0, a0, a0' (#90208) In RISC-V ISel, the instruction `czero.eqz a0, a0, a0` is meaningless. This patch does the following folds in ISel: ``` czero_eqz x, (setcc x, 0, ne) -> x czero_nez x, (setcc x, 0, eq) -> x ``` --------- Signed-off-by: Zhijin Zeng --- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 22 ++-- llvm/test/CodeGen/RISCV/select.ll | 110 ++++++++++++++++++++ 2 files changed, 125 insertions(+), 7 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 539aa3525545..3ab9e7d69105 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -16164,23 +16164,31 @@ SDValue RISCVTargetLowering::PerformDAGCombine(SDNode *N, case ISD::SELECT: return performSELECTCombine(N, DAG, Subtarget); case RISCVISD::CZERO_EQZ: - case RISCVISD::CZERO_NEZ: + case RISCVISD::CZERO_NEZ: { + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); // czero_eq X, (xor Y, 1) -> czero_ne X, Y if Y is 0 or 1. // czero_ne X, (xor Y, 1) -> czero_eq X, Y if Y is 0 or 1. - if (N->getOperand(1).getOpcode() == ISD::XOR && - isOneConstant(N->getOperand(1).getOperand(1))) { - SDValue Cond = N->getOperand(1).getOperand(0); + if (RHS.getOpcode() == ISD::XOR && isOneConstant(RHS.getOperand(1))) { + SDValue Cond = RHS.getOperand(0); APInt Mask = APInt::getBitsSetFrom(Cond.getValueSizeInBits(), 1); if (DAG.MaskedValueIsZero(Cond, Mask)) { unsigned NewOpc = N->getOpcode() == RISCVISD::CZERO_EQZ ? RISCVISD::CZERO_NEZ : RISCVISD::CZERO_EQZ; - return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0), - N->getOperand(0), Cond); + return DAG.getNode(NewOpc, SDLoc(N), N->getValueType(0), LHS, Cond); } } + // czero_eqz x, (setcc x, 0, ne) -> x + // czero_nez x, (setcc x, 0, eq) -> x + if (RHS.getOpcode() == ISD::SETCC && isNullConstant(RHS.getOperand(1)) && + cast(RHS.getOperand(2))->get() == + (N->getOpcode() == RISCVISD::CZERO_EQZ ? ISD::CondCode::SETNE + : ISD::CondCode::SETEQ) && + LHS == RHS.getOperand(0)) + return LHS; return SDValue(); - + } case RISCVISD::SELECT_CC: { // Transform SDValue LHS = N->getOperand(0); diff --git a/llvm/test/CodeGen/RISCV/select.ll b/llvm/test/CodeGen/RISCV/select.ll index e07e52091e9e..ffbbe31412ed 100644 --- a/llvm/test/CodeGen/RISCV/select.ll +++ b/llvm/test/CodeGen/RISCV/select.ll @@ -1858,3 +1858,113 @@ define i32 @select_cst6(i1 zeroext %cond) { %ret = select i1 %cond, i32 2049, i32 2047 ret i32 %ret } + +@select_redundant_czero_eqz_data = global i32 0, align 4 + +define void @select_redundant_czero_eqz1(ptr %0, ptr %1) { +; RV32IM-LABEL: select_redundant_czero_eqz1: +; RV32IM: # %bb.0: # %entry +; RV32IM-NEXT: bnez a0, .LBB49_2 +; RV32IM-NEXT: # %bb.1: +; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) +; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) +; RV32IM-NEXT: .LBB49_2: # %entry +; RV32IM-NEXT: sw a0, 0(a1) +; RV32IM-NEXT: ret +; +; RV64IM-LABEL: select_redundant_czero_eqz1: +; RV64IM: # %bb.0: # %entry +; RV64IM-NEXT: bnez a0, .LBB49_2 +; RV64IM-NEXT: # %bb.1: +; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) +; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) +; RV64IM-NEXT: .LBB49_2: # %entry +; RV64IM-NEXT: sd a0, 0(a1) +; RV64IM-NEXT: ret +; +; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz1: +; RV64IMXVTCONDOPS: # %bb.0: # %entry +; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) +; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) +; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 +; RV64IMXVTCONDOPS-NEXT: or a0, a2, a0 +; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1) +; RV64IMXVTCONDOPS-NEXT: ret +; +; RV32IMZICOND-LABEL: select_redundant_czero_eqz1: +; RV32IMZICOND: # %bb.0: # %entry +; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) +; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) +; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 +; RV32IMZICOND-NEXT: or a0, a2, a0 +; RV32IMZICOND-NEXT: sw a0, 0(a1) +; RV32IMZICOND-NEXT: ret +; +; RV64IMZICOND-LABEL: select_redundant_czero_eqz1: +; RV64IMZICOND: # %bb.0: # %entry +; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) +; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) +; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 +; RV64IMZICOND-NEXT: or a0, a2, a0 +; RV64IMZICOND-NEXT: sd a0, 0(a1) +; RV64IMZICOND-NEXT: ret +entry: + %3 = icmp eq ptr %0, null + %4 = select i1 %3, ptr @select_redundant_czero_eqz_data, ptr %0 + store ptr %4, ptr %1, align 8 + ret void +} + +define void @select_redundant_czero_eqz2(ptr %0, ptr %1) { +; RV32IM-LABEL: select_redundant_czero_eqz2: +; RV32IM: # %bb.0: # %entry +; RV32IM-NEXT: bnez a0, .LBB50_2 +; RV32IM-NEXT: # %bb.1: # %entry +; RV32IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) +; RV32IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) +; RV32IM-NEXT: .LBB50_2: # %entry +; RV32IM-NEXT: sw a0, 0(a1) +; RV32IM-NEXT: ret +; +; RV64IM-LABEL: select_redundant_czero_eqz2: +; RV64IM: # %bb.0: # %entry +; RV64IM-NEXT: bnez a0, .LBB50_2 +; RV64IM-NEXT: # %bb.1: # %entry +; RV64IM-NEXT: lui a0, %hi(select_redundant_czero_eqz_data) +; RV64IM-NEXT: addi a0, a0, %lo(select_redundant_czero_eqz_data) +; RV64IM-NEXT: .LBB50_2: # %entry +; RV64IM-NEXT: sd a0, 0(a1) +; RV64IM-NEXT: ret +; +; RV64IMXVTCONDOPS-LABEL: select_redundant_czero_eqz2: +; RV64IMXVTCONDOPS: # %bb.0: # %entry +; RV64IMXVTCONDOPS-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) +; RV64IMXVTCONDOPS-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) +; RV64IMXVTCONDOPS-NEXT: vt.maskcn a2, a2, a0 +; RV64IMXVTCONDOPS-NEXT: or a0, a0, a2 +; RV64IMXVTCONDOPS-NEXT: sd a0, 0(a1) +; RV64IMXVTCONDOPS-NEXT: ret +; +; RV32IMZICOND-LABEL: select_redundant_czero_eqz2: +; RV32IMZICOND: # %bb.0: # %entry +; RV32IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) +; RV32IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) +; RV32IMZICOND-NEXT: czero.nez a2, a2, a0 +; RV32IMZICOND-NEXT: or a0, a0, a2 +; RV32IMZICOND-NEXT: sw a0, 0(a1) +; RV32IMZICOND-NEXT: ret +; +; RV64IMZICOND-LABEL: select_redundant_czero_eqz2: +; RV64IMZICOND: # %bb.0: # %entry +; RV64IMZICOND-NEXT: lui a2, %hi(select_redundant_czero_eqz_data) +; RV64IMZICOND-NEXT: addi a2, a2, %lo(select_redundant_czero_eqz_data) +; RV64IMZICOND-NEXT: czero.nez a2, a2, a0 +; RV64IMZICOND-NEXT: or a0, a0, a2 +; RV64IMZICOND-NEXT: sd a0, 0(a1) +; RV64IMZICOND-NEXT: ret +entry: + %3 = icmp ne ptr %0, null + %4 = select i1 %3, ptr %0, ptr @select_redundant_czero_eqz_data + store ptr %4, ptr %1, align 8 + ret void +} -- GitLab From 487967af82053cd08022635a2ff768385d936c80 Mon Sep 17 00:00:00 2001 From: Chuanqi Xu Date: Sun, 28 Apr 2024 15:16:07 +0800 Subject: [PATCH 147/301] [Modules] Don't replace local declarations with external declaration with lower visibility Close https://github.com/llvm/llvm-project/issues/88400 For the reproducer: ``` //--- header.h namespace N { template concept X = true; template class Y { public: template friend class Y; }; inline Y x; } //--- bar.cppm module; export module bar; namespace N { // To make sure N::Y won't get elided. using N::x; } //--- foo.cc // expected-no-diagnostics import bar; void y() { N::Y y{}; }; ``` it will crash. The root cause is that in `StoredDeclsList::replaceExternalDecls`, we will replace the existing declarations with external declarations. Then for the reproducer, the redecl chain for Y is like: ``` Y (Local) -> Y (Local, friend) -> Y (Imported) -> Y(Imported, friend) ``` Before the lookup, the stored lookup result is `Y(Local)` then we find `Y(Imported)`. And now we repalce `Y(Local)` with `Y(Imported)`. But `Y(Imported)` is not visible. So we tried to find if there is any redeclarations visible but we find `Y(Local, friend)`, then problem happens. The solution is try to avoid the replace to happen if the external declaration has lower visibility then we can always find the local declarations. This may help the lookup performance slightly. Also I found the implementation of `StoredDeclsList::replaceExternalDecls` is not efficiency. It has an `O(n*m)` complexities. But let's improve that in the future. --- .../include/clang/AST/DeclContextInternals.h | 8 ++- clang/test/Modules/pr88400.cppm | 61 +++++++++++++++++++ 2 files changed, 67 insertions(+), 2 deletions(-) create mode 100644 clang/test/Modules/pr88400.cppm diff --git a/clang/include/clang/AST/DeclContextInternals.h b/clang/include/clang/AST/DeclContextInternals.h index c4734ab57895..42cc677f8213 100644 --- a/clang/include/clang/AST/DeclContextInternals.h +++ b/clang/include/clang/AST/DeclContextInternals.h @@ -160,12 +160,16 @@ public: void replaceExternalDecls(ArrayRef Decls) { // Remove all declarations that are either external or are replaced with - // external declarations. + // external declarations with higher visibilities. erase_if([Decls](NamedDecl *ND) { if (ND->isFromASTFile()) return true; + // FIXME: Can we get rid of this loop completely? for (NamedDecl *D : Decls) - if (D->declarationReplaces(ND, /*IsKnownNewer=*/false)) + // Only replace the local declaration if the external declaration has + // higher visibilities. + if (D->getModuleOwnershipKind() <= ND->getModuleOwnershipKind() && + D->declarationReplaces(ND, /*IsKnownNewer=*/false)) return true; return false; }); diff --git a/clang/test/Modules/pr88400.cppm b/clang/test/Modules/pr88400.cppm new file mode 100644 index 000000000000..ff69137a0b90 --- /dev/null +++ b/clang/test/Modules/pr88400.cppm @@ -0,0 +1,61 @@ +// RUN: rm -rf %t +// RUN: mkdir -p %t +// RUN: split-file %s %t +// +// RUN: %clang_cc1 -std=c++20 %t/bar.cppm -emit-module-interface -o %t/bar.pcm +// RUN: %clang_cc1 -std=c++20 %t/foo.cc -fmodule-file=bar=%t/bar.pcm -fsyntax-only -verify +// RUN: %clang_cc1 -std=c++20 %t/bar.cc -fmodule-file=bar=%t/bar.pcm -fsyntax-only -verify +// +// RUN: %clang_cc1 -std=c++20 %t/bar.cppm -emit-reduced-module-interface -o %t/bar.pcm +// RUN: %clang_cc1 -std=c++20 %t/foo.cc -fmodule-file=bar=%t/bar.pcm -fsyntax-only -verify +// RUN: %clang_cc1 -std=c++20 %t/bar.cc -fmodule-file=bar=%t/bar.pcm -fsyntax-only -verify + +//--- header.h +#pragma once + +namespace N { + template + concept X = true; + + template + class Y { + public: + template + friend class Y; + }; + + inline Y x; +} + +//--- bar.cppm +module; + +#include "header.h" + +export module bar; + +namespace N { + // To make sure N::Y won't get elided. + using N::x; +} + +//--- foo.cc +// expected-no-diagnostics +#include "header.h" + +import bar; + +void y() { + N::Y y{}; +}; + +//--- bar.cc +// expected-no-diagnostics +import bar; + +#include "header.h" + +void y() { + N::Y y{}; +}; + -- GitLab From 5820ad92456dfb68bd964fb2bfa0fa783a5b99fe Mon Sep 17 00:00:00 2001 From: Piyou Chen Date: Sun, 28 Apr 2024 17:10:19 +0800 Subject: [PATCH 148/301] [NFC][RISCV] Keep AVLReg define instr inside VSETVLInfo (#89180) Currently, the vsetvli pass tracks the define instruction through `MRI->getVRegDef` due to the SSA form. This patch keeps the AVLReg DefMI within VSETVLInfo during construction. And replace `MRI->getVRegDef(AVLReg)` with `getAVLRegDefMI()`. This information is useful when vsetvli pass live in post-ra situation. The testcases don't change because the VReg always has a unique def in SSA. --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 95 ++++++++++---------- 1 file changed, 48 insertions(+), 47 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index c40b9031543f..b5fd508fa77d 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -156,7 +156,7 @@ static std::optional getEEWForLoadStore(const MachineInstr &MI) { } } -static bool isNonZeroLoadImmediate(MachineInstr &MI) { +static bool isNonZeroLoadImmediate(const MachineInstr &MI) { return MI.getOpcode() == RISCV::ADDI && MI.getOperand(1).isReg() && MI.getOperand(2).isImm() && MI.getOperand(1).getReg() == RISCV::X0 && @@ -454,8 +454,12 @@ DemandedFields getDemanded(const MachineInstr &MI, /// Defines the abstract state with which the forward dataflow models the /// values of the VL and VTYPE registers after insertion. class VSETVLIInfo { + struct AVLDef { + const MachineInstr *DefMI; + Register DefReg; + }; union { - Register AVLReg; + AVLDef AVLRegDef; unsigned AVLImm; }; @@ -490,9 +494,10 @@ public: void setUnknown() { State = Unknown; } bool isUnknown() const { return State == Unknown; } - void setAVLReg(Register Reg) { - assert(Reg.isVirtual()); - AVLReg = Reg; + void setAVLRegDef(const MachineInstr *DefMI, Register AVLReg) { + assert(DefMI && AVLReg.isVirtual()); + AVLRegDef.DefMI = DefMI; + AVLRegDef.DefReg = AVLReg; State = AVLIsReg; } @@ -510,20 +515,24 @@ public: bool hasAVLVLMAX() const { return State == AVLIsVLMAX; } bool hasAVLIgnored() const { return State == AVLIsIgnored; } Register getAVLReg() const { - assert(hasAVLReg()); - return AVLReg; + assert(hasAVLReg() && AVLRegDef.DefReg.isVirtual()); + return AVLRegDef.DefReg; } unsigned getAVLImm() const { assert(hasAVLImm()); return AVLImm; } + const MachineInstr &getAVLDefMI() const { + assert(hasAVLReg() && AVLRegDef.DefMI); + return *AVLRegDef.DefMI; + } void setAVL(VSETVLIInfo Info) { assert(Info.isValid()); if (Info.isUnknown()) setUnknown(); else if (Info.hasAVLReg()) - setAVLReg(Info.getAVLReg()); + setAVLRegDef(&Info.getAVLDefMI(), Info.getAVLReg()); else if (Info.hasAVLVLMAX()) setAVLVLMAX(); else if (Info.hasAVLIgnored()) @@ -539,14 +548,11 @@ public: bool getTailAgnostic() const { return TailAgnostic; } bool getMaskAgnostic() const { return MaskAgnostic; } - bool hasNonZeroAVL(const MachineRegisterInfo &MRI) const { + bool hasNonZeroAVL() const { if (hasAVLImm()) return getAVLImm() > 0; - if (hasAVLReg()) { - MachineInstr *MI = MRI.getUniqueVRegDef(getAVLReg()); - assert(MI); - return isNonZeroLoadImmediate(*MI); - } + if (hasAVLReg()) + return isNonZeroLoadImmediate(getAVLDefMI()); if (hasAVLVLMAX()) return true; if (hasAVLIgnored()) @@ -554,16 +560,16 @@ public: return false; } - bool hasEquallyZeroAVL(const VSETVLIInfo &Other, - const MachineRegisterInfo &MRI) const { + bool hasEquallyZeroAVL(const VSETVLIInfo &Other) const { if (hasSameAVL(Other)) return true; - return (hasNonZeroAVL(MRI) && Other.hasNonZeroAVL(MRI)); + return (hasNonZeroAVL() && Other.hasNonZeroAVL()); } bool hasSameAVL(const VSETVLIInfo &Other) const { if (hasAVLReg() && Other.hasAVLReg()) - return getAVLReg() == Other.getAVLReg(); + return getAVLDefMI().isIdenticalTo(Other.getAVLDefMI()) && + getAVLReg() == Other.getAVLReg(); if (hasAVLImm() && Other.hasAVLImm()) return getAVLImm() == Other.getAVLImm(); @@ -659,7 +665,7 @@ public: if (Used.VLAny && !(hasSameAVL(Require) && hasSameVLMAX(Require))) return false; - if (Used.VLZeroness && !hasEquallyZeroAVL(Require, MRI)) + if (Used.VLZeroness && !hasEquallyZeroAVL(Require)) return false; return hasCompatibleVTYPE(Used, Require); @@ -744,7 +750,7 @@ public: if (isUnknown()) OS << "unknown"; if (hasAVLReg()) - OS << "AVLReg=" << (unsigned)AVLReg; + OS << "AVLReg=" << (unsigned)getAVLReg(); if (hasAVLImm()) OS << "AVLImm=" << (unsigned)AVLImm; if (hasAVLVLMAX()) @@ -870,7 +876,8 @@ INITIALIZE_PASS(RISCVCoalesceVSETVLI, "riscv-coalesce-vsetvli", // Return a VSETVLIInfo representing the changes made by this VSETVLI or // VSETIVLI instruction. -static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) { +static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI, + const MachineRegisterInfo &MRI) { VSETVLIInfo NewInfo; if (MI.getOpcode() == RISCV::PseudoVSETIVLI) { NewInfo.setAVLImm(MI.getOperand(1).getImm()); @@ -883,7 +890,7 @@ static VSETVLIInfo getInfoForVSETVLI(const MachineInstr &MI) { if (AVLReg == RISCV::X0) NewInfo.setAVLVLMAX(); else - NewInfo.setAVLReg(AVLReg); + NewInfo.setAVLRegDef(MRI.getVRegDef(AVLReg), AVLReg); } NewInfo.setVTYPE(MI.getOperand(2).getImm()); @@ -955,7 +962,7 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, else InstrInfo.setAVLImm(Imm); } else { - InstrInfo.setAVLReg(VLOp.getReg()); + InstrInfo.setAVLRegDef(MRI->getVRegDef(VLOp.getReg()), VLOp.getReg()); } } else { assert(isScalarExtractInstr(MI)); @@ -976,10 +983,9 @@ static VSETVLIInfo computeInfoForInstr(const MachineInstr &MI, uint64_t TSFlags, // register AVLs to avoid extending live ranges without being sure we can // kill the original source reg entirely. if (InstrInfo.hasAVLReg()) { - MachineInstr *DefMI = MRI->getUniqueVRegDef(InstrInfo.getAVLReg()); - assert(DefMI); - if (isVectorConfigInstr(*DefMI)) { - VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(*DefMI); + const MachineInstr &DefMI = InstrInfo.getAVLDefMI(); + if (isVectorConfigInstr(DefMI)) { + VSETVLIInfo DefInstrInfo = getInfoForVSETVLI(DefMI, *MRI); if (DefInstrInfo.hasSameVLMAX(InstrInfo) && (DefInstrInfo.hasAVLImm() || DefInstrInfo.hasAVLVLMAX())) InstrInfo.setAVL(DefInstrInfo); @@ -1017,10 +1023,9 @@ void RISCVInsertVSETVLI::insertVSETVLI(MachineBasicBlock &MBB, // it has the same VLMAX we want and the last VL/VTYPE we observed is the // same, we can use the X0, X0 form. if (Info.hasSameVLMAX(PrevInfo) && Info.hasAVLReg()) { - MachineInstr *DefMI = MRI->getUniqueVRegDef(Info.getAVLReg()); - assert(DefMI); - if (isVectorConfigInstr(*DefMI)) { - VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI); + const MachineInstr &DefMI = Info.getAVLDefMI(); + if (isVectorConfigInstr(DefMI)) { + VSETVLIInfo DefInfo = getInfoForVSETVLI(DefMI, *MRI); if (DefInfo.hasSameAVL(PrevInfo) && DefInfo.hasSameVLMAX(PrevInfo)) { BuildMI(MBB, InsertPt, DL, TII->get(RISCV::PseudoVSETVLIX0)) .addReg(RISCV::X0, RegState::Define | RegState::Dead) @@ -1136,10 +1141,9 @@ bool RISCVInsertVSETVLI::needVSETVLI(const MachineInstr &MI, // and the last VL/VTYPE we observed is the same, we don't need a // VSETVLI here. if (Require.hasAVLReg() && CurInfo.hasCompatibleVTYPE(Used, Require)) { - MachineInstr *DefMI = MRI->getUniqueVRegDef(Require.getAVLReg()); - assert(DefMI); - if (isVectorConfigInstr(*DefMI)) { - VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI); + const MachineInstr &DefMI = Require.getAVLDefMI(); + if (isVectorConfigInstr(DefMI)) { + VSETVLIInfo DefInfo = getInfoForVSETVLI(DefMI, *MRI); if (DefInfo.hasSameAVL(CurInfo) && DefInfo.hasSameVLMAX(CurInfo)) return false; } @@ -1194,7 +1198,7 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, // variant, so we avoid the transform to prevent extending live range of an // avl register operand. // TODO: We can probably relax this for immediates. - bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo, *MRI) && + bool EquallyZero = IncomingInfo.hasEquallyZeroAVL(PrevInfo) && IncomingInfo.hasSameVLMAX(PrevInfo); if (Demanded.VLAny || (Demanded.VLZeroness && !EquallyZero)) Info.setAVL(IncomingInfo); @@ -1225,13 +1229,14 @@ void RISCVInsertVSETVLI::transferBefore(VSETVLIInfo &Info, void RISCVInsertVSETVLI::transferAfter(VSETVLIInfo &Info, const MachineInstr &MI) const { if (isVectorConfigInstr(MI)) { - Info = getInfoForVSETVLI(MI); + Info = getInfoForVSETVLI(MI, *MRI); return; } if (RISCV::isFaultFirstLoad(MI)) { // Update AVL to vl-output of the fault first load. - Info.setAVLReg(MI.getOperand(1).getReg()); + Info.setAVLRegDef(MRI->getVRegDef(MI.getOperand(1).getReg()), + MI.getOperand(1).getReg()); return; } @@ -1325,11 +1330,8 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require, if (!Require.hasAVLReg()) return true; - Register AVLReg = Require.getAVLReg(); - // We need the AVL to be produce by a PHI node in this basic block. - MachineInstr *PHI = MRI->getUniqueVRegDef(AVLReg); - assert(PHI); + const MachineInstr *PHI = &Require.getAVLDefMI(); if (PHI->getOpcode() != RISCV::PHI || PHI->getParent() != &MBB) return true; @@ -1346,7 +1348,7 @@ bool RISCVInsertVSETVLI::needVSETVLIPHI(const VSETVLIInfo &Require, // We found a VSET(I)VLI make sure it matches the output of the // predecessor block. - VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI); + VSETVLIInfo DefInfo = getInfoForVSETVLI(*DefMI, *MRI); if (DefInfo != PBBExit) return true; @@ -1500,8 +1502,7 @@ void RISCVInsertVSETVLI::doPRE(MachineBasicBlock &MBB) { // we need to prove the value is available at the point we're going // to insert the vsetvli at. if (AvailableInfo.hasAVLReg()) { - MachineInstr *AVLDefMI = MRI->getUniqueVRegDef(AvailableInfo.getAVLReg()); - assert(AVLDefMI); + const MachineInstr *AVLDefMI = &AvailableInfo.getAVLDefMI(); // This is an inline dominance check which covers the case of // UnavailablePred being the preheader of a loop. if (AVLDefMI->getParent() != UnavailablePred) @@ -1580,8 +1581,8 @@ static bool canMutatePriorConfig(const MachineInstr &PrevMI, if (Used.VLZeroness) { if (isVLPreservingConfig(PrevMI)) return false; - if (!getInfoForVSETVLI(PrevMI).hasEquallyZeroAVL(getInfoForVSETVLI(MI), - MRI)) + if (!getInfoForVSETVLI(PrevMI, MRI) + .hasEquallyZeroAVL(getInfoForVSETVLI(MI, MRI))) return false; } -- GitLab From 0a0f1f9f1db0546084e9a62ec370025ec23be8f2 Mon Sep 17 00:00:00 2001 From: Chen Zheng Date: Sun, 28 Apr 2024 05:34:07 -0400 Subject: [PATCH 149/301] [PPC]add DEBUG_COUNTER for PPCMIPeephole pass --- llvm/lib/Target/PowerPC/PPCMIPeephole.cpp | 14 +++ .../CodeGen/PowerPC/peephole-counter-XToI.mir | 85 +++++++++++++++++++ .../PowerPC/peephole-counter-perOp.mir | 74 ++++++++++++++++ 3 files changed, 173 insertions(+) create mode 100644 llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir create mode 100644 llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir diff --git a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp index 494e4b52a5b5..c6db8a7bbeb8 100644 --- a/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp +++ b/llvm/lib/Target/PowerPC/PPCMIPeephole.cpp @@ -45,6 +45,7 @@ #include "llvm/CodeGen/MachineRegisterInfo.h" #include "llvm/InitializePasses.h" #include "llvm/Support/Debug.h" +#include "llvm/Support/DebugCounter.h" using namespace llvm; @@ -95,6 +96,13 @@ static cl::opt cl::desc("enable optimization of conditional traps"), cl::init(false), cl::Hidden); +DEBUG_COUNTER( + PeepholeXToICounter, "ppc-xtoi-peephole", + "Controls whether PPC reg+reg to reg+imm peephole is performed on a MI"); + +DEBUG_COUNTER(PeepholePerOpCounter, "ppc-per-op-peephole", + "Controls whether PPC per opcode peephole is performed on a MI"); + namespace { struct PPCMIPeephole : public MachineFunctionPass { @@ -469,6 +477,9 @@ bool PPCMIPeephole::simplifyCode() { if (MI.isDebugInstr()) continue; + if (!DebugCounter::shouldExecute(PeepholeXToICounter)) + continue; + SmallSet RRToRIRegsToUpdate; if (!TII->convertToImmediateForm(MI, RRToRIRegsToUpdate)) continue; @@ -538,6 +549,9 @@ bool PPCMIPeephole::simplifyCode() { if (MI.isDebugInstr()) continue; + if (!DebugCounter::shouldExecute(PeepholePerOpCounter)) + continue; + // Per-opcode peepholes. switch (MI.getOpcode()) { diff --git a/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir new file mode 100644 index 000000000000..d8f2b08adaf2 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/peephole-counter-XToI.mir @@ -0,0 +1,85 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# REQUIRES: asserts +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=0,ppc-xtoi-peephole-count=8 \ +# RUN: | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=3,ppc-xtoi-peephole-count=2 \ +# RUN: | FileCheck %s --check-prefix=ONE-FIRSTSTORE +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=5,ppc-xtoi-peephole-count=2 \ +# RUN: | FileCheck %s --check-prefix=ONE-SECONDSTORE +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-xtoi-peephole-skip=3,ppc-xtoi-peephole-count=4 \ +# RUN: | FileCheck %s --check-prefix=TWO + +--- +name: foldDForm +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x3 + + ; ALL-LABEL: name: foldDForm + ; ALL: liveins: $x3 + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; ALL-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; ALL-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; ALL-NEXT: STD [[LI8_]], 160, [[COPY]] + ; ALL-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; ALL-NEXT: STD [[LI8_]], 176, [[COPY]] + ; ALL-NEXT: dead [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 176 + ; ALL-NEXT: STD killed [[LI8_]], 192, killed [[COPY]] + ; ALL-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-FIRSTSTORE-LABEL: name: foldDForm + ; ONE-FIRSTSTORE: liveins: $x3 + ; ONE-FIRSTSTORE-NEXT: {{ $}} + ; ONE-FIRSTSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; ONE-FIRSTSTORE-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; ONE-FIRSTSTORE-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 160, [[COPY]] + ; ONE-FIRSTSTORE-NEXT: [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; ONE-FIRSTSTORE-NEXT: STD [[LI8_]], 16, killed [[ADDI8_1]] + ; ONE-FIRSTSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176 + ; ONE-FIRSTSTORE-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]] + ; ONE-FIRSTSTORE-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-SECONDSTORE-LABEL: name: foldDForm + ; ONE-SECONDSTORE: liveins: $x3 + ; ONE-SECONDSTORE-NEXT: {{ $}} + ; ONE-SECONDSTORE-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; ONE-SECONDSTORE-NEXT: [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; ONE-SECONDSTORE-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 16, killed [[ADDI8_]] + ; ONE-SECONDSTORE-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; ONE-SECONDSTORE-NEXT: STD [[LI8_]], 176, [[COPY]] + ; ONE-SECONDSTORE-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176 + ; ONE-SECONDSTORE-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]] + ; ONE-SECONDSTORE-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; TWO-LABEL: name: foldDForm + ; TWO: liveins: $x3 + ; TWO-NEXT: {{ $}} + ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc_and_g8rc_nox0 = COPY killed $x3 + ; TWO-NEXT: dead [[ADDI8_:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 144 + ; TWO-NEXT: [[LI8_:%[0-9]+]]:g8rc = LI8 0 + ; TWO-NEXT: STD [[LI8_]], 160, [[COPY]] + ; TWO-NEXT: dead [[ADDI8_1:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 [[COPY]], 160 + ; TWO-NEXT: STD [[LI8_]], 176, [[COPY]] + ; TWO-NEXT: [[ADDI8_2:%[0-9]+]]:g8rc_and_g8rc_nox0 = ADDI8 killed [[COPY]], 176 + ; TWO-NEXT: STD killed [[LI8_]], 16, killed [[ADDI8_2]] + ; TWO-NEXT: BLR8 implicit $lr8, implicit $rm + %0:g8rc_and_g8rc_nox0 = COPY $x3 + %1:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 144 + %2:g8rc = LI8 0 + STD %2:g8rc, 16, %1:g8rc_and_g8rc_nox0 + %3:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 160 + STD %2:g8rc, 16, %3:g8rc_and_g8rc_nox0 + %4:g8rc_and_g8rc_nox0 = ADDI8 %0:g8rc_and_g8rc_nox0, 176 + STD killed %2:g8rc, 16, %4:g8rc_and_g8rc_nox0 + BLR8 implicit $lr8, implicit $rm +... diff --git a/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir b/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir new file mode 100644 index 000000000000..cf3ff291e26c --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/peephole-counter-perOp.mir @@ -0,0 +1,74 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 4 +# REQUIRES: asserts +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=0,ppc-per-op-peephole-count=6 \ +# RUN: | FileCheck %s --check-prefix=ALL +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=3,ppc-per-op-peephole-count=1 \ +# RUN: | FileCheck %s --check-prefix=ONE-FIRST-RLWINM +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=4,ppc-per-op-peephole-count=1 \ +# RUN: | FileCheck %s --check-prefix=ONE-SECOND-RLWINM +# RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -verify-machineinstrs \ +# RUN: -run-pass ppc-mi-peepholes %s -o - -debug-counter=ppc-per-op-peephole-skip=3,ppc-per-op-peephole-count=2 \ +# RUN: | FileCheck %s --check-prefix=TWO + +--- +name: testFoldRLWINM +#CHECK: name: testFoldRLWINM +tracksRegLiveness: true +body: | + bb.0.entry: + liveins: $x3 + ; ALL-LABEL: name: testFoldRLWINM + ; ALL: liveins: $x3 + ; ALL-NEXT: {{ $}} + ; ALL-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; ALL-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; ALL-NEXT: dead [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12 + ; ALL-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 11 + ; ALL-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 10 + ; ALL-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-FIRST-RLWINM-LABEL: name: testFoldRLWINM + ; ONE-FIRST-RLWINM: liveins: $x3 + ; ONE-FIRST-RLWINM-NEXT: {{ $}} + ; ONE-FIRST-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; ONE-FIRST-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; ONE-FIRST-RLWINM-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31 + ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 12 + ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 11 + ; ONE-FIRST-RLWINM-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10 + ; ONE-FIRST-RLWINM-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; ONE-SECOND-RLWINM-LABEL: name: testFoldRLWINM + ; ONE-SECOND-RLWINM: liveins: $x3 + ; ONE-SECOND-RLWINM-NEXT: {{ $}} + ; ONE-SECOND-RLWINM-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; ONE-SECOND-RLWINM-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; ONE-SECOND-RLWINM-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31 + ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[RLWINM]], 19, 0, 12 + ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 11 + ; ONE-SECOND-RLWINM-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10 + ; ONE-SECOND-RLWINM-NEXT: BLR8 implicit $lr8, implicit $rm + ; + ; TWO-LABEL: name: testFoldRLWINM + ; TWO: liveins: $x3 + ; TWO-NEXT: {{ $}} + ; TWO-NEXT: [[COPY:%[0-9]+]]:g8rc = COPY killed $x3 + ; TWO-NEXT: [[COPY1:%[0-9]+]]:gprc = COPY killed [[COPY]].sub_32 + ; TWO-NEXT: [[RLWINM:%[0-9]+]]:gprc = RLWINM [[COPY1]], 27, 5, 31 + ; TWO-NEXT: dead [[RLWINM1:%[0-9]+]]:gprc = RLWINM [[COPY1]], 14, 0, 12 + ; TWO-NEXT: dead [[RLWINM2:%[0-9]+]]:gprc = RLWINM killed [[COPY1]], 14, 0, 11 + ; TWO-NEXT: dead [[RLWINM3:%[0-9]+]]:gprc = RLWINM killed [[RLWINM]], 19, 0, 10 + ; TWO-NEXT: BLR8 implicit $lr8, implicit $rm + %0:g8rc = COPY $x3 + %1:gprc = COPY %0.sub_32:g8rc + %2:gprc = RLWINM %1:gprc, 27, 5, 31 + %3:gprc = RLWINM %2:gprc, 19, 0, 12 + %4:gprc = RLWINM %2:gprc, 19, 0, 11 + %5:gprc = RLWINM %2:gprc, 19, 0, 10 + BLR8 implicit $lr8, implicit $rm +... -- GitLab From e3dea5e3410fd6a1e549cfa7021c4f8652b36095 Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Sun, 28 Apr 2024 12:15:25 +0200 Subject: [PATCH 150/301] [libc++][format] Improves escaping performance. (#88533) The previous patch implemented - P2713R1 Escaping improvements in std::format - LWG3965 Incorrect example in [format.string.escaped] p3 for formatting of combining characters These changes were correct, but had a size and performance penalty. This patch improves the size and performance of the previous patch. The performance is still worse than before since the lookups may require two property lookups instead of one before implementing the paper. The changes give a tighter coupling between the Unicode data and the algorithm. Additional tests are added to notify about changes in future Unicode updates. Before ``` ----------------------------------------------------------------------- Benchmark Time CPU Iterations ----------------------------------------------------------------------- BM_ascii_escaped 110704 ns 110696 ns 6206 BM_unicode_escaped 101371 ns 101374 ns 6862 BM_cyrillic_escaped 63329 ns 63327 ns 11013 BM_japanese_escaped 41223 ns 41225 ns 16938 BM_emoji_escaped 111022 ns 111021 ns 6304 BM_ascii_escaped 112441 ns 112443 ns 6231 BM_unicode_escaped 102776 ns 102779 ns 6813 BM_cyrillic_escaped 58977 ns 58975 ns 11868 BM_japanese_escaped 36885 ns 36886 ns 18975 BM_emoji_escaped 115885 ns 115881 ns 6051 ``` The first change is to manually encode the entire last area and make a manual exception for the 240 excluded entries. This reduced the table from 1077 to 729 entries and gave the following benchmark results. ``` ----------------------------------------------------------------------- Benchmark Time CPU Iterations ----------------------------------------------------------------------- BM_ascii_escaped 104777 ns 104776 ns 6550 BM_unicode_escaped 96980 ns 96982 ns 7238 BM_cyrillic_escaped 60254 ns 60251 ns 11670 BM_japanese_escaped 44452 ns 44452 ns 15734 BM_emoji_escaped 104557 ns 104551 ns 6685 BM_ascii_escaped 107456 ns 107454 ns 6505 BM_unicode_escaped 96219 ns 96216 ns 7301 BM_cyrillic_escaped 56921 ns 56904 ns 12288 BM_japanese_escaped 39530 ns 39529 ns 17492 BM_emoji_escaped 108494 ns 108496 ns 6408 ``` An entry in the table can only contain 2048 code points. For larger ranges there are multiple entries split in chunks with a maximum size of 2048 entries. To encode the entire Unicode code point range 21 bits are required. The manual part starts at 0x323B0 this means all entries in the table fit in 18 bits. This allows to allocate 3 additional bits for the range. This allows entries to have 16384 elements. This range always avoids splitting the range in multiple chunks. This reduces the number of table elements from 729 to 711 and gives the following benchmark results. ``` ----------------------------------------------------------------------- Benchmark Time CPU Iterations ----------------------------------------------------------------------- BM_ascii_escaped 104289 ns 104289 ns 6619 BM_unicode_escaped 96682 ns 96681 ns 7215 BM_cyrillic_escaped 59673 ns 59673 ns 11732 BM_japanese_escaped 41983 ns 41982 ns 16646 BM_emoji_escaped 104119 ns 104120 ns 6683 BM_ascii_escaped 104503 ns 104505 ns 6693 BM_unicode_escaped 93426 ns 93423 ns 7489 BM_cyrillic_escaped 54858 ns 54859 ns 12742 BM_japanese_escaped 36385 ns 36384 ns 19259 BM_emoji_escaped 105608 ns 105610 ns 6592 ``` --- .../include/__format/escaped_output_table.h | 1821 +++++++---------- libcxx/include/format | 2 + .../format.string.std/escaped_output.pass.cpp | 102 + libcxx/utils/generate_escaped_output_table.py | 86 +- 4 files changed, 888 insertions(+), 1123 deletions(-) create mode 100644 libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp diff --git a/libcxx/include/__format/escaped_output_table.h b/libcxx/include/__format/escaped_output_table.h index a4c4c366cf24..6aa91c89defa 100644 --- a/libcxx/include/__format/escaped_output_table.h +++ b/libcxx/include/__format/escaped_output_table.h @@ -105,1110 +105,751 @@ namespace __escaped_output_table { /// table lacks a property, thus having more bits available for the size. /// /// The data has 2 values: -/// - bits [0, 10] The size of the range, allowing 2048 elements. -/// - bits [11, 31] The lower bound code point of the range. The upper bound of -/// the range is lower bound + size. -_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[1077] = { +/// - bits [0, 13] The size of the range, allowing 16384 elements. +/// - bits [14, 31] The lower bound code point of the range. The upper bound of +/// the range is lower bound + size. Note the code expects code units the fit +/// into 18 bits, instead of the 21 bits needed for the full Unicode range. +_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[711] = { 0x00000020 /* 00000000 - 00000020 [ 33] */, - 0x0003f821 /* 0000007f - 000000a0 [ 34] */, - 0x00056800 /* 000000ad - 000000ad [ 1] */, - 0x001bc001 /* 00000378 - 00000379 [ 2] */, - 0x001c0003 /* 00000380 - 00000383 [ 4] */, - 0x001c5800 /* 0000038b - 0000038b [ 1] */, - 0x001c6800 /* 0000038d - 0000038d [ 1] */, - 0x001d1000 /* 000003a2 - 000003a2 [ 1] */, - 0x00298000 /* 00000530 - 00000530 [ 1] */, - 0x002ab801 /* 00000557 - 00000558 [ 2] */, - 0x002c5801 /* 0000058b - 0000058c [ 2] */, - 0x002c8000 /* 00000590 - 00000590 [ 1] */, - 0x002e4007 /* 000005c8 - 000005cf [ 8] */, - 0x002f5803 /* 000005eb - 000005ee [ 4] */, - 0x002fa810 /* 000005f5 - 00000605 [ 17] */, - 0x0030e000 /* 0000061c - 0000061c [ 1] */, - 0x0036e800 /* 000006dd - 000006dd [ 1] */, - 0x00387001 /* 0000070e - 0000070f [ 2] */, - 0x003a5801 /* 0000074b - 0000074c [ 2] */, - 0x003d900d /* 000007b2 - 000007bf [ 14] */, - 0x003fd801 /* 000007fb - 000007fc [ 2] */, - 0x00417001 /* 0000082e - 0000082f [ 2] */, - 0x0041f800 /* 0000083f - 0000083f [ 1] */, - 0x0042e001 /* 0000085c - 0000085d [ 2] */, - 0x0042f800 /* 0000085f - 0000085f [ 1] */, - 0x00435804 /* 0000086b - 0000086f [ 5] */, - 0x00447808 /* 0000088f - 00000897 [ 9] */, - 0x00471000 /* 000008e2 - 000008e2 [ 1] */, - 0x004c2000 /* 00000984 - 00000984 [ 1] */, - 0x004c6801 /* 0000098d - 0000098e [ 2] */, - 0x004c8801 /* 00000991 - 00000992 [ 2] */, - 0x004d4800 /* 000009a9 - 000009a9 [ 1] */, - 0x004d8800 /* 000009b1 - 000009b1 [ 1] */, - 0x004d9802 /* 000009b3 - 000009b5 [ 3] */, - 0x004dd001 /* 000009ba - 000009bb [ 2] */, - 0x004e2801 /* 000009c5 - 000009c6 [ 2] */, - 0x004e4801 /* 000009c9 - 000009ca [ 2] */, - 0x004e7807 /* 000009cf - 000009d6 [ 8] */, - 0x004ec003 /* 000009d8 - 000009db [ 4] */, - 0x004ef000 /* 000009de - 000009de [ 1] */, - 0x004f2001 /* 000009e4 - 000009e5 [ 2] */, - 0x004ff801 /* 000009ff - 00000a00 [ 2] */, - 0x00502000 /* 00000a04 - 00000a04 [ 1] */, - 0x00505803 /* 00000a0b - 00000a0e [ 4] */, - 0x00508801 /* 00000a11 - 00000a12 [ 2] */, - 0x00514800 /* 00000a29 - 00000a29 [ 1] */, - 0x00518800 /* 00000a31 - 00000a31 [ 1] */, - 0x0051a000 /* 00000a34 - 00000a34 [ 1] */, - 0x0051b800 /* 00000a37 - 00000a37 [ 1] */, - 0x0051d001 /* 00000a3a - 00000a3b [ 2] */, - 0x0051e800 /* 00000a3d - 00000a3d [ 1] */, - 0x00521803 /* 00000a43 - 00000a46 [ 4] */, - 0x00524801 /* 00000a49 - 00000a4a [ 2] */, - 0x00527002 /* 00000a4e - 00000a50 [ 3] */, - 0x00529006 /* 00000a52 - 00000a58 [ 7] */, - 0x0052e800 /* 00000a5d - 00000a5d [ 1] */, - 0x0052f806 /* 00000a5f - 00000a65 [ 7] */, - 0x0053b809 /* 00000a77 - 00000a80 [ 10] */, - 0x00542000 /* 00000a84 - 00000a84 [ 1] */, - 0x00547000 /* 00000a8e - 00000a8e [ 1] */, - 0x00549000 /* 00000a92 - 00000a92 [ 1] */, - 0x00554800 /* 00000aa9 - 00000aa9 [ 1] */, - 0x00558800 /* 00000ab1 - 00000ab1 [ 1] */, - 0x0055a000 /* 00000ab4 - 00000ab4 [ 1] */, - 0x0055d001 /* 00000aba - 00000abb [ 2] */, - 0x00563000 /* 00000ac6 - 00000ac6 [ 1] */, - 0x00565000 /* 00000aca - 00000aca [ 1] */, - 0x00567001 /* 00000ace - 00000acf [ 2] */, - 0x0056880e /* 00000ad1 - 00000adf [ 15] */, - 0x00572001 /* 00000ae4 - 00000ae5 [ 2] */, - 0x00579006 /* 00000af2 - 00000af8 [ 7] */, - 0x00580000 /* 00000b00 - 00000b00 [ 1] */, - 0x00582000 /* 00000b04 - 00000b04 [ 1] */, - 0x00586801 /* 00000b0d - 00000b0e [ 2] */, - 0x00588801 /* 00000b11 - 00000b12 [ 2] */, - 0x00594800 /* 00000b29 - 00000b29 [ 1] */, - 0x00598800 /* 00000b31 - 00000b31 [ 1] */, - 0x0059a000 /* 00000b34 - 00000b34 [ 1] */, - 0x0059d001 /* 00000b3a - 00000b3b [ 2] */, - 0x005a2801 /* 00000b45 - 00000b46 [ 2] */, - 0x005a4801 /* 00000b49 - 00000b4a [ 2] */, - 0x005a7006 /* 00000b4e - 00000b54 [ 7] */, - 0x005ac003 /* 00000b58 - 00000b5b [ 4] */, - 0x005af000 /* 00000b5e - 00000b5e [ 1] */, - 0x005b2001 /* 00000b64 - 00000b65 [ 2] */, - 0x005bc009 /* 00000b78 - 00000b81 [ 10] */, - 0x005c2000 /* 00000b84 - 00000b84 [ 1] */, - 0x005c5802 /* 00000b8b - 00000b8d [ 3] */, - 0x005c8800 /* 00000b91 - 00000b91 [ 1] */, - 0x005cb002 /* 00000b96 - 00000b98 [ 3] */, - 0x005cd800 /* 00000b9b - 00000b9b [ 1] */, - 0x005ce800 /* 00000b9d - 00000b9d [ 1] */, - 0x005d0002 /* 00000ba0 - 00000ba2 [ 3] */, - 0x005d2802 /* 00000ba5 - 00000ba7 [ 3] */, - 0x005d5802 /* 00000bab - 00000bad [ 3] */, - 0x005dd003 /* 00000bba - 00000bbd [ 4] */, - 0x005e1802 /* 00000bc3 - 00000bc5 [ 3] */, - 0x005e4800 /* 00000bc9 - 00000bc9 [ 1] */, - 0x005e7001 /* 00000bce - 00000bcf [ 2] */, - 0x005e8805 /* 00000bd1 - 00000bd6 [ 6] */, - 0x005ec00d /* 00000bd8 - 00000be5 [ 14] */, - 0x005fd804 /* 00000bfb - 00000bff [ 5] */, - 0x00606800 /* 00000c0d - 00000c0d [ 1] */, - 0x00608800 /* 00000c11 - 00000c11 [ 1] */, - 0x00614800 /* 00000c29 - 00000c29 [ 1] */, - 0x0061d001 /* 00000c3a - 00000c3b [ 2] */, - 0x00622800 /* 00000c45 - 00000c45 [ 1] */, - 0x00624800 /* 00000c49 - 00000c49 [ 1] */, - 0x00627006 /* 00000c4e - 00000c54 [ 7] */, - 0x0062b800 /* 00000c57 - 00000c57 [ 1] */, - 0x0062d801 /* 00000c5b - 00000c5c [ 2] */, - 0x0062f001 /* 00000c5e - 00000c5f [ 2] */, - 0x00632001 /* 00000c64 - 00000c65 [ 2] */, - 0x00638006 /* 00000c70 - 00000c76 [ 7] */, - 0x00646800 /* 00000c8d - 00000c8d [ 1] */, - 0x00648800 /* 00000c91 - 00000c91 [ 1] */, - 0x00654800 /* 00000ca9 - 00000ca9 [ 1] */, - 0x0065a000 /* 00000cb4 - 00000cb4 [ 1] */, - 0x0065d001 /* 00000cba - 00000cbb [ 2] */, - 0x00662800 /* 00000cc5 - 00000cc5 [ 1] */, - 0x00664800 /* 00000cc9 - 00000cc9 [ 1] */, - 0x00667006 /* 00000cce - 00000cd4 [ 7] */, - 0x0066b805 /* 00000cd7 - 00000cdc [ 6] */, - 0x0066f800 /* 00000cdf - 00000cdf [ 1] */, - 0x00672001 /* 00000ce4 - 00000ce5 [ 2] */, - 0x00678000 /* 00000cf0 - 00000cf0 [ 1] */, - 0x0067a00b /* 00000cf4 - 00000cff [ 12] */, - 0x00686800 /* 00000d0d - 00000d0d [ 1] */, - 0x00688800 /* 00000d11 - 00000d11 [ 1] */, - 0x006a2800 /* 00000d45 - 00000d45 [ 1] */, - 0x006a4800 /* 00000d49 - 00000d49 [ 1] */, - 0x006a8003 /* 00000d50 - 00000d53 [ 4] */, - 0x006b2001 /* 00000d64 - 00000d65 [ 2] */, - 0x006c0000 /* 00000d80 - 00000d80 [ 1] */, - 0x006c2000 /* 00000d84 - 00000d84 [ 1] */, - 0x006cb802 /* 00000d97 - 00000d99 [ 3] */, - 0x006d9000 /* 00000db2 - 00000db2 [ 1] */, - 0x006de000 /* 00000dbc - 00000dbc [ 1] */, - 0x006df001 /* 00000dbe - 00000dbf [ 2] */, - 0x006e3802 /* 00000dc7 - 00000dc9 [ 3] */, - 0x006e5803 /* 00000dcb - 00000dce [ 4] */, - 0x006ea800 /* 00000dd5 - 00000dd5 [ 1] */, - 0x006eb800 /* 00000dd7 - 00000dd7 [ 1] */, - 0x006f0005 /* 00000de0 - 00000de5 [ 6] */, - 0x006f8001 /* 00000df0 - 00000df1 [ 2] */, - 0x006fa80b /* 00000df5 - 00000e00 [ 12] */, - 0x0071d803 /* 00000e3b - 00000e3e [ 4] */, - 0x0072e024 /* 00000e5c - 00000e80 [ 37] */, - 0x00741800 /* 00000e83 - 00000e83 [ 1] */, - 0x00742800 /* 00000e85 - 00000e85 [ 1] */, - 0x00745800 /* 00000e8b - 00000e8b [ 1] */, - 0x00752000 /* 00000ea4 - 00000ea4 [ 1] */, - 0x00753000 /* 00000ea6 - 00000ea6 [ 1] */, - 0x0075f001 /* 00000ebe - 00000ebf [ 2] */, - 0x00762800 /* 00000ec5 - 00000ec5 [ 1] */, - 0x00763800 /* 00000ec7 - 00000ec7 [ 1] */, - 0x00767800 /* 00000ecf - 00000ecf [ 1] */, - 0x0076d001 /* 00000eda - 00000edb [ 2] */, - 0x0077001f /* 00000ee0 - 00000eff [ 32] */, - 0x007a4000 /* 00000f48 - 00000f48 [ 1] */, - 0x007b6803 /* 00000f6d - 00000f70 [ 4] */, - 0x007cc000 /* 00000f98 - 00000f98 [ 1] */, - 0x007de800 /* 00000fbd - 00000fbd [ 1] */, - 0x007e6800 /* 00000fcd - 00000fcd [ 1] */, - 0x007ed824 /* 00000fdb - 00000fff [ 37] */, - 0x00863000 /* 000010c6 - 000010c6 [ 1] */, - 0x00864004 /* 000010c8 - 000010cc [ 5] */, - 0x00867001 /* 000010ce - 000010cf [ 2] */, - 0x00924800 /* 00001249 - 00001249 [ 1] */, - 0x00927001 /* 0000124e - 0000124f [ 2] */, - 0x0092b800 /* 00001257 - 00001257 [ 1] */, - 0x0092c800 /* 00001259 - 00001259 [ 1] */, - 0x0092f001 /* 0000125e - 0000125f [ 2] */, - 0x00944800 /* 00001289 - 00001289 [ 1] */, - 0x00947001 /* 0000128e - 0000128f [ 2] */, - 0x00958800 /* 000012b1 - 000012b1 [ 1] */, - 0x0095b001 /* 000012b6 - 000012b7 [ 2] */, - 0x0095f800 /* 000012bf - 000012bf [ 1] */, - 0x00960800 /* 000012c1 - 000012c1 [ 1] */, - 0x00963001 /* 000012c6 - 000012c7 [ 2] */, - 0x0096b800 /* 000012d7 - 000012d7 [ 1] */, - 0x00988800 /* 00001311 - 00001311 [ 1] */, - 0x0098b001 /* 00001316 - 00001317 [ 2] */, - 0x009ad801 /* 0000135b - 0000135c [ 2] */, - 0x009be802 /* 0000137d - 0000137f [ 3] */, - 0x009cd005 /* 0000139a - 0000139f [ 6] */, - 0x009fb001 /* 000013f6 - 000013f7 [ 2] */, - 0x009ff001 /* 000013fe - 000013ff [ 2] */, - 0x00b40000 /* 00001680 - 00001680 [ 1] */, - 0x00b4e802 /* 0000169d - 0000169f [ 3] */, - 0x00b7c806 /* 000016f9 - 000016ff [ 7] */, - 0x00b8b008 /* 00001716 - 0000171e [ 9] */, - 0x00b9b808 /* 00001737 - 0000173f [ 9] */, - 0x00baa00b /* 00001754 - 0000175f [ 12] */, - 0x00bb6800 /* 0000176d - 0000176d [ 1] */, - 0x00bb8800 /* 00001771 - 00001771 [ 1] */, - 0x00bba00b /* 00001774 - 0000177f [ 12] */, - 0x00bef001 /* 000017de - 000017df [ 2] */, - 0x00bf5005 /* 000017ea - 000017ef [ 6] */, - 0x00bfd005 /* 000017fa - 000017ff [ 6] */, - 0x00c07000 /* 0000180e - 0000180e [ 1] */, - 0x00c0d005 /* 0000181a - 0000181f [ 6] */, - 0x00c3c806 /* 00001879 - 0000187f [ 7] */, - 0x00c55804 /* 000018ab - 000018af [ 5] */, - 0x00c7b009 /* 000018f6 - 000018ff [ 10] */, - 0x00c8f800 /* 0000191f - 0000191f [ 1] */, - 0x00c96003 /* 0000192c - 0000192f [ 4] */, - 0x00c9e003 /* 0000193c - 0000193f [ 4] */, - 0x00ca0802 /* 00001941 - 00001943 [ 3] */, - 0x00cb7001 /* 0000196e - 0000196f [ 2] */, - 0x00cba80a /* 00001975 - 0000197f [ 11] */, - 0x00cd6003 /* 000019ac - 000019af [ 4] */, - 0x00ce5005 /* 000019ca - 000019cf [ 6] */, - 0x00ced802 /* 000019db - 000019dd [ 3] */, - 0x00d0e001 /* 00001a1c - 00001a1d [ 2] */, - 0x00d2f800 /* 00001a5f - 00001a5f [ 1] */, - 0x00d3e801 /* 00001a7d - 00001a7e [ 2] */, - 0x00d45005 /* 00001a8a - 00001a8f [ 6] */, - 0x00d4d005 /* 00001a9a - 00001a9f [ 6] */, - 0x00d57001 /* 00001aae - 00001aaf [ 2] */, - 0x00d67830 /* 00001acf - 00001aff [ 49] */, - 0x00da6802 /* 00001b4d - 00001b4f [ 3] */, - 0x00dbf800 /* 00001b7f - 00001b7f [ 1] */, - 0x00dfa007 /* 00001bf4 - 00001bfb [ 8] */, - 0x00e1c002 /* 00001c38 - 00001c3a [ 3] */, - 0x00e25002 /* 00001c4a - 00001c4c [ 3] */, - 0x00e44806 /* 00001c89 - 00001c8f [ 7] */, - 0x00e5d801 /* 00001cbb - 00001cbc [ 2] */, - 0x00e64007 /* 00001cc8 - 00001ccf [ 8] */, - 0x00e7d804 /* 00001cfb - 00001cff [ 5] */, - 0x00f8b001 /* 00001f16 - 00001f17 [ 2] */, - 0x00f8f001 /* 00001f1e - 00001f1f [ 2] */, - 0x00fa3001 /* 00001f46 - 00001f47 [ 2] */, - 0x00fa7001 /* 00001f4e - 00001f4f [ 2] */, - 0x00fac000 /* 00001f58 - 00001f58 [ 1] */, - 0x00fad000 /* 00001f5a - 00001f5a [ 1] */, - 0x00fae000 /* 00001f5c - 00001f5c [ 1] */, - 0x00faf000 /* 00001f5e - 00001f5e [ 1] */, - 0x00fbf001 /* 00001f7e - 00001f7f [ 2] */, - 0x00fda800 /* 00001fb5 - 00001fb5 [ 1] */, - 0x00fe2800 /* 00001fc5 - 00001fc5 [ 1] */, - 0x00fea001 /* 00001fd4 - 00001fd5 [ 2] */, - 0x00fee000 /* 00001fdc - 00001fdc [ 1] */, - 0x00ff8001 /* 00001ff0 - 00001ff1 [ 2] */, - 0x00ffa800 /* 00001ff5 - 00001ff5 [ 1] */, - 0x00fff810 /* 00001fff - 0000200f [ 17] */, - 0x01014007 /* 00002028 - 0000202f [ 8] */, - 0x0102f810 /* 0000205f - 0000206f [ 17] */, - 0x01039001 /* 00002072 - 00002073 [ 2] */, - 0x01047800 /* 0000208f - 0000208f [ 1] */, - 0x0104e802 /* 0000209d - 0000209f [ 3] */, - 0x0106080e /* 000020c1 - 000020cf [ 15] */, - 0x0107880e /* 000020f1 - 000020ff [ 15] */, - 0x010c6003 /* 0000218c - 0000218f [ 4] */, - 0x01213818 /* 00002427 - 0000243f [ 25] */, - 0x01225814 /* 0000244b - 0000245f [ 21] */, - 0x015ba001 /* 00002b74 - 00002b75 [ 2] */, - 0x015cb000 /* 00002b96 - 00002b96 [ 1] */, - 0x0167a004 /* 00002cf4 - 00002cf8 [ 5] */, - 0x01693000 /* 00002d26 - 00002d26 [ 1] */, - 0x01694004 /* 00002d28 - 00002d2c [ 5] */, - 0x01697001 /* 00002d2e - 00002d2f [ 2] */, - 0x016b4006 /* 00002d68 - 00002d6e [ 7] */, - 0x016b880d /* 00002d71 - 00002d7e [ 14] */, - 0x016cb808 /* 00002d97 - 00002d9f [ 9] */, - 0x016d3800 /* 00002da7 - 00002da7 [ 1] */, - 0x016d7800 /* 00002daf - 00002daf [ 1] */, - 0x016db800 /* 00002db7 - 00002db7 [ 1] */, - 0x016df800 /* 00002dbf - 00002dbf [ 1] */, - 0x016e3800 /* 00002dc7 - 00002dc7 [ 1] */, - 0x016e7800 /* 00002dcf - 00002dcf [ 1] */, - 0x016eb800 /* 00002dd7 - 00002dd7 [ 1] */, - 0x016ef800 /* 00002ddf - 00002ddf [ 1] */, - 0x0172f021 /* 00002e5e - 00002e7f [ 34] */, - 0x0174d000 /* 00002e9a - 00002e9a [ 1] */, - 0x0177a00b /* 00002ef4 - 00002eff [ 12] */, - 0x017eb019 /* 00002fd6 - 00002fef [ 26] */, - 0x01800000 /* 00003000 - 00003000 [ 1] */, - 0x01820000 /* 00003040 - 00003040 [ 1] */, - 0x0184b801 /* 00003097 - 00003098 [ 2] */, - 0x01880004 /* 00003100 - 00003104 [ 5] */, - 0x01898000 /* 00003130 - 00003130 [ 1] */, - 0x018c7800 /* 0000318f - 0000318f [ 1] */, - 0x018f200a /* 000031e4 - 000031ee [ 11] */, - 0x0190f800 /* 0000321f - 0000321f [ 1] */, - 0x05246802 /* 0000a48d - 0000a48f [ 3] */, - 0x05263808 /* 0000a4c7 - 0000a4cf [ 9] */, - 0x05316013 /* 0000a62c - 0000a63f [ 20] */, - 0x0537c007 /* 0000a6f8 - 0000a6ff [ 8] */, - 0x053e5804 /* 0000a7cb - 0000a7cf [ 5] */, - 0x053e9000 /* 0000a7d2 - 0000a7d2 [ 1] */, - 0x053ea000 /* 0000a7d4 - 0000a7d4 [ 1] */, - 0x053ed017 /* 0000a7da - 0000a7f1 [ 24] */, - 0x05416802 /* 0000a82d - 0000a82f [ 3] */, - 0x0541d005 /* 0000a83a - 0000a83f [ 6] */, - 0x0543c007 /* 0000a878 - 0000a87f [ 8] */, - 0x05463007 /* 0000a8c6 - 0000a8cd [ 8] */, - 0x0546d005 /* 0000a8da - 0000a8df [ 6] */, - 0x054aa00a /* 0000a954 - 0000a95e [ 11] */, - 0x054be802 /* 0000a97d - 0000a97f [ 3] */, - 0x054e7000 /* 0000a9ce - 0000a9ce [ 1] */, - 0x054ed003 /* 0000a9da - 0000a9dd [ 4] */, - 0x054ff800 /* 0000a9ff - 0000a9ff [ 1] */, - 0x0551b808 /* 0000aa37 - 0000aa3f [ 9] */, - 0x05527001 /* 0000aa4e - 0000aa4f [ 2] */, - 0x0552d001 /* 0000aa5a - 0000aa5b [ 2] */, - 0x05561817 /* 0000aac3 - 0000aada [ 24] */, - 0x0557b809 /* 0000aaf7 - 0000ab00 [ 10] */, - 0x05583801 /* 0000ab07 - 0000ab08 [ 2] */, - 0x05587801 /* 0000ab0f - 0000ab10 [ 2] */, - 0x0558b808 /* 0000ab17 - 0000ab1f [ 9] */, - 0x05593800 /* 0000ab27 - 0000ab27 [ 1] */, - 0x05597800 /* 0000ab2f - 0000ab2f [ 1] */, - 0x055b6003 /* 0000ab6c - 0000ab6f [ 4] */, - 0x055f7001 /* 0000abee - 0000abef [ 2] */, - 0x055fd005 /* 0000abfa - 0000abff [ 6] */, - 0x06bd200b /* 0000d7a4 - 0000d7af [ 12] */, - 0x06be3803 /* 0000d7c7 - 0000d7ca [ 4] */, - 0x06bfe7ff /* 0000d7fc - 0000dffb [ 2048] */, - 0x06ffe7ff /* 0000dffc - 0000e7fb [ 2048] */, - 0x073fe7ff /* 0000e7fc - 0000effb [ 2048] */, - 0x077fe7ff /* 0000effc - 0000f7fb [ 2048] */, - 0x07bfe103 /* 0000f7fc - 0000f8ff [ 260] */, - 0x07d37001 /* 0000fa6e - 0000fa6f [ 2] */, - 0x07d6d025 /* 0000fada - 0000faff [ 38] */, - 0x07d8380b /* 0000fb07 - 0000fb12 [ 12] */, - 0x07d8c004 /* 0000fb18 - 0000fb1c [ 5] */, - 0x07d9b800 /* 0000fb37 - 0000fb37 [ 1] */, - 0x07d9e800 /* 0000fb3d - 0000fb3d [ 1] */, - 0x07d9f800 /* 0000fb3f - 0000fb3f [ 1] */, - 0x07da1000 /* 0000fb42 - 0000fb42 [ 1] */, - 0x07da2800 /* 0000fb45 - 0000fb45 [ 1] */, - 0x07de180f /* 0000fbc3 - 0000fbd2 [ 16] */, - 0x07ec8001 /* 0000fd90 - 0000fd91 [ 2] */, - 0x07ee4006 /* 0000fdc8 - 0000fdce [ 7] */, - 0x07ee801f /* 0000fdd0 - 0000fdef [ 32] */, - 0x07f0d005 /* 0000fe1a - 0000fe1f [ 6] */, - 0x07f29800 /* 0000fe53 - 0000fe53 [ 1] */, - 0x07f33800 /* 0000fe67 - 0000fe67 [ 1] */, - 0x07f36003 /* 0000fe6c - 0000fe6f [ 4] */, - 0x07f3a800 /* 0000fe75 - 0000fe75 [ 1] */, - 0x07f7e803 /* 0000fefd - 0000ff00 [ 4] */, - 0x07fdf802 /* 0000ffbf - 0000ffc1 [ 3] */, - 0x07fe4001 /* 0000ffc8 - 0000ffc9 [ 2] */, - 0x07fe8001 /* 0000ffd0 - 0000ffd1 [ 2] */, - 0x07fec001 /* 0000ffd8 - 0000ffd9 [ 2] */, - 0x07fee802 /* 0000ffdd - 0000ffdf [ 3] */, - 0x07ff3800 /* 0000ffe7 - 0000ffe7 [ 1] */, - 0x07ff780c /* 0000ffef - 0000fffb [ 13] */, - 0x07fff001 /* 0000fffe - 0000ffff [ 2] */, - 0x08006000 /* 0001000c - 0001000c [ 1] */, - 0x08013800 /* 00010027 - 00010027 [ 1] */, - 0x0801d800 /* 0001003b - 0001003b [ 1] */, - 0x0801f000 /* 0001003e - 0001003e [ 1] */, - 0x08027001 /* 0001004e - 0001004f [ 2] */, - 0x0802f021 /* 0001005e - 0001007f [ 34] */, - 0x0807d804 /* 000100fb - 000100ff [ 5] */, - 0x08081803 /* 00010103 - 00010106 [ 4] */, - 0x0809a002 /* 00010134 - 00010136 [ 3] */, - 0x080c7800 /* 0001018f - 0001018f [ 1] */, - 0x080ce802 /* 0001019d - 0001019f [ 3] */, - 0x080d082e /* 000101a1 - 000101cf [ 47] */, - 0x080ff081 /* 000101fe - 0001027f [ 130] */, - 0x0814e802 /* 0001029d - 0001029f [ 3] */, - 0x0816880e /* 000102d1 - 000102df [ 15] */, - 0x0817e003 /* 000102fc - 000102ff [ 4] */, - 0x08192008 /* 00010324 - 0001032c [ 9] */, - 0x081a5804 /* 0001034b - 0001034f [ 5] */, - 0x081bd804 /* 0001037b - 0001037f [ 5] */, - 0x081cf000 /* 0001039e - 0001039e [ 1] */, - 0x081e2003 /* 000103c4 - 000103c7 [ 4] */, - 0x081eb029 /* 000103d6 - 000103ff [ 42] */, - 0x0824f001 /* 0001049e - 0001049f [ 2] */, - 0x08255005 /* 000104aa - 000104af [ 6] */, - 0x0826a003 /* 000104d4 - 000104d7 [ 4] */, - 0x0827e003 /* 000104fc - 000104ff [ 4] */, - 0x08294007 /* 00010528 - 0001052f [ 8] */, - 0x082b200a /* 00010564 - 0001056e [ 11] */, - 0x082bd800 /* 0001057b - 0001057b [ 1] */, - 0x082c5800 /* 0001058b - 0001058b [ 1] */, - 0x082c9800 /* 00010593 - 00010593 [ 1] */, - 0x082cb000 /* 00010596 - 00010596 [ 1] */, - 0x082d1000 /* 000105a2 - 000105a2 [ 1] */, - 0x082d9000 /* 000105b2 - 000105b2 [ 1] */, - 0x082dd000 /* 000105ba - 000105ba [ 1] */, - 0x082de842 /* 000105bd - 000105ff [ 67] */, - 0x0839b808 /* 00010737 - 0001073f [ 9] */, - 0x083ab009 /* 00010756 - 0001075f [ 10] */, - 0x083b4017 /* 00010768 - 0001077f [ 24] */, - 0x083c3000 /* 00010786 - 00010786 [ 1] */, - 0x083d8800 /* 000107b1 - 000107b1 [ 1] */, - 0x083dd844 /* 000107bb - 000107ff [ 69] */, - 0x08403001 /* 00010806 - 00010807 [ 2] */, - 0x08404800 /* 00010809 - 00010809 [ 1] */, - 0x0841b000 /* 00010836 - 00010836 [ 1] */, - 0x0841c802 /* 00010839 - 0001083b [ 3] */, - 0x0841e801 /* 0001083d - 0001083e [ 2] */, - 0x0842b000 /* 00010856 - 00010856 [ 1] */, - 0x0844f807 /* 0001089f - 000108a6 [ 8] */, - 0x0845802f /* 000108b0 - 000108df [ 48] */, - 0x08479800 /* 000108f3 - 000108f3 [ 1] */, - 0x0847b004 /* 000108f6 - 000108fa [ 5] */, - 0x0848e002 /* 0001091c - 0001091e [ 3] */, - 0x0849d004 /* 0001093a - 0001093e [ 5] */, - 0x084a003f /* 00010940 - 0001097f [ 64] */, - 0x084dc003 /* 000109b8 - 000109bb [ 4] */, - 0x084e8001 /* 000109d0 - 000109d1 [ 2] */, - 0x08502000 /* 00010a04 - 00010a04 [ 1] */, - 0x08503804 /* 00010a07 - 00010a0b [ 5] */, - 0x0850a000 /* 00010a14 - 00010a14 [ 1] */, - 0x0850c000 /* 00010a18 - 00010a18 [ 1] */, - 0x0851b001 /* 00010a36 - 00010a37 [ 2] */, - 0x0851d803 /* 00010a3b - 00010a3e [ 4] */, - 0x08524806 /* 00010a49 - 00010a4f [ 7] */, - 0x0852c806 /* 00010a59 - 00010a5f [ 7] */, - 0x0855001f /* 00010aa0 - 00010abf [ 32] */, - 0x08573803 /* 00010ae7 - 00010aea [ 4] */, - 0x0857b808 /* 00010af7 - 00010aff [ 9] */, - 0x0859b002 /* 00010b36 - 00010b38 [ 3] */, - 0x085ab001 /* 00010b56 - 00010b57 [ 2] */, - 0x085b9804 /* 00010b73 - 00010b77 [ 5] */, - 0x085c9006 /* 00010b92 - 00010b98 [ 7] */, - 0x085ce80b /* 00010b9d - 00010ba8 [ 12] */, - 0x085d804f /* 00010bb0 - 00010bff [ 80] */, - 0x08624836 /* 00010c49 - 00010c7f [ 55] */, - 0x0865980c /* 00010cb3 - 00010cbf [ 13] */, - 0x08679806 /* 00010cf3 - 00010cf9 [ 7] */, - 0x08694007 /* 00010d28 - 00010d2f [ 8] */, - 0x0869d125 /* 00010d3a - 00010e5f [ 294] */, - 0x0873f800 /* 00010e7f - 00010e7f [ 1] */, - 0x08755000 /* 00010eaa - 00010eaa [ 1] */, - 0x08757001 /* 00010eae - 00010eaf [ 2] */, - 0x0875904a /* 00010eb2 - 00010efc [ 75] */, - 0x08794007 /* 00010f28 - 00010f2f [ 8] */, - 0x087ad015 /* 00010f5a - 00010f6f [ 22] */, - 0x087c5025 /* 00010f8a - 00010faf [ 38] */, - 0x087e6013 /* 00010fcc - 00010fdf [ 20] */, - 0x087fb808 /* 00010ff7 - 00010fff [ 9] */, - 0x08827003 /* 0001104e - 00011051 [ 4] */, - 0x0883b008 /* 00011076 - 0001107e [ 9] */, - 0x0885e800 /* 000110bd - 000110bd [ 1] */, - 0x0886180c /* 000110c3 - 000110cf [ 13] */, - 0x08874806 /* 000110e9 - 000110ef [ 7] */, - 0x0887d005 /* 000110fa - 000110ff [ 6] */, - 0x0889a800 /* 00011135 - 00011135 [ 1] */, - 0x088a4007 /* 00011148 - 0001114f [ 8] */, - 0x088bb808 /* 00011177 - 0001117f [ 9] */, - 0x088f0000 /* 000111e0 - 000111e0 [ 1] */, - 0x088fa80a /* 000111f5 - 000111ff [ 11] */, - 0x08909000 /* 00011212 - 00011212 [ 1] */, - 0x0892103d /* 00011242 - 0001127f [ 62] */, - 0x08943800 /* 00011287 - 00011287 [ 1] */, - 0x08944800 /* 00011289 - 00011289 [ 1] */, - 0x08947000 /* 0001128e - 0001128e [ 1] */, - 0x0894f000 /* 0001129e - 0001129e [ 1] */, - 0x08955005 /* 000112aa - 000112af [ 6] */, - 0x08975804 /* 000112eb - 000112ef [ 5] */, - 0x0897d005 /* 000112fa - 000112ff [ 6] */, - 0x08982000 /* 00011304 - 00011304 [ 1] */, - 0x08986801 /* 0001130d - 0001130e [ 2] */, - 0x08988801 /* 00011311 - 00011312 [ 2] */, - 0x08994800 /* 00011329 - 00011329 [ 1] */, - 0x08998800 /* 00011331 - 00011331 [ 1] */, - 0x0899a000 /* 00011334 - 00011334 [ 1] */, - 0x0899d000 /* 0001133a - 0001133a [ 1] */, - 0x089a2801 /* 00011345 - 00011346 [ 2] */, - 0x089a4801 /* 00011349 - 0001134a [ 2] */, - 0x089a7001 /* 0001134e - 0001134f [ 2] */, - 0x089a8805 /* 00011351 - 00011356 [ 6] */, - 0x089ac004 /* 00011358 - 0001135c [ 5] */, - 0x089b2001 /* 00011364 - 00011365 [ 2] */, - 0x089b6802 /* 0001136d - 0001136f [ 3] */, - 0x089ba88a /* 00011375 - 000113ff [ 139] */, - 0x08a2e000 /* 0001145c - 0001145c [ 1] */, - 0x08a3101d /* 00011462 - 0001147f [ 30] */, - 0x08a64007 /* 000114c8 - 000114cf [ 8] */, - 0x08a6d0a5 /* 000114da - 0001157f [ 166] */, - 0x08adb001 /* 000115b6 - 000115b7 [ 2] */, - 0x08aef021 /* 000115de - 000115ff [ 34] */, - 0x08b2280a /* 00011645 - 0001164f [ 11] */, - 0x08b2d005 /* 0001165a - 0001165f [ 6] */, - 0x08b36812 /* 0001166d - 0001167f [ 19] */, - 0x08b5d005 /* 000116ba - 000116bf [ 6] */, - 0x08b65035 /* 000116ca - 000116ff [ 54] */, - 0x08b8d801 /* 0001171b - 0001171c [ 2] */, - 0x08b96003 /* 0001172c - 0001172f [ 4] */, - 0x08ba38b8 /* 00011747 - 000117ff [ 185] */, - 0x08c1e063 /* 0001183c - 0001189f [ 100] */, - 0x08c7980b /* 000118f3 - 000118fe [ 12] */, - 0x08c83801 /* 00011907 - 00011908 [ 2] */, - 0x08c85001 /* 0001190a - 0001190b [ 2] */, - 0x08c8a000 /* 00011914 - 00011914 [ 1] */, - 0x08c8b800 /* 00011917 - 00011917 [ 1] */, - 0x08c9b000 /* 00011936 - 00011936 [ 1] */, - 0x08c9c801 /* 00011939 - 0001193a [ 2] */, - 0x08ca3808 /* 00011947 - 0001194f [ 9] */, - 0x08cad045 /* 0001195a - 0001199f [ 70] */, - 0x08cd4001 /* 000119a8 - 000119a9 [ 2] */, - 0x08cec001 /* 000119d8 - 000119d9 [ 2] */, - 0x08cf281a /* 000119e5 - 000119ff [ 27] */, - 0x08d24007 /* 00011a48 - 00011a4f [ 8] */, - 0x08d5180c /* 00011aa3 - 00011aaf [ 13] */, - 0x08d7c806 /* 00011af9 - 00011aff [ 7] */, - 0x08d850f5 /* 00011b0a - 00011bff [ 246] */, - 0x08e04800 /* 00011c09 - 00011c09 [ 1] */, - 0x08e1b800 /* 00011c37 - 00011c37 [ 1] */, - 0x08e23009 /* 00011c46 - 00011c4f [ 10] */, - 0x08e36802 /* 00011c6d - 00011c6f [ 3] */, - 0x08e48001 /* 00011c90 - 00011c91 [ 2] */, - 0x08e54000 /* 00011ca8 - 00011ca8 [ 1] */, - 0x08e5b848 /* 00011cb7 - 00011cff [ 73] */, - 0x08e83800 /* 00011d07 - 00011d07 [ 1] */, - 0x08e85000 /* 00011d0a - 00011d0a [ 1] */, - 0x08e9b802 /* 00011d37 - 00011d39 [ 3] */, - 0x08e9d800 /* 00011d3b - 00011d3b [ 1] */, - 0x08e9f000 /* 00011d3e - 00011d3e [ 1] */, - 0x08ea4007 /* 00011d48 - 00011d4f [ 8] */, - 0x08ead005 /* 00011d5a - 00011d5f [ 6] */, - 0x08eb3000 /* 00011d66 - 00011d66 [ 1] */, - 0x08eb4800 /* 00011d69 - 00011d69 [ 1] */, - 0x08ec7800 /* 00011d8f - 00011d8f [ 1] */, - 0x08ec9000 /* 00011d92 - 00011d92 [ 1] */, - 0x08ecc806 /* 00011d99 - 00011d9f [ 7] */, - 0x08ed5135 /* 00011daa - 00011edf [ 310] */, - 0x08f7c806 /* 00011ef9 - 00011eff [ 7] */, - 0x08f88800 /* 00011f11 - 00011f11 [ 1] */, - 0x08f9d802 /* 00011f3b - 00011f3d [ 3] */, - 0x08fad055 /* 00011f5a - 00011faf [ 86] */, - 0x08fd880e /* 00011fb1 - 00011fbf [ 15] */, - 0x08ff900c /* 00011ff2 - 00011ffe [ 13] */, - 0x091cd065 /* 0001239a - 000123ff [ 102] */, - 0x09237800 /* 0001246f - 0001246f [ 1] */, - 0x0923a80a /* 00012475 - 0001247f [ 11] */, - 0x092a27ff /* 00012544 - 00012d43 [ 2048] */, - 0x096a224b /* 00012d44 - 00012f8f [ 588] */, - 0x097f980c /* 00012ff3 - 00012fff [ 13] */, - 0x09a1800f /* 00013430 - 0001343f [ 16] */, - 0x09a2b7ff /* 00013456 - 00013c55 [ 2048] */, - 0x09e2b7a9 /* 00013c56 - 000143ff [ 1962] */, - 0x0a323fff /* 00014647 - 00014e46 [ 2048] */, - 0x0a723fff /* 00014e47 - 00015646 [ 2048] */, - 0x0ab23fff /* 00015647 - 00015e46 [ 2048] */, - 0x0af23fff /* 00015e47 - 00016646 [ 2048] */, - 0x0b3239b8 /* 00016647 - 000167ff [ 441] */, - 0x0b51c806 /* 00016a39 - 00016a3f [ 7] */, - 0x0b52f800 /* 00016a5f - 00016a5f [ 1] */, - 0x0b535003 /* 00016a6a - 00016a6d [ 4] */, - 0x0b55f800 /* 00016abf - 00016abf [ 1] */, - 0x0b565005 /* 00016aca - 00016acf [ 6] */, - 0x0b577001 /* 00016aee - 00016aef [ 2] */, - 0x0b57b009 /* 00016af6 - 00016aff [ 10] */, - 0x0b5a3009 /* 00016b46 - 00016b4f [ 10] */, - 0x0b5ad000 /* 00016b5a - 00016b5a [ 1] */, - 0x0b5b1000 /* 00016b62 - 00016b62 [ 1] */, - 0x0b5bc004 /* 00016b78 - 00016b7c [ 5] */, - 0x0b5c82af /* 00016b90 - 00016e3f [ 688] */, - 0x0b74d864 /* 00016e9b - 00016eff [ 101] */, - 0x0b7a5803 /* 00016f4b - 00016f4e [ 4] */, - 0x0b7c4006 /* 00016f88 - 00016f8e [ 7] */, - 0x0b7d003f /* 00016fa0 - 00016fdf [ 64] */, - 0x0b7f280a /* 00016fe5 - 00016fef [ 11] */, - 0x0b7f900d /* 00016ff2 - 00016fff [ 14] */, - 0x0c3fc007 /* 000187f8 - 000187ff [ 8] */, - 0x0c66b029 /* 00018cd6 - 00018cff [ 42] */, - 0x0c684fff /* 00018d09 - 00019508 [ 2048] */, - 0x0ca84fff /* 00019509 - 00019d08 [ 2048] */, - 0x0ce84fff /* 00019d09 - 0001a508 [ 2048] */, - 0x0d284fff /* 0001a509 - 0001ad08 [ 2048] */, - 0x0d684ae6 /* 0001ad09 - 0001afef [ 743] */, - 0x0d7fa000 /* 0001aff4 - 0001aff4 [ 1] */, - 0x0d7fe000 /* 0001affc - 0001affc [ 1] */, - 0x0d7ff800 /* 0001afff - 0001afff [ 1] */, - 0x0d89180e /* 0001b123 - 0001b131 [ 15] */, - 0x0d89981c /* 0001b133 - 0001b14f [ 29] */, - 0x0d8a9801 /* 0001b153 - 0001b154 [ 2] */, - 0x0d8ab00d /* 0001b156 - 0001b163 [ 14] */, - 0x0d8b4007 /* 0001b168 - 0001b16f [ 8] */, - 0x0d97e7ff /* 0001b2fc - 0001bafb [ 2048] */, - 0x0dd7e103 /* 0001bafc - 0001bbff [ 260] */, - 0x0de35804 /* 0001bc6b - 0001bc6f [ 5] */, - 0x0de3e802 /* 0001bc7d - 0001bc7f [ 3] */, - 0x0de44806 /* 0001bc89 - 0001bc8f [ 7] */, - 0x0de4d001 /* 0001bc9a - 0001bc9b [ 2] */, - 0x0de507ff /* 0001bca0 - 0001c49f [ 2048] */, - 0x0e2507ff /* 0001c4a0 - 0001cc9f [ 2048] */, - 0x0e65025f /* 0001cca0 - 0001ceff [ 608] */, - 0x0e797001 /* 0001cf2e - 0001cf2f [ 2] */, - 0x0e7a3808 /* 0001cf47 - 0001cf4f [ 9] */, - 0x0e7e203b /* 0001cfc4 - 0001cfff [ 60] */, - 0x0e87b009 /* 0001d0f6 - 0001d0ff [ 10] */, - 0x0e893801 /* 0001d127 - 0001d128 [ 2] */, - 0x0e8b9807 /* 0001d173 - 0001d17a [ 8] */, - 0x0e8f5814 /* 0001d1eb - 0001d1ff [ 21] */, - 0x0e923079 /* 0001d246 - 0001d2bf [ 122] */, - 0x0e96a00b /* 0001d2d4 - 0001d2df [ 12] */, - 0x0e97a00b /* 0001d2f4 - 0001d2ff [ 12] */, - 0x0e9ab808 /* 0001d357 - 0001d35f [ 9] */, - 0x0e9bc886 /* 0001d379 - 0001d3ff [ 135] */, - 0x0ea2a800 /* 0001d455 - 0001d455 [ 1] */, - 0x0ea4e800 /* 0001d49d - 0001d49d [ 1] */, - 0x0ea50001 /* 0001d4a0 - 0001d4a1 [ 2] */, - 0x0ea51801 /* 0001d4a3 - 0001d4a4 [ 2] */, - 0x0ea53801 /* 0001d4a7 - 0001d4a8 [ 2] */, - 0x0ea56800 /* 0001d4ad - 0001d4ad [ 1] */, - 0x0ea5d000 /* 0001d4ba - 0001d4ba [ 1] */, - 0x0ea5e000 /* 0001d4bc - 0001d4bc [ 1] */, - 0x0ea62000 /* 0001d4c4 - 0001d4c4 [ 1] */, - 0x0ea83000 /* 0001d506 - 0001d506 [ 1] */, - 0x0ea85801 /* 0001d50b - 0001d50c [ 2] */, - 0x0ea8a800 /* 0001d515 - 0001d515 [ 1] */, - 0x0ea8e800 /* 0001d51d - 0001d51d [ 1] */, - 0x0ea9d000 /* 0001d53a - 0001d53a [ 1] */, - 0x0ea9f800 /* 0001d53f - 0001d53f [ 1] */, - 0x0eaa2800 /* 0001d545 - 0001d545 [ 1] */, - 0x0eaa3802 /* 0001d547 - 0001d549 [ 3] */, - 0x0eaa8800 /* 0001d551 - 0001d551 [ 1] */, - 0x0eb53001 /* 0001d6a6 - 0001d6a7 [ 2] */, - 0x0ebe6001 /* 0001d7cc - 0001d7cd [ 2] */, - 0x0ed4600e /* 0001da8c - 0001da9a [ 15] */, - 0x0ed50000 /* 0001daa0 - 0001daa0 [ 1] */, - 0x0ed5844f /* 0001dab0 - 0001deff [ 1104] */, - 0x0ef8f805 /* 0001df1f - 0001df24 [ 6] */, - 0x0ef958d4 /* 0001df2b - 0001dfff [ 213] */, - 0x0f003800 /* 0001e007 - 0001e007 [ 1] */, - 0x0f00c801 /* 0001e019 - 0001e01a [ 2] */, - 0x0f011000 /* 0001e022 - 0001e022 [ 1] */, - 0x0f012800 /* 0001e025 - 0001e025 [ 1] */, - 0x0f015804 /* 0001e02b - 0001e02f [ 5] */, - 0x0f037020 /* 0001e06e - 0001e08e [ 33] */, - 0x0f04806f /* 0001e090 - 0001e0ff [ 112] */, - 0x0f096802 /* 0001e12d - 0001e12f [ 3] */, - 0x0f09f001 /* 0001e13e - 0001e13f [ 2] */, - 0x0f0a5003 /* 0001e14a - 0001e14d [ 4] */, - 0x0f0a813f /* 0001e150 - 0001e28f [ 320] */, - 0x0f157810 /* 0001e2af - 0001e2bf [ 17] */, - 0x0f17d004 /* 0001e2fa - 0001e2fe [ 5] */, - 0x0f1801cf /* 0001e300 - 0001e4cf [ 464] */, - 0x0f27d2e5 /* 0001e4fa - 0001e7df [ 742] */, - 0x0f3f3800 /* 0001e7e7 - 0001e7e7 [ 1] */, - 0x0f3f6000 /* 0001e7ec - 0001e7ec [ 1] */, - 0x0f3f7800 /* 0001e7ef - 0001e7ef [ 1] */, - 0x0f3ff800 /* 0001e7ff - 0001e7ff [ 1] */, - 0x0f462801 /* 0001e8c5 - 0001e8c6 [ 2] */, - 0x0f46b828 /* 0001e8d7 - 0001e8ff [ 41] */, - 0x0f4a6003 /* 0001e94c - 0001e94f [ 4] */, - 0x0f4ad003 /* 0001e95a - 0001e95d [ 4] */, - 0x0f4b0310 /* 0001e960 - 0001ec70 [ 785] */, - 0x0f65a84b /* 0001ecb5 - 0001ed00 [ 76] */, - 0x0f69f0c1 /* 0001ed3e - 0001edff [ 194] */, - 0x0f702000 /* 0001ee04 - 0001ee04 [ 1] */, - 0x0f710000 /* 0001ee20 - 0001ee20 [ 1] */, - 0x0f711800 /* 0001ee23 - 0001ee23 [ 1] */, - 0x0f712801 /* 0001ee25 - 0001ee26 [ 2] */, - 0x0f714000 /* 0001ee28 - 0001ee28 [ 1] */, - 0x0f719800 /* 0001ee33 - 0001ee33 [ 1] */, - 0x0f71c000 /* 0001ee38 - 0001ee38 [ 1] */, - 0x0f71d000 /* 0001ee3a - 0001ee3a [ 1] */, - 0x0f71e005 /* 0001ee3c - 0001ee41 [ 6] */, - 0x0f721803 /* 0001ee43 - 0001ee46 [ 4] */, - 0x0f724000 /* 0001ee48 - 0001ee48 [ 1] */, - 0x0f725000 /* 0001ee4a - 0001ee4a [ 1] */, - 0x0f726000 /* 0001ee4c - 0001ee4c [ 1] */, - 0x0f728000 /* 0001ee50 - 0001ee50 [ 1] */, - 0x0f729800 /* 0001ee53 - 0001ee53 [ 1] */, - 0x0f72a801 /* 0001ee55 - 0001ee56 [ 2] */, - 0x0f72c000 /* 0001ee58 - 0001ee58 [ 1] */, - 0x0f72d000 /* 0001ee5a - 0001ee5a [ 1] */, - 0x0f72e000 /* 0001ee5c - 0001ee5c [ 1] */, - 0x0f72f000 /* 0001ee5e - 0001ee5e [ 1] */, - 0x0f730000 /* 0001ee60 - 0001ee60 [ 1] */, - 0x0f731800 /* 0001ee63 - 0001ee63 [ 1] */, - 0x0f732801 /* 0001ee65 - 0001ee66 [ 2] */, - 0x0f735800 /* 0001ee6b - 0001ee6b [ 1] */, - 0x0f739800 /* 0001ee73 - 0001ee73 [ 1] */, - 0x0f73c000 /* 0001ee78 - 0001ee78 [ 1] */, - 0x0f73e800 /* 0001ee7d - 0001ee7d [ 1] */, - 0x0f73f800 /* 0001ee7f - 0001ee7f [ 1] */, - 0x0f745000 /* 0001ee8a - 0001ee8a [ 1] */, - 0x0f74e004 /* 0001ee9c - 0001eea0 [ 5] */, - 0x0f752000 /* 0001eea4 - 0001eea4 [ 1] */, - 0x0f755000 /* 0001eeaa - 0001eeaa [ 1] */, - 0x0f75e033 /* 0001eebc - 0001eeef [ 52] */, - 0x0f77910d /* 0001eef2 - 0001efff [ 270] */, - 0x0f816003 /* 0001f02c - 0001f02f [ 4] */, - 0x0f84a00b /* 0001f094 - 0001f09f [ 12] */, - 0x0f857801 /* 0001f0af - 0001f0b0 [ 2] */, - 0x0f860000 /* 0001f0c0 - 0001f0c0 [ 1] */, - 0x0f868000 /* 0001f0d0 - 0001f0d0 [ 1] */, - 0x0f87b009 /* 0001f0f6 - 0001f0ff [ 10] */, - 0x0f8d7037 /* 0001f1ae - 0001f1e5 [ 56] */, - 0x0f90180c /* 0001f203 - 0001f20f [ 13] */, - 0x0f91e003 /* 0001f23c - 0001f23f [ 4] */, - 0x0f924806 /* 0001f249 - 0001f24f [ 7] */, - 0x0f92900d /* 0001f252 - 0001f25f [ 14] */, - 0x0f933099 /* 0001f266 - 0001f2ff [ 154] */, - 0x0fb6c003 /* 0001f6d8 - 0001f6db [ 4] */, - 0x0fb76802 /* 0001f6ed - 0001f6ef [ 3] */, - 0x0fb7e802 /* 0001f6fd - 0001f6ff [ 3] */, - 0x0fbbb803 /* 0001f777 - 0001f77a [ 4] */, - 0x0fbed005 /* 0001f7da - 0001f7df [ 6] */, - 0x0fbf6003 /* 0001f7ec - 0001f7ef [ 4] */, - 0x0fbf880e /* 0001f7f1 - 0001f7ff [ 15] */, - 0x0fc06003 /* 0001f80c - 0001f80f [ 4] */, - 0x0fc24007 /* 0001f848 - 0001f84f [ 8] */, - 0x0fc2d005 /* 0001f85a - 0001f85f [ 6] */, - 0x0fc44007 /* 0001f888 - 0001f88f [ 8] */, - 0x0fc57001 /* 0001f8ae - 0001f8af [ 2] */, - 0x0fc5904d /* 0001f8b2 - 0001f8ff [ 78] */, - 0x0fd2a00b /* 0001fa54 - 0001fa5f [ 12] */, - 0x0fd37001 /* 0001fa6e - 0001fa6f [ 2] */, - 0x0fd3e802 /* 0001fa7d - 0001fa7f [ 3] */, - 0x0fd44806 /* 0001fa89 - 0001fa8f [ 7] */, - 0x0fd5f000 /* 0001fabe - 0001fabe [ 1] */, - 0x0fd63007 /* 0001fac6 - 0001facd [ 8] */, - 0x0fd6e003 /* 0001fadc - 0001fadf [ 4] */, - 0x0fd74806 /* 0001fae9 - 0001faef [ 7] */, - 0x0fd7c806 /* 0001faf9 - 0001faff [ 7] */, - 0x0fdc9800 /* 0001fb93 - 0001fb93 [ 1] */, - 0x0fde5824 /* 0001fbcb - 0001fbef [ 37] */, - 0x0fdfd405 /* 0001fbfa - 0001ffff [ 1030] */, - 0x1537001f /* 0002a6e0 - 0002a6ff [ 32] */, - 0x15b9d005 /* 0002b73a - 0002b73f [ 6] */, - 0x15c0f001 /* 0002b81e - 0002b81f [ 2] */, - 0x1675100d /* 0002cea2 - 0002ceaf [ 14] */, - 0x175f080e /* 0002ebe1 - 0002ebef [ 15] */, - 0x1772f7ff /* 0002ee5e - 0002f65d [ 2048] */, - 0x17b2f1a1 /* 0002f65e - 0002f7ff [ 418] */, - 0x17d0f5e1 /* 0002fa1e - 0002ffff [ 1506] */, - 0x189a5804 /* 0003134b - 0003134f [ 5] */, - 0x191d87ff /* 000323b0 - 00032baf [ 2048] */, - 0x195d87ff /* 00032bb0 - 000333af [ 2048] */, - 0x199d87ff /* 000333b0 - 00033baf [ 2048] */, - 0x19dd87ff /* 00033bb0 - 000343af [ 2048] */, - 0x1a1d87ff /* 000343b0 - 00034baf [ 2048] */, - 0x1a5d87ff /* 00034bb0 - 000353af [ 2048] */, - 0x1a9d87ff /* 000353b0 - 00035baf [ 2048] */, - 0x1add87ff /* 00035bb0 - 000363af [ 2048] */, - 0x1b1d87ff /* 000363b0 - 00036baf [ 2048] */, - 0x1b5d87ff /* 00036bb0 - 000373af [ 2048] */, - 0x1b9d87ff /* 000373b0 - 00037baf [ 2048] */, - 0x1bdd87ff /* 00037bb0 - 000383af [ 2048] */, - 0x1c1d87ff /* 000383b0 - 00038baf [ 2048] */, - 0x1c5d87ff /* 00038bb0 - 000393af [ 2048] */, - 0x1c9d87ff /* 000393b0 - 00039baf [ 2048] */, - 0x1cdd87ff /* 00039bb0 - 0003a3af [ 2048] */, - 0x1d1d87ff /* 0003a3b0 - 0003abaf [ 2048] */, - 0x1d5d87ff /* 0003abb0 - 0003b3af [ 2048] */, - 0x1d9d87ff /* 0003b3b0 - 0003bbaf [ 2048] */, - 0x1ddd87ff /* 0003bbb0 - 0003c3af [ 2048] */, - 0x1e1d87ff /* 0003c3b0 - 0003cbaf [ 2048] */, - 0x1e5d87ff /* 0003cbb0 - 0003d3af [ 2048] */, - 0x1e9d87ff /* 0003d3b0 - 0003dbaf [ 2048] */, - 0x1edd87ff /* 0003dbb0 - 0003e3af [ 2048] */, - 0x1f1d87ff /* 0003e3b0 - 0003ebaf [ 2048] */, - 0x1f5d87ff /* 0003ebb0 - 0003f3af [ 2048] */, - 0x1f9d87ff /* 0003f3b0 - 0003fbaf [ 2048] */, - 0x1fdd87ff /* 0003fbb0 - 000403af [ 2048] */, - 0x201d87ff /* 000403b0 - 00040baf [ 2048] */, - 0x205d87ff /* 00040bb0 - 000413af [ 2048] */, - 0x209d87ff /* 000413b0 - 00041baf [ 2048] */, - 0x20dd87ff /* 00041bb0 - 000423af [ 2048] */, - 0x211d87ff /* 000423b0 - 00042baf [ 2048] */, - 0x215d87ff /* 00042bb0 - 000433af [ 2048] */, - 0x219d87ff /* 000433b0 - 00043baf [ 2048] */, - 0x21dd87ff /* 00043bb0 - 000443af [ 2048] */, - 0x221d87ff /* 000443b0 - 00044baf [ 2048] */, - 0x225d87ff /* 00044bb0 - 000453af [ 2048] */, - 0x229d87ff /* 000453b0 - 00045baf [ 2048] */, - 0x22dd87ff /* 00045bb0 - 000463af [ 2048] */, - 0x231d87ff /* 000463b0 - 00046baf [ 2048] */, - 0x235d87ff /* 00046bb0 - 000473af [ 2048] */, - 0x239d87ff /* 000473b0 - 00047baf [ 2048] */, - 0x23dd87ff /* 00047bb0 - 000483af [ 2048] */, - 0x241d87ff /* 000483b0 - 00048baf [ 2048] */, - 0x245d87ff /* 00048bb0 - 000493af [ 2048] */, - 0x249d87ff /* 000493b0 - 00049baf [ 2048] */, - 0x24dd87ff /* 00049bb0 - 0004a3af [ 2048] */, - 0x251d87ff /* 0004a3b0 - 0004abaf [ 2048] */, - 0x255d87ff /* 0004abb0 - 0004b3af [ 2048] */, - 0x259d87ff /* 0004b3b0 - 0004bbaf [ 2048] */, - 0x25dd87ff /* 0004bbb0 - 0004c3af [ 2048] */, - 0x261d87ff /* 0004c3b0 - 0004cbaf [ 2048] */, - 0x265d87ff /* 0004cbb0 - 0004d3af [ 2048] */, - 0x269d87ff /* 0004d3b0 - 0004dbaf [ 2048] */, - 0x26dd87ff /* 0004dbb0 - 0004e3af [ 2048] */, - 0x271d87ff /* 0004e3b0 - 0004ebaf [ 2048] */, - 0x275d87ff /* 0004ebb0 - 0004f3af [ 2048] */, - 0x279d87ff /* 0004f3b0 - 0004fbaf [ 2048] */, - 0x27dd87ff /* 0004fbb0 - 000503af [ 2048] */, - 0x281d87ff /* 000503b0 - 00050baf [ 2048] */, - 0x285d87ff /* 00050bb0 - 000513af [ 2048] */, - 0x289d87ff /* 000513b0 - 00051baf [ 2048] */, - 0x28dd87ff /* 00051bb0 - 000523af [ 2048] */, - 0x291d87ff /* 000523b0 - 00052baf [ 2048] */, - 0x295d87ff /* 00052bb0 - 000533af [ 2048] */, - 0x299d87ff /* 000533b0 - 00053baf [ 2048] */, - 0x29dd87ff /* 00053bb0 - 000543af [ 2048] */, - 0x2a1d87ff /* 000543b0 - 00054baf [ 2048] */, - 0x2a5d87ff /* 00054bb0 - 000553af [ 2048] */, - 0x2a9d87ff /* 000553b0 - 00055baf [ 2048] */, - 0x2add87ff /* 00055bb0 - 000563af [ 2048] */, - 0x2b1d87ff /* 000563b0 - 00056baf [ 2048] */, - 0x2b5d87ff /* 00056bb0 - 000573af [ 2048] */, - 0x2b9d87ff /* 000573b0 - 00057baf [ 2048] */, - 0x2bdd87ff /* 00057bb0 - 000583af [ 2048] */, - 0x2c1d87ff /* 000583b0 - 00058baf [ 2048] */, - 0x2c5d87ff /* 00058bb0 - 000593af [ 2048] */, - 0x2c9d87ff /* 000593b0 - 00059baf [ 2048] */, - 0x2cdd87ff /* 00059bb0 - 0005a3af [ 2048] */, - 0x2d1d87ff /* 0005a3b0 - 0005abaf [ 2048] */, - 0x2d5d87ff /* 0005abb0 - 0005b3af [ 2048] */, - 0x2d9d87ff /* 0005b3b0 - 0005bbaf [ 2048] */, - 0x2ddd87ff /* 0005bbb0 - 0005c3af [ 2048] */, - 0x2e1d87ff /* 0005c3b0 - 0005cbaf [ 2048] */, - 0x2e5d87ff /* 0005cbb0 - 0005d3af [ 2048] */, - 0x2e9d87ff /* 0005d3b0 - 0005dbaf [ 2048] */, - 0x2edd87ff /* 0005dbb0 - 0005e3af [ 2048] */, - 0x2f1d87ff /* 0005e3b0 - 0005ebaf [ 2048] */, - 0x2f5d87ff /* 0005ebb0 - 0005f3af [ 2048] */, - 0x2f9d87ff /* 0005f3b0 - 0005fbaf [ 2048] */, - 0x2fdd87ff /* 0005fbb0 - 000603af [ 2048] */, - 0x301d87ff /* 000603b0 - 00060baf [ 2048] */, - 0x305d87ff /* 00060bb0 - 000613af [ 2048] */, - 0x309d87ff /* 000613b0 - 00061baf [ 2048] */, - 0x30dd87ff /* 00061bb0 - 000623af [ 2048] */, - 0x311d87ff /* 000623b0 - 00062baf [ 2048] */, - 0x315d87ff /* 00062bb0 - 000633af [ 2048] */, - 0x319d87ff /* 000633b0 - 00063baf [ 2048] */, - 0x31dd87ff /* 00063bb0 - 000643af [ 2048] */, - 0x321d87ff /* 000643b0 - 00064baf [ 2048] */, - 0x325d87ff /* 00064bb0 - 000653af [ 2048] */, - 0x329d87ff /* 000653b0 - 00065baf [ 2048] */, - 0x32dd87ff /* 00065bb0 - 000663af [ 2048] */, - 0x331d87ff /* 000663b0 - 00066baf [ 2048] */, - 0x335d87ff /* 00066bb0 - 000673af [ 2048] */, - 0x339d87ff /* 000673b0 - 00067baf [ 2048] */, - 0x33dd87ff /* 00067bb0 - 000683af [ 2048] */, - 0x341d87ff /* 000683b0 - 00068baf [ 2048] */, - 0x345d87ff /* 00068bb0 - 000693af [ 2048] */, - 0x349d87ff /* 000693b0 - 00069baf [ 2048] */, - 0x34dd87ff /* 00069bb0 - 0006a3af [ 2048] */, - 0x351d87ff /* 0006a3b0 - 0006abaf [ 2048] */, - 0x355d87ff /* 0006abb0 - 0006b3af [ 2048] */, - 0x359d87ff /* 0006b3b0 - 0006bbaf [ 2048] */, - 0x35dd87ff /* 0006bbb0 - 0006c3af [ 2048] */, - 0x361d87ff /* 0006c3b0 - 0006cbaf [ 2048] */, - 0x365d87ff /* 0006cbb0 - 0006d3af [ 2048] */, - 0x369d87ff /* 0006d3b0 - 0006dbaf [ 2048] */, - 0x36dd87ff /* 0006dbb0 - 0006e3af [ 2048] */, - 0x371d87ff /* 0006e3b0 - 0006ebaf [ 2048] */, - 0x375d87ff /* 0006ebb0 - 0006f3af [ 2048] */, - 0x379d87ff /* 0006f3b0 - 0006fbaf [ 2048] */, - 0x37dd87ff /* 0006fbb0 - 000703af [ 2048] */, - 0x381d87ff /* 000703b0 - 00070baf [ 2048] */, - 0x385d87ff /* 00070bb0 - 000713af [ 2048] */, - 0x389d87ff /* 000713b0 - 00071baf [ 2048] */, - 0x38dd87ff /* 00071bb0 - 000723af [ 2048] */, - 0x391d87ff /* 000723b0 - 00072baf [ 2048] */, - 0x395d87ff /* 00072bb0 - 000733af [ 2048] */, - 0x399d87ff /* 000733b0 - 00073baf [ 2048] */, - 0x39dd87ff /* 00073bb0 - 000743af [ 2048] */, - 0x3a1d87ff /* 000743b0 - 00074baf [ 2048] */, - 0x3a5d87ff /* 00074bb0 - 000753af [ 2048] */, - 0x3a9d87ff /* 000753b0 - 00075baf [ 2048] */, - 0x3add87ff /* 00075bb0 - 000763af [ 2048] */, - 0x3b1d87ff /* 000763b0 - 00076baf [ 2048] */, - 0x3b5d87ff /* 00076bb0 - 000773af [ 2048] */, - 0x3b9d87ff /* 000773b0 - 00077baf [ 2048] */, - 0x3bdd87ff /* 00077bb0 - 000783af [ 2048] */, - 0x3c1d87ff /* 000783b0 - 00078baf [ 2048] */, - 0x3c5d87ff /* 00078bb0 - 000793af [ 2048] */, - 0x3c9d87ff /* 000793b0 - 00079baf [ 2048] */, - 0x3cdd87ff /* 00079bb0 - 0007a3af [ 2048] */, - 0x3d1d87ff /* 0007a3b0 - 0007abaf [ 2048] */, - 0x3d5d87ff /* 0007abb0 - 0007b3af [ 2048] */, - 0x3d9d87ff /* 0007b3b0 - 0007bbaf [ 2048] */, - 0x3ddd87ff /* 0007bbb0 - 0007c3af [ 2048] */, - 0x3e1d87ff /* 0007c3b0 - 0007cbaf [ 2048] */, - 0x3e5d87ff /* 0007cbb0 - 0007d3af [ 2048] */, - 0x3e9d87ff /* 0007d3b0 - 0007dbaf [ 2048] */, - 0x3edd87ff /* 0007dbb0 - 0007e3af [ 2048] */, - 0x3f1d87ff /* 0007e3b0 - 0007ebaf [ 2048] */, - 0x3f5d87ff /* 0007ebb0 - 0007f3af [ 2048] */, - 0x3f9d87ff /* 0007f3b0 - 0007fbaf [ 2048] */, - 0x3fdd87ff /* 0007fbb0 - 000803af [ 2048] */, - 0x401d87ff /* 000803b0 - 00080baf [ 2048] */, - 0x405d87ff /* 00080bb0 - 000813af [ 2048] */, - 0x409d87ff /* 000813b0 - 00081baf [ 2048] */, - 0x40dd87ff /* 00081bb0 - 000823af [ 2048] */, - 0x411d87ff /* 000823b0 - 00082baf [ 2048] */, - 0x415d87ff /* 00082bb0 - 000833af [ 2048] */, - 0x419d87ff /* 000833b0 - 00083baf [ 2048] */, - 0x41dd87ff /* 00083bb0 - 000843af [ 2048] */, - 0x421d87ff /* 000843b0 - 00084baf [ 2048] */, - 0x425d87ff /* 00084bb0 - 000853af [ 2048] */, - 0x429d87ff /* 000853b0 - 00085baf [ 2048] */, - 0x42dd87ff /* 00085bb0 - 000863af [ 2048] */, - 0x431d87ff /* 000863b0 - 00086baf [ 2048] */, - 0x435d87ff /* 00086bb0 - 000873af [ 2048] */, - 0x439d87ff /* 000873b0 - 00087baf [ 2048] */, - 0x43dd87ff /* 00087bb0 - 000883af [ 2048] */, - 0x441d87ff /* 000883b0 - 00088baf [ 2048] */, - 0x445d87ff /* 00088bb0 - 000893af [ 2048] */, - 0x449d87ff /* 000893b0 - 00089baf [ 2048] */, - 0x44dd87ff /* 00089bb0 - 0008a3af [ 2048] */, - 0x451d87ff /* 0008a3b0 - 0008abaf [ 2048] */, - 0x455d87ff /* 0008abb0 - 0008b3af [ 2048] */, - 0x459d87ff /* 0008b3b0 - 0008bbaf [ 2048] */, - 0x45dd87ff /* 0008bbb0 - 0008c3af [ 2048] */, - 0x461d87ff /* 0008c3b0 - 0008cbaf [ 2048] */, - 0x465d87ff /* 0008cbb0 - 0008d3af [ 2048] */, - 0x469d87ff /* 0008d3b0 - 0008dbaf [ 2048] */, - 0x46dd87ff /* 0008dbb0 - 0008e3af [ 2048] */, - 0x471d87ff /* 0008e3b0 - 0008ebaf [ 2048] */, - 0x475d87ff /* 0008ebb0 - 0008f3af [ 2048] */, - 0x479d87ff /* 0008f3b0 - 0008fbaf [ 2048] */, - 0x47dd87ff /* 0008fbb0 - 000903af [ 2048] */, - 0x481d87ff /* 000903b0 - 00090baf [ 2048] */, - 0x485d87ff /* 00090bb0 - 000913af [ 2048] */, - 0x489d87ff /* 000913b0 - 00091baf [ 2048] */, - 0x48dd87ff /* 00091bb0 - 000923af [ 2048] */, - 0x491d87ff /* 000923b0 - 00092baf [ 2048] */, - 0x495d87ff /* 00092bb0 - 000933af [ 2048] */, - 0x499d87ff /* 000933b0 - 00093baf [ 2048] */, - 0x49dd87ff /* 00093bb0 - 000943af [ 2048] */, - 0x4a1d87ff /* 000943b0 - 00094baf [ 2048] */, - 0x4a5d87ff /* 00094bb0 - 000953af [ 2048] */, - 0x4a9d87ff /* 000953b0 - 00095baf [ 2048] */, - 0x4add87ff /* 00095bb0 - 000963af [ 2048] */, - 0x4b1d87ff /* 000963b0 - 00096baf [ 2048] */, - 0x4b5d87ff /* 00096bb0 - 000973af [ 2048] */, - 0x4b9d87ff /* 000973b0 - 00097baf [ 2048] */, - 0x4bdd87ff /* 00097bb0 - 000983af [ 2048] */, - 0x4c1d87ff /* 000983b0 - 00098baf [ 2048] */, - 0x4c5d87ff /* 00098bb0 - 000993af [ 2048] */, - 0x4c9d87ff /* 000993b0 - 00099baf [ 2048] */, - 0x4cdd87ff /* 00099bb0 - 0009a3af [ 2048] */, - 0x4d1d87ff /* 0009a3b0 - 0009abaf [ 2048] */, - 0x4d5d87ff /* 0009abb0 - 0009b3af [ 2048] */, - 0x4d9d87ff /* 0009b3b0 - 0009bbaf [ 2048] */, - 0x4ddd87ff /* 0009bbb0 - 0009c3af [ 2048] */, - 0x4e1d87ff /* 0009c3b0 - 0009cbaf [ 2048] */, - 0x4e5d87ff /* 0009cbb0 - 0009d3af [ 2048] */, - 0x4e9d87ff /* 0009d3b0 - 0009dbaf [ 2048] */, - 0x4edd87ff /* 0009dbb0 - 0009e3af [ 2048] */, - 0x4f1d87ff /* 0009e3b0 - 0009ebaf [ 2048] */, - 0x4f5d87ff /* 0009ebb0 - 0009f3af [ 2048] */, - 0x4f9d87ff /* 0009f3b0 - 0009fbaf [ 2048] */, - 0x4fdd87ff /* 0009fbb0 - 000a03af [ 2048] */, - 0x501d87ff /* 000a03b0 - 000a0baf [ 2048] */, - 0x505d87ff /* 000a0bb0 - 000a13af [ 2048] */, - 0x509d87ff /* 000a13b0 - 000a1baf [ 2048] */, - 0x50dd87ff /* 000a1bb0 - 000a23af [ 2048] */, - 0x511d87ff /* 000a23b0 - 000a2baf [ 2048] */, - 0x515d87ff /* 000a2bb0 - 000a33af [ 2048] */, - 0x519d87ff /* 000a33b0 - 000a3baf [ 2048] */, - 0x51dd87ff /* 000a3bb0 - 000a43af [ 2048] */, - 0x521d87ff /* 000a43b0 - 000a4baf [ 2048] */, - 0x525d87ff /* 000a4bb0 - 000a53af [ 2048] */, - 0x529d87ff /* 000a53b0 - 000a5baf [ 2048] */, - 0x52dd87ff /* 000a5bb0 - 000a63af [ 2048] */, - 0x531d87ff /* 000a63b0 - 000a6baf [ 2048] */, - 0x535d87ff /* 000a6bb0 - 000a73af [ 2048] */, - 0x539d87ff /* 000a73b0 - 000a7baf [ 2048] */, - 0x53dd87ff /* 000a7bb0 - 000a83af [ 2048] */, - 0x541d87ff /* 000a83b0 - 000a8baf [ 2048] */, - 0x545d87ff /* 000a8bb0 - 000a93af [ 2048] */, - 0x549d87ff /* 000a93b0 - 000a9baf [ 2048] */, - 0x54dd87ff /* 000a9bb0 - 000aa3af [ 2048] */, - 0x551d87ff /* 000aa3b0 - 000aabaf [ 2048] */, - 0x555d87ff /* 000aabb0 - 000ab3af [ 2048] */, - 0x559d87ff /* 000ab3b0 - 000abbaf [ 2048] */, - 0x55dd87ff /* 000abbb0 - 000ac3af [ 2048] */, - 0x561d87ff /* 000ac3b0 - 000acbaf [ 2048] */, - 0x565d87ff /* 000acbb0 - 000ad3af [ 2048] */, - 0x569d87ff /* 000ad3b0 - 000adbaf [ 2048] */, - 0x56dd87ff /* 000adbb0 - 000ae3af [ 2048] */, - 0x571d87ff /* 000ae3b0 - 000aebaf [ 2048] */, - 0x575d87ff /* 000aebb0 - 000af3af [ 2048] */, - 0x579d87ff /* 000af3b0 - 000afbaf [ 2048] */, - 0x57dd87ff /* 000afbb0 - 000b03af [ 2048] */, - 0x581d87ff /* 000b03b0 - 000b0baf [ 2048] */, - 0x585d87ff /* 000b0bb0 - 000b13af [ 2048] */, - 0x589d87ff /* 000b13b0 - 000b1baf [ 2048] */, - 0x58dd87ff /* 000b1bb0 - 000b23af [ 2048] */, - 0x591d87ff /* 000b23b0 - 000b2baf [ 2048] */, - 0x595d87ff /* 000b2bb0 - 000b33af [ 2048] */, - 0x599d87ff /* 000b33b0 - 000b3baf [ 2048] */, - 0x59dd87ff /* 000b3bb0 - 000b43af [ 2048] */, - 0x5a1d87ff /* 000b43b0 - 000b4baf [ 2048] */, - 0x5a5d87ff /* 000b4bb0 - 000b53af [ 2048] */, - 0x5a9d87ff /* 000b53b0 - 000b5baf [ 2048] */, - 0x5add87ff /* 000b5bb0 - 000b63af [ 2048] */, - 0x5b1d87ff /* 000b63b0 - 000b6baf [ 2048] */, - 0x5b5d87ff /* 000b6bb0 - 000b73af [ 2048] */, - 0x5b9d87ff /* 000b73b0 - 000b7baf [ 2048] */, - 0x5bdd87ff /* 000b7bb0 - 000b83af [ 2048] */, - 0x5c1d87ff /* 000b83b0 - 000b8baf [ 2048] */, - 0x5c5d87ff /* 000b8bb0 - 000b93af [ 2048] */, - 0x5c9d87ff /* 000b93b0 - 000b9baf [ 2048] */, - 0x5cdd87ff /* 000b9bb0 - 000ba3af [ 2048] */, - 0x5d1d87ff /* 000ba3b0 - 000babaf [ 2048] */, - 0x5d5d87ff /* 000babb0 - 000bb3af [ 2048] */, - 0x5d9d87ff /* 000bb3b0 - 000bbbaf [ 2048] */, - 0x5ddd87ff /* 000bbbb0 - 000bc3af [ 2048] */, - 0x5e1d87ff /* 000bc3b0 - 000bcbaf [ 2048] */, - 0x5e5d87ff /* 000bcbb0 - 000bd3af [ 2048] */, - 0x5e9d87ff /* 000bd3b0 - 000bdbaf [ 2048] */, - 0x5edd87ff /* 000bdbb0 - 000be3af [ 2048] */, - 0x5f1d87ff /* 000be3b0 - 000bebaf [ 2048] */, - 0x5f5d87ff /* 000bebb0 - 000bf3af [ 2048] */, - 0x5f9d87ff /* 000bf3b0 - 000bfbaf [ 2048] */, - 0x5fdd87ff /* 000bfbb0 - 000c03af [ 2048] */, - 0x601d87ff /* 000c03b0 - 000c0baf [ 2048] */, - 0x605d87ff /* 000c0bb0 - 000c13af [ 2048] */, - 0x609d87ff /* 000c13b0 - 000c1baf [ 2048] */, - 0x60dd87ff /* 000c1bb0 - 000c23af [ 2048] */, - 0x611d87ff /* 000c23b0 - 000c2baf [ 2048] */, - 0x615d87ff /* 000c2bb0 - 000c33af [ 2048] */, - 0x619d87ff /* 000c33b0 - 000c3baf [ 2048] */, - 0x61dd87ff /* 000c3bb0 - 000c43af [ 2048] */, - 0x621d87ff /* 000c43b0 - 000c4baf [ 2048] */, - 0x625d87ff /* 000c4bb0 - 000c53af [ 2048] */, - 0x629d87ff /* 000c53b0 - 000c5baf [ 2048] */, - 0x62dd87ff /* 000c5bb0 - 000c63af [ 2048] */, - 0x631d87ff /* 000c63b0 - 000c6baf [ 2048] */, - 0x635d87ff /* 000c6bb0 - 000c73af [ 2048] */, - 0x639d87ff /* 000c73b0 - 000c7baf [ 2048] */, - 0x63dd87ff /* 000c7bb0 - 000c83af [ 2048] */, - 0x641d87ff /* 000c83b0 - 000c8baf [ 2048] */, - 0x645d87ff /* 000c8bb0 - 000c93af [ 2048] */, - 0x649d87ff /* 000c93b0 - 000c9baf [ 2048] */, - 0x64dd87ff /* 000c9bb0 - 000ca3af [ 2048] */, - 0x651d87ff /* 000ca3b0 - 000cabaf [ 2048] */, - 0x655d87ff /* 000cabb0 - 000cb3af [ 2048] */, - 0x659d87ff /* 000cb3b0 - 000cbbaf [ 2048] */, - 0x65dd87ff /* 000cbbb0 - 000cc3af [ 2048] */, - 0x661d87ff /* 000cc3b0 - 000ccbaf [ 2048] */, - 0x665d87ff /* 000ccbb0 - 000cd3af [ 2048] */, - 0x669d87ff /* 000cd3b0 - 000cdbaf [ 2048] */, - 0x66dd87ff /* 000cdbb0 - 000ce3af [ 2048] */, - 0x671d87ff /* 000ce3b0 - 000cebaf [ 2048] */, - 0x675d87ff /* 000cebb0 - 000cf3af [ 2048] */, - 0x679d87ff /* 000cf3b0 - 000cfbaf [ 2048] */, - 0x67dd87ff /* 000cfbb0 - 000d03af [ 2048] */, - 0x681d87ff /* 000d03b0 - 000d0baf [ 2048] */, - 0x685d87ff /* 000d0bb0 - 000d13af [ 2048] */, - 0x689d87ff /* 000d13b0 - 000d1baf [ 2048] */, - 0x68dd87ff /* 000d1bb0 - 000d23af [ 2048] */, - 0x691d87ff /* 000d23b0 - 000d2baf [ 2048] */, - 0x695d87ff /* 000d2bb0 - 000d33af [ 2048] */, - 0x699d87ff /* 000d33b0 - 000d3baf [ 2048] */, - 0x69dd87ff /* 000d3bb0 - 000d43af [ 2048] */, - 0x6a1d87ff /* 000d43b0 - 000d4baf [ 2048] */, - 0x6a5d87ff /* 000d4bb0 - 000d53af [ 2048] */, - 0x6a9d87ff /* 000d53b0 - 000d5baf [ 2048] */, - 0x6add87ff /* 000d5bb0 - 000d63af [ 2048] */, - 0x6b1d87ff /* 000d63b0 - 000d6baf [ 2048] */, - 0x6b5d87ff /* 000d6bb0 - 000d73af [ 2048] */, - 0x6b9d87ff /* 000d73b0 - 000d7baf [ 2048] */, - 0x6bdd87ff /* 000d7bb0 - 000d83af [ 2048] */, - 0x6c1d87ff /* 000d83b0 - 000d8baf [ 2048] */, - 0x6c5d87ff /* 000d8bb0 - 000d93af [ 2048] */, - 0x6c9d87ff /* 000d93b0 - 000d9baf [ 2048] */, - 0x6cdd87ff /* 000d9bb0 - 000da3af [ 2048] */, - 0x6d1d87ff /* 000da3b0 - 000dabaf [ 2048] */, - 0x6d5d87ff /* 000dabb0 - 000db3af [ 2048] */, - 0x6d9d87ff /* 000db3b0 - 000dbbaf [ 2048] */, - 0x6ddd87ff /* 000dbbb0 - 000dc3af [ 2048] */, - 0x6e1d87ff /* 000dc3b0 - 000dcbaf [ 2048] */, - 0x6e5d87ff /* 000dcbb0 - 000dd3af [ 2048] */, - 0x6e9d87ff /* 000dd3b0 - 000ddbaf [ 2048] */, - 0x6edd87ff /* 000ddbb0 - 000de3af [ 2048] */, - 0x6f1d87ff /* 000de3b0 - 000debaf [ 2048] */, - 0x6f5d87ff /* 000debb0 - 000df3af [ 2048] */, - 0x6f9d87ff /* 000df3b0 - 000dfbaf [ 2048] */, - 0x6fdd854f /* 000dfbb0 - 000e00ff [ 1360] */}; + 0x001fc021 /* 0000007f - 000000a0 [ 34] */, + 0x002b4000 /* 000000ad - 000000ad [ 1] */, + 0x00de0001 /* 00000378 - 00000379 [ 2] */, + 0x00e00003 /* 00000380 - 00000383 [ 4] */, + 0x00e2c000 /* 0000038b - 0000038b [ 1] */, + 0x00e34000 /* 0000038d - 0000038d [ 1] */, + 0x00e88000 /* 000003a2 - 000003a2 [ 1] */, + 0x014c0000 /* 00000530 - 00000530 [ 1] */, + 0x0155c001 /* 00000557 - 00000558 [ 2] */, + 0x0162c001 /* 0000058b - 0000058c [ 2] */, + 0x01640000 /* 00000590 - 00000590 [ 1] */, + 0x01720007 /* 000005c8 - 000005cf [ 8] */, + 0x017ac003 /* 000005eb - 000005ee [ 4] */, + 0x017d4010 /* 000005f5 - 00000605 [ 17] */, + 0x01870000 /* 0000061c - 0000061c [ 1] */, + 0x01b74000 /* 000006dd - 000006dd [ 1] */, + 0x01c38001 /* 0000070e - 0000070f [ 2] */, + 0x01d2c001 /* 0000074b - 0000074c [ 2] */, + 0x01ec800d /* 000007b2 - 000007bf [ 14] */, + 0x01fec001 /* 000007fb - 000007fc [ 2] */, + 0x020b8001 /* 0000082e - 0000082f [ 2] */, + 0x020fc000 /* 0000083f - 0000083f [ 1] */, + 0x02170001 /* 0000085c - 0000085d [ 2] */, + 0x0217c000 /* 0000085f - 0000085f [ 1] */, + 0x021ac004 /* 0000086b - 0000086f [ 5] */, + 0x0223c008 /* 0000088f - 00000897 [ 9] */, + 0x02388000 /* 000008e2 - 000008e2 [ 1] */, + 0x02610000 /* 00000984 - 00000984 [ 1] */, + 0x02634001 /* 0000098d - 0000098e [ 2] */, + 0x02644001 /* 00000991 - 00000992 [ 2] */, + 0x026a4000 /* 000009a9 - 000009a9 [ 1] */, + 0x026c4000 /* 000009b1 - 000009b1 [ 1] */, + 0x026cc002 /* 000009b3 - 000009b5 [ 3] */, + 0x026e8001 /* 000009ba - 000009bb [ 2] */, + 0x02714001 /* 000009c5 - 000009c6 [ 2] */, + 0x02724001 /* 000009c9 - 000009ca [ 2] */, + 0x0273c007 /* 000009cf - 000009d6 [ 8] */, + 0x02760003 /* 000009d8 - 000009db [ 4] */, + 0x02778000 /* 000009de - 000009de [ 1] */, + 0x02790001 /* 000009e4 - 000009e5 [ 2] */, + 0x027fc001 /* 000009ff - 00000a00 [ 2] */, + 0x02810000 /* 00000a04 - 00000a04 [ 1] */, + 0x0282c003 /* 00000a0b - 00000a0e [ 4] */, + 0x02844001 /* 00000a11 - 00000a12 [ 2] */, + 0x028a4000 /* 00000a29 - 00000a29 [ 1] */, + 0x028c4000 /* 00000a31 - 00000a31 [ 1] */, + 0x028d0000 /* 00000a34 - 00000a34 [ 1] */, + 0x028dc000 /* 00000a37 - 00000a37 [ 1] */, + 0x028e8001 /* 00000a3a - 00000a3b [ 2] */, + 0x028f4000 /* 00000a3d - 00000a3d [ 1] */, + 0x0290c003 /* 00000a43 - 00000a46 [ 4] */, + 0x02924001 /* 00000a49 - 00000a4a [ 2] */, + 0x02938002 /* 00000a4e - 00000a50 [ 3] */, + 0x02948006 /* 00000a52 - 00000a58 [ 7] */, + 0x02974000 /* 00000a5d - 00000a5d [ 1] */, + 0x0297c006 /* 00000a5f - 00000a65 [ 7] */, + 0x029dc009 /* 00000a77 - 00000a80 [ 10] */, + 0x02a10000 /* 00000a84 - 00000a84 [ 1] */, + 0x02a38000 /* 00000a8e - 00000a8e [ 1] */, + 0x02a48000 /* 00000a92 - 00000a92 [ 1] */, + 0x02aa4000 /* 00000aa9 - 00000aa9 [ 1] */, + 0x02ac4000 /* 00000ab1 - 00000ab1 [ 1] */, + 0x02ad0000 /* 00000ab4 - 00000ab4 [ 1] */, + 0x02ae8001 /* 00000aba - 00000abb [ 2] */, + 0x02b18000 /* 00000ac6 - 00000ac6 [ 1] */, + 0x02b28000 /* 00000aca - 00000aca [ 1] */, + 0x02b38001 /* 00000ace - 00000acf [ 2] */, + 0x02b4400e /* 00000ad1 - 00000adf [ 15] */, + 0x02b90001 /* 00000ae4 - 00000ae5 [ 2] */, + 0x02bc8006 /* 00000af2 - 00000af8 [ 7] */, + 0x02c00000 /* 00000b00 - 00000b00 [ 1] */, + 0x02c10000 /* 00000b04 - 00000b04 [ 1] */, + 0x02c34001 /* 00000b0d - 00000b0e [ 2] */, + 0x02c44001 /* 00000b11 - 00000b12 [ 2] */, + 0x02ca4000 /* 00000b29 - 00000b29 [ 1] */, + 0x02cc4000 /* 00000b31 - 00000b31 [ 1] */, + 0x02cd0000 /* 00000b34 - 00000b34 [ 1] */, + 0x02ce8001 /* 00000b3a - 00000b3b [ 2] */, + 0x02d14001 /* 00000b45 - 00000b46 [ 2] */, + 0x02d24001 /* 00000b49 - 00000b4a [ 2] */, + 0x02d38006 /* 00000b4e - 00000b54 [ 7] */, + 0x02d60003 /* 00000b58 - 00000b5b [ 4] */, + 0x02d78000 /* 00000b5e - 00000b5e [ 1] */, + 0x02d90001 /* 00000b64 - 00000b65 [ 2] */, + 0x02de0009 /* 00000b78 - 00000b81 [ 10] */, + 0x02e10000 /* 00000b84 - 00000b84 [ 1] */, + 0x02e2c002 /* 00000b8b - 00000b8d [ 3] */, + 0x02e44000 /* 00000b91 - 00000b91 [ 1] */, + 0x02e58002 /* 00000b96 - 00000b98 [ 3] */, + 0x02e6c000 /* 00000b9b - 00000b9b [ 1] */, + 0x02e74000 /* 00000b9d - 00000b9d [ 1] */, + 0x02e80002 /* 00000ba0 - 00000ba2 [ 3] */, + 0x02e94002 /* 00000ba5 - 00000ba7 [ 3] */, + 0x02eac002 /* 00000bab - 00000bad [ 3] */, + 0x02ee8003 /* 00000bba - 00000bbd [ 4] */, + 0x02f0c002 /* 00000bc3 - 00000bc5 [ 3] */, + 0x02f24000 /* 00000bc9 - 00000bc9 [ 1] */, + 0x02f38001 /* 00000bce - 00000bcf [ 2] */, + 0x02f44005 /* 00000bd1 - 00000bd6 [ 6] */, + 0x02f6000d /* 00000bd8 - 00000be5 [ 14] */, + 0x02fec004 /* 00000bfb - 00000bff [ 5] */, + 0x03034000 /* 00000c0d - 00000c0d [ 1] */, + 0x03044000 /* 00000c11 - 00000c11 [ 1] */, + 0x030a4000 /* 00000c29 - 00000c29 [ 1] */, + 0x030e8001 /* 00000c3a - 00000c3b [ 2] */, + 0x03114000 /* 00000c45 - 00000c45 [ 1] */, + 0x03124000 /* 00000c49 - 00000c49 [ 1] */, + 0x03138006 /* 00000c4e - 00000c54 [ 7] */, + 0x0315c000 /* 00000c57 - 00000c57 [ 1] */, + 0x0316c001 /* 00000c5b - 00000c5c [ 2] */, + 0x03178001 /* 00000c5e - 00000c5f [ 2] */, + 0x03190001 /* 00000c64 - 00000c65 [ 2] */, + 0x031c0006 /* 00000c70 - 00000c76 [ 7] */, + 0x03234000 /* 00000c8d - 00000c8d [ 1] */, + 0x03244000 /* 00000c91 - 00000c91 [ 1] */, + 0x032a4000 /* 00000ca9 - 00000ca9 [ 1] */, + 0x032d0000 /* 00000cb4 - 00000cb4 [ 1] */, + 0x032e8001 /* 00000cba - 00000cbb [ 2] */, + 0x03314000 /* 00000cc5 - 00000cc5 [ 1] */, + 0x03324000 /* 00000cc9 - 00000cc9 [ 1] */, + 0x03338006 /* 00000cce - 00000cd4 [ 7] */, + 0x0335c005 /* 00000cd7 - 00000cdc [ 6] */, + 0x0337c000 /* 00000cdf - 00000cdf [ 1] */, + 0x03390001 /* 00000ce4 - 00000ce5 [ 2] */, + 0x033c0000 /* 00000cf0 - 00000cf0 [ 1] */, + 0x033d000b /* 00000cf4 - 00000cff [ 12] */, + 0x03434000 /* 00000d0d - 00000d0d [ 1] */, + 0x03444000 /* 00000d11 - 00000d11 [ 1] */, + 0x03514000 /* 00000d45 - 00000d45 [ 1] */, + 0x03524000 /* 00000d49 - 00000d49 [ 1] */, + 0x03540003 /* 00000d50 - 00000d53 [ 4] */, + 0x03590001 /* 00000d64 - 00000d65 [ 2] */, + 0x03600000 /* 00000d80 - 00000d80 [ 1] */, + 0x03610000 /* 00000d84 - 00000d84 [ 1] */, + 0x0365c002 /* 00000d97 - 00000d99 [ 3] */, + 0x036c8000 /* 00000db2 - 00000db2 [ 1] */, + 0x036f0000 /* 00000dbc - 00000dbc [ 1] */, + 0x036f8001 /* 00000dbe - 00000dbf [ 2] */, + 0x0371c002 /* 00000dc7 - 00000dc9 [ 3] */, + 0x0372c003 /* 00000dcb - 00000dce [ 4] */, + 0x03754000 /* 00000dd5 - 00000dd5 [ 1] */, + 0x0375c000 /* 00000dd7 - 00000dd7 [ 1] */, + 0x03780005 /* 00000de0 - 00000de5 [ 6] */, + 0x037c0001 /* 00000df0 - 00000df1 [ 2] */, + 0x037d400b /* 00000df5 - 00000e00 [ 12] */, + 0x038ec003 /* 00000e3b - 00000e3e [ 4] */, + 0x03970024 /* 00000e5c - 00000e80 [ 37] */, + 0x03a0c000 /* 00000e83 - 00000e83 [ 1] */, + 0x03a14000 /* 00000e85 - 00000e85 [ 1] */, + 0x03a2c000 /* 00000e8b - 00000e8b [ 1] */, + 0x03a90000 /* 00000ea4 - 00000ea4 [ 1] */, + 0x03a98000 /* 00000ea6 - 00000ea6 [ 1] */, + 0x03af8001 /* 00000ebe - 00000ebf [ 2] */, + 0x03b14000 /* 00000ec5 - 00000ec5 [ 1] */, + 0x03b1c000 /* 00000ec7 - 00000ec7 [ 1] */, + 0x03b3c000 /* 00000ecf - 00000ecf [ 1] */, + 0x03b68001 /* 00000eda - 00000edb [ 2] */, + 0x03b8001f /* 00000ee0 - 00000eff [ 32] */, + 0x03d20000 /* 00000f48 - 00000f48 [ 1] */, + 0x03db4003 /* 00000f6d - 00000f70 [ 4] */, + 0x03e60000 /* 00000f98 - 00000f98 [ 1] */, + 0x03ef4000 /* 00000fbd - 00000fbd [ 1] */, + 0x03f34000 /* 00000fcd - 00000fcd [ 1] */, + 0x03f6c024 /* 00000fdb - 00000fff [ 37] */, + 0x04318000 /* 000010c6 - 000010c6 [ 1] */, + 0x04320004 /* 000010c8 - 000010cc [ 5] */, + 0x04338001 /* 000010ce - 000010cf [ 2] */, + 0x04924000 /* 00001249 - 00001249 [ 1] */, + 0x04938001 /* 0000124e - 0000124f [ 2] */, + 0x0495c000 /* 00001257 - 00001257 [ 1] */, + 0x04964000 /* 00001259 - 00001259 [ 1] */, + 0x04978001 /* 0000125e - 0000125f [ 2] */, + 0x04a24000 /* 00001289 - 00001289 [ 1] */, + 0x04a38001 /* 0000128e - 0000128f [ 2] */, + 0x04ac4000 /* 000012b1 - 000012b1 [ 1] */, + 0x04ad8001 /* 000012b6 - 000012b7 [ 2] */, + 0x04afc000 /* 000012bf - 000012bf [ 1] */, + 0x04b04000 /* 000012c1 - 000012c1 [ 1] */, + 0x04b18001 /* 000012c6 - 000012c7 [ 2] */, + 0x04b5c000 /* 000012d7 - 000012d7 [ 1] */, + 0x04c44000 /* 00001311 - 00001311 [ 1] */, + 0x04c58001 /* 00001316 - 00001317 [ 2] */, + 0x04d6c001 /* 0000135b - 0000135c [ 2] */, + 0x04df4002 /* 0000137d - 0000137f [ 3] */, + 0x04e68005 /* 0000139a - 0000139f [ 6] */, + 0x04fd8001 /* 000013f6 - 000013f7 [ 2] */, + 0x04ff8001 /* 000013fe - 000013ff [ 2] */, + 0x05a00000 /* 00001680 - 00001680 [ 1] */, + 0x05a74002 /* 0000169d - 0000169f [ 3] */, + 0x05be4006 /* 000016f9 - 000016ff [ 7] */, + 0x05c58008 /* 00001716 - 0000171e [ 9] */, + 0x05cdc008 /* 00001737 - 0000173f [ 9] */, + 0x05d5000b /* 00001754 - 0000175f [ 12] */, + 0x05db4000 /* 0000176d - 0000176d [ 1] */, + 0x05dc4000 /* 00001771 - 00001771 [ 1] */, + 0x05dd000b /* 00001774 - 0000177f [ 12] */, + 0x05f78001 /* 000017de - 000017df [ 2] */, + 0x05fa8005 /* 000017ea - 000017ef [ 6] */, + 0x05fe8005 /* 000017fa - 000017ff [ 6] */, + 0x06038000 /* 0000180e - 0000180e [ 1] */, + 0x06068005 /* 0000181a - 0000181f [ 6] */, + 0x061e4006 /* 00001879 - 0000187f [ 7] */, + 0x062ac004 /* 000018ab - 000018af [ 5] */, + 0x063d8009 /* 000018f6 - 000018ff [ 10] */, + 0x0647c000 /* 0000191f - 0000191f [ 1] */, + 0x064b0003 /* 0000192c - 0000192f [ 4] */, + 0x064f0003 /* 0000193c - 0000193f [ 4] */, + 0x06504002 /* 00001941 - 00001943 [ 3] */, + 0x065b8001 /* 0000196e - 0000196f [ 2] */, + 0x065d400a /* 00001975 - 0000197f [ 11] */, + 0x066b0003 /* 000019ac - 000019af [ 4] */, + 0x06728005 /* 000019ca - 000019cf [ 6] */, + 0x0676c002 /* 000019db - 000019dd [ 3] */, + 0x06870001 /* 00001a1c - 00001a1d [ 2] */, + 0x0697c000 /* 00001a5f - 00001a5f [ 1] */, + 0x069f4001 /* 00001a7d - 00001a7e [ 2] */, + 0x06a28005 /* 00001a8a - 00001a8f [ 6] */, + 0x06a68005 /* 00001a9a - 00001a9f [ 6] */, + 0x06ab8001 /* 00001aae - 00001aaf [ 2] */, + 0x06b3c030 /* 00001acf - 00001aff [ 49] */, + 0x06d34002 /* 00001b4d - 00001b4f [ 3] */, + 0x06dfc000 /* 00001b7f - 00001b7f [ 1] */, + 0x06fd0007 /* 00001bf4 - 00001bfb [ 8] */, + 0x070e0002 /* 00001c38 - 00001c3a [ 3] */, + 0x07128002 /* 00001c4a - 00001c4c [ 3] */, + 0x07224006 /* 00001c89 - 00001c8f [ 7] */, + 0x072ec001 /* 00001cbb - 00001cbc [ 2] */, + 0x07320007 /* 00001cc8 - 00001ccf [ 8] */, + 0x073ec004 /* 00001cfb - 00001cff [ 5] */, + 0x07c58001 /* 00001f16 - 00001f17 [ 2] */, + 0x07c78001 /* 00001f1e - 00001f1f [ 2] */, + 0x07d18001 /* 00001f46 - 00001f47 [ 2] */, + 0x07d38001 /* 00001f4e - 00001f4f [ 2] */, + 0x07d60000 /* 00001f58 - 00001f58 [ 1] */, + 0x07d68000 /* 00001f5a - 00001f5a [ 1] */, + 0x07d70000 /* 00001f5c - 00001f5c [ 1] */, + 0x07d78000 /* 00001f5e - 00001f5e [ 1] */, + 0x07df8001 /* 00001f7e - 00001f7f [ 2] */, + 0x07ed4000 /* 00001fb5 - 00001fb5 [ 1] */, + 0x07f14000 /* 00001fc5 - 00001fc5 [ 1] */, + 0x07f50001 /* 00001fd4 - 00001fd5 [ 2] */, + 0x07f70000 /* 00001fdc - 00001fdc [ 1] */, + 0x07fc0001 /* 00001ff0 - 00001ff1 [ 2] */, + 0x07fd4000 /* 00001ff5 - 00001ff5 [ 1] */, + 0x07ffc010 /* 00001fff - 0000200f [ 17] */, + 0x080a0007 /* 00002028 - 0000202f [ 8] */, + 0x0817c010 /* 0000205f - 0000206f [ 17] */, + 0x081c8001 /* 00002072 - 00002073 [ 2] */, + 0x0823c000 /* 0000208f - 0000208f [ 1] */, + 0x08274002 /* 0000209d - 0000209f [ 3] */, + 0x0830400e /* 000020c1 - 000020cf [ 15] */, + 0x083c400e /* 000020f1 - 000020ff [ 15] */, + 0x08630003 /* 0000218c - 0000218f [ 4] */, + 0x0909c018 /* 00002427 - 0000243f [ 25] */, + 0x0912c014 /* 0000244b - 0000245f [ 21] */, + 0x0add0001 /* 00002b74 - 00002b75 [ 2] */, + 0x0ae58000 /* 00002b96 - 00002b96 [ 1] */, + 0x0b3d0004 /* 00002cf4 - 00002cf8 [ 5] */, + 0x0b498000 /* 00002d26 - 00002d26 [ 1] */, + 0x0b4a0004 /* 00002d28 - 00002d2c [ 5] */, + 0x0b4b8001 /* 00002d2e - 00002d2f [ 2] */, + 0x0b5a0006 /* 00002d68 - 00002d6e [ 7] */, + 0x0b5c400d /* 00002d71 - 00002d7e [ 14] */, + 0x0b65c008 /* 00002d97 - 00002d9f [ 9] */, + 0x0b69c000 /* 00002da7 - 00002da7 [ 1] */, + 0x0b6bc000 /* 00002daf - 00002daf [ 1] */, + 0x0b6dc000 /* 00002db7 - 00002db7 [ 1] */, + 0x0b6fc000 /* 00002dbf - 00002dbf [ 1] */, + 0x0b71c000 /* 00002dc7 - 00002dc7 [ 1] */, + 0x0b73c000 /* 00002dcf - 00002dcf [ 1] */, + 0x0b75c000 /* 00002dd7 - 00002dd7 [ 1] */, + 0x0b77c000 /* 00002ddf - 00002ddf [ 1] */, + 0x0b978021 /* 00002e5e - 00002e7f [ 34] */, + 0x0ba68000 /* 00002e9a - 00002e9a [ 1] */, + 0x0bbd000b /* 00002ef4 - 00002eff [ 12] */, + 0x0bf58019 /* 00002fd6 - 00002fef [ 26] */, + 0x0c000000 /* 00003000 - 00003000 [ 1] */, + 0x0c100000 /* 00003040 - 00003040 [ 1] */, + 0x0c25c001 /* 00003097 - 00003098 [ 2] */, + 0x0c400004 /* 00003100 - 00003104 [ 5] */, + 0x0c4c0000 /* 00003130 - 00003130 [ 1] */, + 0x0c63c000 /* 0000318f - 0000318f [ 1] */, + 0x0c79000a /* 000031e4 - 000031ee [ 11] */, + 0x0c87c000 /* 0000321f - 0000321f [ 1] */, + 0x29234002 /* 0000a48d - 0000a48f [ 3] */, + 0x2931c008 /* 0000a4c7 - 0000a4cf [ 9] */, + 0x298b0013 /* 0000a62c - 0000a63f [ 20] */, + 0x29be0007 /* 0000a6f8 - 0000a6ff [ 8] */, + 0x29f2c004 /* 0000a7cb - 0000a7cf [ 5] */, + 0x29f48000 /* 0000a7d2 - 0000a7d2 [ 1] */, + 0x29f50000 /* 0000a7d4 - 0000a7d4 [ 1] */, + 0x29f68017 /* 0000a7da - 0000a7f1 [ 24] */, + 0x2a0b4002 /* 0000a82d - 0000a82f [ 3] */, + 0x2a0e8005 /* 0000a83a - 0000a83f [ 6] */, + 0x2a1e0007 /* 0000a878 - 0000a87f [ 8] */, + 0x2a318007 /* 0000a8c6 - 0000a8cd [ 8] */, + 0x2a368005 /* 0000a8da - 0000a8df [ 6] */, + 0x2a55000a /* 0000a954 - 0000a95e [ 11] */, + 0x2a5f4002 /* 0000a97d - 0000a97f [ 3] */, + 0x2a738000 /* 0000a9ce - 0000a9ce [ 1] */, + 0x2a768003 /* 0000a9da - 0000a9dd [ 4] */, + 0x2a7fc000 /* 0000a9ff - 0000a9ff [ 1] */, + 0x2a8dc008 /* 0000aa37 - 0000aa3f [ 9] */, + 0x2a938001 /* 0000aa4e - 0000aa4f [ 2] */, + 0x2a968001 /* 0000aa5a - 0000aa5b [ 2] */, + 0x2ab0c017 /* 0000aac3 - 0000aada [ 24] */, + 0x2abdc009 /* 0000aaf7 - 0000ab00 [ 10] */, + 0x2ac1c001 /* 0000ab07 - 0000ab08 [ 2] */, + 0x2ac3c001 /* 0000ab0f - 0000ab10 [ 2] */, + 0x2ac5c008 /* 0000ab17 - 0000ab1f [ 9] */, + 0x2ac9c000 /* 0000ab27 - 0000ab27 [ 1] */, + 0x2acbc000 /* 0000ab2f - 0000ab2f [ 1] */, + 0x2adb0003 /* 0000ab6c - 0000ab6f [ 4] */, + 0x2afb8001 /* 0000abee - 0000abef [ 2] */, + 0x2afe8005 /* 0000abfa - 0000abff [ 6] */, + 0x35e9000b /* 0000d7a4 - 0000d7af [ 12] */, + 0x35f1c003 /* 0000d7c7 - 0000d7ca [ 4] */, + 0x35ff2103 /* 0000d7fc - 0000f8ff [ 8452] */, + 0x3e9b8001 /* 0000fa6e - 0000fa6f [ 2] */, + 0x3eb68025 /* 0000fada - 0000faff [ 38] */, + 0x3ec1c00b /* 0000fb07 - 0000fb12 [ 12] */, + 0x3ec60004 /* 0000fb18 - 0000fb1c [ 5] */, + 0x3ecdc000 /* 0000fb37 - 0000fb37 [ 1] */, + 0x3ecf4000 /* 0000fb3d - 0000fb3d [ 1] */, + 0x3ecfc000 /* 0000fb3f - 0000fb3f [ 1] */, + 0x3ed08000 /* 0000fb42 - 0000fb42 [ 1] */, + 0x3ed14000 /* 0000fb45 - 0000fb45 [ 1] */, + 0x3ef0c00f /* 0000fbc3 - 0000fbd2 [ 16] */, + 0x3f640001 /* 0000fd90 - 0000fd91 [ 2] */, + 0x3f720006 /* 0000fdc8 - 0000fdce [ 7] */, + 0x3f74001f /* 0000fdd0 - 0000fdef [ 32] */, + 0x3f868005 /* 0000fe1a - 0000fe1f [ 6] */, + 0x3f94c000 /* 0000fe53 - 0000fe53 [ 1] */, + 0x3f99c000 /* 0000fe67 - 0000fe67 [ 1] */, + 0x3f9b0003 /* 0000fe6c - 0000fe6f [ 4] */, + 0x3f9d4000 /* 0000fe75 - 0000fe75 [ 1] */, + 0x3fbf4003 /* 0000fefd - 0000ff00 [ 4] */, + 0x3fefc002 /* 0000ffbf - 0000ffc1 [ 3] */, + 0x3ff20001 /* 0000ffc8 - 0000ffc9 [ 2] */, + 0x3ff40001 /* 0000ffd0 - 0000ffd1 [ 2] */, + 0x3ff60001 /* 0000ffd8 - 0000ffd9 [ 2] */, + 0x3ff74002 /* 0000ffdd - 0000ffdf [ 3] */, + 0x3ff9c000 /* 0000ffe7 - 0000ffe7 [ 1] */, + 0x3ffbc00c /* 0000ffef - 0000fffb [ 13] */, + 0x3fff8001 /* 0000fffe - 0000ffff [ 2] */, + 0x40030000 /* 0001000c - 0001000c [ 1] */, + 0x4009c000 /* 00010027 - 00010027 [ 1] */, + 0x400ec000 /* 0001003b - 0001003b [ 1] */, + 0x400f8000 /* 0001003e - 0001003e [ 1] */, + 0x40138001 /* 0001004e - 0001004f [ 2] */, + 0x40178021 /* 0001005e - 0001007f [ 34] */, + 0x403ec004 /* 000100fb - 000100ff [ 5] */, + 0x4040c003 /* 00010103 - 00010106 [ 4] */, + 0x404d0002 /* 00010134 - 00010136 [ 3] */, + 0x4063c000 /* 0001018f - 0001018f [ 1] */, + 0x40674002 /* 0001019d - 0001019f [ 3] */, + 0x4068402e /* 000101a1 - 000101cf [ 47] */, + 0x407f8081 /* 000101fe - 0001027f [ 130] */, + 0x40a74002 /* 0001029d - 0001029f [ 3] */, + 0x40b4400e /* 000102d1 - 000102df [ 15] */, + 0x40bf0003 /* 000102fc - 000102ff [ 4] */, + 0x40c90008 /* 00010324 - 0001032c [ 9] */, + 0x40d2c004 /* 0001034b - 0001034f [ 5] */, + 0x40dec004 /* 0001037b - 0001037f [ 5] */, + 0x40e78000 /* 0001039e - 0001039e [ 1] */, + 0x40f10003 /* 000103c4 - 000103c7 [ 4] */, + 0x40f58029 /* 000103d6 - 000103ff [ 42] */, + 0x41278001 /* 0001049e - 0001049f [ 2] */, + 0x412a8005 /* 000104aa - 000104af [ 6] */, + 0x41350003 /* 000104d4 - 000104d7 [ 4] */, + 0x413f0003 /* 000104fc - 000104ff [ 4] */, + 0x414a0007 /* 00010528 - 0001052f [ 8] */, + 0x4159000a /* 00010564 - 0001056e [ 11] */, + 0x415ec000 /* 0001057b - 0001057b [ 1] */, + 0x4162c000 /* 0001058b - 0001058b [ 1] */, + 0x4164c000 /* 00010593 - 00010593 [ 1] */, + 0x41658000 /* 00010596 - 00010596 [ 1] */, + 0x41688000 /* 000105a2 - 000105a2 [ 1] */, + 0x416c8000 /* 000105b2 - 000105b2 [ 1] */, + 0x416e8000 /* 000105ba - 000105ba [ 1] */, + 0x416f4042 /* 000105bd - 000105ff [ 67] */, + 0x41cdc008 /* 00010737 - 0001073f [ 9] */, + 0x41d58009 /* 00010756 - 0001075f [ 10] */, + 0x41da0017 /* 00010768 - 0001077f [ 24] */, + 0x41e18000 /* 00010786 - 00010786 [ 1] */, + 0x41ec4000 /* 000107b1 - 000107b1 [ 1] */, + 0x41eec044 /* 000107bb - 000107ff [ 69] */, + 0x42018001 /* 00010806 - 00010807 [ 2] */, + 0x42024000 /* 00010809 - 00010809 [ 1] */, + 0x420d8000 /* 00010836 - 00010836 [ 1] */, + 0x420e4002 /* 00010839 - 0001083b [ 3] */, + 0x420f4001 /* 0001083d - 0001083e [ 2] */, + 0x42158000 /* 00010856 - 00010856 [ 1] */, + 0x4227c007 /* 0001089f - 000108a6 [ 8] */, + 0x422c002f /* 000108b0 - 000108df [ 48] */, + 0x423cc000 /* 000108f3 - 000108f3 [ 1] */, + 0x423d8004 /* 000108f6 - 000108fa [ 5] */, + 0x42470002 /* 0001091c - 0001091e [ 3] */, + 0x424e8004 /* 0001093a - 0001093e [ 5] */, + 0x4250003f /* 00010940 - 0001097f [ 64] */, + 0x426e0003 /* 000109b8 - 000109bb [ 4] */, + 0x42740001 /* 000109d0 - 000109d1 [ 2] */, + 0x42810000 /* 00010a04 - 00010a04 [ 1] */, + 0x4281c004 /* 00010a07 - 00010a0b [ 5] */, + 0x42850000 /* 00010a14 - 00010a14 [ 1] */, + 0x42860000 /* 00010a18 - 00010a18 [ 1] */, + 0x428d8001 /* 00010a36 - 00010a37 [ 2] */, + 0x428ec003 /* 00010a3b - 00010a3e [ 4] */, + 0x42924006 /* 00010a49 - 00010a4f [ 7] */, + 0x42964006 /* 00010a59 - 00010a5f [ 7] */, + 0x42a8001f /* 00010aa0 - 00010abf [ 32] */, + 0x42b9c003 /* 00010ae7 - 00010aea [ 4] */, + 0x42bdc008 /* 00010af7 - 00010aff [ 9] */, + 0x42cd8002 /* 00010b36 - 00010b38 [ 3] */, + 0x42d58001 /* 00010b56 - 00010b57 [ 2] */, + 0x42dcc004 /* 00010b73 - 00010b77 [ 5] */, + 0x42e48006 /* 00010b92 - 00010b98 [ 7] */, + 0x42e7400b /* 00010b9d - 00010ba8 [ 12] */, + 0x42ec004f /* 00010bb0 - 00010bff [ 80] */, + 0x43124036 /* 00010c49 - 00010c7f [ 55] */, + 0x432cc00c /* 00010cb3 - 00010cbf [ 13] */, + 0x433cc006 /* 00010cf3 - 00010cf9 [ 7] */, + 0x434a0007 /* 00010d28 - 00010d2f [ 8] */, + 0x434e8125 /* 00010d3a - 00010e5f [ 294] */, + 0x439fc000 /* 00010e7f - 00010e7f [ 1] */, + 0x43aa8000 /* 00010eaa - 00010eaa [ 1] */, + 0x43ab8001 /* 00010eae - 00010eaf [ 2] */, + 0x43ac804a /* 00010eb2 - 00010efc [ 75] */, + 0x43ca0007 /* 00010f28 - 00010f2f [ 8] */, + 0x43d68015 /* 00010f5a - 00010f6f [ 22] */, + 0x43e28025 /* 00010f8a - 00010faf [ 38] */, + 0x43f30013 /* 00010fcc - 00010fdf [ 20] */, + 0x43fdc008 /* 00010ff7 - 00010fff [ 9] */, + 0x44138003 /* 0001104e - 00011051 [ 4] */, + 0x441d8008 /* 00011076 - 0001107e [ 9] */, + 0x442f4000 /* 000110bd - 000110bd [ 1] */, + 0x4430c00c /* 000110c3 - 000110cf [ 13] */, + 0x443a4006 /* 000110e9 - 000110ef [ 7] */, + 0x443e8005 /* 000110fa - 000110ff [ 6] */, + 0x444d4000 /* 00011135 - 00011135 [ 1] */, + 0x44520007 /* 00011148 - 0001114f [ 8] */, + 0x445dc008 /* 00011177 - 0001117f [ 9] */, + 0x44780000 /* 000111e0 - 000111e0 [ 1] */, + 0x447d400a /* 000111f5 - 000111ff [ 11] */, + 0x44848000 /* 00011212 - 00011212 [ 1] */, + 0x4490803d /* 00011242 - 0001127f [ 62] */, + 0x44a1c000 /* 00011287 - 00011287 [ 1] */, + 0x44a24000 /* 00011289 - 00011289 [ 1] */, + 0x44a38000 /* 0001128e - 0001128e [ 1] */, + 0x44a78000 /* 0001129e - 0001129e [ 1] */, + 0x44aa8005 /* 000112aa - 000112af [ 6] */, + 0x44bac004 /* 000112eb - 000112ef [ 5] */, + 0x44be8005 /* 000112fa - 000112ff [ 6] */, + 0x44c10000 /* 00011304 - 00011304 [ 1] */, + 0x44c34001 /* 0001130d - 0001130e [ 2] */, + 0x44c44001 /* 00011311 - 00011312 [ 2] */, + 0x44ca4000 /* 00011329 - 00011329 [ 1] */, + 0x44cc4000 /* 00011331 - 00011331 [ 1] */, + 0x44cd0000 /* 00011334 - 00011334 [ 1] */, + 0x44ce8000 /* 0001133a - 0001133a [ 1] */, + 0x44d14001 /* 00011345 - 00011346 [ 2] */, + 0x44d24001 /* 00011349 - 0001134a [ 2] */, + 0x44d38001 /* 0001134e - 0001134f [ 2] */, + 0x44d44005 /* 00011351 - 00011356 [ 6] */, + 0x44d60004 /* 00011358 - 0001135c [ 5] */, + 0x44d90001 /* 00011364 - 00011365 [ 2] */, + 0x44db4002 /* 0001136d - 0001136f [ 3] */, + 0x44dd408a /* 00011375 - 000113ff [ 139] */, + 0x45170000 /* 0001145c - 0001145c [ 1] */, + 0x4518801d /* 00011462 - 0001147f [ 30] */, + 0x45320007 /* 000114c8 - 000114cf [ 8] */, + 0x453680a5 /* 000114da - 0001157f [ 166] */, + 0x456d8001 /* 000115b6 - 000115b7 [ 2] */, + 0x45778021 /* 000115de - 000115ff [ 34] */, + 0x4591400a /* 00011645 - 0001164f [ 11] */, + 0x45968005 /* 0001165a - 0001165f [ 6] */, + 0x459b4012 /* 0001166d - 0001167f [ 19] */, + 0x45ae8005 /* 000116ba - 000116bf [ 6] */, + 0x45b28035 /* 000116ca - 000116ff [ 54] */, + 0x45c6c001 /* 0001171b - 0001171c [ 2] */, + 0x45cb0003 /* 0001172c - 0001172f [ 4] */, + 0x45d1c0b8 /* 00011747 - 000117ff [ 185] */, + 0x460f0063 /* 0001183c - 0001189f [ 100] */, + 0x463cc00b /* 000118f3 - 000118fe [ 12] */, + 0x4641c001 /* 00011907 - 00011908 [ 2] */, + 0x46428001 /* 0001190a - 0001190b [ 2] */, + 0x46450000 /* 00011914 - 00011914 [ 1] */, + 0x4645c000 /* 00011917 - 00011917 [ 1] */, + 0x464d8000 /* 00011936 - 00011936 [ 1] */, + 0x464e4001 /* 00011939 - 0001193a [ 2] */, + 0x4651c008 /* 00011947 - 0001194f [ 9] */, + 0x46568045 /* 0001195a - 0001199f [ 70] */, + 0x466a0001 /* 000119a8 - 000119a9 [ 2] */, + 0x46760001 /* 000119d8 - 000119d9 [ 2] */, + 0x4679401a /* 000119e5 - 000119ff [ 27] */, + 0x46920007 /* 00011a48 - 00011a4f [ 8] */, + 0x46a8c00c /* 00011aa3 - 00011aaf [ 13] */, + 0x46be4006 /* 00011af9 - 00011aff [ 7] */, + 0x46c280f5 /* 00011b0a - 00011bff [ 246] */, + 0x47024000 /* 00011c09 - 00011c09 [ 1] */, + 0x470dc000 /* 00011c37 - 00011c37 [ 1] */, + 0x47118009 /* 00011c46 - 00011c4f [ 10] */, + 0x471b4002 /* 00011c6d - 00011c6f [ 3] */, + 0x47240001 /* 00011c90 - 00011c91 [ 2] */, + 0x472a0000 /* 00011ca8 - 00011ca8 [ 1] */, + 0x472dc048 /* 00011cb7 - 00011cff [ 73] */, + 0x4741c000 /* 00011d07 - 00011d07 [ 1] */, + 0x47428000 /* 00011d0a - 00011d0a [ 1] */, + 0x474dc002 /* 00011d37 - 00011d39 [ 3] */, + 0x474ec000 /* 00011d3b - 00011d3b [ 1] */, + 0x474f8000 /* 00011d3e - 00011d3e [ 1] */, + 0x47520007 /* 00011d48 - 00011d4f [ 8] */, + 0x47568005 /* 00011d5a - 00011d5f [ 6] */, + 0x47598000 /* 00011d66 - 00011d66 [ 1] */, + 0x475a4000 /* 00011d69 - 00011d69 [ 1] */, + 0x4763c000 /* 00011d8f - 00011d8f [ 1] */, + 0x47648000 /* 00011d92 - 00011d92 [ 1] */, + 0x47664006 /* 00011d99 - 00011d9f [ 7] */, + 0x476a8135 /* 00011daa - 00011edf [ 310] */, + 0x47be4006 /* 00011ef9 - 00011eff [ 7] */, + 0x47c44000 /* 00011f11 - 00011f11 [ 1] */, + 0x47cec002 /* 00011f3b - 00011f3d [ 3] */, + 0x47d68055 /* 00011f5a - 00011faf [ 86] */, + 0x47ec400e /* 00011fb1 - 00011fbf [ 15] */, + 0x47fc800c /* 00011ff2 - 00011ffe [ 13] */, + 0x48e68065 /* 0001239a - 000123ff [ 102] */, + 0x491bc000 /* 0001246f - 0001246f [ 1] */, + 0x491d400a /* 00012475 - 0001247f [ 11] */, + 0x49510a4b /* 00012544 - 00012f8f [ 2636] */, + 0x4bfcc00c /* 00012ff3 - 00012fff [ 13] */, + 0x4d0c000f /* 00013430 - 0001343f [ 16] */, + 0x4d158fa9 /* 00013456 - 000143ff [ 4010] */, + 0x5191e1b8 /* 00014647 - 000167ff [ 8633] */, + 0x5a8e4006 /* 00016a39 - 00016a3f [ 7] */, + 0x5a97c000 /* 00016a5f - 00016a5f [ 1] */, + 0x5a9a8003 /* 00016a6a - 00016a6d [ 4] */, + 0x5aafc000 /* 00016abf - 00016abf [ 1] */, + 0x5ab28005 /* 00016aca - 00016acf [ 6] */, + 0x5abb8001 /* 00016aee - 00016aef [ 2] */, + 0x5abd8009 /* 00016af6 - 00016aff [ 10] */, + 0x5ad18009 /* 00016b46 - 00016b4f [ 10] */, + 0x5ad68000 /* 00016b5a - 00016b5a [ 1] */, + 0x5ad88000 /* 00016b62 - 00016b62 [ 1] */, + 0x5ade0004 /* 00016b78 - 00016b7c [ 5] */, + 0x5ae402af /* 00016b90 - 00016e3f [ 688] */, + 0x5ba6c064 /* 00016e9b - 00016eff [ 101] */, + 0x5bd2c003 /* 00016f4b - 00016f4e [ 4] */, + 0x5be20006 /* 00016f88 - 00016f8e [ 7] */, + 0x5be8003f /* 00016fa0 - 00016fdf [ 64] */, + 0x5bf9400a /* 00016fe5 - 00016fef [ 11] */, + 0x5bfc800d /* 00016ff2 - 00016fff [ 14] */, + 0x61fe0007 /* 000187f8 - 000187ff [ 8] */, + 0x63358029 /* 00018cd6 - 00018cff [ 42] */, + 0x634262e6 /* 00018d09 - 0001afef [ 8935] */, + 0x6bfd0000 /* 0001aff4 - 0001aff4 [ 1] */, + 0x6bff0000 /* 0001affc - 0001affc [ 1] */, + 0x6bffc000 /* 0001afff - 0001afff [ 1] */, + 0x6c48c00e /* 0001b123 - 0001b131 [ 15] */, + 0x6c4cc01c /* 0001b133 - 0001b14f [ 29] */, + 0x6c54c001 /* 0001b153 - 0001b154 [ 2] */, + 0x6c55800d /* 0001b156 - 0001b163 [ 14] */, + 0x6c5a0007 /* 0001b168 - 0001b16f [ 8] */, + 0x6cbf0903 /* 0001b2fc - 0001bbff [ 2308] */, + 0x6f1ac004 /* 0001bc6b - 0001bc6f [ 5] */, + 0x6f1f4002 /* 0001bc7d - 0001bc7f [ 3] */, + 0x6f224006 /* 0001bc89 - 0001bc8f [ 7] */, + 0x6f268001 /* 0001bc9a - 0001bc9b [ 2] */, + 0x6f28125f /* 0001bca0 - 0001ceff [ 4704] */, + 0x73cb8001 /* 0001cf2e - 0001cf2f [ 2] */, + 0x73d1c008 /* 0001cf47 - 0001cf4f [ 9] */, + 0x73f1003b /* 0001cfc4 - 0001cfff [ 60] */, + 0x743d8009 /* 0001d0f6 - 0001d0ff [ 10] */, + 0x7449c001 /* 0001d127 - 0001d128 [ 2] */, + 0x745cc007 /* 0001d173 - 0001d17a [ 8] */, + 0x747ac014 /* 0001d1eb - 0001d1ff [ 21] */, + 0x74918079 /* 0001d246 - 0001d2bf [ 122] */, + 0x74b5000b /* 0001d2d4 - 0001d2df [ 12] */, + 0x74bd000b /* 0001d2f4 - 0001d2ff [ 12] */, + 0x74d5c008 /* 0001d357 - 0001d35f [ 9] */, + 0x74de4086 /* 0001d379 - 0001d3ff [ 135] */, + 0x75154000 /* 0001d455 - 0001d455 [ 1] */, + 0x75274000 /* 0001d49d - 0001d49d [ 1] */, + 0x75280001 /* 0001d4a0 - 0001d4a1 [ 2] */, + 0x7528c001 /* 0001d4a3 - 0001d4a4 [ 2] */, + 0x7529c001 /* 0001d4a7 - 0001d4a8 [ 2] */, + 0x752b4000 /* 0001d4ad - 0001d4ad [ 1] */, + 0x752e8000 /* 0001d4ba - 0001d4ba [ 1] */, + 0x752f0000 /* 0001d4bc - 0001d4bc [ 1] */, + 0x75310000 /* 0001d4c4 - 0001d4c4 [ 1] */, + 0x75418000 /* 0001d506 - 0001d506 [ 1] */, + 0x7542c001 /* 0001d50b - 0001d50c [ 2] */, + 0x75454000 /* 0001d515 - 0001d515 [ 1] */, + 0x75474000 /* 0001d51d - 0001d51d [ 1] */, + 0x754e8000 /* 0001d53a - 0001d53a [ 1] */, + 0x754fc000 /* 0001d53f - 0001d53f [ 1] */, + 0x75514000 /* 0001d545 - 0001d545 [ 1] */, + 0x7551c002 /* 0001d547 - 0001d549 [ 3] */, + 0x75544000 /* 0001d551 - 0001d551 [ 1] */, + 0x75a98001 /* 0001d6a6 - 0001d6a7 [ 2] */, + 0x75f30001 /* 0001d7cc - 0001d7cd [ 2] */, + 0x76a3000e /* 0001da8c - 0001da9a [ 15] */, + 0x76a80000 /* 0001daa0 - 0001daa0 [ 1] */, + 0x76ac044f /* 0001dab0 - 0001deff [ 1104] */, + 0x77c7c005 /* 0001df1f - 0001df24 [ 6] */, + 0x77cac0d4 /* 0001df2b - 0001dfff [ 213] */, + 0x7801c000 /* 0001e007 - 0001e007 [ 1] */, + 0x78064001 /* 0001e019 - 0001e01a [ 2] */, + 0x78088000 /* 0001e022 - 0001e022 [ 1] */, + 0x78094000 /* 0001e025 - 0001e025 [ 1] */, + 0x780ac004 /* 0001e02b - 0001e02f [ 5] */, + 0x781b8020 /* 0001e06e - 0001e08e [ 33] */, + 0x7824006f /* 0001e090 - 0001e0ff [ 112] */, + 0x784b4002 /* 0001e12d - 0001e12f [ 3] */, + 0x784f8001 /* 0001e13e - 0001e13f [ 2] */, + 0x78528003 /* 0001e14a - 0001e14d [ 4] */, + 0x7854013f /* 0001e150 - 0001e28f [ 320] */, + 0x78abc010 /* 0001e2af - 0001e2bf [ 17] */, + 0x78be8004 /* 0001e2fa - 0001e2fe [ 5] */, + 0x78c001cf /* 0001e300 - 0001e4cf [ 464] */, + 0x793e82e5 /* 0001e4fa - 0001e7df [ 742] */, + 0x79f9c000 /* 0001e7e7 - 0001e7e7 [ 1] */, + 0x79fb0000 /* 0001e7ec - 0001e7ec [ 1] */, + 0x79fbc000 /* 0001e7ef - 0001e7ef [ 1] */, + 0x79ffc000 /* 0001e7ff - 0001e7ff [ 1] */, + 0x7a314001 /* 0001e8c5 - 0001e8c6 [ 2] */, + 0x7a35c028 /* 0001e8d7 - 0001e8ff [ 41] */, + 0x7a530003 /* 0001e94c - 0001e94f [ 4] */, + 0x7a568003 /* 0001e95a - 0001e95d [ 4] */, + 0x7a580310 /* 0001e960 - 0001ec70 [ 785] */, + 0x7b2d404b /* 0001ecb5 - 0001ed00 [ 76] */, + 0x7b4f80c1 /* 0001ed3e - 0001edff [ 194] */, + 0x7b810000 /* 0001ee04 - 0001ee04 [ 1] */, + 0x7b880000 /* 0001ee20 - 0001ee20 [ 1] */, + 0x7b88c000 /* 0001ee23 - 0001ee23 [ 1] */, + 0x7b894001 /* 0001ee25 - 0001ee26 [ 2] */, + 0x7b8a0000 /* 0001ee28 - 0001ee28 [ 1] */, + 0x7b8cc000 /* 0001ee33 - 0001ee33 [ 1] */, + 0x7b8e0000 /* 0001ee38 - 0001ee38 [ 1] */, + 0x7b8e8000 /* 0001ee3a - 0001ee3a [ 1] */, + 0x7b8f0005 /* 0001ee3c - 0001ee41 [ 6] */, + 0x7b90c003 /* 0001ee43 - 0001ee46 [ 4] */, + 0x7b920000 /* 0001ee48 - 0001ee48 [ 1] */, + 0x7b928000 /* 0001ee4a - 0001ee4a [ 1] */, + 0x7b930000 /* 0001ee4c - 0001ee4c [ 1] */, + 0x7b940000 /* 0001ee50 - 0001ee50 [ 1] */, + 0x7b94c000 /* 0001ee53 - 0001ee53 [ 1] */, + 0x7b954001 /* 0001ee55 - 0001ee56 [ 2] */, + 0x7b960000 /* 0001ee58 - 0001ee58 [ 1] */, + 0x7b968000 /* 0001ee5a - 0001ee5a [ 1] */, + 0x7b970000 /* 0001ee5c - 0001ee5c [ 1] */, + 0x7b978000 /* 0001ee5e - 0001ee5e [ 1] */, + 0x7b980000 /* 0001ee60 - 0001ee60 [ 1] */, + 0x7b98c000 /* 0001ee63 - 0001ee63 [ 1] */, + 0x7b994001 /* 0001ee65 - 0001ee66 [ 2] */, + 0x7b9ac000 /* 0001ee6b - 0001ee6b [ 1] */, + 0x7b9cc000 /* 0001ee73 - 0001ee73 [ 1] */, + 0x7b9e0000 /* 0001ee78 - 0001ee78 [ 1] */, + 0x7b9f4000 /* 0001ee7d - 0001ee7d [ 1] */, + 0x7b9fc000 /* 0001ee7f - 0001ee7f [ 1] */, + 0x7ba28000 /* 0001ee8a - 0001ee8a [ 1] */, + 0x7ba70004 /* 0001ee9c - 0001eea0 [ 5] */, + 0x7ba90000 /* 0001eea4 - 0001eea4 [ 1] */, + 0x7baa8000 /* 0001eeaa - 0001eeaa [ 1] */, + 0x7baf0033 /* 0001eebc - 0001eeef [ 52] */, + 0x7bbc810d /* 0001eef2 - 0001efff [ 270] */, + 0x7c0b0003 /* 0001f02c - 0001f02f [ 4] */, + 0x7c25000b /* 0001f094 - 0001f09f [ 12] */, + 0x7c2bc001 /* 0001f0af - 0001f0b0 [ 2] */, + 0x7c300000 /* 0001f0c0 - 0001f0c0 [ 1] */, + 0x7c340000 /* 0001f0d0 - 0001f0d0 [ 1] */, + 0x7c3d8009 /* 0001f0f6 - 0001f0ff [ 10] */, + 0x7c6b8037 /* 0001f1ae - 0001f1e5 [ 56] */, + 0x7c80c00c /* 0001f203 - 0001f20f [ 13] */, + 0x7c8f0003 /* 0001f23c - 0001f23f [ 4] */, + 0x7c924006 /* 0001f249 - 0001f24f [ 7] */, + 0x7c94800d /* 0001f252 - 0001f25f [ 14] */, + 0x7c998099 /* 0001f266 - 0001f2ff [ 154] */, + 0x7db60003 /* 0001f6d8 - 0001f6db [ 4] */, + 0x7dbb4002 /* 0001f6ed - 0001f6ef [ 3] */, + 0x7dbf4002 /* 0001f6fd - 0001f6ff [ 3] */, + 0x7dddc003 /* 0001f777 - 0001f77a [ 4] */, + 0x7df68005 /* 0001f7da - 0001f7df [ 6] */, + 0x7dfb0003 /* 0001f7ec - 0001f7ef [ 4] */, + 0x7dfc400e /* 0001f7f1 - 0001f7ff [ 15] */, + 0x7e030003 /* 0001f80c - 0001f80f [ 4] */, + 0x7e120007 /* 0001f848 - 0001f84f [ 8] */, + 0x7e168005 /* 0001f85a - 0001f85f [ 6] */, + 0x7e220007 /* 0001f888 - 0001f88f [ 8] */, + 0x7e2b8001 /* 0001f8ae - 0001f8af [ 2] */, + 0x7e2c804d /* 0001f8b2 - 0001f8ff [ 78] */, + 0x7e95000b /* 0001fa54 - 0001fa5f [ 12] */, + 0x7e9b8001 /* 0001fa6e - 0001fa6f [ 2] */, + 0x7e9f4002 /* 0001fa7d - 0001fa7f [ 3] */, + 0x7ea24006 /* 0001fa89 - 0001fa8f [ 7] */, + 0x7eaf8000 /* 0001fabe - 0001fabe [ 1] */, + 0x7eb18007 /* 0001fac6 - 0001facd [ 8] */, + 0x7eb70003 /* 0001fadc - 0001fadf [ 4] */, + 0x7eba4006 /* 0001fae9 - 0001faef [ 7] */, + 0x7ebe4006 /* 0001faf9 - 0001faff [ 7] */, + 0x7ee4c000 /* 0001fb93 - 0001fb93 [ 1] */, + 0x7ef2c024 /* 0001fbcb - 0001fbef [ 37] */, + 0x7efe8405 /* 0001fbfa - 0001ffff [ 1030] */, + 0xa9b8001f /* 0002a6e0 - 0002a6ff [ 32] */, + 0xadce8005 /* 0002b73a - 0002b73f [ 6] */, + 0xae078001 /* 0002b81e - 0002b81f [ 2] */, + 0xb3a8800d /* 0002cea2 - 0002ceaf [ 14] */, + 0xbaf8400e /* 0002ebe1 - 0002ebef [ 15] */, + 0xbb9789a1 /* 0002ee5e - 0002f7ff [ 2466] */, + 0xbe8785e1 /* 0002fa1e - 0002ffff [ 1506] */, + 0xc4d2c004 /* 0003134b - 0003134f [ 5] */}; +/// Returns whether the code unit needs to be escaped. +/// /// At the end of the valid Unicode code points space a lot of code points are /// either reserved or a noncharacter. Adding all these entries to the -/// lookup table would add 446 entries to the table (in Unicode 14). -/// Instead the only the start of the region is stored, every code point in -/// this region needs to be escaped. -_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __unallocated_region_lower_bound = 0x000e01f0; +/// lookup table would greatly increase the size of the table. Instead these +/// entries are manually processed. In this large area of reserved code points, +/// there is a small area of extended graphemes that should not be escaped +/// unconditionally. This is also manually coded. See the generation script for +/// more details. -/// Returns whether the code unit needs to be escaped. /// /// \pre The code point is a valid Unicode code point. [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool __needs_escape(const char32_t __code_point) noexcept { - // Since __unallocated_region_lower_bound contains the unshifted range do the - // comparison without shifting. - if (__code_point >= __unallocated_region_lower_bound) + + // The entries in the gap at the end. + if(__code_point >= 0x000e0100 && __code_point <= 0x000e01ef) + return false; + + // The entries at the end. + if (__code_point >= 0x000323b0) return true; - ptrdiff_t __i = std::ranges::upper_bound(__entries, (__code_point << 11) | 0x7ffu) - __entries; + ptrdiff_t __i = std::ranges::upper_bound(__entries, (__code_point << 14) | 0x3fffu) - __entries; if (__i == 0) return false; --__i; - uint32_t __upper_bound = (__entries[__i] >> 11) + (__entries[__i] & 0x7ffu); + uint32_t __upper_bound = (__entries[__i] >> 14) + (__entries[__i] & 0x3fffu); return __code_point <= __upper_bound; } diff --git a/libcxx/include/format b/libcxx/include/format index f1e87de0f830..07c2ba083199 100644 --- a/libcxx/include/format +++ b/libcxx/include/format @@ -193,6 +193,8 @@ namespace std { #include <__format/concepts.h> #include <__format/container_adaptor.h> #include <__format/enable_insertable.h> +#include <__format/escaped_output_table.h> +#include <__format/extended_grapheme_cluster_table.h> #include <__format/format_arg.h> #include <__format/format_arg_store.h> #include <__format/format_args.h> diff --git a/libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp b/libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp new file mode 100644 index 000000000000..5b1191642c9a --- /dev/null +++ b/libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp @@ -0,0 +1,102 @@ +//===----------------------------------------------------------------------===// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +// UNSUPPORTED: c++03, c++11, c++14, c++17, c++20 +// UNSUPPORTED: GCC-ALWAYS_INLINE-FIXME + +// + +// Tests the properties of the Unicode escaped output table. +// The libc++ algorithm has size and speed optimizations based on the properties +// of Unicode. This means updating the Unicode tables has a likilihood of +// breaking test. This is an assert; it requires validating whether the +// assumptions of the size and speed optimizations are still valid. + +#include +#include +#include +#include + +// Contains the entries for [format.string.escaped]/2.2.1.2.1 +// CE is a Unicode encoding and C corresponds to a UCS scalar value whose +// Unicode property General_Category has a value in the groups Separator (Z) +// or Other (C), as described by table 12 of UAX #44 +// +// Separator (Z) consists of General_Category +// - Zs Space_Separator, +// - Zl Line_Separator, +// - Zp Paragraph_Separator. +// +// Other (C) consists of General_Category +// - Cc Control, +// - Cf Format, +// - Cs Surrogate, +// - Co Private_Use, +// - Cn Unassigned. +inline constexpr int Zs = 17; +inline constexpr int Zl = 1; +inline constexpr int Zp = 1; +inline constexpr int Z = Zs + Zl + Zp; + +inline constexpr int Cc = 65; +inline constexpr int Cf = 170; +inline constexpr int Cs = 2'048; +inline constexpr int Co = 137'468; +inline constexpr int Cn = 824'718; +inline constexpr int C = Cc + Cf + Cs + Co + Cn; + +// This is the final part of the Unicode properties table: +// +// 31350..323AF ; Lo # [4192] CJK UNIFIED IDEOGRAPH-31350..CJK UNIFIED IDEOGRAPH-323AF +// 323B0..E0000 ; Cn # [711761] .. +// E0001 ; Cf # LANGUAGE TAG +// E0002..E001F ; Cn # [30] .. +// E0020..E007F ; Cf # [96] TAG SPACE..CANCEL TAG +// E0080..E00FF ; Cn # [128] .. +// E0100..E01EF ; Mn # [240] VARIATION SELECTOR-17..VARIATION SELECTOR-256 +// E01F0..EFFFF ; Cn # [65040] .. +// F0000..FFFFD ; Co # [65534] .. +// FFFFE..FFFFF ; Cn # [2] .. +// 100000..10FFFD; Co # [65534] .. +// 10FFFE..10FFFF; Cn # [2] .. +// +// It can be observed all entries in the range 323B0..10FFFF are in the +// categories Cf, Co, Cn, except a small range with the property Mn. +// In order to reduce the size of the table only the entires in the range +// [0000, 323B0) are stored in the table. The entries in the range +// [323B0, 10FFFF] use a hand-crafted algorithm. +// +// This means a number of entries are omitted +inline constexpr int excluded = ((0x10FFFF - 0x323B0) + 1) - 240; + +inline constexpr int entries = Z + C - excluded; + +static constexpr int count_entries() { + return std::transform_reduce( + std::begin(std::__escaped_output_table::__entries), + std::end(std::__escaped_output_table::__entries), + 0, + std::plus{}, + [](auto entry) { return 1 + static_cast(entry & 0x3fffu); }); +} +static_assert(count_entries() == entries); + +int main(int, char**) { + for (char32_t c = 0x31350; c <= 0x323AF; ++c) // 31350..323AF ; Lo # [4192] + assert(std::__escaped_output_table::__needs_escape(c) == false); + + for (char32_t c = 0x323B0; c <= 0xE00FF; ++c) // 323B0..E00FF ; C + assert(std::__escaped_output_table::__needs_escape(c) == true); + + for (char32_t c = 0xE0100; c <= 0xE01EF; ++c) // E0100..E01EF ; Mn # [240] + assert(std::__escaped_output_table::__needs_escape(c) == false); + + for (char32_t c = 0xE01F0; c <= 0x10FFFF; ++c) // E01F0..10FFFF; C + assert(std::__escaped_output_table::__needs_escape(c) == true); + + return 0; +} diff --git a/libcxx/utils/generate_escaped_output_table.py b/libcxx/utils/generate_escaped_output_table.py index a11ce259096d..523a0be3a451 100755 --- a/libcxx/utils/generate_escaped_output_table.py +++ b/libcxx/utils/generate_escaped_output_table.py @@ -113,34 +113,41 @@ DATA_ARRAY_TEMPLATE = """ /// table lacks a property, thus having more bits available for the size. /// /// The data has 2 values: -/// - bits [0, 10] The size of the range, allowing 2048 elements. -/// - bits [11, 31] The lower bound code point of the range. The upper bound of -/// the range is lower bound + size. +/// - bits [0, 13] The size of the range, allowing 16384 elements. +/// - bits [14, 31] The lower bound code point of the range. The upper bound of +/// the range is lower bound + size. Note the code expects code units the fit +/// into 18 bits, instead of the 21 bits needed for the full Unicode range. _LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __entries[{size}] = {{ {entries}}}; +/// Returns whether the code unit needs to be escaped. +/// /// At the end of the valid Unicode code points space a lot of code points are /// either reserved or a noncharacter. Adding all these entries to the -/// lookup table would add 446 entries to the table (in Unicode 14). -/// Instead the only the start of the region is stored, every code point in -/// this region needs to be escaped. -_LIBCPP_HIDE_FROM_ABI inline constexpr uint32_t __unallocated_region_lower_bound = 0x{unallocated:08x}; +/// lookup table would greatly increase the size of the table. Instead these +/// entries are manually processed. In this large area of reserved code points, +/// there is a small area of extended graphemes that should not be escaped +/// unconditionally. This is also manually coded. See the generation script for +/// more details. -/// Returns whether the code unit needs to be escaped. /// /// \pre The code point is a valid Unicode code point. [[nodiscard]] _LIBCPP_HIDE_FROM_ABI constexpr bool __needs_escape(const char32_t __code_point) noexcept {{ - // Since __unallocated_region_lower_bound contains the unshifted range do the - // comparison without shifting. - if (__code_point >= __unallocated_region_lower_bound) + + // The entries in the gap at the end. + if(__code_point >= 0x{gap_lower:08x} && __code_point <= 0x{gap_upper:08x}) + return false; + + // The entries at the end. + if (__code_point >= 0x{unallocated:08x}) return true; - ptrdiff_t __i = std::ranges::upper_bound(__entries, (__code_point << 11) | 0x7ffu) - __entries; + ptrdiff_t __i = std::ranges::upper_bound(__entries, (__code_point << 14) | 0x3fffu) - __entries; if (__i == 0) return false; --__i; - uint32_t __upper_bound = (__entries[__i] >> 11) + (__entries[__i] & 0x7ffu); + uint32_t __upper_bound = (__entries[__i] >> 14) + (__entries[__i] & 0x3fffu); return __code_point <= __upper_bound; }} """ @@ -245,28 +252,33 @@ def property_ranges_to_table(ranges: list[PropertyRange]) -> list[Entry]: while True: e = Entry(range.lower, range.upper - range.lower) - if e.offset <= 2047: + if e.offset <= 16383: result.append(e) break - e.offset = 2047 + e.offset = 16383 result.append(e) - range.lower += 2048 + range.lower += 16384 return result cpp_entrytemplate = " 0x{:08x} /* {:08x} - {:08x} [{:>5}] */" -def generate_cpp_data(ranges: list[PropertyRange], unallocated: int) -> str: +def generate_cpp_data( + ranges: list[PropertyRange], unallocated: int, gap_lower: int, gap_upper: int +) -> str: result = StringIO() table = property_ranges_to_table(ranges) + # Validates all entries fit in 18 bits. + for x in table: + assert x.lower + x.offset < 0x3FFFF result.write( DATA_ARRAY_TEMPLATE.format( size=len(table), entries=",\n".join( [ cpp_entrytemplate.format( - x.lower << 11 | x.offset, + x.lower << 14 | x.offset, x.lower, x.lower + x.offset, x.offset + 1, @@ -275,6 +287,8 @@ def generate_cpp_data(ranges: list[PropertyRange], unallocated: int) -> str: ] ), unallocated=unallocated, + gap_lower=gap_lower, + gap_upper=gap_upper, ) ) @@ -305,22 +319,28 @@ def generate_data_tables() -> str: data = compactPropertyRanges(sorted(properties, key=lambda x: x.lower)) - # The last entry is large. In Unicode 14 it contains the entries - # 3134B..0FFFF 912564 elements - # This are 446 entries of 1325 entries in the table. - # Based on the nature of these entries it is expected they remain for the - # forseeable future. Therefore we only store the lower bound of this section. - # - # When this region becomes substantially smaller we need to investigate - # this design. - # - # Due to P2713R1 Escaping improvements in std::format the range + # The output table has two large entries at the end, with a small "gap" # E0100..E01EF ; Grapheme_Extend # Mn [240] VARIATION SELECTOR-17..VARIATION SELECTOR-256 - # is no longer part of these entries. This causes an increase in the size - # of the table. - assert data[-1].upper == 0x10FFFF - - return "\n".join([generate_cpp_data(data[:-1], data[-1].lower)]) + # Based on Unicode 15.1.0: + # - Encoding all these entries in the table requires 1173 entries. + # - Manually handling these last two blocks reduces the size to 729 entries. + # This not only reduces the binary size, but also improves the performance + # by having fewer elements to search. + # The exact entries may differ between Unicode versions. When these numbers + # change the test needs to be updated too. + # libcxx/test/libcxx/utilities/format/format.string/format.string.std/escaped_output.pass.cpp + assert (data[-2].lower) == 0x323B0 + assert (data[-2].upper) == 0xE00FF + assert (data[-1].lower) == 0xE01F0 + assert (data[-1].upper) == 0x10FFFF + + return "\n".join( + [ + generate_cpp_data( + data[:-2], data[-2].lower, data[-2].upper + 1, data[-1].lower - 1 + ) + ] + ) if __name__ == "__main__": -- GitLab From 367efa0b0542e6f4171e8c914728946c302ab24b Mon Sep 17 00:00:00 2001 From: Chuanqi Xu Date: Sun, 28 Apr 2024 17:50:49 +0800 Subject: [PATCH 151/301] [NFC] [Modules] Avoid scanning the stored decl list twice when replace external decls This patch fixes a FIXME in StoredDeclList::replaceExternalDecls. StoredDeclList::replaceExternalDecls will iterate the list first to remove some declarations and iterate the list again to get the tail of the list. It should be better to avoid the second iterations. --- .../include/clang/AST/DeclContextInternals.h | 31 ++++++++++--------- 1 file changed, 17 insertions(+), 14 deletions(-) diff --git a/clang/include/clang/AST/DeclContextInternals.h b/clang/include/clang/AST/DeclContextInternals.h index 42cc677f8213..e169c4859219 100644 --- a/clang/include/clang/AST/DeclContextInternals.h +++ b/clang/include/clang/AST/DeclContextInternals.h @@ -42,11 +42,12 @@ class StoredDeclsList { /// external declarations. DeclsAndHasExternalTy Data; - template - void erase_if(Fn ShouldErase) { + template DeclListNode::Decls *erase_if(Fn ShouldErase) { Decls List = Data.getPointer(); + if (!List) - return; + return nullptr; + ASTContext &C = getASTContext(); DeclListNode::Decls NewHead = nullptr; DeclListNode::Decls *NewLast = nullptr; @@ -79,6 +80,17 @@ class StoredDeclsList { Data.setPointer(NewHead); assert(llvm::none_of(getLookupResult(), ShouldErase) && "Still exists!"); + + if (!Data.getPointer()) + // All declarations are erased. + return nullptr; + else if (NewHead.is()) + // The list only contains a declaration, the header itself. + return (DeclListNode::Decls *)&Data; + else { + assert(NewLast && NewLast->is() && "Not the tail?"); + return NewLast; + } } void erase(NamedDecl *ND) { @@ -161,7 +173,7 @@ public: void replaceExternalDecls(ArrayRef Decls) { // Remove all declarations that are either external or are replaced with // external declarations with higher visibilities. - erase_if([Decls](NamedDecl *ND) { + DeclListNode::Decls *Tail = erase_if([Decls](NamedDecl *ND) { if (ND->isFromASTFile()) return true; // FIXME: Can we get rid of this loop completely? @@ -189,24 +201,15 @@ public: DeclsAsList = Node; } - DeclListNode::Decls Head = Data.getPointer(); - if (Head.isNull()) { + if (!Data.getPointer()) { Data.setPointer(DeclsAsList); return; } - // Find the end of the existing list. - // FIXME: It would be possible to preserve information from erase_if to - // avoid this rescan looking for the end of the list. - DeclListNode::Decls *Tail = &Head; - while (DeclListNode *Node = Tail->dyn_cast()) - Tail = &Node->Rest; - // Append the Decls. DeclListNode *Node = C.AllocateDeclListNode(Tail->get()); Node->Rest = DeclsAsList; *Tail = Node; - Data.setPointer(Head); } /// Return the list of all the decls. -- GitLab From bfd269d0d0d6cb58235a838eb659eef97e4f2ebf Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Sun, 28 Apr 2024 06:35:59 -0500 Subject: [PATCH 152/301] [AMDGPU] Fix test failing on Windows for `ld.lld.exe` --- clang/test/Driver/amdgpu-toolchain.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/test/Driver/amdgpu-toolchain.c b/clang/test/Driver/amdgpu-toolchain.c index faaff05004f6..8ab6a0713147 100644 --- a/clang/test/Driver/amdgpu-toolchain.c +++ b/clang/test/Driver/amdgpu-toolchain.c @@ -27,4 +27,4 @@ // RUN: %clang -### --target=amdgcn-amd-amdhsa -mcpu=gfx906 -nogpulib \ // RUN: -fuse-ld=ld %s 2>&1 | FileCheck -check-prefixes=LD %s -// LD: ld.lld" +// LD: ld.lld -- GitLab From 46321395ce5c13079322ab0d965967fb60472fd2 Mon Sep 17 00:00:00 2001 From: Kiran Chandramohan Date: Sun, 28 Apr 2024 12:51:56 +0100 Subject: [PATCH 153/301] [Flang][OpenMP] Remove deprecated FIR lowering tests (#90188) Remove OpenMP FIR lowering tests. These are now replaced by HLFIR based tests. This might hopefully speedup testing as well. --- flang/test/Lower/OpenMP/FIR/array-bounds.f90 | 121 ---- .../test/Lower/OpenMP/FIR/atomic-capture.f90 | 119 ---- flang/test/Lower/OpenMP/FIR/atomic-read.f90 | 80 --- flang/test/Lower/OpenMP/FIR/atomic-update.f90 | 141 ----- flang/test/Lower/OpenMP/FIR/atomic-write.f90 | 77 --- flang/test/Lower/OpenMP/FIR/copyin.f90 | 358 ----------- flang/test/Lower/OpenMP/FIR/critical.f90 | 38 -- .../Lower/OpenMP/FIR/declare-target-data.f90 | 88 --- .../FIR/declare-target-func-and-subr.f90 | 178 ------ ...arget-implicit-func-and-subr-cap-enter.f90 | 192 ------ ...lare-target-implicit-func-and-subr-cap.f90 | 218 ------- .../test/Lower/OpenMP/FIR/default-clause.f90 | 281 --------- .../delayed-privatization-firstprivate.f90 | 32 - .../FIR/delayed-privatization-private.f90 | 41 -- .../OpenMP/FIR/firstprivate-commonblock.f90 | 30 - flang/test/Lower/OpenMP/FIR/flush.f90 | 45 -- flang/test/Lower/OpenMP/FIR/if-clause.f90 | 498 ---------------- flang/test/Lower/OpenMP/FIR/is-device.f90 | 14 - .../OpenMP/FIR/lastprivate-commonblock.f90 | 49 -- flang/test/Lower/OpenMP/FIR/location.f90 | 71 --- flang/test/Lower/OpenMP/FIR/loop-combined.f90 | 83 --- .../Lower/OpenMP/FIR/map-component-ref.f90 | 33 -- flang/test/Lower/OpenMP/FIR/master.f90 | 100 ---- .../FIR/omp-declare-target-program-var.f90 | 12 - flang/test/Lower/OpenMP/FIR/omp-is-gpu.f90 | 16 - .../test/Lower/OpenMP/FIR/ordered-threads.f90 | 40 -- .../parallel-firstprivate-clause-scalar.f90 | 159 ----- .../parallel-lastprivate-clause-scalar.f90 | 261 --------- .../FIR/parallel-private-clause-fixes.f90 | 84 --- .../OpenMP/FIR/parallel-private-clause.f90 | 387 ------------ .../FIR/parallel-reduction-add-byref.f90 | 117 ---- .../OpenMP/FIR/parallel-reduction-add.f90 | 105 ---- .../Lower/OpenMP/FIR/parallel-sections.f90 | 65 -- .../OpenMP/FIR/parallel-wsloop-firstpriv.f90 | 69 --- .../test/Lower/OpenMP/FIR/parallel-wsloop.f90 | 297 ---------- flang/test/Lower/OpenMP/FIR/parallel.f90 | 211 ------- .../Lower/OpenMP/FIR/pre-fir-tree-loop.f90 | 70 --- .../test/Lower/OpenMP/FIR/pre-fir-tree01.f90 | 19 - .../Lower/OpenMP/FIR/private-commonblock.f90 | 109 ---- .../test/Lower/OpenMP/FIR/requires-common.f90 | 19 - .../Lower/OpenMP/FIR/requires-notarget.f90 | 14 - flang/test/Lower/OpenMP/FIR/requires.f90 | 14 - flang/test/Lower/OpenMP/FIR/rtl-flags.f90 | 39 -- flang/test/Lower/OpenMP/FIR/sections-pft.f90 | 91 --- flang/test/Lower/OpenMP/FIR/sections.f90 | 288 --------- flang/test/Lower/OpenMP/FIR/simd.f90 | 176 ------ .../test/Lower/OpenMP/FIR/simple-barrier.f90 | 6 - flang/test/Lower/OpenMP/FIR/single.f90 | 123 ---- .../Lower/OpenMP/FIR/stop-stmt-in-region.f90 | 154 ----- flang/test/Lower/OpenMP/FIR/target.f90 | 554 ------------------ .../Lower/OpenMP/FIR/target_cpu_features.f90 | 19 - flang/test/Lower/OpenMP/FIR/task.f90 | 237 -------- flang/test/Lower/OpenMP/FIR/taskgroup.f90 | 21 - flang/test/Lower/OpenMP/FIR/taskwait.f90 | 12 - flang/test/Lower/OpenMP/FIR/taskyield.f90 | 12 - flang/test/Lower/OpenMP/FIR/teams.f90 | 117 ---- .../threadprivate-char-array-chararray.f90 | 46 -- .../OpenMP/FIR/threadprivate-commonblock.f90 | 91 --- .../threadprivate-integer-different-kinds.f90 | 67 --- .../OpenMP/FIR/threadprivate-non-global.f90 | 91 --- .../FIR/threadprivate-pointer-allocatable.f90 | 51 -- ...ivate-real-logical-complex-derivedtype.f90 | 58 -- .../FIR/threadprivate-use-association-2.f90 | 39 -- .../FIR/threadprivate-use-association.f90 | 74 --- flang/test/Lower/OpenMP/FIR/unstructured.f90 | 365 ------------ flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 | 84 --- .../test/Lower/OpenMP/FIR/wsloop-collapse.f90 | 66 --- .../Lower/OpenMP/FIR/wsloop-monotonic.f90 | 38 -- .../Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 | 39 -- .../test/Lower/OpenMP/FIR/wsloop-ordered.f90 | 46 -- .../OpenMP/FIR/wsloop-reduction-add-byref.f90 | 413 ------------- .../Lower/OpenMP/FIR/wsloop-reduction-add.f90 | 388 ------------ .../FIR/wsloop-reduction-iand-byref.f90 | 48 -- .../OpenMP/FIR/wsloop-reduction-iand.f90 | 38 -- .../FIR/wsloop-reduction-ieor-byref.f90 | 47 -- .../OpenMP/FIR/wsloop-reduction-ieor.f90 | 38 -- .../OpenMP/FIR/wsloop-reduction-ior-byref.f90 | 47 -- .../Lower/OpenMP/FIR/wsloop-reduction-ior.f90 | 38 -- .../wsloop-reduction-logical-eqv-byref.f90 | 193 ------ .../FIR/wsloop-reduction-logical-eqv.f90 | 187 ------ .../wsloop-reduction-logical-neqv-byref.f90 | 195 ------ .../FIR/wsloop-reduction-logical-neqv.f90 | 189 ------ .../OpenMP/FIR/wsloop-reduction-max-byref.f90 | 95 --- .../Lower/OpenMP/FIR/wsloop-reduction-max.f90 | 84 --- .../OpenMP/FIR/wsloop-reduction-min-byref.f90 | 95 --- .../Lower/OpenMP/FIR/wsloop-reduction-min.f90 | 84 --- flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 | 37 -- .../test/Lower/OpenMP/FIR/wsloop-variable.f90 | 187 ------ flang/test/Lower/OpenMP/FIR/wsloop.f90 | 78 --- 89 files changed, 10440 deletions(-) delete mode 100644 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delete mode 100644 flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 delete mode 100644 flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 delete mode 100644 flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 delete mode 100644 flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 delete mode 100644 flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 delete mode 100644 flang/test/Lower/OpenMP/FIR/wsloop.f90 diff --git a/flang/test/Lower/OpenMP/FIR/array-bounds.f90 b/flang/test/Lower/OpenMP/FIR/array-bounds.f90 deleted file mode 100644 index c2bb7a94712b..000000000000 --- a/flang/test/Lower/OpenMP/FIR/array-bounds.f90 +++ /dev/null @@ -1,121 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes=HOST,ALL -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefixes=DEVICE,ALL - -!ALL-LABEL: func.func @_QPread_write_section( -!ALL: %[[ITER:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFread_write_sectionEi"} -!ALL: %[[READ:.*]] = fir.address_of(@_QFread_write_sectionEsp_read) : !fir.ref> -!ALL: %[[C10:.*]] = arith.constant 10 : index -!ALL: %[[WRITE:.*]] = fir.address_of(@_QFread_write_sectionEsp_write) : !fir.ref> -!ALL: %[[C10_0:.*]] = arith.constant 10 : index -!ALL: %[[C1:.*]] = arith.constant 1 : index -!ALL: %[[C2:.*]] = arith.constant 1 : index -!ALL: %[[C3:.*]] = arith.constant 4 : index -!ALL: %[[BOUNDS0:.*]] = omp.map.bounds lower_bound(%[[C2]] : index) upper_bound(%[[C3]] : index) extent(%[[C10]] : index) stride(%[[C1]] : index) start_idx(%[[C1]] : index) -!ALL: %[[MAP0:.*]] = omp.map.info var_ptr(%[[READ]] : !fir.ref>, !fir.array<10xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS0]]) -> !fir.ref> {name = "sp_read(2:5)"} -!ALL: %[[C4:.*]] = arith.constant 1 : index -!ALL: %[[C5:.*]] = arith.constant 1 : index -!ALL: %[[C6:.*]] = arith.constant 4 : index -!ALL: %[[BOUNDS1:.*]] = omp.map.bounds lower_bound(%[[C5]] : index) upper_bound(%[[C6]] : index) extent(%[[C10_0]] : index) stride(%[[C4]] : index) start_idx(%[[C4]] : index) -!ALL: %[[MAP1:.*]] = omp.map.info var_ptr(%[[WRITE]] : !fir.ref>, !fir.array<10xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS1]]) -> !fir.ref> {name = "sp_write(2:5)"} -!ALL: %[[MAP2:.*]] = omp.map.info var_ptr(%[[ITER]] : !fir.ref, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !fir.ref {name = "i"} -!ALL: omp.target map_entries(%[[MAP0]] -> %{{.*}}, %[[MAP1]] -> %{{.*}}, %[[MAP2]] -> %{{.*}} : !fir.ref>, !fir.ref>, !fir.ref) { - -subroutine read_write_section() - integer :: sp_read(10) = (/1,2,3,4,5,6,7,8,9,10/) - integer :: sp_write(10) = (/0,0,0,0,0,0,0,0,0,0/) - -!$omp target map(tofrom:sp_read(2:5)) map(tofrom:sp_write(2:5)) - do i = 2, 5 - sp_write(i) = sp_read(i) - end do -!$omp end target -end subroutine read_write_section - -module assumed_array_routines -contains -!ALL-LABEL: func.func @_QMassumed_array_routinesPassumed_shape_array( -!ALL-SAME: %[[ARG0:.*]]: !fir.box> {fir.bindc_name = "arr_read_write"}) -!ALL: %[[INTERMEDIATE_ALLOCA:.*]] = fir.alloca !fir.box> -!ALL: %[[ALLOCA:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QMassumed_array_routinesFassumed_shape_arrayEi"} -!ALL: %[[C0:.*]] = arith.constant 1 : index -!ALL: %[[C1:.*]] = arith.constant 0 : index -!ALL: %[[DIMS0:.*]]:3 = fir.box_dims %arg0, %[[C1]] : (!fir.box>, index) -> (index, index, index) -!ALL: %[[C3:.*]] = arith.constant 1 : index -!ALL: %[[C4:.*]] = arith.constant 4 : index -!ALL: %[[C0_1:.*]] = arith.constant 0 : index -!ALL: %[[DIMS1:.*]]:3 = fir.box_dims %arg0, %[[C0_1]] : (!fir.box>, index) -> (index, index, index) -!ALL: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%[[C3]] : index) upper_bound(%[[C4]] : index) extent(%[[DIMS1]]#1 : index) stride(%[[DIMS0]]#2 : index) start_idx(%[[C0]] : index) {stride_in_bytes = true} -!ALL: %[[BOXADDRADDR:.*]] = fir.box_offset %0 base_addr : (!fir.ref>>) -> !fir.llvm_ptr>> -!ALL: %[[MAP_MEMBER:.*]] = omp.map.info var_ptr(%0 : !fir.ref>>, !fir.array) var_ptr_ptr(%[[BOXADDRADDR]] : !fir.llvm_ptr>>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.llvm_ptr>> {name = ""} -!ALL: %[[MAP:.*]] = omp.map.info var_ptr(%0 : !fir.ref>>, !fir.box>) map_clauses(tofrom) capture(ByRef) members(%[[MAP_MEMBER]] : !fir.llvm_ptr>>) -> !fir.ref> {name = "arr_read_write(2:5)"} -!ALL: %[[MAP2:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !fir.ref {name = "i"} -!ALL: omp.target map_entries(%[[MAP_MEMBER]] -> %{{.*}}, %[[MAP]] -> %{{.*}}, %[[MAP2]] -> %{{.*}} : !fir.llvm_ptr>>, !fir.ref>, !fir.ref) { - subroutine assumed_shape_array(arr_read_write) - integer, intent(inout) :: arr_read_write(:) - - !$omp target map(tofrom:arr_read_write(2:5)) - do i = 2, 5 - arr_read_write(i) = i - end do - !$omp end target - end subroutine assumed_shape_array - -!ALL-LABEL: func.func @_QMassumed_array_routinesPassumed_size_array( -!ALL-SAME: %[[ARG0:.*]]: !fir.ref> {fir.bindc_name = "arr_read_write"}) -!ALL: %[[ALLOCA:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QMassumed_array_routinesFassumed_size_arrayEi"} -!ALL: %[[C0:.*]] = arith.constant 1 : index -!ALL: %[[C1:.*]] = arith.constant 1 : index -!ALL: %[[C2:.*]] = arith.constant 4 : index -!ALL: %[[DIFF:.*]] = arith.subi %[[C2]], %[[C1]] : index -!ALL: %[[EXT:.*]] = arith.addi %[[DIFF]], %[[C0]] : index -!ALL: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%[[C1]] : index) upper_bound(%[[C2]] : index) extent(%[[EXT]] : index) stride(%[[C0]] : index) start_idx(%[[C0]] : index) -!ALL: %[[MAP:.*]] = omp.map.info var_ptr(%[[ARG0]] : !fir.ref>, !fir.array) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "arr_read_write(2:5)"} -!ALL: %[[MAP2:.*]] = omp.map.info var_ptr(%[[ALLOCA]] : !fir.ref, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !fir.ref {name = "i"} -!ALL: omp.target map_entries(%[[MAP]] -> %{{.*}}, %[[MAP2]] -> %{{.*}} : !fir.ref>, !fir.ref) { - subroutine assumed_size_array(arr_read_write) - integer, intent(inout) :: arr_read_write(*) - - !$omp target map(tofrom:arr_read_write(2:5)) - do i = 2, 5 - arr_read_write(i) = i - end do - !$omp end target - end subroutine assumed_size_array -end module assumed_array_routines - -!DEVICE-NOT:func.func @_QPcall_assumed_shape_and_size_array() { - -!HOST-LABEL:func.func @_QPcall_assumed_shape_and_size_array() { -!HOST:%{{.*}} = arith.constant 20 : index -!HOST:%[[ALLOCA:.*]] = fir.alloca !fir.array<20xi32> {bindc_name = "arr_read_write", uniq_name = "_QFcall_assumed_shape_and_size_arrayEarr_read_write"} -!HOST:%{{.*}} = arith.constant 1 : i64 -!HOST:%{{.*}} = fir.convert %{{.*}} : (i64) -> index -!HOST:%{{.*}} = arith.constant 1 : i64 -!HOST:%{{.*}} = fir.convert %{{.*}} : (i64) -> index -!HOST:%{{.*}} = arith.constant 10 : i64 -!HOST:%{{.*}} = fir.convert %{{.*}} : (i64) -> index -!HOST:%[[SHAPE0:.*]] = fir.shape %{{.*}} : (index) -> !fir.shape<1> -!HOST:%[[SLICE0:.*]] = fir.slice %{{.*}}, %{{.*}}, %{{.*}} : (index, index, index) -> !fir.slice<1> -!HOST:%[[ARG0EMB:.*]] = fir.embox %[[ALLOCA]](%[[SHAPE0]]) [%[[SLICE0]]] : (!fir.ref>, !fir.shape<1>, !fir.slice<1>) -> !fir.box> -!HOST:%[[ARG0:.*]] = fir.convert %[[ARG0EMB]] : (!fir.box>) -> !fir.box> -!HOST:fir.call @_QMassumed_array_routinesPassumed_shape_array(%[[ARG0]]) fastmath : (!fir.box>) -> () -!HOST:%{{.*}} = arith.constant 10 : i64 -!HOST:%{{.*}} = fir.convert %{{.*}} : (i64) -> index -!HOST:%{{.*}} = arith.constant 1 : i64 -!HOST:%{{.*}} = fir.convert %{{.*}} : (i64) -> index -!HOST:%{{.*}} = arith.constant 20 : i64 -!HOST:%{{.*}} = fir.convert %{{.*}} : (i64) -> index -!HOST:%[[SHAPE1:.*]] = fir.shape %{{.*}} : (index) -> !fir.shape<1> -!HOST:%[[SLICE1:.*]] = fir.slice %{{.*}}, %{{.*}}, %{{.*}} : (index, index, index) -> !fir.slice<1> -!HOST:%[[ARG1EMB:.*]] = fir.embox %[[ALLOCA]](%[[SHAPE1]]) [%[[SLICE1]]] : (!fir.ref>, !fir.shape<1>, !fir.slice<1>) -> !fir.box> -!HOST:%[[ADDROF:.*]] = fir.box_addr %[[ARG1EMB]] : (!fir.box>) -> !fir.ref> -!HOST:%[[ARG1:.*]] = fir.convert %[[ADDROF]] : (!fir.ref>) -> !fir.ref> -!HOST:fir.call @_QMassumed_array_routinesPassumed_size_array(%[[ARG1]]) fastmath : (!fir.ref>) -> () -!HOST:return -!HOST:} -subroutine call_assumed_shape_and_size_array - use assumed_array_routines - integer :: arr_read_write(20) - call assumed_shape_array(arr_read_write(1:10)) - call assumed_size_array(arr_read_write(10:20)) -end subroutine call_assumed_shape_and_size_array diff --git a/flang/test/Lower/OpenMP/FIR/atomic-capture.f90 b/flang/test/Lower/OpenMP/FIR/atomic-capture.f90 deleted file mode 100644 index 9b94214b9da8..000000000000 --- a/flang/test/Lower/OpenMP/FIR/atomic-capture.f90 +++ /dev/null @@ -1,119 +0,0 @@ -! REQUIRES: openmp_runtime - -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -! This test checks the lowering of atomic capture - -program OmpAtomicCapture - use omp_lib - integer :: x, y - -!CHECK: %[[X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"} -!CHECK: %[[Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: omp.atomic.capture memory_order(release) { -!CHECK: omp.atomic.read %[[X]] = %[[Y]] : !fir.ref -!CHECK: omp.atomic.update %[[Y]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[ARG]] : i32 -!CHECK: omp.yield(%[[result]] : i32) -!CHECK: } -!CHECK: } - - !$omp atomic capture release - x = y - y = x + y - !$omp end atomic - - -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: omp.atomic.capture hint(uncontended) { -!CHECK: omp.atomic.update %[[Y]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[result:.*]] = arith.muli %[[temp]], %[[ARG]] : i32 -!CHECK: omp.yield(%[[result]] : i32) -!CHECK: } -!CHECK: omp.atomic.read %[[X]] = %[[Y]] : !fir.ref -!CHECK: } - - !$omp atomic hint(omp_sync_hint_uncontended) capture - y = x * y - x = y - !$omp end atomic - -!CHECK: %[[constant_20:.*]] = arith.constant 20 : i32 -!CHECK: %[[constant_8:.*]] = arith.constant 8 : i32 -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: %[[result:.*]] = arith.subi %[[constant_8]], %[[temp]] : i32 -!CHECK: %[[result_noreassoc:.*]] = fir.no_reassoc %[[result]] : i32 -!CHECK: %[[result:.*]] = arith.addi %[[constant_20]], %[[result_noreassoc]] : i32 -!CHECK: omp.atomic.capture memory_order(acquire) hint(nonspeculative) { -!CHECK: omp.atomic.read %[[X]] = %[[Y]] : !fir.ref -!CHECK: omp.atomic.write %[[Y]] = %[[result]] : !fir.ref, i32 -!CHECK: } - - !$omp atomic hint(omp_lock_hint_nonspeculative) capture acquire - x = y - y = 2 * 10 + (8 - x) - !$omp end atomic - - -!CHECK: %[[constant_20:.*]] = arith.constant 20 : i32 -!CHECK: %[[constant_8:.*]] = arith.constant 8 : i32 -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: %[[result:.*]] = arith.subi %[[constant_8]], %[[temp]] : i32 -!CHECK: %[[result_noreassoc:.*]] = fir.no_reassoc %[[result]] : i32 -!CHECK: %[[result:.*]] = arith.addi %[[constant_20]], %[[result_noreassoc]] : i32 -!CHECK: omp.atomic.capture { -!CHECK: omp.atomic.read %[[X]] = %[[Y]] : !fir.ref -!CHECK: omp.atomic.write %[[Y]] = %[[result]] : !fir.ref, i32 -!CHECK: } - - !$omp atomic capture - x = y - y = 2 * 10 + (8 - x) - !$omp end atomic -end program - - - -subroutine pointers_in_atomic_capture() -!CHECK: %[[A:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFpointers_in_atomic_captureEa"} -!CHECK: {{.*}} = fir.zero_bits !fir.ptr -!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ptr) -> !fir.box> -!CHECK: fir.store {{.*}} to %[[A]] : !fir.ref>> -!CHECK: %[[B:.*]] = fir.alloca !fir.box> {bindc_name = "b", uniq_name = "_QFpointers_in_atomic_captureEb"} -!CHECK: {{.*}} = fir.zero_bits !fir.ptr -!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ptr) -> !fir.box> -!CHECK: fir.store {{.*}} to %[[B]] : !fir.ref>> -!CHECK: %[[C:.*]] = fir.alloca i32 {bindc_name = "c", fir.target, uniq_name = "_QFpointers_in_atomic_captureEc"} -!CHECK: %[[D:.*]] = fir.alloca i32 {bindc_name = "d", fir.target, uniq_name = "_QFpointers_in_atomic_captureEd"} -!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ref) -> !fir.box> -!CHECK: fir.store {{.*}} to %[[A]] : !fir.ref>> -!CHECK: {{.*}} = fir.embox {{.*}} : (!fir.ref) -> !fir.box> -!CHECK: fir.store {{.*}} to %[[B]] : !fir.ref>> -!CHECK: %[[loaded_A:.*]] = fir.load %[[A]] : !fir.ref>> -!CHECK: %[[loaded_A_addr:.*]] = fir.box_addr %[[loaded_A]] : (!fir.box>) -> !fir.ptr -!CHECK: %[[loaded_B:.*]] = fir.load %[[B]] : !fir.ref>> -!CHECK: %[[loaded_B_addr:.*]] = fir.box_addr %[[loaded_B]] : (!fir.box>) -> !fir.ptr -!CHECK: %[[PRIVATE_LOADED_B:.*]] = fir.load %[[B]] : !fir.ref>> -!CHECK: %[[PRIVATE_LOADED_B_addr:.*]] = fir.box_addr %[[PRIVATE_LOADED_B]] : (!fir.box>) -> !fir.ptr -!CHECK: %[[loaded_value:.*]] = fir.load %[[PRIVATE_LOADED_B_addr]] : !fir.ptr -!CHECK: omp.atomic.capture { -!CHECK: omp.atomic.update %[[loaded_A_addr]] : !fir.ptr { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[result:.*]] = arith.addi %[[ARG]], %[[loaded_value]] : i32 -!CHECK: omp.yield(%[[result]] : i32) -!CHECK: } -!CHECK: omp.atomic.read %[[loaded_B_addr]] = %[[loaded_A_addr]] : !fir.ptr, i32 -!CHECK: } - integer, pointer :: a, b - integer, target :: c, d - a=>c - b=>d - - !$omp atomic capture - a = a + b - b = a - !$omp end atomic -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/atomic-read.f90 b/flang/test/Lower/OpenMP/FIR/atomic-read.f90 deleted file mode 100644 index 7698c3d7490f..000000000000 --- a/flang/test/Lower/OpenMP/FIR/atomic-read.f90 +++ /dev/null @@ -1,80 +0,0 @@ -! REQUIRES: openmp_runtime - -! RUN: bbc --use-desc-for-alloc=false -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -! This test checks the lowering of atomic read - -!CHECK: func @_QQmain() attributes {fir.bindc_name = "ompatomic"} { -!CHECK: %[[VAR_A:.*]] = fir.alloca !fir.char<1> {bindc_name = "a", uniq_name = "_QFEa"} -!CHECK: %[[VAR_B:.*]] = fir.alloca !fir.char<1> {bindc_name = "b", uniq_name = "_QFEb"} -!CHECK: %[[VAR_C:.*]] = fir.alloca !fir.logical<4> {bindc_name = "c", uniq_name = "_QFEc"} -!CHECK: %[[VAR_D:.*]] = fir.alloca !fir.logical<4> {bindc_name = "d", uniq_name = "_QFEd"} -!CHECK: %[[VAR_E:.*]] = fir.alloca !fir.char<1,8> {bindc_name = "e", uniq_name = "_QFEe"} -!CHECK: %[[VAR_F:.*]] = fir.alloca !fir.char<1,8> {bindc_name = "f", uniq_name = "_QFEf"} -!CHECK: %[[VAR_G:.*]] = fir.alloca f32 {bindc_name = "g", uniq_name = "_QFEg"} -!CHECK: %[[VAR_H:.*]] = fir.alloca f32 {bindc_name = "h", uniq_name = "_QFEh"} -!CHECK: %[[VAR_X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"} -!CHECK: %[[VAR_Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"} -!CHECK: omp.atomic.read %[[VAR_X]] = %[[VAR_Y]] memory_order(acquire) hint(uncontended) : !fir.ref, i32 -!CHECK: omp.atomic.read %[[VAR_A]] = %[[VAR_B]] memory_order(relaxed) : !fir.ref>, !fir.char<1> -!CHECK: omp.atomic.read %[[VAR_C]] = %[[VAR_D]] memory_order(seq_cst) hint(contended) : !fir.ref>, !fir.logical<4> -!CHECK: omp.atomic.read %[[VAR_E]] = %[[VAR_F]] hint(speculative) : !fir.ref>, !fir.char<1,8> -!CHECK: omp.atomic.read %[[VAR_G]] = %[[VAR_H]] hint(nonspeculative) : !fir.ref, f32 -!CHECK: omp.atomic.read %[[VAR_G]] = %[[VAR_H]] : !fir.ref, f32 -!CHECK: return -!CHECK: } - -program OmpAtomic - - use omp_lib - integer :: x, y - character :: a, b - logical :: c, d - character(8) :: e, f - real g, h - !$omp atomic acquire read hint(omp_sync_hint_uncontended) - x = y - !$omp atomic relaxed read hint(omp_sync_hint_none) - a = b - !$omp atomic read seq_cst hint(omp_sync_hint_contended) - c = d - !$omp atomic read hint(omp_sync_hint_speculative) - e = f - !$omp atomic read hint(omp_sync_hint_nonspeculative) - g = h - !$omp atomic read - g = h -end program OmpAtomic - -! Test lowering atomic read for pointer variables. -! Please notice to use %[[VAL_4]] and %[[VAL_1]] for operands of atomic -! operation, instead of %[[VAL_3]] and %[[VAL_0]]. - -!CHECK-LABEL: func.func @_QPatomic_read_pointer() { -!CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "x", uniq_name = "_QFatomic_read_pointerEx"} -!CHECK: %[[VAL_1:.*]] = fir.alloca !fir.ptr {uniq_name = "_QFatomic_read_pointerEx.addr"} -!CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ptr -!CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref> -!CHECK: %[[VAL_3:.*]] = fir.alloca !fir.box> {bindc_name = "y", uniq_name = "_QFatomic_read_pointerEy"} -!CHECK: %[[VAL_4:.*]] = fir.alloca !fir.ptr {uniq_name = "_QFatomic_read_pointerEy.addr"} -!CHECK: %[[VAL_5:.*]] = fir.zero_bits !fir.ptr -!CHECK: fir.store %[[VAL_5]] to %[[VAL_4]] : !fir.ref> -!CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_1]] : !fir.ref> -!CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]] : !fir.ref> -!CHECK: omp.atomic.read %[[VAL_7]] = %[[VAL_6]] : !fir.ptr, i32 -!CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_4]] : !fir.ref> -!CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_8]] : !fir.ptr -!CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_1]] : !fir.ref> -!CHECK: fir.store %[[VAL_9]] to %[[VAL_10]] : !fir.ptr -!CHECK: return -!CHECK: } - -subroutine atomic_read_pointer() - integer, pointer :: x, y - - !$omp atomic read - y = x - - x = y -end - diff --git a/flang/test/Lower/OpenMP/FIR/atomic-update.f90 b/flang/test/Lower/OpenMP/FIR/atomic-update.f90 deleted file mode 100644 index ae201807c337..000000000000 --- a/flang/test/Lower/OpenMP/FIR/atomic-update.f90 +++ /dev/null @@ -1,141 +0,0 @@ -! REQUIRES: openmp_runtime - -! This test checks lowering of atomic and atomic update constructs -! RUN: bbc --use-desc-for-alloc=false -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: %flang_fc1 -mllvm --use-desc-for-alloc=false -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -program OmpAtomicUpdate - use omp_lib - integer :: x, y, z - integer, pointer :: a, b - integer, target :: c, d - integer(1) :: i1 - - a=>c - b=>d - -!CHECK: func.func @_QQmain() attributes {fir.bindc_name = "ompatomicupdate"} { -!CHECK: %[[A:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFEa"} -!CHECK: %[[A_ADDR:.*]] = fir.alloca !fir.ptr {uniq_name = "_QFEa.addr"} -!CHECK: %{{.*}} = fir.zero_bits !fir.ptr -!CHECK: fir.store %{{.*}} to %[[A_ADDR]] : !fir.ref> -!CHECK: %[[B:.*]] = fir.alloca !fir.box> {bindc_name = "b", uniq_name = "_QFEb"} -!CHECK: %[[B_ADDR:.*]] = fir.alloca !fir.ptr {uniq_name = "_QFEb.addr"} -!CHECK: %{{.*}} = fir.zero_bits !fir.ptr -!CHECK: fir.store %{{.*}} to %[[B_ADDR]] : !fir.ref> -!CHECK: %[[C_ADDR:.*]] = fir.address_of(@_QFEc) : !fir.ref -!CHECK: %[[D_ADDR:.*]] = fir.address_of(@_QFEd) : !fir.ref -!CHECK: %[[I1:.*]] = fir.alloca i8 {bindc_name = "i1", uniq_name = "_QFEi1"} -!CHECK: %[[X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"} -!CHECK: %[[Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"} -!CHECK: %[[Z:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFEz"} -!CHECK: %{{.*}} = fir.convert %[[C_ADDR]] : (!fir.ref) -> !fir.ptr -!CHECK: fir.store %{{.*}} to %[[A_ADDR]] : !fir.ref> -!CHECK: %{{.*}} = fir.convert %[[D_ADDR]] : (!fir.ref) -> !fir.ptr -!CHECK: fir.store {{.*}} to %[[B_ADDR]] : !fir.ref> -!CHECK: %[[LOADED_A:.*]] = fir.load %[[A_ADDR]] : !fir.ref> -!CHECK: %[[LOADED_B:.*]] = fir.load %[[B_ADDR]] : !fir.ref> -!CHECK: %{{.*}} = fir.load %[[LOADED_B]] : !fir.ptr -!CHECK: omp.atomic.update %[[LOADED_A]] : !fir.ptr { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.addi %[[ARG]], %{{.*}} : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } - !$omp atomic update - a = a + b - -!CHECK: {{.*}} = arith.constant 1 : i32 -!CHECK: omp.atomic.update %[[Y]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.addi %[[ARG]], {{.*}} : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } -!CHECK: %[[LOADED_X:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: omp.atomic.update %[[Z]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.muli %[[LOADED_X]], %[[ARG]] : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } - !$omp atomic - y = y + 1 - !$omp atomic update - z = x * z - -!CHECK: %{{.*}} = arith.constant 1 : i32 -!CHECK: omp.atomic.update memory_order(relaxed) hint(uncontended) %[[X]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.subi %[[ARG]], {{.*}} : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } -!CHECK: %[[LOADED_X:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: %[[LOADED_Z:.*]] = fir.load %[[Z]] : !fir.ref -!CHECK: omp.atomic.update memory_order(relaxed) %[[Y]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %{{.*}} = arith.cmpi sgt, %[[ARG]], %[[LOADED_X]] : i32 -!CHECK: %{{.*}} = arith.select %{{.*}}, %[[ARG]], %[[LOADED_X]] : i32 -!CHECK: %{{.*}} = arith.cmpi sgt, %{{.*}}, %[[LOADED_Z]] : i32 -!CHECK: %[[RESULT:.*]] = arith.select %{{.*}}, %{{.*}}, %[[LOADED_Z]] : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } -!CHECK: %[[LOADED_X:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: omp.atomic.update memory_order(relaxed) hint(contended) %[[Z]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.addi %[[ARG]], %[[LOADED_X]] : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } - !$omp atomic relaxed update hint(omp_sync_hint_uncontended) - x = x - 1 - !$omp atomic update relaxed - y = max(y, x, z) - !$omp atomic relaxed hint(omp_sync_hint_contended) - z = z + x - -!CHECK: %{{.*}} = arith.constant 10 : i32 -!CHECK: omp.atomic.update memory_order(release) hint(contended) %[[Z]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.muli {{.*}}, %[[ARG]] : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } -!CHECK: %[[LOADED_Z:.*]] = fir.load %[[Z]] : !fir.ref -!CHECK: omp.atomic.update memory_order(release) hint(speculative) %[[X]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.divsi %[[ARG]], %[[LOADED_Z]] : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } - - !$omp atomic release update hint(omp_lock_hint_contended) - z = z * 10 - !$omp atomic hint(omp_lock_hint_speculative) update release - x = x / z - -!CHECK: %{{.*}} = arith.constant 10 : i32 -!CHECK: omp.atomic.update memory_order(seq_cst) hint(nonspeculative) %[[Y]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.addi %{{.*}}, %[[ARG]] : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } -!CHECK: %[[LOADED_Y:.*]] = fir.load %[[Y]] : !fir.ref -!CHECK: omp.atomic.update memory_order(seq_cst) %[[Z]] : !fir.ref { -!CHECK: ^bb0(%[[ARG:.*]]: i32): -!CHECK: %[[RESULT:.*]] = arith.addi %[[LOADED_Y]], %[[ARG]] : i32 -!CHECK: omp.yield(%[[RESULT]] : i32) -!CHECK: } - !$omp atomic hint(omp_sync_hint_nonspeculative) seq_cst - y = 10 + y - !$omp atomic seq_cst update - z = y + z - -!CHECK: %[[C1_VAL:.*]] = arith.constant 1 : i32 -!CHECK: omp.atomic.update %[[I1]] : !fir.ref { -!CHECK: ^bb0(%[[VAL:.*]]: i8): -!CHECK: %[[CVT_VAL:.*]] = fir.convert %[[VAL]] : (i8) -> i32 -!CHECK: %[[ADD_VAL:.*]] = arith.addi %[[CVT_VAL]], %[[C1_VAL]] : i32 -!CHECK: %[[UPDATED_VAL:.*]] = fir.convert %[[ADD_VAL]] : (i32) -> i8 -!CHECK: omp.yield(%[[UPDATED_VAL]] : i8) -!CHECK: } - !$omp atomic - i1 = i1 + 1 - !$omp end atomic -!CHECK: return -!CHECK: } -end program OmpAtomicUpdate diff --git a/flang/test/Lower/OpenMP/FIR/atomic-write.f90 b/flang/test/Lower/OpenMP/FIR/atomic-write.f90 deleted file mode 100644 index 142481b7a1d2..000000000000 --- a/flang/test/Lower/OpenMP/FIR/atomic-write.f90 +++ /dev/null @@ -1,77 +0,0 @@ -! REQUIRES: openmp_runtime - -! RUN: bbc --use-desc-for-alloc=false -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -! This test checks the lowering of atomic write - -!CHECK: func @_QQmain() attributes {fir.bindc_name = "ompatomicwrite"} { -!CHECK: %[[VAR_X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"} -!CHECK: %[[VAR_Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"} -!CHECK: %[[VAR_Z:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFEz"} -!CHECK: %[[CONST_44:.*]] = arith.constant 44 : i32 -!CHECK: omp.atomic.write %[[VAR_X]] = %[[CONST_44]] hint(uncontended) memory_order(seq_cst) : !fir.ref, i32 -!CHECK: %[[CONST_7:.*]] = arith.constant 7 : i32 -!CHECK: {{.*}} = fir.load %[[VAR_Y]] : !fir.ref -!CHECK: %[[VAR_7y:.*]] = arith.muli %[[CONST_7]], {{.*}} : i32 -!CHECK: omp.atomic.write %[[VAR_X]] = %[[VAR_7y]] memory_order(relaxed) : !fir.ref, i32 -!CHECK: %[[CONST_10:.*]] = arith.constant 10 : i32 -!CHECK: {{.*}} = fir.load %[[VAR_X]] : !fir.ref -!CHECK: {{.*}} = arith.muli %[[CONST_10]], {{.*}} : i32 -!CHECK: {{.*}} = fir.load %[[VAR_Z]] : !fir.ref -!CHECK: %[[CONST_2:.*]] = arith.constant 2 : i32 -!CHECK: {{.*}} = arith.divsi {{.*}}, %[[CONST_2]] : i32 -!CHECK: {{.*}} = arith.addi {{.*}}, {{.*}} : i32 -!CHECK: omp.atomic.write %[[VAR_Y]] = {{.*}} hint(speculative) memory_order(release) : !fir.ref, i32 -!CHECK: return -!CHECK: } - -program OmpAtomicWrite - use omp_lib - integer :: x, y, z - !$omp atomic seq_cst write hint(omp_sync_hint_uncontended) - x = 8*4 + 12 - - !$omp atomic write relaxed - x = 7 * y - - !$omp atomic write release hint(omp_sync_hint_speculative) - y = 10*x + z/2 -end program OmpAtomicWrite - -! Test lowering atomic read for pointer variables. -! Please notice to use %[[VAL_1]] for operands of atomic operation, instead -! of %[[VAL_0]]. - -!CHECK-LABEL: func.func @_QPatomic_write_pointer() { -!CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "x", uniq_name = "_QFatomic_write_pointerEx"} -!CHECK: %[[VAL_1:.*]] = fir.alloca !fir.ptr {uniq_name = "_QFatomic_write_pointerEx.addr"} -!CHECK: %[[VAL_2:.*]] = fir.zero_bits !fir.ptr -!CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref> -!CHECK: %[[VAL_3:.*]] = arith.constant 1 : i32 -!CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]] : !fir.ref> -!CHECK: omp.atomic.write %[[VAL_4]] = %[[VAL_3]] : !fir.ptr, i32 -!CHECK: %[[VAL_5:.*]] = arith.constant 2 : i32 -!CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_1]] : !fir.ref> -!CHECK: fir.store %[[VAL_5]] to %[[VAL_6]] : !fir.ptr -!CHECK: return -!CHECK: } - -subroutine atomic_write_pointer() - integer, pointer :: x - - !$omp atomic write - x = 1 - - x = 2 -end - -!CHECK-LABEL: func.func @_QPatomic_write_typed_assign -!CHECK: %[[VAR:.*]] = fir.alloca f32 {bindc_name = "r2", uniq_name = "{{.*}}r2"} -!CHECK: %[[CST:.*]] = arith.constant 0.000000e+00 : f32 -!CHECK: omp.atomic.write %[[VAR]] = %[[CST]] : !fir.ref, f32 - -subroutine atomic_write_typed_assign - real :: r2 - !$omp atomic write - r2 = 0 -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/copyin.f90 b/flang/test/Lower/OpenMP/FIR/copyin.f90 deleted file mode 100644 index e256404d3d55..000000000000 --- a/flang/test/Lower/OpenMP/FIR/copyin.f90 +++ /dev/null @@ -1,358 +0,0 @@ -! This test checks lowering of `COPYIN` clause. -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -! CHECK-LABEL: func.func @_QPcopyin_scalar_array() { -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QFcopyin_scalar_arrayEx1) : !fir.ref -! CHECK: %[[VAL_1:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref -> !fir.ref -! CHECK: %[[VAL_2:.*]] = fir.address_of(@_QFcopyin_scalar_arrayEx2) : !fir.ref> -! CHECK: %[[VAL_3:.*]] = arith.constant 10 : index -! CHECK: %[[VAL_4:.*]] = omp.threadprivate %[[VAL_2]] : !fir.ref> -> !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref -> !fir.ref -! CHECK: %[[VAL_6:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: fir.store %[[VAL_6]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_7:.*]] = omp.threadprivate %[[VAL_2]] : !fir.ref> -> !fir.ref> -! CHECK: %[[VAL_8:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_9:.*]] = fir.array_load %[[VAL_7]](%[[VAL_8]]) : (!fir.ref>, !fir.shape<1>) -> !fir.array<10xi64> -! CHECK: %[[VAL_10:.*]] = fir.shape %[[VAL_3]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_11:.*]] = fir.array_load %[[VAL_4]](%[[VAL_10]]) : (!fir.ref>, !fir.shape<1>) -> !fir.array<10xi64> -! CHECK: %[[VAL_12:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_13:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_3]], %[[VAL_12]] : index -! CHECK: %[[VAL_15:.*]] = fir.do_loop %[[VAL_16:.*]] = %[[VAL_13]] to %[[VAL_14]] step %[[VAL_12]] unordered iter_args(%[[VAL_17:.*]] = %[[VAL_9]]) -> (!fir.array<10xi64>) { -! CHECK: %[[VAL_18:.*]] = fir.array_fetch %[[VAL_11]], %[[VAL_16]] : (!fir.array<10xi64>, index) -> i64 -! CHECK: %[[VAL_19:.*]] = fir.array_update %[[VAL_17]], %[[VAL_18]], %[[VAL_16]] : (!fir.array<10xi64>, i64, index) -> !fir.array<10xi64> -! CHECK: fir.result %[[VAL_19]] : !fir.array<10xi64> -! CHECK: } -! CHECK: fir.array_merge_store %[[VAL_9]], %[[VAL_20:.*]] to %[[VAL_7]] : !fir.array<10xi64>, !fir.array<10xi64>, !fir.ref> -! CHECK: omp.barrier -! CHECK: fir.call @_QPsub1(%[[VAL_5]], %[[VAL_7]]) {{.*}}: (!fir.ref, !fir.ref>) -> () -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine copyin_scalar_array() - integer(kind=4), save :: x1 - integer(kind=8), save :: x2(10) - !$omp threadprivate(x1, x2) - - !$omp parallel copyin(x1) copyin(x2) - call sub1(x1, x2) - !$omp end parallel - -end - -! CHECK-LABEL: func.func @_QPcopyin_char_chararray() { -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QFcopyin_char_chararrayEx3) : !fir.ref> -! CHECK: %[[VAL_1:.*]] = arith.constant 5 : index -! CHECK: %[[VAL_2:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref> -> !fir.ref> -! CHECK: %[[VAL_3:.*]] = fir.address_of(@_QFcopyin_char_chararrayEx4) : !fir.ref>> -! CHECK: %[[VAL_4:.*]] = arith.constant 5 : index -! CHECK: %[[VAL_5:.*]] = arith.constant 10 : index -! CHECK: %[[VAL_6:.*]] = omp.threadprivate %[[VAL_3]] : !fir.ref>> -> !fir.ref>> -! CHECK: omp.parallel { -! CHECK: %[[VAL_7:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref> -> !fir.ref> -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_9:.*]] = fir.convert %[[VAL_1]] : (index) -> i64 -! CHECK: %[[VAL_10:.*]] = arith.muli %[[VAL_8]], %[[VAL_9]] : i64 -! CHECK: %[[VAL_11:.*]] = arith.constant false -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_7]] : (!fir.ref>) -> !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_2]] : (!fir.ref>) -> !fir.ref -! CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[VAL_12]], %[[VAL_13]], %[[VAL_10]], %[[VAL_11]]) {{.*}}: (!fir.ref, !fir.ref, i64, i1) -> () -! CHECK: %[[VAL_14:.*]] = omp.threadprivate %[[VAL_3]] : !fir.ref>> -> !fir.ref>> -! CHECK: %[[VAL_15:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_16:.*]] = fir.array_load %[[VAL_14]](%[[VAL_15]]) : (!fir.ref>>, !fir.shape<1>) -> !fir.array<10x!fir.char<1,5>> -! CHECK: %[[VAL_17:.*]] = fir.shape %[[VAL_5]] : (index) -> !fir.shape<1> -! CHECK: %[[VAL_18:.*]] = fir.array_load %[[VAL_6]](%[[VAL_17]]) : (!fir.ref>>, !fir.shape<1>) -> !fir.array<10x!fir.char<1,5>> -! CHECK: %[[VAL_19:.*]] = arith.constant 1 : index -! CHECK: %[[VAL_20:.*]] = arith.constant 0 : index -! CHECK: %[[VAL_21:.*]] = arith.subi %[[VAL_5]], %[[VAL_19]] : index -! CHECK: %[[VAL_22:.*]] = fir.do_loop %[[VAL_23:.*]] = %[[VAL_20]] to %[[VAL_21]] step %[[VAL_19]] unordered iter_args(%[[VAL_24:.*]] = %[[VAL_16]]) -> (!fir.array<10x!fir.char<1,5>>) { -! CHECK: %[[VAL_25:.*]] = fir.array_access %[[VAL_18]], %[[VAL_23]] : (!fir.array<10x!fir.char<1,5>>, index) -> !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.array_access %[[VAL_24]], %[[VAL_23]] : (!fir.array<10x!fir.char<1,5>>, index) -> !fir.ref> -! CHECK: %[[VAL_27:.*]] = arith.constant 5 : index -! CHECK: %[[VAL_28:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_27]] : (index) -> i64 -! CHECK: %[[VAL_30:.*]] = arith.muli %[[VAL_28]], %[[VAL_29]] : i64 -! CHECK: %[[VAL_31:.*]] = arith.constant false -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_26]] : (!fir.ref>) -> !fir.ref -! CHECK: %[[VAL_33:.*]] = fir.convert %[[VAL_25]] : (!fir.ref>) -> !fir.ref -! CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[VAL_32]], %[[VAL_33]], %[[VAL_30]], %[[VAL_31]]) {{.*}}: (!fir.ref, !fir.ref, i64, i1) -> () -! CHECK: %[[VAL_34:.*]] = fir.array_amend %[[VAL_24]], %[[VAL_26]] : (!fir.array<10x!fir.char<1,5>>, !fir.ref>) -> !fir.array<10x!fir.char<1,5>> -! CHECK: fir.result %[[VAL_34]] : !fir.array<10x!fir.char<1,5>> -! CHECK: } -! CHECK: fir.array_merge_store %[[VAL_16]], %[[VAL_35:.*]] to %[[VAL_14]] : !fir.array<10x!fir.char<1,5>>, !fir.array<10x!fir.char<1,5>>, !fir.ref>> -! CHECK: omp.barrier -! CHECK: %[[VAL_37:.*]] = fir.emboxchar %[[VAL_7]], %[[VAL_1]] : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_14]] : (!fir.ref>>) -> !fir.ref> -! CHECK: %[[VAL_39:.*]] = fir.emboxchar %[[VAL_38]], %[[VAL_4]] : (!fir.ref>, index) -> !fir.boxchar<1> -! CHECK: fir.call @_QPsub2(%[[VAL_37]], %[[VAL_39]]) {{.*}}: (!fir.boxchar<1>, !fir.boxchar<1>) -> () -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine copyin_char_chararray() - character(5), save :: x3, x4(10) - !$omp threadprivate(x3, x4) - - !$omp parallel copyin(x3) copyin(x4) - call sub2(x3, x4) - !$omp end parallel - -end - -! CHECK-LABEL: func.func @_QPcopyin_derived_type() { -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QFcopyin_derived_typeEx5) : !fir.ref}>> -! CHECK: %[[VAL_1:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref}>> -> !fir.ref}>> -! CHECK: omp.parallel { -! CHECK: %[[VAL_2:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref}>> -> !fir.ref}>> -! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1]] : !fir.ref}>> -! CHECK: fir.store %[[VAL_3]] to %[[VAL_2]] : !fir.ref}>> -! CHECK: omp.barrier -! CHECK: fir.call @_QPsub3(%[[VAL_2]]) {{.*}}: (!fir.ref}>>) -> () -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine copyin_derived_type() - type my_type - integer :: t_i - integer :: t_arr(5) - end type my_type - type(my_type), save :: x5 - !$omp threadprivate(x5) - - !$omp parallel copyin(x5) - call sub3(x5) - !$omp end parallel - -end - -! CHECK-LABEL: func.func @_QPcombined_parallel_worksharing_loop() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFcombined_parallel_worksharing_loopEi"} -! CHECK: %[[VAL_1:.*]] = fir.address_of(@_QFcombined_parallel_worksharing_loopEx6) : !fir.ref -! CHECK: %[[VAL_2:.*]] = omp.threadprivate %[[VAL_1]] : !fir.ref -> !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = omp.threadprivate %[[VAL_1]] : !fir.ref -> !fir.ref -! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_2]] : !fir.ref -! CHECK: fir.store %[[VAL_5]] to %[[VAL_4]] : !fir.ref -! CHECK: omp.barrier -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = fir.load %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[VAL_9:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_9]] to %[[VAL_3]] : !fir.ref -! CHECK: fir.call @_QPsub4(%[[VAL_4]]) {{.*}}: (!fir.ref) -> () -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine combined_parallel_worksharing_loop() - integer, save :: x6 - !$omp threadprivate(x6) - - !$omp parallel do copyin(x6) - do i=1, x6 - call sub4(x6) - end do - !$omp end parallel do - -end - -! CHECK-LABEL: func.func @_QPcombined_parallel_sections() { -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QFcombined_parallel_sectionsEx7) : !fir.ref -! CHECK: %[[VAL_1:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref -> !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_2:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref -> !fir.ref -! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: fir.store %[[VAL_3]] to %[[VAL_2]] : !fir.ref -! CHECK: omp.barrier -! CHECK: omp.sections { -! CHECK: omp.section { -! CHECK: fir.call @_QPsub5(%[[VAL_2]]) {{.*}}: (!fir.ref) -> () -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.section { -! CHECK: fir.call @_QPsub6(%[[VAL_2]]) {{.*}}: (!fir.ref) -> () -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine combined_parallel_sections() - integer, save :: x7 - !$omp threadprivate(x7) - - !$omp parallel sections copyin(x7) - !$omp section - call sub5(x7) - !$omp section - call sub6(x7) - !$omp end parallel sections - -end - - -!CHECK: func.func @_QPcommon_1() { -!CHECK: %[[val_0:.*]] = fir.address_of(@c_) : !fir.ref> -!CHECK: %[[val_1:.*]] = omp.threadprivate %[[val_0]] : !fir.ref> -> !fir.ref> -!CHECK: %[[val_2:.*]] = fir.convert %[[val_1]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0:.*]] = arith.constant 0 : index -!CHECK: %[[val_3:.*]] = fir.coordinate_of %[[val_2]], %[[val_c0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_4:.*]] = fir.convert %[[val_3]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_5:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFcommon_1Ey"} -!CHECK: omp.parallel { -!CHECK: %[[val_6:.*]] = omp.threadprivate %[[val_0]] : !fir.ref> -> !fir.ref> -!CHECK: %[[val_7:.*]] = fir.convert %[[val_6]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0_0:.*]] = arith.constant 0 : index -!CHECK: %[[val_8:.*]] = fir.coordinate_of %[[val_7]], %[[val_c0_0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_9:.*]] = fir.convert %[[val_8]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_10:.*]] = fir.load %[[val_4]] : !fir.ref -!CHECK: fir.store %[[val_10]] to %[[val_9]] : !fir.ref -!CHECK: omp.barrier -!CHECK: omp.sections { -!CHECK: omp.section { -!CHECK: %[[val_11:.*]] = fir.load %[[val_9]] : !fir.ref -!CHECK: %[[val_c1_i32:.*]] = arith.constant 1 : i32 -!CHECK: %[[val_12:.*]] = arith.addi %[[val_11]], %[[val_c1_i32]] : i32 -!CHECK: fir.store %[[val_12]] to %[[val_5]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.section { -!CHECK: %[[val_11:.*]] = fir.load %[[val_5]] : !fir.ref -!CHECK: %[[val_12:.*]] = fir.load %[[val_5]] : !fir.ref -!CHECK: %[[val_13:.*]] = arith.muli %[[val_11]], %[[val_12]] : i32 -!CHECK: fir.store %[[val_13]] to %[[val_9]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } -subroutine common_1() - integer :: x - integer :: y - common /c/ x - !$omp threadprivate(/c/) - - !$omp parallel sections copyin(/c/) - !$omp section - y = x + 1 - !$omp section - x = y * y - !$omp end parallel sections -end subroutine - -!CHECK: func.func @_QPcommon_2() { -!CHECK: %[[val_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFcommon_2Ei"} -!CHECK: %[[val_1:.*]] = fir.address_of(@d_) : !fir.ref> -!CHECK: %[[val_2:.*]] = omp.threadprivate %[[val_1]] : !fir.ref> -> !fir.ref> -!CHECK: %[[val_3:.*]] = fir.convert %[[val_2]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0:.*]] = arith.constant 0 : index -!CHECK: %[[val_4:.*]] = fir.coordinate_of %[[val_3]], %[[val_c0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_5:.*]] = fir.convert %[[val_4]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_6:.*]] = fir.convert %[[val_2]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c4:.*]] = arith.constant 4 : index -!CHECK: %[[val_7:.*]] = fir.coordinate_of %[[val_6]], %[[val_c4]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_8:.*]] = fir.convert %[[val_7]] : (!fir.ref) -> !fir.ref -!CHECK: omp.parallel { -!CHECK: %[[val_9:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -!CHECK: %[[val_10:.*]] = omp.threadprivate %[[val_1]] : !fir.ref> -> !fir.ref> -!CHECK: %[[val_11:.*]] = fir.convert %[[val_10]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0_0:.*]] = arith.constant 0 : index -!CHECK: %[[val_12:.*]] = fir.coordinate_of %[[val_11]], %[[val_c0_0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_13:.*]] = fir.convert %[[val_12]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_14:.*]] = fir.convert %[[val_10]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c4_1:.*]] = arith.constant 4 : index -!CHECK: %[[val_15:.*]] = fir.coordinate_of %[[val_14]], %[[val_c4_1]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_16:.*]] = fir.convert %[[val_15]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_17:.*]] = fir.load %[[val_5]] : !fir.ref -!CHECK: fir.store %[[val_17]] to %[[val_13]] : !fir.ref -!CHECK: %[[val_18:.*]] = fir.load %[[val_8]] : !fir.ref -!CHECK: fir.store %[[val_18]] to %[[val_16]] : !fir.ref -!CHECK: omp.barrier -!CHECK: %[[val_c1_i32:.*]] = arith.constant 1 : i32 -!CHECK: %[[val_19:.*]] = fir.load %[[val_13]] : !fir.ref -!CHECK: %[[val_c1_i32_2:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[arg:.*]]) : i32 = (%[[val_c1_i32]]) to (%[[val_19]]) inclusive step (%[[val_c1_i32_2]]) { -!CHECK: fir.store %[[arg]] to %[[val_9]] : !fir.ref -!CHECK: %[[val_20:.*]] = fir.load %[[val_16]] : !fir.ref -!CHECK: %[[val_21:.*]] = fir.load %[[val_9]] : !fir.ref -!CHECK: %[[val_22:.*]] = arith.addi %[[val_20]], %[[val_21]] : i32 -!CHECK: fir.store %[[val_22]] to %[[val_16]] : !fir.ref -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } -subroutine common_2() - integer :: x - integer :: y - common /d/ x, y - !$omp threadprivate(/d/) - - !$omp parallel do copyin(/d/) - do i = 1, x - y = y + i - end do - !$omp end parallel do -end subroutine - -!CHECK: func.func @_QPcommon_3() { -!CHECK: %[[val_0:.*]] = fir.address_of(@blk_) : !fir.ref> -!CHECK: %[[val_1:.*]] = omp.threadprivate %[[val_0]] : !fir.ref> -> !fir.ref> -!CHECK: %[[val_2:.*]] = fir.convert %[[val_1]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c4:.*]] = arith.constant 4 : index -!CHECK: %[[val_3:.*]] = fir.coordinate_of %[[val_2]], %[[val_c4]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_4:.*]] = fir.convert %[[val_3]] : (!fir.ref) -> !fir.ref -!CHECK: omp.parallel { -!CHECK: %[[val_5:.*]] = omp.threadprivate %[[val_0]] : !fir.ref> -> !fir.ref> -!CHECK: %[[val_6:.*]] = fir.convert %[[val_5]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c4_0:.*]] = arith.constant 4 : index -!CHECK: %[[val_7:.*]] = fir.coordinate_of %[[val_6]], %[[val_c4_0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_8:.*]] = fir.convert %[[val_7]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_9:.*]] = fir.load %[[val_4]] : !fir.ref -!CHECK: fir.store %[[val_9]] to %[[val_8]] : !fir.ref -!CHECK: omp.barrier -!CHECK: omp.sections { -!CHECK: omp.section { -!CHECK: %[[val_10:.*]] = fir.load %[[val_8]] : !fir.ref -!CHECK: %[[val_c3_i32:.*]] = arith.constant 3 : i32 -!CHECK: %[[val_11:.*]] = arith.addi %[[val_10]], %[[val_c3_i32]] : i32 -!CHECK: fir.store %[[val_11]] to %[[val_8]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } -subroutine common_3() - integer :: x - integer :: y - common /blk/ x, y - !$omp threadprivate (/blk/) - - !$omp parallel sections copyin(/blk/) - !$omp section - y = y + 3 - !$omp end parallel sections -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/critical.f90 b/flang/test/Lower/OpenMP/FIR/critical.f90 deleted file mode 100644 index fa33fb0fe58b..000000000000 --- a/flang/test/Lower/OpenMP/FIR/critical.f90 +++ /dev/null @@ -1,38 +0,0 @@ -! REQUIRES: openmp_runtime - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefix="OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --fir-to-llvm-ir | tco | FileCheck %s --check-prefix="LLVMIR" - -!OMPDialect: omp.critical.declare @help2 -!OMPDialect: omp.critical.declare @help1 hint(contended) - -subroutine omp_critical() - use omp_lib - integer :: x, y -!OMPDialect: omp.critical(@help1) -!LLVMIR: call void @__kmpc_critical_with_hint({{.*}}, {{.*}}, {{.*}} @{{.*}}help1.var, i32 2) -!$OMP CRITICAL(help1) HINT(omp_lock_hint_contended) - x = x + y -!OMPDialect: omp.terminator -!LLVMIR: call void @__kmpc_end_critical({{.*}}, {{.*}}, {{.*}} @{{.*}}help1.var) -!$OMP END CRITICAL(help1) - -! Test that the same name can be used again -! Also test with the zero hint expression -!OMPDialect: omp.critical(@help2) -!LLVMIR: call void @__kmpc_critical_with_hint({{.*}}, {{.*}}, {{.*}} @{{.*}}help2.var, i32 0) -!$OMP CRITICAL(help2) HINT(omp_lock_hint_none) - x = x - y -!OMPDialect: omp.terminator -!LLVMIR: call void @__kmpc_end_critical({{.*}}, {{.*}}, {{.*}} @{{.*}}help2.var) -!$OMP END CRITICAL(help2) - -!OMPDialect: omp.critical -!LLVMIR: call void @__kmpc_critical({{.*}}, {{.*}}, {{.*}} @{{.*}}_.var) -!$OMP CRITICAL - y = x + y -!OMPDialect: omp.terminator -!LLVMIR: call void @__kmpc_end_critical({{.*}}, {{.*}}, {{.*}} @{{.*}}_.var) -!$OMP END CRITICAL -end subroutine omp_critical diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-data.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-data.f90 deleted file mode 100644 index bb3bbc8dfa83..000000000000 --- a/flang/test/Lower/OpenMP/FIR/declare-target-data.f90 +++ /dev/null @@ -1,88 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s - -module test_0 - implicit none - -!CHECK-DAG: fir.global @_QMtest_0Edata_int {omp.declare_target = #omp.declaretarget} : i32 -INTEGER :: data_int = 10 -!$omp declare target link(data_int) - -!CHECK-DAG: fir.global @_QMtest_0Earray_1d({{.*}}) {omp.declare_target = #omp.declaretarget} : !fir.array<3xi32> -INTEGER :: array_1d(3) = (/1,2,3/) -!$omp declare target link(array_1d) - -!CHECK-DAG: fir.global @_QMtest_0Earray_2d({{.*}}) {omp.declare_target = #omp.declaretarget} : !fir.array<2x2xi32> -INTEGER :: array_2d(2,2) = reshape((/1,2,3,4/), (/2,2/)) -!$omp declare target link(array_2d) - -!CHECK-DAG: fir.global @_QMtest_0Ept1 {omp.declare_target = #omp.declaretarget} : !fir.box> -INTEGER, POINTER :: pt1 -!$omp declare target link(pt1) - -!CHECK-DAG: fir.global @_QMtest_0Ept2_tar {omp.declare_target = #omp.declaretarget} target : i32 -INTEGER, TARGET :: pt2_tar = 5 -!$omp declare target link(pt2_tar) - -!CHECK-DAG: fir.global @_QMtest_0Ept2 {omp.declare_target = #omp.declaretarget} : !fir.box> -INTEGER, POINTER :: pt2 => pt2_tar -!$omp declare target link(pt2) - -!CHECK-DAG: fir.global @_QMtest_0Edata_int_to {omp.declare_target = #omp.declaretarget} : i32 -INTEGER :: data_int_to = 5 -!$omp declare target to(data_int_to) - -!CHECK-DAG: fir.global @_QMtest_0Edata_int_enter {omp.declare_target = #omp.declaretarget} : i32 -INTEGER :: data_int_enter = 5 -!$omp declare target enter(data_int_enter) - -!CHECK-DAG: fir.global @_QMtest_0Edata_int_clauseless {omp.declare_target = #omp.declaretarget} : i32 -INTEGER :: data_int_clauseless = 1 -!$omp declare target(data_int_clauseless) - -!CHECK-DAG: fir.global @_QMtest_0Edata_extended_to_1 {omp.declare_target = #omp.declaretarget} : f32 -!CHECK-DAG: fir.global @_QMtest_0Edata_extended_to_2 {omp.declare_target = #omp.declaretarget} : f32 -REAL :: data_extended_to_1 = 2 -REAL :: data_extended_to_2 = 3 -!$omp declare target to(data_extended_to_1, data_extended_to_2) - -!CHECK-DAG: fir.global @_QMtest_0Edata_extended_enter_1 {omp.declare_target = #omp.declaretarget} : f32 -!CHECK-DAG: fir.global @_QMtest_0Edata_extended_enter_2 {omp.declare_target = #omp.declaretarget} : f32 -REAL :: data_extended_enter_1 = 2 -REAL :: data_extended_enter_2 = 3 -!$omp declare target enter(data_extended_enter_1, data_extended_enter_2) - -!CHECK-DAG: fir.global @_QMtest_0Edata_extended_link_1 {omp.declare_target = #omp.declaretarget} : f32 -!CHECK-DAG: fir.global @_QMtest_0Edata_extended_link_2 {omp.declare_target = #omp.declaretarget} : f32 -REAL :: data_extended_link_1 = 2 -REAL :: data_extended_link_2 = 3 -!$omp declare target link(data_extended_link_1, data_extended_link_2) - -contains -end module test_0 - -PROGRAM commons - !CHECK-DAG: fir.global @numbers_ {omp.declare_target = #omp.declaretarget} : tuple { - REAL :: one = 1 - REAL :: two = 2 - COMMON /numbers/ one, two - !$omp declare target(/numbers/) - - !CHECK-DAG: fir.global @numbers_link_ {omp.declare_target = #omp.declaretarget} : tuple { - REAL :: one_link = 1 - REAL :: two_link = 2 - COMMON /numbers_link/ one_link, two_link - !$omp declare target link(/numbers_link/) - - !CHECK-DAG: fir.global @numbers_to_ {omp.declare_target = #omp.declaretarget} : tuple { - REAL :: one_to = 1 - REAL :: two_to = 2 - COMMON /numbers_to/ one_to, two_to - !$omp declare target to(/numbers_to/) - - !CHECK-DAG: fir.global @numbers_enter_ {omp.declare_target = #omp.declaretarget} : tuple { - REAL :: one_enter = 1 - REAL :: two_enter = 2 - COMMON /numbers_enter/ one_enter, two_enter - !$omp declare target enter(/numbers_enter/) -END diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-func-and-subr.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-func-and-subr.f90 deleted file mode 100644 index 36d4d7db64e5..000000000000 --- a/flang/test/Lower/OpenMP/FIR/declare-target-func-and-subr.f90 +++ /dev/null @@ -1,178 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s --check-prefixes ALL,HOST -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-device %s -o - | FileCheck %s --check-prefixes ALL,DEVICE - -! Check specification valid forms of declare target with functions -! utilising device_type and to clauses as well as the default -! zero clause declare target - -! DEVICE-LABEL: func.func @_QPfunc_t_device() -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_T_DEVICE() RESULT(I) -!$omp declare target to(FUNC_T_DEVICE) device_type(nohost) - INTEGER :: I - I = 1 -END FUNCTION FUNC_T_DEVICE - -! DEVICE-LABEL: func.func @_QPfunc_enter_device() -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_ENTER_DEVICE() RESULT(I) -!$omp declare target enter(FUNC_ENTER_DEVICE) device_type(nohost) - INTEGER :: I - I = 1 -END FUNCTION FUNC_ENTER_DEVICE - -! HOST-LABEL: func.func @_QPfunc_t_host() -! HOST-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_T_HOST() RESULT(I) -!$omp declare target to(FUNC_T_HOST) device_type(host) - INTEGER :: I - I = 1 -END FUNCTION FUNC_T_HOST - -! HOST-LABEL: func.func @_QPfunc_enter_host() -! HOST-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_ENTER_HOST() RESULT(I) -!$omp declare target enter(FUNC_ENTER_HOST) device_type(host) - INTEGER :: I - I = 1 -END FUNCTION FUNC_ENTER_HOST - -! ALL-LABEL: func.func @_QPfunc_t_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_T_ANY() RESULT(I) -!$omp declare target to(FUNC_T_ANY) device_type(any) - INTEGER :: I - I = 1 -END FUNCTION FUNC_T_ANY - -! ALL-LABEL: func.func @_QPfunc_enter_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_ENTER_ANY() RESULT(I) -!$omp declare target enter(FUNC_ENTER_ANY) device_type(any) - INTEGER :: I - I = 1 -END FUNCTION FUNC_ENTER_ANY - -! ALL-LABEL: func.func @_QPfunc_default_t_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_DEFAULT_T_ANY() RESULT(I) -!$omp declare target to(FUNC_DEFAULT_T_ANY) - INTEGER :: I - I = 1 -END FUNCTION FUNC_DEFAULT_T_ANY - -! ALL-LABEL: func.func @_QPfunc_default_enter_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_DEFAULT_ENTER_ANY() RESULT(I) -!$omp declare target enter(FUNC_DEFAULT_ENTER_ANY) - INTEGER :: I - I = 1 -END FUNCTION FUNC_DEFAULT_ENTER_ANY - -! ALL-LABEL: func.func @_QPfunc_default_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_DEFAULT_ANY() RESULT(I) -!$omp declare target - INTEGER :: I - I = 1 -END FUNCTION FUNC_DEFAULT_ANY - -! ALL-LABEL: func.func @_QPfunc_default_extendedlist() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -FUNCTION FUNC_DEFAULT_EXTENDEDLIST() RESULT(I) -!$omp declare target(FUNC_DEFAULT_EXTENDEDLIST) - INTEGER :: I - I = 1 -END FUNCTION FUNC_DEFAULT_EXTENDEDLIST - -!! ----- - -! Check specification valid forms of declare target with subroutines -! utilising device_type and to clauses as well as the default -! zero clause declare target - -! DEVICE-LABEL: func.func @_QPsubr_t_device() -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_T_DEVICE() -!$omp declare target to(SUBR_T_DEVICE) device_type(nohost) -END - -! DEVICE-LABEL: func.func @_QPsubr_enter_device() -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_ENTER_DEVICE() -!$omp declare target enter(SUBR_ENTER_DEVICE) device_type(nohost) -END - -! HOST-LABEL: func.func @_QPsubr_t_host() -! HOST-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_T_HOST() -!$omp declare target to(SUBR_T_HOST) device_type(host) -END - -! HOST-LABEL: func.func @_QPsubr_enter_host() -! HOST-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_ENTER_HOST() -!$omp declare target enter(SUBR_ENTER_HOST) device_type(host) -END - -! ALL-LABEL: func.func @_QPsubr_t_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_T_ANY() -!$omp declare target to(SUBR_T_ANY) device_type(any) -END - -! ALL-LABEL: func.func @_QPsubr_enter_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_ENTER_ANY() -!$omp declare target enter(SUBR_ENTER_ANY) device_type(any) -END - -! ALL-LABEL: func.func @_QPsubr_default_t_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_DEFAULT_T_ANY() -!$omp declare target to(SUBR_DEFAULT_T_ANY) -END - -! ALL-LABEL: func.func @_QPsubr_default_enter_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_DEFAULT_ENTER_ANY() -!$omp declare target enter(SUBR_DEFAULT_ENTER_ANY) -END - -! ALL-LABEL: func.func @_QPsubr_default_any() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_DEFAULT_ANY() -!$omp declare target -END - -! ALL-LABEL: func.func @_QPsubr_default_extendedlist() -! ALL-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -SUBROUTINE SUBR_DEFAULT_EXTENDEDLIST() -!$omp declare target(SUBR_DEFAULT_EXTENDEDLIST) -END - -!! ----- - -! DEVICE-LABEL: func.func @_QPrecursive_declare_target -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -RECURSIVE FUNCTION RECURSIVE_DECLARE_TARGET(INCREMENT) RESULT(K) -!$omp declare target to(RECURSIVE_DECLARE_TARGET) device_type(nohost) - INTEGER :: INCREMENT, K - IF (INCREMENT == 10) THEN - K = INCREMENT - ELSE - K = RECURSIVE_DECLARE_TARGET(INCREMENT + 1) - END IF -END FUNCTION RECURSIVE_DECLARE_TARGET - -! DEVICE-LABEL: func.func @_QPrecursive_declare_target_enter -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}} -RECURSIVE FUNCTION RECURSIVE_DECLARE_TARGET_ENTER(INCREMENT) RESULT(K) -!$omp declare target enter(RECURSIVE_DECLARE_TARGET_ENTER) device_type(nohost) - INTEGER :: INCREMENT, K - IF (INCREMENT == 10) THEN - K = INCREMENT - ELSE - K = RECURSIVE_DECLARE_TARGET_ENTER(INCREMENT + 1) - END IF -END FUNCTION RECURSIVE_DECLARE_TARGET_ENTER diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 deleted file mode 100644 index 8e88d1b0f52a..000000000000 --- a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap-enter.f90 +++ /dev/null @@ -1,192 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE -!RUN: bbc -emit-fir -fopenmp %s -o - | FileCheck %s -!RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE - -! CHECK-LABEL: func.func @_QPimplicitly_captured_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_twice() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_twice - -! CHECK-LABEL: func.func @_QPtarget_function_twice_host -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_twice_host() result(i) -!$omp declare target enter(target_function_twice_host) device_type(host) - integer :: i - i = implicitly_captured_twice() -end function target_function_twice_host - -! DEVICE-LABEL: func.func @_QPtarget_function_twice_device -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_twice_device() result(i) -!$omp declare target enter(target_function_twice_device) device_type(nohost) - integer :: i - i = implicitly_captured_twice() -end function target_function_twice_device - -!! ----- - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_nest -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_nest() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_nest - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_one -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_two() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_two - -! DEVICE-LABEL: func.func @_QPtarget_function_test -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_test() result(j) -!$omp declare target enter(target_function_test) device_type(nohost) - integer :: i, j - i = implicitly_captured_one() - j = implicitly_captured_two() + i -end function target_function_test - -!! ----- - -! CHECK-LABEL: func.func @_QPimplicitly_captured_nest_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_nest_twice() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_nest_twice - -! CHECK-LABEL: func.func @_QPimplicitly_captured_one_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_one_twice() result(k) - k = implicitly_captured_nest_twice() -end function implicitly_captured_one_twice - -! CHECK-LABEL: func.func @_QPimplicitly_captured_two_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_two_twice() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_two_twice - -! DEVICE-LABEL: func.func @_QPtarget_function_test_device -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_test_device() result(j) - !$omp declare target enter(target_function_test_device) device_type(nohost) - integer :: i, j - i = implicitly_captured_one_twice() - j = implicitly_captured_two_twice() + i -end function target_function_test_device - -! CHECK-LABEL: func.func @_QPtarget_function_test_host -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_test_host() result(j) - !$omp declare target enter(target_function_test_host) device_type(host) - integer :: i, j - i = implicitly_captured_one_twice() - j = implicitly_captured_two_twice() + i -end function target_function_test_host - -!! ----- - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_with_dev_type_recursive -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -recursive function implicitly_captured_with_dev_type_recursive(increment) result(k) -!$omp declare target enter(implicitly_captured_with_dev_type_recursive) device_type(host) - integer :: increment, k - if (increment == 10) then - k = increment - else - k = implicitly_captured_with_dev_type_recursive(increment + 1) - end if -end function implicitly_captured_with_dev_type_recursive - -! DEVICE-LABEL: func.func @_QPtarget_function_with_dev_type_recurse -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_with_dev_type_recurse() result(i) -!$omp declare target enter(target_function_with_dev_type_recurse) device_type(nohost) - integer :: i - i = implicitly_captured_with_dev_type_recursive(0) -end function target_function_with_dev_type_recurse - -!! ----- - -module test_module -contains -! CHECK-LABEL: func.func @_QMtest_modulePimplicitly_captured_nest_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function implicitly_captured_nest_twice() result(i) - integer :: i - i = 10 - end function implicitly_captured_nest_twice - -! CHECK-LABEL: func.func @_QMtest_modulePimplicitly_captured_one_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function implicitly_captured_one_twice() result(k) - !$omp declare target enter(implicitly_captured_one_twice) device_type(host) - k = implicitly_captured_nest_twice() - end function implicitly_captured_one_twice - -! DEVICE-LABEL: func.func @_QMtest_modulePimplicitly_captured_two_twice -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function implicitly_captured_two_twice() result(y) - integer :: y - y = 5 - end function implicitly_captured_two_twice - -! DEVICE-LABEL: func.func @_QMtest_modulePtarget_function_test_device -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function target_function_test_device() result(j) - !$omp declare target enter(target_function_test_device) device_type(nohost) - integer :: i, j - i = implicitly_captured_one_twice() - j = implicitly_captured_two_twice() + i - end function target_function_test_device -end module test_module - -!! ----- - -program mb - interface - subroutine caller_recursive - !$omp declare target enter(caller_recursive) device_type(nohost) - end subroutine - - recursive subroutine implicitly_captured_recursive(increment) - integer :: increment - end subroutine - end interface -end program - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_recursive -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -recursive subroutine implicitly_captured_recursive(increment) - integer :: increment - if (increment == 10) then - return - else - call implicitly_captured_recursive(increment + 1) - end if -end subroutine - -! DEVICE-LABEL: func.func @_QPcaller_recursive -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -subroutine caller_recursive -!$omp declare target enter(caller_recursive) device_type(nohost) - call implicitly_captured_recursive(0) -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 b/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 deleted file mode 100644 index a90b04246e6d..000000000000 --- a/flang/test/Lower/OpenMP/FIR/declare-target-implicit-func-and-subr-cap.f90 +++ /dev/null @@ -1,218 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE -!RUN: bbc -emit-fir -fopenmp %s -o - | FileCheck %s -!RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE - -! CHECK-LABEL: func.func @_QPimplicitly_captured -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured(toggle) result(k) - integer :: i, j, k - logical :: toggle - i = 10 - j = 5 - if (toggle) then - k = i - else - k = j - end if -end function implicitly_captured - - -! CHECK-LABEL: func.func @_QPtarget_function -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function(toggle) result(i) -!$omp declare target - integer :: i - logical :: toggle - i = implicitly_captured(toggle) -end function target_function - -!! ----- - -! CHECK-LABEL: func.func @_QPimplicitly_captured_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_twice() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_twice - -! CHECK-LABEL: func.func @_QPtarget_function_twice_host -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_twice_host() result(i) -!$omp declare target to(target_function_twice_host) device_type(host) - integer :: i - i = implicitly_captured_twice() -end function target_function_twice_host - -! DEVICE-LABEL: func.func @_QPtarget_function_twice_device -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_twice_device() result(i) -!$omp declare target to(target_function_twice_device) device_type(nohost) - integer :: i - i = implicitly_captured_twice() -end function target_function_twice_device - -!! ----- - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_nest -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_nest() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_nest - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_one -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_two() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_two - -! DEVICE-LABEL: func.func @_QPtarget_function_test -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_test() result(j) -!$omp declare target to(target_function_test) device_type(nohost) - integer :: i, j - i = implicitly_captured_one() - j = implicitly_captured_two() + i -end function target_function_test - -!! ----- - -! CHECK-LABEL: func.func @_QPimplicitly_captured_nest_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_nest_twice() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_nest_twice - -! CHECK-LABEL: func.func @_QPimplicitly_captured_one_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_one_twice() result(k) - k = implicitly_captured_nest_twice() -end function implicitly_captured_one_twice - -! CHECK-LABEL: func.func @_QPimplicitly_captured_two_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function implicitly_captured_two_twice() result(k) - integer :: i - i = 10 - k = i -end function implicitly_captured_two_twice - -! DEVICE-LABEL: func.func @_QPtarget_function_test_device -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_test_device() result(j) - !$omp declare target to(target_function_test_device) device_type(nohost) - integer :: i, j - i = implicitly_captured_one_twice() - j = implicitly_captured_two_twice() + i -end function target_function_test_device - -! CHECK-LABEL: func.func @_QPtarget_function_test_host -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_test_host() result(j) - !$omp declare target to(target_function_test_host) device_type(host) - integer :: i, j - i = implicitly_captured_one_twice() - j = implicitly_captured_two_twice() + i -end function target_function_test_host - -!! ----- - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_with_dev_type_recursive -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -recursive function implicitly_captured_with_dev_type_recursive(increment) result(k) -!$omp declare target to(implicitly_captured_with_dev_type_recursive) device_type(host) - integer :: increment, k - if (increment == 10) then - k = increment - else - k = implicitly_captured_with_dev_type_recursive(increment + 1) - end if -end function implicitly_captured_with_dev_type_recursive - -! DEVICE-LABEL: func.func @_QPtarget_function_with_dev_type_recurse -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -function target_function_with_dev_type_recurse() result(i) -!$omp declare target to(target_function_with_dev_type_recurse) device_type(nohost) - integer :: i - i = implicitly_captured_with_dev_type_recursive(0) -end function target_function_with_dev_type_recurse - -!! ----- - -module test_module -contains -! CHECK-LABEL: func.func @_QMtest_modulePimplicitly_captured_nest_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function implicitly_captured_nest_twice() result(i) - integer :: i - i = 10 - end function implicitly_captured_nest_twice - -! CHECK-LABEL: func.func @_QMtest_modulePimplicitly_captured_one_twice -! CHECK-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function implicitly_captured_one_twice() result(k) - !$omp declare target to(implicitly_captured_one_twice) device_type(host) - k = implicitly_captured_nest_twice() - end function implicitly_captured_one_twice - -! DEVICE-LABEL: func.func @_QMtest_modulePimplicitly_captured_two_twice -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function implicitly_captured_two_twice() result(y) - integer :: y - y = 5 - end function implicitly_captured_two_twice - -! DEVICE-LABEL: func.func @_QMtest_modulePtarget_function_test_device -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} - function target_function_test_device() result(j) - !$omp declare target to(target_function_test_device) device_type(nohost) - integer :: i, j - i = implicitly_captured_one_twice() - j = implicitly_captured_two_twice() + i - end function target_function_test_device -end module test_module - -!! ----- - -program mb - interface - subroutine caller_recursive - !$omp declare target to(caller_recursive) device_type(nohost) - end subroutine - - recursive subroutine implicitly_captured_recursive(increment) - integer :: increment - end subroutine - end interface -end program - -! DEVICE-LABEL: func.func @_QPimplicitly_captured_recursive -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -recursive subroutine implicitly_captured_recursive(increment) - integer :: increment - if (increment == 10) then - return - else - call implicitly_captured_recursive(increment + 1) - end if -end subroutine - -! DEVICE-LABEL: func.func @_QPcaller_recursive -! DEVICE-SAME: {{.*}}attributes {omp.declare_target = #omp.declaretarget{{.*}}} -subroutine caller_recursive -!$omp declare target to(caller_recursive) device_type(nohost) - call implicitly_captured_recursive(0) -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/default-clause.f90 b/flang/test/Lower/OpenMP/FIR/default-clause.f90 deleted file mode 100644 index 14c0d375896a..000000000000 --- a/flang/test/Lower/OpenMP/FIR/default-clause.f90 +++ /dev/null @@ -1,281 +0,0 @@ -! This test checks lowering of OpenMP parallel directive -! with `DEFAULT` clause present. - -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - - -!CHECK: func @_QQmain() attributes {fir.bindc_name = "default_clause_lowering"} { -!CHECK: %[[W:.*]] = fir.alloca i32 {bindc_name = "w", uniq_name = "_QFEw"} -!CHECK: %[[X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"} -!CHECK: %[[Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFEy"} -!CHECK: %[[Z:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFEz"} -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFEx"} -!CHECK: %[[const:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[const]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFEy"} -!CHECK: %[[PRIVATE_W:.*]] = fir.alloca i32 {bindc_name = "w", pinned, uniq_name = "_QFEw"} -!CHECK: %[[const:.*]] = arith.constant 2 : i32 -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: %[[result:.*]] = arith.muli %[[const]], %[[temp]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_W]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 45 : i32 -!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[const]] : i32 -!CHECK: fir.store %[[result]] to %[[Z]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - -program default_clause_lowering - integer :: x, y, z, w - - !$omp parallel default(private) firstprivate(x) shared(z) - x = y * 2 - z = w + 45 - !$omp end parallel - -!CHECK: omp.parallel { -!CHECK: %[[temp:.*]] = fir.load %[[Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - - !$omp parallel default(shared) - x = y - !$omp end parallel - -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFEx"} -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFEy"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - - !$omp parallel default(none) private(x, y) - x = y - !$omp end parallel - -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFEy"} -!CHECK: %[[temp:.*]] = fir.load %[[Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_Y]] : !fir.ref -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - - !$omp parallel default(firstprivate) firstprivate(y) - x = y - !$omp end parallel - -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFEx"} -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFEy"} -!CHECK: %[[temp:.*]] = fir.load %[[Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_Y]] : !fir.ref -!CHECK: %[[PRIVATE_W:.*]] = fir.alloca i32 {bindc_name = "w", pinned, uniq_name = "_QFEw"} -!CHECK: %[[temp:.*]] = fir.load %[[W]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_W]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 2 : i32 -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: %[[result:.*]] = arith.muli %[[const]], %[[temp]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_W]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 45 : i32 -!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[const]] : i32 -!CHECK: fir.store %[[result]] to %[[Z]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - - !$omp parallel default(firstprivate) private(x) shared(z) - x = y * 2 - z = w + 45 - !$omp end parallel - -!CHECK: omp.parallel { -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFEx"} -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFEy"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_W:.*]] = fir.alloca i32 {bindc_name = "w", pinned, uniq_name = "_QFEw"} -!CHECK: %[[temp:.*]] = fir.load %[[W]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_W]] : !fir.ref -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_W]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - !$omp parallel - !$omp parallel default(private) - x = y - !$omp end parallel - - !$omp parallel default(firstprivate) - w = x - !$omp end parallel - !$omp end parallel - -end program default_clause_lowering - -subroutine nested_default_clause_tests - integer :: x, y, z, w, k, a - -!CHECK: %[[K:.*]] = fir.alloca i32 {bindc_name = "k", uniq_name = "_QFnested_default_clause_testsEk"} -!CHECK: %[[W:.*]] = fir.alloca i32 {bindc_name = "w", uniq_name = "_QFnested_default_clause_testsEw"} -!CHECK: %[[X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[Y:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[Z:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFnested_default_clause_testsEz"} -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[PRIVATE_Z:.*]] = fir.alloca i32 {bindc_name = "z", pinned, uniq_name = "_QFnested_default_clause_testsEz"} -!CHECK: %[[PRIVATE_K:.*]] = fir.alloca i32 {bindc_name = "k", pinned, uniq_name = "_QFnested_default_clause_testsEk"} -!CHECK: omp.parallel { -!CHECK: %[[INNER_PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[INNER_PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[const:.*]] = arith.constant 20 : i32 -!CHECK: fir.store %[[const]] to %[[INNER_PRIVATE_Y]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 10 : i32 -!CHECK: fir.store %[[const]] to %[[INNER_PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.parallel { -!CHECK: %[[INNER_PRIVATE_W:.*]] = fir.alloca i32 {bindc_name = "w", pinned, uniq_name = "_QFnested_default_clause_testsEw"} -!CHECK: %[[INNER_PRIVATE_Z:.*]] = fir.alloca i32 {bindc_name = "z", pinned, uniq_name = "_QFnested_default_clause_testsEz"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Z]] -!CHECK: fir.store %[[temp]] to %[[INNER_PRIVATE_Z]] : !fir.ref -!CHECK: %[[INNER_PRIVATE_K:.*]] = fir.alloca i32 {bindc_name = "k", pinned, uniq_name = "_QFnested_default_clause_testsEk"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_K]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[INNER_PRIVATE_K]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 30 : i32 -!CHECK: fir.store %[[const]] to %[[PRIVATE_Y]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 40 : i32 -!CHECK: fir.store %[[const]] to %[[INNER_PRIVATE_W]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 50 : i32 -!CHECK: fir.store %[[const]] to %[[INNER_PRIVATE_Z]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 40 : i32 -!CHECK: fir.store %[[const]] to %[[INNER_PRIVATE_K]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - !$omp parallel firstprivate(x) private(y) shared(w) default(private) - !$omp parallel default(private) - y = 20 - x = 10 - !$omp end parallel - - !$omp parallel default(firstprivate) shared(y) private(w) - y = 30 - w = 40 - z = 50 - k = 40 - !$omp end parallel - !$omp end parallel - - -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[PRIVATE_Z:.*]] = fir.alloca i32 {bindc_name = "z", pinned, uniq_name = "_QFnested_default_clause_testsEz"} -!CHECK: %[[PRIVATE_W:.*]] = fir.alloca i32 {bindc_name = "w", pinned, uniq_name = "_QFnested_default_clause_testsEw"} -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_INNER_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_INNER_X]] : !fir.ref -!CHECK: %[[INNER_PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[INNER_PRIVATE_Y]] : !fir.ref -!CHECK: %[[temp:.*]] = fir.load %[[INNER_PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_INNER_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_INNER_W:.*]] = fir.alloca i32 {bindc_name = "w", pinned, uniq_name = "_QFnested_default_clause_testsEw"} -!CHECK: %[[PRIVATE_INNER_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[temp_1:.*]] = fir.load %[[PRIVATE_INNER_X]] : !fir.ref -!CHECK: %[[temp_2:.*]] = fir.load %[[PRIVATE_Z]] : !fir.ref -!CHECK: %[[result:.*]] = arith.addi %{{.*}}, %{{.*}} : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_INNER_W]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - !$omp parallel default(private) - !$omp parallel default(firstprivate) - x = y - !$omp end parallel - - !$omp parallel default(private) shared(z) - w = x + z - !$omp end parallel - !$omp end parallel - -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[PRIVATE_W:.*]] = fir.alloca i32 {bindc_name = "w", pinned, uniq_name = "_QFnested_default_clause_testsEw"} -!CHECK: %[[PRIVATE_Z:.*]] = fir.alloca i32 {bindc_name = "z", pinned, uniq_name = "_QFnested_default_clause_testsEz"} -!CHECK: omp.parallel { -!CHECK: %[[INNER_PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[INNER_PRIVATE_X]] : !fir.ref -!CHECK: %[[INNER_PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[INNER_PRIVATE_Y]] : !fir.ref -!CHECK: %[[temp:.*]] = fir.load %[[INNER_PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[INNER_PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.parallel { -!CHECK: %[[temp_1:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[temp_2:.*]] = fir.load %[[PRIVATE_Z]] : !fir.ref -!CHECK: %[[temp_3:.*]] = arith.addi %[[temp_1]], %[[temp_2]] : i32 -!CHECK: fir.store %[[temp_3]] to %[[PRIVATE_W]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: } - !$omp parallel default(private) - !$omp parallel default(firstprivate) - x = y - !$omp end parallel - - !$omp parallel default(shared) - w = x + z - !$omp end parallel - !$omp end parallel - -!CHECK: omp.parallel { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFnested_default_clause_testsEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[PRIVATE_Y:.*]] = fir.alloca i32 {bindc_name = "y", pinned, uniq_name = "_QFnested_default_clause_testsEy"} -!CHECK: %[[temp:.*]] = fir.load %[[Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_Y]] : !fir.ref -!CHECK: omp.single { -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_Y]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: } - !$omp parallel default(firstprivate) - !$omp single - x = y - !$omp end single - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/delayed-privatization-firstprivate.f90 b/flang/test/Lower/OpenMP/FIR/delayed-privatization-firstprivate.f90 deleted file mode 100644 index 50938342dee7..000000000000 --- a/flang/test/Lower/OpenMP/FIR/delayed-privatization-firstprivate.f90 +++ /dev/null @@ -1,32 +0,0 @@ -! Test delayed privatization for the `private` clause. - -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir \ -! RUN: --openmp-enable-delayed-privatization -o - %s 2>&1 | FileCheck %s -! RUN: bbc -emit-fir -hlfir=false -fopenmp --openmp-enable-delayed-privatization \ -! RUN: -o - %s 2>&1 | FileCheck %s - -subroutine delayed_privatization_firstprivate - implicit none - integer :: var1 - -!$OMP PARALLEL FIRSTPRIVATE(var1) - var1 = 10 -!$OMP END PARALLEL -end subroutine - -! CHECK-LABEL: omp.private {type = firstprivate} -! CHECK-SAME: @[[VAR1_PRIVATIZER_SYM:.*]] : !fir.ref alloc { -! CHECK-NEXT: ^bb0(%[[PRIV_ARG:.*]]: !fir.ref): -! CHECK-NEXT: %[[PRIV_ALLOC:.*]] = fir.alloca i32 {bindc_name = "var1", pinned, uniq_name = "_QFdelayed_privatization_firstprivateEvar1"} -! CHECK-NEXT: omp.yield(%[[PRIV_ALLOC]] : !fir.ref) -! CHECK: } copy { -! CHECK: ^bb0(%[[PRIV_ORIG_ARG:.*]]: !fir.ref, %[[PRIV_PRIV_ARG:.*]]: !fir.ref): -! CHECK: %[[ORIG_VAL:.*]] = fir.load %[[PRIV_ORIG_ARG]] : !fir.ref -! CHECK: fir.store %[[ORIG_VAL]] to %[[PRIV_PRIV_ARG]] : !fir.ref -! CHECK: omp.yield(%[[PRIV_PRIV_ARG]] : !fir.ref) -! CHECK: } - -! CHECK-LABEL: @_QPdelayed_privatization_firstprivate -! CHECK: omp.parallel private(@[[VAR1_PRIVATIZER_SYM]] %{{.*}} -> %{{.*}} : !fir.ref) { -! CHECK: omp.terminator - diff --git a/flang/test/Lower/OpenMP/FIR/delayed-privatization-private.f90 b/flang/test/Lower/OpenMP/FIR/delayed-privatization-private.f90 deleted file mode 100644 index b13687faa3f2..000000000000 --- a/flang/test/Lower/OpenMP/FIR/delayed-privatization-private.f90 +++ /dev/null @@ -1,41 +0,0 @@ -! Test delayed privatization for the `private` clause. - -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir \ -! RUN: --openmp-enable-delayed-privatization -o - %s 2>&1 | FileCheck %s -! RUN: bbc -emit-fir -hlfir=false -fopenmp --openmp-enable-delayed-privatization \ -! RUN: -o - %s 2>&1 | FileCheck %s - -subroutine delayed_privatization_private - implicit none - integer :: var1 - -!$OMP PARALLEL PRIVATE(var1) - var1 = 10 -!$OMP END PARALLEL - -!$OMP PARALLEL PRIVATE(var1) - var1 = 20 -!$OMP END PARALLEL - -end subroutine - -! CHECK-LABEL: omp.private {type = private} -! CHECK-SAME: @[[PRIVATIZER_SYM:.*]] : !fir.ref alloc { -! CHECK-NEXT: ^bb0(%[[PRIV_ARG:.*]]: !fir.ref): -! CHECK-NEXT: %[[PRIV_ALLOC:.*]] = fir.alloca i32 {bindc_name = "var1", pinned, uniq_name = "_QFdelayed_privatization_privateEvar1"} -! CHECK-NEXT: omp.yield(%[[PRIV_ALLOC]] : !fir.ref) -! CHECK-NOT: } copy { - -! CHECK-LABEL: @_QPdelayed_privatization_private -! CHECK: %[[ORIG_ALLOC:.*]] = fir.alloca i32 {bindc_name = "var1", uniq_name = "_QFdelayed_privatization_privateEvar1"} -! CHECK: omp.parallel private(@[[PRIVATIZER_SYM]] %[[ORIG_ALLOC]] -> %[[PAR_ARG:.*]] : !fir.ref) { -! CHECK: %[[C10:.*]] = arith.constant 10 : i32 -! CHECK: fir.store %[[C10]] to %[[PAR_ARG]] : !fir.ref -! CHECK: omp.terminator - -! Test that the same privatizer is used if the a variable with the same type and -! name was previously privatized. -! CHECK: omp.parallel private(@[[PRIVATIZER_SYM]] %[[ORIG_ALLOC]] -> %[[PAR_ARG:.*]] : !fir.ref) { -! CHECK: %[[C20:.*]] = arith.constant 20 : i32 -! CHECK: fir.store %[[C20]] to %[[PAR_ARG]] : !fir.ref -! CHECK: omp.terminator diff --git a/flang/test/Lower/OpenMP/FIR/firstprivate-commonblock.f90 b/flang/test/Lower/OpenMP/FIR/firstprivate-commonblock.f90 deleted file mode 100644 index 6adc7d9f6c82..000000000000 --- a/flang/test/Lower/OpenMP/FIR/firstprivate-commonblock.f90 +++ /dev/null @@ -1,30 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s - -!CHECK: func.func @_QPfirstprivate_common() { -!CHECK: %[[val_0:.*]] = fir.address_of(@c_) : !fir.ref> -!CHECK: %[[val_1:.*]] = fir.convert %[[val_0]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0:.*]] = arith.constant 0 : index -!CHECK: %[[val_2:.*]] = fir.coordinate_of %[[val_1]], %[[val_c0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_3:.*]] = fir.convert %[[val_2]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_4:.*]] = fir.convert %[[val_0]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c4:.*]] = arith.constant 4 : index -!CHECK: %[[val_5:.*]] = fir.coordinate_of %[[val_4]], %[[val_c4]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_6:.*]] = fir.convert %[[val_5]] : (!fir.ref) -> !fir.ref -!CHECK: omp.parallel { -!CHECK: %[[val_7:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFfirstprivate_commonEx"} -!CHECK: %[[val_8:.*]] = fir.load %[[val_3]] : !fir.ref -!CHECK: fir.store %[[val_8]] to %[[val_7]] : !fir.ref -!CHECK: %[[val_9:.*]] = fir.alloca f32 {bindc_name = "y", pinned, uniq_name = "_QFfirstprivate_commonEy"} -!CHECK: %[[val_10:.*]] = fir.load %[[val_6]] : !fir.ref -!CHECK: fir.store %[[val_10]] to %[[val_9]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } - -subroutine firstprivate_common - common /c/ x, y - real x, y - !$omp parallel firstprivate(/c/) - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/flush.f90 b/flang/test/Lower/OpenMP/FIR/flush.f90 deleted file mode 100644 index 2c281632b85c..000000000000 --- a/flang/test/Lower/OpenMP/FIR/flush.f90 +++ /dev/null @@ -1,45 +0,0 @@ -! This test checks lowering of OpenMP Flush Directive. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="LLVMIRDialect,OMPDialect" - -subroutine flush_standalone(a, b, c) - integer, intent(inout) :: a, b, c - -!$omp flush(a,b,c) -!$omp flush -!OMPDialect: omp.flush(%{{.*}}, %{{.*}}, %{{.*}} : -!FIRDialect: !fir.ref, !fir.ref, !fir.ref) -!LLVMIRDialect: !llvm.ptr, !llvm.ptr, !llvm.ptr) -!OMPDialect: omp.flush - -end subroutine flush_standalone - -subroutine flush_parallel(a, b, c) - integer, intent(inout) :: a, b, c - -!$omp parallel -!OMPDialect: omp.parallel { - -!OMPDialect: omp.flush(%{{.*}}, %{{.*}}, %{{.*}} : -!FIRDialect: !fir.ref, !fir.ref, !fir.ref) -!LLVMIRDialect: !llvm.ptr, !llvm.ptr, !llvm.ptr) -!OMPDialect: omp.flush -!$omp flush(a,b,c) -!$omp flush - -!FIRDialect: %{{.*}} = fir.load %{{.*}} : !fir.ref -!FIRDialect: %{{.*}} = fir.load %{{.*}} : !fir.ref -!FIRDialect: %{{.*}} = arith.addi %{{.*}}, %{{.*}} : i32 -!FIRDialect: fir.store %{{.*}} to %{{.*}} : !fir.ref - -!LLVMIRDialect: %{{.*}} = llvm.load %{{.*}} : !llvm.ptr -> i32 -!LLVMIRDialect: %{{.*}} = llvm.load %{{.*}} : !llvm.ptr -> i32 -!LLVMIRDialect: %{{.*}} = llvm.add %{{.*}}, %{{.*}} : i32 -!LLVMIRDialect: llvm.store %{{.*}}, %{{.*}} : i32, !llvm.ptr - c = a + b - -!OMPDialect: omp.terminator -!$omp END parallel - -end subroutine flush_parallel diff --git a/flang/test/Lower/OpenMP/FIR/if-clause.f90 b/flang/test/Lower/OpenMP/FIR/if-clause.f90 deleted file mode 100644 index 683d9f7ef972..000000000000 --- a/flang/test/Lower/OpenMP/FIR/if-clause.f90 +++ /dev/null @@ -1,498 +0,0 @@ -! This test checks lowering of OpenMP IF clauses. - -! The "if" clause was added to the "simd" directive in OpenMP 5.0, and -! to the "teams" directive in OpenMP 5.2. -! RUN: bbc -fopenmp -fopenmp-version=52 -emit-fir %s -o - | FileCheck %s -! RUN: %flang_fc1 -fopenmp -fopenmp-version=52 -emit-fir %s -o - | FileCheck %s - -program main - integer :: i - - ! TODO When they are supported, add tests for: - ! - DISTRIBUTE PARALLEL DO - ! - DISTRIBUTE PARALLEL DO SIMD - ! - DISTRIBUTE SIMD - ! - PARALLEL SECTIONS - ! - PARALLEL WORKSHARE - ! - TARGET PARALLEL - ! - TARGET TEAMS DISTRIBUTE - ! - TARGET TEAMS DISTRIBUTE PARALLEL DO - ! - TARGET TEAMS DISTRIBUTE PARALLEL DO SIMD - ! - TARGET TEAMS DISTRIBUTE SIMD - ! - TARGET UPDATE - ! - TASKLOOP - ! - TASKLOOP SIMD - ! - TEAMS DISTRIBUTE - ! - TEAMS DISTRIBUTE PARALLEL DO - ! - TEAMS DISTRIBUTE PARALLEL DO SIMD - ! - TEAMS DISTRIBUTE SIMD - - ! ---------------------------------------------------------------------------- - ! DO SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.wsloop - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp do simd - do i = 1, 10 - end do - !$omp end do simd - - ! CHECK: omp.wsloop - !$omp do simd if(.true.) - do i = 1, 10 - end do - !$omp end do simd - - ! CHECK: omp.wsloop - !$omp do simd if(simd: .true.) - do i = 1, 10 - end do - !$omp end do simd - - ! ---------------------------------------------------------------------------- - ! PARALLEL - ! ---------------------------------------------------------------------------- - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp parallel - i = 10 - !$omp end parallel - - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - !$omp parallel if(.true.) - i = 10 - !$omp end parallel - - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - !$omp parallel if(parallel: .true.) - i = 10 - !$omp end parallel - - ! ---------------------------------------------------------------------------- - ! PARALLEL DO - ! ---------------------------------------------------------------------------- - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp parallel do - do i = 1, 10 - end do - !$omp end parallel do - - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - !$omp parallel do if(.true.) - do i = 1, 10 - end do - !$omp end parallel do - - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - !$omp parallel do if(parallel: .true.) - do i = 1, 10 - end do - !$omp end parallel do - - ! ---------------------------------------------------------------------------- - ! PARALLEL DO SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.wsloop - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp parallel do simd - do i = 1, 10 - end do - !$omp end parallel do simd - - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.wsloop - !$omp parallel do simd if(.true.) - do i = 1, 10 - end do - !$omp end parallel do simd - - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.wsloop - !$omp parallel do simd if(parallel: .true.) if(simd: .false.) - do i = 1, 10 - end do - !$omp end parallel do simd - - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.wsloop - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp parallel do simd if(parallel: .true.) - do i = 1, 10 - end do - !$omp end parallel do simd - - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.wsloop - !$omp parallel do simd if(simd: .true.) - do i = 1, 10 - end do - !$omp end parallel do simd - - ! ---------------------------------------------------------------------------- - ! SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.simd - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp simd - do i = 1, 10 - end do - !$omp end simd - - ! CHECK: omp.simd - ! CHECK-SAME: if({{.*}}) - !$omp simd if(.true.) - do i = 1, 10 - end do - !$omp end simd - - ! CHECK: omp.simd - ! CHECK-SAME: if({{.*}}) - !$omp simd if(simd: .true.) - do i = 1, 10 - end do - !$omp end simd - - ! ---------------------------------------------------------------------------- - ! TARGET - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target - !$omp end target - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - !$omp target if(.true.) - !$omp end target - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - !$omp target if(target: .true.) - !$omp end target - - ! ---------------------------------------------------------------------------- - ! TARGET DATA - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target_data - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target data map(tofrom: i) - !$omp end target data - - ! CHECK: omp.target_data - ! CHECK-SAME: if({{.*}}) - !$omp target data map(tofrom: i) if(.true.) - !$omp end target data - - ! CHECK: omp.target_data - ! CHECK-SAME: if({{.*}}) - !$omp target data map(tofrom: i) if(target data: .true.) - !$omp end target data - - ! ---------------------------------------------------------------------------- - ! TARGET ENTER DATA - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target_enter_data - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: map - !$omp target enter data map(to: i) - - ! CHECK: omp.target_enter_data - ! CHECK-SAME: if({{.*}}) - !$omp target enter data map(to: i) if(.true.) - - ! CHECK: omp.target_enter_data - ! CHECK-SAME: if({{.*}}) - !$omp target enter data map(to: i) if(target enter data: .true.) - - ! ---------------------------------------------------------------------------- - ! TARGET EXIT DATA - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target_exit_data - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: map - !$omp target exit data map(from: i) - - ! CHECK: omp.target_exit_data - ! CHECK-SAME: if({{.*}}) - !$omp target exit data map(from: i) if(.true.) - - ! CHECK: omp.target_exit_data - ! CHECK-SAME: if({{.*}}) - !$omp target exit data map(from: i) if(target exit data: .true.) - - ! ---------------------------------------------------------------------------- - ! TARGET PARALLEL DO - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target parallel do - do i = 1, 10 - end do - !$omp end target parallel do - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - !$omp target parallel do if(.true.) - do i = 1, 10 - end do - !$omp end target parallel do - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - !$omp target parallel do if(target: .true.) if(parallel: .false.) - do i = 1, 10 - end do - !$omp end target parallel do - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target parallel do if(target: .true.) - do i = 1, 10 - end do - !$omp end target parallel do - - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - !$omp target parallel do if(parallel: .true.) - do i = 1, 10 - end do - !$omp end target parallel do - - ! ---------------------------------------------------------------------------- - ! TARGET PARALLEL DO SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.wsloop - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target parallel do simd - do i = 1, 10 - end do - !$omp end target parallel do simd - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.wsloop - !$omp target parallel do simd if(.true.) - do i = 1, 10 - end do - !$omp end target parallel do simd - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.wsloop - !$omp target parallel do simd if(target: .true.) if(parallel: .false.) & - !$omp& if(simd: .true.) - do i = 1, 10 - end do - !$omp end target parallel do simd - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.parallel - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.wsloop - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target parallel do simd if(target: .true.) - do i = 1, 10 - end do - !$omp end target parallel do simd - - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.parallel - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.wsloop - !$omp target parallel do simd if(parallel: .true.) if(simd: .false.) - do i = 1, 10 - end do - !$omp end target parallel do simd - - ! ---------------------------------------------------------------------------- - ! TARGET SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.simd - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target simd - do i = 1, 10 - end do - !$omp end target simd - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.simd - ! CHECK-SAME: if({{.*}}) - !$omp target simd if(.true.) - do i = 1, 10 - end do - !$omp end target simd - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.simd - ! CHECK-SAME: if({{.*}}) - !$omp target simd if(target: .true.) if(simd: .false.) - do i = 1, 10 - end do - !$omp end target simd - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.simd - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target simd if(target: .true.) - do i = 1, 10 - end do - !$omp end target simd - - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.simd - ! CHECK-SAME: if({{.*}}) - !$omp target simd if(simd: .true.) - do i = 1, 10 - end do - !$omp end target simd - - ! ---------------------------------------------------------------------------- - ! TARGET TEAMS - ! ---------------------------------------------------------------------------- - - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.teams - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target teams - i = 1 - !$omp end target teams - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.teams - ! CHECK-SAME: if({{.*}}) - !$omp target teams if(.true.) - i = 1 - !$omp end target teams - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.teams - ! CHECK-SAME: if({{.*}}) - !$omp target teams if(target: .true.) if(teams: .false.) - i = 1 - !$omp end target teams - - ! CHECK: omp.target - ! CHECK-SAME: if({{.*}}) - ! CHECK: omp.teams - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp target teams if(target: .true.) - i = 1 - !$omp end target teams - - ! CHECK: omp.target - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - ! CHECK: omp.teams - ! CHECK-SAME: if({{.*}}) - !$omp target teams if(teams: .true.) - i = 1 - !$omp end target teams - - ! ---------------------------------------------------------------------------- - ! TASK - ! ---------------------------------------------------------------------------- - ! CHECK: omp.task - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp task - !$omp end task - - ! CHECK: omp.task - ! CHECK-SAME: if({{.*}}) - !$omp task if(.true.) - !$omp end task - - ! CHECK: omp.task - ! CHECK-SAME: if({{.*}}) - !$omp task if(task: .true.) - !$omp end task - - ! ---------------------------------------------------------------------------- - ! TEAMS - ! ---------------------------------------------------------------------------- - ! CHECK: omp.teams - ! CHECK-NOT: if({{.*}}) - ! CHECK-SAME: { - !$omp teams - i = 1 - !$omp end teams - - ! CHECK: omp.teams - ! CHECK-SAME: if({{.*}}) - !$omp teams if(.true.) - i = 1 - !$omp end teams - - ! CHECK: omp.teams - ! CHECK-SAME: if({{.*}}) - !$omp teams if(teams: .true.) - i = 1 - !$omp end teams -end program main diff --git a/flang/test/Lower/OpenMP/FIR/is-device.f90 b/flang/test/Lower/OpenMP/FIR/is-device.f90 deleted file mode 100644 index 79e0ee506c5f..000000000000 --- a/flang/test/Lower/OpenMP/FIR/is-device.f90 +++ /dev/null @@ -1,14 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s --check-prefix=HOST -!RUN: %flang_fc1 -emit-fir -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEVICE-FLAG-ONLY -!RUN: bbc -fopenmp -fopenmp-is-target-device -emit-fir -o - %s | FileCheck %s --check-prefix=DEVICE -!RUN: bbc -fopenmp -emit-fir -o - %s | FileCheck %s --check-prefix=HOST -!RUN: bbc -fopenmp-is-target-device -emit-fir -o - %s | FileCheck %s --check-prefix=DEVICE-FLAG-ONLY - -!DEVICE: module attributes {{{.*}}, omp.is_target_device = true{{.*}}} -!HOST: module attributes {{{.*}}, omp.is_target_device = false{{.*}}} -!DEVICE-FLAG-ONLY: module attributes {{{.*}}" -!DEVICE-FLAG-ONLY-NOT: , omp.is_target_device = {{.*}} -!DEVICE-FLAG-ONLY-SAME: } -subroutine omp_subroutine() -end subroutine omp_subroutine diff --git a/flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 b/flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 deleted file mode 100644 index 86c4d917fa51..000000000000 --- a/flang/test/Lower/OpenMP/FIR/lastprivate-commonblock.f90 +++ /dev/null @@ -1,49 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s - -!CHECK: func.func @_QPlastprivate_common() { -!CHECK: %[[val_0:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -!CHECK: %[[val_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFlastprivate_commonEi"} -!CHECK: %[[val_2:.*]] = fir.address_of(@c_) : !fir.ref> -!CHECK: %[[val_3:.*]] = fir.convert %[[val_2]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0:.*]] = arith.constant 0 : index -!CHECK: %[[val_4:.*]] = fir.coordinate_of %[[val_3]], %[[val_c0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_5:.*]] = fir.convert %[[val_4]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_6:.*]] = fir.convert %[[val_2]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c4:.*]] = arith.constant 4 : index -!CHECK: %[[val_7:.*]] = fir.coordinate_of %[[val_6]], %[[val_c4]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_8:.*]] = fir.convert %[[val_7]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_9:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivate_commonEx"} -!CHECK: %[[val_10:.*]] = fir.alloca f32 {bindc_name = "y", pinned, uniq_name = "_QFlastprivate_commonEy"} -!CHECK: %[[val_c1_i32:.*]] = arith.constant 1 : i32 -!CHECK: %[[val_c100_i32:.*]] = arith.constant 100 : i32 -!CHECK: %[[val_c1_i32_0:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[arg:.*]]) : i32 = (%[[val_c1_i32]]) to (%[[val_c100_i32]]) inclusive step (%[[val_c1_i32_0]]) { -!CHECK: fir.store %[[arg]] to %[[val_0]] : !fir.ref -!CHECK: %[[val_11:.*]] = arith.addi %[[arg]], %[[val_c1_i32_0]] : i32 -!CHECK: %[[val_c0_i32:.*]] = arith.constant 0 : i32 -!CHECK: %[[val_12:.*]] = arith.cmpi slt, %[[val_c1_i32_0]], %[[val_c0_i32]] : i32 -!CHECK: %[[val_13:.*]] = arith.cmpi slt, %[[val_11]], %[[val_c100_i32]] : i32 -!CHECK: %[[val_14:.*]] = arith.cmpi sgt, %[[val_11]], %[[val_c100_i32]] : i32 -!CHECK: %[[val_15:.*]] = arith.select %[[val_12]], %[[val_13]], %[[val_14]] : i1 -!CHECK: fir.if %[[val_15]] { -!CHECK: fir.store %[[val_11]] to %[[val_0]] : !fir.ref -!CHECK: %[[val_16:.*]] = fir.load %[[val_9]] : !fir.ref -!CHECK: fir.store %[[val_16]] to %[[val_5]] : !fir.ref -!CHECK: %[[val_17:.*]] = fir.load %[[val_10]] : !fir.ref -!CHECK: fir.store %[[val_17]] to %[[val_8]] : !fir.ref -!CHECK: } -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } -subroutine lastprivate_common - common /c/ x, y - real x, y - !$omp do lastprivate(/c/) - do i=1,100 - end do - !$omp end do -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/location.f90 b/flang/test/Lower/OpenMP/FIR/location.f90 deleted file mode 100644 index 6a7fb3c03584..000000000000 --- a/flang/test/Lower/OpenMP/FIR/location.f90 +++ /dev/null @@ -1,71 +0,0 @@ -! This test checks location of OpenMP constructs and clauses - -!RUN: %flang_fc1 -emit-fir -fopenmp -mmlir --mlir-print-debuginfo %s -o - | FileCheck %s - -!CHECK-LABEL: sub_parallel -subroutine sub_parallel() - print *, x -!CHECK: omp.parallel { - !$omp parallel - print *, x -!CHECK: omp.terminator loc(#[[PAR_LOC:.*]]) -!CHECK: } loc(#[[PAR_LOC]]) - !$omp end parallel - print *, x -end - -!CHECK-LABEL: sub_target -subroutine sub_target() - print *, x -!CHECK: omp.target {{.*}} { - !$omp target - print *, x -!CHECK: omp.terminator loc(#[[TAR_LOC:.*]]) -!CHECK: } loc(#[[TAR_LOC]]) - !$omp end target - print *, x -end - -!CHECK-LABEL: sub_loop -subroutine sub_loop() -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest {{.*}} { - !$omp do - do i=1,10 - print *, i -!CHECK: omp.yield loc(#[[LOOP_LOC:.*]]) -!CHECK: } loc(#[[LOOP_LOC]]) -!CHECK: omp.terminator loc(#[[LOOP_LOC]]) -!CHECK: } loc(#[[LOOP_LOC]]) - end do - !$omp end do -end - -!CHECK-LABEL: sub_standalone -subroutine sub_standalone() - !CHECK: omp.barrier loc(#[[BAR_LOC:.*]]) - !$omp barrier - !CHECK: omp.taskwait loc(#[[TW_LOC:.*]]) - !$omp taskwait - !CHECK: omp.taskyield loc(#[[TY_LOC:.*]]) - !$omp taskyield -end - -subroutine sub_if(c) - logical(kind=4) :: c - !CHECK: %[[CVT:.*]] = fir.convert %{{.*}} : (!fir.logical<4>) -> i1 loc(#[[IF_LOC:.*]]) - !CHECK: omp.task if(%[[CVT]]) - !$omp task if(c) - print *, "Task" - !$omp end task - !CHECK: } loc(#[[TASK_LOC:.*]]) -end subroutine - -!CHECK: #[[PAR_LOC]] = loc("{{.*}}location.f90":9:9) -!CHECK: #[[TAR_LOC]] = loc("{{.*}}location.f90":21:9) -!CHECK: #[[LOOP_LOC]] = loc("{{.*}}location.f90":33:9) -!CHECK: #[[BAR_LOC]] = loc("{{.*}}location.f90":47:9) -!CHECK: #[[TW_LOC]] = loc("{{.*}}location.f90":49:9) -!CHECK: #[[TY_LOC]] = loc("{{.*}}location.f90":51:9) -!CHECK: #[[IF_LOC]] = loc("{{.*}}location.f90":58:14) -!CHECK: #[[TASK_LOC]] = loc("{{.*}}location.f90":58:9) diff --git a/flang/test/Lower/OpenMP/FIR/loop-combined.f90 b/flang/test/Lower/OpenMP/FIR/loop-combined.f90 deleted file mode 100644 index 6c6618dc9fb5..000000000000 --- a/flang/test/Lower/OpenMP/FIR/loop-combined.f90 +++ /dev/null @@ -1,83 +0,0 @@ -! This test checks lowering of OpenMP combined loop constructs. - -! RUN: bbc -fopenmp -emit-fir %s -o - | FileCheck %s -! RUN: %flang_fc1 -fopenmp -emit-fir %s -o - | FileCheck %s - -program main - integer :: i - - ! TODO When DISTRIBUTE, TASKLOOP and TEAMS are supported add: - ! - DISTRIBUTE PARALLEL DO SIMD - ! - DISTRIBUTE PARALLEL DO - ! - DISTRIBUTE SIMD - ! - TARGET TEAMS DISTRIBUTE PARALLEL DO SIMD - ! - TARGET TEAMS DISTRIBUTE PARALLEL DO - ! - TARGET TEAMS DISTRIBUTE SIMD - ! - TARGET TEAMS DISTRIBUTE - ! - TASKLOOP SIMD - ! - TEAMS DISTRIBUTE PARALLEL DO SIMD - ! - TEAMS DISTRIBUTE PARALLEL DO - ! - TEAMS DISTRIBUTE SIMD - ! - TEAMS DISTRIBUTE - - ! ---------------------------------------------------------------------------- - ! DO SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.wsloop - !$omp do simd - do i = 1, 10 - end do - !$omp end do simd - - ! ---------------------------------------------------------------------------- - ! PARALLEL DO SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.parallel - ! CHECK: omp.wsloop - !$omp parallel do simd - do i = 1, 10 - end do - !$omp end parallel do simd - - ! ---------------------------------------------------------------------------- - ! PARALLEL DO - ! ---------------------------------------------------------------------------- - ! CHECK: omp.parallel - ! CHECK: omp.wsloop - !$omp parallel do - do i = 1, 10 - end do - !$omp end parallel do - - ! ---------------------------------------------------------------------------- - ! TARGET PARALLEL DO SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target - ! CHECK: omp.parallel - ! CHECK: omp.wsloop - !$omp target parallel do simd - do i = 1, 10 - end do - !$omp end target parallel do simd - - ! ---------------------------------------------------------------------------- - ! TARGET PARALLEL DO - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target - ! CHECK: omp.parallel - ! CHECK: omp.wsloop - !$omp target parallel do - do i = 1, 10 - end do - !$omp end target parallel do - - ! ---------------------------------------------------------------------------- - ! TARGET SIMD - ! ---------------------------------------------------------------------------- - ! CHECK: omp.target - ! CHECK: omp.simd - !$omp target simd - do i = 1, 10 - end do - !$omp end target simd -end program main diff --git a/flang/test/Lower/OpenMP/FIR/map-component-ref.f90 b/flang/test/Lower/OpenMP/FIR/map-component-ref.f90 deleted file mode 100644 index 6799941701f4..000000000000 --- a/flang/test/Lower/OpenMP/FIR/map-component-ref.f90 +++ /dev/null @@ -1,33 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s -! RUN: bbc -fopenmp -emit-fir %s -o - | FileCheck %s - -! CHECK: %[[V0:[0-9]+]] = fir.alloca !fir.type<_QFfooTt0{a0:i32,a1:i32}> {bindc_name = "a", uniq_name = "_QFfooEa"} -! CHECK: %[[V1:[0-9]+]] = fir.declare %[[V0]] {uniq_name = "_QFfooEa"} : (!fir.ref>) -> !fir.ref> -! CHECK: %[[V2:[0-9]+]] = fir.field_index a1, !fir.type<_QFfooTt0{a0:i32,a1:i32}> -! CHECK: %[[V3:[0-9]+]] = fir.coordinate_of %[[V1]], %[[V2]] : (!fir.ref>, !fir.field) -> !fir.ref -! CHECK: %[[V4:[0-9]+]] = omp.map.info var_ptr(%[[V3]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "a%a1"} -! CHECK: %[[V5:[0-9]+]] = omp.map.info var_ptr(%[[V1]] : !fir.ref>, !fir.type<_QFfooTt0{a0:i32,a1:i32}>) map_clauses(implicit, tofrom) capture(ByRef) -> !fir.ref> {name = "a"} -! CHECK: omp.target map_entries(%[[V4]] -> %arg0, %[[V5]] -> %arg1 : !fir.ref, !fir.ref>) { -! CHECK: ^bb0(%arg0: !fir.ref, %arg1: !fir.ref>): -! CHECK: %c0_i32 = arith.constant 0 : i32 -! CHECK: %[[V6:[0-9]+]] = fir.declare %arg1 {uniq_name = "_QFfooEa"} : (!fir.ref>) -> !fir.ref> -! CHECK: %[[V7:[0-9]+]] = fir.field_index a1, !fir.type<_QFfooTt0{a0:i32,a1:i32}> -! CHECK: %[[V8:[0-9]+]] = fir.coordinate_of %[[V6]], %[[V7]] : (!fir.ref>, !fir.field) -> !fir.ref -! CHECK: fir.store %c0_i32 to %[[V8]] : !fir.ref -! CHECK: omp.terminator -! CHECK: } - -subroutine foo() - implicit none - - type t0 - integer :: a0, a1 - end type - - type(t0) :: a - - !$omp target map(a%a1) - a%a1 = 0 - !$omp end target -end - diff --git a/flang/test/Lower/OpenMP/FIR/master.f90 b/flang/test/Lower/OpenMP/FIR/master.f90 deleted file mode 100644 index dd9910da2f41..000000000000 --- a/flang/test/Lower/OpenMP/FIR/master.f90 +++ /dev/null @@ -1,100 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect" - -!=============================================================================== -! parallel construct with function call which has master construct internally -!=============================================================================== -!FIRDialect-LABEL: func @_QPomp_master -subroutine omp_master() - -!OMPDialect: omp.master { -!$omp master - - !FIRDialect: fir.call @_QPmaster() {{.*}}: () -> () - call master() - -!OMPDialect: omp.terminator -!$omp end master - -end subroutine omp_master - -!FIRDialect-LABEL: func @_QPparallel_function_master -subroutine parallel_function_master() - -!OMPDialect: omp.parallel { -!$omp parallel - - !FIRDialect: fir.call @_QPfoo() {{.*}}: () -> () - call foo() - -!OMPDialect: omp.terminator -!$omp end parallel - -end subroutine parallel_function_master - -!=============================================================================== -! master construct nested inside parallel construct -!=============================================================================== - -!FIRDialect-LABEL: func @_QPomp_parallel_master -subroutine omp_parallel_master() - -!OMPDialect: omp.parallel { -!$omp parallel - !FIRDialect: fir.call @_QPparallel() {{.*}}: () -> () - call parallel() - -!OMPDialect: omp.master { -!$omp master - - !FIRDialect: fir.call @_QPparallel_master() {{.*}}: () -> () - call parallel_master() - -!OMPDialect: omp.terminator -!$omp end master - -!OMPDialect: omp.terminator -!$omp end parallel - -end subroutine omp_parallel_master - -!=============================================================================== -! master construct nested inside parallel construct with conditional flow -!=============================================================================== - -!FIRDialect-LABEL: func @_QPomp_master_parallel -subroutine omp_master_parallel() - integer :: alpha, beta, gama - alpha = 4 - beta = 5 - gama = 6 - -!OMPDialect: omp.master { -!$omp master - - !FIRDialect: %{{.*}} = fir.load %{{.*}} - !FIRDialect: %{{.*}} = fir.load %{{.*}} - !FIRDialect: %[[RESULT:.*]] = arith.cmpi sge, %{{.*}}, %{{.*}} - !FIRDialect: fir.if %[[RESULT]] { - if (alpha .ge. gama) then - -!OMPDialect: omp.parallel { -!$omp parallel - !FIRDialect: fir.call @_QPinside_if_parallel() {{.*}}: () -> () - call inside_if_parallel() - -!OMPDialect: omp.terminator -!$omp end parallel - - !FIRDialect: %{{.*}} = fir.load %{{.*}} - !FIRDialect: %{{.*}} = fir.load %{{.*}} - !FIRDialect: %{{.*}} = arith.addi %{{.*}}, %{{.*}} - !FIRDialect: fir.store %{{.*}} to %{{.*}} - beta = alpha + gama - end if - !FIRDialect: else - -!OMPDialect: omp.terminator -!$omp end master - -end subroutine omp_master_parallel diff --git a/flang/test/Lower/OpenMP/FIR/omp-declare-target-program-var.f90 b/flang/test/Lower/OpenMP/FIR/omp-declare-target-program-var.f90 deleted file mode 100644 index 0da76f6d9ad2..000000000000 --- a/flang/test/Lower/OpenMP/FIR/omp-declare-target-program-var.f90 +++ /dev/null @@ -1,12 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s --check-prefixes=HOST,ALL -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=ALL - -PROGRAM main - ! HOST-DAG: %0 = fir.alloca f32 {bindc_name = "i", uniq_name = "_QFEi"} - REAL :: I - ! ALL-DAG: fir.global internal @_QFEi {omp.declare_target = #omp.declaretarget} : f32 { - ! ALL-DAG: %0 = fir.undefined f32 - ! ALL-DAG: fir.has_value %0 : f32 - ! ALL-DAG: } - !$omp declare target(I) -END diff --git a/flang/test/Lower/OpenMP/FIR/omp-is-gpu.f90 b/flang/test/Lower/OpenMP/FIR/omp-is-gpu.f90 deleted file mode 100644 index ac8d24974801..000000000000 --- a/flang/test/Lower/OpenMP/FIR/omp-is-gpu.f90 +++ /dev/null @@ -1,16 +0,0 @@ -!REQUIRES: amdgpu-registered-target, nvptx-registered-target - -!RUN: %flang_fc1 -triple amdgcn-amd-amdhsa -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s -!RUN: %flang_fc1 -triple nvptx64-nvidia-cuda -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s -!RUN: bbc -fopenmp -fopenmp-is-target-device -fopenmp-is-gpu -emit-fir -o - %s | FileCheck %s - -!RUN: not %flang_fc1 -triple amdgcn-amd-amdhsa -emit-fir -fopenmp %s -o - 2>&1 | FileCheck %s --check-prefix=FLANG-ERROR -!RUN: not %flang_fc1 -triple nvptx64-nvidia-cuda -emit-fir -fopenmp %s -o - 2>&1 | FileCheck %s --check-prefix=FLANG-ERROR -!RUN: not bbc -fopenmp -fopenmp-is-gpu -emit-fir %s -o - 2>&1 | FileCheck %s --check-prefix=BBC-ERROR - -!CHECK: module attributes {{{.*}}omp.is_gpu = true -subroutine omp_subroutine() -end subroutine omp_subroutine - -!FLANG-ERROR: error: OpenMP AMDGPU/NVPTX is only prepared to deal with device code. -!BBC-ERROR: FATAL: -fopenmp-is-gpu can only be set if -fopenmp-is-target-device is also set diff --git a/flang/test/Lower/OpenMP/FIR/ordered-threads.f90 b/flang/test/Lower/OpenMP/FIR/ordered-threads.f90 deleted file mode 100644 index 2dea4c857e87..000000000000 --- a/flang/test/Lower/OpenMP/FIR/ordered-threads.f90 +++ /dev/null @@ -1,40 +0,0 @@ -! This test checks lowering of OpenMP ordered directive with threads Clause. -! Without clause in ordered direcitve, it behaves as if threads clause is -! specified. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefix=FIRDialect -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefix=LLVMIRDialect -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --fir-to-llvm-ir | tco | FileCheck %s --check-prefix=LLVMIR - -subroutine ordered - integer :: i - integer :: a(20) - -!FIRDialect: omp.ordered.region { -!LLVMIRDialect: omp.ordered.region { -!LLVMIR: [[TMP0:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB0:[0-9]+]]) -!LLVMIR-NEXT: call void @__kmpc_ordered(ptr @[[GLOB0]], i32 [[TMP0]]) -!$OMP ORDERED - a(i) = a(i-1) + 1 -!FIRDialect: omp.terminator -!FIRDialect-NEXT: } -!LLVMIRDialect: omp.terminator -!LLVMIRDialect-NEXT: } -!LLVMIR: call void @__kmpc_end_ordered(ptr @[[GLOB0]], i32 [[TMP0]]) -!$OMP END ORDERED - -!FIRDialect: omp.ordered.region { -!LLVMIRDialect: omp.ordered.region { -!LLVMIR: [[TMP1:%.*]] = call i32 @__kmpc_global_thread_num(ptr @[[GLOB1:[0-9]+]]) -!LLVMIR-NEXT: call void @__kmpc_ordered(ptr @[[GLOB1]], i32 [[TMP1]]) -!$OMP ORDERED THREADS - a(i) = a(i-1) + 1 -!FIRDialect: omp.terminator -!FIRDialect-NEXT: } -!LLVMIRDialect: omp.terminator -!LLVMIRDialect-NEXT: } -!LLVMIR: call void @__kmpc_end_ordered(ptr @[[GLOB1]], i32 [[TMP1]]) -!LLVMIR-NEXT: ret void -!$OMP END ORDERED - -end diff --git a/flang/test/Lower/OpenMP/FIR/parallel-firstprivate-clause-scalar.f90 b/flang/test/Lower/OpenMP/FIR/parallel-firstprivate-clause-scalar.f90 deleted file mode 100644 index 37f916ecb84c..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-firstprivate-clause-scalar.f90 +++ /dev/null @@ -1,159 +0,0 @@ -! This test checks lowering of `FIRSTPRIVATE` clause for scalar types. - -! REQUIRES: shell -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s --check-prefix=FIRDialect - -!FIRDialect-DAG: func @_QPfirstprivate_complex(%[[ARG1:.*]]: !fir.ref>{{.*}}, %[[ARG2:.*]]: !fir.ref>{{.*}}) { -!FIRDialect: omp.parallel { -!FIRDialect: %[[ARG1_PVT:.*]] = fir.alloca !fir.complex<4> {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_complexEarg1"} -!FIRDialect: %[[ARG1_VAL:.*]] = fir.load %[[ARG1]] : !fir.ref> -!FIRDialect: fir.store %[[ARG1_VAL]] to %[[ARG1_PVT]] : !fir.ref> -!FIRDialect: %[[ARG2_PVT:.*]] = fir.alloca !fir.complex<8> {bindc_name = "arg2", pinned, uniq_name = "_QFfirstprivate_complexEarg2"} -!FIRDialect: %[[ARG2_VAL:.*]] = fir.load %[[ARG2]] : !fir.ref> -!FIRDialect: fir.store %[[ARG2_VAL]] to %[[ARG2_PVT]] : !fir.ref> -!FIRDialect: fir.call @_QPfoo(%[[ARG1_PVT]], %[[ARG2_PVT]]) {{.*}}: (!fir.ref>, !fir.ref>) -> () -!FIRDialect: omp.terminator -!FIRDialect: } - -subroutine firstprivate_complex(arg1, arg2) - complex(4) :: arg1 - complex(8) :: arg2 - -!$OMP PARALLEL FIRSTPRIVATE(arg1, arg2) - call foo(arg1, arg2) -!$OMP END PARALLEL - -end subroutine - -!FIRDialect-DAG: func @_QPfirstprivate_integer(%[[ARG1:.*]]: !fir.ref{{.*}}, %[[ARG2:.*]]: !fir.ref{{.*}}, %[[ARG3:.*]]: !fir.ref{{.*}}, %[[ARG4:.*]]: !fir.ref{{.*}}, %[[ARG5:.*]]: !fir.ref{{.*}}, %[[ARG6:.*]]: !fir.ref{{.*}}) { -!FIRDialect: omp.parallel { -!FIRDialect: %[[ARG1_PVT:.*]] = fir.alloca i32 {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_integerEarg1"} -!FIRDialect: %[[ARG1_VAL:.*]] = fir.load %[[ARG1]] : !fir.ref -!FIRDialect: fir.store %[[ARG1_VAL]] to %[[ARG1_PVT]] : !fir.ref -!FIRDialect: %[[ARG2_PVT:.*]] = fir.alloca i8 {bindc_name = "arg2", pinned, uniq_name = "_QFfirstprivate_integerEarg2"} -!FIRDialect: %[[ARG2_VAL:.*]] = fir.load %[[ARG2]] : !fir.ref -!FIRDialect: fir.store %[[ARG2_VAL]] to %[[ARG2_PVT]] : !fir.ref -!FIRDialect: %[[ARG3_PVT:.*]] = fir.alloca i16 {bindc_name = "arg3", pinned, uniq_name = "_QFfirstprivate_integerEarg3"} -!FIRDialect: %[[ARG3_VAL:.*]] = fir.load %[[ARG3]] : !fir.ref -!FIRDialect: fir.store %[[ARG3_VAL]] to %[[ARG3_PVT]] : !fir.ref -!FIRDialect: %[[ARG4_PVT:.*]] = fir.alloca i32 {bindc_name = "arg4", pinned, uniq_name = "_QFfirstprivate_integerEarg4"} -!FIRDialect: %[[ARG4_VAL:.*]] = fir.load %[[ARG4]] : !fir.ref -!FIRDialect: fir.store %[[ARG4_VAL]] to %[[ARG4_PVT]] : !fir.ref -!FIRDialect: %[[ARG5_PVT:.*]] = fir.alloca i64 {bindc_name = "arg5", pinned, uniq_name = "_QFfirstprivate_integerEarg5"} -!FIRDialect: %[[ARG5_VAL:.*]] = fir.load %[[ARG5]] : !fir.ref -!FIRDialect: fir.store %[[ARG5_VAL]] to %[[ARG5_PVT]] : !fir.ref -!FIRDialect: %[[ARG6_PVT:.*]] = fir.alloca i128 {bindc_name = "arg6", pinned, uniq_name = "_QFfirstprivate_integerEarg6"} -!FIRDialect: %[[ARG6_VAL:.*]] = fir.load %[[ARG6]] : !fir.ref -!FIRDialect: fir.store %[[ARG6_VAL]] to %[[ARG6_PVT]] : !fir.ref -!FIRDialect: fir.call @_QPbar(%[[ARG1_PVT]], %[[ARG2_PVT]], %[[ARG3_PVT]], %[[ARG4_PVT]], %[[ARG5_PVT]], %[[ARG6_PVT]]) {{.*}}: (!fir.ref, !fir.ref, !fir.ref, !fir.ref, !fir.ref, !fir.ref) -> () -!FIRDialect: omp.terminator -!FIRDialect: } - -subroutine firstprivate_integer(arg1, arg2, arg3, arg4, arg5, arg6) - integer :: arg1 - integer(kind=1) :: arg2 - integer(kind=2) :: arg3 - integer(kind=4) :: arg4 - integer(kind=8) :: arg5 - integer(kind=16) :: arg6 - -!$OMP PARALLEL FIRSTPRIVATE(arg1, arg2, arg3, arg4, arg5, arg6) - call bar(arg1, arg2, arg3, arg4, arg5, arg6) -!$OMP END PARALLEL - -end subroutine - -!FIRDialect-DAG: func @_QPfirstprivate_logical(%[[ARG1:.*]]: !fir.ref>{{.*}}, %[[ARG2:.*]]: !fir.ref>{{.*}}, %[[ARG3:.*]]: !fir.ref>{{.*}}, %[[ARG4:.*]]: !fir.ref>{{.*}}, %[[ARG5:.*]]: !fir.ref>{{.*}}) { -!FIRDialect: omp.parallel { -!FIRDialect: %[[ARG1_PVT:.*]] = fir.alloca !fir.logical<4> {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_logicalEarg1"} -!FIRDialect: %[[ARG1_VAL:.*]] = fir.load %[[ARG1]] : !fir.ref> -!FIRDialect: fir.store %[[ARG1_VAL]] to %[[ARG1_PVT]] : !fir.ref> -!FIRDialect: %[[ARG2_PVT:.*]] = fir.alloca !fir.logical<1> {bindc_name = "arg2", pinned, uniq_name = "_QFfirstprivate_logicalEarg2"} -!FIRDialect: %[[ARG2_VAL:.*]] = fir.load %[[ARG2]] : !fir.ref> -!FIRDialect: fir.store %[[ARG2_VAL]] to %[[ARG2_PVT]] : !fir.ref> -!FIRDialect: %[[ARG3_PVT:.*]] = fir.alloca !fir.logical<2> {bindc_name = "arg3", pinned, uniq_name = "_QFfirstprivate_logicalEarg3"} -!FIRDialect: %[[ARG3_VAL:.*]] = fir.load %[[ARG3]] : !fir.ref> -!FIRDialect: fir.store %[[ARG3_VAL]] to %[[ARG3_PVT]] : !fir.ref> -!FIRDialect: %[[ARG4_PVT:.*]] = fir.alloca !fir.logical<4> {bindc_name = "arg4", pinned, uniq_name = "_QFfirstprivate_logicalEarg4"} -!FIRDialect: %[[ARG4_VAL:.*]] = fir.load %[[ARG4]] : !fir.ref> -!FIRDialect: fir.store %[[ARG4_VAL]] to %[[ARG4_PVT]] : !fir.ref> -!FIRDialect: %[[ARG5_PVT:.*]] = fir.alloca !fir.logical<8> {bindc_name = "arg5", pinned, uniq_name = "_QFfirstprivate_logicalEarg5"} -!FIRDialect: %[[ARG5_VAL:.*]] = fir.load %[[ARG5]] : !fir.ref> -!FIRDialect: fir.store %[[ARG5_VAL]] to %[[ARG5_PVT]] : !fir.ref> -!FIRDialect: fir.call @_QPbaz(%[[ARG1_PVT]], %[[ARG2_PVT]], %[[ARG3_PVT]], %[[ARG4_PVT]], %[[ARG5_PVT]]) {{.*}}: (!fir.ref>, !fir.ref>, !fir.ref>, !fir.ref>, !fir.ref>) -> () -!FIRDialect: omp.terminator -!FIRDialect: } - -subroutine firstprivate_logical(arg1, arg2, arg3, arg4, arg5) - logical :: arg1 - logical(kind=1) :: arg2 - logical(kind=2) :: arg3 - logical(kind=4) :: arg4 - logical(kind=8) :: arg5 - -!$OMP PARALLEL FIRSTPRIVATE(arg1, arg2, arg3, arg4, arg5) - call baz(arg1, arg2, arg3, arg4, arg5) -!$OMP END PARALLEL - -end subroutine - -!FIRDialect-DAG: func @_QPfirstprivate_real(%[[ARG1:.*]]: !fir.ref{{.*}}, %[[ARG2:.*]]: !fir.ref{{.*}}, %[[ARG3:.*]]: !fir.ref{{.*}}, %[[ARG4:.*]]: !fir.ref{{.*}}, %[[ARG5:.*]]: !fir.ref{{.*}}, %[[ARG6:.*]]: !fir.ref{{.*}}) { -!FIRDialect: omp.parallel { -!FIRDialect: %[[ARG1_PVT:.*]] = fir.alloca f32 {bindc_name = "arg1", pinned, uniq_name = "_QFfirstprivate_realEarg1"} -!FIRDialect: %[[ARG1_VAL:.*]] = fir.load %[[ARG1]] : !fir.ref -!FIRDialect: fir.store %[[ARG1_VAL]] to %[[ARG1_PVT]] : !fir.ref -!FIRDialect: %[[ARG2_PVT:.*]] = fir.alloca f16 {bindc_name = "arg2", pinned, uniq_name = "_QFfirstprivate_realEarg2"} -!FIRDialect: %[[ARG2_VAL:.*]] = fir.load %[[ARG2]] : !fir.ref -!FIRDialect: fir.store %[[ARG2_VAL]] to %[[ARG2_PVT]] : !fir.ref -!FIRDialect: %[[ARG3_PVT:.*]] = fir.alloca f32 {bindc_name = "arg3", pinned, uniq_name = "_QFfirstprivate_realEarg3"} -!FIRDialect: %[[ARG3_VAL:.*]] = fir.load %[[ARG3]] : !fir.ref -!FIRDialect: fir.store %[[ARG3_VAL]] to %[[ARG3_PVT]] : !fir.ref -!FIRDialect: %[[ARG4_PVT:.*]] = fir.alloca f64 {bindc_name = "arg4", pinned, uniq_name = "_QFfirstprivate_realEarg4"} -!FIRDialect: %[[ARG4_VAL:.*]] = fir.load %[[ARG4]] : !fir.ref -!FIRDialect: fir.store %[[ARG4_VAL]] to %[[ARG4_PVT]] : !fir.ref -!FIRDialect: %[[ARG5_PVT:.*]] = fir.alloca f80 {bindc_name = "arg5", pinned, uniq_name = "_QFfirstprivate_realEarg5"} -!FIRDialect: %[[ARG5_VAL:.*]] = fir.load %[[ARG5]] : !fir.ref -!FIRDialect: fir.store %[[ARG5_VAL]] to %[[ARG5_PVT]] : !fir.ref -!FIRDialect: %[[ARG6_PVT:.*]] = fir.alloca f128 {bindc_name = "arg6", pinned, uniq_name = "_QFfirstprivate_realEarg6"} -!FIRDialect: %[[ARG6_VAL:.*]] = fir.load %[[ARG6]] : !fir.ref -!FIRDialect: fir.store %[[ARG6_VAL]] to %[[ARG6_PVT]] : !fir.ref -!FIRDialect: fir.call @_QPqux(%[[ARG1_PVT]], %[[ARG2_PVT]], %[[ARG3_PVT]], %[[ARG4_PVT]], %[[ARG5_PVT]], %[[ARG6_PVT]]) {{.*}}: (!fir.ref, !fir.ref, !fir.ref, !fir.ref, !fir.ref, !fir.ref) -> () -!FIRDialect: omp.terminator -!FIRDialect: } - -subroutine firstprivate_real(arg1, arg2, arg3, arg4, arg5, arg6) - real :: arg1 - real(kind=2) :: arg2 - real(kind=4) :: arg3 - real(kind=8) :: arg4 - real(kind=10) :: arg5 - real(kind=16) :: arg6 - -!$OMP PARALLEL FIRSTPRIVATE(arg1, arg2, arg3, arg4, arg5, arg6) - call qux(arg1, arg2, arg3, arg4, arg5, arg6) -!$OMP END PARALLEL - -end subroutine - -!FIRDialect-LABEL: func.func @_QPmultiple_firstprivate( -!FIRDialect-SAME: %[[A_ADDR:.*]]: !fir.ref {fir.bindc_name = "a"}, -!FIRDialect-SAME: %[[B_ADDR:.*]]: !fir.ref {fir.bindc_name = "b"}) { -!FIRDialect: omp.parallel { -!FIRDialect: %[[A_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "a", pinned, uniq_name = "_QFmultiple_firstprivateEa"} -!FIRDialect: %[[A:.*]] = fir.load %[[A_ADDR]] : !fir.ref -!FIRDialect: fir.store %[[A]] to %[[A_PRIV_ADDR]] : !fir.ref -!FIRDialect: %[[B_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "b", pinned, uniq_name = "_QFmultiple_firstprivateEb"} -!FIRDialect: %[[B:.*]] = fir.load %[[B_ADDR]] : !fir.ref -!FIRDialect: fir.store %[[B]] to %[[B_PRIV_ADDR]] : !fir.ref -!FIRDialect: fir.call @_QPquux(%[[A_PRIV_ADDR]], %[[B_PRIV_ADDR]]) {{.*}}: (!fir.ref, !fir.ref) -> () -!FIRDialect: omp.terminator -!FIRDialect: } -!FIRDialect: return -!FIRDialect: } - -subroutine multiple_firstprivate(a, b) - integer :: a, b -!$OMP PARALLEL FIRSTPRIVATE(a) FIRSTPRIVATE(b) - call quux(a, b) -!$OMP END PARALLEL -end subroutine multiple_firstprivate diff --git a/flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 b/flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 deleted file mode 100644 index 16832355f5d1..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-lastprivate-clause-scalar.f90 +++ /dev/null @@ -1,261 +0,0 @@ -! This test checks lowering of `LASTPRIVATE` clause for scalar types. - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: %flang_fc1 -fopenmp -emit-fir -flang-deprecated-no-hlfir %s -o - | FileCheck %s - -!CHECK: func @_QPlastprivate_character(%[[ARG1:.*]]: !fir.boxchar<1>{{.*}}) { -!CHECK-DAG: %[[ARG1_UNBOX:.*]]:2 = fir.unboxchar -!CHECK-DAG: %[[FIVE:.*]] = arith.constant 5 : index -!CHECK-DAG: %[[ARG1_REF:.*]] = fir.convert %[[ARG1_UNBOX]]#0 : (!fir.ref>) -> !fir.ref> - -!CHECK: omp.parallel { -!CHECK-DAG: %[[ARG1_PVT:.*]] = fir.alloca !fir.char<1,5> {bindc_name = "arg1", - -! Check that we are accessing the clone inside the loop -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { -!CHECK: %[[UNIT:.*]] = arith.constant 6 : i32 -!CHECK-NEXT: %[[ADDR:.*]] = fir.address_of(@_QQclX -!CHECK-NEXT: %[[CVT0:.*]] = fir.convert %[[ADDR]] -!CHECK-NEXT: %[[CNST:.*]] = arith.constant -!CHECK-NEXT: %[[CALL_BEGIN_IO:.*]] = fir.call @_FortranAioBeginExternalListOutput(%[[UNIT]], %[[CVT0]], %[[CNST]]) {{.*}}: (i32, !fir.ref, i32) -> !fir.ref -!CHECK-NEXT: %[[CVT_0_1:.*]] = fir.convert %[[ARG1_PVT]] -!CHECK-NEXT: %[[CVT_0_2:.*]] = fir.convert %[[FIVE]] -!CHECK-NEXT: %[[CALL_OP_ASCII:.*]] = fir.call @_FortranAioOutputAscii(%[[CALL_BEGIN_IO]], %[[CVT_0_1]], %[[CVT_0_2]]) -!CHECK-NEXT: %[[CALL_END_IO:.*]] = fir.call @_FortranAioEndIoStatement(%[[CALL_BEGIN_IO]]) - -! Testing last iteration check -!CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[T1:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 -!CHECK: %[[T2:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 -!CHECK: %[[T3:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 -!CHECK: %[[IV_CMP:.*]] = arith.select %[[T1]], %[[T2]], %[[T3]] : i1 -!CHECK: fir.if %[[IV_CMP]] { -!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref - -! Testing lastprivate val update -!CHECK-DAG: %[[CVT:.*]] = fir.convert %[[ARG1_REF]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: %[[CVT1:.*]] = fir.convert %[[ARG1_PVT]] : (!fir.ref>) -> !fir.ref -!CHECK: fir.call @llvm.memmove.p0.p0.i64(%[[CVT]], %[[CVT1]]{{.*}}) -!CHECK: } -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -subroutine lastprivate_character(arg1) - character(5) :: arg1 -!$OMP PARALLEL -!$OMP DO LASTPRIVATE(arg1) -do n = 1, 5 - arg1(n:n) = 'c' - print *, arg1 -end do -!$OMP END DO -!$OMP END PARALLEL -end subroutine - -!CHECK: func @_QPlastprivate_int(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}) { -!CHECK-DAG: omp.parallel { -!CHECK-DAG: %[[CLONE:.*]] = fir.alloca i32 {bindc_name = "arg1" -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { - -! Testing last iteration check -!CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[T1:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 -!CHECK: %[[T2:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 -!CHECK: %[[T3:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 -!CHECK: %[[IV_CMP:.*]] = arith.select %[[T1]], %[[T2]], %[[T3]] : i1 -!CHECK: fir.if %[[IV_CMP]] { -!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref - -! Testing lastprivate val update -!CHECK-NEXT: %[[CLONE_LD:.*]] = fir.load %[[CLONE]] : !fir.ref -!CHECK-NEXT: fir.store %[[CLONE_LD]] to %[[ARG1]] : !fir.ref -!CHECK: } -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -subroutine lastprivate_int(arg1) - integer :: arg1 -!$OMP PARALLEL -!$OMP DO LASTPRIVATE(arg1) -do n = 1, 5 - arg1 = 2 - print *, arg1 -end do -!$OMP END DO -!$OMP END PARALLEL -print *, arg1 -end subroutine - -!CHECK: func.func @_QPmult_lastprivate_int(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "arg2"}) { -!CHECK: omp.parallel { -!CHECK-DAG: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" -!CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { - -! Testing last iteration check -!CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[T1:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 -!CHECK: %[[T2:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 -!CHECK: %[[T3:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 -!CHECK: %[[IV_CMP:.*]] = arith.select %[[T1]], %[[T2]], %[[T3]] : i1 -!CHECK: fir.if %[[IV_CMP]] { -!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref -! Testing lastprivate val update -!CHECK-DAG: %[[CLONE_LD1:.*]] = fir.load %[[CLONE1]] : !fir.ref -!CHECK-DAG: fir.store %[[CLONE_LD1]] to %[[ARG1]] : !fir.ref -!CHECK-DAG: %[[CLONE_LD2:.*]] = fir.load %[[CLONE2]] : !fir.ref -!CHECK-DAG: fir.store %[[CLONE_LD2]] to %[[ARG2]] : !fir.ref -!CHECK: } -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -subroutine mult_lastprivate_int(arg1, arg2) - integer :: arg1, arg2 -!$OMP PARALLEL -!$OMP DO LASTPRIVATE(arg1) LASTPRIVATE(arg2) -do n = 1, 5 - arg1 = 2 - arg2 = 3 - print *, arg1, arg2 -end do -!$OMP END DO -!$OMP END PARALLEL -print *, arg1, arg2 -end subroutine - -!CHECK: func.func @_QPmult_lastprivate_int2(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "arg2"}) { -!CHECK: omp.parallel { -!CHECK-DAG: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" -!CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { - -!Testing last iteration check -!CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[T1:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 -!CHECK: %[[T2:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 -!CHECK: %[[T3:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 -!CHECK: %[[IV_CMP:.*]] = arith.select %[[T1]], %[[T2]], %[[T3]] : i1 -!CHECK: fir.if %[[IV_CMP]] { -!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref -!Testing lastprivate val update -!CHECK-DAG: %[[CLONE_LD2:.*]] = fir.load %[[CLONE2]] : !fir.ref -!CHECK-DAG: fir.store %[[CLONE_LD2]] to %[[ARG2]] : !fir.ref -!CHECK-DAG: %[[CLONE_LD1:.*]] = fir.load %[[CLONE1]] : !fir.ref -!CHECK-DAG: fir.store %[[CLONE_LD1]] to %[[ARG1]] : !fir.ref -!CHECK: } -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -subroutine mult_lastprivate_int2(arg1, arg2) - integer :: arg1, arg2 -!$OMP PARALLEL -!$OMP DO LASTPRIVATE(arg1, arg2) -do n = 1, 5 - arg1 = 2 - arg2 = 3 - print *, arg1, arg2 -end do -!$OMP END DO -!$OMP END PARALLEL -print *, arg1, arg2 -end subroutine - -!CHECK: func.func @_QPfirstpriv_lastpriv_int(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}, %[[ARG2:.*]]: !fir.ref {fir.bindc_name = "arg2"}) { -!CHECK: omp.parallel { -! Firstprivate update -!CHECK-DAG: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" -!CHECK-DAG: %[[FPV_LD:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK-DAG: fir.store %[[FPV_LD]] to %[[CLONE1]] : !fir.ref -! Lastprivate Allocation -!CHECK-DAG: %[[CLONE2:.*]] = fir.alloca i32 {bindc_name = "arg2" -!CHECK-NOT: omp.barrier -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { - -! Testing last iteration check -!CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[T1:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 -!CHECK: %[[T2:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 -!CHECK: %[[T3:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 -!CHECK: %[[IV_CMP:.*]] = arith.select %[[T1]], %[[T2]], %[[T3]] : i1 -!CHECK: fir.if %[[IV_CMP]] { -!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref -! Testing lastprivate val update -!CHECK-NEXT: %[[CLONE_LD:.*]] = fir.load %[[CLONE2]] : !fir.ref -!CHECK-NEXT: fir.store %[[CLONE_LD]] to %[[ARG2]] : !fir.ref -!CHECK-NEXT: } -!CHECK-NEXT: omp.yield -!CHECK-NEXT: } -!CHECK-NEXT: omp.terminator -!CHECK-NEXT: } - -subroutine firstpriv_lastpriv_int(arg1, arg2) - integer :: arg1, arg2 -!$OMP PARALLEL -!$OMP DO FIRSTPRIVATE(arg1) LASTPRIVATE(arg2) -do n = 1, 5 - arg1 = 2 - arg2 = 3 - print *, arg1, arg2 -end do -!$OMP END DO -!$OMP END PARALLEL -print *, arg1, arg2 -end subroutine - -!CHECK: func.func @_QPfirstpriv_lastpriv_int2(%[[ARG1:.*]]: !fir.ref {fir.bindc_name = "arg1"}) { -!CHECK: omp.parallel { -! Firstprivate update -!CHECK: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "arg1" -!CHECK-NEXT: %[[FPV_LD:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK-NEXT: fir.store %[[FPV_LD]] to %[[CLONE1]] : !fir.ref -!CHECK-NEXT: omp.barrier -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[INDX_WS:.*]]) : {{.*}} { -! Testing last iteration check -!CHECK: %[[V:.*]] = arith.addi %[[INDX_WS]], %{{.*}} : i32 -!CHECK: %[[C0:.*]] = arith.constant 0 : i32 -!CHECK: %[[T1:.*]] = arith.cmpi slt, %{{.*}}, %[[C0]] : i32 -!CHECK: %[[T2:.*]] = arith.cmpi slt, %[[V]], %{{.*}} : i32 -!CHECK: %[[T3:.*]] = arith.cmpi sgt, %[[V]], %{{.*}} : i32 -!CHECK: %[[IV_CMP:.*]] = arith.select %[[T1]], %[[T2]], %[[T3]] : i1 -!CHECK: fir.if %[[IV_CMP]] { -!CHECK: fir.store %[[V]] to %{{.*}} : !fir.ref -! Testing lastprivate val update -!CHECK-NEXT: %[[CLONE_LD:.*]] = fir.load %[[CLONE1]] : !fir.ref -!CHECK-NEXT: fir.store %[[CLONE_LD]] to %[[ARG1]] : !fir.ref -!CHECK-NEXT: } -!CHECK-NEXT: omp.yield -!CHECK-NEXT: } -!CHECK-NEXT: omp.terminator -!CHECK-NEXT: } - -subroutine firstpriv_lastpriv_int2(arg1) - integer :: arg1 -!$OMP PARALLEL -!$OMP DO FIRSTPRIVATE(arg1) LASTPRIVATE(arg1) -do n = 1, 5 - arg1 = 2 - print *, arg1 -end do -!$OMP END DO -!$OMP END PARALLEL -print *, arg1 -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 b/flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 deleted file mode 100644 index fb0fb9594c35..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-private-clause-fixes.f90 +++ /dev/null @@ -1,84 +0,0 @@ -! This test checks a few bug fixes in the PRIVATE clause lowering - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -! CHECK-LABEL: multiple_private_fix -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_private_fixEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "j", uniq_name = "_QFmultiple_private_fixEj"} -! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_private_fixEx"} -! CHECK: omp.parallel { -! CHECK-DAG: %[[PRIV_J:.*]] = fir.alloca i32 {bindc_name = "j", pinned -! CHECK-DAG: %[[PRIV_I:.*]] = fir.alloca i32 {adapt.valuebyref, pinned -! CHECK-DAG: %[[PRIV_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned -! CHECK: %[[ONE:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_4:.*]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[VAL_6:.*]]) : i32 = (%[[ONE]]) to (%[[VAL_3]]) inclusive step (%[[VAL_5]]) { -! CHECK: fir.store %[[VAL_6]] to %[[PRIV_I]] : !fir.ref -! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i32) -> index -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> index -! CHECK: %[[VAL_11:.*]] = arith.constant 1 : index -! CHECK: %[[LB:.*]] = fir.convert %[[VAL_8]] : (index) -> i32 -! CHECK: %[[VAL_12:.*]]:2 = fir.do_loop %[[VAL_13:[^ ]*]] = -! CHECK-SAME: %[[VAL_8]] to %[[VAL_10]] step %[[VAL_11]] -! CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i32) { -! CHECK: fir.store %[[IV]] to %[[PRIV_J]] : !fir.ref -! CHECK: %[[LOAD:.*]] = fir.load %[[PRIV_I]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[PRIV_J]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = arith.addi %[[LOAD]], %[[VAL_15]] : i32 -! CHECK: fir.store %[[VAL_16]] to %[[PRIV_X]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_13]], %[[VAL_11]] : index -! CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_11]] : (index) -> i32 -! CHECK: %[[IVLOAD:.*]] = fir.load %[[PRIV_J]] : !fir.ref -! CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] -! CHECK: fir.result %[[VAL_17]], %[[IVINC]] : index, i32 -! CHECK: } -! CHECK: fir.store %[[VAL_12]]#1 to %[[PRIV_J]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -subroutine multiple_private_fix(gama) - integer :: i, j, x, gama -!$OMP PARALLEL DO PRIVATE(j,x) - do i = 1, gama - do j = 1, gama - x = i + j - end do - end do -!$OMP END PARALLEL DO -end subroutine - -! CHECK-LABEL: multiple_private_fix2 -! CHECK: %[[X1:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_private_fix2Ex"} -! CHECK: omp.parallel { -! CHECK: %[[X2:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFmultiple_private_fix2Ex"} -! CHECK: omp.parallel { -! CHECK: %[[X3:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFmultiple_private_fix2Ex"} -! CHECK: %[[C3:.*]] = arith.constant 1 : i32 -! CHECK: fir.store %[[C3]] to %[[X3]] : !fir.ref -! CHECK: omp.terminator -! CHECK: } -! CHECK: %[[C2:.*]] = arith.constant 1 : i32 -! CHECK: fir.store %[[C2]] to %[[X2]] : !fir.ref -! CHECK: omp.terminator -! CHECK: } -! CHECK: %[[C1:.*]] = arith.constant 1 : i32 -! CHECK: fir.store %[[C1]] to %[[X1]] : !fir.ref -! CHECK: return -subroutine multiple_private_fix2() - integer :: x - !$omp parallel private(x) - !$omp parallel private(x) - x = 1 - !$omp end parallel - x = 1 - !$omp end parallel - x = 1 -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 b/flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 deleted file mode 100644 index 2e68d25a15ed..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-private-clause.f90 +++ /dev/null @@ -1,387 +0,0 @@ -! This test checks lowering of OpenMP parallel Directive with -! `PRIVATE` clause present. - -! REQUIRES: shell -! RUN: bbc --use-desc-for-alloc=false -fopenmp -emit-fir -hlfir=false %s -o - | \ -! RUN: FileCheck %s --check-prefix=FIRDialect - -!FIRDialect: func @_QPprivate_clause(%[[ARG1:.*]]: !fir.ref{{.*}}, %[[ARG2:.*]]: !fir.ref>{{.*}}, %[[ARG3:.*]]: !fir.boxchar<1>{{.*}}, %[[ARG4:.*]]: !fir.boxchar<1>{{.*}}) { -!FIRDialect-DAG: %[[ALPHA:.*]] = fir.alloca i32 {{{.*}}, uniq_name = "{{.*}}Ealpha"} -!FIRDialect-DAG: %[[ALPHA_ARRAY:.*]] = fir.alloca !fir.array<10xi32> {{{.*}}, uniq_name = "{{.*}}Ealpha_array"} -!FIRDialect-DAG: %[[BETA:.*]] = fir.alloca !fir.char<1,5> {{{.*}}, uniq_name = "{{.*}}Ebeta"} -!FIRDialect-DAG: %[[BETA_ARRAY:.*]] = fir.alloca !fir.array<10x!fir.char<1,5>> {{{.*}}, uniq_name = "{{.*}}Ebeta_array"} - -!FIRDialect-DAG: omp.parallel { -!FIRDialect-DAG: %[[ALPHA_PRIVATE:.*]] = fir.alloca i32 {{{.*}}, pinned, uniq_name = "{{.*}}Ealpha"} -!FIRDialect-DAG: %[[ALPHA_ARRAY_PRIVATE:.*]] = fir.alloca !fir.array<10xi32> {{{.*}}, pinned, uniq_name = "{{.*}}Ealpha_array"} -!FIRDialect-DAG: %[[BETA_PRIVATE:.*]] = fir.alloca !fir.char<1,5> {{{.*}}, pinned, uniq_name = "{{.*}}Ebeta"} -!FIRDialect-DAG: %[[BETA_ARRAY_PRIVATE:.*]] = fir.alloca !fir.array<10x!fir.char<1,5>> {{{.*}}, pinned, uniq_name = "{{.*}}Ebeta_array"} -!FIRDialect-DAG: %[[ARG1_PRIVATE:.*]] = fir.alloca i32 {{{.*}}, pinned, uniq_name = "{{.*}}Earg1"} -!FIRDialect-DAG: %[[ARG2_ARRAY_PRIVATE:.*]] = fir.alloca !fir.array<10xi32> {{{.*}}, pinned, uniq_name = "{{.*}}Earg2"} -!FIRDialect-DAG: %[[ARG3_PRIVATE:.*]] = fir.alloca !fir.char<1,5> {{{.*}}, pinned, uniq_name = "{{.*}}Earg3"} -!FIRDialect-DAG: %[[ARG4_ARRAY_PRIVATE:.*]] = fir.alloca !fir.array<10x!fir.char<1,5>> {{{.*}}, pinned, uniq_name = "{{.*}}Earg4"} -!FIRDialect: omp.terminator -!FIRDialect: } - -subroutine private_clause(arg1, arg2, arg3, arg4) - - integer :: arg1, arg2(10) - integer :: alpha, alpha_array(10) - character(5) :: arg3, arg4(10) - character(5) :: beta, beta_array(10) - -!$OMP PARALLEL PRIVATE(alpha, alpha_array, beta, beta_array, arg1, arg2, arg3, arg4) - alpha = 1 - alpha_array = 4 - beta = "hi" - beta_array = "hi" - arg1 = 2 - arg2 = 3 - arg3 = "world" - arg4 = "world" -!$OMP END PARALLEL - -end subroutine - -!FIRDialect: func @_QPprivate_clause_scalar() { -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.complex<4> {bindc_name = "c", uniq_name = "{{.*}}Ec"} -!FIRDialect-DAG: {{.*}} = fir.alloca i8 {bindc_name = "i1", uniq_name = "{{.*}}Ei1"} -!FIRDialect-DAG: {{.*}} = fir.alloca i128 {bindc_name = "i16", uniq_name = "{{.*}}Ei16"} -!FIRDialect-DAG: {{.*}} = fir.alloca i16 {bindc_name = "i2", uniq_name = "{{.*}}Ei2"} -!FIRDialect-DAG: {{.*}} = fir.alloca i32 {bindc_name = "i4", uniq_name = "{{.*}}Ei4"} -!FIRDialect-DAG: {{.*}} = fir.alloca i64 {bindc_name = "i8", uniq_name = "{{.*}}Ei8"} -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.logical<4> {bindc_name = "l", uniq_name = "{{.*}}El"} -!FIRDialect-DAG: {{.*}} = fir.alloca f32 {bindc_name = "r", uniq_name = "{{.*}}Er"} - -!FIRDialect: omp.parallel { -!FIRDialect-DAG: {{.*}} = fir.alloca i8 {bindc_name = "i1", pinned, uniq_name = "{{.*}}Ei1"} -!FIRDialect-DAG: {{.*}} = fir.alloca i16 {bindc_name = "i2", pinned, uniq_name = "{{.*}}Ei2"} -!FIRDialect-DAG: {{.*}} = fir.alloca i32 {bindc_name = "i4", pinned, uniq_name = "{{.*}}Ei4"} -!FIRDialect-DAG: {{.*}} = fir.alloca i64 {bindc_name = "i8", pinned, uniq_name = "{{.*}}Ei8"} -!FIRDialect-DAG: {{.*}} = fir.alloca i128 {bindc_name = "i16", pinned, uniq_name = "{{.*}}Ei16"} -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.complex<4> {bindc_name = "c", pinned, uniq_name = "{{.*}}Ec"} -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.logical<4> {bindc_name = "l", pinned, uniq_name = "{{.*}}El"} -!FIRDialect-DAG: {{.*}} = fir.alloca f32 {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - -subroutine private_clause_scalar() - - integer(kind=1) :: i1 - integer(kind=2) :: i2 - integer(kind=4) :: i4 - integer(kind=8) :: i8 - integer(kind=16) :: i16 - complex :: c - logical :: l - real :: r - -!$OMP PARALLEL PRIVATE(i1, i2, i4, i8, i16, c, l, r) - print *, i1, i2, i4, i8, i16, c, l, r -!$OMP END PARALLEL - -end subroutine - -!FIRDialect: func @_QPprivate_clause_derived_type() { -!FIRDialect: {{.*}} = fir.alloca !fir.type<{{.*}}{t_i:i32,t_arr:!fir.array<5xi32>}> {bindc_name = "t", uniq_name = "{{.*}}Et"} - -!FIRDialect: omp.parallel { -!FIRDialect: {{.*}} = fir.alloca !fir.type<{{.*}}{t_i:i32,t_arr:!fir.array<5xi32>}> {bindc_name = "t", pinned, uniq_name = "{{.*}}Et"} - -subroutine private_clause_derived_type() - - type my_type - integer :: t_i - integer :: t_arr(5) - end type my_type - type(my_type) :: t - -!$OMP PARALLEL PRIVATE(t) - print *, t%t_i -!$OMP END PARALLEL - -end subroutine - -!FIRDialect: func @_QPprivate_clause_allocatable() { -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.box> {bindc_name = "x", uniq_name = "{{.*}}Ex"} -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.heap {uniq_name = "{{.*}}Ex.addr"} -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.box>> {bindc_name = "x2", uniq_name = "{{.*}}Ex2"} -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.heap> {uniq_name = "{{.*}}Ex2.addr"} -!FIRDialect-DAG: {{.*}} = fir.address_of(@{{.*}}Ex3) : !fir.ref>> -!FIRDialect-DAG: [[TMP8:%.*]] = fir.address_of(@{{.*}}Ex4) : !fir.ref>>> - -!FIRDialect: omp.parallel { -!FIRDialect-DAG: [[TMP35:%.*]] = fir.alloca !fir.box> {bindc_name = "x", pinned, uniq_name = "{{.*}}Ex"} -!FIRDialect-DAG: [[TMP39:%.*]] = fir.alloca !fir.box>> {bindc_name = "x2", pinned, uniq_name = "{{.*}}Ex2"} -!FIRDialect-DAG: [[TMP45:%.*]] = fir.alloca !fir.box> {bindc_name = "x3", pinned, uniq_name = "{{.*}}Ex3"} - -!FIRDialect-DAG: [[TMP51:%.*]] = fir.load [[TMP8]] : !fir.ref>>> -!FIRDialect-DAG: [[TMP97:%.*]] = fir.load [[TMP8]] : !fir.ref>>> -!FIRDialect-DAG: [[TMP98:%.*]]:3 = fir.box_dims [[TMP97]], {{.*}} : (!fir.box>>, index) -> (index, index, index) -!FIRDialect-DAG: [[TMP50:%.*]] = fir.alloca !fir.box>> {bindc_name = "x4", pinned, uniq_name = "{{.*}}Ex4"} - -! FIRDialect-DAG: [[TMP101:%.*]] = fir.allocmem !fir.array, {{.*}} {fir.must_be_heap = true, uniq_name = "{{.*}}Ex4.alloc"} -! FIRDialect-DAG: [[TMP102:%.*]] = fir.shape_shift {{.*}}#0, {{.*}} : (index, index) -> !fir.shapeshift<1> -! FIRDialect-DAG: [[TMP103:%.*]] = fir.embox [[TMP101]]([[TMP102]]) : (!fir.heap>, !fir.shapeshift<1>) -> !fir.box>> -! FIRDialect-DAG: fir.store [[TMP103]] to [[TMP50]] : !fir.ref>>> - - -subroutine private_clause_allocatable() - - integer, allocatable :: x, x2(:) - integer, allocatable, save :: x3, x4(:) - - print *, x, x2, x3, x4 - -!$OMP PARALLEL PRIVATE(x, x2, x3, x4) - print *, x, x2, x3, x4 -!$OMP END PARALLEL - -end subroutine - - -!FIRDialect: func @_QPprivate_clause_real_call_allocatable() { -!FIRDialect-DAG: {{.*}} = fir.alloca !fir.box> {bindc_name = "x5", uniq_name = "{{.*}}Ex5"} -!FIRDialect-DAG: {{.*}} = fir.zero_bits !fir.heap -!FIRDialect-DAG: {{.*}} = fir.embox %1 : (!fir.heap) -> !fir.box> -!FIRDialect-DAG: fir.store %2 to %0 : !fir.ref>> -!FIRDialect-DAG: omp.parallel { -!FIRDialect-DAG: [[TMP203:%.*]] = fir.alloca !fir.box> {bindc_name = "x5", pinned, uniq_name = "{{.*}}Ex5"} - -!FIRDialect-DAG: fir.if %{{.*}} { - -!FIRDialect-DAG: fir.store %{{.*}} to [[TMP203]] : !fir.ref>> -!FIRDialect-DAG: } else { - -!FIRDialect-DAG: fir.store %{{.*}} to [[TMP203]] : !fir.ref>> -!FIRDialect-DAG: } -!FIRDialect-DAG: fir.call @_QFprivate_clause_real_call_allocatablePhelper_private_clause_real_call_allocatable([[TMP203]]) fastmath : (!fir.ref>>) -> () -!FIRDialect-DAG: %{{.*}} = fir.load [[TMP203]] : !fir.ref>> - -!FIRDialect-DAG: fir.if %{{.*}} { -!FIRDialect-DAG: %{{.*}} = fir.load [[TMP203]] : !fir.ref>> - -!FIRDialect-DAG: fir.store %{{.*}} to [[TMP203]] : !fir.ref>> -!FIRDialect-DAG: } -!FIRDialect-DAG: omp.terminator -!FIRDialect-DAG: } -!FIRDialect-DAG: return -!FIRDialect-DAG: } - - -subroutine private_clause_real_call_allocatable - real, allocatable :: x5 - !$omp parallel private(x5) - call helper_private_clause_real_call_allocatable(x5) - !$omp end parallel - contains - subroutine helper_private_clause_real_call_allocatable(x6) - real, allocatable :: x6 - print *, allocated(x6) - end subroutine -end subroutine - -!FIRDialect: func.func @_QPincrement_list_items(%arg0: !fir.ref>>}>>>> {fir.bindc_name = "head"}) { -!FIRDialect: {{%.*}} = fir.alloca !fir.box>>}>>> {bindc_name = "p", uniq_name = "_QFincrement_list_itemsEp"} -!FIRDialect: omp.parallel { -!FIRDialect: {{%.*}} = fir.alloca !fir.box>>}>>> {bindc_name = "p", pinned, uniq_name = "_QFincrement_list_itemsEp"} -!FIRDialect: omp.single { - -!FIRDialect: omp.terminator -!FIRDialect: omp.terminator -!FIRDialect: return - -subroutine increment_list_items (head) - type node - integer :: payload - type (node), pointer :: next - end type node - - type (node), pointer :: head - type (node), pointer :: p -!$omp parallel private(p) -!$omp single - p => head - do - p => p%next - if ( associated (p) .eqv. .false. ) exit - end do -!$omp end single -!$omp end parallel -end subroutine increment_list_items - -!FIRDialect: func.func @_QPparallel_pointer() { -!FIRDialect-DAG: [[PP0:%.*]] = fir.alloca !fir.box> {bindc_name = "y1", uniq_name = "{{.*}}Ey1"} -!FIRDialect-DAG: [[PP1:%.*]] = fir.alloca !fir.ptr {uniq_name = "{{.*}}Ey1.addr"} -!FIRDialect-DAG: [[PP2:%.*]] = fir.zero_bits !fir.ptr -!FIRDialect: fir.store [[PP2]] to [[PP1]] : !fir.ref> -!FIRDialect-DAG: [[PP3:%.*]] = fir.alloca !fir.box>> {bindc_name = "y2", uniq_name = "{{.*}}Ey2"} - -!FIRDialect: fir.store %6 to %3 : !fir.ref>>> -!FIRDialect-DAG: [[PP7:%.*]] = fir.alloca i32 {bindc_name = "z1", fir.target, uniq_name = "{{.*}}Ez1"} - -!FIRDialect-DAG: [[PP8:%.*]] = fir.alloca !fir.array<10xi32> {bindc_name = "z2", fir.target, uniq_name = "{{.*}}Ez2"} -!FIRDialect: omp.parallel { -!FIRDialect-DAG: [[PP9:%.*]] = fir.alloca !fir.box> {bindc_name = "y1", pinned, uniq_name = "{{.*}}Ey1"} -!FIRDialect-DAG: [[PP10:%.*]] = fir.alloca !fir.box>> {bindc_name = "y2", pinned, uniq_name = "{{.*}}Ey2"} -!FIRDialect-DAG: [[PP11:%.*]] = fir.embox [[PP7]] : (!fir.ref) -> !fir.box> -!FIRDialect: fir.store [[PP11]] to [[PP9]] : !fir.ref>> -!FIRDialect-DAG: [[PP12:%.*]] = fir.shape %c{{.*}} : (index) -> !fir.shape<1> -!FIRDialect-DAG: [[PP13:%.*]] = fir.embox [[PP8]]([[PP12]]) : (!fir.ref>, !fir.shape<1>) -> !fir.box>> -!FIRDialect: fir.store %13 to [[PP10]] : !fir.ref>>> -!FIRDialect: omp.terminator -!FIRDialect: } -!FIRDialect: return -!FIRDialect: } - -subroutine parallel_pointer() - integer, pointer :: y1, y2(:) - integer, target :: z1, z2(10) - -!$omp parallel private(y1, y2) - y1=>z1 - y2=>z2 -!$omp end parallel -end subroutine parallel_pointer - - -!FIRDialect-LABEL: func @_QPsimple_loop_1() -subroutine simple_loop_1 - integer :: i - real, allocatable :: r; - ! FIRDialect: omp.parallel - !$OMP PARALLEL PRIVATE(r) - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - - ! FIRDialect: omp.wsloop { - ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP DO - do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! FIRDialect: omp.yield - ! FIRDialect: omp.terminator - ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - !$OMP END DO - ! FIRDialect: omp.terminator - !$OMP END PARALLEL -end subroutine - -!FIRDialect-LABEL: func @_QPsimple_loop_2() -subroutine simple_loop_2 - integer :: i - real, allocatable :: r; - ! FIRDialect: omp.parallel - !$OMP PARALLEL - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - - ! FIRDialect: omp.wsloop { - ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP DO PRIVATE(r) - do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! FIRDialect: omp.yield - ! FIRDialect: omp.terminator - ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - !$OMP END DO - ! FIRDialect: omp.terminator - !$OMP END PARALLEL -end subroutine - -!FIRDialect-LABEL: func @_QPsimple_loop_3() -subroutine simple_loop_3 - integer :: i - real, allocatable :: r; - ! FIRDialect: omp.parallel - ! FIRDialect: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - - ! FIRDialect: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[WS_STEP:.*]] = arith.constant 1 : i32 - - ! FIRDialect: omp.wsloop { - ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP PARALLEL DO PRIVATE(r) - do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! FIRDialect: omp.yield - ! FIRDialect: omp.terminator - ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - !$OMP END PARALLEL DO - ! FIRDialect: omp.terminator -end subroutine - -!CHECK-LABEL: func @_QPsimd_loop_1() -subroutine simd_loop_1 - integer :: i - real, allocatable :: r; - ! FIRDialect: [[R:%.*]] = fir.alloca !fir.box> {bindc_name = "r", pinned, uniq_name = "{{.*}}Er"} - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> - - ! FIRDialect: %[[LB:.*]] = arith.constant 1 : i32 - ! FIRDialect: %[[UB:.*]] = arith.constant 9 : i32 - ! FIRDialect: %[[STEP:.*]] = arith.constant 1 : i32 - - ! FIRDialect: omp.simd { - ! FIRDialect-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - !$OMP SIMD PRIVATE(r) - do i=1, 9 - ! FIRDialect: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! FIRDialect: %[[LOAD_IV:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! FIRDialect: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD - ! FIRDialect: omp.yield - ! FIRDialect: {{%.*}} = fir.load [[R]] : !fir.ref>> - ! FIRDialect: fir.if {{%.*}} { - ! FIRDialect: [[LD:%.*]] = fir.load [[R]] : !fir.ref>> - ! FIRDialect: [[AD:%.*]] = fir.box_addr [[LD]] : (!fir.box>) -> !fir.heap - ! FIRDialect: fir.freemem [[AD]] : !fir.heap - ! FIRDialect: fir.store {{%.*}} to [[R]] : !fir.ref>> -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/parallel-reduction-add-byref.f90 b/flang/test/Lower/OpenMP/FIR/parallel-reduction-add-byref.f90 deleted file mode 100644 index ea45e716ceae..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-reduction-add-byref.f90 +++ /dev/null @@ -1,117 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction -o - %s 2>&1 | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir --force-byref-reduction -o - %s 2>&1 | FileCheck %s - -!CHECK-LABEL: omp.declare_reduction -!CHECK-SAME: @[[RED_F32_NAME:.*]] : !fir.ref -!CHECK-SAME: init { -!CHECK: ^bb0(%{{.*}}: !fir.ref): -!CHECK: %[[C0_1:.*]] = arith.constant 0.000000e+00 : f32 -!CHECK: %[[REF:.*]] = fir.alloca f32 -!CHECKL fir.store [[%C0_1]] to %[[REF]] : !fir.ref -!CHECK: omp.yield(%[[REF]] : !fir.ref) -!CHECK: } combiner { -!CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -!CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -!CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK: %[[RES:.*]] = arith.addf %[[LD0]], %[[LD1]] {{.*}}: f32 -!CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -!CHECK: omp.yield(%[[ARG0]] : !fir.ref) -!CHECK: } - -!CHECK-LABEL: omp.declare_reduction -!CHECK-SAME: @[[RED_I32_NAME:.*]] : !fir.ref -!CHECK-SAME: init { -!CHECK: ^bb0(%{{.*}}: !fir.ref): -!CHECK: %[[C0_1:.*]] = arith.constant 0 : i32 -!CHECK: %[[REF:.*]] = fir.alloca i32 -!CHECKL fir.store [[%C0_1]] to %[[REF]] : !fir.ref -!CHECK: omp.yield(%[[REF]] : !fir.ref) -!CHECK: } combiner { -!CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -!CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -!CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK: %[[RES:.*]] = arith.addi %[[LD0]], %[[LD1]] : i32 -!CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -!CHECK: omp.yield(%[[ARG0]] : !fir.ref) -!CHECK: } - -!CHECK-LABEL: func.func @_QPsimple_int_add -!CHECK: %[[IREF:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_int_addEi"} -!CHECK: %[[I_START:.*]] = arith.constant 0 : i32 -!CHECK: fir.store %[[I_START]] to %[[IREF]] : !fir.ref -!CHECK: omp.parallel byref reduction(@[[RED_I32_NAME]] %[[IREF]] -> %[[PRV:.+]] : !fir.ref) { -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[I_INCR:.+]] = arith.constant 1 : i32 -!CHECK: %[[RES:.+]] = arith.addi %[[LPRV]], %[[I_INCR]] -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -subroutine simple_int_add - integer :: i - i = 0 - - !$omp parallel reduction(+:i) - i = i + 1 - !$omp end parallel - - print *, i -end subroutine - -!CHECK-LABEL: func.func @_QPsimple_real_add -!CHECK: %[[RREF:.*]] = fir.alloca f32 {bindc_name = "r", uniq_name = "_QFsimple_real_addEr"} -!CHECK: %[[R_START:.*]] = arith.constant 0.000000e+00 : f32 -!CHECK: fir.store %[[R_START]] to %[[RREF]] : !fir.ref -!CHECK: omp.parallel byref reduction(@[[RED_F32_NAME]] %[[RREF]] -> %[[PRV:.+]] : !fir.ref) { -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[R_INCR:.+]] = arith.constant 1.500000e+00 : f32 -!CHECK: %[[RES]] = arith.addf %[[LPRV]], %[[R_INCR]] {{.*}} : f32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -subroutine simple_real_add - real :: r - r = 0.0 - - !$omp parallel reduction(+:r) - r = r + 1.5 - !$omp end parallel - - print *, r -end subroutine - -!CHECK-LABEL: func.func @_QPint_real_add -!CHECK: %[[IREF:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFint_real_addEi"} -!CHECK: %[[RREF:.*]] = fir.alloca f32 {bindc_name = "r", uniq_name = "_QFint_real_addEr"} -!CHECK: %[[R_START:.*]] = arith.constant 0.000000e+00 : f32 -!CHECK: fir.store %[[R_START]] to %[[RREF]] : !fir.ref -!CHECK: %[[I_START:.*]] = arith.constant 0 : i32 -!CHECK: fir.store %[[I_START]] to %[[IREF]] : !fir.ref -!CHECK: omp.parallel byref reduction(@[[RED_I32_NAME]] %[[IREF]] -> %[[PRV0:.+]] : !fir.ref, @[[RED_F32_NAME]] %[[RREF]] -> %[[PRV1:.+]] : !fir.ref) { -!CHECK: %[[R_INCR:.*]] = arith.constant 1.500000e+00 : f32 -!CHECK: %[[LPRV1:.+]] = fir.load %[[PRV1]] : !fir.ref -!CHECK: %[[RES1:.+]] = arith.addf %[[R_INCR]], %[[LPRV1]] {{.*}} : f32 -!CHECK: fir.store %[[RES1]] to %[[PRV1]] -!CHECK: %[[LPRV0:.+]] = fir.load %[[PRV0]] : !fir.ref -!CHECK: %[[I_INCR:.*]] = arith.constant 3 : i32 -!CHECK: %[[RES0:.+]] = arith.addi %[[LPRV0]], %[[I_INCR]] -!CHECK: fir.store %[[RES0]] to %[[PRV0]] -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -subroutine int_real_add - real :: r - integer :: i - - r = 0.0 - i = 0 - - !$omp parallel reduction(+:i,r) - r = 1.5 + r - i = i + 3 - !$omp end parallel - - print *, r - print *, i -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/parallel-reduction-add.f90 b/flang/test/Lower/OpenMP/FIR/parallel-reduction-add.f90 deleted file mode 100644 index 3f6d9e647c9b..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-reduction-add.f90 +++ /dev/null @@ -1,105 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp -o - %s 2>&1 | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s - -!CHECK-LABEL: omp.declare_reduction -!CHECK-SAME: @[[RED_F32_NAME:.*]] : f32 init { -!CHECK: ^bb0(%{{.*}}: f32): -!CHECK: %[[C0_1:.*]] = arith.constant 0.000000e+00 : f32 -!CHECK: omp.yield(%[[C0_1]] : f32) -!CHECK: } combiner { -!CHECK: ^bb0(%[[ARG0:.*]]: f32, %[[ARG1:.*]]: f32): -!CHECK: %[[RES:.*]] = arith.addf %[[ARG0]], %[[ARG1]] {{.*}}: f32 -!CHECK: omp.yield(%[[RES]] : f32) -!CHECK: } - -!CHECK-LABEL: omp.declare_reduction -!CHECK-SAME: @[[RED_I32_NAME:.*]] : i32 init { -!CHECK: ^bb0(%{{.*}}: i32): -!CHECK: %[[C0_1:.*]] = arith.constant 0 : i32 -!CHECK: omp.yield(%[[C0_1]] : i32) -!CHECK: } combiner { -!CHECK: ^bb0(%[[ARG0:.*]]: i32, %[[ARG1:.*]]: i32): -!CHECK: %[[RES:.*]] = arith.addi %[[ARG0]], %[[ARG1]] : i32 -!CHECK: omp.yield(%[[RES]] : i32) -!CHECK: } - -!CHECK-LABEL: func.func @_QPsimple_int_add -!CHECK: %[[IREF:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_int_addEi"} -!CHECK: %[[I_START:.*]] = arith.constant 0 : i32 -!CHECK: fir.store %[[I_START]] to %[[IREF]] : !fir.ref -!CHECK: omp.parallel reduction(@[[RED_I32_NAME]] %[[IREF]] -> %[[PRV:.+]] : !fir.ref) { -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[I_INCR:.+]] = arith.constant 1 : i32 -!CHECK: %[[RES:.+]] = arith.addi %[[LPRV]], %[[I_INCR]] -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -subroutine simple_int_add - integer :: i - i = 0 - - !$omp parallel reduction(+:i) - i = i + 1 - !$omp end parallel - - print *, i -end subroutine - -!CHECK-LABEL: func.func @_QPsimple_real_add -!CHECK: %[[RREF:.*]] = fir.alloca f32 {bindc_name = "r", uniq_name = "_QFsimple_real_addEr"} -!CHECK: %[[R_START:.*]] = arith.constant 0.000000e+00 : f32 -!CHECK: fir.store %[[R_START]] to %[[RREF]] : !fir.ref -!CHECK: omp.parallel reduction(@[[RED_F32_NAME]] %[[RREF]] -> %[[PRV:.+]] : !fir.ref) { -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[R_INCR:.+]] = arith.constant 1.500000e+00 : f32 -!CHECK: %[[RES]] = arith.addf %[[LPRV]], %[[R_INCR]] {{.*}} : f32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -subroutine simple_real_add - real :: r - r = 0.0 - - !$omp parallel reduction(+:r) - r = r + 1.5 - !$omp end parallel - - print *, r -end subroutine - -!CHECK-LABEL: func.func @_QPint_real_add -!CHECK: %[[IREF:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFint_real_addEi"} -!CHECK: %[[RREF:.*]] = fir.alloca f32 {bindc_name = "r", uniq_name = "_QFint_real_addEr"} -!CHECK: %[[R_START:.*]] = arith.constant 0.000000e+00 : f32 -!CHECK: fir.store %[[R_START]] to %[[RREF]] : !fir.ref -!CHECK: %[[I_START:.*]] = arith.constant 0 : i32 -!CHECK: fir.store %[[I_START]] to %[[IREF]] : !fir.ref -!CHECK: omp.parallel reduction(@[[RED_I32_NAME]] %[[IREF]] -> %[[PRV0:.+]] : !fir.ref, @[[RED_F32_NAME]] %[[RREF]] -> %[[PRV1:.+]] : !fir.ref) { -!CHECK: %[[R_INCR:.*]] = arith.constant 1.500000e+00 : f32 -!CHECK: %[[LPRV1:.+]] = fir.load %[[PRV1]] : !fir.ref -!CHECK: %[[RES1:.+]] = arith.addf %[[R_INCR]], %[[LPRV1]] {{.*}} : f32 -!CHECK: fir.store %[[RES1]] to %[[PRV1]] -!CHECK: %[[LPRV0:.+]] = fir.load %[[PRV0]] : !fir.ref -!CHECK: %[[I_INCR:.*]] = arith.constant 3 : i32 -!CHECK: %[[RES0:.+]] = arith.addi %[[LPRV0]], %[[I_INCR]] -!CHECK: fir.store %[[RES0]] to %[[PRV0]] -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -subroutine int_real_add - real :: r - integer :: i - - r = 0.0 - i = 0 - - !$omp parallel reduction(+:i,r) - r = 1.5 + r - i = i + 3 - !$omp end parallel - - print *, r - print *, i -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/parallel-sections.f90 b/flang/test/Lower/OpenMP/FIR/parallel-sections.f90 deleted file mode 100644 index 7730ab87a719..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-sections.f90 +++ /dev/null @@ -1,65 +0,0 @@ -! REQUIRES: openmp_runtime - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --cfg-conversion | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect,LLVMDialect" - -!=============================================================================== -! Parallel sections construct -!=============================================================================== - -!FIRDialect: func @_QPomp_parallel_sections -subroutine omp_parallel_sections(x, y) - integer, intent(inout) :: x, y - !OMPDialect: omp.parallel { - !OMPDialect: omp.sections { - !$omp parallel sections - !OMPDialect: omp.section { - !$omp section - !FIRDialect: fir.load - !FIRDialect: arith.addi - !FIRDialect: fir.store - x = x + 12 - !OMPDialect: omp.terminator - !OMPDialect: omp.section { - !$omp section - !FIRDialect: fir.load - !FIRDialect: arith.subi - !FIRDialect: fir.store - y = y - 5 - !OMPDialect: omp.terminator - !OMPDialect: omp.terminator - !OMPDialect: omp.terminator - !$omp end parallel sections -end subroutine omp_parallel_sections - -!=============================================================================== -! Parallel sections construct with allocate clause -!=============================================================================== - -!FIRDialect: func @_QPomp_parallel_sections -subroutine omp_parallel_sections_allocate(x, y) - use omp_lib - integer, intent(inout) :: x, y - !FIRDialect: %[[allocator_1:.*]] = arith.constant 4 : i64 - !FIRDialect: %[[allocator_2:.*]] = arith.constant 4 : i64 - !LLVMDialect: %[[allocator_1:.*]] = llvm.mlir.constant(4 : i64) : i64 - !LLVMDialect: %[[allocator_2:.*]] = llvm.mlir.constant(4 : i64) : i64 - !OMPDialect: omp.parallel allocate( - !FIRDialect: %[[allocator_2]] : i64 -> %{{.*}} : !fir.ref) { - !LLVMDialect: %[[allocator_2]] : i64 -> %{{.*}} : !llvm.ptr) { - !OMPDialect: omp.sections allocate( - !FIRDialect: %[[allocator_1]] : i64 -> %{{.*}} : !fir.ref) { - !LLVMDialect: %[[allocator_1]] : i64 -> %{{.*}} : !llvm.ptr) { - !$omp parallel sections allocate(omp_high_bw_mem_alloc: x) - !OMPDialect: omp.section { - !$omp section - x = x + 12 - !OMPDialect: omp.terminator - !OMPDialect: omp.section { - !$omp section - y = y + 5 - !OMPDialect: omp.terminator - !OMPDialect: omp.terminator - !OMPDialect: omp.terminator - !$omp end parallel sections -end subroutine omp_parallel_sections_allocate diff --git a/flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 b/flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 deleted file mode 100644 index 490f6d0cf7bc..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-wsloop-firstpriv.f90 +++ /dev/null @@ -1,69 +0,0 @@ -! This test checks lowering of OpenMP parallel DO, with the loop bound being -! a firstprivate variable - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -! CHECK: func @_QPomp_do_firstprivate(%[[ARG0:.*]]: !fir.ref {fir.bindc_name = "a"}) -subroutine omp_do_firstprivate(a) - integer::a - integer::n - n = a+1 - !$omp parallel do firstprivate(a) - ! CHECK: omp.parallel { - ! CHECK-NEXT: %[[REF:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} - ! CHECK-NEXT: %[[CLONE:.*]] = fir.alloca i32 {bindc_name = "a", pinned - ! CHECK-NEXT: %[[LD:.*]] = fir.load %[[ARG0]] : !fir.ref - ! CHECK-NEXT: fir.store %[[LD]] to %[[CLONE]] : !fir.ref - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: %[[UB:.*]] = fir.load %[[CLONE]] : !fir.ref - ! CHECK-NEXT: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: omp.wsloop { - ! CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - ! CHECK-NEXT: fir.store %[[ARG1]] to %[[REF]] : !fir.ref - ! CHECK-NEXT: fir.call @_QPfoo(%[[REF]], %[[CLONE]]) {{.*}}: (!fir.ref, !fir.ref) -> () - ! CHECK-NEXT: omp.yield - ! CHECK-NEXT: } - ! CHECK-NEXT: omp.terminator - ! CHECK-NEXT: } - do i=1, a - call foo(i, a) - end do - !$omp end parallel do - !CHECK: fir.call @_QPbar(%[[ARG0]]) {{.*}}: (!fir.ref) -> () - call bar(a) -end subroutine omp_do_firstprivate - -! CHECK: func @_QPomp_do_firstprivate2(%[[ARG0:.*]]: !fir.ref {fir.bindc_name = "a"}, %[[ARG1:.*]]: !fir.ref {fir.bindc_name = "n"}) -subroutine omp_do_firstprivate2(a, n) - integer::a - integer::n - n = a+1 - !$omp parallel do firstprivate(a, n) - ! CHECK: omp.parallel { - ! CHECK-NEXT: %[[REF:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} - ! CHECK-NEXT: %[[CLONE:.*]] = fir.alloca i32 {bindc_name = "a", pinned - ! CHECK-NEXT: %[[LD:.*]] = fir.load %[[ARG0]] : !fir.ref - ! CHECK-NEXT: fir.store %[[LD]] to %[[CLONE]] : !fir.ref - ! CHECK-NEXT: %[[CLONE1:.*]] = fir.alloca i32 {bindc_name = "n", pinned - ! CHECK-NEXT: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref - ! CHECK-NEXT: fir.store %[[LD1]] to %[[CLONE1]] : !fir.ref - - - ! CHECK: %[[LB:.*]] = fir.load %[[CLONE]] : !fir.ref - ! CHECK-NEXT: %[[UB:.*]] = fir.load %[[CLONE1]] : !fir.ref - ! CHECK-NEXT: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: omp.wsloop { - ! CHECK-NEXT: omp.loop_nest (%[[ARG2:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - ! CHECK-NEXT: fir.store %[[ARG2]] to %[[REF]] : !fir.ref - ! CHECK-NEXT: fir.call @_QPfoo(%[[REF]], %[[CLONE]]) {{.*}}: (!fir.ref, !fir.ref) -> () - ! CHECK-NEXT: omp.yield - ! CHECK-NEXT: } - ! CHECK-NEXT: omp.terminator - ! CHECK-NEXT: } - do i= a, n - call foo(i, a) - end do - !$omp end parallel do - !CHECK: fir.call @_QPbar(%[[ARG1]]) {{.*}}: (!fir.ref) -> () - call bar(n) -end subroutine omp_do_firstprivate2 diff --git a/flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 b/flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 deleted file mode 100644 index 630d647bc64b..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel-wsloop.f90 +++ /dev/null @@ -1,297 +0,0 @@ -! This test checks lowering of OpenMP DO Directive (Worksharing). - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -! CHECK-LABEL: func @_QPsimple_parallel_do() -subroutine simple_parallel_do - integer :: i - ! CHECK: omp.parallel - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP PARALLEL DO - do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! CHECK: omp.yield - ! CHECK: omp.terminator - ! CHECK: omp.terminator - !$OMP END PARALLEL DO -end subroutine - -! CHECK-LABEL: func @_QPparallel_do_with_parallel_clauses -! CHECK-SAME: %[[COND_REF:.*]]: !fir.ref> {fir.bindc_name = "cond"}, %[[NT_REF:.*]]: !fir.ref {fir.bindc_name = "nt"} -subroutine parallel_do_with_parallel_clauses(cond, nt) - logical :: cond - integer :: nt - integer :: i - ! CHECK: %[[COND:.*]] = fir.load %[[COND_REF]] : !fir.ref> - ! CHECK: %[[COND_CVT:.*]] = fir.convert %[[COND]] : (!fir.logical<4>) -> i1 - ! CHECK: %[[NT:.*]] = fir.load %[[NT_REF]] : !fir.ref - ! CHECK: omp.parallel if(%[[COND_CVT]] : i1) num_threads(%[[NT]] : i32) proc_bind(close) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP PARALLEL DO IF(cond) NUM_THREADS(nt) PROC_BIND(close) - do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! CHECK: omp.yield - ! CHECK: omp.terminator - ! CHECK: omp.terminator - !$OMP END PARALLEL DO -end subroutine - -! CHECK-LABEL: func @_QPparallel_do_with_clauses -! CHECK-SAME: %[[NT_REF:.*]]: !fir.ref {fir.bindc_name = "nt"} -subroutine parallel_do_with_clauses(nt) - integer :: nt - integer :: i - ! CHECK: %[[NT:.*]] = fir.load %[[NT_REF]] : !fir.ref - ! CHECK: omp.parallel num_threads(%[[NT]] : i32) - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop schedule(dynamic) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) - !$OMP PARALLEL DO NUM_THREADS(nt) SCHEDULE(dynamic) - do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! CHECK: omp.yield - ! CHECK: omp.terminator - ! CHECK: omp.terminator - !$OMP END PARALLEL DO -end subroutine - -!=============================================================================== -! Checking for the following construct: -! !$omp parallel do private(...) firstprivate(...) -!=============================================================================== - -! CHECK-LABEL: func @_QPparallel_do_with_privatisation_clauses -! CHECK-SAME: %[[COND_REF:.*]]: !fir.ref> {fir.bindc_name = "cond"}, %[[NT_REF:.*]]: !fir.ref {fir.bindc_name = "nt"} -subroutine parallel_do_with_privatisation_clauses(cond,nt) - logical :: cond - integer :: nt - integer :: i - ! CHECK: omp.parallel - ! CHECK: %[[PRIVATE_COND_REF:.*]] = fir.alloca !fir.logical<4> {bindc_name = "cond", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEcond"} - ! CHECK: %[[PRIVATE_NT_REF:.*]] = fir.alloca i32 {bindc_name = "nt", pinned, uniq_name = "_QFparallel_do_with_privatisation_clausesEnt"} - ! CHECK: %[[NT_VAL:.*]] = fir.load %[[NT_REF]] : !fir.ref - ! CHECK: fir.store %[[NT_VAL]] to %[[PRIVATE_NT_REF]] : !fir.ref - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP PARALLEL DO PRIVATE(cond) FIRSTPRIVATE(nt) - do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[IV_ADDR:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[IV_ADDR]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - ! CHECK: %[[PRIVATE_COND_VAL:.*]] = fir.load %[[PRIVATE_COND_REF]] : !fir.ref> - ! CHECK: %[[PRIVATE_COND_VAL_CVT:.*]] = fir.convert %[[PRIVATE_COND_VAL]] : (!fir.logical<4>) -> i1 - ! CHECK: fir.call @_FortranAioOutputLogical({{.*}}, %[[PRIVATE_COND_VAL_CVT]]) {{.*}}: (!fir.ref, i1) -> i1 - ! CHECK: %[[PRIVATE_NT_VAL:.*]] = fir.load %[[PRIVATE_NT_REF]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[PRIVATE_NT_VAL]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i, cond, nt - end do - ! CHECK: omp.yield - ! CHECK: omp.terminator - ! CHECK: omp.terminator - !$OMP END PARALLEL DO -end subroutine - -!=============================================================================== -! Checking for the following construct -! !$omp parallel private(...) firstprivate(...) -! !$omp do -!=============================================================================== - -subroutine parallel_private_do(cond,nt) -logical :: cond - integer :: nt - integer :: i - !$OMP PARALLEL PRIVATE(cond) FIRSTPRIVATE(nt) - !$OMP DO - do i=1, 9 - call foo(i, cond, nt) - end do - !$OMP END DO - !$OMP END PARALLEL -end subroutine parallel_private_do - -! CHECK-LABEL: func.func @_QPparallel_private_do( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "cond"}, -! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "nt"}) { -! CHECK: %[[I:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFparallel_private_doEi"} -! CHECK: omp.parallel { -! CHECK: %[[I_PRIV:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[COND_ADDR:.*]] = fir.alloca !fir.logical<4> {bindc_name = "cond", pinned, uniq_name = "_QFparallel_private_doEcond"} -! CHECK: %[[NT_ADDR:.*]] = fir.alloca i32 {bindc_name = "nt", pinned, uniq_name = "_QFparallel_private_doEnt"} -! CHECK: %[[NT:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: fir.store %[[NT]] to %[[NT_ADDR]] : !fir.ref -! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 9 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV]] : !fir.ref -! CHECK: fir.call @_QPfoo(%[[I_PRIV]], %[[COND_ADDR]], %[[NT_ADDR]]) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -!=============================================================================== -! Checking for the following construct -! !$omp parallel -! !$omp do firstprivate(...) firstprivate(...) -!=============================================================================== - -subroutine omp_parallel_multiple_firstprivate_do(a, b) - integer::a, b - !$OMP PARALLEL FIRSTPRIVATE(a) FIRSTPRIVATE(b) - !$OMP DO - do i=1, 10 - call bar(i, a) - end do - !$OMP END DO - !$OMP END PARALLEL -end subroutine omp_parallel_multiple_firstprivate_do - -! CHECK-LABEL: func.func @_QPomp_parallel_multiple_firstprivate_do( -! CHECK-SAME: %[[A_ADDR:.*]]: !fir.ref {fir.bindc_name = "a"}, -! CHECK-SAME: %[[B_ADDR:.*]]: !fir.ref {fir.bindc_name = "b"}) { -! CHECK: %[[I_ADDR:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFomp_parallel_multiple_firstprivate_doEi"} -! CHECK: omp.parallel { -! CHECK: %[[I_PRIV_ADDR:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[A_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "a", pinned, uniq_name = "_QFomp_parallel_multiple_firstprivate_doEa"} -! CHECK: %[[A:.*]] = fir.load %[[A_ADDR]] : !fir.ref -! CHECK: fir.store %[[A]] to %[[A_PRIV_ADDR]] : !fir.ref -! CHECK: %[[B_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "b", pinned, uniq_name = "_QFomp_parallel_multiple_firstprivate_doEb"} -! CHECK: %[[B:.*]] = fir.load %[[B_ADDR]] : !fir.ref -! CHECK: fir.store %[[B]] to %[[B_PRIV_ADDR]] : !fir.ref -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref -! CHECK: fir.call @_QPbar(%[[I_PRIV_ADDR]], %[[A_PRIV_ADDR]]) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -!=============================================================================== -! Checking for the following construct -! !$omp parallel -! !$omp do private(...) firstprivate(...) -!=============================================================================== - -subroutine parallel_do_private(cond,nt) -logical :: cond - integer :: nt - integer :: i - !$OMP PARALLEL - !$OMP DO PRIVATE(cond) FIRSTPRIVATE(nt) - do i=1, 9 - call foo(i, cond, nt) - end do - !$OMP END DO - !$OMP END PARALLEL -end subroutine parallel_do_private - -! CHECK-LABEL: func.func @_QPparallel_do_private( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref> {fir.bindc_name = "cond"}, -! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "nt"}) { -! CHECK: %[[I_ADDR:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFparallel_do_privateEi"} -! CHECK: omp.parallel { -! CHECK: %[[I_PRIV_ADDR:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[COND_ADDR:.*]] = fir.alloca !fir.logical<4> {bindc_name = "cond", pinned, uniq_name = "_QFparallel_do_privateEcond"} -! CHECK: %[[NT_ADDR:.*]] = fir.alloca i32 {bindc_name = "nt", pinned, uniq_name = "_QFparallel_do_privateEnt"} -! CHECK: %[[NT:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: fir.store %[[NT]] to %[[NT_ADDR]] : !fir.ref -! CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 9 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_8]]) inclusive step (%[[VAL_9]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref -! CHECK: fir.call @_QPfoo(%[[I_PRIV_ADDR]], %[[COND_ADDR]], %[[NT_ADDR]]) {{.*}}: (!fir.ref, !fir.ref>, !fir.ref) -> () -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -!=============================================================================== -! Checking for the following construct -! !$omp parallel -! !$omp do firstprivate(...) firstprivate(...) -!=============================================================================== - -subroutine omp_parallel_do_multiple_firstprivate(a, b) - integer::a, b - !$OMP PARALLEL - !$OMP DO FIRSTPRIVATE(a) FIRSTPRIVATE(b) - do i=1, 10 - call bar(i, a) - end do - !$OMP END DO - !$OMP END PARALLEL -end subroutine omp_parallel_do_multiple_firstprivate - -! CHECK-LABEL: func.func @_QPomp_parallel_do_multiple_firstprivate( -! CHECK-SAME: %[[A_ADDR:.*]]: !fir.ref {fir.bindc_name = "a"}, -! CHECK-SAME: %[[B_ADDR:.*]]: !fir.ref {fir.bindc_name = "b"}) { -! CHECK: %[[I_ADDR:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFomp_parallel_do_multiple_firstprivateEi"} -! CHECK: omp.parallel { -! CHECK: %[[I_PRIV_ADDR:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[A_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "a", pinned, uniq_name = "_QFomp_parallel_do_multiple_firstprivateEa"} -! CHECK: %[[A:.*]] = fir.load %[[A_ADDR]] : !fir.ref -! CHECK: fir.store %[[A]] to %[[A_PRIV_ADDR]] : !fir.ref -! CHECK: %[[B_PRIV_ADDR:.*]] = fir.alloca i32 {bindc_name = "b", pinned, uniq_name = "_QFomp_parallel_do_multiple_firstprivateEb"} -! CHECK: %[[B:.*]] = fir.load %[[B_ADDR]] : !fir.ref -! CHECK: fir.store %[[B]] to %[[B_PRIV_ADDR]] : !fir.ref -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[I]] to %[[I_PRIV_ADDR]] : !fir.ref -! CHECK: fir.call @_QPbar(%[[I_PRIV_ADDR]], %[[A_PRIV_ADDR]]) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } diff --git a/flang/test/Lower/OpenMP/FIR/parallel.f90 b/flang/test/Lower/OpenMP/FIR/parallel.f90 deleted file mode 100644 index a2ceb2d939f2..000000000000 --- a/flang/test/Lower/OpenMP/FIR/parallel.f90 +++ /dev/null @@ -1,211 +0,0 @@ -! REQUIRES: openmp_runtime - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="LLVMDialect,OMPDialect" - -!FIRDialect-LABEL: func @_QPparallel_simple -subroutine parallel_simple() - !OMPDialect: omp.parallel -!$omp parallel - !FIRDialect: fir.call - call f1() -!$omp end parallel -end subroutine parallel_simple - -!=============================================================================== -! `if` clause -!=============================================================================== - -!FIRDialect-LABEL: func @_QPparallel_if -subroutine parallel_if(alpha, beta, gamma) - integer, intent(in) :: alpha - logical, intent(in) :: beta - logical(1) :: logical1 - logical(2) :: logical2 - logical(4) :: logical4 - logical(8) :: logical8 - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(alpha .le. 0) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(.false.) - !FIRDialect: fir.call - call f2() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(alpha .ge. 0) - !FIRDialect: fir.call - call f3() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(.true.) - !FIRDialect: fir.call - call f4() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(beta) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(logical1) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(logical2) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(logical4) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if(%{{.*}} : i1) { - !$omp parallel if(logical8) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - -end subroutine parallel_if - -!=============================================================================== -! `num_threads` clause -!=============================================================================== - -!FIRDialect-LABEL: func @_QPparallel_numthreads -subroutine parallel_numthreads(num_threads) - integer, intent(inout) :: num_threads - - !OMPDialect: omp.parallel num_threads(%{{.*}}: i32) { - !$omp parallel num_threads(16) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - num_threads = 4 - - !OMPDialect: omp.parallel num_threads(%{{.*}} : i32) { - !$omp parallel num_threads(num_threads) - !FIRDialect: fir.call - call f2() - !OMPDialect: omp.terminator - !$omp end parallel - -end subroutine parallel_numthreads - -!=============================================================================== -! `proc_bind` clause -!=============================================================================== - -!FIRDialect-LABEL: func @_QPparallel_proc_bind -subroutine parallel_proc_bind() - - !OMPDialect: omp.parallel proc_bind(master) { - !$omp parallel proc_bind(master) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel proc_bind(close) { - !$omp parallel proc_bind(close) - !FIRDialect: fir.call - call f2() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel proc_bind(spread) { - !$omp parallel proc_bind(spread) - !FIRDialect: fir.call - call f3() - !OMPDialect: omp.terminator - !$omp end parallel - -end subroutine parallel_proc_bind - -!=============================================================================== -! `allocate` clause -!=============================================================================== - -!FIRDialect-LABEL: func @_QPparallel_allocate -subroutine parallel_allocate() - use omp_lib - integer :: x - !OMPDialect: omp.parallel allocate( - !FIRDialect: %{{.+}} : i64 -> %{{.+}} : !fir.ref - !LLVMDialect: %{{.+}} : i64 -> %{{.+}} : !llvm.ptr - !OMPDialect: ) { - !$omp parallel allocate(omp_high_bw_mem_alloc: x) private(x) - !FIRDialect: arith.addi - x = x + 12 - !OMPDialect: omp.terminator - !$omp end parallel -end subroutine parallel_allocate - -!=============================================================================== -! multiple clauses -!=============================================================================== - -!FIRDialect-LABEL: func @_QPparallel_multiple_clauses -subroutine parallel_multiple_clauses(alpha, num_threads) - use omp_lib - integer, intent(inout) :: alpha - integer, intent(in) :: num_threads - - !OMPDialect: omp.parallel if({{.*}} : i1) proc_bind(master) { - !$omp parallel if(alpha .le. 0) proc_bind(master) - !FIRDialect: fir.call - call f1() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel num_threads({{.*}} : i32) proc_bind(close) { - !$omp parallel proc_bind(close) num_threads(num_threads) - !FIRDialect: fir.call - call f2() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if({{.*}} : i1) num_threads({{.*}} : i32) { - !$omp parallel num_threads(num_threads) if(alpha .le. 0) - !FIRDialect: fir.call - call f3() - !OMPDialect: omp.terminator - !$omp end parallel - - !OMPDialect: omp.parallel if({{.*}} : i1) num_threads({{.*}} : i32) allocate( - !FIRDialect: %{{.+}} : i64 -> %{{.+}} : !fir.ref - !LLVMDialect: %{{.+}} : i64 -> %{{.+}} : !llvm.ptr - !OMPDialect: ) { - !$omp parallel num_threads(num_threads) if(alpha .le. 0) allocate(omp_high_bw_mem_alloc: alpha) private(alpha) - !FIRDialect: fir.call - call f3() - !FIRDialect: arith.addi - alpha = alpha + 12 - !OMPDialect: omp.terminator - !$omp end parallel - -end subroutine parallel_multiple_clauses diff --git a/flang/test/Lower/OpenMP/FIR/pre-fir-tree-loop.f90 b/flang/test/Lower/OpenMP/FIR/pre-fir-tree-loop.f90 deleted file mode 100644 index eca8fb304986..000000000000 --- a/flang/test/Lower/OpenMP/FIR/pre-fir-tree-loop.f90 +++ /dev/null @@ -1,70 +0,0 @@ -! RUN: bbc -fopenmp -pft-test -o %t %s | FileCheck %s -! RUN: %flang_fc1 -fopenmp -fdebug-dump-pft -o %t %s | FileCheck %s - -! Loop constructs always have an `end do` which can be the target of -! a branch. So OpenMP loop constructs do not need an artificial -! continue inserted for a target. - -!CHECK-LABEL: sb0 -!CHECK-NOT: continue -subroutine sb0(cond) - implicit none - logical :: cond - integer :: i - !$omp parallel do - do i = 1, 20 - if( cond) then - cycle - end if - end do - return -end subroutine - -!CHECK-LABEL: sb1 -!CHECK-NOT: continue -subroutine sb1(cond) - implicit none - logical :: cond - integer :: i - !$omp parallel do - do i = 1, 20 - if( cond) then - cycle - end if - end do - !$omp end parallel do - return -end subroutine - -!CHECK-LABEL: sb2 -!CHECK-NOT: continue -subroutine sb2 - integer :: i, n - integer :: tmp - - !$omp parallel do - do ifld=1,n - do isum=1,n - if (tmp > n) then - exit - endif - enddo - tmp = n - enddo -end subroutine - -!CHECK-LABEL: sb3 -!CHECK-NOT: continue -subroutine sb3 - integer :: i, n - integer :: tmp - - !$omp parallel do - do ifld=1,n - do isum=1,n - if (tmp > n) then - exit - endif - enddo - enddo -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/pre-fir-tree01.f90 b/flang/test/Lower/OpenMP/FIR/pre-fir-tree01.f90 deleted file mode 100644 index fc817942513e..000000000000 --- a/flang/test/Lower/OpenMP/FIR/pre-fir-tree01.f90 +++ /dev/null @@ -1,19 +0,0 @@ -! RUN: bbc -fopenmp -pft-test -o %t %s | FileCheck %s -! RUN: %flang_fc1 -fopenmp -fdebug-dump-pft -o %t %s | FileCheck %s - -! Test structure of the Pre-FIR tree with OpenMP - -subroutine sub1(a, b, n) - real :: a(:), b(:) - integer :: n, i - !$omp parallel do - do i = 1, n - b(i) = exp(a(i)) - end do - !$omp end parallel do -end subroutine - -! CHECK-LABEL: Subroutine sub1 -! CHECK: <> -! CHECK: <> -! CHECK: <> diff --git a/flang/test/Lower/OpenMP/FIR/private-commonblock.f90 b/flang/test/Lower/OpenMP/FIR/private-commonblock.f90 deleted file mode 100644 index 90036e0c0c7e..000000000000 --- a/flang/test/Lower/OpenMP/FIR/private-commonblock.f90 +++ /dev/null @@ -1,109 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s - -!CHECK: func.func @_QPprivate_common() { -!CHECK: omp.parallel { -!CHECK: %[[X:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFprivate_commonEx"} -!CHECK: %[[Y:.*]] = fir.alloca f32 {bindc_name = "y", pinned, uniq_name = "_QFprivate_commonEy"} -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } -subroutine private_common - common /c/ x, y - real x, y - !$omp parallel private(/c/) - !$omp end parallel -end subroutine - -!CHECK: %[[val_0:.*]] = fir.address_of(@blk_) : !fir.ref> -!CHECK: %[[val_1:.*]] = fir.convert %0 : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0:.*]] = arith.constant 0 : index -!CHECK: %[[val_2:.*]] = fir.coordinate_of %[[val_1]], %[[val_c0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_3:.*]] = fir.convert %[[val_2]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_4:.*]] = fir.convert %[[val_0]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c4:.*]] = arith.constant 4 : index -!CHECK: %[[val_5:.*]] = fir.coordinate_of %[[val_4]], %[[val_c4]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_6:.*]] = fir.convert %[[val_5]] : (!fir.ref) -> !fir.ref> -!CHECK: %[[val_7:.*]] = fir.convert %[[val_0]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c44:.*]] = arith.constant 44 : index -!CHECK: %[[val_8:.*]] = fir.coordinate_of %[[val_7]], %[[val_c44]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_9:.*]] = fir.convert %[[val_8]] : (!fir.ref) -> !fir.ref> -!CHECK: %[[val_c5:.*]] = arith.constant 5 : index -!CHECK: %[[val_10:.*]] = fir.convert %[[val_0]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c49:.*]] = arith.constant 49 : index -!CHECK: %[[val_11:.*]] = fir.coordinate_of %[[val_10]], %[[val_c49]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_12:.*]] = fir.convert %[[val_11]] : (!fir.ref) -> !fir.ref>> -!CHECK: %[[val_c5_0:.*]] = arith.constant 5 : index -!CHECK: %[[val_14:.*]] = fir.emboxchar %[[val_9]], %[[val_c5]] : (!fir.ref>, index) -> !fir.boxchar<1> -!CHECK: %[[val_15:.*]] = fir.convert %[[val_12]] : (!fir.ref>>) -> !fir.ref> -!CHECK: %[[val_16:.*]] = fir.emboxchar %[[val_15]], %[[val_c5_0]] : (!fir.ref>, index) -> !fir.boxchar<1> -!CHECK: fir.call @_QPsub1(%[[val_3]], %[[val_6]], %[[val_14]], %[[val_16]]) fastmath : (!fir.ref, !fir.ref>, !fir.boxchar<1>, !fir.boxchar<1>) -> () -!CHECK: omp.parallel { -!CHECK: %[[val_21:.*]] = fir.alloca i32 {bindc_name = "a", pinned, uniq_name = "_QFprivate_clause_commonblockEa"} -!CHECK: %[[val_22:.*]] = fir.alloca !fir.array<10xf32> {bindc_name = "b", pinned, uniq_name = "_QFprivate_clause_commonblockEb"} -!CHECK: %[[val_23:.*]] = fir.alloca !fir.char<1,5> {bindc_name = "c", pinned, uniq_name = "_QFprivate_clause_commonblockEc"} -!CHECK: %[[val_24:.*]] = fir.alloca !fir.array<5x!fir.char<1,5>> {bindc_name = "d", pinned, uniq_name = "_QFprivate_clause_commonblockEd"} -!CHECK: %[[val_26:.*]] = fir.emboxchar %[[val_23]], %[[val_c5]] : (!fir.ref>, index) -> !fir.boxchar<1> -!CHECK: %[[val_27:.*]] = fir.convert %[[val_24]] : (!fir.ref>>) -> !fir.ref> -!CHECK: %[[val_28:.*]] = fir.emboxchar %[[val_27]], %[[val_c5_0]] : (!fir.ref>, index) -> !fir.boxchar<1> -!CHECK: fir.call @_QPsub2(%[[val_21]], %[[val_22]], %[[val_26]], %[[val_28]]) fastmath : (!fir.ref, !fir.ref>, !fir.boxchar<1>, !fir.boxchar<1>) -> () -!CHECK: omp.terminator -!CHECK: } -!CHECK: %[[val_18:.*]] = fir.emboxchar %[[val_9]], %[[val_c5]] : (!fir.ref>, index) -> !fir.boxchar<1> -!CHECK: %[[val_19:.*]] = fir.convert %[[val_12]] : (!fir.ref>>) -> !fir.ref> -!CHECK: %[[val_20:.*]] = fir.emboxchar %[[val_19]], %[[val_c5_0]] : (!fir.ref>, index) -> !fir.boxchar<1> -!CHECK: fir.call @_QPsub3(%[[val_3]], %[[val_6]], %[[val_18]], %[[val_20]]) fastmath : {{.*}} -!CHECK: return -!CHECK: } -subroutine private_clause_commonblock() - integer::a - real::b(10) - character(5):: c, d(5) - common /blk/ a, b, c, d - - call sub1(a, b, c, d) - !$omp parallel private(/blk/) - call sub2(a, b, c, d) - !$omp end parallel - call sub3(a, b, c, d) -end subroutine - -!CHECK: func.func @_QPprivate_clause_commonblock_pointer() { -!CHECK: %[[val_0:.*]] = fir.address_of(@blk_) : !fir.ref> -!CHECK: %[[val_1:.*]] = fir.convert %[[val_0]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c24:.*]] = arith.constant 24 : index -!CHECK: %[[val_2:.*]] = fir.coordinate_of %[[val_1]], %[[val_c24]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_3:.*]] = fir.convert %[[val_2]] : (!fir.ref) -> !fir.ref -!CHECK: %[[val_4:.*]] = fir.convert %[[val_0]] : (!fir.ref>) -> !fir.ref> -!CHECK: %[[val_c0:.*]] = arith.constant 0 : index -!CHECK: %[[val_5:.*]] = fir.coordinate_of %[[val_4]], %[[val_c0]] : (!fir.ref>, index) -> !fir.ref -!CHECK: %[[val_6:.*]] = fir.convert %[[val_5]] : (!fir.ref) -> !fir.ref>>> -!CHECK: %[[val_7:.*]] = fir.load %[[val_6]] : !fir.ref>>> -!CHECK: %[[val_8:.*]] = fir.box_addr %[[val_7]] : (!fir.box>>) -> !fir.ptr> -!CHECK: %[[val_9:.*]] = fir.convert %[[val_8]] : (!fir.ptr>) -> !fir.ref> -!CHECK: fir.call @_QPsub4(%[[val_9]], %[[val_3]]) fastmath : (!fir.ref>, !fir.ref) -> () -!CHECK: omp.parallel { -!CHECK: %[[val_13:.*]] = fir.alloca !fir.box>> {bindc_name = "c", pinned, uniq_name = "_QFprivate_clause_commonblock_pointerEc"} -!CHECK: %[[val_14:.*]] = fir.alloca i32 {bindc_name = "a", pinned, uniq_name = "_QFprivate_clause_commonblock_pointerEa"} -!CHECK: %[[val_15:.*]] = fir.load %[[val_13]] : !fir.ref>>> -!CHECK: %[[val_16:.*]] = fir.box_addr %[[val_15]] : (!fir.box>>) -> !fir.ptr> -!CHECK: %[[val_17:.*]] = fir.convert %[[val_16]] : (!fir.ptr>) -> !fir.ref> -!CHECK: fir.call @_QPsub5(%[[val_17]], %[[val_14]]) fastmath : (!fir.ref>, !fir.ref) -> () -!CHECK: omp.terminator -!CHECK: } -!CHECK: %[[val_10:.*]] = fir.load %[[val_6]] : !fir.ref>>> -!CHECK: %[[val_11:.*]] = fir.box_addr %[[val_10]] : (!fir.box>>) -> !fir.ptr> -!CHECK: %[[val_12:.*]] = fir.convert %[[val_11]] : (!fir.ptr>) -> !fir.ref> -!CHECK: fir.call @_QPsub6(%[[val_12]], %[[val_3]]) fastmath : (!fir.ref>, !fir.ref) -> () -!CHECK: return -!CHECK: } -subroutine private_clause_commonblock_pointer() - complex, pointer :: c - integer:: a - common /blk/ c, a - call sub4(c, a) - !$omp parallel private(/blk/) - call sub5(c, a) - !$omp end parallel - call sub6(c, a) -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/requires-common.f90 b/flang/test/Lower/OpenMP/FIR/requires-common.f90 deleted file mode 100644 index 2e112d72de3f..000000000000 --- a/flang/test/Lower/OpenMP/FIR/requires-common.f90 +++ /dev/null @@ -1,19 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s -! RUN: bbc -fopenmp -emit-fir %s -o - | FileCheck %s -! RUN: bbc -fopenmp -fopenmp-is-target-device -emit-fir %s -o - | FileCheck %s - -! This test checks the lowering of requires into MLIR - -!CHECK: module attributes { -!CHECK-SAME: omp.requires = #omp -block data init - !$omp requires unified_shared_memory - integer :: x - common /block/ x - data x / 10 / -end - -subroutine f - !$omp declare target -end subroutine f diff --git a/flang/test/Lower/OpenMP/FIR/requires-notarget.f90 b/flang/test/Lower/OpenMP/FIR/requires-notarget.f90 deleted file mode 100644 index bfa509208428..000000000000 --- a/flang/test/Lower/OpenMP/FIR/requires-notarget.f90 +++ /dev/null @@ -1,14 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s -! RUN: bbc -fopenmp -emit-fir %s -o - | FileCheck %s -! RUN: bbc -fopenmp -fopenmp-is-target-device -emit-fir %s -o - | FileCheck %s - -! This test checks that requires lowering into MLIR skips creating the -! omp.requires attribute with target-related clauses if there are no device -! functions in the compilation unit - -!CHECK: module attributes { -!CHECK-NOT: omp.requires -program requires - !$omp requires unified_shared_memory reverse_offload atomic_default_mem_order(seq_cst) -end program requires diff --git a/flang/test/Lower/OpenMP/FIR/requires.f90 b/flang/test/Lower/OpenMP/FIR/requires.f90 deleted file mode 100644 index bc53931b9f24..000000000000 --- a/flang/test/Lower/OpenMP/FIR/requires.f90 +++ /dev/null @@ -1,14 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s -! RUN: bbc -fopenmp -emit-fir %s -o - | FileCheck %s -! RUN: bbc -fopenmp -fopenmp-is-target-device -emit-fir %s -o - | FileCheck %s - -! This test checks the lowering of requires into MLIR - -!CHECK: module attributes { -!CHECK-SAME: omp.requires = #omp -program requires - !$omp requires unified_shared_memory reverse_offload atomic_default_mem_order(seq_cst) - !$omp target - !$omp end target -end program requires diff --git a/flang/test/Lower/OpenMP/FIR/rtl-flags.f90 b/flang/test/Lower/OpenMP/FIR/rtl-flags.f90 deleted file mode 100644 index ad8eb9e73213..000000000000 --- a/flang/test/Lower/OpenMP/FIR/rtl-flags.f90 +++ /dev/null @@ -1,39 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DEFAULT-DEVICE-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-version=45 %s -o - | FileCheck %s --check-prefix=DEFAULT-HOST-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-is-target-device -fopenmp-version=45 %s -o - | FileCheck %s --check-prefix=DEFAULT-DEVICE-FIR-VERSION -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-version=45 %s -o - | FileCheck %s --check-prefix=DEFAULT-HOST-FIR-VERSION -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-target-debug -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DBG-DEVICE-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-target-debug=111 -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=DBG-EQ-DEVICE-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-assume-teams-oversubscription -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=TEAMS-OSUB-DEVICE-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-assume-threads-oversubscription -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=THREAD-OSUB-DEVICE-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-assume-no-thread-state -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=THREAD-STATE-DEVICE-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-assume-no-nested-parallelism -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=NEST-PAR-DEVICE-FIR -!RUN: %flang_fc1 -emit-fir -fopenmp -fopenmp-target-debug -fopenmp-assume-teams-oversubscription -fopenmp-assume-no-nested-parallelism -fopenmp-assume-threads-oversubscription -fopenmp-assume-no-thread-state -fopenmp-is-target-device %s -o - | FileCheck %s --check-prefix=ALL-DEVICE-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=DEFAULT-DEVICE-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-is-target-device -fopenmp-version=45 -o - %s | FileCheck %s --check-prefix=DEFAULT-DEVICE-FIR-VERSION -!RUN: bbc -emit-fir -fopenmp -o - %s | FileCheck %s --check-prefix=DEFAULT-HOST-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-version=45 -o - %s | FileCheck %s --check-prefix=DEFAULT-HOST-FIR-VERSION -!RUN: bbc -emit-fir -fopenmp -fopenmp-target-debug=111 -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=DBG-EQ-DEVICE-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-assume-teams-oversubscription -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=TEAMS-OSUB-DEVICE-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-assume-threads-oversubscription -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=THREAD-OSUB-DEVICE-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-assume-no-thread-state -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=THREAD-STATE-DEVICE-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-assume-no-nested-parallelism -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=NEST-PAR-DEVICE-FIR -!RUN: bbc -emit-fir -fopenmp -fopenmp-target-debug=1 -fopenmp-assume-teams-oversubscription -fopenmp-assume-no-nested-parallelism -fopenmp-assume-threads-oversubscription -fopenmp-assume-no-thread-state -fopenmp-is-target-device -o - %s | FileCheck %s --check-prefix=ALL-DEVICE-FIR - -!DEFAULT-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!DEFAULT-DEVICE-FIR-SAME: omp.is_target_device = true -!DEFAULT-DEVICE-FIR-VERSION: module attributes {{{.*}}omp.flags = #omp.flags -!DEFAULT-DEVICE-FIR-VERSION-SAME: omp.is_target_device = true -!DEFAULT-DEVICE-FIR-VERSION-SAME: omp.version = #omp.version -!DEFAULT-HOST-FIR: module attributes {{{.*}}omp.is_target_device = false{{.*}} -!DEFAULT-HOST-FIR-VERSION: module attributes {{{.*}}omp.is_target_device = false -!DEFAULT-HOST-FIR-VERSION-SAME: omp.version = #omp.version -!DBG-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!DBG-EQ-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!TEAMS-OSUB-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!THREAD-OSUB-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!THREAD-STATE-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!NEST-PAR-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -!ALL-DEVICE-FIR: module attributes {{{.*}}omp.flags = #omp.flags -subroutine omp_subroutine() -end subroutine omp_subroutine diff --git a/flang/test/Lower/OpenMP/FIR/sections-pft.f90 b/flang/test/Lower/OpenMP/FIR/sections-pft.f90 deleted file mode 100644 index 7b20a87022c9..000000000000 --- a/flang/test/Lower/OpenMP/FIR/sections-pft.f90 +++ /dev/null @@ -1,91 +0,0 @@ -! RUN: %flang_fc1 -fdebug-pre-fir-tree -fopenmp %s | FileCheck %s - -subroutine openmp_sections(x, y) - - integer, intent(inout)::x, y - -!============================================================================== -! empty construct -!============================================================================== -!$omp sections -!$omp end sections - -!CHECK: OpenMPConstruct -!CHECK: End OpenMPConstruct - -!============================================================================== -! single section, without `!$omp section` -!============================================================================== -!$omp sections - call F1() -!$omp end sections - -!CHECK: OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: End OpenMPConstruct - -!============================================================================== -! single section with `!$omp section` -!============================================================================== -!$omp sections - !$omp section - call F1 -!$omp end sections - -!CHECK: OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: End OpenMPConstruct - -!============================================================================== -! multiple sections -!============================================================================== -!$omp sections - !$omp section - call F1 - !$omp section - call F2 - !$omp section - call F3 -!$omp end sections - -!CHECK: OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: End OpenMPConstruct - -!============================================================================== -! multiple sections with clauses -!============================================================================== -!$omp sections PRIVATE(x) FIRSTPRIVATE(y) - !$omp section - call F1 - !$omp section - call F2 - !$omp section - call F3 -!$omp end sections NOWAIT - -!CHECK: OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: OpenMPConstruct -!CHECK: CallStmt -!CHECK: End OpenMPConstruct -!CHECK: End OpenMPConstruct - -end subroutine openmp_sections diff --git a/flang/test/Lower/OpenMP/FIR/sections.f90 b/flang/test/Lower/OpenMP/FIR/sections.f90 deleted file mode 100644 index 7b313f3dc0b4..000000000000 --- a/flang/test/Lower/OpenMP/FIR/sections.f90 +++ /dev/null @@ -1,288 +0,0 @@ -! REQUIRES: openmp_runtime - -! This test checks the lowering of OpenMP sections construct with several clauses present - -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -!CHECK: func @_QQmain() attributes {fir.bindc_name = "sample"} { -!CHECK: %[[COUNT:.*]] = fir.address_of(@_QFEcount) : !fir.ref -!CHECK: %[[ETA:.*]] = fir.alloca f32 {bindc_name = "eta", uniq_name = "_QFEeta"} -!CHECK: %[[CONST_1:.*]] = arith.constant 4 : i64 -!CHECK: omp.sections allocate(%[[CONST_1]] : i64 -> %0 : !fir.ref) { -!CHECK: omp.section { -!CHECK: %[[PRIVATE_ETA:.*]] = fir.alloca f32 {bindc_name = "eta", pinned, uniq_name = "_QFEeta"} -!CHECK: %[[PRIVATE_DOUBLE_COUNT:.*]] = fir.alloca i32 {bindc_name = "double_count", pinned, uniq_name = "_QFEdouble_count"} -!CHECK: %[[const:.*]] = arith.constant 5 : i32 -!CHECK: fir.store %[[const]] to %[[COUNT]] : !fir.ref -!CHECK: %[[temp_count:.*]] = fir.load %[[COUNT]] : !fir.ref -!CHECK: %[[temp_double_count:.*]] = fir.load %[[PRIVATE_DOUBLE_COUNT]] : !fir.ref -!CHECK: %[[result:.*]] = arith.muli %[[temp_count]], %[[temp_double_count]] : i32 -!CHECK: {{.*}} = fir.convert %[[result]] : (i32) -> f32 -!CHECK: fir.store {{.*}} to %[[PRIVATE_ETA]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.section { -!CHECK: %[[PRIVATE_ETA:.*]] = fir.alloca f32 {bindc_name = "eta", pinned, uniq_name = "_QFEeta"} -!CHECK: %[[PRIVATE_DOUBLE_COUNT:.*]] = fir.alloca i32 {bindc_name = "double_count", pinned, uniq_name = "_QFEdouble_count"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_DOUBLE_COUNT]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 1 : i32 -!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[const]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_DOUBLE_COUNT]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.section { -!CHECK: %[[PRIVATE_ETA:.*]] = fir.alloca f32 {bindc_name = "eta", pinned, uniq_name = "_QFEeta"} -!CHECK: %[[PRIVATE_DOUBLE_COUNT:.*]] = fir.alloca i32 {bindc_name = "double_count", pinned, uniq_name = "_QFEdouble_count"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_ETA]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 7.000000e+00 : f32 -!CHECK: %[[result:.*]] = arith.subf %[[temp]], %[[const]] {{.*}}: f32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_ETA]] : !fir.ref -!CHECK: {{.*}} = fir.load %[[COUNT]] : !fir.ref -!CHECK: %[[temp_count:.*]] = fir.convert {{.*}} : (i32) -> f32 -!CHECK: %[[temp_eta:.*]] = fir.load %[[PRIVATE_ETA]] : !fir.ref -!CHECK: {{.*}} = arith.mulf %[[temp_count]], %[[temp_eta]] {{.*}}: f32 -!CHECK: %[[result:.*]] = fir.convert {{.*}} : (f32) -> i32 -!CHECK: fir.store %[[result]] to %[[COUNT]] : !fir.ref -!CHECK: {{.*}} = fir.load %[[COUNT]] : !fir.ref -!CHECK: %[[temp_count:.*]] = fir.convert {{.*}} : (i32) -> f32 -!CHECK: %[[temp_eta:.*]] = fir.load %[[PRIVATE_ETA]] : !fir.ref -!CHECK: {{.*}} = arith.subf %[[temp_count]], %[[temp_eta]] {{.*}}: f32 -!CHECK: %[[result:.*]] = fir.convert {{.*}} : (f32) -> i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_DOUBLE_COUNT]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.sections nowait { -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } - -program sample - use omp_lib - integer :: count = 0, double_count = 1 - !$omp sections private (eta, double_count) allocate(omp_high_bw_mem_alloc: count) - !$omp section - count = 1 + 4 - eta = count * double_count - !$omp section - double_count = double_count + 1 - !$omp section - eta = eta - 7 - count = count * eta - double_count = count - eta - !$omp end sections - - !$omp sections - !$omp end sections nowait -end program sample - -!CHECK: func @_QPfirstprivate(%[[ARG:.*]]: !fir.ref {fir.bindc_name = "alpha"}) { -!CHECK: omp.sections { -!CHECK: omp.section { -!CHECK: %[[PRIVATE_ALPHA:.*]] = fir.alloca f32 {bindc_name = "alpha", pinned, uniq_name = "_QFfirstprivateEalpha"} -!CHECK: %[[temp:.*]] = fir.load %[[ARG]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_ALPHA]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.sections { -!CHECK: omp.section { -!CHECK: %[[PRIVATE_VAR:.*]] = fir.load %[[ARG]] : !fir.ref -!CHECK: %[[CONSTANT:.*]] = arith.constant 5.000000e+00 : f32 -!CHECK: %[[PRIVATE_VAR_2:.*]] = arith.mulf %[[PRIVATE_VAR]], %[[CONSTANT]] {{.*}}: f32 -!CHECK: fir.store %[[PRIVATE_VAR_2]] to %[[ARG]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } - -subroutine firstprivate(alpha) - real :: alpha - !$omp sections firstprivate(alpha) - !$omp end sections - - !$omp sections - alpha = alpha * 5 - !$omp end sections -end subroutine - -subroutine lastprivate() - integer :: x -!CHECK: %[[X:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFlastprivateEx"} -!CHECK: omp.sections { - !$omp sections lastprivate(x) -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivateEx"} -!CHECK: %[[const:.*]] = arith.constant 10 : i32 -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[result:.*]] = arith.muli %c10_i32, %[[temp]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - !$omp section - x = x * 10 -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivateEx"} -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 1 : i32 -!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[const]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[true:.*]] = arith.constant true -!CHECK: fir.if %[[true]] { -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[X]] : !fir.ref -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - !$omp section - x = x + 1 -!CHECK: omp.terminator -!CHECK: } - !$omp end sections - -!CHECK: omp.sections { - !$omp sections firstprivate(x) lastprivate(x) -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivateEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.barrier -!CHECK: %[[const:.*]] = arith.constant 10 : i32 -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[result:.*]] = arith.muli %c10_i32, %[[temp]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - !$omp section - x = x * 10 -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivateEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.barrier -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 1 : i32 -!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[const]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[true:.*]] = arith.constant true -!CHECK: fir.if %true { -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[X]] : !fir.ref -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - !$omp section - x = x + 1 -!CHECK: omp.terminator -!CHECK: } - !$omp end sections - -!CHECK: omp.sections nowait { - !$omp sections firstprivate(x) lastprivate(x) -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivateEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.barrier -!CHECK: %[[const:.*]] = arith.constant 10 : i32 -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[result:.*]] = arith.muli %c10_i32, %[[temp]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } - !$omp section - x = x * 10 -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivateEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.barrier -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 1 : i32 -!CHECK: %[[result:.*]] = arith.addi %[[temp]], %[[const]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[true:.*]] = arith.constant true -!CHECK: fir.if %true { -!CHECK: %[[temp:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[X]] : !fir.ref -!CHECK: omp.barrier -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - !$omp section - x = x + 1 -!CHECK: omp.terminator -!CHECK: } - !$omp end sections nowait - -!CHECK: omp.sections { -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca i32 {bindc_name = "x", pinned, uniq_name = "_QFlastprivateEx"} -!CHECK: cf.br ^bb1 -!CHECK: ^bb1: // pred: ^bb0 -!CHECK: %[[INNER_PRIVATE_X:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[const:.*]] = arith.constant 1 : i32 -!CHECK: %[[result:.*]] = arith.addi %[[INNER_PRIVATE_X]], %[[const]] : i32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[loaded_value:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: fir.store %[[loaded_value]] to %[[X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: return -!CHECK: } - - !$omp sections lastprivate(x) - !$omp section - goto 30 - 30 x = x + 1 - !$omp end sections -end subroutine - -subroutine unstructured_sections_privatization() -!CHECK: %[[X:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFunstructured_sections_privatizationEx"} -!CHECK: omp.sections { -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFunstructured_sections_privatizationEx"} -!CHECK: cf.br ^bb1 -!CHECK: ^bb1: // pred: ^bb0 -!CHECK: %[[INNER_PRIVATE_X:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[constant:.*]] = arith.constant 1.000000e+00 : f32 -!CHECK: %[[result:.*]] = arith.addf %[[INNER_PRIVATE_X]], %[[constant]] fastmath : f32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - !$omp sections private(x) - !$omp section - goto 40 - 40 x = x + 1 - !$omp end sections -!CHECK: omp.sections { -!CHECK: omp.section { -!CHECK: %[[PRIVATE_X:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFunstructured_sections_privatizationEx"} -!CHECK: %[[temp:.*]] = fir.load %[[X]] : !fir.ref -!CHECK: fir.store %[[temp]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: cf.br ^bb1 -!CHECK: ^bb1: // pred: ^bb0 -!CHECK: %[[INNER_PRIVATE_X:.*]] = fir.load %[[PRIVATE_X]] : !fir.ref -!CHECK: %[[constant:.*]] = arith.constant 1.000000e+00 : f32 -!CHECK: %[[result:.*]] = arith.addf %[[INNER_PRIVATE_X]], %[[constant]] fastmath : f32 -!CHECK: fir.store %[[result]] to %[[PRIVATE_X]] : !fir.ref -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - !$omp sections firstprivate(x) - !$omp section - goto 50 - 50 x = x + 1 - !$omp end sections -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/simd.f90 b/flang/test/Lower/OpenMP/FIR/simd.f90 deleted file mode 100644 index 91e8750578bf..000000000000 --- a/flang/test/Lower/OpenMP/FIR/simd.f90 +++ /dev/null @@ -1,176 +0,0 @@ -! Tests for 2.9.3.1 Simd - -! The "if" clause was added to the "simd" directive in OpenMP 5.0. -! RUN: bbc -fopenmp -fopenmp-version=50 -emit-fir -hlfir=false %s -o - | FileCheck %s - -!CHECK-LABEL: func @_QPsimd() -subroutine simd - integer :: i - !$OMP SIMD - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: %[[UB:.*]] = arith.constant 9 : i32 - ! CHECK-NEXT: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK-NEXT: omp.simd { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_if_clause -subroutine simd_with_if_clause(n, threshold) - integer :: i, n, threshold - !$OMP SIMD IF( n .GE. threshold ) - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UB:.*]] = fir.load %arg0 - ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: %[[COND:.*]] = arith.cmpi sge - ! CHECK: omp.simd if(%[[COND:.*]]) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i = 1, n - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_simdlen_clause -subroutine simd_with_simdlen_clause(n, threshold) - integer :: i, n, threshold - !$OMP SIMD SIMDLEN(2) - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UB:.*]] = fir.load %arg0 - ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.simd simdlen(2) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i = 1, n - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_simdlen_clause_from_param -subroutine simd_with_simdlen_clause_from_param(n, threshold) - integer :: i, n, threshold - integer, parameter :: simdlen = 2; - !$OMP SIMD SIMDLEN(simdlen) - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UB:.*]] = fir.load %arg0 - ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.simd simdlen(2) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i = 1, n - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_simdlen_clause_from_expr_from_param -subroutine simd_with_simdlen_clause_from_expr_from_param(n, threshold) - integer :: i, n, threshold - integer, parameter :: simdlen = 2; - !$OMP SIMD SIMDLEN(simdlen*2 + 2) - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UB:.*]] = fir.load %arg0 - ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.simd simdlen(6) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i = 1, n - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_safelen_clause -subroutine simd_with_safelen_clause(n, threshold) - integer :: i, n, threshold - !$OMP SIMD SAFELEN(2) - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UB:.*]] = fir.load %arg0 - ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.simd safelen(2) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i = 1, n - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_safelen_clause_from_expr_from_param -subroutine simd_with_safelen_clause_from_expr_from_param(n, threshold) - integer :: i, n, threshold - integer, parameter :: safelen = 2; - !$OMP SIMD SAFELEN(safelen*2 + 2) - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UB:.*]] = fir.load %arg0 - ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.simd safelen(6) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i = 1, n - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_simdlen_safelen_clause -subroutine simd_with_simdlen_safelen_clause(n, threshold) - integer :: i, n, threshold - !$OMP SIMD SIMDLEN(1) SAFELEN(2) - ! CHECK: %[[LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UB:.*]] = fir.load %arg0 - ! CHECK: %[[STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.simd simdlen(1) safelen(2) { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[LB]]) to (%[[UB]]) inclusive step (%[[STEP]]) { - do i = 1, n - ! CHECK: fir.store %[[I]] to %[[LOCAL:.*]] : !fir.ref - ! CHECK: %[[LD:.*]] = fir.load %[[LOCAL]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LD]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - !$OMP END SIMD -end subroutine - -!CHECK-LABEL: func @_QPsimd_with_collapse_clause -subroutine simd_with_collapse_clause(n) - integer :: i, j, n - integer :: A(n,n) - ! CHECK: %[[LOWER_I:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UPPER_I:.*]] = fir.load %[[PARAM_ARG:.*]] : !fir.ref - ! CHECK: %[[STEP_I:.*]] = arith.constant 1 : i32 - ! CHECK: %[[LOWER_J:.*]] = arith.constant 1 : i32 - ! CHECK: %[[UPPER_J:.*]] = fir.load %[[PARAM_ARG:.*]] : !fir.ref - ! CHECK: %[[STEP_J:.*]] = arith.constant 1 : i32 - ! CHECK: omp.simd { - ! CHECK-NEXT: omp.loop_nest (%[[ARG_0:.*]], %[[ARG_1:.*]]) : i32 = ( - ! CHECK-SAME: %[[LOWER_I]], %[[LOWER_J]]) to ( - ! CHECK-SAME: %[[UPPER_I]], %[[UPPER_J]]) inclusive step ( - ! CHECK-SAME: %[[STEP_I]], %[[STEP_J]]) { - !$OMP SIMD COLLAPSE(2) - do i = 1, n - do j = 1, n - A(i,j) = i + j - end do - end do - !$OMP END SIMD -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/simple-barrier.f90 b/flang/test/Lower/OpenMP/FIR/simple-barrier.f90 deleted file mode 100644 index c621b8062eaa..000000000000 --- a/flang/test/Lower/OpenMP/FIR/simple-barrier.f90 +++ /dev/null @@ -1,6 +0,0 @@ -! RUN: bbc -fopenmp -emit-fir -o - %s | FileCheck %s - -subroutine sample() -! CHECK: omp.barrier -!$omp barrier -end subroutine sample diff --git a/flang/test/Lower/OpenMP/FIR/single.f90 b/flang/test/Lower/OpenMP/FIR/single.f90 deleted file mode 100644 index 65ae07c2c284..000000000000 --- a/flang/test/Lower/OpenMP/FIR/single.f90 +++ /dev/null @@ -1,123 +0,0 @@ -! REQUIRES: openmp_runtime - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s -!RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s - -!=============================================================================== -! Single construct -!=============================================================================== - -!CHECK-LABEL: func @_QPomp_single -!CHECK-SAME: (%[[x:.*]]: !fir.ref {fir.bindc_name = "x"}) -subroutine omp_single(x) - integer, intent(inout) :: x - !CHECK: omp.parallel - !$omp parallel - !CHECK: omp.single - !$omp single - !CHECK: %[[xval:.*]] = fir.load %[[x]] : !fir.ref - !CHECK: %[[res:.*]] = arith.addi %[[xval]], %{{.*}} : i32 - !CHECK: fir.store %[[res]] to %[[x]] : !fir.ref - x = x + 12 - !CHECK: omp.terminator - !$omp end single - !CHECK: omp.terminator - !$omp end parallel -end subroutine omp_single - -!=============================================================================== -! Single construct with nowait -!=============================================================================== - -!CHECK-LABEL: func @_QPomp_single_nowait -!CHECK-SAME: (%[[x:.*]]: !fir.ref {fir.bindc_name = "x"}) -subroutine omp_single_nowait(x) - integer, intent(inout) :: x - !CHECK: omp.parallel - !$omp parallel - !CHECK: omp.single nowait - !$omp single - !CHECK: %[[xval:.*]] = fir.load %[[x]] : !fir.ref - !CHECK: %[[res:.*]] = arith.addi %[[xval]], %{{.*}} : i32 - !CHECK: fir.store %[[res]] to %[[x]] : !fir.ref - x = x + 12 - !CHECK: omp.terminator - !$omp end single nowait - !CHECK: omp.terminator - !$omp end parallel -end subroutine omp_single_nowait - -!=============================================================================== -! Single construct with allocate -!=============================================================================== - -!CHECK-LABEL: func @_QPsingle_allocate -subroutine single_allocate() - use omp_lib - integer :: x - !CHECK: omp.parallel { - !$omp parallel - !CHECK: omp.single allocate(%{{.+}} : i64 -> %{{.+}} : !fir.ref) { - !$omp single allocate(omp_high_bw_mem_alloc: x) private(x) - !CHECK: arith.addi - x = x + 12 - !CHECK: omp.terminator - !$omp end single - !CHECK: omp.terminator - !$omp end parallel -end subroutine single_allocate - -!=============================================================================== -! Single construct with private/firstprivate -!=============================================================================== - -! CHECK-LABEL: func.func @_QPsingle_privatization( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}, -! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "y"}) { -! CHECK: omp.single { -! CHECK: %[[VAL_2:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFsingle_privatizationEx"} -! CHECK: %[[VAL_3:.*]] = fir.alloca f64 {bindc_name = "y", pinned, uniq_name = "_QFsingle_privatizationEy"} -! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: fir.store %[[VAL_4]] to %[[VAL_3]] : !fir.ref -! CHECK: fir.call @_QPbar(%[[VAL_2]], %[[VAL_3]]) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine single_privatization(x, y) - real :: x - real(8) :: y - - !$omp single private(x) firstprivate(y) - call bar(x, y) - !$omp end single -end subroutine - -! CHECK-LABEL: func.func @_QPsingle_privatization2( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "x"}, -! CHECK-SAME: %[[VAL_1:.*]]: !fir.ref {fir.bindc_name = "y"}) { -! CHECK: omp.parallel { -! CHECK: omp.single { -! CHECK: %[[VAL_2:.*]] = fir.alloca f32 {bindc_name = "x", pinned, uniq_name = "_QFsingle_privatization2Ex"} -! CHECK: %[[VAL_3:.*]] = fir.alloca f64 {bindc_name = "y", pinned, uniq_name = "_QFsingle_privatization2Ey"} -! CHECK: %[[VAL_4:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: fir.store %[[VAL_4]] to %[[VAL_3]] : !fir.ref -! CHECK: fir.call @_QPbar(%[[VAL_2]], %[[VAL_3]]) {{.*}}: (!fir.ref, !fir.ref) -> () -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine single_privatization2(x, y) - real :: x - real(8) :: y - - !$omp parallel - !$omp single private(x) firstprivate(y) - call bar(x, y) - !$omp end single - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 b/flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 deleted file mode 100644 index 32cc6d17c420..000000000000 --- a/flang/test/Lower/OpenMP/FIR/stop-stmt-in-region.f90 +++ /dev/null @@ -1,154 +0,0 @@ -! This test checks lowering of stop statement in OpenMP region. - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -! CHECK-LABEL: func.func @_QPtest_stop_in_region1() { -! CHECK: omp.parallel { -! CHECK: %[[VAL_0:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_1:.*]] = arith.constant false -! CHECK: %[[VAL_2:.*]] = arith.constant false -! CHECK: %[[VAL_3:.*]] = fir.call @_FortranAStopStatement(%[[VAL_0]], %[[VAL_1]], %[[VAL_2]]) {{.*}} : (i32, i1, i1) -> none -! CHECK-NOT: fir.unreachable -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine test_stop_in_region1() - !$omp parallel - stop 1 - !$omp end parallel -end - -! CHECK-LABEL: func.func @_QPtest_stop_in_region2() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFtest_stop_in_region2Ex"} -! CHECK: omp.parallel { -! CHECK: %[[VAL_1:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_2:.*]] = arith.constant false -! CHECK: %[[VAL_3:.*]] = arith.constant false -! CHECK: %[[VAL_4:.*]] = fir.call @_FortranAStopStatement(%[[VAL_1]], %[[VAL_2]], %[[VAL_3]]) {{.*}} : (i32, i1, i1) -> none -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine test_stop_in_region2() - integer :: x - !$omp parallel - stop 1 - x = 2 - !$omp end parallel -end - -! CHECK-LABEL: func.func @_QPtest_stop_in_region3() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFtest_stop_in_region3Ex"} -! CHECK: omp.parallel { -! CHECK: %[[VAL_1:.*]] = arith.constant 3 : i32 -! CHECK: fir.store %[[VAL_1]] to %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_3:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_4:.*]] = arith.cmpi sgt, %[[VAL_2]], %[[VAL_3]] : i32 -! CHECK: cf.cond_br %[[VAL_4]], ^bb1, ^bb2 -! CHECK: ^bb1: -! CHECK: %[[VAL_5:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = arith.constant false -! CHECK: %[[VAL_7:.*]] = arith.constant false -! CHECK: %[[VAL_8:.*]] = fir.call @_FortranAStopStatement(%[[VAL_5]], %[[VAL_6]], %[[VAL_7]]) {{.*}} : (i32, i1, i1) -> none -! CHECK: omp.terminator -! CHECK: ^bb2: -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine test_stop_in_region3() - integer :: x - !$omp parallel - x = 3 - if (x > 1) stop x - !$omp end parallel -end - -! CHECK-LABEL: func.func @_QPtest_stop_in_region4() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFtest_stop_in_region4Ei"} -! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFtest_stop_in_region4Ex"} -! CHECK: %[[VAL_3:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_4:.*]] = arith.constant 10 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[VAL_6:.*]]) : i32 = (%[[VAL_3]]) to (%[[VAL_4]]) inclusive step (%[[VAL_5]]) { -! CHECK: fir.store %[[VAL_6]] to %[[VAL_0]] : !fir.ref -! CHECK: cf.br ^bb1 -! CHECK: ^bb1: -! CHECK: %[[VAL_7:.*]] = arith.constant 3 : i32 -! CHECK: fir.store %[[VAL_7]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_10:.*]] = arith.cmpi sgt, %[[VAL_8]], %[[VAL_9]] : i32 -! CHECK: cf.cond_br %[[VAL_10]], ^bb2, ^bb3 -! CHECK: ^bb2: -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = arith.constant false -! CHECK: %[[VAL_13:.*]] = arith.constant false -! CHECK: %[[VAL_14:.*]] = fir.call @_FortranAStopStatement(%[[VAL_11]], %[[VAL_12]], %[[VAL_13]]) {{.*}} : (i32, i1, i1) -> none -! CHECK: omp.yield -! CHECK: ^bb3: -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: cf.br ^bb1 -! CHECK: ^bb1: -! CHECK: return -! CHECK: } - -subroutine test_stop_in_region4() - integer :: x - !$omp do - do i = 1, 10 - x = 3 - if (x > 1) stop x - enddo - !$omp end do -end - - -!CHECK-LABEL: func.func @_QPtest_stop_in_region5 -!CHECK: omp.parallel { -!CHECK: {{.*}} fir.call @_FortranAStopStatement({{.*}}, {{.*}}, {{.*}}) fastmath : (i32, i1, i1) -> none -!CHECK: omp.terminator -!CHECK: } -!CHECK: return - -subroutine test_stop_in_region5() - !$omp parallel - block - stop 1 - end block - !$omp end parallel -end - -!CHECK-LABEL: func.func @_QPtest_stop_in_region6 -!CHECK: omp.parallel { -!CHECK: cf.cond_br %{{.*}}, ^[[BB1:.*]], ^[[BB2:.*]] -!CHECK: ^[[BB1]]: -!CHECK: {{.*}}fir.call @_FortranAStopStatement({{.*}}, {{.*}}, {{.*}}) fastmath : (i32, i1, i1) -> none -!CHECK: omp.terminator -!CHECK: ^[[BB2]]: -!CHECK: {{.*}}fir.call @_FortranAStopStatement({{.*}}, {{.*}}, {{.*}}) fastmath : (i32, i1, i1) -> none -!CHECK: omp.terminator -!CHECK: } -!CHECK: return - -subroutine test_stop_in_region6(x) - integer :: x - !$omp parallel - if (x .gt. 1) then - stop 1 - else - stop 2 - end if - !$omp end parallel -end diff --git a/flang/test/Lower/OpenMP/FIR/target.f90 b/flang/test/Lower/OpenMP/FIR/target.f90 deleted file mode 100644 index ea4b9240e9e5..000000000000 --- a/flang/test/Lower/OpenMP/FIR/target.f90 +++ /dev/null @@ -1,554 +0,0 @@ -! The "thread_limit" clause was added to the "target" construct in OpenMP 5.1. -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -fopenmp-version=51 %s -o - | FileCheck %s - -!=============================================================================== -! Target_Enter Simple -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_enter_simple() { -subroutine omp_target_enter_simple - integer :: a(1024) - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(to) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_enter_data map_entries(%[[MAP]] : !fir.ref>) - !$omp target enter data map(to: a) -end subroutine omp_target_enter_simple - -!=============================================================================== -! Target_Enter Map types -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_enter_mt() { -subroutine omp_target_enter_mt - integer :: a(1024) - integer :: b(1024) - integer :: c(1024) - integer :: d(1024) - !CHECK: %[[BOUNDS_0:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_0:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(to) capture(ByRef) bounds(%[[BOUNDS_0]]) -> !fir.ref> {name = "a"} - !CHECK: %[[BOUNDS_1:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr(%{{.*}}) map_clauses(to) capture(ByRef) bounds(%[[BOUNDS_1]]) -> !fir.ref> {name = "b"} - !CHECK: %[[BOUNDS_2:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(always, exit_release_or_enter_alloc) capture(ByRef) bounds(%[[BOUNDS_2]]) -> !fir.ref> {name = "c"} - !CHECK: %[[BOUNDS_3:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_3:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(to) capture(ByRef) bounds(%[[BOUNDS_3]]) -> !fir.ref> {name = "d"} - !CHECK: omp.target_enter_data map_entries(%[[MAP_0]], %[[MAP_1]], %[[MAP_2]], %[[MAP_3]] : !fir.ref>, !fir.ref>, !fir.ref>, !fir.ref>) - !$omp target enter data map(to: a, b) map(always, alloc: c) map(to: d) -end subroutine omp_target_enter_mt - -!=============================================================================== -! `Nowait` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_enter_nowait() { -subroutine omp_target_enter_nowait - integer :: a(1024) - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(to) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_enter_data nowait map_entries(%[[MAP]] : !fir.ref>) - !$omp target enter data map(to: a) nowait -end subroutine omp_target_enter_nowait - -!=============================================================================== -! `if` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_enter_if() { -subroutine omp_target_enter_if - integer :: a(1024) - integer :: i - i = 5 - !CHECK: %[[VAL_3:.*]] = fir.load %[[VAL_1:.*]] : !fir.ref - !CHECK: %[[VAL_4:.*]] = arith.constant 10 : i32 - !CHECK: %[[VAL_5:.*]] = arith.cmpi slt, %[[VAL_3]], %[[VAL_4]] : i32 - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(to) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_enter_data if(%[[VAL_5]] : i1) map_entries(%[[MAP]] : !fir.ref>) - !$omp target enter data if(i<10) map(to: a) -end subroutine omp_target_enter_if - -!=============================================================================== -! `device` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_enter_device() { -subroutine omp_target_enter_device - integer :: a(1024) - !CHECK: %[[VAL_1:.*]] = arith.constant 2 : i32 - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(to) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_enter_data device(%[[VAL_1]] : i32) map_entries(%[[MAP]] : !fir.ref>) - !$omp target enter data map(to: a) device(2) -end subroutine omp_target_enter_device - -!=============================================================================== -! Target_Exit Simple -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_exit_simple() { -subroutine omp_target_exit_simple - integer :: a(1024) - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(from) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_exit_data map_entries(%[[MAP]] : !fir.ref>) - !$omp target exit data map(from: a) -end subroutine omp_target_exit_simple - -!=============================================================================== -! Target_Exit Map types -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_exit_mt() { -subroutine omp_target_exit_mt - integer :: a(1024) - integer :: b(1024) - integer :: c(1024) - integer :: d(1024) - integer :: e(1024) - !CHECK: %[[BOUNDS_0:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_0:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(from) capture(ByRef) bounds(%[[BOUNDS_0]]) -> !fir.ref> {name = "a"} - !CHECK: %[[BOUNDS_1:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(from) capture(ByRef) bounds(%[[BOUNDS_1]]) -> !fir.ref> {name = "b"} - !CHECK: %[[BOUNDS_2:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(exit_release_or_enter_alloc) capture(ByRef) bounds(%[[BOUNDS_2]]) -> !fir.ref> {name = "c"} - !CHECK: %[[BOUNDS_3:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_3:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(always, delete) capture(ByRef) bounds(%[[BOUNDS_3]]) -> !fir.ref> {name = "d"} - !CHECK: %[[BOUNDS_4:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_4:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(from) capture(ByRef) bounds(%[[BOUNDS_4]]) -> !fir.ref> {name = "e"} - !CHECK: omp.target_exit_data map_entries(%[[MAP_0]], %[[MAP_1]], %[[MAP_2]], %[[MAP_3]], %[[MAP_4]] : !fir.ref>, !fir.ref>, !fir.ref>, !fir.ref>, !fir.ref>) - !$omp target exit data map(from: a,b) map(release: c) map(always, delete: d) map(from: e) -end subroutine omp_target_exit_mt - -!=============================================================================== -! `device` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_exit_device() { -subroutine omp_target_exit_device - integer :: a(1024) - integer :: d - !CHECK: %[[VAL_2:.*]] = fir.load %[[VAL_1:.*]] : !fir.ref - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(from) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_exit_data device(%[[VAL_2]] : i32) map_entries(%[[MAP]] : !fir.ref>) - !$omp target exit data map(from: a) device(d) -end subroutine omp_target_exit_device - -!=============================================================================== -! Target_Update `to` clause -!=============================================================================== - -subroutine omp_target_update_to - integer :: a(1024) - - !CHECK-DAG: %[[A_ALLOC:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "a", uniq_name = "_QFomp_target_update_toEa"} - !CHECK-DAG: %[[BOUNDS:.*]] = omp.map.bounds - - !CHECK: %[[TO_MAP:.*]] = omp.map.info var_ptr(%[[A_ALLOC]] : !fir.ref>, !fir.array<1024xi32>) - !CHECK-SAME: map_clauses(to) capture(ByRef) - !CHECK-SAME: bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - - !CHECK: omp.target_update - !CHECK-SAME: motion_entries(%[[TO_MAP]] : !fir.ref>) - !$omp target update to(a) -end subroutine omp_target_update_to - -!=============================================================================== -! Target_Update `from` clause -!=============================================================================== - -subroutine omp_target_update_from - integer :: a(1024) - - !CHECK-DAG: %[[A_ALLOC:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "a", uniq_name = "_QFomp_target_update_fromEa"} - !CHECK-DAG: %[[BOUNDS:.*]] = omp.map.bounds - - !CHECK: %[[FROM_MAP:.*]] = omp.map.info var_ptr(%[[A_ALLOC]] : !fir.ref>, !fir.array<1024xi32>) - !CHECK-SAME: map_clauses(from) capture(ByRef) - !CHECK-SAME: bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - - !CHECK: omp.target_update - !CHECK-SAME: motion_entries(%[[FROM_MAP]] : !fir.ref>) - !$omp target update from(a) -end subroutine omp_target_update_from - -!=============================================================================== -! Target_Update `if` clause -!=============================================================================== - -subroutine omp_target_update_if - integer :: a(1024) - logical :: i - - !CHECK-DAG: %[[A_ALLOC:.*]] = fir.alloca - !CHECK-DAG: %[[BOUNDS:.*]] = omp.map.bounds - !CHECK-DAG: %[[COND:.*]] = fir.convert %{{.*}} : (!fir.logical<4>) -> i1 - - !CHECK: %[[TO_MAP:.*]] = omp.map.info - - !CHECK: omp.target_update if(%[[COND]] : i1) - !CHECK-SAME: motion_entries(%[[TO_MAP]] : !fir.ref>) - !$omp target update to(a) if(i) -end subroutine omp_target_update_if - -!=============================================================================== -! Target_Update `device` clause -!=============================================================================== - -subroutine omp_target_update_device - integer :: a(1024) - - !CHECK-DAG: %[[A_ALLOC:.*]] = fir.alloca - !CHECK-DAG: %[[BOUNDS:.*]] = omp.map.bounds - !CHECK-DAG: %[[DEVICE:.*]] = arith.constant 1 : i32 - - !CHECK: %[[TO_MAP:.*]] = omp.map.info - - !CHECK: omp.target_update - !CHECK-SAME: device(%[[DEVICE]] : i32) - !CHECK-SAME: motion_entries(%[[TO_MAP]] : !fir.ref>) - !$omp target update to(a) device(1) -end subroutine omp_target_update_device - -!=============================================================================== -! Target_Update `nowait` clause -!=============================================================================== - -subroutine omp_target_update_nowait - integer :: a(1024) - - !CHECK-DAG: %[[A_ALLOC:.*]] = fir.alloca - !CHECK-DAG: %[[BOUNDS:.*]] = omp.map.bounds - - !CHECK: %[[TO_MAP:.*]] = omp.map.info - - !CHECK: omp.target_update - !CHECK-SAME: nowait - !CHECK-SAME: motion_entries(%[[TO_MAP]] : !fir.ref>) - !$omp target update to(a) nowait -end subroutine omp_target_update_nowait - -!=============================================================================== -! Target_Data with region -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_data() { -subroutine omp_target_data - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "a", uniq_name = "_QFomp_target_dataEa"} - integer :: a(1024) - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr(%[[VAL_0]] : !fir.ref>, !fir.array<1024xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_data map_entries(%[[MAP]] : !fir.ref>) { - !$omp target data map(tofrom: a) - !CHECK: %[[VAL_1:.*]] = arith.constant 10 : i32 - !CHECK: %[[VAL_2:.*]] = arith.constant 1 : i64 - !CHECK: %[[VAL_3:.*]] = arith.constant 1 : i64 - !CHECK: %[[VAL_4:.*]] = arith.subi %[[VAL_2]], %[[VAL_3]] : i64 - !CHECK: %[[VAL_5:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_4]] : (!fir.ref>, i64) -> !fir.ref - !CHECK: fir.store %[[VAL_1]] to %[[VAL_5]] : !fir.ref - a(1) = 10 - !CHECK: omp.terminator - !$omp end target data - !CHECK: } -end subroutine omp_target_data - -!CHECK-LABEL: func.func @_QPomp_target_data_mt -subroutine omp_target_data_mt - integer :: a(1024) - integer :: b(1024) - !CHECK: %[[VAR_A:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "a", uniq_name = "_QFomp_target_data_mtEa"} - !CHECK: %[[VAR_B:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "b", uniq_name = "_QFomp_target_data_mtEb"} - !CHECK: %[[BOUNDS_A:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_A:.*]] = omp.map.info var_ptr(%[[VAR_A]] : !fir.ref>, !fir.array<1024xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS_A]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target_data map_entries(%[[MAP_A]] : !fir.ref>) { - !$omp target data map(a) - !CHECK: omp.terminator - !$omp end target data - !CHECK: } - !CHECK: %[[BOUNDS_B:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP_B:.*]] = omp.map.info var_ptr(%[[VAR_B]] : !fir.ref>, !fir.array<1024xi32>) map_clauses(always, from) capture(ByRef) bounds(%[[BOUNDS_B]]) -> !fir.ref> {name = "b"} - !CHECK: omp.target_data map_entries(%[[MAP_B]] : !fir.ref>) { - !$omp target data map(always, from : b) - !CHECK: omp.terminator - !$omp end target data - !CHECK: } -end subroutine omp_target_data_mt - -!=============================================================================== -! Target with region -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target() { -subroutine omp_target - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "a", uniq_name = "_QFomp_targetEa"} - integer :: a(1024) - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound({{.*}}) upper_bound({{.*}}) extent({{.*}}) stride({{.*}}) start_idx({{.*}}) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr(%[[VAL_0]] : !fir.ref>, !fir.array<1024xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: omp.target map_entries(%[[MAP]] -> %[[ARG_0:.*]] : !fir.ref>) { - !CHECK: ^bb0(%[[ARG_0]]: !fir.ref>): - !$omp target map(tofrom: a) - !CHECK: %[[VAL_1:.*]] = arith.constant 10 : i32 - !CHECK: %[[VAL_2:.*]] = arith.constant 1 : i64 - !CHECK: %[[VAL_3:.*]] = arith.constant 1 : i64 - !CHECK: %[[VAL_4:.*]] = arith.subi %[[VAL_2]], %[[VAL_3]] : i64 - !CHECK: %[[VAL_5:.*]] = fir.coordinate_of %[[ARG_0]], %[[VAL_4]] : (!fir.ref>, i64) -> !fir.ref - !CHECK: fir.store %[[VAL_1]] to %[[VAL_5]] : !fir.ref - a(1) = 10 - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target - -!=============================================================================== -! Target implicit capture -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_implicit() { -subroutine omp_target_implicit - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "a", uniq_name = "_QFomp_target_implicitEa"} - integer :: a(1024) - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr(%[[VAL_0]] : !fir.ref>, !fir.array<1024xi32>) map_clauses(implicit, tofrom) capture(ByRef) bounds(%{{.*}}) -> !fir.ref> {name = "a"} - !CHECK: omp.target map_entries(%[[MAP]] -> %[[ARG_0:.*]] : !fir.ref>) { - !CHECK: ^bb0(%[[ARG_0]]: !fir.ref>): - !$omp target - !CHECK: %[[VAL_5:.*]] = fir.coordinate_of %[[ARG_0]], %{{.*}} : (!fir.ref>, i64) -> !fir.ref - a(1) = 10 - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target_implicit - -!=============================================================================== -! Target implicit capture nested -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_implicit_nested() { -subroutine omp_target_implicit_nested - integer::a, b - !CHECK: omp.target map_entries(%{{.*}} -> %[[ARG0:.*]], %{{.*}} -> %[[ARG1:.*]] : !fir.ref, !fir.ref) { - !CHECK: ^bb0(%[[ARG0]]: !fir.ref, %[[ARG1]]: !fir.ref): - !$omp target - !CHECK: fir.store %{{.*}} to %[[ARG0]] : !fir.ref - a = 10 - !$omp parallel - !CHECK: fir.store %{{.*}} to %[[ARG1]] : !fir.ref - b = 20 - !CHECK: omp.terminator - !$omp end parallel - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target_implicit_nested - -!=============================================================================== -! Target implicit capture with bounds -!=============================================================================== - - -!CHECK-LABEL: func.func @_QPomp_target_implicit_bounds( -!CHECK: %[[VAL_0:.*]]: !fir.ref {fir.bindc_name = "n"}) { -subroutine omp_target_implicit_bounds(n) - !CHECK: %[[VAL_COPY:.*]] = fir.alloca i32 - !CHECK: %[[VAL_1:.*]] = fir.load %[[VAL_0]] : !fir.ref - !CHECK: fir.store %[[VAL_1]] to %[[VAL_COPY]] : !fir.ref - !CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i32) -> i64 - !CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_2]] : (i64) -> index - !CHECK: %[[VAL_4:.*]] = arith.constant 0 : index - !CHECK: %[[VAL_5:.*]] = arith.cmpi sgt, %[[VAL_3]], %[[VAL_4]] : index - !CHECK: %[[VAL_6:.*]] = arith.select %[[VAL_5]], %[[VAL_3]], %[[VAL_4]] : index - !CHECK: %[[VAL_7:.*]] = arith.constant 1024 : i64 - !CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i64) -> index - !CHECK: %[[VAL_9:.*]] = arith.constant 0 : index - !CHECK: %[[VAL_10:.*]] = arith.cmpi sgt, %[[VAL_8]], %[[VAL_9]] : index - !CHECK: %[[VAL_11:.*]] = arith.select %[[VAL_10]], %[[VAL_8]], %[[VAL_9]] : index - !CHECK: %[[VAL_12:.*]] = fir.alloca !fir.array, %[[VAL_6]] {bindc_name = "a", uniq_name = "_QFomp_target_implicit_boundsEa"} - integer :: n - integer :: a(n, 1024) - !CHECK: %[[VAL_13:.*]] = arith.constant 1 : index - !CHECK: %[[VAL_14:.*]] = arith.constant 0 : index - !CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_6]], %[[VAL_13]] : index - !CHECK: %[[VAL_16:.*]] = omp.map.bounds lower_bound(%[[VAL_14]] : index) upper_bound(%[[VAL_15]] : index) extent(%[[VAL_6]] : index) stride(%[[VAL_13]] : index) start_idx(%[[VAL_13]] : index) - !CHECK: %[[VAL_17:.*]] = arith.constant 0 : index - !CHECK: %[[VAL_18:.*]] = arith.subi %[[VAL_11]], %[[VAL_13]] : index - !CHECK: %[[VAL_19:.*]] = omp.map.bounds lower_bound(%[[VAL_17]] : index) upper_bound(%[[VAL_18]] : index) extent(%[[VAL_11]] : index) stride(%[[VAL_13]] : index) start_idx(%[[VAL_13]] : index) - !CHECK: %[[VAL_20:.*]] = omp.map.info var_ptr(%[[VAL_12]] : !fir.ref>, !fir.array) map_clauses(implicit, tofrom) capture(ByRef) bounds(%[[VAL_16]], %[[VAL_19]]) -> !fir.ref> {name = "a"} - !CHECK: %[[VAL_21:.*]] = omp.map.info var_ptr(%[[VAL_COPY]] : !fir.ref, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !fir.ref {name = ""} - !CHECK: omp.target map_entries(%[[VAL_20]] -> %[[VAL_22:.*]], %[[VAL_21]] -> %[[VAL_23:.*]] : !fir.ref>, !fir.ref) { - !CHECK: ^bb0(%[[VAL_22]]: !fir.ref>, %[[VAL_23]]: !fir.ref): - !$omp target - !CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_23]] : !fir.ref - !CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> i64 - !CHECK: %[[VAL_26:.*]] = arith.constant 0 : index - !CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (i64) -> index - !CHECK: %[[VAL_28:.*]] = arith.cmpi sgt, %[[VAL_27]], %[[VAL_26]] : index - !CHECK: %[[VAL_29:.*]] = arith.select %[[VAL_28]], %[[VAL_27]], %[[VAL_26]] : index - !CHECK: %[[VAL_30:.*]] = arith.constant 33 : i32 - !CHECK: %[[VAL_31:.*]] = fir.convert %[[VAL_22]] : (!fir.ref>) -> !fir.ref> - !CHECK: %[[VAL_32:.*]] = arith.constant 1 : index - !CHECK: %[[VAL_33:.*]] = arith.constant 0 : index - !CHECK: %[[VAL_34:.*]] = arith.constant 11 : i64 - !CHECK: %[[VAL_35:.*]] = fir.convert %[[VAL_34]] : (i64) -> index - !CHECK: %[[VAL_36:.*]] = arith.subi %[[VAL_35]], %[[VAL_32]] : index - !CHECK: %[[VAL_37:.*]] = arith.muli %[[VAL_32]], %[[VAL_36]] : index - !CHECK: %[[VAL_38:.*]] = arith.addi %[[VAL_37]], %[[VAL_33]] : index - !CHECK: %[[VAL_39:.*]] = arith.muli %[[VAL_32]], %[[VAL_29]] : index - !CHECK: %[[VAL_40:.*]] = arith.constant 22 : i64 - !CHECK: %[[VAL_41:.*]] = fir.convert %[[VAL_40]] : (i64) -> index - !CHECK: %[[VAL_42:.*]] = arith.subi %[[VAL_41]], %[[VAL_32]] : index - !CHECK: %[[VAL_43:.*]] = arith.muli %[[VAL_39]], %[[VAL_42]] : index - !CHECK: %[[VAL_44:.*]] = arith.addi %[[VAL_43]], %[[VAL_38]] : index - !CHECK: %[[VAL_45:.*]] = fir.coordinate_of %[[VAL_31]], %[[VAL_44]] : (!fir.ref>, index) -> !fir.ref - !CHECK: fir.store %[[VAL_30]] to %[[VAL_45]] : !fir.ref - a(11, 22) = 33 - !CHECK: omp.terminator - !$omp end target -!CHECK: } -end subroutine omp_target_implicit_bounds - -!=============================================================================== -! Target `thread_limit` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_thread_limit() { -subroutine omp_target_thread_limit - integer :: a - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "a"} - !CHECK: %[[VAL_1:.*]] = arith.constant 64 : i32 - !CHECK: omp.target thread_limit(%[[VAL_1]] : i32) map_entries(%[[MAP]] -> %[[ARG_0:.*]] : !fir.ref) { - !CHECK: ^bb0(%[[ARG_0]]: !fir.ref): - !$omp target map(tofrom: a) thread_limit(64) - a = 10 - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target_thread_limit - -!=============================================================================== -! Target `use_device_ptr` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_device_ptr() { -subroutine omp_target_device_ptr - use iso_c_binding, only : c_ptr, c_loc - type(c_ptr) :: a - integer, target :: b - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}}) map_clauses(tofrom) capture(ByRef) -> {{.*}} {name = "a"} - !CHECK: omp.target_data map_entries(%[[MAP]]{{.*}} - !$omp target data map(tofrom: a) use_device_ptr(a) - !CHECK: ^bb0(%[[VAL_1:.*]]: !fir.ref>): - !CHECK: {{.*}} = fir.coordinate_of %[[VAL_1:.*]], {{.*}} : (!fir.ref>, !fir.field) -> !fir.ref - a = c_loc(b) - !CHECK: omp.terminator - !$omp end target data - !CHECK: } -end subroutine omp_target_device_ptr - - !=============================================================================== - ! Target `use_device_addr` clause - !=============================================================================== - - !CHECK-LABEL: func.func @_QPomp_target_device_addr() { - subroutine omp_target_device_addr - integer, pointer :: a - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFomp_target_device_addrEa"} - !CHECK: %[[MAP_MEMBERS:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, i32) var_ptr_ptr({{.*}} : !fir.llvm_ptr>) map_clauses(tofrom) capture(ByRef) -> !fir.llvm_ptr> {name = ""} - !CHECK: %[[MAP:.*]] = omp.map.info var_ptr({{.*}} : !fir.ref>>, !fir.box>) map_clauses(tofrom) capture(ByRef) members(%[[MAP_MEMBERS]] : !fir.llvm_ptr>) -> !fir.ref>> {name = "a"} - !CHECK: omp.target_data map_entries(%[[MAP_MEMBERS]], %[[MAP]] : {{.*}}) use_device_addr(%[[VAL_0]] : !fir.ref>>) { - !$omp target data map(tofrom: a) use_device_addr(a) - !CHECK: ^bb0(%[[VAL_1:.*]]: !fir.ref>>): - !CHECK: {{.*}} = fir.load %[[VAL_1]] : !fir.ref>> - a = 10 - !CHECK: omp.terminator - !$omp end target data - !CHECK: } -end subroutine omp_target_device_addr - -!=============================================================================== -! Target with parallel loop -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_parallel_do() { -subroutine omp_target_parallel_do - !CHECK: %[[C1024:.*]] = arith.constant 1024 : index - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.array<1024xi32> {bindc_name = "a", uniq_name = "_QFomp_target_parallel_doEa"} - integer :: a(1024) - !CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFomp_target_parallel_doEi"} - integer :: i - !CHECK: %[[C1:.*]] = arith.constant 1 : index - !CHECK: %[[C0:.*]] = arith.constant 0 : index - !CHECK: %[[SUB:.*]] = arith.subi %[[C1024]], %[[C1]] : index - !CHECK: %[[BOUNDS:.*]] = omp.map.bounds lower_bound(%[[C0]] : index) upper_bound(%[[SUB]] : index) extent(%[[C1024]] : index) stride(%[[C1]] : index) start_idx(%[[C1]] : index) - !CHECK: %[[MAP1:.*]] = omp.map.info var_ptr(%[[VAL_0]] : !fir.ref>, !fir.array<1024xi32>) map_clauses(tofrom) capture(ByRef) bounds(%[[BOUNDS]]) -> !fir.ref> {name = "a"} - !CHECK: %[[MAP2:.*]] = omp.map.info var_ptr(%[[VAL_1]] : !fir.ref, i32) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByCopy) -> !fir.ref {name = "i"} - !CHECK: omp.target map_entries(%[[MAP1]] -> %[[VAL_2:.*]], %[[MAP2]] -> %[[VAL_3:.*]] : !fir.ref>, !fir.ref) { - !CHECK: ^bb0(%[[VAL_2]]: !fir.ref>, %[[VAL_3]]: !fir.ref): - !CHECK-NEXT: omp.parallel - !$omp target parallel do map(tofrom: a) - !CHECK: %[[VAL_4:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} - !CHECK: %[[VAL_5:.*]] = arith.constant 1 : i32 - !CHECK: %[[VAL_6:.*]] = arith.constant 1024 : i32 - !CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 - !CHECK: omp.wsloop { - !CHECK: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_5]]) to (%[[VAL_6]]) inclusive step (%[[VAL_7]]) { - !CHECK: fir.store %[[VAL_8]] to %[[VAL_4]] : !fir.ref - !CHECK: %[[VAL_9:.*]] = arith.constant 10 : i32 - !CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_4]] : !fir.ref - !CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i32) -> i64 - !CHECK: %[[VAL_12:.*]] = arith.constant 1 : i64 - !CHECK: %[[VAL_13:.*]] = arith.subi %[[VAL_11]], %[[VAL_12]] : i64 - !CHECK: %[[VAL_14:.*]] = fir.coordinate_of %[[VAL_2]], %[[VAL_13]] : (!fir.ref>, i64) -> !fir.ref - !CHECK: fir.store %[[VAL_9]] to %[[VAL_14]] : !fir.ref - do i = 1, 1024 - a(i) = 10 - end do - !CHECK: omp.yield - !CHECK: } - !CHECK: omp.terminator - !CHECK: } - !CHECK: omp.terminator - !CHECK: } - !CHECK: omp.terminator - !CHECK: } - !$omp end target parallel do -end subroutine omp_target_parallel_do - -!=============================================================================== -! Target `is_device_ptr` clause -!=============================================================================== - -!CHECK-LABEL: func.func @_QPomp_target_is_device_ptr() { -subroutine omp_target_is_device_ptr - use iso_c_binding, only : c_ptr, c_loc - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}> {bindc_name = "a", uniq_name = "_QFomp_target_is_device_ptrEa"} - type(c_ptr) :: a - !CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "b", fir.target, uniq_name = "_QFomp_target_is_device_ptrEb"} - integer, target :: b - !CHECK: %[[MAP_0:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(tofrom) capture(ByRef) -> !fir.ref> {name = "a"} - !CHECK: %[[MAP_1:.*]] = omp.map.info var_ptr(%[[VAL_0:.*]] : !fir.ref, i32) map_clauses(tofrom) capture(ByRef) -> !fir.ref {name = "b"} - !CHECK: %[[MAP_2:.*]] = omp.map.info var_ptr(%[[DEV_PTR:.*]] : !fir.ref>, !fir.type<_QM__fortran_builtinsT__builtin_c_ptr{__address:i64}>) map_clauses(implicit, exit_release_or_enter_alloc) capture(ByRef) -> !fir.ref> {name = "a"} - !CHECK: omp.target is_device_ptr(%[[DEV_PTR:.*]] : !fir.ref>) map_entries(%[[MAP_0:.*]] -> %[[ARG0:.*]], %[[MAP_1:.*]] -> %[[ARG1:.*]], %[[MAP_2:.*]] -> %[[ARG2:.*]] : !fir.ref>, !fir.ref, !fir.ref>) { - !CHECK: ^bb0(%[[ARG0]]: !fir.ref>, %[[ARG1]]: !fir.ref, %[[ARG2]]: !fir.ref>): - !$omp target map(tofrom: a,b) is_device_ptr(a) - !CHECK: {{.*}} = fir.coordinate_of %[[VAL_0:.*]], {{.*}} : (!fir.ref>, !fir.field) -> !fir.ref - a = c_loc(b) - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target_is_device_ptr - - !=============================================================================== - ! Target `has_device_addr` clause - !=============================================================================== - - !CHECK-LABEL: func.func @_QPomp_target_has_device_addr() { - subroutine omp_target_has_device_addr - !CHECK: %[[VAL_0:.*]] = fir.alloca !fir.box> {bindc_name = "a", uniq_name = "_QFomp_target_has_device_addrEa"} - integer, pointer :: a - !CHECK: omp.target has_device_addr(%[[VAL_0:.*]] : !fir.ref>>) map_entries({{.*}} -> {{.*}}, {{.*}} -> {{.*}} : !fir.llvm_ptr>, !fir.ref>>) { - !$omp target has_device_addr(a) - !CHECK: {{.*}} = fir.load %[[VAL_0:.*]] : !fir.ref>> - a = 10 - !CHECK: omp.terminator - !$omp end target - !CHECK: } -end subroutine omp_target_has_device_addr diff --git a/flang/test/Lower/OpenMP/FIR/target_cpu_features.f90 b/flang/test/Lower/OpenMP/FIR/target_cpu_features.f90 deleted file mode 100644 index 5154782e1ae1..000000000000 --- a/flang/test/Lower/OpenMP/FIR/target_cpu_features.f90 +++ /dev/null @@ -1,19 +0,0 @@ -!REQUIRES: amdgpu-registered-target, nvptx-registered-target -!RUN: %flang_fc1 -emit-fir -triple amdgcn-amd-amdhsa -target-cpu gfx908 -fopenmp -fopenmp-is-target-device %s -o - | FileCheck --check-prefix=AMDGCN %s -!RUN: %flang_fc1 -emit-fir -triple nvptx64-nvidia-cuda -target-cpu sm_80 -fopenmp -fopenmp-is-target-device %s -o - | FileCheck --check-prefix=NVPTX %s - -!=============================================================================== -! Target_Enter Simple -!=============================================================================== - -!AMDGCN: module attributes { -!AMDGCN-SAME: fir.target_cpu = "gfx908" -!AMDGCN-SAME: fir.target_features = #llvm.target_features<["+16-bit-insts", "+ci-insts", -!AMDGCN-SAME: "+dl-insts", "+dot1-insts", "+dot10-insts", "+dot2-insts", "+dot3-insts", -!AMDGCN-SAME: "+dot4-insts", "+dot5-insts", "+dot6-insts", "+dot7-insts", "+dpp", -!AMDGCN-SAME: "+gfx8-insts", "+gfx9-insts", "+gws", "+image-insts", "+mai-insts", -!AMDGCN-SAME: "+s-memrealtime", "+s-memtime-inst", "+wavefrontsize64"]> - -!NVPTX: module attributes { -!NVPTX-SAME: fir.target_cpu = "sm_80" -!NVPTX-SAME: fir.target_features = #llvm.target_features<["+ptx61", "+sm_80"]> diff --git a/flang/test/Lower/OpenMP/FIR/task.f90 b/flang/test/Lower/OpenMP/FIR/task.f90 deleted file mode 100644 index 012ac757d304..000000000000 --- a/flang/test/Lower/OpenMP/FIR/task.f90 +++ /dev/null @@ -1,237 +0,0 @@ -! REQUIRES: openmp_runtime - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -!CHECK-LABEL: func @_QPomp_task_simple() { -subroutine omp_task_simple - !CHECK: omp.task { - !$omp task - !CHECK: fir.call @_QPfoo() {{.*}}: () -> () - call foo() - !CHECK: omp.terminator - !$omp end task -end subroutine omp_task_simple - -!=============================================================================== -! `if` clause -!=============================================================================== - -!CHECK-LABEL: func @_QPomp_task_if(%{{.+}}) { -subroutine omp_task_if(bar) - logical, intent(inout) :: bar - !CHECK: omp.task if(%{{.+}}) { - !$omp task if(bar) - !CHECK: fir.call @_QPfoo() {{.*}}: () -> () - call foo() - !CHECK: omp.terminator - !$omp end task -end subroutine omp_task_if - -!=============================================================================== -! `final` clause -!=============================================================================== - -!CHECK-LABEL: func @_QPomp_task_final(%{{.+}}) { -subroutine omp_task_final(bar) - logical, intent(inout) :: bar - !CHECK: omp.task final(%{{.+}}) { - !$omp task final(bar) - !CHECK: fir.call @_QPfoo() {{.*}}: () -> () - call foo() - !CHECK: omp.terminator - !$omp end task -end subroutine omp_task_final - -!=============================================================================== -! `priority` clause -!=============================================================================== - -!CHECK-LABEL: func @_QPomp_task_priority(%{{.+}}) { -subroutine omp_task_priority(bar) - integer, intent(inout) :: bar - !CHECK: omp.task priority(%{{.+}}) { - !$omp task priority(bar) - !CHECK: fir.call @_QPfoo() {{.*}}: () -> () - call foo() - !CHECK: omp.terminator - !$omp end task -end subroutine omp_task_priority - -!=============================================================================== -! `allocate` clause -!=============================================================================== - -!CHECK-LABEL: func @_QPtask_allocate -subroutine task_allocate() - use omp_lib - integer :: x - !CHECK: omp.task allocate(%{{.+}} : i64 -> %{{.+}} : !fir.ref) { - !$omp task allocate(omp_high_bw_mem_alloc: x) private(x) - !CHECK: arith.addi - x = x + 12 - !CHECK: omp.terminator - !$omp end task -end subroutine task_allocate - -!=============================================================================== -! `depend` clause -!=============================================================================== - -!CHECK-LABEL: func @_QPtask_depend -subroutine task_depend() - integer :: x - !CHECK: omp.task depend(taskdependin -> %{{.+}} : !fir.ref) { - !$omp task depend(in : x) - !CHECK: arith.addi - x = x + 12 - !CHECK: omp.terminator - !$omp end task -end subroutine task_depend - -!CHECK-LABEL: func @_QPtask_depend_non_int -subroutine task_depend_non_int() - character(len = 15) :: x - integer, allocatable :: y - complex :: z - !CHECK: omp.task depend(taskdependin -> %{{.+}} : !fir.ref>, taskdependin -> %{{.+}} : !fir.ref>>, taskdependin -> %{{.+}} : !fir.ref>) { - !$omp task depend(in : x, y, z) - !CHECK: omp.terminator - !$omp end task -end subroutine task_depend_non_int - -!CHECK-LABEL: func @_QPtask_depend_all_kinds_one_task -subroutine task_depend_all_kinds_one_task() - integer :: x - !CHECK: omp.task depend(taskdependin -> %{{.+}} : !fir.ref, taskdependout -> %{{.+}} : !fir.ref, taskdependinout -> %{{.+}} : !fir.ref) { - !$omp task depend(in : x) depend(out : x) depend(inout : x) - !CHECK: arith.addi - x = x + 12 - !CHECK: omp.terminator - !$omp end task -end subroutine task_depend_all_kinds_one_task - -!CHECK-LABEL: func @_QPtask_depend_multi_var -subroutine task_depend_multi_var() - integer :: x - integer :: y - !CHECK: omp.task depend(taskdependin -> %{{.*}} : !fir.ref, taskdependin -> %{{.+}} : !fir.ref) { - !$omp task depend(in :x,y) - !CHECK: arith.addi - x = x + 12 - y = y + 12 - !CHECK: omp.terminator - !$omp end task -end subroutine task_depend_multi_var - -!CHECK-LABEL: func @_QPtask_depend_multi_task -subroutine task_depend_multi_task() - integer :: x - !CHECK: omp.task depend(taskdependout -> %{{.+}} : !fir.ref) - !$omp task depend(out : x) - !CHECK: arith.addi - x = x + 12 - !CHECK: omp.terminator - !$omp end task - !CHECK: omp.task depend(taskdependinout -> %{{.+}} : !fir.ref) - !$omp task depend(inout : x) - !CHECK: arith.addi - x = x + 12 - !CHECK: omp.terminator - !$omp end task - !CHECK: omp.task depend(taskdependin -> %{{.+}} : !fir.ref) - !$omp task depend(in : x) - !CHECK: arith.addi - x = x + 12 - !CHECK: omp.terminator - !$omp end task -end subroutine task_depend_multi_task - -!=============================================================================== -! `private` clause -!=============================================================================== -!CHECK-LABEL: func @_QPtask_private -subroutine task_private - type mytype - integer :: x - end type mytype - - !CHECK: %[[int_var:.+]] = fir.alloca i32 - !CHECK: %[[mytype_var:.+]] = fir.alloca !fir.type<_QFtask_privateTmytype{x:i32}> - integer :: int_var - type(mytype) :: mytype_var - - !CHECK: fir.call @_QPbar(%[[int_var]], %[[mytype_var]]) {{.*}}: (!fir.ref, !fir.ref>) -> () - call bar(int_var, mytype_var) - - !CHECK: omp.task { - !$omp task private(int_var, mytype_var) - !CHECK: %[[int_var_private:.+]] = fir.alloca i32 - !CHECK: %[[mytype_var_private:.+]] = fir.alloca !fir.type<_QFtask_privateTmytype{x:i32}> - - !CHECK: fir.call @_QPbar(%[[int_var_private]], %[[mytype_var_private]]) {{.*}}: (!fir.ref, !fir.ref>) -> () - call bar(int_var, mytype_var) - !CHECK: omp.terminator - !$omp end task -end subroutine task_private - -!=============================================================================== -! `firstprivate` clause -!=============================================================================== -!CHECK-LABEL: func @_QPtask_firstprivate -subroutine task_firstprivate - type mytype - integer :: x - end type mytype - - !CHECK: %[[int_var:.+]] = fir.alloca i32 - !CHECK: %[[mytype_var:.+]] = fir.alloca !fir.type<_QFtask_firstprivateTmytype{x:i32}> - integer :: int_var - type(mytype) :: mytype_var - - !CHECK: fir.call @_QPbaz(%[[int_var]], %[[mytype_var]]) {{.*}}: (!fir.ref, !fir.ref>) -> () - call baz(int_var, mytype_var) - - !CHECK: omp.task { - !$omp task firstprivate(int_var, mytype_var) - !CHECK: %[[int_var_firstprivate:.+]] = fir.alloca i32 - !CHECK: %[[int_var_load:.+]] = fir.load %[[int_var]] : !fir.ref - !CHECK: fir.store %[[int_var_load]] to %[[int_var_firstprivate]] : !fir.ref - !CHECK: %[[mytype_var_firstprivate:.+]] = fir.alloca !fir.type<_QFtask_firstprivateTmytype{x:i32}> - !CHECK: %[[mytype_var_load:.+]] = fir.load %[[mytype_var]] : !fir.ref> - !CHECK: fir.store %[[mytype_var_load]] to %[[mytype_var_firstprivate]] - !CHECK: fir.call @_QPbaz(%[[int_var_firstprivate]], %[[mytype_var_firstprivate]]) {{.*}}: (!fir.ref, !fir.ref>) -> () - call baz(int_var, mytype_var) - !CHECK: omp.terminator - !$omp end task -end subroutine task_firstprivate - -!=============================================================================== -! Multiple clauses -!=============================================================================== - -!CHECK-LABEL: func @_QPtask_multiple_clauses -subroutine task_multiple_clauses() - use omp_lib - - !CHECK: %[[x:.+]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFtask_multiple_clausesEx"} - !CHECK: %[[y:.+]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFtask_multiple_clausesEy"} - !CHECK: %[[z:.+]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFtask_multiple_clausesEz"} - integer :: x, y, z - logical :: buzz - - !CHECK: omp.task if(%{{.+}}) final(%{{.+}}) priority(%{{.+}}) allocate(%{{.+}} : i64 -> %{{.+}} : !fir.ref) { - !$omp task if(buzz) final(buzz) priority(z) allocate(omp_high_bw_mem_alloc: x) private(x) firstprivate(y) - - !CHECK: %[[x_priv:.+]] = fir.alloca i32 - !CHECK: %[[y_priv:.+]] = fir.alloca i32 - !CHECK: %[[y_load:.+]] = fir.load %[[y]] : !fir.ref - !CHECK: fir.store %[[y_load]] to %[[y_priv]] : !fir.ref - - !CHECK: arith.addi - x = x + 12 - !CHECK: arith.subi - y = y - 12 - - !CHECK: omp.terminator - !$omp end task -end subroutine task_multiple_clauses diff --git a/flang/test/Lower/OpenMP/FIR/taskgroup.f90 b/flang/test/Lower/OpenMP/FIR/taskgroup.f90 deleted file mode 100644 index 78b9da8e9b09..000000000000 --- a/flang/test/Lower/OpenMP/FIR/taskgroup.f90 +++ /dev/null @@ -1,21 +0,0 @@ -! REQUIRES: openmp_runtime - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -!CHECK-LABEL: @_QPomp_taskgroup -subroutine omp_taskgroup -use omp_lib -integer :: allocated_x -!CHECK-DAG: %{{.*}} = fir.alloca i32 {bindc_name = "allocated_x", uniq_name = "_QFomp_taskgroupEallocated_x"} -!CHECK-DAG: %{{.*}} = arith.constant 4 : i64 - -!CHECK: omp.taskgroup allocate(%{{.*}} : i64 -> %0 : !fir.ref) -!$omp taskgroup allocate(omp_high_bw_mem_alloc: allocated_x) -!$omp task -!CHECK: fir.call @_QPwork() {{.*}}: () -> () - call work() -!CHECK: omp.terminator -!$omp end task -!CHECK: omp.terminator -!$omp end taskgroup -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/taskwait.f90 b/flang/test/Lower/OpenMP/FIR/taskwait.f90 deleted file mode 100644 index eed4f1b84a22..000000000000 --- a/flang/test/Lower/OpenMP/FIR/taskwait.f90 +++ /dev/null @@ -1,12 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect" - -!FIRDialect-LABEL: @_QPomp_taskwait -subroutine omp_taskwait - !OMPDialect: omp.taskwait - !$omp taskwait - !FIRDialect: fir.call @_QPfoo() {{.*}}: () -> () - call foo() - !OMPDialect: omp.taskwait - !$omp taskwait -end subroutine omp_taskwait diff --git a/flang/test/Lower/OpenMP/FIR/taskyield.f90 b/flang/test/Lower/OpenMP/FIR/taskyield.f90 deleted file mode 100644 index ca0bc1d071df..000000000000 --- a/flang/test/Lower/OpenMP/FIR/taskyield.f90 +++ /dev/null @@ -1,12 +0,0 @@ -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s --check-prefixes="FIRDialect,OMPDialect" -!RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | fir-opt --fir-to-llvm-ir | FileCheck %s --check-prefixes="OMPDialect" - -!FIRDialect-LABEL: @_QPomp_taskyield -subroutine omp_taskyield - !OMPDialect: omp.taskyield - !$omp taskyield - !FIRDialect: fir.call @_QPfoo() {{.*}}: () -> () - call foo() - !OMPDialect: omp.taskyield - !$omp taskyield -end subroutine omp_taskyield diff --git a/flang/test/Lower/OpenMP/FIR/teams.f90 b/flang/test/Lower/OpenMP/FIR/teams.f90 deleted file mode 100644 index 9c0593a24f2d..000000000000 --- a/flang/test/Lower/OpenMP/FIR/teams.f90 +++ /dev/null @@ -1,117 +0,0 @@ -! REQUIRES: openmp_runtime - -! RUN: %flang_fc1 -emit-fir -fopenmp %s -o - | FileCheck %s - -! CHECK-LABEL: func @_QPteams_simple -subroutine teams_simple() - ! CHECK: omp.teams - !$omp teams - ! CHECK: fir.call - call f1() - ! CHECK: omp.terminator - !$omp end teams -end subroutine teams_simple - -!=============================================================================== -! `num_teams` clause -!=============================================================================== - -! CHECK-LABEL: func @_QPteams_numteams -subroutine teams_numteams(num_teams) - integer, intent(inout) :: num_teams - - ! CHECK: omp.teams - ! CHECK-SAME: num_teams( to %{{.*}}: i32) - !$omp teams num_teams(4) - ! CHECK: fir.call - call f1() - ! CHECK: omp.terminator - !$omp end teams - - ! CHECK: omp.teams - ! CHECK-SAME: num_teams( to %{{.*}}: i32) - !$omp teams num_teams(num_teams) - ! CHECK: fir.call - call f2() - ! CHECK: omp.terminator - !$omp end teams - -end subroutine teams_numteams - -!=============================================================================== -! `if` clause -!=============================================================================== - -! CHECK-LABEL: func @_QPteams_if -subroutine teams_if(alpha) - integer, intent(in) :: alpha - logical :: condition - - ! CHECK: omp.teams - ! CHECK-SAME: if(%{{.*}}) - !$omp teams if(.false.) - ! CHECK: fir.call - call f1() - ! CHECK: omp.terminator - !$omp end teams - - ! CHECK: omp.teams - ! CHECK-SAME: if(%{{.*}}) - !$omp teams if(alpha .le. 0) - ! CHECK: fir.call - call f2() - ! CHECK: omp.terminator - !$omp end teams - - ! CHECK: omp.teams - ! CHECK-SAME: if(%{{.*}}) - !$omp teams if(condition) - ! CHECK: fir.call - call f3() - ! CHECK: omp.terminator - !$omp end teams -end subroutine teams_if - -!=============================================================================== -! `thread_limit` clause -!=============================================================================== - -! CHECK-LABEL: func @_QPteams_threadlimit -subroutine teams_threadlimit(thread_limit) - integer, intent(inout) :: thread_limit - - ! CHECK: omp.teams - ! CHECK-SAME: thread_limit(%{{.*}}: i32) - !$omp teams thread_limit(4) - ! CHECK: fir.call - call f1() - ! CHECK: omp.terminator - !$omp end teams - - ! CHECK: omp.teams - ! CHECK-SAME: thread_limit(%{{.*}}: i32) - !$omp teams thread_limit(thread_limit) - ! CHECK: fir.call - call f2() - ! CHECK: omp.terminator - !$omp end teams - -end subroutine teams_threadlimit - -!=============================================================================== -! `allocate` clause -!=============================================================================== - -! CHECK-LABEL: func @_QPteams_allocate -subroutine teams_allocate() - use omp_lib - integer :: x - integer :: y - ! CHECK: omp.teams - ! CHECK-SAME: allocate(%{{.+}} : i64 -> %{{.+}} : !fir.ref) - !$omp teams allocate(omp_high_bw_mem_alloc: x) private(x) - ! CHECK: arith.addi - x = x + 12 - ! CHECK: omp.terminator - !$omp end teams -end subroutine teams_allocate diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-char-array-chararray.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-char-array-chararray.f90 deleted file mode 100644 index 3580add37ef4..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-char-array-chararray.f90 +++ /dev/null @@ -1,46 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for character, array, and character array. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -module test - character :: x - integer :: y(5) - character(5) :: z(5) - - !$omp threadprivate(x, y, z) - -!CHECK-DAG: fir.global @_QMtestEx : !fir.char<1> { -!CHECK-DAG: fir.global @_QMtestEy : !fir.array<5xi32> { -!CHECK-DAG: fir.global @_QMtestEz : !fir.array<5x!fir.char<1,5>> { - -contains - subroutine sub() -!CHECK-DAG: [[ADDR0:%.*]] = fir.address_of(@_QMtestEx) : !fir.ref> -!CHECK-DAG: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR1:%.*]] = fir.address_of(@_QMtestEy) : !fir.ref> -!CHECK-DAG: [[NEWADDR1:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR2:%.*]] = fir.address_of(@_QMtestEz) : !fir.ref>> -!CHECK-DAG: [[NEWADDR2:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[NEWADDR1]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -!CHECK-DAG: %{{.*}} = fir.embox [[NEWADDR2]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> - print *, x, y, z - - !$omp parallel -!CHECK-DAG: [[ADDR33:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR34:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR35:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.convert [[ADDR33]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR34]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR35]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> - print *, x, y, z - !$omp end parallel - -!CHECK-DAG: %{{.*}} = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[NEWADDR1]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -!CHECK-DAG: %{{.*}} = fir.embox [[NEWADDR2]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> - print *, x, y, z - - end -end diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-commonblock.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-commonblock.f90 deleted file mode 100644 index 49f592ec8121..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-commonblock.f90 +++ /dev/null @@ -1,91 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for common block. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -module test - integer:: a - real :: b(2) - complex, pointer :: c, d(:) - character(5) :: e, f(2) - common /blk/ a, b, c, d, e, f - - !$omp threadprivate(/blk/) - -!CHECK: fir.global common @blk_(dense<0> : vector<103xi8>) : !fir.array<103xi8> - -contains - subroutine sub() -!CHECK: [[ADDR0:%.*]] = fir.address_of(@blk_) : !fir.ref> -!CHECK: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR1:%.*]] = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[C0:%.*]] = arith.constant 0 : index -!CHECK-DAG: [[ADDR2:%.*]] = fir.coordinate_of [[ADDR1]], [[C0]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR3:%.*]] = fir.convert [[ADDR2]] : (!fir.ref) -> !fir.ref -!CHECK-DAG: [[ADDR4:%.*]] = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[C1:%.*]] = arith.constant 4 : index -!CHECK-DAG: [[ADDR5:%.*]] = fir.coordinate_of [[ADDR4]], [[C1]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR6:%.*]] = fir.convert [[ADDR5]] : (!fir.ref) -> !fir.ref> -!CHECK-DAG: [[ADDR7:%.*]] = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[C2:%.*]] = arith.constant 16 : index -!CHECK-DAG: [[ADDR8:%.*]] = fir.coordinate_of [[ADDR7]], [[C2]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR9:%.*]] = fir.convert [[ADDR8]] : (!fir.ref) -> !fir.ref>>> -!CHECK-DAG: [[ADDR10:%.*]] = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[C3:%.*]] = arith.constant 40 : index -!CHECK-DAG: [[ADDR11:%.*]] = fir.coordinate_of [[ADDR10]], [[C3]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR12:%.*]] = fir.convert [[ADDR11]] : (!fir.ref) -> !fir.ref>>>> -!CHECK-DAG: [[ADDR13:%.*]] = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[C4:%.*]] = arith.constant 88 : index -!CHECK-DAG: [[ADDR14:%.*]] = fir.coordinate_of [[ADDR13]], [[C4]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR15:%.*]] = fir.convert [[ADDR14]] : (!fir.ref) -> !fir.ref> -!CHECK-DAG: [[ADDR16:%.*]] = fir.convert [[NEWADDR0]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[C5:%.*]] = arith.constant 93 : index -!CHECK-DAG: [[ADDR17:%.*]] = fir.coordinate_of [[ADDR16]], [[C5]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR18:%.*]] = fir.convert [[ADDR17]] : (!fir.ref) -> !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR3]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR6]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR9]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR12]] : !fir.ref>>>> -!CHECK-DAG: %{{.*}} = fir.convert [[ADDR15]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR18]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> - print *, a, b, c, d, e, f - - !$omp parallel -!CHECK: [[ADDR77:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR78:%.*]] = fir.convert [[ADDR77]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR79:%.*]] = fir.coordinate_of [[ADDR78]], [[C0:%.*]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR80:%.*]] = fir.convert [[ADDR79:%.*]] : (!fir.ref) -> !fir.ref -!CHECK-DAG: [[ADDR81:%.*]] = fir.convert [[ADDR77]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR82:%.*]] = fir.coordinate_of [[ADDR81]], [[C1:%.*]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR83:%.*]] = fir.convert [[ADDR82:%.*]] : (!fir.ref) -> !fir.ref> -!CHECK-DAG: [[ADDR84:%.*]] = fir.convert [[ADDR77]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR85:%.*]] = fir.coordinate_of [[ADDR84]], [[C2:%.*]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR86:%.*]] = fir.convert [[ADDR85:%.*]] : (!fir.ref) -> !fir.ref>>> -!CHECK-DAG: [[ADDR87:%.*]] = fir.convert [[ADDR77]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR88:%.*]] = fir.coordinate_of [[ADDR87]], [[C3:%.*]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR89:%.*]] = fir.convert [[ADDR88:%.*]] : (!fir.ref) -> !fir.ref>>>> -!CHECK-DAG: [[ADDR90:%.*]] = fir.convert [[ADDR77]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR91:%.*]] = fir.coordinate_of [[ADDR90]], [[C4:%.*]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR92:%.*]] = fir.convert [[ADDR91:%.*]] : (!fir.ref) -> !fir.ref> -!CHECK-DAG: [[ADDR93:%.*]] = fir.convert [[ADDR77]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR94:%.*]] = fir.coordinate_of [[ADDR93]], [[C5:%.*]] : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR95:%.*]] = fir.convert [[ADDR94:%.*]] : (!fir.ref) -> !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR80]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR83]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR86]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR89]] : !fir.ref>>>> -!CHECK-DAG: %{{.*}} = fir.convert [[ADDR92]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR95]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> - print *, a, b, c, d, e, f - !$omp end parallel - -!CHECK-DAG: %{{.*}} = fir.load [[ADDR3]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR6]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR9]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR12]] : !fir.ref>>>> -!CHECK-DAG: %{{.*}} = fir.convert [[ADDR15]] : (!fir.ref>) -> !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR18]](%{{.*}}) : (!fir.ref>>, !fir.shape<1>) -> !fir.box>> - print *, a, b, c, d, e, f - - end -end diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-integer-different-kinds.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-integer-different-kinds.f90 deleted file mode 100644 index 39c77406cc22..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-integer-different-kinds.f90 +++ /dev/null @@ -1,67 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for variables with different kind. - -!REQUIRES: shell -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -program test - integer, save :: i - integer(kind=1), save :: i1 - integer(kind=2), save :: i2 - integer(kind=4), save :: i4 - integer(kind=8), save :: i8 - integer(kind=16), save :: i16 - -!CHECK-DAG: [[ADDR0:%.*]] = fir.address_of(@_QFEi) : !fir.ref -!CHECK-DAG: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR1:%.*]] = fir.address_of(@_QFEi1) : !fir.ref -!CHECK-DAG: [[NEWADDR1:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR2:%.*]] = fir.address_of(@_QFEi16) : !fir.ref -!CHECK-DAG: [[NEWADDR2:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR3:%.*]] = fir.address_of(@_QFEi2) : !fir.ref -!CHECK-DAG: [[NEWADDR3:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR4:%.*]] = fir.address_of(@_QFEi4) : !fir.ref -!CHECK-DAG: [[NEWADDR4:%.*]] = omp.threadprivate [[ADDR4]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR5:%.*]] = fir.address_of(@_QFEi8) : !fir.ref -!CHECK-DAG: [[NEWADDR5:%.*]] = omp.threadprivate [[ADDR5]] : !fir.ref -> !fir.ref - !$omp threadprivate(i, i1, i2, i4, i8, i16) - -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR0]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR4]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR5]] : !fir.ref - print *, i, i1, i2, i4, i8, i16 - - !$omp parallel -!CHECK-DAG: [[ADDR39:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR40:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR41:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR42:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR43:%.*]] = omp.threadprivate [[ADDR4]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR44:%.*]] = omp.threadprivate [[ADDR5]] : !fir.ref -> !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR39]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR40]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR41]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR42]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR43]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR44]] : !fir.ref - print *, i, i1, i2, i4, i8, i16 - !$omp end parallel - -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR0]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR4]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR5]] : !fir.ref - print *, i, i1, i2, i4, i8, i16 - -!CHECK-DAG: fir.global internal @_QFEi : i32 { -!CHECK-DAG: fir.global internal @_QFEi1 : i8 { -!CHECK-DAG: fir.global internal @_QFEi16 : i128 { -!CHECK-DAG: fir.global internal @_QFEi2 : i16 { -!CHECK-DAG: fir.global internal @_QFEi4 : i32 { -!CHECK-DAG: fir.global internal @_QFEi8 : i64 { -end diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-non-global.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-non-global.f90 deleted file mode 100644 index b089693b2097..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-non-global.f90 +++ /dev/null @@ -1,91 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for non-character non-SAVEd non-initialized scalars with or without -! allocatable or pointer attribute in main program. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -program test - integer :: x - real :: y - logical :: z - complex :: w - integer, pointer :: a - real, allocatable :: b - -!CHECK-DAG: [[ADDR0:%.*]] = fir.address_of(@_QFEa) : !fir.ref>> -!CHECK-DAG: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR1:%.*]] = fir.address_of(@_QFEb) : !fir.ref>> -!CHECK-DAG: [[NEWADDR1:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR2:%.*]] = fir.address_of(@_QFEw) : !fir.ref> -!CHECK-DAG: [[NEWADDR2:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR3:%.*]] = fir.address_of(@_QFEx) : !fir.ref -!CHECK-DAG: [[NEWADDR3:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR4:%.*]] = fir.address_of(@_QFEy) : !fir.ref -!CHECK-DAG: [[NEWADDR4:%.*]] = omp.threadprivate [[ADDR4]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR5:%.*]] = fir.address_of(@_QFEz) : !fir.ref> -!CHECK-DAG: [[NEWADDR5:%.*]] = omp.threadprivate [[ADDR5]] : !fir.ref> -> !fir.ref> - !$omp threadprivate(x, y, z, w, a, b) - - call sub(a, b) - -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR4]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR5]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR0]] : !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref>> - print *, x, y, z, w, a, b - - !$omp parallel -!CHECK-DAG: [[ADDR68:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR69:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR70:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR71:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR72:%.*]] = omp.threadprivate [[ADDR4]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR73:%.*]] = omp.threadprivate [[ADDR5]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR71]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR72]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR73]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR70]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR68]] : !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR69]] : !fir.ref>> - print *, x, y, z, w, a, b - !$omp end parallel - -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR4]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR5]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR0]] : !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref>> - print *, x, y, z, w, a, b - -!CHECK: return - -!CHECK-DAG: fir.global internal @_QFEa : !fir.box> { -!CHECK-DAG: [[Z0:%.*]] = fir.zero_bits !fir.ptr -!CHECK-DAG: [[E0:%.*]] = fir.embox [[Z0]] : (!fir.ptr) -> !fir.box> -!CHECK-DAG: fir.has_value [[E0]] : !fir.box> -!CHECK-DAG: } -!CHECK-DAG: fir.global internal @_QFEb : !fir.box> { -!CHECK-DAG: [[Z1:%.*]] = fir.zero_bits !fir.heap -!CHECK-DAG: [[E1:%.*]] = fir.embox [[Z1]] : (!fir.heap) -> !fir.box> -!CHECK-DAG: fir.has_value [[E1]] : !fir.box> -!CHECK-DAG: } -!CHECK-DAG: fir.global internal @_QFEw : !fir.complex<4> { -!CHECK-DAG: [[Z2:%.*]] = fir.undefined !fir.complex<4> -!CHECK-DAG: fir.has_value [[Z2]] : !fir.complex<4> -!CHECK-DAG: } -!CHECK-DAG: fir.global internal @_QFEx : i32 { -!CHECK-DAG: [[Z3:%.*]] = fir.undefined i32 -!CHECK-DAG: fir.has_value [[Z3]] : i32 -!CHECK-DAG: } -!CHECK-DAG: fir.global internal @_QFEy : f32 { -!CHECK-DAG: [[Z4:%.*]] = fir.undefined f32 -!CHECK-DAG: fir.has_value [[Z4]] : f32 -!CHECK-DAG: } -!CHECK-DAG: fir.global internal @_QFEz : !fir.logical<4> { -!CHECK-DAG: [[Z5:%.*]] = fir.undefined !fir.logical<4> -!CHECK-DAG: fir.has_value [[Z5]] : !fir.logical<4> -!CHECK-DAG: } -end diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-pointer-allocatable.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-pointer-allocatable.f90 deleted file mode 100644 index fd33c20f9f93..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-pointer-allocatable.f90 +++ /dev/null @@ -1,51 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for allocatable and pointer variables. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -module test - integer, pointer :: x(:), m - real, allocatable :: y(:), n - - !$omp threadprivate(x, y, m, n) - -!CHECK-DAG: fir.global @_QMtestEm : !fir.box> { -!CHECK-DAG: fir.global @_QMtestEn : !fir.box> { -!CHECK-DAG: fir.global @_QMtestEx : !fir.box>> { -!CHECK-DAG: fir.global @_QMtestEy : !fir.box>> { - -contains - subroutine sub() -!CHECK-DAG: [[ADDR0:%.*]] = fir.address_of(@_QMtestEm) : !fir.ref>> -!CHECK-DAG: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR1:%.*]] = fir.address_of(@_QMtestEn) : !fir.ref>> -!CHECK-DAG: [[NEWADDR1:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR2:%.*]] = fir.address_of(@_QMtestEx) : !fir.ref>>> -!CHECK-DAG: [[NEWADDR2:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref>>> -> !fir.ref>>> -!CHECK-DAG: [[ADDR3:%.*]] = fir.address_of(@_QMtestEy) : !fir.ref>>> -!CHECK-DAG: [[NEWADDR3:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref>>> -> !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR0]] : !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref>> - print *, x, y, m, n - - !$omp parallel -!CHECK-DAG: [[ADDR54:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR55:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref>> -> !fir.ref>> -!CHECK-DAG: [[ADDR56:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref>>> -> !fir.ref>>> -!CHECK-DAG: [[ADDR57:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref>>> -> !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR56]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR57]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR54]] : !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR55]] : !fir.ref>> - print *, x, y, m, n - !$omp end parallel - -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref>>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR0]] : !fir.ref>> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref>> - print *, x, y, m, n - end -end diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-real-logical-complex-derivedtype.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-real-logical-complex-derivedtype.f90 deleted file mode 100644 index 749fe5c8bf54..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-real-logical-complex-derivedtype.f90 +++ /dev/null @@ -1,58 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for real, logical, complex, and derived type. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -module test - type my_type - integer :: t_i - real :: t_arr(5) - end type my_type - real :: x - complex :: y - logical :: z - type(my_type) :: t - - !$omp threadprivate(x, y, z, t) - -!CHECK-DAG: fir.global @_QMtestEt : !fir.type<_QMtestTmy_type{t_i:i32,t_arr:!fir.array<5xf32>}> { -!CHECK-DAG: fir.global @_QMtestEx : f32 { -!CHECK-DAG: fir.global @_QMtestEy : !fir.complex<4> { -!CHECK-DAG: fir.global @_QMtestEz : !fir.logical<4> { - -contains - subroutine sub() -!CHECK-DAG: [[ADDR0:%.*]] = fir.address_of(@_QMtestEt) : !fir.ref}>> -!CHECK-DAG: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref}>> -> !fir.ref}>> -!CHECK-DAG: [[ADDR1:%.*]] = fir.address_of(@_QMtestEx) : !fir.ref -!CHECK-DAG: [[NEWADDR1:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR2:%.*]] = fir.address_of(@_QMtestEy) : !fir.ref> -!CHECK-DAG: [[NEWADDR2:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR3:%.*]] = fir.address_of(@_QMtestEz) : !fir.ref> -!CHECK-DAG: [[NEWADDR3:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.coordinate_of [[NEWADDR0]] - print *, x, y, z, t%t_i - - !$omp parallel -!CHECK-DAG: [[ADDR38:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref}>> -> !fir.ref}>> -!CHECK-DAG: [[ADDR39:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR40:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR41:%.*]] = omp.threadprivate [[ADDR3]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR39]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR40]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR41]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.coordinate_of [[ADDR38]] - print *, x, y, z, t%t_i - !$omp end parallel - -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR1]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR2]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[NEWADDR3]] : !fir.ref> -!CHECK-DAG: %{{.*}} = fir.coordinate_of [[NEWADDR0]] - print *, x, y, z, t%t_i - - end -end diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-use-association-2.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-use-association-2.f90 deleted file mode 100644 index 6db5735c21f1..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-use-association-2.f90 +++ /dev/null @@ -1,39 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for threadprivate variable double use in use association. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s -!RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s - -! CHECK-LABEL: fir.global @_QMmEx : i32 -module m - integer :: x - !$omp threadprivate(x) -end - -! CHECK-LABEL: func.func @_QMm2Ptest() { -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QMmEx) : !fir.ref -! CHECK: %[[VAL_1:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref -> !fir.ref -! CHECK: fir.call @_QPbar(%[[VAL_1]]) {{.*}}: (!fir.ref) -> () -! CHECK: return -! CHECK: } -! -! CHECK-LABEL: func.func private @_QMm2FtestPinternal_test() {{.*}} { -! CHECK: %[[VAL_0:.*]] = fir.address_of(@_QMmEx) : !fir.ref -! CHECK: %[[VAL_1:.*]] = omp.threadprivate %[[VAL_0]] : !fir.ref -> !fir.ref -! CHECK: fir.call @_QPbar(%[[VAL_1]]) {{.*}}: (!fir.ref) -> () -! CHECK: return -! CHECK: } - -module m2 - use m - contains - subroutine test() - use m - call bar(x) - contains - subroutine internal_test() - use m - call bar(x) - end - end -end diff --git a/flang/test/Lower/OpenMP/FIR/threadprivate-use-association.f90 b/flang/test/Lower/OpenMP/FIR/threadprivate-use-association.f90 deleted file mode 100644 index 685237430a1c..000000000000 --- a/flang/test/Lower/OpenMP/FIR/threadprivate-use-association.f90 +++ /dev/null @@ -1,74 +0,0 @@ -! This test checks lowering of OpenMP Threadprivate Directive. -! Test for threadprivate variable in use association. - -!RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -!CHECK-DAG: fir.global common @blk_(dense<0> : vector<24xi8>) : !fir.array<24xi8> -!CHECK-DAG: fir.global @_QMtestEy : f32 { - -module test - integer :: x - real :: y, z(5) - common /blk/ x, z - - !$omp threadprivate(y, /blk/) - -contains - subroutine sub() -! CHECK-LABEL: @_QMtestPsub -!CHECK-DAG: [[ADDR0:%.*]] = fir.address_of(@blk_) : !fir.ref> -!CHECK-DAG: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR1:%.*]] = fir.address_of(@_QMtestEy) : !fir.ref -!CHECK-DAG: [[NEWADDR1:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref -> !fir.ref - - !$omp parallel -!CHECK-DAG: [[ADDR2:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR3:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR4:%.*]] = fir.convert [[ADDR2]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR5:%.*]] = fir.coordinate_of [[ADDR4]], %{{.*}} : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR6:%.*]] = fir.convert [[ADDR5:%.*]] : (!fir.ref) -> !fir.ref -!CHECK-DAG: [[ADDR7:%.*]] = fir.convert [[ADDR2]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR8:%.*]] = fir.coordinate_of [[ADDR7]], %{{.*}} : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR9:%.*]] = fir.convert [[ADDR8:%.*]] : (!fir.ref) -> !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR6]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR3]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR9]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> - print *, x, y, z - !$omp end parallel - end -end - -program main - use test - integer :: x1 - real :: z1(5) - common /blk/ x1, z1 - - !$omp threadprivate(/blk/) - - call sub() - -! CHECK-LABEL: @_QQmain() -!CHECK-DAG: [[ADDR0:%.*]] = fir.address_of(@blk_) : !fir.ref> -!CHECK-DAG: [[NEWADDR0:%.*]] = omp.threadprivate [[ADDR0]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR1:%.*]] = fir.address_of(@blk_) : !fir.ref> -!CHECK-DAG: [[NEWADDR1:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR2:%.*]] = fir.address_of(@_QMtestEy) : !fir.ref -!CHECK-DAG: [[NEWADDR2:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref -> !fir.ref - - !$omp parallel -!CHECK-DAG: [[ADDR4:%.*]] = omp.threadprivate [[ADDR1]] : !fir.ref> -> !fir.ref> -!CHECK-DAG: [[ADDR5:%.*]] = omp.threadprivate [[ADDR2]] : !fir.ref -> !fir.ref -!CHECK-DAG: [[ADDR6:%.*]] = fir.convert [[ADDR4]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR7:%.*]] = fir.coordinate_of [[ADDR6]], %{{.*}} : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR8:%.*]] = fir.convert [[ADDR7:%.*]] : (!fir.ref) -> !fir.ref -!CHECK-DAG: [[ADDR9:%.*]] = fir.convert [[ADDR4]] : (!fir.ref>) -> !fir.ref> -!CHECK-DAG: [[ADDR10:%.*]] = fir.coordinate_of [[ADDR9]], %{{.*}} : (!fir.ref>, index) -> !fir.ref -!CHECK-DAG: [[ADDR11:%.*]] = fir.convert [[ADDR10:%.*]] : (!fir.ref) -> !fir.ref> -!CHECK-DAG: %{{.*}} = fir.load [[ADDR8]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.load [[ADDR5]] : !fir.ref -!CHECK-DAG: %{{.*}} = fir.embox [[ADDR11]](%{{.*}}) : (!fir.ref>, !fir.shape<1>) -> !fir.box> - print *, x1, y, z1 - !$omp end parallel - -end diff --git a/flang/test/Lower/OpenMP/FIR/unstructured.f90 b/flang/test/Lower/OpenMP/FIR/unstructured.f90 deleted file mode 100644 index 6d1c9aab1464..000000000000 --- a/flang/test/Lower/OpenMP/FIR/unstructured.f90 +++ /dev/null @@ -1,365 +0,0 @@ -! Test unstructured code adjacent to and inside OpenMP constructs. - -! RUN: bbc %s -fopenmp -emit-fir -hlfir=false -o "-" | FileCheck %s - -! CHECK-LABEL: func @_QPss1{{.*}} { -! CHECK: br ^bb1 -! CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -! CHECK: cond_br %{{[0-9]*}}, ^bb2, ^bb5 -! CHECK: ^bb2: // pred: ^bb1 -! CHECK: cond_br %{{[0-9]*}}, ^bb3, ^bb4 -! CHECK: ^bb4: // pred: ^bb2 -! CHECK: fir.call @_FortranAioBeginExternalListOutput -! CHECK: br ^bb1 -! CHECK: ^bb5: // 2 preds: ^bb1, ^bb3 -! CHECK: omp.master { -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: omp.terminator -! CHECK: } -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: } -subroutine ss1(n) ! unstructured code followed by a structured OpenMP construct - do i = 1, 3 - if (i .eq. n) exit - print*, 'ss1-A', i - enddo - !$omp master - print*, 'ss1-B', i - !$omp end master - print* -end - -! CHECK-LABEL: func @_QPss2{{.*}} { -! CHECK: omp.master { -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: br ^bb1 -! CHECK: ^bb1: // 2 preds: ^bb0, ^bb4 -! CHECK: cond_br %{{[0-9]*}}, ^bb2, ^bb5 -! CHECK: ^bb2: // pred: ^bb1 -! CHECK: cond_br %{{[0-9]*}}, ^bb3, ^bb4 -! CHECK: ^bb3: // pred: ^bb2 -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: br ^bb1 -! CHECK: ^bb5: // 2 preds: ^bb1, ^bb3 -! CHECK: omp.terminator -! CHECK: } -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: } -subroutine ss2(n) ! unstructured OpenMP construct; loop exit inside construct - !$omp master - print*, 'ss2-A', n - do i = 1, 3 - if (i .eq. n) exit - print*, 'ss2-B', i - enddo - !$omp end master - print*, 'ss2-C', i - print* -end - -! CHECK-LABEL: func @_QPss3{{.*}} { -! CHECK: omp.parallel { -! CHECK: %[[ALLOCA_K:.*]] = fir.alloca i32 {bindc_name = "k", pinned} -! CHECK: %[[ALLOCA_1:.*]] = fir.alloca i32 {{{.*}}, pinned} -! CHECK: %[[ALLOCA_2:.*]] = fir.alloca i32 {{{.*}}, pinned} -! CHECK: br ^bb1 -! CHECK: ^bb1: // 2 preds: ^bb0, ^bb3 -! CHECK: cond_br %{{[0-9]*}}, ^bb2, ^bb4 -! CHECK: ^bb2: // pred: ^bb1 -! CHECK: omp.wsloop { -! CHECK: omp.loop_nest (%[[ARG1:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG1]] to %[[ALLOCA_2]] : !fir.ref -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD_1:.*]] = fir.load %[[ALLOCA_2]] : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_1]]) -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.wsloop { -! CHECK: omp.loop_nest (%[[ARG2:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG2]] to %[[ALLOCA_1]] : !fir.ref -! CHECK: br ^bb1 -! CHECK: ^bb2: // 2 preds: ^bb1, ^bb5 -! CHECK: cond_br %{{[0-9]*}}, ^bb3, ^bb6 -! CHECK: ^bb3: // pred: ^bb2 -! CHECK: cond_br %{{[0-9]*}}, ^bb4, ^bb5 -! CHECK: ^bb4: // pred: ^bb3 -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD_2:.*]] = fir.load %[[ALLOCA_K]] : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD_2]]) -! CHECK: br ^bb2 -! CHECK: ^bb6: // 2 preds: ^bb2, ^bb4 -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: br ^bb1 -! CHECK: ^bb4: // pred: ^bb1 -! CHECK: omp.terminator -! CHECK: } -! CHECK: } -subroutine ss3(n) ! nested unstructured OpenMP constructs - !$omp parallel - do i = 1, 3 - !$omp do - do k = 1, 3 - print*, 'ss3-A', k - enddo - !$omp end do - !$omp do - do j = 1, 3 - do k = 1, 3 - if (k .eq. n) exit - print*, 'ss3-B', k - enddo - enddo - !$omp end do - enddo - !$omp end parallel -end - -! CHECK-LABEL: func @_QPss4{{.*}} { -! CHECK: omp.parallel { -! CHECK: %[[ALLOCA:.*]] = fir.alloca i32 {{{.*}}, pinned} -! CHECK: omp.wsloop { -! CHECK: omp.loop_nest (%[[ARG:.*]]) : {{.*}} { -! CHECK: fir.store %[[ARG]] to %[[ALLOCA]] : !fir.ref -! CHECK: %[[COND:.*]] = arith.cmpi eq, %{{.*}}, %{{.*}} -! CHECK: %[[COND_XOR:.*]] = arith.xori %[[COND]], %{{.*}} -! CHECK: fir.if %[[COND_XOR]] { -! CHECK: @_FortranAioBeginExternalListOutput -! CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA]] : !fir.ref -! CHECK: @_FortranAioOutputInteger32(%{{.*}}, %[[LOAD]]) -! CHECK: } else { -! CHECK: } -! CHECK-NEXT: omp.yield -! CHECK-NEXT: } -! CHECK-NEXT: omp.terminator -! CHECK-NEXT: } -! CHECK: omp.terminator -! CHECK-NEXT: } -subroutine ss4(n) ! CYCLE in OpenMP wsloop constructs - !$omp parallel - do i = 1, 3 - !$omp do - do j = 1, 3 - if (j .eq. n) cycle - print*, 'ss4', j - enddo - !$omp end do - enddo - !$omp end parallel -end - -! CHECK-LABEL: func @_QPss5() { -! CHECK: omp.parallel { -! CHECK: omp.wsloop { -! CHECK: omp.loop_nest {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB3:.*]] -! CHECK: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK: ^[[BB3]]: -! CHECK: br ^[[BB2]] -! CHECK: ^[[BB6]]: -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -subroutine ss5() ! EXIT inside OpenMP wsloop (inside parallel) - integer :: x - !$omp parallel private(x) - !$omp do - do j = 1, 3 - x = j * i - do k = 1, 3 - if (k .eq. n) exit - x = k - x = x + k - enddo - x = j - 222 - enddo - !$omp end do - !$omp end parallel -end - -! CHECK-LABEL: func @_QPss6() { -! CHECK: omp.parallel { -! CHECK: br ^[[BB1_OUTER:.*]] -! CHECK: ^[[BB1_OUTER]]: -! CHECK: cond_br %{{.*}}, ^[[BB2_OUTER:.*]], ^[[BB3_OUTER:.*]] -! CHECK: ^[[BB2_OUTER]]: -! CHECK: omp.wsloop { -! CHECK: omp.loop_nest {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK: ^[[BB5]] -! CHECK: br ^[[BB2]] -! CHECK: ^[[BB6]]: -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: br ^[[BB1_OUTER]] -! CHECK: ^[[BB3_OUTER]]: -! CHECK: omp.terminator -! CHECK: } -subroutine ss6() ! EXIT inside OpenMP wsloop in a do loop (inside parallel) - integer :: x - !$omp parallel private(x) - do i = 1, 3 - !$omp do - do j = 1, 3 - x = j * i - do k = 1, 3 - if (k .eq. n) exit - x = k - x = x + k - enddo - x = j - 222 - enddo - !$omp end do - enddo - !$omp end parallel -end - -! CHECK-LABEL: func @_QPss7() { -! CHECK: br ^[[BB1_OUTER:.*]] -! CHECK: ^[[BB1_OUTER]]: -! CHECK: cond_br %{{.*}}, ^[[BB2_OUTER:.*]], ^[[BB3_OUTER:.*]] -! CHECK-NEXT: ^[[BB2_OUTER:.*]]: -! CHECK: omp.parallel { -! CHECK: omp.wsloop { -! CHECK: omp.loop_nest {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK-NEXT: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK-NEXT: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK-NEXT: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK-NEXT: ^[[BB4]]: -! CHECK: br ^[[BB6]] -! CHECK-NEXT: ^[[BB5]]: -! CHECK: br ^[[BB2]] -! CHECK-NEXT: ^[[BB6]]: -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: br ^[[BB1_OUTER]] -! CHECK-NEXT: ^[[BB3_OUTER]]: -! CHECK-NEXT: return -subroutine ss7() ! EXIT inside OpenMP parallel do (inside do loop) - integer :: x - do i = 1, 3 - !$omp parallel do private(x) - do j = 1, 3 - x = j * i - do k = 1, 3 - if (k .eq. n) exit - x = k - x = x + k - enddo - enddo - !$omp end parallel do - enddo -end - -! CHECK-LABEL: func @_QPss8() { -! CHECK: omp.parallel { -! CHECK: omp.wsloop { -! CHECK: omp.loop_nest {{.*}} { -! CHECK: br ^[[BB1:.*]] -! CHECK-NEXT: ^[[BB1]]: -! CHECK: br ^[[BB2:.*]] -! CHECK: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB6:.*]] -! CHECK: ^[[BB3]]: -! CHECK: cond_br %{{.*}}, ^[[BB4:.*]], ^[[BB5:.*]] -! CHECK: ^[[BB4]]: -! CHECK-NEXT: br ^[[BB6]] -! CHECK: ^[[BB5]]: -! CHECK: br ^[[BB2]] -! CHECK-NEXT: ^[[BB6]]: -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -subroutine ss8() ! EXIT inside OpenMP parallel do - integer :: x - !$omp parallel do private(x) - do j = 1, 3 - x = j * i - do k = 1, 3 - if (k .eq. n) exit - x = k - x = x + k - enddo - enddo - !$omp end parallel do -end - -! CHECK-LABEL: func @_QPss9() { -! CHECK: omp.parallel { -! CHECK-NEXT: omp.parallel { -! CHECK: br ^[[BB1:.*]] -! CHECK: ^[[BB1]]: -! CHECK: cond_br %{{.*}}, ^[[BB2:.*]], ^[[BB5:.*]] -! CHECK-NEXT: ^[[BB2]]: -! CHECK: cond_br %{{.*}}, ^[[BB3:.*]], ^[[BB4:.*]] -! CHECK-NEXT: ^[[BB3]]: -! CHECK-NEXT: br ^[[BB5]] -! CHECK-NEXT: ^[[BB4]]: -! CHECK: br ^[[BB1]] -! CHECK-NEXT: ^[[BB5]]: -! CHECK: omp.terminator -! CHECK-NEXT: } -! CHECK: omp.terminator -! CHECK-NEXT } -! CHECK: } -subroutine ss9() ! EXIT inside OpenMP parallel (inside parallel) - integer :: x - !$omp parallel - !$omp parallel private(x) - do k = 1, 3 - if (k .eq. n) exit - x = k - x = x + k - end do - !$omp end parallel - !$omp end parallel -end - -! CHECK-LABEL: func @_QQmain -program p - call ss1(2) - call ss2(2) - call ss3(2) - call ss4(2) - call ss5() - call ss6() - call ss7() - call ss8() - call ss9() -end diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 deleted file mode 100644 index e4b85fb44776..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-chunks.f90 +++ /dev/null @@ -1,84 +0,0 @@ -! This test checks that chunk size is passed correctly when lowering of -! OpenMP DO Directive(Worksharing) with chunk size - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -program wsloop - integer :: i - integer :: chunk - -! CHECK-LABEL: func.func @_QQmain() attributes {fir.bindc_name = "wsloop"} { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "chunk", uniq_name = "_QFEchunk"} - -!$OMP DO SCHEDULE(static, 4) - -do i=1, 9 - print*, i - -! CHECK: %[[VAL_2:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_3:.*]] = arith.constant 9 : i32 -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 4 : i32 -! CHECK: omp.wsloop schedule(static = %[[VAL_5]] : i32) nowait { -! CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[VAL_2]]) to (%[[VAL_3]]) inclusive step (%[[VAL_4]]) { -! CHECK: fir.store %[[ARG0]] to %[[STORE_IV:.*]] : !fir.ref -! CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]] : !fir.ref -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } - -end do -!$OMP END DO NOWAIT -!$OMP DO SCHEDULE(static, 2+2) - -do i=1, 9 - print*, i*2 - -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_15:.*]] = arith.constant 9 : i32 -! CHECK: %[[VAL_16:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_17:.*]] = arith.constant 4 : i32 -! CHECK: omp.wsloop schedule(static = %[[VAL_17]] : i32) nowait { -! CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i32 = (%[[VAL_14]]) to (%[[VAL_15]]) inclusive step (%[[VAL_16]]) { -! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref -! CHECK: %[[VAL_24:.*]] = arith.constant 2 : i32 -! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.muli %[[VAL_24]], %[[LOAD_IV1]] : i32 -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_25]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } - -end do -!$OMP END DO NOWAIT -chunk = 6 -!$OMP DO SCHEDULE(static, chunk) - -do i=1, 9 - print*, i*3 -end do -!$OMP END DO NOWAIT -! CHECK: %[[VAL_28:.*]] = arith.constant 6 : i32 -! CHECK: fir.store %[[VAL_28]] to %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_29:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_30:.*]] = arith.constant 9 : i32 -! CHECK: %[[VAL_31:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_32:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: omp.wsloop schedule(static = %[[VAL_32]] : i32) nowait { -! CHECK-NEXT: omp.loop_nest (%[[ARG2:.*]]) : i32 = (%[[VAL_29]]) to (%[[VAL_30]]) inclusive step (%[[VAL_31]]) { -! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]] : !fir.ref -! CHECK: %[[VAL_39:.*]] = arith.constant 3 : i32 -! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]] : !fir.ref -! CHECK: %[[VAL_40:.*]] = arith.muli %[[VAL_39]], %[[LOAD_IV2]] : i32 -! CHECK: {{.*}} = fir.call @_FortranAioOutputInteger32({{.*}}, %[[VAL_40]]) {{.*}}: (!fir.ref, i32) -> i1 -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -end diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 deleted file mode 100644 index a2ba3ebfe196..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-collapse.f90 +++ /dev/null @@ -1,66 +0,0 @@ -! This test checks lowering of OpenMP DO Directive(Worksharing) with collapse. - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -program wsloop_collapse - integer :: i, j, k - integer :: a, b, c - integer :: x -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "a", uniq_name = "_QFEa"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "b", uniq_name = "_QFEb"} -! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "c", uniq_name = "_QFEc"} -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFEi"} -! CHECK: %[[VAL_4:.*]] = fir.alloca i32 {bindc_name = "j", uniq_name = "_QFEj"} -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {bindc_name = "k", uniq_name = "_QFEk"} -! CHECK: %[[VAL_6:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFEx"} - a=3 -! CHECK: %[[VAL_7:.*]] = arith.constant 3 : i32 -! CHECK: fir.store %[[VAL_7]] to %[[VAL_0]] : !fir.ref - b=2 -! CHECK: %[[VAL_8:.*]] = arith.constant 2 : i32 -! CHECK: fir.store %[[VAL_8]] to %[[VAL_1]] : !fir.ref - c=5 -! CHECK: %[[VAL_9:.*]] = arith.constant 5 : i32 -! CHECK: fir.store %[[VAL_9]] to %[[VAL_2]] : !fir.ref - x=0 -! CHECK: %[[VAL_10:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_10]] to %[[VAL_6]] : !fir.ref - - !$omp do collapse(3) -! CHECK: %[[VAL_20:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_0]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_23:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_1]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_26:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_27:.*]] = fir.load %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_28:.*]] = arith.constant 1 : i32 - do i = 1, a - do j= 1, b - do k = 1, c -! CHECK: omp.wsloop { -! CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]], %[[ARG1:.*]], %[[ARG2:.*]]) : i32 = (%[[VAL_20]], %[[VAL_23]], %[[VAL_26]]) to (%[[VAL_21]], %[[VAL_24]], %[[VAL_27]]) inclusive step (%[[VAL_22]], %[[VAL_25]], %[[VAL_28]]) { -! CHECK: fir.store %[[ARG0]] to %[[STORE_IV0:.*]] : !fir.ref -! CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref -! CHECK: fir.store %[[ARG2]] to %[[STORE_IV2:.*]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_6]] : !fir.ref -! CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = arith.addi %[[VAL_12]], %[[LOAD_IV0]] : i32 -! CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref -! CHECK: %[[VAL_14:.*]] = arith.addi %[[VAL_13]], %[[LOAD_IV1]] : i32 -! CHECK: %[[LOAD_IV2:.*]] = fir.load %[[STORE_IV2]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = arith.addi %[[VAL_14]], %[[LOAD_IV2]] : i32 -! CHECK: fir.store %[[VAL_15]] to %[[VAL_6]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } - x = x + i + j + k - end do - end do - end do - !$omp end do -! CHECK: return -! CHECK: } -end program wsloop_collapse diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 deleted file mode 100644 index 941885bdb1e3..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-monotonic.f90 +++ /dev/null @@ -1,38 +0,0 @@ -! This test checks lowering of OpenMP DO Directive (Worksharing) with -! monotonic schedule modifier. - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -program wsloop_dynamic - integer :: i -!CHECK-LABEL: func @_QQmain() - -!$OMP PARALLEL -!CHECK: omp.parallel { - -!$OMP DO SCHEDULE(monotonic:dynamic) -!CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} -!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 -!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 -!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(dynamic, monotonic) nowait { -!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { -!CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - - do i=1, 9 - print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 - end do -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -!$OMP END DO NOWAIT -!$OMP END PARALLEL -end diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 deleted file mode 100644 index 96a3e71f34b1..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-nonmonotonic.f90 +++ /dev/null @@ -1,39 +0,0 @@ -! This test checks lowering of OpenMP DO Directive(Worksharing) with -! non-monotonic schedule modifier. - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -program wsloop_dynamic - integer :: i -!CHECK-LABEL: func @_QQmain() - - -!$OMP PARALLEL -!CHECK: omp.parallel { - -!$OMP DO SCHEDULE(nonmonotonic:dynamic) -!CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} -!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 -!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 -!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(dynamic, nonmonotonic) nowait { -!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) -!CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref - - do i=1, 9 - print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 - end do -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -!$OMP END DO NOWAIT -!$OMP END PARALLEL -end diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 deleted file mode 100644 index fec027608d99..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-ordered.f90 +++ /dev/null @@ -1,46 +0,0 @@ -! This test checks lowering of worksharing-loop construct with ordered clause. - -! RUN: bbc -fopenmp -emit-fir %s -o - | FileCheck %s - -! This checks lowering ordered clause specified without parameter -subroutine wsloop_ordered_no_para() - integer :: a(10), i - -! CHECK: omp.wsloop ordered(0) { -! CHECK-NEXT: omp.loop_nest (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } - - !$omp do ordered - do i = 2, 10 - !$omp ordered - a(i) = a(i-1) + 1 - !$omp end ordered - end do - !$omp end do - -end - -! This checks lowering ordered clause specified with a parameter -subroutine wsloop_ordered_with_para() - integer :: a(10), i - -! CHECK: func @_QPwsloop_ordered_with_para() { -! CHECK: omp.wsloop ordered(1) { -! CHECK-NEXT: omp.loop_nest (%{{.*}}) : i32 = (%{{.*}}) to (%{{.*}}) inclusive step (%{{.*}}) { -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } - - !$omp do ordered(1) - do i = 2, 10 - !!$omp ordered depend(sink: i-1) - a(i) = a(i-1) + 1 - !!$omp ordered depend(source) - end do - !$omp end do - -end diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 deleted file mode 100644 index b6dfec09007e..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add-byref.f90 +++ /dev/null @@ -1,413 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir --force-byref-reduction %s -o - | FileCheck %s -! NOTE: Assertions have been autogenerated by utils/generate-test-checks.py - -! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_f64 : !fir.ref -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref): -! CHECK: %[[C0_1:.*]] = arith.constant 0.000000e+00 : f64 -! CHECK: %[[REF:.*]] = fir.alloca f64 -! CHECK: fir.store %[[C0_1]] to %[[REF]] : !fir.ref -! CHECK: omp.yield(%[[REF]] : !fir.ref) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[RES:.*]] = arith.addf %[[LD0]], %[[LD1]] fastmath : f64 -! CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -! CHECK: omp.yield(%[[ARG0]] : !fir.ref) -! CHECK: } - -! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_i64 : !fir.ref -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref): -! CHECK: %[[C0_1:.*]] = arith.constant 0 : i64 -! CHECK: %[[REF:.*]] = fir.alloca i64 -! CHECK: fir.store %[[C0_1]] to %[[REF]] : !fir.ref -! CHECK: omp.yield(%[[REF]] : !fir.ref) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[RES:.*]] = arith.addi %[[LD0]], %[[LD1]] : i64 -! CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -! CHECK: omp.yield(%[[ARG0]] : !fir.ref) -! CHECK: } - -! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_f32 : !fir.ref -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref): -! CHECK: %[[C0_1:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: %[[REF:.*]] = fir.alloca f32 -! CHECK: fir.store %[[C0_1]] to %[[REF]] : !fir.ref -! CHECK: omp.yield(%[[REF]] : !fir.ref) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[RES:.*]] = arith.addf %[[LD0]], %[[LD1]] fastmath : f32 -! CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -! CHECK: omp.yield(%[[ARG0]] : !fir.ref) -! CHECK: } - -! CHECK-LABEL: omp.declare_reduction @add_reduction_byref_i32 : !fir.ref -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref): -! CHECK: %[[C0_1:.*]] = arith.constant 0 : i32 -! CHECK: %[[REF:.*]] = fir.alloca i32 -! CHECK: fir.store %[[C0_1]] to %[[REF]] : !fir.ref -! CHECK: omp.yield(%[[REF]] : !fir.ref) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[RES:.*]] = arith.addi %[[LD0]], %[[LD1]] : i32 -! CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -! CHECK: omp.yield(%[[ARG0]] : !fir.ref) -! CHECK: } - -! CHECK-LABEL: func.func @_QPsimple_int_reduction() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_int_reductionEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFsimple_int_reductionEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_int_reduction - integer :: x - x = 0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = x + i - end do - !$omp end do - !$omp end parallel -end subroutine - - -! CHECK-LABEL: func.func @_QPsimple_real_reduction() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_real_reductionEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFsimple_real_reductionEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i32) -> f32 -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_9]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_real_reduction - real :: x - x = 0.0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = x + i - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_int_reduction_switch_order() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_int_reduction_switch_orderEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFsimple_int_reduction_switch_orderEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_int_reduction_switch_order - integer :: x - x = 0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = i + x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_real_reduction_switch_order() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_real_reduction_switch_orderEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFsimple_real_reduction_switch_orderEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> f32 -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_10]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_real_reduction_switch_order - real :: x - x = 0.0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = i + x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_int_reductions_same_type() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_int_reductions_same_typeEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_int_reductions_same_typeEx"} -! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFmultiple_int_reductions_same_typeEy"} -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFmultiple_int_reductions_same_typeEz"} -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_4]] to %[[VAL_1]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_5]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_6]] to %[[VAL_3]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_7:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_byref_i32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_15]], %[[VAL_16]] : i32 -! CHECK: fir.store %[[VAL_17]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = arith.addi %[[VAL_21]], %[[VAL_22]] : i32 -! CHECK: fir.store %[[VAL_23]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine multiple_int_reductions_same_type - integer :: x,y,z - x = 0 - y = 0 - z = 0 - !$omp parallel - !$omp do reduction(+:x,y,z) - do i=1, 100 - x = x + i - y = y + i - z = z + i - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_real_reductions_same_type() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_real_reductions_same_typeEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFmultiple_real_reductions_same_typeEx"} -! CHECK: %[[VAL_2:.*]] = fir.alloca f32 {bindc_name = "y", uniq_name = "_QFmultiple_real_reductions_same_typeEy"} -! CHECK: %[[VAL_3:.*]] = fir.alloca f32 {bindc_name = "z", uniq_name = "_QFmultiple_real_reductions_same_typeEz"} -! CHECK: %[[VAL_4:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_4]] to %[[VAL_1]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_5]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_6]] to %[[VAL_3]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_7:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_f32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]] : (i32) -> f32 -! CHECK: %[[VAL_18:.*]] = arith.addf %[[VAL_15]], %[[VAL_17]] fastmath : f32 -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> f32 -! CHECK: %[[VAL_22:.*]] = arith.addf %[[VAL_19]], %[[VAL_21]] fastmath : f32 -! CHECK: fir.store %[[VAL_22]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: fir.store %[[VAL_26]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine multiple_real_reductions_same_type - real :: x,y,z - x = 0.0 - y = 0.0 - z = 0.0 - !$omp parallel - !$omp do reduction(+:x,y,z) - do i=1, 100 - x = x + i - y = y + i - z = z + i - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_reductions_different_type() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_reductions_different_typeEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f64 {bindc_name = "w", uniq_name = "_QFmultiple_reductions_different_typeEw"} -! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_reductions_different_typeEx"} -! CHECK: %[[VAL_3:.*]] = fir.alloca i64 {bindc_name = "y", uniq_name = "_QFmultiple_reductions_different_typeEy"} -! CHECK: %[[VAL_4:.*]] = fir.alloca f32 {bindc_name = "z", uniq_name = "_QFmultiple_reductions_different_typeEz"} -! CHECK: %[[VAL_5:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_5]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i64 -! CHECK: fir.store %[[VAL_6]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_7:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_7]] to %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_8:.*]] = arith.constant 0.000000e+00 : f64 -! CHECK: fir.store %[[VAL_8]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_9:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_11:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@add_reduction_byref_i32 %[[VAL_2]] -> %[[VAL_13:.*]] : !fir.ref, @add_reduction_byref_i64 %[[VAL_3]] -> %[[VAL_14:.*]] : !fir.ref, @add_reduction_byref_f32 %[[VAL_4]] -> %[[VAL_15:.*]] : !fir.ref, @add_reduction_byref_f64 %[[VAL_1]] -> %[[VAL_16:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_17:.*]]) : i32 = (%[[VAL_10]]) to (%[[VAL_11]]) inclusive step (%[[VAL_12]]) { -! CHECK: fir.store %[[VAL_17]] to %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_22]] : (i32) -> i64 -! CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_21]], %[[VAL_23]] : i64 -! CHECK: fir.store %[[VAL_24]] to %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_26]] : (i32) -> f32 -! CHECK: %[[VAL_28:.*]] = arith.addf %[[VAL_25]], %[[VAL_27]] fastmath : f32 -! CHECK: fir.store %[[VAL_28]] to %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_16]] : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.convert %[[VAL_30]] : (i32) -> f64 -! CHECK: %[[VAL_32:.*]] = arith.addf %[[VAL_29]], %[[VAL_31]] fastmath : f64 -! CHECK: fir.store %[[VAL_32]] to %[[VAL_16]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - - -subroutine multiple_reductions_different_type - integer :: x - integer(kind=8) :: y - real :: z - real(kind=8) :: w - x = 0 - y = 0 - z = 0.0 - w = 0.0 - !$omp parallel - !$omp do reduction(+:x,y,z,w) - do i=1, 100 - x = x + i - y = y + i - z = z + i - w = w + i - end do - !$omp end do - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 deleted file mode 100644 index e0b9330b1a6d..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-add.f90 +++ /dev/null @@ -1,388 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -! CHECK-LABEL: omp.declare_reduction @add_reduction_f64 : f64 init { -! CHECK: ^bb0(%[[VAL_0:.*]]: f64): -! CHECK: %[[VAL_1:.*]] = arith.constant 0.000000e+00 : f64 -! CHECK: omp.yield(%[[VAL_1]] : f64) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[VAL_0:.*]]: f64, %[[VAL_1:.*]]: f64): -! CHECK: %[[VAL_2:.*]] = arith.addf %[[VAL_0]], %[[VAL_1]] fastmath : f64 -! CHECK: omp.yield(%[[VAL_2]] : f64) -! CHECK: } - -! CHECK-LABEL: omp.declare_reduction @add_reduction_i64 : i64 init { -! CHECK: ^bb0(%[[VAL_0:.*]]: i64): -! CHECK: %[[VAL_1:.*]] = arith.constant 0 : i64 -! CHECK: omp.yield(%[[VAL_1]] : i64) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[VAL_0:.*]]: i64, %[[VAL_1:.*]]: i64): -! CHECK: %[[VAL_2:.*]] = arith.addi %[[VAL_0]], %[[VAL_1]] : i64 -! CHECK: omp.yield(%[[VAL_2]] : i64) -! CHECK: } - -! CHECK-LABEL: omp.declare_reduction @add_reduction_f32 : f32 init { -! CHECK: ^bb0(%[[VAL_0:.*]]: f32): -! CHECK: %[[VAL_1:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: omp.yield(%[[VAL_1]] : f32) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[VAL_0:.*]]: f32, %[[VAL_1:.*]]: f32): -! CHECK: %[[VAL_2:.*]] = arith.addf %[[VAL_0]], %[[VAL_1]] fastmath : f32 -! CHECK: omp.yield(%[[VAL_2]] : f32) -! CHECK: } - -! CHECK-LABEL: omp.declare_reduction @add_reduction_i32 : i32 init { -! CHECK: ^bb0(%[[VAL_0:.*]]: i32): -! CHECK: %[[VAL_1:.*]] = arith.constant 0 : i32 -! CHECK: omp.yield(%[[VAL_1]] : i32) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[VAL_0:.*]]: i32, %[[VAL_1:.*]]: i32): -! CHECK: %[[VAL_2:.*]] = arith.addi %[[VAL_0]], %[[VAL_1]] : i32 -! CHECK: omp.yield(%[[VAL_2]] : i32) -! CHECK: } - -! CHECK-LABEL: func.func @_QPsimple_int_reduction() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_int_reductionEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFsimple_int_reductionEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_int_reduction - integer :: x - x = 0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = x + i - end do - !$omp end do - !$omp end parallel -end subroutine - - -! CHECK-LABEL: func.func @_QPsimple_real_reduction() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_real_reductionEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFsimple_real_reductionEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_10]] : (i32) -> f32 -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_9]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_real_reduction - real :: x - x = 0.0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = x + i - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_int_reduction_switch_order() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_int_reduction_switch_orderEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFsimple_int_reduction_switch_orderEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = arith.addi %[[VAL_9]], %[[VAL_10]] : i32 -! CHECK: fir.store %[[VAL_11]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_int_reduction_switch_order - integer :: x - x = 0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = i + x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_real_reduction_switch_order() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_real_reduction_switch_orderEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFsimple_real_reduction_switch_orderEx"} -! CHECK: %[[VAL_2:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_2]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_4:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_5:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_7:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_8:.*]]) : i32 = (%[[VAL_4]]) to (%[[VAL_5]]) inclusive step (%[[VAL_6]]) { -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i32) -> f32 -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = arith.addf %[[VAL_10]], %[[VAL_11]] fastmath : f32 -! CHECK: fir.store %[[VAL_12]] to %[[VAL_7]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine simple_real_reduction_switch_order - real :: x - x = 0.0 - !$omp parallel - !$omp do reduction(+:x) - do i=1, 100 - x = i + x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_int_reductions_same_type() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_int_reductions_same_typeEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_int_reductions_same_typeEx"} -! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "y", uniq_name = "_QFmultiple_int_reductions_same_typeEy"} -! CHECK: %[[VAL_3:.*]] = fir.alloca i32 {bindc_name = "z", uniq_name = "_QFmultiple_int_reductions_same_typeEz"} -! CHECK: %[[VAL_4:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_4]] to %[[VAL_1]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_5]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_6]] to %[[VAL_3]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_7:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_i32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = arith.addi %[[VAL_15]], %[[VAL_16]] : i32 -! CHECK: fir.store %[[VAL_17]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = arith.addi %[[VAL_21]], %[[VAL_22]] : i32 -! CHECK: fir.store %[[VAL_23]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine multiple_int_reductions_same_type - integer :: x,y,z - x = 0 - y = 0 - z = 0 - !$omp parallel - !$omp do reduction(+:x,y,z) - do i=1, 100 - x = x + i - y = y + i - z = z + i - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_real_reductions_same_type() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_real_reductions_same_typeEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFmultiple_real_reductions_same_typeEx"} -! CHECK: %[[VAL_2:.*]] = fir.alloca f32 {bindc_name = "y", uniq_name = "_QFmultiple_real_reductions_same_typeEy"} -! CHECK: %[[VAL_3:.*]] = fir.alloca f32 {bindc_name = "z", uniq_name = "_QFmultiple_real_reductions_same_typeEz"} -! CHECK: %[[VAL_4:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_4]] to %[[VAL_1]] : !fir.ref -! CHECK: %[[VAL_5:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_5]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_6]] to %[[VAL_3]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_7:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_9:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_f32 %[[VAL_1]] -> %[[VAL_11:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_2]] -> %[[VAL_12:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_3]] -> %[[VAL_13:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_14:.*]]) : i32 = (%[[VAL_8]]) to (%[[VAL_9]]) inclusive step (%[[VAL_10]]) { -! CHECK: fir.store %[[VAL_14]] to %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_15:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_17:.*]] = fir.convert %[[VAL_16]] : (i32) -> f32 -! CHECK: %[[VAL_18:.*]] = arith.addf %[[VAL_15]], %[[VAL_17]] fastmath : f32 -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> f32 -! CHECK: %[[VAL_22:.*]] = arith.addf %[[VAL_19]], %[[VAL_21]] fastmath : f32 -! CHECK: fir.store %[[VAL_22]] to %[[VAL_12]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_24:.*]] = fir.load %[[VAL_7]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i32) -> f32 -! CHECK: %[[VAL_26:.*]] = arith.addf %[[VAL_23]], %[[VAL_25]] fastmath : f32 -! CHECK: fir.store %[[VAL_26]] to %[[VAL_13]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - -subroutine multiple_real_reductions_same_type - real :: x,y,z - x = 0.0 - y = 0.0 - z = 0.0 - !$omp parallel - !$omp do reduction(+:x,y,z) - do i=1, 100 - x = x + i - y = y + i - z = z + i - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_reductions_different_type() { -! CHECK: %[[VAL_0:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_reductions_different_typeEi"} -! CHECK: %[[VAL_1:.*]] = fir.alloca f64 {bindc_name = "w", uniq_name = "_QFmultiple_reductions_different_typeEw"} -! CHECK: %[[VAL_2:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFmultiple_reductions_different_typeEx"} -! CHECK: %[[VAL_3:.*]] = fir.alloca i64 {bindc_name = "y", uniq_name = "_QFmultiple_reductions_different_typeEy"} -! CHECK: %[[VAL_4:.*]] = fir.alloca f32 {bindc_name = "z", uniq_name = "_QFmultiple_reductions_different_typeEz"} -! CHECK: %[[VAL_5:.*]] = arith.constant 0 : i32 -! CHECK: fir.store %[[VAL_5]] to %[[VAL_2]] : !fir.ref -! CHECK: %[[VAL_6:.*]] = arith.constant 0 : i64 -! CHECK: fir.store %[[VAL_6]] to %[[VAL_3]] : !fir.ref -! CHECK: %[[VAL_7:.*]] = arith.constant 0.000000e+00 : f32 -! CHECK: fir.store %[[VAL_7]] to %[[VAL_4]] : !fir.ref -! CHECK: %[[VAL_8:.*]] = arith.constant 0.000000e+00 : f64 -! CHECK: fir.store %[[VAL_8]] to %[[VAL_1]] : !fir.ref -! CHECK: omp.parallel { -! CHECK: %[[VAL_9:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_10:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_11:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@add_reduction_i32 %[[VAL_2]] -> %[[VAL_13:.*]] : !fir.ref, @add_reduction_i64 %[[VAL_3]] -> %[[VAL_14:.*]] : !fir.ref, @add_reduction_f32 %[[VAL_4]] -> %[[VAL_15:.*]] : !fir.ref, @add_reduction_f64 %[[VAL_1]] -> %[[VAL_16:.*]] : !fir.ref) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_17:.*]]) : i32 = (%[[VAL_10]]) to (%[[VAL_11]]) inclusive step (%[[VAL_12]]) { -! CHECK: fir.store %[[VAL_17]] to %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_18:.*]] = fir.load %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_20:.*]] = arith.addi %[[VAL_18]], %[[VAL_19]] : i32 -! CHECK: fir.store %[[VAL_20]] to %[[VAL_13]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.load %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_22:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_23:.*]] = fir.convert %[[VAL_22]] : (i32) -> i64 -! CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_21]], %[[VAL_23]] : i64 -! CHECK: fir.store %[[VAL_24]] to %[[VAL_14]] : !fir.ref -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_26:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_26]] : (i32) -> f32 -! CHECK: %[[VAL_28:.*]] = arith.addf %[[VAL_25]], %[[VAL_27]] fastmath : f32 -! CHECK: fir.store %[[VAL_28]] to %[[VAL_15]] : !fir.ref -! CHECK: %[[VAL_29:.*]] = fir.load %[[VAL_16]] : !fir.ref -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_9]] : !fir.ref -! CHECK: %[[VAL_31:.*]] = fir.convert %[[VAL_30]] : (i32) -> f64 -! CHECK: %[[VAL_32:.*]] = arith.addf %[[VAL_29]], %[[VAL_31]] fastmath : f64 -! CHECK: fir.store %[[VAL_32]] to %[[VAL_16]] : !fir.ref -! CHECK: omp.yield -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: omp.terminator -! CHECK: } -! CHECK: return -! CHECK: } - - -subroutine multiple_reductions_different_type - integer :: x - integer(kind=8) :: y - real :: z - real(kind=8) :: w - x = 0 - y = 0 - z = 0.0 - w = 0.0 - !$omp parallel - !$omp do reduction(+:x,y,z,w) - do i=1, 100 - x = x + i - y = y + i - z = z + i - w = w + i - end do - !$omp end do - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 deleted file mode 100644 index b25ab84f60fe..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand-byref.f90 +++ /dev/null @@ -1,48 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir --force-byref-reduction %s -o - | FileCheck %s - -!CHECK-LABEL: omp.declare_reduction @iand_byref_i32 : !fir.ref -!CHECK-SAME: init { -!CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref): -!CHECK: %[[C0_1:.*]] = arith.constant -1 : i32 -!CHECK: %[[REF:.*]] = fir.alloca i32 -!CHECK: fir.store %[[C0_1]] to %[[REF]] : !fir.ref -!CHECK: omp.yield(%[[REF]] : !fir.ref) - -!CHECK-LABEL: } combiner { -!CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -!CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -!CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK: %[[RES:.*]] = arith.andi %[[LD0]], %[[LD1]] : i32 -!CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -!CHECK: omp.yield(%[[ARG0]] : !fir.ref) -!CHECK: } - - -!CHECK-LABEL: @_QPreduction_iand -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iandEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@iand_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.andi %[[LPRV]], %[[Y_I]] : i32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_iand(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(iand:x) - do i=1, 100 - x = iand(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 deleted file mode 100644 index dfc140d7d5f6..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-iand.f90 +++ /dev/null @@ -1,38 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -!CHECK: omp.declare_reduction @[[IAND_DECLARE_I:.*]] : i32 init { -!CHECK: %[[ZERO_VAL_I:.*]] = arith.constant -1 : i32 -!CHECK: omp.yield(%[[ZERO_VAL_I]] : i32) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0_I:.*]]: i32, %[[ARG1_I:.*]]: i32): -!CHECK: %[[IAND_VAL_I:.*]] = arith.andi %[[ARG0_I]], %[[ARG1_I]] : i32 -!CHECK: omp.yield(%[[IAND_VAL_I]] : i32) - -!CHECK-LABEL: @_QPreduction_iand -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iandEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[IAND_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.andi %[[LPRV]], %[[Y_I]] : i32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_iand(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(iand:x) - do i=1, 100 - x = iand(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 deleted file mode 100644 index 56eb087bae5a..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor-byref.f90 +++ /dev/null @@ -1,47 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -mmlir --force-byref-reduction -fopenmp %s -o - | FileCheck %s - -! CHECK-LABEL: omp.declare_reduction @ieor_byref_i32 : !fir.ref -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref): -! CHECK: %[[C0_1:.*]] = arith.constant 0 : i32 -! CHECK: %[[REF:.*]] = fir.alloca i32 -! CHECK: fir.store %[[C0_1]] to %[[REF]] : !fir.ref -! CHECK: omp.yield(%[[REF]] : !fir.ref) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[RES:.*]] = arith.xori %[[LD0]], %[[LD1]] : i32 -! CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -! CHECK: omp.yield(%[[ARG0]] : !fir.ref) -! CHECK: } - -!CHECK-LABEL: @_QPreduction_ieor -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_ieorEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@ieor_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.xori %[[LPRV]], %[[Y_I]] : i32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_ieor(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(ieor:x) - do i=1, 100 - x = ieor(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 deleted file mode 100644 index 1ddf82b828cb..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ieor.f90 +++ /dev/null @@ -1,38 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -!CHECK: omp.declare_reduction @[[IEOR_DECLARE_I:.*]] : i32 init { -!CHECK: %[[ZERO_VAL_I:.*]] = arith.constant 0 : i32 -!CHECK: omp.yield(%[[ZERO_VAL_I]] : i32) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0_I:.*]]: i32, %[[ARG1_I:.*]]: i32): -!CHECK: %[[IEOR_VAL_I:.*]] = arith.xori %[[ARG0_I]], %[[ARG1_I]] : i32 -!CHECK: omp.yield(%[[IEOR_VAL_I]] : i32) - -!CHECK-LABEL: @_QPreduction_ieor -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_ieorEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[IEOR_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.xori %[[LPRV]], %[[Y_I]] : i32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_ieor(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(ieor:x) - do i=1, 100 - x = ieor(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 deleted file mode 100644 index e761d24cd303..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior-byref.f90 +++ /dev/null @@ -1,47 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir --force-byref-reduction %s -o - | FileCheck %s - -! CHECK-LABEL: omp.declare_reduction @ior_byref_i32 : !fir.ref -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref): -! CHECK: %[[C0_1:.*]] = arith.constant 0 : i32 -! CHECK: %[[REF:.*]] = fir.alloca i32 -! CHECK: fir.store %[[C0_1]] to %[[REF]] : !fir.ref -! CHECK: omp.yield(%[[REF]] : !fir.ref) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -! CHECK: %[[RES:.*]] = arith.ori %[[LD0]], %[[LD1]] : i32 -! CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -! CHECK: omp.yield(%[[ARG0]] : !fir.ref) -! CHECK: } - -!CHECK-LABEL: @_QPreduction_ior -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iorEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@ior_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.ori %[[LPRV]], %[[Y_I]] : i32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_ior(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(ior:x) - do i=1, 100 - x = ior(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 deleted file mode 100644 index 148dbc909bab..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-ior.f90 +++ /dev/null @@ -1,38 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -!CHECK: omp.declare_reduction @[[IOR_DECLARE_I:.*]] : i32 init { -!CHECK: %[[ZERO_VAL_I:.*]] = arith.constant 0 : i32 -!CHECK: omp.yield(%[[ZERO_VAL_I]] : i32) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0_I:.*]]: i32, %[[ARG1_I:.*]]: i32): -!CHECK: %[[IOR_VAL_I:.*]] = arith.ori %[[ARG0_I]], %[[ARG1_I]] : i32 -!CHECK: omp.yield(%[[IOR_VAL_I]] : i32) - -!CHECK-LABEL: @_QPreduction_ior -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_iorEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[IOR_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.ori %[[LPRV]], %[[Y_I]] : i32 -!CHECK: fir.store %[[RES]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_ior(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(ior:x) - do i=1, 100 - x = ior(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 deleted file mode 100644 index 17cd02a0ca7f..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv-byref.f90 +++ /dev/null @@ -1,193 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir --force-byref-reduction %s -o - | FileCheck %s - -! NOTE: Assertions have been autogenerated by utils/generate-test-checks.py - -! CHECK-LABEL: omp.declare_reduction @eqv_reduction : !fir.ref> -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>): -! CHECK: %[[VAL_1:.*]] = arith.constant true -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i1) -> !fir.logical<4> -! CHECK: %[[REF:.*]] = fir.alloca !fir.logical<4> -! CHECK: fir.store %[[VAL_2]] to %[[REF]] : !fir.ref> -! CHECK: omp.yield(%[[REF]] : !fir.ref>) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref>, %[[ARG1:.*]]: !fir.ref>): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref> -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref> -! CHECK: %[[VAL_2:.*]] = fir.convert %[[LD0]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_3:.*]] = fir.convert %[[LD1]] : (!fir.logical<4>) -> i1 -! CHECK: %[[RES:.*]] = arith.cmpi eq, %[[VAL_2]], %[[VAL_3]] : i1 -! CHECK: %[[VAL_5:.*]] = fir.convert %[[RES]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_5]] to %[[ARG0]] : !fir.ref> -! CHECK: omp.yield(%[[ARG0]] : !fir.ref>) -! CHECK: } - -! CHECK-LABEL: func.func @_QPsimple_reduction( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reductionEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reductionEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.eqv.:x) - do i=1, 100 - x = x .eqv. y(i) - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_reduction_switch_order( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reduction_switch_orderEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reduction_switch_orderEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction_switch_order(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.eqv.:x) - do i=1, 100 - x = y(i) .eqv. x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_reductions( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "w"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_reductionsEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} -! CHECK: %[[VAL_4:.*]] = fir.alloca !fir.logical<4> {bindc_name = "z", uniq_name = "_QFmultiple_reductionsEz"} -! CHECK: %[[VAL_5:.*]] = arith.constant true -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_6]] to %[[VAL_2]] : !fir.ref> -! CHECK: %[[VAL_7:.*]] = arith.constant true -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref> -! CHECK: %[[VAL_9:.*]] = arith.constant true -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_10]] to %[[VAL_4]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_11:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @eqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @eqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi eq, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi eq, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi eq, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine multiple_reductions(w) - logical :: x,y,z,w(100) - x = .true. - y = .true. - z = .true. - !$omp parallel - !$omp do reduction(.eqv.:x,y,z) - do i=1, 100 - x = x .eqv. w(i) - y = y .eqv. w(i) - z = z .eqv. w(i) - end do - !$omp end do - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 deleted file mode 100644 index e714e45540c3..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-eqv.f90 +++ /dev/null @@ -1,187 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -! NOTE: Assertions have been autogenerated by utils/generate-test-checks.py - -! CHECK-LABEL: omp.declare_reduction @eqv_reduction : !fir.logical<4> init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.logical<4>): -! CHECK: %[[VAL_1:.*]] = arith.constant true -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i1) -> !fir.logical<4> -! CHECK: omp.yield(%[[VAL_2]] : !fir.logical<4>) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.logical<4>, %[[VAL_1:.*]]: !fir.logical<4>): -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_0]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_1]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_4:.*]] = arith.cmpi eq, %[[VAL_2]], %[[VAL_3]] : i1 -! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i1) -> !fir.logical<4> -! CHECK: omp.yield(%[[VAL_5]] : !fir.logical<4>) -! CHECK: } - -! CHECK-LABEL: func.func @_QPsimple_reduction( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reductionEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reductionEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.eqv.:x) - do i=1, 100 - x = x .eqv. y(i) - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_reduction_switch_order( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reduction_switch_orderEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reduction_switch_orderEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi eq, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction_switch_order(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.eqv.:x) - do i=1, 100 - x = y(i) .eqv. x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_reductions( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "w"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_reductionsEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} -! CHECK: %[[VAL_4:.*]] = fir.alloca !fir.logical<4> {bindc_name = "z", uniq_name = "_QFmultiple_reductionsEz"} -! CHECK: %[[VAL_5:.*]] = arith.constant true -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_6]] to %[[VAL_2]] : !fir.ref> -! CHECK: %[[VAL_7:.*]] = arith.constant true -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref> -! CHECK: %[[VAL_9:.*]] = arith.constant true -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_10]] to %[[VAL_4]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_11:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@eqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @eqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @eqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi eq, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi eq, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi eq, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine multiple_reductions(w) - logical :: x,y,z,w(100) - x = .true. - y = .true. - z = .true. - !$omp parallel - !$omp do reduction(.eqv.:x,y,z) - do i=1, 100 - x = x .eqv. w(i) - y = y .eqv. w(i) - z = z .eqv. w(i) - end do - !$omp end do - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 deleted file mode 100644 index 89d16c3191b2..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv-byref.f90 +++ /dev/null @@ -1,195 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir --force-byref-reduction %s -o - | FileCheck %s - -! NOTE: Assertions have been autogenerated by utils/generate-test-checks.py - - -! CHECK-LABEL: omp.declare_reduction @neqv_reduction : !fir.ref> -! CHECK-SAME: init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.ref>): -! CHECK: %[[VAL_1:.*]] = arith.constant false -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i1) -> !fir.logical<4> -! CHECK: %[[REF:.*]] = fir.alloca !fir.logical<4> -! CHECK: fir.store %[[VAL_2]] to %[[REF]] : !fir.ref> -! CHECK: omp.yield(%[[REF]] : !fir.ref>) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref>, %[[ARG1:.*]]: !fir.ref>): -! CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref> -! CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref> -! CHECK: %[[VAL_2:.*]] = fir.convert %[[LD0]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_3:.*]] = fir.convert %[[LD1]] : (!fir.logical<4>) -> i1 -! CHECK: %[[RES:.*]] = arith.cmpi ne, %[[VAL_2]], %[[VAL_3]] : i1 -! CHECK: %[[VAL_5:.*]] = fir.convert %[[RES]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_5]] to %[[ARG0]] : !fir.ref> -! CHECK: omp.yield(%[[ARG0]] : !fir.ref>) -! CHECK: } - -! CHECK-LABEL: func.func @_QPsimple_reduction( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reductionEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reductionEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.neqv.:x) - do i=1, 100 - x = x .neqv. y(i) - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_reduction_switch_order( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reduction_switch_orderEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reduction_switch_orderEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction_switch_order(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.neqv.:x) - do i=1, 100 - x = y(i) .neqv. x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_reductions( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "w"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_reductionsEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} -! CHECK: %[[VAL_4:.*]] = fir.alloca !fir.logical<4> {bindc_name = "z", uniq_name = "_QFmultiple_reductionsEz"} -! CHECK: %[[VAL_5:.*]] = arith.constant true -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_6]] to %[[VAL_2]] : !fir.ref> -! CHECK: %[[VAL_7:.*]] = arith.constant true -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref> -! CHECK: %[[VAL_9:.*]] = arith.constant true -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_10]] to %[[VAL_4]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_11:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop byref reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @neqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @neqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi ne, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi ne, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi ne, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - - -subroutine multiple_reductions(w) - logical :: x,y,z,w(100) - x = .true. - y = .true. - z = .true. - !$omp parallel - !$omp do reduction(.neqv.:x,y,z) - do i=1, 100 - x = x .neqv. w(i) - y = y .neqv. w(i) - z = z .neqv. w(i) - end do - !$omp end do - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 deleted file mode 100644 index 106e867f367b..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-logical-neqv.f90 +++ /dev/null @@ -1,189 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp %s -o - | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp %s -o - | FileCheck %s - -! NOTE: Assertions have been autogenerated by utils/generate-test-checks.py - - -! CHECK-LABEL: omp.declare_reduction @neqv_reduction : !fir.logical<4> init { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.logical<4>): -! CHECK: %[[VAL_1:.*]] = arith.constant false -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_1]] : (i1) -> !fir.logical<4> -! CHECK: omp.yield(%[[VAL_2]] : !fir.logical<4>) - -! CHECK-LABEL: } combiner { -! CHECK: ^bb0(%[[VAL_0:.*]]: !fir.logical<4>, %[[VAL_1:.*]]: !fir.logical<4>): -! CHECK: %[[VAL_2:.*]] = fir.convert %[[VAL_0]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_3:.*]] = fir.convert %[[VAL_1]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_4:.*]] = arith.cmpi ne, %[[VAL_2]], %[[VAL_3]] : i1 -! CHECK: %[[VAL_5:.*]] = fir.convert %[[VAL_4]] : (i1) -> !fir.logical<4> -! CHECK: omp.yield(%[[VAL_5]] : !fir.logical<4>) -! CHECK: } - -! CHECK-LABEL: func.func @_QPsimple_reduction( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reductionEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reductionEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_12:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_13:.*]] = fir.convert %[[VAL_12]] : (i32) -> i64 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_15:.*]] = arith.subi %[[VAL_13]], %[[VAL_14]] : i64 -! CHECK: %[[VAL_16:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_15]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_11]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.neqv.:x) - do i=1, 100 - x = x .neqv. y(i) - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPsimple_reduction_switch_order( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "y"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFsimple_reduction_switch_orderEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFsimple_reduction_switch_orderEx"} -! CHECK: %[[VAL_3:.*]] = arith.constant true -! CHECK: %[[VAL_4:.*]] = fir.convert %[[VAL_3]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_4]] to %[[VAL_2]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_5:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_6:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_7:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_8:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_9:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_10:.*]]) : i32 = (%[[VAL_6]]) to (%[[VAL_7]]) inclusive step (%[[VAL_8]]) { -! CHECK: fir.store %[[VAL_10]] to %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_11:.*]] = fir.load %[[VAL_5]] : !fir.ref -! CHECK: %[[VAL_12:.*]] = fir.convert %[[VAL_11]] : (i32) -> i64 -! CHECK: %[[VAL_13:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_14:.*]] = arith.subi %[[VAL_12]], %[[VAL_13]] : i64 -! CHECK: %[[VAL_15:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_14]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_16:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_9]] : !fir.ref> -! CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_16]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_19:.*]] = fir.convert %[[VAL_17]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_20:.*]] = arith.cmpi ne, %[[VAL_18]], %[[VAL_19]] : i1 -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_21]] to %[[VAL_9]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - -subroutine simple_reduction_switch_order(y) - logical :: x, y(100) - x = .true. - !$omp parallel - !$omp do reduction(.neqv.:x) - do i=1, 100 - x = y(i) .neqv. x - end do - !$omp end do - !$omp end parallel -end subroutine - -! CHECK-LABEL: func.func @_QPmultiple_reductions( -! CHECK-SAME: %[[VAL_0:.*]]: !fir.ref>> {fir.bindc_name = "w"}) { -! CHECK: %[[VAL_1:.*]] = fir.alloca i32 {bindc_name = "i", uniq_name = "_QFmultiple_reductionsEi"} -! CHECK: %[[VAL_2:.*]] = fir.alloca !fir.logical<4> {bindc_name = "x", uniq_name = "_QFmultiple_reductionsEx"} -! CHECK: %[[VAL_3:.*]] = fir.alloca !fir.logical<4> {bindc_name = "y", uniq_name = "_QFmultiple_reductionsEy"} -! CHECK: %[[VAL_4:.*]] = fir.alloca !fir.logical<4> {bindc_name = "z", uniq_name = "_QFmultiple_reductionsEz"} -! CHECK: %[[VAL_5:.*]] = arith.constant true -! CHECK: %[[VAL_6:.*]] = fir.convert %[[VAL_5]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_6]] to %[[VAL_2]] : !fir.ref> -! CHECK: %[[VAL_7:.*]] = arith.constant true -! CHECK: %[[VAL_8:.*]] = fir.convert %[[VAL_7]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_8]] to %[[VAL_3]] : !fir.ref> -! CHECK: %[[VAL_9:.*]] = arith.constant true -! CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_9]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_10]] to %[[VAL_4]] : !fir.ref> -! CHECK: omp.parallel { -! CHECK: %[[VAL_11:.*]] = fir.alloca i32 {adapt.valuebyref, pinned} -! CHECK: %[[VAL_12:.*]] = arith.constant 1 : i32 -! CHECK: %[[VAL_13:.*]] = arith.constant 100 : i32 -! CHECK: %[[VAL_14:.*]] = arith.constant 1 : i32 -! CHECK: omp.wsloop reduction(@neqv_reduction %[[VAL_2]] -> %[[VAL_15:.*]] : !fir.ref>, @neqv_reduction %[[VAL_3]] -> %[[VAL_16:.*]] : !fir.ref>, @neqv_reduction %[[VAL_4]] -> %[[VAL_17:.*]] : !fir.ref>) { -! CHECK-NEXT: omp.loop_nest (%[[VAL_18:.*]]) : i32 = (%[[VAL_12]]) to (%[[VAL_13]]) inclusive step (%[[VAL_14]]) { -! CHECK: fir.store %[[VAL_18]] to %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_19:.*]] = fir.load %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_20:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_21:.*]] = fir.convert %[[VAL_20]] : (i32) -> i64 -! CHECK: %[[VAL_22:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_23:.*]] = arith.subi %[[VAL_21]], %[[VAL_22]] : i64 -! CHECK: %[[VAL_24:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_23]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_25:.*]] = fir.load %[[VAL_24]] : !fir.ref> -! CHECK: %[[VAL_26:.*]] = fir.convert %[[VAL_19]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_27:.*]] = fir.convert %[[VAL_25]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_28:.*]] = arith.cmpi ne, %[[VAL_26]], %[[VAL_27]] : i1 -! CHECK: %[[VAL_29:.*]] = fir.convert %[[VAL_28]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_29]] to %[[VAL_15]] : !fir.ref> -! CHECK: %[[VAL_30:.*]] = fir.load %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_31:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_32:.*]] = fir.convert %[[VAL_31]] : (i32) -> i64 -! CHECK: %[[VAL_33:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_34:.*]] = arith.subi %[[VAL_32]], %[[VAL_33]] : i64 -! CHECK: %[[VAL_35:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_34]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_36:.*]] = fir.load %[[VAL_35]] : !fir.ref> -! CHECK: %[[VAL_37:.*]] = fir.convert %[[VAL_30]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_38:.*]] = fir.convert %[[VAL_36]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_39:.*]] = arith.cmpi ne, %[[VAL_37]], %[[VAL_38]] : i1 -! CHECK: %[[VAL_40:.*]] = fir.convert %[[VAL_39]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_40]] to %[[VAL_16]] : !fir.ref> -! CHECK: %[[VAL_41:.*]] = fir.load %[[VAL_17]] : !fir.ref> -! CHECK: %[[VAL_42:.*]] = fir.load %[[VAL_11]] : !fir.ref -! CHECK: %[[VAL_43:.*]] = fir.convert %[[VAL_42]] : (i32) -> i64 -! CHECK: %[[VAL_44:.*]] = arith.constant 1 : i64 -! CHECK: %[[VAL_45:.*]] = arith.subi %[[VAL_43]], %[[VAL_44]] : i64 -! CHECK: %[[VAL_46:.*]] = fir.coordinate_of %[[VAL_0]], %[[VAL_45]] : (!fir.ref>>, i64) -> !fir.ref> -! CHECK: %[[VAL_47:.*]] = fir.load %[[VAL_46]] : !fir.ref> -! CHECK: %[[VAL_48:.*]] = fir.convert %[[VAL_41]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_49:.*]] = fir.convert %[[VAL_47]] : (!fir.logical<4>) -> i1 -! CHECK: %[[VAL_50:.*]] = arith.cmpi ne, %[[VAL_48]], %[[VAL_49]] : i1 -! CHECK: %[[VAL_51:.*]] = fir.convert %[[VAL_50]] : (i1) -> !fir.logical<4> -! CHECK: fir.store %[[VAL_51]] to %[[VAL_17]] : !fir.ref> -! CHECK: omp.yield -! CHECK: omp.terminator -! CHECK: omp.terminator -! CHECK: return - - -subroutine multiple_reductions(w) - logical :: x,y,z,w(100) - x = .true. - y = .true. - z = .true. - !$omp parallel - !$omp do reduction(.neqv.:x,y,z) - do i=1, 100 - x = x .neqv. w(i) - y = y .neqv. w(i) - z = z .neqv. w(i) - end do - !$omp end do - !$omp end parallel -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 deleted file mode 100644 index a4244d11a558..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max-byref.f90 +++ /dev/null @@ -1,95 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction -o - %s 2>&1 | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -mmlir --force-byref-reduction -o - %s 2>&1 | FileCheck %s - -!CHECK: omp.declare_reduction @max_byref_f32 : !fir.ref -!CHECK-SAME: init { -!CHECK: %[[MINIMUM_VAL:.*]] = arith.constant -3.40282347E+38 : f32 -!CHECK: %[[REF:.*]] = fir.alloca f32 -!CHECK: fir.store %[[MINIMUM_VAL]] to %[[REF]] : !fir.ref -!CHECK: omp.yield(%[[REF]] : !fir.ref) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -!CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -!CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK: %[[RES:.*]] = arith.maxnumf %[[LD0]], %[[LD1]] {{.*}}: f32 -!CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -!CHECK: omp.yield(%[[ARG0]] : !fir.ref) - -!CHECK-LABEL: omp.declare_reduction @max_byref_i32 : !fir.ref -!CHECK-SAME: init { -!CHECK: %[[MINIMUM_VAL:.*]] = arith.constant -2147483648 : i32 -!CHECK: fir.store %[[MINIMUM_VAL]] to %[[REF]] : !fir.ref -!CHECK: omp.yield(%[[REF]] : !fir.ref) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -!CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -!CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK: %[[RES:.*]] = arith.maxsi %[[LD0]], %[[LD1]] : i32 -!CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -!CHECK: omp.yield(%[[ARG0]] : !fir.ref) - -!CHECK-LABEL: @_QPreduction_max_int -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@max_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi sgt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -!CHECK-LABEL: @_QPreduction_max_real -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_max_realEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@max_byref_f32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_max_int(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(max:x) - do i=1, 100 - x = max(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine - -subroutine reduction_max_real(y) - real :: x, y(:) - x = 0.0 - !$omp parallel - !$omp do reduction(max:x) - do i=1, 100 - x = max(y(i), x) - end do - !$omp end do - !$omp end parallel - print *, x - - !$omp parallel - !$omp do reduction(max:x) - do i=1, 100 - !CHECK-NOT: omp.reduction - if (y(i) .gt. x) x = y(i) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 deleted file mode 100644 index e000bc36ca3f..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-max.f90 +++ /dev/null @@ -1,84 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp -o - %s 2>&1 | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s - -!CHECK: omp.declare_reduction @[[MAX_DECLARE_F:.*]] : f32 init { -!CHECK: %[[MINIMUM_VAL_F:.*]] = arith.constant -3.40282347E+38 : f32 -!CHECK: omp.yield(%[[MINIMUM_VAL_F]] : f32) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0_F:.*]]: f32, %[[ARG1_F:.*]]: f32): -!CHECK: %[[COMB_VAL_F:.*]] = arith.maxnumf %[[ARG0_F]], %[[ARG1_F]] {{.*}}: f32 -!CHECK: omp.yield(%[[COMB_VAL_F]] : f32) - -!CHECK: omp.declare_reduction @[[MAX_DECLARE_I:.*]] : i32 init { -!CHECK: %[[MINIMUM_VAL_I:.*]] = arith.constant -2147483648 : i32 -!CHECK: omp.yield(%[[MINIMUM_VAL_I]] : i32) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0_I:.*]]: i32, %[[ARG1_I:.*]]: i32): -!CHECK: %[[COMB_VAL_I:.*]] = arith.maxsi %[[ARG0_I]], %[[ARG1_I]] : i32 -!CHECK: omp.yield(%[[COMB_VAL_I]] : i32) - -!CHECK-LABEL: @_QPreduction_max_int -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_max_intEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MAX_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi sgt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -!CHECK-LABEL: @_QPreduction_max_real -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_max_realEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MAX_DECLARE_F]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_max_int(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(max:x) - do i=1, 100 - x = max(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine - -subroutine reduction_max_real(y) - real :: x, y(:) - x = 0.0 - !$omp parallel - !$omp do reduction(max:x) - do i=1, 100 - x = max(y(i), x) - end do - !$omp end do - !$omp end parallel - print *, x - - !$omp parallel - !$omp do reduction(max:x) - do i=1, 100 - !CHECK-NOT: omp.reduction - if (y(i) .gt. x) x = y(i) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 deleted file mode 100644 index 17435e1a194c..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min-byref.f90 +++ /dev/null @@ -1,95 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp --force-byref-reduction -o - %s 2>&1 | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -mmlir --force-byref-reduction -fopenmp -o - %s 2>&1 | FileCheck %s - -!CHECK: omp.declare_reduction @min_byref_f32 : !fir.ref -!CHECK-SAME: init { -!CHECK: %[[MAXIMUM_VAL:.*]] = arith.constant 3.40282347E+38 : f32 -!CHECK: %[[REF:.*]] = fir.alloca f32 -!CHECK: fir.store %[[MAXIMUM_VAL]] to %[[REF]] : !fir.ref -!CHECK: omp.yield(%[[REF]] : !fir.ref) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -!CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -!CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK: %[[RES:.*]] = arith.minnumf %[[LD0]], %[[LD1]] {{.*}}: f32 -!CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -!CHECK: omp.yield(%[[ARG0]] : !fir.ref) - -!CHECK-LABEL: omp.declare_reduction @min_byref_i32 : !fir.ref -!CHECK-SAME: init { -!CHECK: %[[MAXIMUM_VAL:.*]] = arith.constant 2147483647 : i32 -!CHECK: fir.store %[[MAXIMUM_VAL]] to %[[REF]] : !fir.ref -!CHECK: omp.yield(%[[REF]] : !fir.ref) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0:.*]]: !fir.ref, %[[ARG1:.*]]: !fir.ref): -!CHECK: %[[LD0:.*]] = fir.load %[[ARG0]] : !fir.ref -!CHECK: %[[LD1:.*]] = fir.load %[[ARG1]] : !fir.ref -!CHECK: %[[RES:.*]] = arith.minsi %[[LD0]], %[[LD1]] : i32 -!CHECK: fir.store %[[RES]] to %[[ARG0]] : !fir.ref -!CHECK: omp.yield(%[[ARG0]] : !fir.ref) - -!CHECK-LABEL: @_QPreduction_min_int -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_min_intEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@min_byref_i32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi slt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -!CHECK-LABEL: @_QPreduction_min_real -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_min_realEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop byref reduction(@min_byref_f32 %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_min_int(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(min:x) - do i=1, 100 - x = min(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine - -subroutine reduction_min_real(y) - real :: x, y(:) - x = 0.0 - !$omp parallel - !$omp do reduction(min:x) - do i=1, 100 - x = min(y(i), x) - end do - !$omp end do - !$omp end parallel - print *, x - - !$omp parallel - !$omp do reduction(min:x) - do i=1, 100 - !CHECK-NOT: omp.reduction - if (y(i) .gt. x) x = y(i) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 deleted file mode 100644 index 1d18ece7297d..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-reduction-min.f90 +++ /dev/null @@ -1,84 +0,0 @@ -! RUN: bbc -emit-fir -hlfir=false -fopenmp -o - %s 2>&1 | FileCheck %s -! RUN: %flang_fc1 -emit-fir -flang-deprecated-no-hlfir -fopenmp -o - %s 2>&1 | FileCheck %s - -!CHECK: omp.declare_reduction @[[MIN_DECLARE_F:.*]] : f32 init { -!CHECK: %[[MAXIMUM_VAL_F:.*]] = arith.constant 3.40282347E+38 : f32 -!CHECK: omp.yield(%[[MAXIMUM_VAL_F]] : f32) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0_F:.*]]: f32, %[[ARG1_F:.*]]: f32): -!CHECK: %[[COMB_VAL_F:.*]] = arith.minnumf %[[ARG0_F]], %[[ARG1_F]] {{.*}}: f32 -!CHECK: omp.yield(%[[COMB_VAL_F]] : f32) - -!CHECK: omp.declare_reduction @[[MIN_DECLARE_I:.*]] : i32 init { -!CHECK: %[[MAXIMUM_VAL_I:.*]] = arith.constant 2147483647 : i32 -!CHECK: omp.yield(%[[MAXIMUM_VAL_I]] : i32) -!CHECK: combiner -!CHECK: ^bb0(%[[ARG0_I:.*]]: i32, %[[ARG1_I:.*]]: i32): -!CHECK: %[[COMB_VAL_I:.*]] = arith.minsi %[[ARG0_I]], %[[ARG1_I]] : i32 -!CHECK: omp.yield(%[[COMB_VAL_I]] : i32) - -!CHECK-LABEL: @_QPreduction_min_int -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca i32 {bindc_name = "x", uniq_name = "_QFreduction_min_intEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MIN_DECLARE_I]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpi slt, %[[LPRV]], %[[Y_I]] : i32 -!CHECK: %[[SEL:.+]] = arith.select %[[RES]], %[[LPRV]], %[[Y_I]] -!CHECK: fir.store %[[SEL]] to %[[PRV]] : !fir.ref -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -!CHECK-LABEL: @_QPreduction_min_real -!CHECK-SAME: %[[Y_BOX:.*]]: !fir.box> -!CHECK: %[[X_REF:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFreduction_min_realEx"} -!CHECK: omp.parallel -!CHECK: omp.wsloop reduction(@[[MIN_DECLARE_F]] %[[X_REF]] -> %[[PRV:.+]] : !fir.ref) -!CHECK-NEXT: omp.loop_nest -!CHECK: %[[LPRV:.+]] = fir.load %[[PRV]] : !fir.ref -!CHECK: %[[Y_I_REF:.*]] = fir.coordinate_of %[[Y_BOX]] -!CHECK: %[[Y_I:.*]] = fir.load %[[Y_I_REF]] : !fir.ref -!CHECK: %[[RES:.+]] = arith.cmpf ogt, %[[Y_I]], %[[LPRV]] {{.*}} : f32 -!CHECK: omp.yield -!CHECK: omp.terminator -!CHECK: omp.terminator - -subroutine reduction_min_int(y) - integer :: x, y(:) - x = 0 - !$omp parallel - !$omp do reduction(min:x) - do i=1, 100 - x = min(x, y(i)) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine - -subroutine reduction_min_real(y) - real :: x, y(:) - x = 0.0 - !$omp parallel - !$omp do reduction(min:x) - do i=1, 100 - x = min(y(i), x) - end do - !$omp end do - !$omp end parallel - print *, x - - !$omp parallel - !$omp do reduction(min:x) - do i=1, 100 - !CHECK-NOT: omp.reduction - if (y(i) .gt. x) x = y(i) - end do - !$omp end do - !$omp end parallel - print *, x -end subroutine diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 deleted file mode 100644 index 751e4c8c5709..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-simd.f90 +++ /dev/null @@ -1,37 +0,0 @@ -! This test checks lowering of OpenMP DO Directive(Worksharing) with -! simd schedule modifier. - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -program wsloop_dynamic - integer :: i -!CHECK-LABEL: func @_QQmain() - -!$OMP PARALLEL -!CHECK: omp.parallel { - -!$OMP DO SCHEDULE(simd: runtime) -!CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 -!CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 -!CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop schedule(runtime, simd) nowait { -!CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { -!CHECK: fir.store %[[I]] to %[[STORE:.*]] : !fir.ref - - do i=1, 9 - print*, i -!CHECK: %[[RTBEGIN:.*]] = fir.call @_FortranAioBeginExternalListOutput -!CHECK: %[[LOAD:.*]] = fir.load %[[STORE]] : !fir.ref -!CHECK: fir.call @_FortranAioOutputInteger32(%[[RTBEGIN]], %[[LOAD]]) {{.*}}: (!fir.ref, i32) -> i1 -!CHECK: fir.call @_FortranAioEndIoStatement(%[[RTBEGIN]]) {{.*}}: (!fir.ref) -> i32 - end do -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -!$OMP END DO NOWAIT -!$OMP END PARALLEL -end diff --git a/flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 b/flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 deleted file mode 100644 index 4bd876012278..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop-variable.f90 +++ /dev/null @@ -1,187 +0,0 @@ -! This test checks lowering of OpenMP DO Directive(Worksharing) for different -! types of loop iteration variable, lower bound, upper bound, and step. - -!REQUIRES: shell -!RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - 2>&1 | FileCheck %s - -!CHECK: OpenMP loop iteration variable cannot have more than 64 bits size and will be narrowed into 64 bits. - -program wsloop_variable - integer(kind=1) :: i1_lb, i1_ub - integer(kind=2) :: i2, i2_ub, i2_s - integer(kind=4) :: i4_s - integer(kind=8) :: i8, i8_s - integer(kind=16) :: i16, i16_lb - real :: x - -!CHECK: %[[TMP0:.*]] = arith.constant 1 : i32 -!CHECK: %[[TMP1:.*]] = arith.constant 100 : i32 -!CHECK: %[[TMP2:.*]] = fir.convert %[[TMP0]] : (i32) -> i64 -!CHECK: %[[TMP3:.*]] = fir.convert %{{.*}} : (i8) -> i64 -!CHECK: %[[TMP4:.*]] = fir.convert %{{.*}} : (i16) -> i64 -!CHECK: %[[TMP5:.*]] = fir.convert %{{.*}} : (i128) -> i64 -!CHECK: %[[TMP6:.*]] = fir.convert %[[TMP1]] : (i32) -> i64 -!CHECK: %[[TMP7:.*]] = fir.convert %{{.*}} : (i32) -> i64 -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]], %[[ARG1:.*]]) : i64 = (%[[TMP2]], %[[TMP5]]) to (%[[TMP3]], %[[TMP6]]) inclusive step (%[[TMP4]], %[[TMP7]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i64) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV0:.*]] : !fir.ref -!CHECK: fir.store %[[ARG1]] to %[[STORE_IV1:.*]] : !fir.ref -!CHECK: %[[LOAD_IV0:.*]] = fir.load %[[STORE_IV0]] : !fir.ref -!CHECK: %[[LOAD_IV0_I64:.*]] = fir.convert %[[LOAD_IV0]] : (i16) -> i64 -!CHECK: %[[LOAD_IV1:.*]] = fir.load %[[STORE_IV1]] : !fir.ref -!CHECK: %[[TMP10:.*]] = arith.addi %[[LOAD_IV0_I64]], %[[LOAD_IV1]] : i64 -!CHECK: %[[TMP11:.*]] = fir.convert %[[TMP10]] : (i64) -> f32 -!CHECK: fir.store %[[TMP11]] to %{{.*}} : !fir.ref -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - - !$omp do collapse(2) - do i2 = 1, i1_ub, i2_s - do i8 = i16_lb, 100, i4_s - x = i2 + i8 - end do - end do - !$omp end do - -!CHECK: %[[TMP12:.*]] = arith.constant 1 : i32 -!CHECK: %[[TMP13:.*]] = fir.convert %{{.*}} : (i8) -> i32 -!CHECK: %[[TMP14:.*]] = fir.convert %{{.*}} : (i64) -> i32 -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[TMP12]]) to (%[[TMP13]]) inclusive step (%[[TMP14]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE3:.*]] : !fir.ref -!CHECK: %[[LOAD3:.*]] = fir.load %[[STORE3]] : !fir.ref -!CHECK: %[[TMP16:.*]] = fir.convert %[[LOAD3]] : (i16) -> f32 -!CHECK: fir.store %[[TMP16]] to %{{.*}} : !fir.ref -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - - !$omp do - do i2 = 1, i1_ub, i8_s - x = i2 - end do - !$omp end do - -!CHECK: %[[TMP17:.*]] = fir.convert %{{.*}} : (i8) -> i64 -!CHECK: %[[TMP18:.*]] = fir.convert %{{.*}} : (i16) -> i64 -!CHECK: %[[TMP19:.*]] = fir.convert %{{.*}} : (i32) -> i64 -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[ARG1:.*]]) : i64 = (%[[TMP17]]) to (%[[TMP18]]) inclusive step (%[[TMP19]]) { -!CHECK: %[[ARG1_I128:.*]] = fir.convert %[[ARG1]] : (i64) -> i128 -!CHECK: fir.store %[[ARG1_I128]] to %[[STORE4:.*]] : !fir.ref -!CHECK: %[[LOAD4:.*]] = fir.load %[[STORE4]] : !fir.ref -!CHECK: %[[TMP21:.*]] = fir.convert %[[LOAD4]] : (i128) -> f32 -!CHECK: fir.store %[[TMP21]] to %{{.*}} : !fir.ref -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - - !$omp do - do i16 = i1_lb, i2_ub, i4_s - x = i16 - end do - !$omp end do - -end program wsloop_variable - -!CHECK-LABEL: func.func @_QPwsloop_variable_sub() { -!CHECK: %[[IV2:.*]] = fir.alloca i8 {adapt.valuebyref, pinned} -!CHECK: %[[VAL_0:.*]] = fir.alloca i128 {bindc_name = "i16_lb", uniq_name = "_QFwsloop_variable_subEi16_lb"} -!CHECK: %[[VAL_1:.*]] = fir.alloca i8 {bindc_name = "i1_ub", uniq_name = "_QFwsloop_variable_subEi1_ub"} -!CHECK: %[[VAL_2:.*]] = fir.alloca i16 {bindc_name = "i2", uniq_name = "_QFwsloop_variable_subEi2"} -!CHECK: %[[VAL_3:.*]] = fir.alloca i16 {bindc_name = "i2_s", uniq_name = "_QFwsloop_variable_subEi2_s"} -!CHECK: %[[VAL_4:.*]] = fir.alloca i32 {bindc_name = "i4_s", uniq_name = "_QFwsloop_variable_subEi4_s"} -!CHECK: %[[VAL_5:.*]] = fir.alloca i64 {bindc_name = "i8", uniq_name = "_QFwsloop_variable_subEi8"} -!CHECK: %[[J1:.*]] = fir.alloca i8 {bindc_name = "j1", uniq_name = "_QFwsloop_variable_subEj1"} -!CHECK: %[[VAL_6:.*]] = fir.alloca f32 {bindc_name = "x", uniq_name = "_QFwsloop_variable_subEx"} -!CHECK: %[[VAL_7:.*]] = arith.constant 1 : i32 -!CHECK: %[[VAL_8:.*]] = fir.load %[[VAL_1]] : !fir.ref -!CHECK: %[[VAL_9:.*]] = fir.load %[[VAL_3]] : !fir.ref -!CHECK: %[[VAL_10:.*]] = fir.convert %[[VAL_8]] : (i8) -> i32 -!CHECK: %[[VAL_11:.*]] = fir.convert %[[VAL_9]] : (i16) -> i32 -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[VAL_7]]) to (%[[VAL_10]]) inclusive step (%[[VAL_11]]) { -!CHECK: %[[ARG0_I16:.*]] = fir.convert %[[ARG0]] : (i32) -> i16 -!CHECK: fir.store %[[ARG0_I16]] to %[[STORE_IV:.*]] : !fir.ref -!CHECK: %[[VAL_13:.*]] = fir.load %[[VAL_0]] : !fir.ref -!CHECK: %[[VAL_14:.*]] = fir.convert %[[VAL_13]] : (i128) -> index -!CHECK: %[[VAL_15:.*]] = arith.constant 100 : i32 -!CHECK: %[[VAL_16:.*]] = fir.convert %[[VAL_15]] : (i32) -> index -!CHECK: %[[VAL_17:.*]] = fir.load %[[VAL_4]] : !fir.ref -!CHECK: %[[VAL_18:.*]] = fir.convert %[[VAL_17]] : (i32) -> index -!CHECK: %[[LB:.*]] = fir.convert %[[VAL_14]] : (index) -> i64 -!CHECK: %[[VAL_19:.*]]:2 = fir.do_loop %[[VAL_20:[^ ]*]] = -!CHECK-SAME: %[[VAL_14]] to %[[VAL_16]] step %[[VAL_18]] -!CHECK-SAME: iter_args(%[[IV:.*]] = %[[LB]]) -> (index, i64) { -!CHECK: fir.store %[[IV]] to %[[VAL_5]] : !fir.ref -!CHECK: %[[LOAD_IV:.*]] = fir.load %[[STORE_IV]] : !fir.ref -!CHECK: %[[VAL_22:.*]] = fir.convert %[[LOAD_IV]] : (i16) -> i64 -!CHECK: %[[VAL_23:.*]] = fir.load %[[VAL_5]] : !fir.ref -!CHECK: %[[VAL_24:.*]] = arith.addi %[[VAL_22]], %[[VAL_23]] : i64 -!CHECK: %[[VAL_25:.*]] = fir.convert %[[VAL_24]] : (i64) -> f32 -!CHECK: fir.store %[[VAL_25]] to %[[VAL_6]] : !fir.ref -!CHECK: %[[VAL_26:.*]] = arith.addi %[[VAL_20]], %[[VAL_18]] : index -!CHECK: %[[STEPCAST:.*]] = fir.convert %[[VAL_18]] : (index) -> i64 -!CHECK: %[[IVLOAD:.*]] = fir.load %[[VAL_5]] : !fir.ref -!CHECK: %[[IVINC:.*]] = arith.addi %[[IVLOAD]], %[[STEPCAST]] -!CHECK: fir.result %[[VAL_26]], %[[IVINC]] : index, i64 -!CHECK: } -!CHECK: fir.store %[[VAL_19]]#1 to %[[VAL_5]] : !fir.ref -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - -subroutine wsloop_variable_sub - integer(kind=1) :: i1, i1_ub, j1 - integer(kind=2) :: i2, i2_s - integer(kind=4) :: i4_s - integer(kind=8) :: i8 - integer(kind=16) :: i16_lb - real :: x - - !$omp do - do i2 = 1, i1_ub, i2_s - do i8 = i16_lb, 100, i4_s - x = i2 + i8 - end do - end do - !$omp end do - -!CHECK: %[[C1:.*]] = arith.constant 1 : i32 -!CHECK: %[[C10:.*]] = arith.constant 10 : i32 -!CHECK: %[[C1_2:.*]] = arith.constant 1 : i32 -!CHECK: omp.wsloop { -!CHECK-NEXT: omp.loop_nest (%[[ARG0:.*]]) : i32 = (%[[C1]]) to (%[[C10]]) inclusive step (%[[C1_2]]) { -!CHECK: %[[ARG0_I8:.*]] = fir.convert %[[ARG0]] : (i32) -> i8 -!CHECK: fir.store %[[ARG0_I8]] to %[[IV2]] : !fir.ref -!CHECK: %[[IV2LOAD:.*]] = fir.load %[[IV2]] : !fir.ref -!CHECK: %[[J1LOAD:.*]] = fir.load %[[J1]] : !fir.ref -!CHECK: %[[VAL_27:.*]] = arith.cmpi eq, %[[IV2LOAD]], %[[J1LOAD]] : i8 -!CHECK: fir.if %[[VAL_27]] { -!CHECK: } else { -!CHECK: } -!CHECK: omp.yield -!CHECK: } -!CHECK: omp.terminator -!CHECK: } - - j1 = 5 - !$omp do - do i1 = 1, 10 - if (i1 .eq. j1) then - print *, "EQ" - end if - end do - !$omp end do - -!CHECK: return -!CHECK: } - -end diff --git a/flang/test/Lower/OpenMP/FIR/wsloop.f90 b/flang/test/Lower/OpenMP/FIR/wsloop.f90 deleted file mode 100644 index c9e428abdb44..000000000000 --- a/flang/test/Lower/OpenMP/FIR/wsloop.f90 +++ /dev/null @@ -1,78 +0,0 @@ -! This test checks lowering of OpenMP DO Directive (Worksharing). - -! RUN: bbc -fopenmp -emit-fir -hlfir=false %s -o - | FileCheck %s - -!CHECK-LABEL: func @_QPsimple_loop() -subroutine simple_loop - integer :: i - ! CHECK: omp.parallel - !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP DO - do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV:.*]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! CHECK: omp.yield - ! CHECK: omp.terminator - !$OMP END DO - ! CHECK: omp.terminator - !$OMP END PARALLEL -end subroutine - -!CHECK-LABEL: func @_QPsimple_loop_with_step() -subroutine simple_loop_with_step - integer :: i - ! CHECK: omp.parallel - !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 2 : i32 - ! CHECK: omp.wsloop { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - !$OMP DO - do i=1, 9, 2 - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! CHECK: omp.yield - ! CHECK: omp.terminator - !$OMP END DO - ! CHECK: omp.terminator - !$OMP END PARALLEL -end subroutine - -!CHECK-LABEL: func @_QPloop_with_schedule_nowait() -subroutine loop_with_schedule_nowait - integer :: i - ! CHECK: omp.parallel - !$OMP PARALLEL - ! CHECK: %[[ALLOCA_IV:.*]] = fir.alloca i32 {{{.*}}, pinned} - ! CHECK: %[[WS_LB:.*]] = arith.constant 1 : i32 - ! CHECK: %[[WS_UB:.*]] = arith.constant 9 : i32 - ! CHECK: %[[WS_STEP:.*]] = arith.constant 1 : i32 - ! CHECK: omp.wsloop schedule(runtime) nowait { - ! CHECK-NEXT: omp.loop_nest (%[[I:.*]]) : i32 = (%[[WS_LB]]) to (%[[WS_UB]]) inclusive step (%[[WS_STEP]]) { - !$OMP DO SCHEDULE(runtime) - do i=1, 9 - ! CHECK: fir.store %[[I]] to %[[ALLOCA_IV]] : !fir.ref - ! CHECK: %[[LOAD_IV:.*]] = fir.load %[[ALLOCA_IV]] : !fir.ref - ! CHECK: fir.call @_FortranAioOutputInteger32({{.*}}, %[[LOAD_IV]]) {{.*}}: (!fir.ref, i32) -> i1 - print*, i - end do - ! CHECK: omp.yield - ! CHECK: omp.terminator - !$OMP END DO NOWAIT - ! CHECK: omp.terminator - !$OMP END PARALLEL -end subroutine -- GitLab From 19d2d3fe50c301272350d12c53c801b17e29e64e Mon Sep 17 00:00:00 2001 From: Mark de Wever Date: Sun, 28 Apr 2024 14:12:27 +0200 Subject: [PATCH 154/301] [libc++][modules] Enable installation by default. (#90094) This was suggested during the review of https://github.com/llvm/llvm-project/pull/89413 This does not change the experimental state of modules. --- libcxx/CMakeLists.txt | 2 +- libcxx/cmake/caches/Generic-cxx20.cmake | 1 - libcxx/cmake/caches/Generic-cxx23.cmake | 1 - libcxx/cmake/caches/Generic-cxx26.cmake | 1 - libcxx/cmake/caches/Generic-hardening-mode-extensive.cmake | 1 - libcxx/cmake/caches/Generic-no-exceptions.cmake | 1 - libcxx/cmake/caches/Generic-no-experimental.cmake | 1 - libcxx/cmake/caches/Generic-no-filesystem.cmake | 1 - libcxx/cmake/caches/Generic-no-localization.cmake | 1 - libcxx/cmake/caches/Generic-no-random_device.cmake | 1 - libcxx/cmake/caches/Generic-no-threads.cmake | 1 - libcxx/cmake/caches/Generic-no-unicode.cmake | 1 - libcxx/cmake/caches/Generic-no-wide-characters.cmake | 1 - libcxx/docs/BuildingLibcxx.rst | 2 +- libcxx/docs/ReleaseNotes/19.rst | 2 ++ 15 files changed, 4 insertions(+), 14 deletions(-) diff --git a/libcxx/CMakeLists.txt b/libcxx/CMakeLists.txt index 2977c26646cb..f34cb178e076 100644 --- a/libcxx/CMakeLists.txt +++ b/libcxx/CMakeLists.txt @@ -178,7 +178,7 @@ set(LIBCXX_LIBDIR_SUFFIX "${LLVM_LIBDIR_SUFFIX}" CACHE STRING option(LIBCXX_INSTALL_HEADERS "Install the libc++ headers." ON) option(LIBCXX_INSTALL_LIBRARY "Install the libc++ library." ON) option(LIBCXX_INSTALL_MODULES - "Install the libc++ C++20 module source files (experimental)." OFF + "Install the libc++ C++20 module source files (experimental)." ON ) cmake_dependent_option(LIBCXX_INSTALL_STATIC_LIBRARY "Install the static libc++ library." ON diff --git a/libcxx/cmake/caches/Generic-cxx20.cmake b/libcxx/cmake/caches/Generic-cxx20.cmake index 641c131a737b..3c44fdaf0e42 100644 --- a/libcxx/cmake/caches/Generic-cxx20.cmake +++ b/libcxx/cmake/caches/Generic-cxx20.cmake @@ -1,3 +1,2 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_TEST_PARAMS "std=c++20" CACHE STRING "") set(LIBCXXABI_TEST_PARAMS "${LIBCXX_TEST_PARAMS}" CACHE STRING "") diff --git a/libcxx/cmake/caches/Generic-cxx23.cmake b/libcxx/cmake/caches/Generic-cxx23.cmake index f5409e4652e4..bf88abf56ca6 100644 --- a/libcxx/cmake/caches/Generic-cxx23.cmake +++ b/libcxx/cmake/caches/Generic-cxx23.cmake @@ -1,3 +1,2 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_TEST_PARAMS "std=c++23" CACHE STRING "") set(LIBCXXABI_TEST_PARAMS "${LIBCXX_TEST_PARAMS}" CACHE STRING "") diff --git a/libcxx/cmake/caches/Generic-cxx26.cmake b/libcxx/cmake/caches/Generic-cxx26.cmake index 2d9c018a4ff5..6ba9482af578 100644 --- a/libcxx/cmake/caches/Generic-cxx26.cmake +++ b/libcxx/cmake/caches/Generic-cxx26.cmake @@ -1,3 +1,2 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_TEST_PARAMS "std=c++26" CACHE STRING "") set(LIBCXXABI_TEST_PARAMS "${LIBCXX_TEST_PARAMS}" CACHE STRING "") diff --git a/libcxx/cmake/caches/Generic-hardening-mode-extensive.cmake b/libcxx/cmake/caches/Generic-hardening-mode-extensive.cmake index 9542dcdbf778..72263dfd8463 100644 --- a/libcxx/cmake/caches/Generic-hardening-mode-extensive.cmake +++ b/libcxx/cmake/caches/Generic-hardening-mode-extensive.cmake @@ -1,2 +1 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_HARDENING_MODE "extensive" CACHE STRING "") diff --git a/libcxx/cmake/caches/Generic-no-exceptions.cmake b/libcxx/cmake/caches/Generic-no-exceptions.cmake index c68adfc1276b..f0dffef60dba 100644 --- a/libcxx/cmake/caches/Generic-no-exceptions.cmake +++ b/libcxx/cmake/caches/Generic-no-exceptions.cmake @@ -1,3 +1,2 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_ENABLE_EXCEPTIONS OFF CACHE BOOL "") set(LIBCXXABI_ENABLE_EXCEPTIONS OFF CACHE BOOL "") diff --git a/libcxx/cmake/caches/Generic-no-experimental.cmake b/libcxx/cmake/caches/Generic-no-experimental.cmake index 62b7d7373d44..f33ed0141899 100644 --- a/libcxx/cmake/caches/Generic-no-experimental.cmake +++ b/libcxx/cmake/caches/Generic-no-experimental.cmake @@ -1,3 +1,2 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_TEST_PARAMS "enable_experimental=False" CACHE STRING "") set(LIBCXXABI_TEST_PARAMS "${LIBCXX_TEST_PARAMS}" CACHE STRING "") diff --git a/libcxx/cmake/caches/Generic-no-filesystem.cmake b/libcxx/cmake/caches/Generic-no-filesystem.cmake index 01ae7e68f12c..4000f3a3e8ef 100644 --- a/libcxx/cmake/caches/Generic-no-filesystem.cmake +++ b/libcxx/cmake/caches/Generic-no-filesystem.cmake @@ -1,2 +1 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_ENABLE_FILESYSTEM OFF CACHE BOOL "") diff --git a/libcxx/cmake/caches/Generic-no-localization.cmake b/libcxx/cmake/caches/Generic-no-localization.cmake index fc4957b2d53a..79d6b44c7139 100644 --- a/libcxx/cmake/caches/Generic-no-localization.cmake +++ b/libcxx/cmake/caches/Generic-no-localization.cmake @@ -1,2 +1 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_ENABLE_LOCALIZATION OFF CACHE BOOL "") diff --git a/libcxx/cmake/caches/Generic-no-random_device.cmake b/libcxx/cmake/caches/Generic-no-random_device.cmake index ddf479add626..e9b4cc60cc80 100644 --- a/libcxx/cmake/caches/Generic-no-random_device.cmake +++ b/libcxx/cmake/caches/Generic-no-random_device.cmake @@ -1,2 +1 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_ENABLE_RANDOM_DEVICE OFF CACHE BOOL "") diff --git a/libcxx/cmake/caches/Generic-no-threads.cmake b/libcxx/cmake/caches/Generic-no-threads.cmake index 724fbc466b58..616baef1be7b 100644 --- a/libcxx/cmake/caches/Generic-no-threads.cmake +++ b/libcxx/cmake/caches/Generic-no-threads.cmake @@ -1,4 +1,3 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_ENABLE_THREADS OFF CACHE BOOL "") set(LIBCXXABI_ENABLE_THREADS OFF CACHE BOOL "") set(LIBCXX_ENABLE_MONOTONIC_CLOCK OFF CACHE BOOL "") diff --git a/libcxx/cmake/caches/Generic-no-unicode.cmake b/libcxx/cmake/caches/Generic-no-unicode.cmake index a4cf7dd73772..01160bf21898 100644 --- a/libcxx/cmake/caches/Generic-no-unicode.cmake +++ b/libcxx/cmake/caches/Generic-no-unicode.cmake @@ -1,2 +1 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_ENABLE_UNICODE OFF CACHE BOOL "") diff --git a/libcxx/cmake/caches/Generic-no-wide-characters.cmake b/libcxx/cmake/caches/Generic-no-wide-characters.cmake index dc19389bb5ae..728d41086a38 100644 --- a/libcxx/cmake/caches/Generic-no-wide-characters.cmake +++ b/libcxx/cmake/caches/Generic-no-wide-characters.cmake @@ -1,2 +1 @@ -set(LIBCXX_INSTALL_MODULES ON CACHE BOOL "") # TODO MODULES Remove when enabled automatically. set(LIBCXX_ENABLE_WIDE_CHARACTERS OFF CACHE BOOL "") diff --git a/libcxx/docs/BuildingLibcxx.rst b/libcxx/docs/BuildingLibcxx.rst index a0a0cdb43397..e425b9dadfe7 100644 --- a/libcxx/docs/BuildingLibcxx.rst +++ b/libcxx/docs/BuildingLibcxx.rst @@ -208,7 +208,7 @@ libc++ specific options .. option:: LIBCXX_INSTALL_MODULES:BOOL - **Default**: ``OFF`` + **Default**: ``ON`` Toggle the installation of the experimental libc++ module sources. diff --git a/libcxx/docs/ReleaseNotes/19.rst b/libcxx/docs/ReleaseNotes/19.rst index 938ab76c6ecb..ac4fd0ecc122 100644 --- a/libcxx/docs/ReleaseNotes/19.rst +++ b/libcxx/docs/ReleaseNotes/19.rst @@ -149,3 +149,5 @@ Build System Changes - The Cmake variable ``LIBCXX_ENABLE_CLANG_TIDY`` has been removed. The build system has been changed to automatically detect the presence of ``clang-tidy`` and the required ``Clang`` libraries. + +- The CMake options ``LIBCXX_INSTALL_MODULES`` now defaults to ``ON``. -- GitLab From b6a8f5486bc12b132ec984bc8767506e3bcb6694 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sun, 28 Apr 2024 13:15:54 +0100 Subject: [PATCH 155/301] [LV] Consider all exit branch conditions uniform. If we vectorize a loop with multiple exits, all exiting branches should be considered uniform, as the resulting loop will be controlled by the canonical IV only. Previously we were overestimating the cost of values contributing to the other exits. --- .../Transforms/Vectorize/LoopVectorize.cpp | 18 ++++++---- .../LoopVectorize/AArch64/induction-costs.ll | 34 +++++++++---------- 2 files changed, 28 insertions(+), 24 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index 74ceb9eecf21..e2dd62619b01 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -4167,7 +4167,6 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { // Worklist containing uniform instructions demanding lane 0. SetVector Worklist; - BasicBlock *Latch = TheLoop->getLoopLatch(); // Add uniform instructions demanding lane 0 to the worklist. Instructions // that are scalar with predication must not be considered uniform after @@ -4189,12 +4188,16 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { Worklist.insert(I); }; - // Start with the conditional branch. If the branch condition is an - // instruction contained in the loop that is only used by the branch, it is - // uniform. - auto *Cmp = dyn_cast(Latch->getTerminator()->getOperand(0)); - if (Cmp && TheLoop->contains(Cmp) && Cmp->hasOneUse()) - addToWorklistIfAllowed(Cmp); + // Start with the conditional branches exiting the loop. If the branch + // condition is an instruction contained in the loop that is only used by the + // branch, it is uniform. + SmallVector Exiting; + TheLoop->getExitingBlocks(Exiting); + for (BasicBlock *E : Exiting) { + auto *Cmp = dyn_cast(E->getTerminator()->getOperand(0)); + if (Cmp && TheLoop->contains(Cmp) && Cmp->hasOneUse()) + addToWorklistIfAllowed(Cmp); + } auto PrevVF = VF.divideCoefficientBy(2); // Return true if all lanes perform the same memory operation, and we can @@ -4335,6 +4338,7 @@ void LoopVectorizationCostModel::collectLoopUniforms(ElementCount VF) { // nodes separately. An induction variable will remain uniform if all users // of the induction variable and induction variable update remain uniform. // The code below handles both pointer and non-pointer induction variables. + BasicBlock *Latch = TheLoop->getLoopLatch(); for (const auto &Induction : Legal->getInductionVars()) { auto *Ind = Induction.first; auto *IndUpdate = cast(Ind->getIncomingValueForBlock(Latch)); diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll index 03f8243a35af..4d9c850abdf3 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/induction-costs.ll @@ -9,37 +9,37 @@ define i32 @multi_exit_iv_uniform(i32 %a, i64 %N, ptr %dst) { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[UMIN:%.*]] = call i64 @llvm.umin.i64(i64 [[N]], i64 2147483648) ; CHECK-NEXT: [[TMP0:%.*]] = add nuw nsw i64 [[UMIN]], 1 -; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], 4 +; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ule i64 [[TMP0]], 8 ; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]] ; CHECK: vector.ph: -; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 4 +; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP0]], 8 ; CHECK-NEXT: [[TMP1:%.*]] = icmp eq i64 [[N_MOD_VF]], 0 -; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 4, i64 [[N_MOD_VF]] +; CHECK-NEXT: [[TMP2:%.*]] = select i1 [[TMP1]], i64 8, i64 [[N_MOD_VF]] ; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP0]], [[TMP2]] -; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <2 x i32> poison, i32 [[A]], i64 0 -; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <2 x i32> [[BROADCAST_SPLATINSERT]], <2 x i32> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[A]], i64 0 +; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: br label [[VECTOR_BODY:%.*]] ; CHECK: vector.body: ; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ] -; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <2 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP10:%.*]], [[VECTOR_BODY]] ] +; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi <4 x i32> [ zeroinitializer, [[VECTOR_PH]] ], [ [[TMP11:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP3:%.*]] = add i64 [[INDEX]], 0 -; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 2 +; CHECK-NEXT: [[TMP4:%.*]] = add i64 [[INDEX]], 4 ; CHECK-NEXT: [[TMP5:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP3]] ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr i64, ptr [[DST]], i64 [[TMP4]] -; CHECK-NEXT: [[TMP7:%.*]] = zext <2 x i32> [[BROADCAST_SPLAT]] to <2 x i64> +; CHECK-NEXT: [[TMP7:%.*]] = zext <4 x i32> [[BROADCAST_SPLAT]] to <4 x i64> ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr i64, ptr [[TMP5]], i32 0 -; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP5]], i32 2 -; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP8]], align 8 -; CHECK-NEXT: store <2 x i64> [[TMP7]], ptr [[TMP9]], align 8 -; CHECK-NEXT: [[TMP10]] = add <2 x i32> [[VEC_PHI]], -; CHECK-NEXT: [[TMP11]] = add <2 x i32> [[VEC_PHI1]], -; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4 +; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i64, ptr [[TMP5]], i32 4 +; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr [[TMP8]], align 8 +; CHECK-NEXT: store <4 x i64> [[TMP7]], ptr [[TMP9]], align 8 +; CHECK-NEXT: [[TMP10]] = add <4 x i32> [[VEC_PHI]], +; CHECK-NEXT: [[TMP11]] = add <4 x i32> [[VEC_PHI1]], +; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 8 ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] ; CHECK-NEXT: br i1 [[TMP12]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]] ; CHECK: middle.block: -; CHECK-NEXT: [[BIN_RDX:%.*]] = add <2 x i32> [[TMP11]], [[TMP10]] -; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v2i32(<2 x i32> [[BIN_RDX]]) +; CHECK-NEXT: [[BIN_RDX:%.*]] = add <4 x i32> [[TMP11]], [[TMP10]] +; CHECK-NEXT: [[TMP13:%.*]] = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> [[BIN_RDX]]) ; CHECK-NEXT: br label [[SCALAR_PH]] ; CHECK: scalar.ph: ; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ [[N_VEC]], [[MIDDLE_BLOCK]] ], [ 0, [[ENTRY:%.*]] ] -- GitLab From dc6ce60801ede0c6423470961d3728596ee46b04 Mon Sep 17 00:00:00 2001 From: Fabian Mora Date: Sun, 28 Apr 2024 10:03:12 -0400 Subject: [PATCH 156/301] [mlir][gpu] Remove `offloadingHandler` from `ModuleToBinary` (#90368) This patch removes the `offloadingHandler` option from the `ModuleToBinary` pass. The option is removed as it cannot be parsed from textual form. This fixes issue #90344. --- mlir/include/mlir/Dialect/GPU/Transforms/Passes.td | 2 -- mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp | 5 +---- 2 files changed, 1 insertion(+), 6 deletions(-) diff --git a/mlir/include/mlir/Dialect/GPU/Transforms/Passes.td b/mlir/include/mlir/Dialect/GPU/Transforms/Passes.td index a8235bed6f27..4a9ddafdd177 100644 --- a/mlir/include/mlir/Dialect/GPU/Transforms/Passes.td +++ b/mlir/include/mlir/Dialect/GPU/Transforms/Passes.td @@ -88,8 +88,6 @@ def GpuModuleToBinaryPass 4. `fatbinary`, `fatbin`: produces fatbinaries. }]; let options = [ - Option<"offloadingHandler", "handler", "Attribute", "nullptr", - "Offloading handler to be attached to the resulting binary op.">, Option<"toolkitPath", "toolkit", "std::string", [{""}], "Toolkit path.">, ListOption<"linkFiles", "l", "std::string", diff --git a/mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp b/mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp index 01613ab5268b..836e939a8295 100644 --- a/mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp +++ b/mlir/lib/Dialect/GPU/Transforms/ModuleToBinary.cpp @@ -88,10 +88,7 @@ void GpuModuleToBinaryPass::runOnOperation() { TargetOptions targetOptions(toolkitPath, linkFiles, cmdOptions, *targetFormat, lazyTableBuilder); if (failed(transformGpuModulesToBinaries( - getOperation(), - offloadingHandler ? dyn_cast( - offloadingHandler.getValue()) - : OffloadingLLVMTranslationAttrInterface(nullptr), + getOperation(), OffloadingLLVMTranslationAttrInterface(nullptr), targetOptions))) return signalPassFailure(); } -- GitLab From 4cec3b36f6d6c858992530fa5592824622ada9c7 Mon Sep 17 00:00:00 2001 From: Renato Golin Date: Sun, 28 Apr 2024 15:25:24 +0100 Subject: [PATCH 157/301] [MLIR][Linalg] More Linalg named ops (#90236) Adding `min` that was already implemented but not exposed. Adding a few additional unary ops: * Reciprocal as `arith.div(1,arg)` * Round as `math.round(arg)` * Sqrt as `math.sqrt(arg)` * Rsqrt as `math.rsqrt(arg)` * Square as `math.powf(arg, 2)` * TanH as `math.tanh(arg)` All with the agreed semantics at the round table: no implicit broadcast/type cast. --- .../mlir/Dialect/Linalg/IR/LinalgEnums.td | 8 +- .../Linalg/IR/LinalgNamedStructuredOps.yaml | 261 +++++++++++++++++- mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 16 ++ .../linalg/opdsl/lang/comprehension.py | 5 + .../linalg/opdsl/ops/core_named_ops.py | 81 +++++- .../Dialect/Linalg/generalize-named-ops.mlir | 153 ++++++++++ mlir/test/Dialect/Linalg/named-ops-fail.mlir | 112 ++++++++ mlir/test/Dialect/Linalg/named-ops.mlir | 220 +++++++++++++++ 8 files changed, 853 insertions(+), 3 deletions(-) diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td index 59f909aed8f6..7a350d2c0142 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td @@ -22,7 +22,13 @@ def UnaryFn : I32EnumAttr<"UnaryFn", "", [ I32EnumAttrCase<"abs", 2>, I32EnumAttrCase<"ceil", 3>, I32EnumAttrCase<"floor", 4>, - I32EnumAttrCase<"negf", 5> + I32EnumAttrCase<"negf", 5>, + I32EnumAttrCase<"reciprocal", 6>, + I32EnumAttrCase<"round", 7>, + I32EnumAttrCase<"sqrt", 8>, + I32EnumAttrCase<"rsqrt", 9>, + I32EnumAttrCase<"square", 10>, + I32EnumAttrCase<"tanh", 11> ]> { let genSpecializedAttr = 0; let cppNamespace = "::mlir::linalg"; diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml b/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml index 1ff6c4086cf3..b75675773475 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml @@ -304,6 +304,216 @@ structured_op: !LinalgStructuredOpConfig - !ScalarExpression scalar_arg: I --- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: reciprocal + cpp_class_name: ReciprocalOp + doc: |- + Applies reciprocal(x) elementwise. + + No numeric casting is performed on the input operand. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: I + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: unary + fn_name: reciprocal + operands: + - !ScalarExpression + scalar_arg: I +--- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: round + cpp_class_name: RoundOp + doc: |- + Applies round(x) elementwise. + + No numeric casting is performed on the input operand. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: I + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: unary + fn_name: round + operands: + - !ScalarExpression + scalar_arg: I +--- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: sqrt + cpp_class_name: SqrtOp + doc: |- + Applies sqrt(x) elementwise. + + No numeric casting is performed on the input operand. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: I + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: unary + fn_name: sqrt + operands: + - !ScalarExpression + scalar_arg: I +--- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: rsqrt + cpp_class_name: RsqrtOp + doc: |- + Applies rsqrt(x) elementwise. + + No numeric casting is performed on the input operand. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: I + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: unary + fn_name: rsqrt + operands: + - !ScalarExpression + scalar_arg: I +--- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: square + cpp_class_name: SquareOp + doc: |- + Applies square(x) elementwise. + + No numeric casting is performed on the input operand. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: I + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: unary + fn_name: square + operands: + - !ScalarExpression + scalar_arg: I +--- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: tanh + cpp_class_name: TanhOp + doc: |- + Applies tanh(x) elementwise. + + No numeric casting is performed on the input operand. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: I + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: unary + fn_name: tanh + operands: + - !ScalarExpression + scalar_arg: I +--- !LinalgOpConfig metadata: !LinalgOpMetadata name: elemwise_binary cpp_class_name: ElemwiseBinaryOp @@ -625,7 +835,7 @@ metadata: !LinalgOpMetadata This means reduction/broadcast/element cast semantics is explicit. Further passes can take that into account when lowering this code. For example, - a `linalg.broadcast` + `linalg.div` sequence can be lowered to a + a `linalg.broadcast` + `linalg.max` sequence can be lowered to a `linalg.generic` with different affine maps for the two operands. structured_op: !LinalgStructuredOpConfig args: @@ -663,6 +873,55 @@ structured_op: !LinalgStructuredOpConfig - !ScalarExpression scalar_arg: rhs --- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: min + cpp_class_name: MinOp + doc: |- + Takes the min (signed) between two inputs, elementwise. + + The shapes and element types must be identical. The appropriate casts, + broadcasts and reductions should be done previously to calling this op. + + This means reduction/broadcast/element cast semantics is explicit. Further + passes can take that into account when lowering this code. For example, + a `linalg.broadcast` + `linalg.min` sequence can be lowered to a + `linalg.generic` with different affine maps for the two operands. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: lhs + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: rhs + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: binary + fn_name: min_signed + operands: + - !ScalarExpression + scalar_arg: lhs + - !ScalarExpression + scalar_arg: rhs +--- !LinalgOpConfig metadata: !LinalgOpMetadata name: matmul cpp_class_name: MatmulOp diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp index 9c5c58fa1fab..5d10b59373ad 100644 --- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp +++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp @@ -395,6 +395,22 @@ public: return builder.create(arg.getLoc(), arg); case UnaryFn::negf: return builder.create(arg.getLoc(), arg); + case UnaryFn::reciprocal: { + Attribute oneAttr = builder.getOneAttr(arg.getType()); + auto one = builder.create(arg.getLoc(), + ::cast(oneAttr)); + return builder.create(arg.getLoc(), one, arg); + } + case UnaryFn::round: + return builder.create(arg.getLoc(), arg); + case UnaryFn::sqrt: + return builder.create(arg.getLoc(), arg); + case UnaryFn::rsqrt: + return builder.create(arg.getLoc(), arg); + case UnaryFn::square: + return builder.create(arg.getLoc(), arg, arg); + case UnaryFn::tanh: + return builder.create(arg.getLoc(), arg); } llvm_unreachable("unsupported unary function"); } diff --git a/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py b/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py index 23d6d26b7e29..f7bc81bd2f68 100644 --- a/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py +++ b/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py @@ -291,6 +291,11 @@ class UnaryFn: ceil = UnaryFnType("ceil") floor = UnaryFnType("floor") negf = UnaryFnType("negf") + round = UnaryFnType("round") + sqrt = UnaryFnType("sqrt") + rsqrt = UnaryFnType("rsqrt") + square = UnaryFnType("square") + tanh = UnaryFnType("tanh") class BinaryFnType: diff --git a/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py b/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py index 5b05364f6d35..2c8864be1107 100644 --- a/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py +++ b/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py @@ -108,6 +108,66 @@ def negf( O[None] = UnaryFn.negf(I[None]) +@linalg_structured_op +def round( + I=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Applies round(x) elementwise. + + No numeric casting is performed on the input operand. + """ + O[None] = UnaryFn.round(I[None]) + + +@linalg_structured_op +def sqrt( + I=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Applies sqrt(x) elementwise. + + No numeric casting is performed on the input operand. + """ + O[None] = UnaryFn.sqrt(I[None]) + + +@linalg_structured_op +def rsqrt( + I=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Applies rsqrt(x) elementwise. + + No numeric casting is performed on the input operand. + """ + O[None] = UnaryFn.rsqrt(I[None]) + + +@linalg_structured_op +def square( + I=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Applies square(x) elementwise. + + No numeric casting is performed on the input operand. + """ + O[None] = UnaryFn.square(I[None]) + + +@linalg_structured_op +def tanh( + I=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Applies tanh(x) elementwise. + + No numeric casting is performed on the input operand. + """ + O[None] = UnaryFn.tanh(I[None]) + + @linalg_structured_op def elemwise_binary( lhs=TensorDef(T1), @@ -233,12 +293,31 @@ def max( This means reduction/broadcast/element cast semantics is explicit. Further passes can take that into account when lowering this code. For example, - a `linalg.broadcast` + `linalg.div` sequence can be lowered to a + a `linalg.broadcast` + `linalg.max` sequence can be lowered to a `linalg.generic` with different affine maps for the two operands. """ O[None] = BinaryFn.max_signed(lhs[None], rhs[None]) +@linalg_structured_op +def min( + lhs=TensorDef(T1), + rhs=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Takes the min (signed) between two inputs, elementwise. + + The shapes and element types must be identical. The appropriate casts, + broadcasts and reductions should be done previously to calling this op. + + This means reduction/broadcast/element cast semantics is explicit. Further + passes can take that into account when lowering this code. For example, + a `linalg.broadcast` + `linalg.min` sequence can be lowered to a + `linalg.generic` with different affine maps for the two operands. + """ + O[None] = BinaryFn.min_signed(lhs[None], rhs[None]) + + @linalg_structured_op def matmul( A=TensorDef(T1, S.M, S.K), diff --git a/mlir/test/Dialect/Linalg/generalize-named-ops.mlir b/mlir/test/Dialect/Linalg/generalize-named-ops.mlir index e852824cdb73..add34412b92f 100644 --- a/mlir/test/Dialect/Linalg/generalize-named-ops.mlir +++ b/mlir/test/Dialect/Linalg/generalize-named-ops.mlir @@ -565,6 +565,134 @@ func.func @generalize_negf(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) // ----- +func.func @generalize_reciprocal(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { + linalg.reciprocal ins(%arg : memref<7x14x21xf32>) outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_reciprocal +// CHECK-SAME: (%[[ARG:.+]]: memref<7x14x21xf32>, %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: %[[one:.+]] = arith.constant 1.000000e+00 : f32 + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]] : memref<7x14x21xf32>) outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32) +// CHECK-NEXT: %[[reciprocal:.+]] = arith.divf %[[one]], %[[BBARG0]] : f32 +// CHECK-NEXT: linalg.yield %[[reciprocal]] : f32 + +// ----- + +func.func @generalize_round(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { + linalg.round ins(%arg : memref<7x14x21xf32>) outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_round +// CHECK-SAME: (%[[ARG:.+]]: memref<7x14x21xf32>, %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]] : memref<7x14x21xf32>) outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32) +// CHECK-NEXT: %[[round:.+]] = math.round %[[BBARG0]] : f32 +// CHECK-NEXT: linalg.yield %[[round]] : f32 + +// ----- + +func.func @generalize_sqrt(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { + linalg.sqrt ins(%arg : memref<7x14x21xf32>) outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_sqrt +// CHECK-SAME: (%[[ARG:.+]]: memref<7x14x21xf32>, %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]] : memref<7x14x21xf32>) outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32) +// CHECK-NEXT: %[[sqrt:.+]] = math.sqrt %[[BBARG0]] : f32 +// CHECK-NEXT: linalg.yield %[[sqrt]] : f32 + +// ----- + +func.func @generalize_rsqrt(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { + linalg.rsqrt ins(%arg : memref<7x14x21xf32>) outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_rsqrt +// CHECK-SAME: (%[[ARG:.+]]: memref<7x14x21xf32>, %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]] : memref<7x14x21xf32>) outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32) +// CHECK-NEXT: %[[rsqrt:.+]] = math.rsqrt %[[BBARG0]] : f32 +// CHECK-NEXT: linalg.yield %[[rsqrt]] : f32 + +// ----- + +func.func @generalize_square(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { + linalg.square ins(%arg : memref<7x14x21xf32>) outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_square +// CHECK-SAME: (%[[ARG:.+]]: memref<7x14x21xf32>, %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]] : memref<7x14x21xf32>) outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32) +// CHECK-NEXT: %[[square:.+]] = arith.mulf %[[BBARG0]], %[[BBARG0]] : f32 +// CHECK-NEXT: linalg.yield %[[square]] : f32 + +// ----- + +func.func @generalize_tanh(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { + linalg.tanh ins(%arg : memref<7x14x21xf32>) outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_tanh +// CHECK-SAME: (%[[ARG:.+]]: memref<7x14x21xf32>, %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]] : memref<7x14x21xf32>) outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32) +// CHECK-NEXT: %[[tanh:.+]] = math.tanh %[[BBARG0]] : f32 +// CHECK-NEXT: linalg.yield %[[tanh]] : f32 + +// ----- + func.func @generalize_max(%lhs: memref<7x14x21xf32>, %rhs: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { linalg.max ins(%lhs, %rhs : memref<7x14x21xf32>, memref<7x14x21xf32>) @@ -590,6 +718,31 @@ func.func @generalize_max(%lhs: memref<7x14x21xf32>, %rhs: memref<7x14x21xf32>, // ----- +func.func @generalize_min(%lhs: memref<7x14x21xf32>, %rhs: memref<7x14x21xf32>, + %out: memref<7x14x21xf32>) { + linalg.min ins(%lhs, %rhs : memref<7x14x21xf32>, memref<7x14x21xf32>) + outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_min +// CHECK-SAME: (%[[LHS:.+]]: memref<7x14x21xf32>, %[[RHS:.+]]: memref<7x14x21xf32>, +// CHECK-SAME: %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]], %[[RHS]] : memref<7x14x21xf32>, memref<7x14x21xf32>) +// CHECK-SAME: outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32, %[[BBARG2:.+]]: f32) +// CHECK-NEXT: %[[min:.+]] = arith.minimumf %[[BBARG0]], %[[BBARG1]] : f32 +// CHECK-NEXT: linalg.yield %[[min]] : f32 + +// ----- + // CHECK-LABEL: func @fill_tensor func.func @fill_tensor(%f: f32, %v: vector<2x4xf32>) -> (tensor, tensor>) { diff --git a/mlir/test/Dialect/Linalg/named-ops-fail.mlir b/mlir/test/Dialect/Linalg/named-ops-fail.mlir index c351e139a97e..f66608e71ffc 100644 --- a/mlir/test/Dialect/Linalg/named-ops-fail.mlir +++ b/mlir/test/Dialect/Linalg/named-ops-fail.mlir @@ -176,6 +176,102 @@ func.func @negf_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { // ----- +func.func @reciprocal_type_cast(%arg: memref<4x8x16xf16>, %out: memref<4x8x16xf32>) { + // CHECK: operand 1 ('f16') doesn't match the element type of the enclosing linalg.generic op ('f32') + linalg.reciprocal ins(%arg : memref<4x8x16xf16>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @reciprocal_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.reciprocal ins(%arg : memref<8x16xf32>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @round_type_cast(%arg: memref<4x8x16xf16>, %out: memref<4x8x16xf32>) { + // CHECK: operand 1 ('f16') doesn't match the element type of the enclosing linalg.generic op ('f32') + linalg.round ins(%arg : memref<4x8x16xf16>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @round_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.round ins(%arg : memref<8x16xf32>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @sqrt_type_cast(%arg: memref<4x8x16xf16>, %out: memref<4x8x16xf32>) { + // CHECK: operand 1 ('f16') doesn't match the element type of the enclosing linalg.generic op ('f32') + linalg.sqrt ins(%arg : memref<4x8x16xf16>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @sqrt_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.sqrt ins(%arg : memref<8x16xf32>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @rsqrt_type_cast(%arg: memref<4x8x16xf16>, %out: memref<4x8x16xf32>) { + // CHECK: operand 1 ('f16') doesn't match the element type of the enclosing linalg.generic op ('f32') + linalg.rsqrt ins(%arg : memref<4x8x16xf16>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @rsqrt_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.rsqrt ins(%arg : memref<8x16xf32>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @square_type_cast(%arg: memref<4x8x16xf16>, %out: memref<4x8x16xf32>) { + // CHECK: operand 1 ('f16') doesn't match the element type of the enclosing linalg.generic op ('f32') + linalg.square ins(%arg : memref<4x8x16xf16>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @square_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.square ins(%arg : memref<8x16xf32>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @tanh_type_cast(%arg: memref<4x8x16xf16>, %out: memref<4x8x16xf32>) { + // CHECK: operand 1 ('f16') doesn't match the element type of the enclosing linalg.generic op ('f32') + linalg.tanh ins(%arg : memref<4x8x16xf16>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @tanh_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.tanh ins(%arg : memref<8x16xf32>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + func.func @max_type_cast(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf16>, %arg2: memref<4x8x16xf32>) { // CHECK: op requires the same type for all operands and results linalg.max ins(%arg0, %arg1 : memref<4x8x16xf32>, memref<4x8x16xf16>) outs(%arg2: memref<4x8x16xf32>) @@ -189,3 +285,19 @@ func.func @max_broadcast(%arg0: memref<8x16xf32>, %arg1: memref<4x8x16xf32>, %ar linalg.max ins(%arg0, %arg1 : memref<8x16xf32>, memref<4x8x16xf32>) outs(%arg2: memref<4x8x16xf32>) return } + +// ----- + +func.func @min_type_cast(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf16>, %arg2: memref<4x8x16xf32>) { + // CHECK: op requires the same type for all operands and results + linalg.min ins(%arg0, %arg1 : memref<4x8x16xf32>, memref<4x8x16xf16>) outs(%arg2: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @min_broadcast(%arg0: memref<8x16xf32>, %arg1: memref<4x8x16xf32>, %arg2: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.min ins(%arg0, %arg1 : memref<8x16xf32>, memref<4x8x16xf32>) outs(%arg2: memref<4x8x16xf32>) + return +} diff --git a/mlir/test/Dialect/Linalg/named-ops.mlir b/mlir/test/Dialect/Linalg/named-ops.mlir index 7064e1b3f9dc..cf59f6736100 100644 --- a/mlir/test/Dialect/Linalg/named-ops.mlir +++ b/mlir/test/Dialect/Linalg/named-ops.mlir @@ -1597,6 +1597,192 @@ func.func @negf_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { // ----- +// CHECK-LABEL: func @reciprocal_dynamic +func.func @reciprocal_dynamic(%arg0: memref, %arg1: memref) { + // CHECK: linalg.reciprocal + // CHECK-SAME: ins(%{{.+}} : memref) outs(%{{.+}} : memref) + linalg.reciprocal ins(%arg0 : memref) outs(%arg1: memref) + return +} + +// ----- + +// CHECK-LABEL: func @reciprocal_static +func.func @reciprocal_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>) { + // CHECK: linalg.reciprocal + // CHECK-SAME: ins(%{{.+}} : memref<4x8x16xf32>) outs(%{{.+}} : memref<4x8x16xf32>) + linalg.reciprocal ins(%arg0 : memref<4x8x16xf32>) outs(%arg1: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @reciprocal_tensor +func.func @reciprocal_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.reciprocal + // CHECK-SAME: ins(%{{.+}} : tensor<4x8x16xf32>) outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.reciprocal ins(%arg0 : tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + +// CHECK-LABEL: func @round_dynamic +func.func @round_dynamic(%arg0: memref, %arg1: memref) { + // CHECK: linalg.round + // CHECK-SAME: ins(%{{.+}} : memref) outs(%{{.+}} : memref) + linalg.round ins(%arg0 : memref) outs(%arg1: memref) + return +} + +// ----- + +// CHECK-LABEL: func @round_static +func.func @round_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>) { + // CHECK: linalg.round + // CHECK-SAME: ins(%{{.+}} : memref<4x8x16xf32>) outs(%{{.+}} : memref<4x8x16xf32>) + linalg.round ins(%arg0 : memref<4x8x16xf32>) outs(%arg1: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @round_tensor +func.func @round_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.round + // CHECK-SAME: ins(%{{.+}} : tensor<4x8x16xf32>) outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.round ins(%arg0 : tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + +// CHECK-LABEL: func @sqrt_dynamic +func.func @sqrt_dynamic(%arg0: memref, %arg1: memref) { + // CHECK: linalg.sqrt + // CHECK-SAME: ins(%{{.+}} : memref) outs(%{{.+}} : memref) + linalg.sqrt ins(%arg0 : memref) outs(%arg1: memref) + return +} + +// ----- + +// CHECK-LABEL: func @sqrt_static +func.func @sqrt_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>) { + // CHECK: linalg.sqrt + // CHECK-SAME: ins(%{{.+}} : memref<4x8x16xf32>) outs(%{{.+}} : memref<4x8x16xf32>) + linalg.sqrt ins(%arg0 : memref<4x8x16xf32>) outs(%arg1: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @sqrt_tensor +func.func @sqrt_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.sqrt + // CHECK-SAME: ins(%{{.+}} : tensor<4x8x16xf32>) outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.sqrt ins(%arg0 : tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + +// CHECK-LABEL: func @rsqrt_dynamic +func.func @rsqrt_dynamic(%arg0: memref, %arg1: memref) { + // CHECK: linalg.rsqrt + // CHECK-SAME: ins(%{{.+}} : memref) outs(%{{.+}} : memref) + linalg.rsqrt ins(%arg0 : memref) outs(%arg1: memref) + return +} + +// ----- + +// CHECK-LABEL: func @rsqrt_static +func.func @rsqrt_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>) { + // CHECK: linalg.rsqrt + // CHECK-SAME: ins(%{{.+}} : memref<4x8x16xf32>) outs(%{{.+}} : memref<4x8x16xf32>) + linalg.rsqrt ins(%arg0 : memref<4x8x16xf32>) outs(%arg1: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @rsqrt_tensor +func.func @rsqrt_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.rsqrt + // CHECK-SAME: ins(%{{.+}} : tensor<4x8x16xf32>) outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.rsqrt ins(%arg0 : tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + +// CHECK-LABEL: func @square_dynamic +func.func @square_dynamic(%arg0: memref, %arg1: memref) { + // CHECK: linalg.square + // CHECK-SAME: ins(%{{.+}} : memref) outs(%{{.+}} : memref) + linalg.square ins(%arg0 : memref) outs(%arg1: memref) + return +} + +// ----- + +// CHECK-LABEL: func @square_static +func.func @square_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>) { + // CHECK: linalg.square + // CHECK-SAME: ins(%{{.+}} : memref<4x8x16xf32>) outs(%{{.+}} : memref<4x8x16xf32>) + linalg.square ins(%arg0 : memref<4x8x16xf32>) outs(%arg1: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @square_tensor +func.func @square_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.square + // CHECK-SAME: ins(%{{.+}} : tensor<4x8x16xf32>) outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.square ins(%arg0 : tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + +// CHECK-LABEL: func @tanh_dynamic +func.func @tanh_dynamic(%arg0: memref, %arg1: memref) { + // CHECK: linalg.tanh + // CHECK-SAME: ins(%{{.+}} : memref) outs(%{{.+}} : memref) + linalg.tanh ins(%arg0 : memref) outs(%arg1: memref) + return +} + +// ----- + +// CHECK-LABEL: func @tanh_static +func.func @tanh_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>) { + // CHECK: linalg.tanh + // CHECK-SAME: ins(%{{.+}} : memref<4x8x16xf32>) outs(%{{.+}} : memref<4x8x16xf32>) + linalg.tanh ins(%arg0 : memref<4x8x16xf32>) outs(%arg1: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @tanh_tensor +func.func @tanh_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.tanh + // CHECK-SAME: ins(%{{.+}} : tensor<4x8x16xf32>) outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.tanh ins(%arg0 : tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + // CHECK-LABEL: func @max_dynamic func.func @max_dynamic(%arg0: memref, %arg1: memref, %arg2: memref) { // CHECK: linalg.max @@ -1631,6 +1817,40 @@ func.func @max_tensor(%arg0: tensor<4x8x16xf32>, %arg1: tensor<4x8x16xf32>) -> t // ----- +// CHECK-LABEL: func @min_dynamic +func.func @min_dynamic(%arg0: memref, %arg1: memref, %arg2: memref) { + // CHECK: linalg.min + // CHECK-SAME: ins(%{{.+}}, %{{.+}} : memref, memref) + // CHECK-SAME: outs(%{{.+}} : memref) + linalg.min ins(%arg0, %arg1 : memref, memref) outs(%arg2: memref) + return +} + +// ----- + +// CHECK-LABEL: func @min_static +func.func @min_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>, %arg2: memref<4x8x16xf32>) { + // CHECK: linalg.min + // CHECK-SAME: ins(%{{.+}}, %{{.+}} : memref<4x8x16xf32>, memref<4x8x16xf32>) + // CHECK-SAME: outs(%{{.+}} : memref<4x8x16xf32>) + linalg.min ins(%arg0, %arg1 : memref<4x8x16xf32>, memref<4x8x16xf32>) outs(%arg2: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @min_tensor +func.func @min_tensor(%arg0: tensor<4x8x16xf32>, %arg1: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.min + // CHECK-SAME: ins(%{{.+}}, %{{.+}} : tensor<4x8x16xf32>, tensor<4x8x16xf32>) + // CHECK-SAME: outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.min ins(%arg0, %arg1 : tensor<4x8x16xf32>, tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + // CHECK-LABEL: func @fill_tensor func.func @fill_tensor(%f: f32, %v: vector<2x4xf32>) -> (tensor, tensor>) { %e0 = tensor.empty() : tensor -- GitLab From 256d76f48060a353ba3bb885698e2ba8d1c87ec6 Mon Sep 17 00:00:00 2001 From: Sameer Sahasrabuddhe Date: Sun, 28 Apr 2024 19:56:14 +0530 Subject: [PATCH 158/301] [Docs] Improve the description of convergence (#89038) - Clarify convergence of threads v/s convergence of operations. - Explicitly address operations that are not in any cycle. This was inspired by a discussion on Discourse: https://discourse.llvm.org/t/llvm-convergence-semantics/77642 --- llvm/docs/ConvergenceAndUniformity.rst | 122 ++++++++++++++----------- llvm/docs/ConvergentOperations.rst | 3 +- 2 files changed, 71 insertions(+), 54 deletions(-) diff --git a/llvm/docs/ConvergenceAndUniformity.rst b/llvm/docs/ConvergenceAndUniformity.rst index 0e97595508f9..863cebd91a20 100644 --- a/llvm/docs/ConvergenceAndUniformity.rst +++ b/llvm/docs/ConvergenceAndUniformity.rst @@ -10,34 +10,61 @@ Convergence And Uniformity Introduction ============ -Some parallel environments execute threads in groups that allow -communication within the group using special primitives called -*convergent* operations. The outcome of a convergent operation is -sensitive to the set of threads that executes it "together", i.e., -convergently. - -A value is said to be *uniform* across a set of threads if it is the -same across those threads, and *divergent* otherwise. Correspondingly, -a branch is said to be a uniform branch if its condition is uniform, -and it is a divergent branch otherwise. - -Whether threads are *converged* or not depends on the paths they take -through the control flow graph. Threads take different outgoing edges -at a *divergent branch*. Divergent branches constrain +In some environments, groups of threads execute the same program in parallel, +where efficient communication within a group is established using special +primitives called :ref:`convergent operations`. The +outcome of a convergent operation is sensitive to the set of threads that +participate in it. + +The intuitive picture of *convergence* is built around threads executing in +"lock step" --- a set of threads is thought of as *converged* if they are all +executing "the same sequence of instructions together". Such threads may +*diverge* at a *divergent branch*, and they may later *reconverge* at some +common program point. + +In this intuitive picture, when converged threads execute an instruction, the +resulting value is said to be *uniform* if it is the same in those threads, and +*divergent* otherwise. Correspondingly, a branch is said to be a uniform branch +if its condition is uniform, and it is a divergent branch otherwise. + +But the assumption of lock-step execution is not necessary for describing +communication at convergent operations. It also constrains the implementation +(compiler as well as hardware) by overspecifying how threads execute in such a +parallel environment. To eliminate this assumption: + +- We define convergence as a relation between the execution of each instruction + by different threads and not as a relation between the threads themselves. + This definition is reasonable for known targets and is compatible with the + semantics of :ref:`convergent operations` in LLVM IR. +- We also define uniformity in terms of this convergence. The output of an + instruction can be examined for uniformity across multiple threads only if the + corresponding executions of that instruction are converged. + +This document decribes a static analysis for determining convergence at each +instruction in a function. The analysis extends previous work on divergence +analysis [DivergenceSPMD]_ to cover irreducible control-flow. The described +analysis is used in LLVM to implement a UniformityAnalysis that determines the +uniformity of value(s) computed at each instruction in an LLVM IR or MIR +function. + +.. [DivergenceSPMD] Julian Rosemann, Simon Moll, and Sebastian + Hack. 2021. An Abstract Interpretation for SPMD Divergence on + Reducible Control Flow Graphs. Proc. ACM Program. Lang. 5, POPL, + Article 31 (January 2021), 35 pages. + https://doi.org/10.1145/3434312 + +Motivation +========== + +Divergent branches constrain program transforms such as changing the CFG or moving a convergent operation to a different point of the CFG. Performing these transformations across a divergent branch can change the sets of threads that execute convergent operations convergently. While these -constraints are out of scope for this document, the described -*uniformity analysis* allows these transformations to identify +constraints are out of scope for this document, +uniformity analysis allows these transformations to identify uniform branches where these constraints do not hold. -Convergence and -uniformity are inter-dependent: When threads diverge at a divergent -branch, they may later *reconverge* at a common program point. -Subsequent operations are performed convergently, but the inputs may -be non-uniform, thus producing divergent outputs. - Uniformity is also useful by itself on targets that execute threads in groups with shared execution resources (e.g. waves, warps, or subgroups): @@ -50,18 +77,6 @@ subgroups): branches, since the whole group of threads follows either one side of the branch or the other. -This document presents a definition of convergence that is reasonable -for real targets and is compatible with the currently implicit -semantics of convergent operations in LLVM IR. This is accompanied by -a *uniformity analysis* that extends previous work on divergence analysis -[DivergenceSPMD]_ to cover irreducible control-flow. - -.. [DivergenceSPMD] Julian Rosemann, Simon Moll, and Sebastian - Hack. 2021. An Abstract Interpretation for SPMD Divergence on - Reducible Control Flow Graphs. Proc. ACM Program. Lang. 5, POPL, - Article 31 (January 2021), 35 pages. - https://doi.org/10.1145/3434312 - Terminology =========== @@ -133,12 +148,6 @@ meaning. Dynamic instances listed in the same column are converged. Convergence =========== -*Converged-with* is a transitive symmetric relation over dynamic -instances produced by *different threads* for the *same static -instance*. Informally, two threads that produce converged dynamic -instances are said to be *converged*, and they are said to execute -that static instance *convergently*, at that point in the execution. - *Convergence-before* is a strict partial order over dynamic instances that is defined as the transitive closure of: @@ -171,11 +180,16 @@ to be converged (i.e., related to each other in the converged-with relation). The resulting convergence order includes the edges ``P -> Q2``, ``Q1 -> R``, ``P -> R``, ``P -> T``, etc. -The fact that *convergence-before* is a strict partial order is a -constraint on the *converged-with* relation. It is trivially satisfied -if different dynamic instances are never converged. It is also -trivially satisfied for all known implementations for which -convergence plays some role. +*Converged-with* is a transitive symmetric relation over dynamic instances +produced by *different threads* for the *same static instance*. + +It is impractical to provide any one definition for the *converged-with* +relation, since different environments may wish to relate dynamic instances in +different ways. The fact that *convergence-before* is a strict partial order is +a constraint on the *converged-with* relation. It is trivially satisfied if +different dynamic instances are never converged. Below, we provide a relation +called :ref:`maximal converged-with`, which satisifies +*convergence-before* and is suitable for known targets. .. _convergence-note-convergence: @@ -217,14 +231,16 @@ iterations of parent cycles as well. Dynamic instances ``X1`` and ``X2`` produced by different threads for the same static instance ``X`` are converged in the maximal - converged-with relation if and only if for every cycle ``C`` with - header ``H`` that contains ``X``: - - - every dynamic instance ``H1`` of ``H`` that precedes ``X1`` in - the respective thread is convergence-before ``X2``, and, - - every dynamic instance ``H2`` of ``H`` that precedes ``X2`` in - the respective thread is convergence-before ``X1``, - - without assuming that ``X1`` is converged with ``X2``. + converged-with relation if and only if: + + - ``X`` is not contained in any cycle, or, + - For every cycle ``C`` with header ``H`` that contains ``X``: + + - every dynamic instance ``H1`` of ``H`` that precedes ``X1`` in + the respective thread is convergence-before ``X2``, and, + - every dynamic instance ``H2`` of ``H`` that precedes ``X2`` in + the respective thread is convergence-before ``X1``, + - without assuming that ``X1`` is converged with ``X2``. .. note:: diff --git a/llvm/docs/ConvergentOperations.rst b/llvm/docs/ConvergentOperations.rst index 332675f3edef..5081efffc89a 100644 --- a/llvm/docs/ConvergentOperations.rst +++ b/llvm/docs/ConvergentOperations.rst @@ -936,7 +936,8 @@ property ` of static instances in the convergence region of 1. Both threads executed converged dynamic instances of every token definition ``D`` such that ``X`` is in the convergence region of ``D``, and, - 2. For every cycle ``C`` with header ``H`` that contains ``X``: + 2. Either ``X`` is not contained in any cycle, or, for every cycle ``C`` + with header ``H`` that contains ``X``: - every dynamic instance ``H1`` of ``H`` that precedes ``X1`` in the respective thread is convergence-before ``X2``, and, -- GitLab From 98001a662c28c7e7d36b13be3073d41dbcd961b0 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 28 Apr 2024 16:59:02 +0100 Subject: [PATCH 159/301] [X86] Fix tabs/spaces typo. NFC. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index f0cec6224e84..82d3859225fd 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -45272,7 +45272,7 @@ static SDValue commuteSelect(SDNode *N, SelectionDAG &DAG, ISD::getSetCCInverse(cast(Cond.getOperand(2))->get(), Cond.getOperand(0).getValueType()); Cond = DAG.getSetCC(SDLoc(Cond), Cond.getValueType(), Cond.getOperand(0), - Cond.getOperand(1), NewCC); + Cond.getOperand(1), NewCC); return DAG.getSelect(DL, LHS.getValueType(), Cond, RHS, LHS); } -- GitLab From a1aea37fd1fe6a61342f6ca672581c3641efaaeb Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Sun, 28 Apr 2024 17:25:39 +0100 Subject: [PATCH 160/301] [X86] cmp.ll - update check prefixes to share common CHECK Split ndd/no-ndd check prefix cases --- llvm/test/CodeGen/X86/cmp.ll | 570 +++++++++++------------------------ 1 file changed, 182 insertions(+), 388 deletions(-) diff --git a/llvm/test/CodeGen/X86/cmp.ll b/llvm/test/CodeGen/X86/cmp.ll index 30e52f063075..402da547613c 100644 --- a/llvm/test/CodeGen/X86/cmp.ll +++ b/llvm/test/CodeGen/X86/cmp.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd -show-mc-encoding | FileCheck --check-prefix=NDD %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -show-mc-encoding | FileCheck %s --check-prefixes=CHECK,NO-NDD +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+ndd -show-mc-encoding | FileCheck --check-prefixes=CHECK,NDD %s @d = dso_local global i8 0, align 1 @d64 = dso_local global i64 0 @@ -17,18 +17,6 @@ define i32 @test1(i32 %X, ptr %y) nounwind { ; CHECK-NEXT: .LBB0_2: # %ReturnBlock ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: test1: -; NDD: # %bb.0: # %entry -; NDD-NEXT: cmpl $0, (%rsi) # encoding: [0x83,0x3e,0x00] -; NDD-NEXT: je .LBB0_2 # encoding: [0x74,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB0_2-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.1: # %cond_true -; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00] -; NDD-NEXT: retq # encoding: [0xc3] -; NDD-NEXT: .LBB0_2: # %ReturnBlock -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] entry: %tmp = load i32, ptr %y %tmp.upgrd.1 = icmp eq i32 %tmp, 0 @@ -54,19 +42,6 @@ define i32 @test2(i32 %X, ptr %y) nounwind { ; CHECK-NEXT: .LBB1_2: # %ReturnBlock ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: test2: -; NDD: # %bb.0: # %entry -; NDD-NEXT: testl $536870911, (%rsi) # encoding: [0xf7,0x06,0xff,0xff,0xff,0x1f] -; NDD-NEXT: # imm = 0x1FFFFFFF -; NDD-NEXT: je .LBB1_2 # encoding: [0x74,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB1_2-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.1: # %cond_true -; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00] -; NDD-NEXT: retq # encoding: [0xc3] -; NDD-NEXT: .LBB1_2: # %ReturnBlock -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] entry: %tmp = load i32, ptr %y %tmp1 = shl i32 %tmp, 3 @@ -92,18 +67,6 @@ define i8 @test2b(i8 %X, ptr %y) nounwind { ; CHECK-NEXT: .LBB2_2: # %ReturnBlock ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: test2b: -; NDD: # %bb.0: # %entry -; NDD-NEXT: testb $31, (%rsi) # encoding: [0xf6,0x06,0x1f] -; NDD-NEXT: je .LBB2_2 # encoding: [0x74,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB2_2-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.1: # %cond_true -; NDD-NEXT: movb $1, %al # encoding: [0xb0,0x01] -; NDD-NEXT: retq # encoding: [0xc3] -; NDD-NEXT: .LBB2_2: # %ReturnBlock -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] entry: %tmp = load i8, ptr %y %tmp1 = shl i8 %tmp, 3 @@ -124,13 +87,6 @@ define i64 @test3(i64 %x) nounwind { ; CHECK-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff] ; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: test3: -; NDD: # %bb.0: # %entry -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff] -; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] entry: %t = icmp eq i64 %x, 0 %r = zext i1 %t to i64 @@ -144,13 +100,6 @@ define i64 @test4(i64 %x) nounwind { ; CHECK-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff] ; CHECK-NEXT: setle %al # encoding: [0x0f,0x9e,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: test4: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff] -; NDD-NEXT: setle %al # encoding: [0x0f,0x9e,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %t = icmp slt i64 %x, 1 %r = zext i1 %t to i64 ret i64 %r @@ -176,26 +125,6 @@ define i32 @test5(double %A) nounwind { ; CHECK-NEXT: jmp foo@PLT # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: foo@PLT-1, kind: FK_PCRel_1 -; -; NDD-LABEL: test5: -; NDD: # %bb.0: # %entry -; NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A] -; NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte -; NDD-NEXT: ja .LBB5_3 # encoding: [0x77,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.1: # %entry -; NDD-NEXT: ucomisd {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 # encoding: [0x66,0x0f,0x2e,0x05,A,A,A,A] -; NDD-NEXT: # fixup A - offset: 4, value: {{\.?LCPI[0-9]+_[0-9]+}}-4, kind: reloc_riprel_4byte -; NDD-NEXT: jb .LBB5_3 # encoding: [0x72,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB5_3-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %bb12 -; NDD-NEXT: movl $32, %eax # encoding: [0xb8,0x20,0x00,0x00,0x00] -; NDD-NEXT: retq # encoding: [0xc3] -; NDD-NEXT: .LBB5_3: # %bb8 -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: jmp foo@PLT # TAILCALL -; NDD-NEXT: # encoding: [0xeb,A] -; NDD-NEXT: # fixup A - offset: 1, value: foo@PLT-1, kind: FK_PCRel_1 entry: %tmp2 = fcmp ogt double %A, 1.500000e+02 %tmp5 = fcmp ult double %A, 7.500000e+01 @@ -224,18 +153,6 @@ define i32 @test6() nounwind align 2 { ; CHECK-NEXT: .LBB6_1: # %T ; CHECK-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: test6: -; NDD: # %bb.0: # %entry -; NDD-NEXT: cmpq $0, -{{[0-9]+}}(%rsp) # encoding: [0x48,0x83,0x7c,0x24,0xf8,0x00] -; NDD-NEXT: je .LBB6_1 # encoding: [0x74,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB6_1-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.2: # %F -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] -; NDD-NEXT: .LBB6_1: # %T -; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00] -; NDD-NEXT: retq # encoding: [0xc3] entry: %A = alloca { i64, i64 }, align 8 %B = getelementptr inbounds { i64, i64 }, ptr %A, i64 0, i32 1 @@ -251,12 +168,12 @@ F: } define i32 @test7(i64 %res) nounwind { -; CHECK-LABEL: test7: -; CHECK: # %bb.0: # %entry -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test7: +; NO-NDD: # %bb.0: # %entry +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test7: ; NDD: # %bb.0: # %entry @@ -271,13 +188,13 @@ entry: } define i32 @test8(i64 %res) nounwind { -; CHECK-LABEL: test8: -; CHECK: # %bb.0: -; CHECK-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20] -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03] -; CHECK-NEXT: setb %al # encoding: [0x0f,0x92,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test8: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20] +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: cmpl $3, %edi # encoding: [0x83,0xff,0x03] +; NO-NDD-NEXT: setb %al # encoding: [0x0f,0x92,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test8: ; NDD: # %bb.0: @@ -292,12 +209,12 @@ define i32 @test8(i64 %res) nounwind { } define i32 @test9(i64 %res) nounwind { -; CHECK-LABEL: test9: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: shrq $33, %rdi # encoding: [0x48,0xc1,0xef,0x21] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test9: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: shrq $33, %rdi # encoding: [0x48,0xc1,0xef,0x21] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test9: ; NDD: # %bb.0: @@ -311,12 +228,12 @@ define i32 @test9(i64 %res) nounwind { } define i32 @test10(i64 %res) nounwind { -; CHECK-LABEL: test10: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test10: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: shrq $32, %rdi # encoding: [0x48,0xc1,0xef,0x20] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test10: ; NDD: # %bb.0: @@ -330,13 +247,13 @@ define i32 @test10(i64 %res) nounwind { } define i32 @test11(i64 %l) nounwind { -; CHECK-LABEL: test11: -; CHECK: # %bb.0: -; CHECK-NEXT: shrq $47, %rdi # encoding: [0x48,0xc1,0xef,0x2f] -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test11: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shrq $47, %rdi # encoding: [0x48,0xc1,0xef,0x2f] +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: cmpl $1, %edi # encoding: [0x83,0xff,0x01] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test11: ; NDD: # %bb.0: @@ -372,27 +289,6 @@ define i32 @test12() ssp uwtable { ; CHECK-NEXT: popq %rcx # encoding: [0x59] ; CHECK-NEXT: .cfi_def_cfa_offset 8 ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: test12: -; NDD: # %bb.0: # %entry -; NDD-NEXT: pushq %rax # encoding: [0x50] -; NDD-NEXT: .cfi_def_cfa_offset 16 -; NDD-NEXT: callq test12b@PLT # encoding: [0xe8,A,A,A,A] -; NDD-NEXT: # fixup A - offset: 1, value: test12b@PLT-4, kind: FK_PCRel_4 -; NDD-NEXT: testb %al, %al # encoding: [0x84,0xc0] -; NDD-NEXT: je .LBB12_2 # encoding: [0x74,A] -; NDD-NEXT: # fixup A - offset: 1, value: .LBB12_2-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.1: # %T -; NDD-NEXT: movl $1, %eax # encoding: [0xb8,0x01,0x00,0x00,0x00] -; NDD-NEXT: popq %rcx # encoding: [0x59] -; NDD-NEXT: .cfi_def_cfa_offset 8 -; NDD-NEXT: retq # encoding: [0xc3] -; NDD-NEXT: .LBB12_2: # %F -; NDD-NEXT: .cfi_def_cfa_offset 16 -; NDD-NEXT: movl $2, %eax # encoding: [0xb8,0x02,0x00,0x00,0x00] -; NDD-NEXT: popq %rcx # encoding: [0x59] -; NDD-NEXT: .cfi_def_cfa_offset 8 -; NDD-NEXT: retq # encoding: [0xc3] entry: %tmp1 = call zeroext i1 @test12b() br i1 %tmp1, label %T, label %F @@ -407,12 +303,12 @@ F: declare zeroext i1 @test12b() define i32 @test13(i32 %mask, i32 %base, i32 %intra) { -; CHECK-LABEL: test13: -; CHECK: # %bb.0: -; CHECK-NEXT: movl %esi, %eax # encoding: [0x89,0xf0] -; CHECK-NEXT: testb $8, %dil # encoding: [0x40,0xf6,0xc7,0x08] -; CHECK-NEXT: cmovnel %edx, %eax # encoding: [0x0f,0x45,0xc2] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test13: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: movl %esi, %eax # encoding: [0x89,0xf0] +; NO-NDD-NEXT: testb $8, %dil # encoding: [0x40,0xf6,0xc7,0x08] +; NO-NDD-NEXT: cmovnel %edx, %eax # encoding: [0x0f,0x45,0xc2] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test13: ; NDD: # %bb.0: @@ -426,12 +322,12 @@ define i32 @test13(i32 %mask, i32 %base, i32 %intra) { } define i32 @test14(i32 %mask, i32 %base, i32 %intra) { -; CHECK-LABEL: test14: -; CHECK: # %bb.0: -; CHECK-NEXT: movl %esi, %eax # encoding: [0x89,0xf0] -; CHECK-NEXT: shrl $7, %edi # encoding: [0xc1,0xef,0x07] -; CHECK-NEXT: cmovnsl %edx, %eax # encoding: [0x0f,0x49,0xc2] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test14: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: movl %esi, %eax # encoding: [0x89,0xf0] +; NO-NDD-NEXT: shrl $7, %edi # encoding: [0xc1,0xef,0x07] +; NO-NDD-NEXT: cmovnsl %edx, %eax # encoding: [0x0f,0x49,0xc2] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test14: ; NDD: # %bb.0: @@ -446,14 +342,14 @@ define i32 @test14(i32 %mask, i32 %base, i32 %intra) { ; PR19964 define zeroext i1 @test15(i32 %bf.load, i32 %n) { -; CHECK-LABEL: test15: -; CHECK: # %bb.0: -; CHECK-NEXT: shrl $16, %edi # encoding: [0xc1,0xef,0x10] -; CHECK-NEXT: sete %cl # encoding: [0x0f,0x94,0xc1] -; CHECK-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7] -; CHECK-NEXT: setae %al # encoding: [0x0f,0x93,0xc0] -; CHECK-NEXT: orb %cl, %al # encoding: [0x08,0xc8] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test15: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shrl $16, %edi # encoding: [0xc1,0xef,0x10] +; NO-NDD-NEXT: sete %cl # encoding: [0x0f,0x94,0xc1] +; NO-NDD-NEXT: cmpl %esi, %edi # encoding: [0x39,0xf7] +; NO-NDD-NEXT: setae %al # encoding: [0x0f,0x93,0xc0] +; NO-NDD-NEXT: orb %cl, %al # encoding: [0x08,0xc8] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test15: ; NDD: # %bb.0: @@ -476,12 +372,6 @@ define i8 @signbit_i16(i16 signext %L) { ; CHECK-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff] ; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: signbit_i16: -; NDD: # %bb.0: -; NDD-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff] -; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %lshr = lshr i16 %L, 15 %trunc = trunc i16 %lshr to i8 %not = xor i8 %trunc, 1 @@ -494,12 +384,6 @@ define i8 @signbit_i32(i32 %L) { ; CHECK-NEXT: testl %edi, %edi # encoding: [0x85,0xff] ; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: signbit_i32: -; NDD: # %bb.0: -; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff] -; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %lshr = lshr i32 %L, 31 %trunc = trunc i32 %lshr to i8 %not = xor i8 %trunc, 1 @@ -512,12 +396,6 @@ define i8 @signbit_i64(i64 %L) { ; CHECK-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff] ; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: signbit_i64: -; NDD: # %bb.0: -; NDD-NEXT: testq %rdi, %rdi # encoding: [0x48,0x85,0xff] -; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %lshr = lshr i64 %L, 63 %trunc = trunc i64 %lshr to i8 %not = xor i8 %trunc, 1 @@ -530,12 +408,6 @@ define zeroext i1 @signbit_i32_i1(i32 %L) { ; CHECK-NEXT: testl %edi, %edi # encoding: [0x85,0xff] ; CHECK-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: signbit_i32_i1: -; NDD: # %bb.0: -; NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff] -; NDD-NEXT: setns %al # encoding: [0x0f,0x99,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %lshr = lshr i32 %L, 31 %trunc = trunc i32 %lshr to i1 %not = xor i1 %trunc, true @@ -544,20 +416,20 @@ define zeroext i1 @signbit_i32_i1(i32 %L) { ; This test failed due to incorrect handling of "shift + icmp" sequence define void @test20(i32 %bf.load, i8 %x1, ptr %b_addr) { -; CHECK-LABEL: test20: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00] -; CHECK-NEXT: # imm = 0xFFFFFF -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: movzbl %sil, %ecx # encoding: [0x40,0x0f,0xb6,0xce] -; CHECK-NEXT: addl %eax, %ecx # encoding: [0x01,0xc1] -; CHECK-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02] -; CHECK-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00] -; CHECK-NEXT: # imm = 0xFFFFFF -; CHECK-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A] -; CHECK-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: test20: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00] +; NO-NDD-NEXT: # imm = 0xFFFFFF +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: movzbl %sil, %ecx # encoding: [0x40,0x0f,0xb6,0xce] +; NO-NDD-NEXT: addl %eax, %ecx # encoding: [0x01,0xc1] +; NO-NDD-NEXT: setne (%rdx) # encoding: [0x0f,0x95,0x02] +; NO-NDD-NEXT: testl $16777215, %edi # encoding: [0xf7,0xc7,0xff,0xff,0xff,0x00] +; NO-NDD-NEXT: # imm = 0xFFFFFF +; NO-NDD-NEXT: setne d(%rip) # encoding: [0x0f,0x95,0x05,A,A,A,A] +; NO-NDD-NEXT: # fixup A - offset: 3, value: d-4, kind: reloc_riprel_4byte +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: test20: ; NDD: # %bb.0: @@ -593,11 +465,6 @@ define i32 @highmask_i64_simplify(i64 %val) { ; CHECK: # %bb.0: ; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: highmask_i64_simplify: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %and = and i64 %val, -2199023255552 %cmp = icmp ult i64 %and, 0 %ret = zext i1 %cmp to i32 @@ -605,12 +472,12 @@ define i32 @highmask_i64_simplify(i64 %val) { } define i32 @highmask_i64_mask64(i64 %val) { -; CHECK-LABEL: highmask_i64_mask64: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: shrq $41, %rdi # encoding: [0x48,0xc1,0xef,0x29] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: highmask_i64_mask64: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: shrq $41, %rdi # encoding: [0x48,0xc1,0xef,0x29] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: highmask_i64_mask64: ; NDD: # %bb.0: @@ -625,14 +492,14 @@ define i32 @highmask_i64_mask64(i64 %val) { } define i64 @highmask_i64_mask64_extra_use(i64 %val) nounwind { -; CHECK-LABEL: highmask_i64_mask64_extra_use: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: movq %rdi, %rcx # encoding: [0x48,0x89,0xf9] -; CHECK-NEXT: shrq $41, %rcx # encoding: [0x48,0xc1,0xe9,0x29] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: highmask_i64_mask64_extra_use: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: movq %rdi, %rcx # encoding: [0x48,0x89,0xf9] +; NO-NDD-NEXT: shrq $41, %rcx # encoding: [0x48,0xc1,0xe9,0x29] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: highmask_i64_mask64_extra_use: ; NDD: # %bb.0: @@ -649,12 +516,12 @@ define i64 @highmask_i64_mask64_extra_use(i64 %val) nounwind { } define i32 @highmask_i64_mask32(i64 %val) { -; CHECK-LABEL: highmask_i64_mask32: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: shrq $20, %rdi # encoding: [0x48,0xc1,0xef,0x14] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: highmask_i64_mask32: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: shrq $20, %rdi # encoding: [0x48,0xc1,0xef,0x14] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: highmask_i64_mask32: ; NDD: # %bb.0: @@ -669,14 +536,14 @@ define i32 @highmask_i64_mask32(i64 %val) { } define i64 @highmask_i64_mask32_extra_use(i64 %val) nounwind { -; CHECK-LABEL: highmask_i64_mask32_extra_use: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: testq $-1048576, %rdi # encoding: [0x48,0xf7,0xc7,0x00,0x00,0xf0,0xff] -; CHECK-NEXT: # imm = 0xFFF00000 -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: highmask_i64_mask32_extra_use: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: testq $-1048576, %rdi # encoding: [0x48,0xf7,0xc7,0x00,0x00,0xf0,0xff] +; NO-NDD-NEXT: # imm = 0xFFF00000 +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: highmask_i64_mask32_extra_use: ; NDD: # %bb.0: @@ -700,13 +567,6 @@ define i32 @highmask_i64_mask8(i64 %val) { ; CHECK-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff] ; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: highmask_i64_mask8: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testq $-16, %rdi # encoding: [0x48,0xf7,0xc7,0xf0,0xff,0xff,0xff] -; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %and = and i64 %val, -16 %cmp = icmp ne i64 %and, 0 %ret = zext i1 %cmp to i32 @@ -714,12 +574,12 @@ define i32 @highmask_i64_mask8(i64 %val) { } define i32 @lowmask_i64_mask64(i64 %val) { -; CHECK-LABEL: lowmask_i64_mask64: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: shlq $16, %rdi # encoding: [0x48,0xc1,0xe7,0x10] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: lowmask_i64_mask64: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: shlq $16, %rdi # encoding: [0x48,0xc1,0xe7,0x10] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: lowmask_i64_mask64: ; NDD: # %bb.0: @@ -734,14 +594,14 @@ define i32 @lowmask_i64_mask64(i64 %val) { } define i64 @lowmask_i64_mask64_extra_use(i64 %val) nounwind { -; CHECK-LABEL: lowmask_i64_mask64_extra_use: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: movq %rdi, %rcx # encoding: [0x48,0x89,0xf9] -; CHECK-NEXT: shlq $16, %rcx # encoding: [0x48,0xc1,0xe1,0x10] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: lowmask_i64_mask64_extra_use: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: movq %rdi, %rcx # encoding: [0x48,0x89,0xf9] +; NO-NDD-NEXT: shlq $16, %rcx # encoding: [0x48,0xc1,0xe1,0x10] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: lowmask_i64_mask64_extra_use: ; NDD: # %bb.0: @@ -758,12 +618,12 @@ define i64 @lowmask_i64_mask64_extra_use(i64 %val) nounwind { } define i32 @lowmask_i64_mask32(i64 %val) { -; CHECK-LABEL: lowmask_i64_mask32: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: shlq $44, %rdi # encoding: [0x48,0xc1,0xe7,0x2c] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: lowmask_i64_mask32: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: shlq $44, %rdi # encoding: [0x48,0xc1,0xe7,0x2c] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: lowmask_i64_mask32: ; NDD: # %bb.0: @@ -778,14 +638,14 @@ define i32 @lowmask_i64_mask32(i64 %val) { } define i64 @lowmask_i64_mask32_extra_use(i64 %val) nounwind { -; CHECK-LABEL: lowmask_i64_mask32_extra_use: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00] -; CHECK-NEXT: # imm = 0xFFFFF -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: lowmask_i64_mask32_extra_use: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00] +; NO-NDD-NEXT: # imm = 0xFFFFF +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: imulq %rdi, %rax # encoding: [0x48,0x0f,0xaf,0xc7] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: lowmask_i64_mask32_extra_use: ; NDD: # %bb.0: @@ -809,13 +669,6 @@ define i32 @lowmask_i64_mask8(i64 %val) { ; CHECK-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f] ; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: lowmask_i64_mask8: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f] -; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %and = and i64 %val, 31 %cmp = icmp eq i64 %and, 0 %ret = zext i1 %cmp to i32 @@ -830,14 +683,6 @@ define i32 @highmask_i32_mask32(i32 %val) { ; CHECK-NEXT: # imm = 0xFFF00000 ; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: highmask_i32_mask32: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testl $-1048576, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xf0,0xff] -; NDD-NEXT: # imm = 0xFFF00000 -; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %and = and i32 %val, -1048576 %cmp = icmp ne i32 %and, 0 %ret = zext i1 %cmp to i32 @@ -851,13 +696,6 @@ define i32 @highmask_i32_mask8(i32 %val) { ; CHECK-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff] ; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: highmask_i32_mask8: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testl $-16, %edi # encoding: [0xf7,0xc7,0xf0,0xff,0xff,0xff] -; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %and = and i32 %val, -16 %cmp = icmp eq i32 %and, 0 %ret = zext i1 %cmp to i32 @@ -872,14 +710,6 @@ define i32 @lowmask_i32_mask32(i32 %val) { ; CHECK-NEXT: # imm = 0xFFFFF ; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: lowmask_i32_mask32: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testl $1048575, %edi # encoding: [0xf7,0xc7,0xff,0xff,0x0f,0x00] -; NDD-NEXT: # imm = 0xFFFFF -; NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %and = and i32 %val, 1048575 %cmp = icmp eq i32 %and, 0 %ret = zext i1 %cmp to i32 @@ -893,13 +723,6 @@ define i32 @lowmask_i32_mask8(i32 %val) { ; CHECK-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f] ; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: lowmask_i32_mask8: -; NDD: # %bb.0: -; NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; NDD-NEXT: testb $31, %dil # encoding: [0x40,0xf6,0xc7,0x1f] -; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %and = and i32 %val, 31 %cmp = icmp ne i32 %and, 0 %ret = zext i1 %cmp to i32 @@ -907,12 +730,12 @@ define i32 @lowmask_i32_mask8(i32 %val) { } define i1 @shifted_mask64_testb(i64 %a) { -; CHECK-LABEL: shifted_mask64_testb: -; CHECK: # %bb.0: -; CHECK-NEXT: shrq $50, %rdi # encoding: [0x48,0xc1,0xef,0x32] -; CHECK-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: shifted_mask64_testb: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shrq $50, %rdi # encoding: [0x48,0xc1,0xef,0x32] +; NO-NDD-NEXT: testb %dil, %dil # encoding: [0x40,0x84,0xff] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: shifted_mask64_testb: ; NDD: # %bb.0: @@ -926,12 +749,12 @@ define i1 @shifted_mask64_testb(i64 %a) { } define i1 @shifted_mask64_testw(i64 %a) { -; CHECK-LABEL: shifted_mask64_testw: -; CHECK: # %bb.0: -; CHECK-NEXT: shrq $33, %rdi # encoding: [0x48,0xc1,0xef,0x21] -; CHECK-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: shifted_mask64_testw: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shrq $33, %rdi # encoding: [0x48,0xc1,0xef,0x21] +; NO-NDD-NEXT: testw %di, %di # encoding: [0x66,0x85,0xff] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: shifted_mask64_testw: ; NDD: # %bb.0: @@ -945,12 +768,12 @@ define i1 @shifted_mask64_testw(i64 %a) { } define i1 @shifted_mask64_testl(i64 %a) { -; CHECK-LABEL: shifted_mask64_testl: -; CHECK: # %bb.0: -; CHECK-NEXT: shrq $7, %rdi # encoding: [0x48,0xc1,0xef,0x07] -; CHECK-NEXT: testl %edi, %edi # encoding: [0x85,0xff] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: shifted_mask64_testl: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: shrq $7, %rdi # encoding: [0x48,0xc1,0xef,0x07] +; NO-NDD-NEXT: testl %edi, %edi # encoding: [0x85,0xff] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: shifted_mask64_testl: ; NDD: # %bb.0: @@ -964,15 +787,15 @@ define i1 @shifted_mask64_testl(i64 %a) { } define i1 @shifted_mask64_extra_use_const(i64 %a) { -; CHECK-LABEL: shifted_mask64_extra_use_const: -; CHECK: # %bb.0: -; CHECK-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03] -; CHECK-NEXT: # imm = 0x3FC000000000000 -; CHECK-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A] -; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: shifted_mask64_extra_use_const: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03] +; NO-NDD-NEXT: # imm = 0x3FC000000000000 +; NO-NDD-NEXT: testq %rcx, %rdi # encoding: [0x48,0x85,0xcf] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A] +; NO-NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: shifted_mask64_extra_use_const: ; NDD: # %bb.0: @@ -990,15 +813,15 @@ define i1 @shifted_mask64_extra_use_const(i64 %a) { } define i1 @shifted_mask64_extra_use_and(i64 %a) { -; CHECK-LABEL: shifted_mask64_extra_use_and: -; CHECK: # %bb.0: -; CHECK-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03] -; CHECK-NEXT: # imm = 0x3FC000000000000 -; CHECK-NEXT: andq %rdi, %rcx # encoding: [0x48,0x21,0xf9] -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A] -; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: shifted_mask64_extra_use_and: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: movabsq $287104476244869120, %rcx # encoding: [0x48,0xb9,0x00,0x00,0x00,0x00,0x00,0x00,0xfc,0x03] +; NO-NDD-NEXT: # imm = 0x3FC000000000000 +; NO-NDD-NEXT: andq %rdi, %rcx # encoding: [0x48,0x21,0xf9] +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: movq %rcx, d64(%rip) # encoding: [0x48,0x89,0x0d,A,A,A,A] +; NO-NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: shifted_mask64_extra_use_and: ; NDD: # %bb.0: @@ -1022,13 +845,6 @@ define i1 @shifted_mask32_testl_immediate(i64 %a) { ; CHECK-NEXT: # imm = 0x3FC0000 ; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: shifted_mask32_testl_immediate: -; NDD: # %bb.0: -; NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03] -; NDD-NEXT: # imm = 0x3FC0000 -; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; NDD-NEXT: retq # encoding: [0xc3] %v0 = and i64 %a, 66846720 ; 0xff << 18 %v1 = icmp ne i64 %v0, 0 ret i1 %v1 @@ -1044,16 +860,6 @@ define i1 @shifted_mask32_extra_use_const(i64 %a) { ; CHECK-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte ; CHECK-NEXT: # imm = 0x3FC0000 ; CHECK-NEXT: retq # encoding: [0xc3] -; -; NDD-LABEL: shifted_mask32_extra_use_const: -; NDD: # %bb.0: -; NDD-NEXT: testl $66846720, %edi # encoding: [0xf7,0xc7,0x00,0x00,0xfc,0x03] -; NDD-NEXT: # imm = 0x3FC0000 -; NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; NDD-NEXT: movq $66846720, d64(%rip) # encoding: [0x48,0xc7,0x05,A,A,A,A,0x00,0x00,0xfc,0x03] -; NDD-NEXT: # fixup A - offset: 3, value: d64-8, kind: reloc_riprel_4byte -; NDD-NEXT: # imm = 0x3FC0000 -; NDD-NEXT: retq # encoding: [0xc3] %v0 = and i64 %a, 66846720 ; 0xff << 18 %v1 = icmp ne i64 %v0, 0 store i64 66846720, ptr @d64 @@ -1061,14 +867,14 @@ define i1 @shifted_mask32_extra_use_const(i64 %a) { } define i1 @shifted_mask32_extra_use_and(i64 %a) { -; CHECK-LABEL: shifted_mask32_extra_use_and: -; CHECK: # %bb.0: -; CHECK-NEXT: andq $66846720, %rdi # encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03] -; CHECK-NEXT: # imm = 0x3FC0000 -; CHECK-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] -; CHECK-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A] -; CHECK-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: shifted_mask32_extra_use_and: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: andq $66846720, %rdi # encoding: [0x48,0x81,0xe7,0x00,0x00,0xfc,0x03] +; NO-NDD-NEXT: # imm = 0x3FC0000 +; NO-NDD-NEXT: setne %al # encoding: [0x0f,0x95,0xc0] +; NO-NDD-NEXT: movq %rdi, d64(%rip) # encoding: [0x48,0x89,0x3d,A,A,A,A] +; NO-NDD-NEXT: # fixup A - offset: 3, value: d64-4, kind: reloc_riprel_4byte +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: shifted_mask32_extra_use_and: ; NDD: # %bb.0: @@ -1085,14 +891,14 @@ define i1 @shifted_mask32_extra_use_and(i64 %a) { } define { i64, i64 } @pr39968(i64, i64, i32) { -; CHECK-LABEL: pr39968: -; CHECK: # %bb.0: -; CHECK-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] -; CHECK-NEXT: testb $64, %dl # encoding: [0xf6,0xc2,0x40] -; CHECK-NEXT: cmovneq %rdi, %rsi # encoding: [0x48,0x0f,0x45,0xf7] -; CHECK-NEXT: cmovneq %rdi, %rax # encoding: [0x48,0x0f,0x45,0xc7] -; CHECK-NEXT: movq %rsi, %rdx # encoding: [0x48,0x89,0xf2] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: pr39968: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: xorl %eax, %eax # encoding: [0x31,0xc0] +; NO-NDD-NEXT: testb $64, %dl # encoding: [0xf6,0xc2,0x40] +; NO-NDD-NEXT: cmovneq %rdi, %rsi # encoding: [0x48,0x0f,0x45,0xf7] +; NO-NDD-NEXT: cmovneq %rdi, %rax # encoding: [0x48,0x0f,0x45,0xc7] +; NO-NDD-NEXT: movq %rsi, %rdx # encoding: [0x48,0x89,0xf2] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: pr39968: ; NDD: # %bb.0: @@ -1124,18 +930,6 @@ define i32 @pr42189(i16 signext %c) { ; CHECK-NEXT: jmp g@PLT # TAILCALL ; CHECK-NEXT: # encoding: [0xeb,A] ; CHECK-NEXT: # fixup A - offset: 1, value: g@PLT-1, kind: FK_PCRel_1 -; -; NDD-LABEL: pr42189: -; NDD: # %bb.0: # %entry -; NDD-NEXT: cmpl $32767, %edi # encoding: [0x81,0xff,0xff,0x7f,0x00,0x00] -; NDD-NEXT: # imm = 0x7FFF -; NDD-NEXT: jne f@PLT # TAILCALL -; NDD-NEXT: # encoding: [0x75,A] -; NDD-NEXT: # fixup A - offset: 1, value: f@PLT-1, kind: FK_PCRel_1 -; NDD-NEXT: # %bb.1: # %if.then -; NDD-NEXT: jmp g@PLT # TAILCALL -; NDD-NEXT: # encoding: [0xeb,A] -; NDD-NEXT: # fixup A - offset: 1, value: g@PLT-1, kind: FK_PCRel_1 entry: %cmp = icmp eq i16 %c, 32767 br i1 %cmp, label %if.then, label %if.end @@ -1160,12 +954,12 @@ declare i32 @f() ; The store makes sure the chain result of the load is used which used to ; prevent the post isel peephole from catching this. define i1 @fold_test_and_with_chain(ptr %x, ptr %y, i32 %z) { -; CHECK-LABEL: fold_test_and_with_chain: -; CHECK: # %bb.0: -; CHECK-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17] -; CHECK-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] -; CHECK-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16] -; CHECK-NEXT: retq # encoding: [0xc3] +; NO-NDD-LABEL: fold_test_and_with_chain: +; NO-NDD: # %bb.0: +; NO-NDD-NEXT: testl %edx, (%rdi) # encoding: [0x85,0x17] +; NO-NDD-NEXT: sete %al # encoding: [0x0f,0x94,0xc0] +; NO-NDD-NEXT: movl %edx, (%rsi) # encoding: [0x89,0x16] +; NO-NDD-NEXT: retq # encoding: [0xc3] ; ; NDD-LABEL: fold_test_and_with_chain: ; NDD: # %bb.0: -- GitLab From 8ad092f126bd1d6f9fe6006eba1e3115a080235e Mon Sep 17 00:00:00 2001 From: Fangrui Song Date: Sun, 28 Apr 2024 09:42:43 -0700 Subject: [PATCH 161/301] [cc1as] Respect -mrelax-all So that `clang -c -mrelax-all a.s` sets MCRelaxAll and assembles JMP/JCC to a near jump instead of silently ignoring `-mrelax-all`. --- clang/test/Misc/cc1as-relax-all.s | 13 +++++++++++++ clang/tools/driver/cc1as_main.cpp | 1 + 2 files changed, 14 insertions(+) create mode 100644 clang/test/Misc/cc1as-relax-all.s diff --git a/clang/test/Misc/cc1as-relax-all.s b/clang/test/Misc/cc1as-relax-all.s new file mode 100644 index 000000000000..e76fc6f61bab --- /dev/null +++ b/clang/test/Misc/cc1as-relax-all.s @@ -0,0 +1,13 @@ +// REQUIRES: x86-registered-target +// RUN: %clang -cc1as -triple x86_64 -filetype obj -mrelax-all %s -o %t.o +// RUN: llvm-objdump -d %t.o | FileCheck %s + +// CHECK: <.text>: +// CHECK-NEXT: 0: e9 06 00 00 00 jmp 0xb +// CHECK-NEXT: 5: 0f 84 00 00 00 00 je 0xb +// CHECK-EMPTY: + +jmp foo +je foo + +foo: ret diff --git a/clang/tools/driver/cc1as_main.cpp b/clang/tools/driver/cc1as_main.cpp index 5498c3f9d4a2..86afe22fac24 100644 --- a/clang/tools/driver/cc1as_main.cpp +++ b/clang/tools/driver/cc1as_main.cpp @@ -426,6 +426,7 @@ static bool ExecuteAssemblerImpl(AssemblerInvocation &Opts, assert(MRI && "Unable to create target register info!"); MCTargetOptions MCOptions; + MCOptions.MCRelaxAll = Opts.RelaxAll; MCOptions.EmitDwarfUnwind = Opts.EmitDwarfUnwind; MCOptions.EmitCompactUnwindNonCanonical = Opts.EmitCompactUnwindNonCanonical; MCOptions.X86RelaxRelocations = Opts.RelaxELFRelocations; -- GitLab From 216787cffc4a864e0effb165c1c32b92328a0a06 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Th=C3=A9o=20Degioanni?= Date: Sun, 28 Apr 2024 19:26:31 +0200 Subject: [PATCH 162/301] [mlir][arith] Add tests for i0 canonicalization (#89665) Before #87193, the canonicalizer in arith crashed when attempting signed extension on an i0 value. To hopefully avoid it happening again, this PR introduces tests for canonicalization of arith operations with i0 values, focusing on operations related to bit width or signedness. --- mlir/test/Dialect/Arith/canonicalize.mlir | 81 +++++++++++++++++++++++ 1 file changed, 81 insertions(+) diff --git a/mlir/test/Dialect/Arith/canonicalize.mlir b/mlir/test/Dialect/Arith/canonicalize.mlir index 6c4193bc06ca..f7ce2123a93c 100644 --- a/mlir/test/Dialect/Arith/canonicalize.mlir +++ b/mlir/test/Dialect/Arith/canonicalize.mlir @@ -2831,6 +2831,87 @@ func.func @unsignedExtendConstantResource() -> tensor { return %ext : tensor } +// CHECK-LABEL: @extsi_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i16 +// CHECK: return %[[ZERO]] : i16 +func.func @extsi_i0() -> i16 { + %c0 = arith.constant 0 : i0 + %extsi = arith.extsi %c0 : i0 to i16 + return %extsi : i16 +} + +// CHECK-LABEL: @extui_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i16 +// CHECK: return %[[ZERO]] : i16 +func.func @extui_i0() -> i16 { + %c0 = arith.constant 0 : i0 + %extui = arith.extui %c0 : i0 to i16 + return %extui : i16 +} + +// CHECK-LABEL: @trunc_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i0 +// CHECK: return %[[ZERO]] : i0 +func.func @trunc_i0() -> i0 { + %cFF = arith.constant 0xFF : i8 + %trunc = arith.trunci %cFF : i8 to i0 + return %trunc : i0 +} + +// CHECK-LABEL: @shli_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i0 +// CHECK: return %[[ZERO]] : i0 +func.func @shli_i0() -> i0 { + %c0 = arith.constant 0 : i0 + %shli = arith.shli %c0, %c0 : i0 + return %shli : i0 +} + +// CHECK-LABEL: @shrsi_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i0 +// CHECK: return %[[ZERO]] : i0 +func.func @shrsi_i0() -> i0 { + %c0 = arith.constant 0 : i0 + %shrsi = arith.shrsi %c0, %c0 : i0 + return %shrsi : i0 +} + +// CHECK-LABEL: @shrui_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i0 +// CHECK: return %[[ZERO]] : i0 +func.func @shrui_i0() -> i0 { + %c0 = arith.constant 0 : i0 + %shrui = arith.shrui %c0, %c0 : i0 + return %shrui : i0 +} + +// CHECK-LABEL: @maxsi_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i0 +// CHECK: return %[[ZERO]] : i0 +func.func @maxsi_i0() -> i0 { + %c0 = arith.constant 0 : i0 + %maxsi = arith.maxsi %c0, %c0 : i0 + return %maxsi : i0 +} + +// CHECK-LABEL: @minsi_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i0 +// CHECK: return %[[ZERO]] : i0 +func.func @minsi_i0() -> i0 { + %c0 = arith.constant 0 : i0 + %minsi = arith.minsi %c0, %c0 : i0 + return %minsi : i0 +} + +// CHECK-LABEL: @mulsi_extended_i0 +// CHECK: %[[ZERO:.*]] = arith.constant 0 : i0 +// CHECK: return %[[ZERO]], %[[ZERO]] : i0 +func.func @mulsi_extended_i0() -> (i0, i0) { + %c0 = arith.constant 0 : i0 + %mulsi_extended:2 = arith.mulsi_extended %c0, %c0 : i0 + return %mulsi_extended#0, %mulsi_extended#1 : i0, i0 +} + {-# dialect_resources: { builtin: { -- GitLab From 6dd90616c477d83c156eed62c880e951bb508cfd Mon Sep 17 00:00:00 2001 From: cor3ntin Date: Sun, 28 Apr 2024 20:25:44 +0200 Subject: [PATCH 163/301] [Clang] Implement C++26 Attributes for Structured Bindings (P0609R3) (#89906) https://www.open-std.org/jtc1/sc22/wg21/docs/papers/2024/p0609r3.pdf We support this feature in all language mode. maybe_unused applied to a binding makes the whole declaration unused. --- clang/docs/LanguageExtensions.rst | 1 + clang/docs/ReleaseNotes.rst | 2 + clang/include/clang/Basic/Attr.td | 2 +- .../clang/Basic/DiagnosticParseKinds.td | 9 +++ clang/include/clang/Sema/DeclSpec.h | 10 +-- clang/include/clang/Sema/ParsedAttr.h | 1 + clang/lib/AST/DeclBase.cpp | 4 +- clang/lib/Frontend/InitPreprocessor.cpp | 2 +- clang/lib/Parse/ParseDecl.cpp | 41 +++++++++--- clang/lib/Sema/DeclSpec.cpp | 4 +- clang/lib/Sema/SemaDecl.cpp | 2 +- clang/lib/Sema/SemaDeclCXX.cpp | 2 + clang/test/Lexer/cxx-features.cpp | 2 +- clang/test/Parser/cxx1z-decomposition.cpp | 63 ++++++++++++++++--- clang/test/SemaCXX/unused.cpp | 12 +++- clang/www/cxx_status.html | 2 +- 16 files changed, 127 insertions(+), 32 deletions(-) diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index f18b946efd4b..127d1b6dd482 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -1493,6 +1493,7 @@ Conditional ``explicit`` __cpp_conditional_explicit C+ ``if consteval`` __cpp_if_consteval C++23 C++20 ``static operator()`` __cpp_static_call_operator C++23 C++03 Attributes on Lambda-Expressions C++23 C++11 +Attributes on Structured Bindings __cpp_structured_bindings C++26 C++03 ``= delete ("should have a reason");`` __cpp_deleted_function C++26 C++03 -------------------------------------------- -------------------------------- ------------- ------------- Designated initializers (N494) C99 C89 diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index a1390d6536b2..64a523a6f25f 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -143,6 +143,8 @@ C++2c Feature Support - Implemented `P2573R2: = delete("should have a reason"); `_ +- Implemented `P0609R3: Attributes for Structured Bindings `_ + Resolutions to C++ Defect Reports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/Attr.td b/clang/include/clang/Basic/Attr.td index 4408d517e70e..97e06fe7d2e6 100644 --- a/clang/include/clang/Basic/Attr.td +++ b/clang/include/clang/Basic/Attr.td @@ -3211,7 +3211,7 @@ def ObjCRequiresPropertyDefs : InheritableAttr { def Unused : InheritableAttr { let Spellings = [CXX11<"", "maybe_unused", 201603>, GCC<"unused">, C23<"", "maybe_unused", 202106>]; - let Subjects = SubjectList<[Var, ObjCIvar, Type, Enum, EnumConstant, Label, + let Subjects = SubjectList<[Var, Binding, ObjCIvar, Type, Enum, EnumConstant, Label, Field, ObjCMethod, FunctionLike]>; let Documentation = [WarnMaybeUnusedDocs]; } diff --git a/clang/include/clang/Basic/DiagnosticParseKinds.td b/clang/include/clang/Basic/DiagnosticParseKinds.td index 38174cf3549f..fdffb35ea0d9 100644 --- a/clang/include/clang/Basic/DiagnosticParseKinds.td +++ b/clang/include/clang/Basic/DiagnosticParseKinds.td @@ -478,6 +478,15 @@ def ext_decomp_decl_empty : ExtWarn< "ISO C++17 does not allow a decomposition group to be empty">, InGroup>; +// C++26 structured bindings +def ext_decl_attrs_on_binding : ExtWarn< + "an attribute specifier sequence attached to a structured binding declaration " + "is a C++2c extension">, InGroup; +def warn_cxx23_compat_decl_attrs_on_binding : Warning< + "an attribute specifier sequence attached to a structured binding declaration " + "is incompatible with C++ standards before C++2c">, + InGroup, DefaultIgnore; + /// Objective-C parser diagnostics def err_expected_minus_or_plus : Error< "method type specifier must start with '-' or '+'">; diff --git a/clang/include/clang/Sema/DeclSpec.h b/clang/include/clang/Sema/DeclSpec.h index c9eecdafe62c..760c7980be52 100644 --- a/clang/include/clang/Sema/DeclSpec.h +++ b/clang/include/clang/Sema/DeclSpec.h @@ -36,6 +36,7 @@ #include "llvm/ADT/SmallVector.h" #include "llvm/Support/Compiler.h" #include "llvm/Support/ErrorHandling.h" +#include namespace clang { class ASTContext; @@ -1790,6 +1791,7 @@ public: struct Binding { IdentifierInfo *Name; SourceLocation NameLoc; + std::optional Attrs; }; private: @@ -2339,10 +2341,10 @@ public: } /// Set the decomposition bindings for this declarator. - void - setDecompositionBindings(SourceLocation LSquareLoc, - ArrayRef Bindings, - SourceLocation RSquareLoc); + void setDecompositionBindings( + SourceLocation LSquareLoc, + MutableArrayRef Bindings, + SourceLocation RSquareLoc); /// AddTypeInfo - Add a chunk to this declarator. Also extend the range to /// EndLoc, which should be the last token of the chunk. diff --git a/clang/include/clang/Sema/ParsedAttr.h b/clang/include/clang/Sema/ParsedAttr.h index 25a5fa05b21c..8368d9ce6146 100644 --- a/clang/include/clang/Sema/ParsedAttr.h +++ b/clang/include/clang/Sema/ParsedAttr.h @@ -948,6 +948,7 @@ public: ParsedAttributes(AttributeFactory &factory) : pool(factory) {} ParsedAttributes(const ParsedAttributes &) = delete; ParsedAttributes &operator=(const ParsedAttributes &) = delete; + ParsedAttributes(ParsedAttributes &&G) = default; AttributePool &getPool() const { return pool; } diff --git a/clang/lib/AST/DeclBase.cpp b/clang/lib/AST/DeclBase.cpp index c33babf8d1df..f341c74cf86e 100644 --- a/clang/lib/AST/DeclBase.cpp +++ b/clang/lib/AST/DeclBase.cpp @@ -1115,7 +1115,9 @@ int64_t Decl::getID() const { const FunctionType *Decl::getFunctionType(bool BlocksToo) const { QualType Ty; - if (const auto *D = dyn_cast(this)) + if (const auto *D = dyn_cast(this)) + return nullptr; + else if (const auto *D = dyn_cast(this)) Ty = D->getType(); else if (const auto *D = dyn_cast(this)) Ty = D->getUnderlyingType(); diff --git a/clang/lib/Frontend/InitPreprocessor.cpp b/clang/lib/Frontend/InitPreprocessor.cpp index 745d1a5aca55..c1d209466ffe 100644 --- a/clang/lib/Frontend/InitPreprocessor.cpp +++ b/clang/lib/Frontend/InitPreprocessor.cpp @@ -703,7 +703,7 @@ static void InitializeCPlusPlusFeatureTestMacros(const LangOptions &LangOpts, Builder.defineMacro("__cpp_nested_namespace_definitions", "201411L"); Builder.defineMacro("__cpp_variadic_using", "201611L"); Builder.defineMacro("__cpp_aggregate_bases", "201603L"); - Builder.defineMacro("__cpp_structured_bindings", "201606L"); + Builder.defineMacro("__cpp_structured_bindings", "202403L"); Builder.defineMacro("__cpp_nontype_template_args", "201411L"); // (not latest) Builder.defineMacro("__cpp_fold_expressions", "201603L"); diff --git a/clang/lib/Parse/ParseDecl.cpp b/clang/lib/Parse/ParseDecl.cpp index 05ad5ecbfaa0..a7846e102a43 100644 --- a/clang/lib/Parse/ParseDecl.cpp +++ b/clang/lib/Parse/ParseDecl.cpp @@ -7038,18 +7038,23 @@ void Parser::ParseDirectDeclarator(Declarator &D) { void Parser::ParseDecompositionDeclarator(Declarator &D) { assert(Tok.is(tok::l_square)); + TentativeParsingAction PA(*this); + BalancedDelimiterTracker T(*this, tok::l_square); + T.consumeOpen(); + + if (isCXX11AttributeSpecifier()) + DiagnoseAndSkipCXX11Attributes(); + // If this doesn't look like a structured binding, maybe it's a misplaced // array declarator. - // FIXME: Consume the l_square first so we don't need extra lookahead for - // this. - if (!(NextToken().is(tok::identifier) && - GetLookAheadToken(2).isOneOf(tok::comma, tok::r_square)) && - !(NextToken().is(tok::r_square) && - GetLookAheadToken(2).isOneOf(tok::equal, tok::l_brace))) + if (!(Tok.is(tok::identifier) && + NextToken().isOneOf(tok::comma, tok::r_square, tok::kw_alignas, + tok::l_square)) && + !(Tok.is(tok::r_square) && + NextToken().isOneOf(tok::equal, tok::l_brace))) { + PA.Revert(); return ParseMisplacedBracketDeclarator(D); - - BalancedDelimiterTracker T(*this, tok::l_square); - T.consumeOpen(); + } SmallVector Bindings; while (Tok.isNot(tok::r_square)) { @@ -7074,13 +7079,27 @@ void Parser::ParseDecompositionDeclarator(Declarator &D) { } } + if (isCXX11AttributeSpecifier()) + DiagnoseAndSkipCXX11Attributes(); + if (Tok.isNot(tok::identifier)) { Diag(Tok, diag::err_expected) << tok::identifier; break; } - Bindings.push_back({Tok.getIdentifierInfo(), Tok.getLocation()}); + IdentifierInfo *II = Tok.getIdentifierInfo(); + SourceLocation Loc = Tok.getLocation(); ConsumeToken(); + + ParsedAttributes Attrs(AttrFactory); + if (isCXX11AttributeSpecifier()) { + Diag(Tok, getLangOpts().CPlusPlus26 + ? diag::warn_cxx23_compat_decl_attrs_on_binding + : diag::ext_decl_attrs_on_binding); + MaybeParseCXX11Attributes(Attrs); + } + + Bindings.push_back({II, Loc, std::move(Attrs)}); } if (Tok.isNot(tok::r_square)) @@ -7095,6 +7114,8 @@ void Parser::ParseDecompositionDeclarator(Declarator &D) { T.consumeClose(); } + PA.Commit(); + return D.setDecompositionBindings(T.getOpenLocation(), Bindings, T.getCloseLocation()); } diff --git a/clang/lib/Sema/DeclSpec.cpp b/clang/lib/Sema/DeclSpec.cpp index b79683bb32a6..5f63c857c430 100644 --- a/clang/lib/Sema/DeclSpec.cpp +++ b/clang/lib/Sema/DeclSpec.cpp @@ -293,7 +293,7 @@ DeclaratorChunk DeclaratorChunk::getFunction(bool hasProto, void Declarator::setDecompositionBindings( SourceLocation LSquareLoc, - ArrayRef Bindings, + MutableArrayRef Bindings, SourceLocation RSquareLoc) { assert(!hasName() && "declarator given multiple names!"); @@ -317,7 +317,7 @@ void Declarator::setDecompositionBindings( new DecompositionDeclarator::Binding[Bindings.size()]; BindingGroup.DeleteBindings = true; } - std::uninitialized_copy(Bindings.begin(), Bindings.end(), + std::uninitialized_move(Bindings.begin(), Bindings.end(), BindingGroup.Bindings); } } diff --git a/clang/lib/Sema/SemaDecl.cpp b/clang/lib/Sema/SemaDecl.cpp index e0745fe9a453..671752b56e01 100644 --- a/clang/lib/Sema/SemaDecl.cpp +++ b/clang/lib/Sema/SemaDecl.cpp @@ -1974,7 +1974,7 @@ static bool ShouldDiagnoseUnusedDecl(const LangOptions &LangOpts, // it is, by the bindings' expressions). bool IsAllPlaceholders = true; for (const auto *BD : DD->bindings()) { - if (BD->isReferenced()) + if (BD->isReferenced() || BD->hasAttr()) return false; IsAllPlaceholders = IsAllPlaceholders && BD->isPlaceholderVar(LangOpts); } diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index abdbc9d8830c..1a71a37c0732 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -910,6 +910,8 @@ Sema::ActOnDecompositionDeclarator(Scope *S, Declarator &D, auto *BD = BindingDecl::Create(Context, DC, B.NameLoc, VarName); + ProcessDeclAttributeList(S, BD, *B.Attrs); + // Find the shadowed declaration before filtering for scope. NamedDecl *ShadowedDecl = D.getCXXScopeSpec().isEmpty() ? getShadowedDeclaration(BD, Previous) diff --git a/clang/test/Lexer/cxx-features.cpp b/clang/test/Lexer/cxx-features.cpp index baaa9d4434e9..4a08eb61cd39 100644 --- a/clang/test/Lexer/cxx-features.cpp +++ b/clang/test/Lexer/cxx-features.cpp @@ -222,7 +222,7 @@ #error "wrong value for __cpp_aggregate_bases" #endif -#if check(structured_bindings, 0, 0, 0, 201606, 201606, 201606, 201606) +#if check(structured_bindings, 0, 0, 0, 202403L, 202403L, 202403L, 202403L) #error "wrong value for __cpp_structured_bindings" #endif diff --git a/clang/test/Parser/cxx1z-decomposition.cpp b/clang/test/Parser/cxx1z-decomposition.cpp index 90d60df2e47f..4b17f72effb0 100644 --- a/clang/test/Parser/cxx1z-decomposition.cpp +++ b/clang/test/Parser/cxx1z-decomposition.cpp @@ -1,6 +1,7 @@ -// RUN: %clang_cc1 -std=c++17 %s -verify=expected,cxx17 -fcxx-exceptions -// RUN: %clang_cc1 -std=c++2b %s -verify=expected,cxx2b -fcxx-exceptions -// RUN: not %clang_cc1 -std=c++17 %s -emit-llvm-only -fcxx-exceptions +// RUN: %clang_cc1 -std=c++17 %s -triple x86_64-unknown-linux-gnu -verify=expected,cxx17,pre2c -fcxx-exceptions +// RUN: %clang_cc1 -std=c++2b %s -triple x86_64-unknown-linux-gnu -verify=expected,cxx2b,pre2c,post2b -fcxx-exceptions +// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-unknown-linux-gnu -verify=expected,cxx2c,post2b -fcxx-exceptions +// RUN: not %clang_cc1 -std=c++17 %s -triple x86_64-unknown-linux-gnu -emit-llvm-only -fcxx-exceptions struct S { int a, b, c; }; @@ -58,7 +59,7 @@ namespace OtherDecl { namespace GoodSpecifiers { void f() { int n[1]; - const volatile auto &[a] = n; // cxx2b-warning {{volatile qualifier in structured binding declaration is deprecated}} + const volatile auto &[a] = n; // post2b-warning {{volatile qualifier in structured binding declaration is deprecated}} } } @@ -97,8 +98,8 @@ namespace BadSpecifiers { S [a] = s; // expected-error {{cannot be declared with type 'S'}} decltype(auto) [b] = s; // expected-error {{cannot be declared with type 'decltype(auto)'}} auto ([c2]) = s; // cxx17-error {{decomposition declaration cannot be declared with parenthese}} \ - // cxx2b-error {{use of undeclared identifier 'c2'}} \ - // cxx2b-error {{expected body of lambda expression}} \ + // post2b-error {{use of undeclared identifier 'c2'}} \ + // post2b-error {{expected body of lambda expression}} \ // FIXME: This error is not very good. auto [d]() = s; // expected-error {{expected ';'}} expected-error {{expected expression}} @@ -119,9 +120,6 @@ namespace BadSpecifiers { [[]] auto [ok_3] = s; alignas(S) auto [ok_4] = s; - // ... but not after the identifier or declarator. - // FIXME: These errors are not very good. - auto [bad_attr_1 [[]]] = s; // expected-error {{attribute list cannot appear here}} expected-error 2{{}} auto [bad_attr_2] [[]] = s; // expected-error {{expected ';'}} expected-error {{}} } } @@ -156,3 +154,50 @@ namespace Init { S [goodish4] { 4 }; // expected-error {{cannot be declared with type 'S'}} } } + + +namespace attributes { + +struct S{ + int a; + int b = 0; +}; + +void err() { + auto [[]] = S{0}; // expected-error {{expected unqualified-id}} + auto [ alignas(42) a, foo ] = S{0}; // expected-error {{an attribute list cannot appear here}} + auto [ c, [[]] d ] = S{0}; // expected-error {{an attribute list cannot appear here}} + auto [ e, alignas(42) f ] = S{0}; // expected-error {{an attribute list cannot appear here}} +} + +void ok() { + auto [ a alignas(42) [[]], b alignas(42) [[]]] = S{0}; // expected-error 2{{'alignas' attribute only applies to variables, data members and tag types}} \ + // pre2c-warning 2{{an attribute specifier sequence attached to a structured binding declaration is a C++2c extension}} + auto [ c [[]] alignas(42), d [[]] alignas(42) [[]]] = S{0}; // expected-error 2{{'alignas' attribute only applies to variables, data members and tag types}} \ + // pre2c-warning 2{{an attribute specifier sequence attached to a structured binding declaration is a C++2c extension}} +} + + +auto [G1 [[deprecated]], G2 [[deprecated]]] = S{42}; // #deprecated-here +// pre2c-warning@-1 2{{an attribute specifier sequence attached to a structured binding declaration is a C++2c extension}} + +int test() { + return G1 + G2; // expected-warning {{'G1' is deprecated}} expected-note@#deprecated-here {{here}} \ + // expected-warning {{'G2' is deprecated}} expected-note@#deprecated-here {{here}} +} + +void invalid_attributes() { + // pre2c-warning@+1 {{an attribute specifier sequence attached to a structured binding declaration is a C++2c extension}} + auto [a alignas(42) // expected-error {{'alignas' attribute only applies to variables, data members and tag types}} + [[assume(true), // expected-error {{'assume' attribute cannot be applied to a declaration}} + carries_dependency, // expected-error {{'carries_dependency' attribute only applies to parameters, Objective-C methods, and functions}} + fallthrough, // expected-error {{'fallthrough' attribute cannot be applied to a declaration}} + likely, // expected-error {{'likely' attribute cannot be applied to a declaration}} + unlikely, // expected-error {{'unlikely' attribute cannot be applied to a declaration}} + nodiscard, // expected-warning {{'nodiscard' attribute only applies to Objective-C methods, enums, structs, unions, classes, functions, function pointers, and typedefs}} + noreturn, // expected-error {{'noreturn' attribute only applies to functions}} + no_unique_address]], // expected-error {{'no_unique_address' attribute only applies to non-bit-field non-static data members}} + b] = S{0}; +} + +} diff --git a/clang/test/SemaCXX/unused.cpp b/clang/test/SemaCXX/unused.cpp index 0af9e5b68b00..1f40c1b1ca90 100644 --- a/clang/test/SemaCXX/unused.cpp +++ b/clang/test/SemaCXX/unused.cpp @@ -102,11 +102,21 @@ namespace PR33839 { for (auto [x] : a) { // expected-warning {{unused variable '[x]'}} } } - void use() { + void use() { f(); // expected-note {{instantiation of}} g(); g(); h(); // expected-note {{instantiation of}} } } + +namespace maybe_unused_binding { + +void test() { + struct X { int a, b; } x; + auto [a [[maybe_unused]], b] = x; // expected-warning {{an attribute specifier sequence attached to a structured binding declaration is a C++2c extension}} +} + +} + #endif diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index c233171e63c8..0d796597d05c 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -187,7 +187,7 @@ C++23, informally referred to as C++26.

Trivial infinite loops are not Undefined Behavior P2809R3 (DR) - No + Clang 19 Erroneous behaviour for uninitialized reads -- GitLab From 352602010fac5c7e07bc6b992848ab746d0c2857 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 28 Apr 2024 11:44:45 -0700 Subject: [PATCH 164/301] Repply [memprof] Introduce FrameIdConverter and CallStackIdConverter (#90307) Currently, we convert FrameId to Frame and CallStackId to a call stack at several places. This patch unifies those into function objects -- FrameIdConverter and CallStackIdConverter. The existing implementation of CallStackIdConverter, being removed in this patch, handles both FrameId and CallStackId conversions. This patch splits it into two phases for flexibility (but make them composable) because some places only require the FrameId conversion. This iteration fixes a problem uncovered with ubsan, where we were dereferencing an uninitialized std::unique_ptr. --- llvm/include/llvm/ProfileData/MemProf.h | 58 +++++++++++++++++ llvm/include/llvm/ProfileData/MemProfReader.h | 14 ++--- llvm/lib/ProfileData/InstrProfReader.cpp | 62 +++++++------------ llvm/unittests/ProfileData/InstrProfTest.cpp | 62 +++++-------------- llvm/unittests/ProfileData/MemProfTest.cpp | 36 +++-------- 5 files changed, 107 insertions(+), 125 deletions(-) diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index d378c3696f8d..8b00faf2a219 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -737,6 +737,64 @@ public: // Compute a CallStackId for a given call stack. CallStackId hashCallStack(ArrayRef CS); +namespace detail { +// "Dereference" the iterator from DenseMap or OnDiskChainedHashTable. We have +// to do so in one of two different ways depending on the type of the hash +// table. +template +value_type DerefIterator(IterTy Iter) { + using deref_type = llvm::remove_cvref_t; + if constexpr (std::is_same_v) + return *Iter; + else + return Iter->second; +} +} // namespace detail + +// A function object that returns a frame for a given FrameId. +template struct FrameIdConverter { + std::optional LastUnmappedId; + MapTy ⤅ + + FrameIdConverter() = delete; + FrameIdConverter(MapTy &Map) : Map(Map) {} + + Frame operator()(FrameId Id) { + auto Iter = Map.find(Id); + if (Iter == Map.end()) { + LastUnmappedId = Id; + return Frame(0, 0, 0, false); + } + return detail::DerefIterator(Iter); + } +}; + +// A function object that returns a call stack for a given CallStackId. +template struct CallStackIdConverter { + std::optional LastUnmappedId; + MapTy ⤅ + std::function FrameIdToFrame; + + CallStackIdConverter() = delete; + CallStackIdConverter(MapTy &Map, std::function FrameIdToFrame) + : Map(Map), FrameIdToFrame(FrameIdToFrame) {} + + llvm::SmallVector operator()(CallStackId CSId) { + llvm::SmallVector Frames; + auto CSIter = Map.find(CSId); + if (CSIter == Map.end()) { + LastUnmappedId = CSId; + } else { + llvm::SmallVector CS = + detail::DerefIterator>(CSIter); + Frames.reserve(CS.size()); + for (FrameId Id : CS) + Frames.push_back(FrameIdToFrame(Id)); + } + return Frames; + } +}; + // Verify that each CallStackId is computed with hashCallStack. This function // is intended to help transition from CallStack to CSId in // IndexedAllocationInfo. diff --git a/llvm/include/llvm/ProfileData/MemProfReader.h b/llvm/include/llvm/ProfileData/MemProfReader.h index 444c58e8bdc8..b42e4f597774 100644 --- a/llvm/include/llvm/ProfileData/MemProfReader.h +++ b/llvm/include/llvm/ProfileData/MemProfReader.h @@ -76,20 +76,16 @@ public: Callback = std::bind(&MemProfReader::idToFrame, this, std::placeholders::_1); - auto CallStackCallback = [&](CallStackId CSId) { - llvm::SmallVector CallStack; - auto Iter = CSIdToCallStack.find(CSId); - assert(Iter != CSIdToCallStack.end()); - for (FrameId Id : Iter->second) - CallStack.push_back(Callback(Id)); - return CallStack; - }; + memprof::CallStackIdConverter CSIdConv( + CSIdToCallStack, Callback); const IndexedMemProfRecord &IndexedRecord = Iter->second; GuidRecord = { Iter->first, - IndexedRecord.toMemProfRecord(CallStackCallback), + IndexedRecord.toMemProfRecord(CSIdConv), }; + if (CSIdConv.LastUnmappedId) + return make_error(instrprof_error::hash_mismatch); Iter++; return Error::success(); } diff --git a/llvm/lib/ProfileData/InstrProfReader.cpp b/llvm/lib/ProfileData/InstrProfReader.cpp index cefb6af12d00..ba21e01abfba 100644 --- a/llvm/lib/ProfileData/InstrProfReader.cpp +++ b/llvm/lib/ProfileData/InstrProfReader.cpp @@ -1520,54 +1520,38 @@ IndexedMemProfReader::getMemProfRecord(const uint64_t FuncNameHash) const { // Setup a callback to convert from frame ids to frame using the on-disk // FrameData hash table. - std::optional LastUnmappedFrameId; - auto IdToFrameCallback = [&](const memprof::FrameId Id) { - auto FrIter = MemProfFrameTable->find(Id); - if (FrIter == MemProfFrameTable->end()) { - LastUnmappedFrameId = Id; - return memprof::Frame(0, 0, 0, false); - } - return *FrIter; - }; - - // Setup a callback to convert call stack ids to call stacks using the on-disk - // hash table. - std::optional LastUnmappedCSId; - auto CSIdToCallStackCallback = [&](memprof::CallStackId CSId) { - llvm::SmallVector Frames; - auto CSIter = MemProfCallStackTable->find(CSId); - if (CSIter == MemProfCallStackTable->end()) { - LastUnmappedCSId = CSId; - } else { - const llvm::SmallVector &CS = *CSIter; - Frames.reserve(CS.size()); - for (memprof::FrameId Id : CS) - Frames.push_back(IdToFrameCallback(Id)); - } - return Frames; - }; + memprof::FrameIdConverter FrameIdConv( + *MemProfFrameTable.get()); const memprof::IndexedMemProfRecord IndexedRecord = *Iter; memprof::MemProfRecord Record; - if (MemProfCallStackTable) - Record = IndexedRecord.toMemProfRecord(CSIdToCallStackCallback); - else - Record = memprof::MemProfRecord(IndexedRecord, IdToFrameCallback); + if (MemProfCallStackTable) { + // Setup a callback to convert call stack ids to call stacks using the + // on-disk hash table. + memprof::CallStackIdConverter CSIdConv( + *MemProfCallStackTable.get(), FrameIdConv); - // Check that all frame ids were successfully converted to frames. - if (LastUnmappedFrameId) { - return make_error(instrprof_error::hash_mismatch, - "memprof frame not found for frame id " + - Twine(*LastUnmappedFrameId)); + Record = IndexedRecord.toMemProfRecord(CSIdConv); + + // Check that all call stack ids were successfully converted to call stacks. + if (CSIdConv.LastUnmappedId) { + return make_error( + instrprof_error::hash_mismatch, + "memprof call stack not found for call stack id " + + Twine(*CSIdConv.LastUnmappedId)); + } + } else { + Record = memprof::MemProfRecord(IndexedRecord, FrameIdConv); } - // Check that all call stack ids were successfully converted to call stacks. - if (LastUnmappedCSId) { + // Check that all frame ids were successfully converted to frames. + if (FrameIdConv.LastUnmappedId) { return make_error( instrprof_error::hash_mismatch, - "memprof call stack not found for call stack id " + - Twine(*LastUnmappedCSId)); + "memprof frame not found for frame id " + + Twine(*FrameIdConv.LastUnmappedId)); } + return Record; } diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index edc427dcbc45..acc633de11b6 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -495,44 +495,6 @@ TEST_F(InstrProfTest, test_memprof_v0) { EXPECT_THAT(WantRecord, EqualsRecord(Record)); } -struct CallStackIdConverter { - std::optional LastUnmappedFrameId; - std::optional LastUnmappedCSId; - - const FrameIdMapTy &IdToFrameMap; - const CallStackIdMapTy &CSIdToCallStackMap; - - CallStackIdConverter() = delete; - CallStackIdConverter(const FrameIdMapTy &IdToFrameMap, - const CallStackIdMapTy &CSIdToCallStackMap) - : IdToFrameMap(IdToFrameMap), CSIdToCallStackMap(CSIdToCallStackMap) {} - - llvm::SmallVector - operator()(::llvm::memprof::CallStackId CSId) { - auto IdToFrameCallback = [&](const memprof::FrameId Id) { - auto Iter = IdToFrameMap.find(Id); - if (Iter == IdToFrameMap.end()) { - LastUnmappedFrameId = Id; - return memprof::Frame(0, 0, 0, false); - } - return Iter->second; - }; - - llvm::SmallVector Frames; - auto CSIter = CSIdToCallStackMap.find(CSId); - if (CSIter == CSIdToCallStackMap.end()) { - LastUnmappedCSId = CSId; - } else { - const ::llvm::SmallVector<::llvm::memprof::FrameId> &CS = - CSIter->getSecond(); - Frames.reserve(CS.size()); - for (::llvm::memprof::FrameId Id : CS) - Frames.push_back(IdToFrameCallback(Id)); - } - return Frames; - } -}; - TEST_F(InstrProfTest, test_memprof_v2_full_schema) { const MemInfoBlock MIB = makeFullMIB(); @@ -562,14 +524,16 @@ TEST_F(InstrProfTest, test_memprof_v2_full_schema) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); + memprof::FrameIdConverter FrameIdConv(IdToFrameMap); + memprof::CallStackIdConverter CSIdConv( + CSIdToCallStackMap, FrameIdConv); const ::llvm::memprof::MemProfRecord WantRecord = IndexedMR.toMemProfRecord(CSIdConv); - ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) - << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; - ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) - << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; + ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt) + << "could not map frame id: " << *FrameIdConv.LastUnmappedId; + ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } @@ -602,14 +566,16 @@ TEST_F(InstrProfTest, test_memprof_v2_partial_schema) { ASSERT_THAT_ERROR(RecordOr.takeError(), Succeeded()); const memprof::MemProfRecord &Record = RecordOr.get(); - CallStackIdConverter CSIdConv(IdToFrameMap, CSIdToCallStackMap); + memprof::FrameIdConverter FrameIdConv(IdToFrameMap); + memprof::CallStackIdConverter CSIdConv( + CSIdToCallStackMap, FrameIdConv); const ::llvm::memprof::MemProfRecord WantRecord = IndexedMR.toMemProfRecord(CSIdConv); - ASSERT_EQ(CSIdConv.LastUnmappedFrameId, std::nullopt) - << "could not map frame id: " << *CSIdConv.LastUnmappedFrameId; - ASSERT_EQ(CSIdConv.LastUnmappedCSId, std::nullopt) - << "could not map call stack id: " << *CSIdConv.LastUnmappedCSId; + ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt) + << "could not map frame id: " << *FrameIdConv.LastUnmappedId; + ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt) + << "could not map call stack id: " << *CSIdConv.LastUnmappedId; EXPECT_THAT(WantRecord, EqualsRecord(Record)); } diff --git a/llvm/unittests/ProfileData/MemProfTest.cpp b/llvm/unittests/ProfileData/MemProfTest.cpp index 98dacd3511e1..d031049cea14 100644 --- a/llvm/unittests/ProfileData/MemProfTest.cpp +++ b/llvm/unittests/ProfileData/MemProfTest.cpp @@ -502,37 +502,15 @@ TEST(MemProf, IndexedMemProfRecordToMemProfRecord) { IndexedRecord.CallSiteIds.push_back(llvm::memprof::hashCallStack(CS3)); IndexedRecord.CallSiteIds.push_back(llvm::memprof::hashCallStack(CS4)); - bool CSIdMissing = false; - bool FrameIdMissing = false; - - auto Callback = [&](CallStackId CSId) -> llvm::SmallVector { - llvm::SmallVector CallStack; - llvm::SmallVector FrameIds; - - auto Iter = CallStackIdMap.find(CSId); - if (Iter == CallStackIdMap.end()) - CSIdMissing = true; - else - FrameIds = Iter->second; - - for (FrameId Id : FrameIds) { - Frame F(0, 0, 0, false); - auto Iter = FrameIdMap.find(Id); - if (Iter == FrameIdMap.end()) - FrameIdMissing = true; - else - F = Iter->second; - CallStack.push_back(F); - } - - return CallStack; - }; - - MemProfRecord Record = IndexedRecord.toMemProfRecord(Callback); + llvm::memprof::FrameIdConverter FrameIdConv(FrameIdMap); + llvm::memprof::CallStackIdConverter CSIdConv( + CallStackIdMap, FrameIdConv); + + MemProfRecord Record = IndexedRecord.toMemProfRecord(CSIdConv); // Make sure that all lookups are successful. - ASSERT_FALSE(CSIdMissing); - ASSERT_FALSE(FrameIdMissing); + ASSERT_EQ(FrameIdConv.LastUnmappedId, std::nullopt); + ASSERT_EQ(CSIdConv.LastUnmappedId, std::nullopt); // Verify the contents of Record. ASSERT_THAT(Record.AllocSites, SizeIs(2)); -- GitLab From c9dae43438897590a21edbc89003bd6704659c7c Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 28 Apr 2024 12:49:08 -0700 Subject: [PATCH 165/301] [memprof] Add access checks to PortableMemInfoBlock::get* (#90121) commit 4c8ec8f8bc3fb4dda4fd36c3b2ad745bd3451970 Author: Kazu Hirata Date: Wed Apr 24 16:25:35 2024 -0700 introduced the idea of serializing/deserializing a subset of the fields in PortableMemInfoBlock. While it reduces the size of the indexed MemProf profile file, we now could inadvertently access unavailable fields and go without noticing. To protect ourselves from the risk, this patch adds access checks to PortableMemInfoBlock::get* methods by embedding a bit set representing available fields into PortableMemInfoBlock. --- llvm/include/llvm/ProfileData/MemProf.h | 39 +++++++++--- llvm/unittests/ProfileData/InstrProfTest.cpp | 8 +-- llvm/unittests/ProfileData/MemProfTest.cpp | 62 +++++++++++++++++++- 3 files changed, 97 insertions(+), 12 deletions(-) diff --git a/llvm/include/llvm/ProfileData/MemProf.h b/llvm/include/llvm/ProfileData/MemProf.h index 8b00faf2a219..4274f2a6849b 100644 --- a/llvm/include/llvm/ProfileData/MemProf.h +++ b/llvm/include/llvm/ProfileData/MemProf.h @@ -2,6 +2,7 @@ #define LLVM_PROFILEDATA_MEMPROF_H_ #include "llvm/ADT/MapVector.h" +#include "llvm/ADT/STLForwardCompat.h" #include "llvm/ADT/STLFunctionalExtras.h" #include "llvm/ADT/SmallVector.h" #include "llvm/IR/GlobalValue.h" @@ -10,6 +11,7 @@ #include "llvm/Support/EndianStream.h" #include "llvm/Support/raw_ostream.h" +#include #include #include @@ -55,7 +57,10 @@ MemProfSchema getHotColdSchema(); // deserialize methods. struct PortableMemInfoBlock { PortableMemInfoBlock() = default; - explicit PortableMemInfoBlock(const MemInfoBlock &Block) { + explicit PortableMemInfoBlock(const MemInfoBlock &Block, + const MemProfSchema &IncomingSchema) { + for (const Meta Id : IncomingSchema) + Schema.set(llvm::to_underlying(Id)); #define MIBEntryDef(NameTag, Name, Type) Name = Block.Name; #include "llvm/ProfileData/MIBEntryDef.inc" #undef MIBEntryDef @@ -67,10 +72,12 @@ struct PortableMemInfoBlock { // Read the contents of \p Ptr based on the \p Schema to populate the // MemInfoBlock member. - void deserialize(const MemProfSchema &Schema, const unsigned char *Ptr) { + void deserialize(const MemProfSchema &IncomingSchema, + const unsigned char *Ptr) { using namespace support; - for (const Meta Id : Schema) { + Schema.reset(); + for (const Meta Id : IncomingSchema) { switch (Id) { #define MIBEntryDef(NameTag, Name, Type) \ case Meta::Name: { \ @@ -82,6 +89,8 @@ struct PortableMemInfoBlock { llvm_unreachable("Unknown meta type id, is the profile collected from " "a newer version of the runtime?"); } + + Schema.set(llvm::to_underlying(Id)); } } @@ -114,17 +123,29 @@ struct PortableMemInfoBlock { #undef MIBEntryDef } + // Return the schema, only for unit tests. + std::bitset getSchema() const { + return Schema; + } + // Define getters for each type which can be called by analyses. #define MIBEntryDef(NameTag, Name, Type) \ - Type get##Name() const { return Name; } + Type get##Name() const { \ + assert(Schema[llvm::to_underlying(Meta::Name)]); \ + return Name; \ + } #include "llvm/ProfileData/MIBEntryDef.inc" #undef MIBEntryDef void clear() { *this = PortableMemInfoBlock(); } bool operator==(const PortableMemInfoBlock &Other) const { + if (Other.Schema != Schema) + return false; + #define MIBEntryDef(NameTag, Name, Type) \ - if (Other.get##Name() != get##Name()) \ + if (Schema[llvm::to_underlying(Meta::Name)] && \ + Other.get##Name() != get##Name()) \ return false; #include "llvm/ProfileData/MIBEntryDef.inc" #undef MIBEntryDef @@ -155,6 +176,9 @@ struct PortableMemInfoBlock { } private: + // The set of available fields, indexed by Meta::Name. + std::bitset Schema; + #define MIBEntryDef(NameTag, Name, Type) Type Name = Type(); #include "llvm/ProfileData/MIBEntryDef.inc" #undef MIBEntryDef @@ -296,8 +320,9 @@ struct IndexedAllocationInfo { IndexedAllocationInfo() = default; IndexedAllocationInfo(ArrayRef CS, CallStackId CSId, - const MemInfoBlock &MB) - : CallStack(CS.begin(), CS.end()), CSId(CSId), Info(MB) {} + const MemInfoBlock &MB, + const MemProfSchema &Schema = getFullSchema()) + : CallStack(CS.begin(), CS.end()), CSId(CSId), Info(MB, Schema) {} // Returns the size in bytes when this allocation info struct is serialized. size_t serializedSize(const MemProfSchema &Schema, diff --git a/llvm/unittests/ProfileData/InstrProfTest.cpp b/llvm/unittests/ProfileData/InstrProfTest.cpp index acc633de11b6..402de64fe99b 100644 --- a/llvm/unittests/ProfileData/InstrProfTest.cpp +++ b/llvm/unittests/ProfileData/InstrProfTest.cpp @@ -407,13 +407,13 @@ IndexedMemProfRecord makeRecord( IndexedMemProfRecord makeRecordV2(std::initializer_list<::llvm::memprof::CallStackId> AllocFrames, std::initializer_list<::llvm::memprof::CallStackId> CallSiteFrames, - const MemInfoBlock &Block) { + const MemInfoBlock &Block, const memprof::MemProfSchema &Schema) { llvm::memprof::IndexedMemProfRecord MR; for (const auto &CSId : AllocFrames) // We don't populate IndexedAllocationInfo::CallStack because we use it only // in Version0 and Version1. MR.AllocSites.emplace_back(::llvm::SmallVector(), CSId, - Block); + Block, Schema); for (const auto &CSId : CallSiteFrames) MR.CallSiteIds.push_back(CSId); return MR; @@ -506,7 +506,7 @@ TEST_F(InstrProfTest, test_memprof_v2_full_schema) { const IndexedMemProfRecord IndexedMR = makeRecordV2( /*AllocFrames=*/{0x111, 0x222}, - /*CallSiteFrames=*/{0x333}, MIB); + /*CallSiteFrames=*/{0x333}, MIB, memprof::getFullSchema()); const FrameIdMapTy IdToFrameMap = getFrameMapping(); const auto CSIdToCallStackMap = getCallStackMapping(); for (const auto &I : IdToFrameMap) { @@ -548,7 +548,7 @@ TEST_F(InstrProfTest, test_memprof_v2_partial_schema) { const IndexedMemProfRecord IndexedMR = makeRecordV2( /*AllocFrames=*/{0x111, 0x222}, - /*CallSiteFrames=*/{0x333}, MIB); + /*CallSiteFrames=*/{0x333}, MIB, memprof::getHotColdSchema()); const FrameIdMapTy IdToFrameMap = getFrameMapping(); const auto CSIdToCallStackMap = getCallStackMapping(); for (const auto &I : IdToFrameMap) { diff --git a/llvm/unittests/ProfileData/MemProfTest.cpp b/llvm/unittests/ProfileData/MemProfTest.cpp index d031049cea14..40335d191ba7 100644 --- a/llvm/unittests/ProfileData/MemProfTest.cpp +++ b/llvm/unittests/ProfileData/MemProfTest.cpp @@ -1,6 +1,7 @@ #include "llvm/ProfileData/MemProf.h" #include "llvm/ADT/DenseMap.h" #include "llvm/ADT/MapVector.h" +#include "llvm/ADT/STLForwardCompat.h" #include "llvm/DebugInfo/DIContext.h" #include "llvm/DebugInfo/Symbolize/SymbolizableModule.h" #include "llvm/IR/Value.h" @@ -241,7 +242,7 @@ TEST(MemProf, PortableWrapper) { /*dealloc_cpu=*/4); const auto Schema = llvm::memprof::getFullSchema(); - PortableMemInfoBlock WriteBlock(Info); + PortableMemInfoBlock WriteBlock(Info, Schema); std::string Buffer; llvm::raw_string_ostream OS(Buffer); @@ -326,6 +327,65 @@ TEST(MemProf, RecordSerializationRoundTripVerion2) { EXPECT_EQ(Record, GotRecord); } +TEST(MemProf, RecordSerializationRoundTripVersion2HotColdSchema) { + const auto Schema = llvm::memprof::getHotColdSchema(); + + MemInfoBlock Info; + Info.AllocCount = 11; + Info.TotalSize = 22; + Info.TotalLifetime = 33; + Info.TotalLifetimeAccessDensity = 44; + + llvm::SmallVector CallStackIds = {0x123, 0x456}; + + llvm::SmallVector CallSiteIds = {0x333, 0x444}; + + IndexedMemProfRecord Record; + for (const auto &CSId : CallStackIds) { + // Use the same info block for both allocation sites. + Record.AllocSites.emplace_back(llvm::SmallVector(), CSId, Info, + Schema); + } + Record.CallSiteIds.assign(CallSiteIds); + + std::bitset SchemaBitSet; + for (auto Id : Schema) + SchemaBitSet.set(llvm::to_underlying(Id)); + + // Verify that SchemaBitSet has the fields we expect and nothing else, which + // we check with count(). + EXPECT_EQ(SchemaBitSet.count(), 4U); + EXPECT_TRUE(SchemaBitSet[llvm::to_underlying(Meta::AllocCount)]); + EXPECT_TRUE(SchemaBitSet[llvm::to_underlying(Meta::TotalSize)]); + EXPECT_TRUE(SchemaBitSet[llvm::to_underlying(Meta::TotalLifetime)]); + EXPECT_TRUE( + SchemaBitSet[llvm::to_underlying(Meta::TotalLifetimeAccessDensity)]); + + // Verify that Schema has propagated all the way to the Info field in each + // IndexedAllocationInfo. + ASSERT_THAT(Record.AllocSites, ::SizeIs(2)); + EXPECT_EQ(Record.AllocSites[0].Info.getSchema(), SchemaBitSet); + EXPECT_EQ(Record.AllocSites[1].Info.getSchema(), SchemaBitSet); + + std::string Buffer; + llvm::raw_string_ostream OS(Buffer); + Record.serialize(Schema, OS, llvm::memprof::Version2); + OS.flush(); + + const IndexedMemProfRecord GotRecord = IndexedMemProfRecord::deserialize( + Schema, reinterpret_cast(Buffer.data()), + llvm::memprof::Version2); + + // Verify that Schema comes back correctly after deserialization. Technically, + // the comparison between Record and GotRecord below includes the comparison + // of their Schemas, but we'll verify the Schemas on our own. + ASSERT_THAT(GotRecord.AllocSites, ::SizeIs(2)); + EXPECT_EQ(GotRecord.AllocSites[0].Info.getSchema(), SchemaBitSet); + EXPECT_EQ(GotRecord.AllocSites[1].Info.getSchema(), SchemaBitSet); + + EXPECT_EQ(Record, GotRecord); +} + TEST(MemProf, SymbolizationFilter) { std::unique_ptr Symbolizer(new MockSymbolizer()); -- GitLab From fac349a169976f822fb27f03e623fa0d28aec1f3 Mon Sep 17 00:00:00 2001 From: Christian Sigg Date: Sun, 28 Apr 2024 22:01:42 +0200 Subject: [PATCH 166/301] =?UTF-8?q?Reapply=20"[mlir]=20Mark=20`isa/dyn=5Fc?= =?UTF-8?q?ast/cast/...`=20member=20functions=20depreca=E2=80=A6=20(#90406?= =?UTF-8?q?)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …ted. (#89998)" (#90250) This partially reverts commit 7aedd7dc754c74a49fe84ed2640e269c25414087. This change removes calls to the deprecated member functions. It does not mark the functions deprecated yet and does not disable the deprecation warning in TypeSwitch. This seems to cause problems with MSVC. --- flang/include/flang/Lower/Mangler.h | 2 +- .../flang/Optimizer/Analysis/TBAAForest.h | 2 +- .../flang/Optimizer/Builder/BoxValue.h | 20 +- .../include/flang/Optimizer/Builder/Factory.h | 12 +- .../flang/Optimizer/Builder/HLFIRTools.h | 14 +- .../flang/Optimizer/Builder/IntrinsicCall.h | 4 +- .../Optimizer/Builder/PPCIntrinsicCall.h | 6 +- .../Dialect/CanonicalizationPatterns.td | 23 +- .../include/flang/Optimizer/Dialect/FIROps.td | 12 +- .../include/flang/Optimizer/Dialect/FIRType.h | 74 ++--- .../flang/Optimizer/Dialect/FIRTypes.td | 2 +- .../Dialect/FortranVariableInterface.td | 10 +- .../flang/Optimizer/HLFIR/HLFIRDialect.h | 20 +- flang/include/flang/Optimizer/Support/Utils.h | 4 +- flang/include/flang/Tools/PointerModels.h | 4 +- flang/lib/Lower/Allocatable.cpp | 12 +- flang/lib/Lower/Bridge.cpp | 39 +-- flang/lib/Lower/CallInterface.cpp | 6 +- flang/lib/Lower/ConvertArrayConstructor.cpp | 11 +- flang/lib/Lower/ConvertCall.cpp | 56 ++-- flang/lib/Lower/ConvertConstant.cpp | 23 +- flang/lib/Lower/ConvertExpr.cpp | 188 +++++------ flang/lib/Lower/ConvertExprToHLFIR.cpp | 28 +- .../lib/Lower/ConvertProcedureDesignator.cpp | 6 +- flang/lib/Lower/ConvertVariable.cpp | 22 +- flang/lib/Lower/CustomIntrinsicCall.cpp | 35 +- flang/lib/Lower/DirectivesCommon.h | 24 +- flang/lib/Lower/HlfirIntrinsics.cpp | 4 +- flang/lib/Lower/HostAssociations.cpp | 14 +- flang/lib/Lower/IO.cpp | 55 ++-- flang/lib/Lower/OpenACC.cpp | 4 +- flang/lib/Lower/OpenMP/ClauseProcessor.cpp | 8 +- flang/lib/Lower/OpenMP/OpenMP.cpp | 12 +- flang/lib/Lower/OpenMP/ReductionProcessor.cpp | 18 +- flang/lib/Lower/VectorSubscripts.cpp | 2 +- .../lib/Optimizer/Analysis/AliasAnalysis.cpp | 4 +- flang/lib/Optimizer/Builder/BoxValue.cpp | 4 +- flang/lib/Optimizer/Builder/Character.cpp | 41 +-- flang/lib/Optimizer/Builder/Complex.cpp | 3 +- flang/lib/Optimizer/Builder/FIRBuilder.cpp | 107 ++++--- flang/lib/Optimizer/Builder/HLFIRTools.cpp | 78 +++-- flang/lib/Optimizer/Builder/IntrinsicCall.cpp | 107 ++++--- flang/lib/Optimizer/Builder/MutableBox.cpp | 35 +- .../Optimizer/Builder/PPCIntrinsicCall.cpp | 44 ++- .../Optimizer/Builder/Runtime/Allocatable.cpp | 2 +- .../Optimizer/Builder/Runtime/Character.cpp | 8 +- .../Optimizer/Builder/Runtime/Intrinsics.cpp | 6 +- .../lib/Optimizer/Builder/Runtime/Ragged.cpp | 3 +- .../Optimizer/Builder/Runtime/Reduction.cpp | 20 +- .../lib/Optimizer/CodeGen/BoxedProcedure.cpp | 16 +- flang/lib/Optimizer/CodeGen/CGOps.cpp | 14 +- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 203 ++++++------ flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp | 18 +- flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp | 13 +- flang/lib/Optimizer/CodeGen/TBAABuilder.cpp | 2 +- flang/lib/Optimizer/CodeGen/Target.cpp | 4 +- flang/lib/Optimizer/CodeGen/TargetRewrite.cpp | 21 +- flang/lib/Optimizer/CodeGen/TypeConverter.cpp | 18 +- flang/lib/Optimizer/Dialect/FIRAttr.cpp | 14 +- flang/lib/Optimizer/Dialect/FIROps.cpp | 302 +++++++++--------- flang/lib/Optimizer/Dialect/FIRType.cpp | 121 +++---- .../Dialect/FortranVariableInterface.cpp | 11 +- flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp | 30 +- flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp | 192 ++++++----- .../HLFIR/Transforms/BufferizeHLFIR.cpp | 29 +- .../HLFIR/Transforms/ConvertToFIR.cpp | 47 +-- .../HLFIR/Transforms/LowerHLFIRIntrinsics.cpp | 2 +- .../LowerHLFIROrderedAssignments.cpp | 2 +- .../Transforms/OptimizedBufferization.cpp | 12 +- .../Transforms/SimplifyHLFIRIntrinsics.cpp | 3 +- .../Optimizer/Transforms/AbstractResult.cpp | 16 +- .../lib/Optimizer/Transforms/AddDebugInfo.cpp | 6 +- .../Optimizer/Transforms/AffineDemotion.cpp | 9 +- .../Optimizer/Transforms/AffinePromotion.cpp | 11 +- .../Optimizer/Transforms/ArrayValueCopy.cpp | 30 +- .../Transforms/CharacterConversion.cpp | 4 +- .../Optimizer/Transforms/LoopVersioning.cpp | 2 +- .../Optimizer/Transforms/MemoryAllocation.cpp | 2 +- .../Transforms/PolymorphicOpConversion.cpp | 38 +-- .../Transforms/SimplifyIntrinsics.cpp | 52 +-- .../lib/Optimizer/Transforms/StackArrays.cpp | 2 +- .../Optimizer/Builder/ComplexTest.cpp | 2 +- .../Optimizer/Builder/DoLoopHelperTest.cpp | 2 +- .../Optimizer/Builder/FIRBuilderTest.cpp | 48 +-- flang/unittests/Optimizer/RTBuilder.cpp | 2 +- .../mlir/Dialect/Linalg/IR/LinalgOps.td | 4 +- .../Dialect/OpenMP/OpenMPOpsInterfaces.td | 8 +- .../include/mlir/Dialect/XeGPU/IR/XeGPUOps.td | 10 +- .../mlir/IR/BuiltinLocationAttributes.td | 13 +- mlir/include/mlir/IR/Value.h | 8 +- .../ComplexToStandard/ComplexToStandard.cpp | 2 +- .../Polynomial/IR/PolynomialAttributes.cpp | 2 +- .../Vector/Transforms/VectorLinearize.cpp | 16 +- 93 files changed, 1326 insertions(+), 1275 deletions(-) diff --git a/flang/include/flang/Lower/Mangler.h b/flang/include/flang/Lower/Mangler.h index 41939abe29e5..99da96b0d6ba 100644 --- a/flang/include/flang/Lower/Mangler.h +++ b/flang/include/flang/Lower/Mangler.h @@ -90,7 +90,7 @@ inline std::string mangleArrayLiteral( return mangleArrayLiteral(x.values().size() * sizeof(x.values()[0]), x.shape(), Fortran::common::TypeCategory::Derived, /*kind=*/0, /*charLen=*/-1, - eleTy.cast().getName()); + mlir::cast(eleTy).getName()); } /// Return the compiler-generated name of a static namelist variable descriptor. diff --git a/flang/include/flang/Optimizer/Analysis/TBAAForest.h b/flang/include/flang/Optimizer/Analysis/TBAAForest.h index b69e50bbe05c..619ed4939c51 100644 --- a/flang/include/flang/Optimizer/Analysis/TBAAForest.h +++ b/flang/include/flang/Optimizer/Analysis/TBAAForest.h @@ -88,7 +88,7 @@ public: // name must be used so that we add to the tbaa tree added in the FIR pass mlir::Attribute attr = func->getAttr(getInternalFuncNameAttrName()); if (attr) { - return getFuncTree(attr.cast()); + return getFuncTree(mlir::cast(attr)); } return getFuncTree(func.getSymNameAttr()); } diff --git a/flang/include/flang/Optimizer/Builder/BoxValue.h b/flang/include/flang/Optimizer/Builder/BoxValue.h index 2fed2d48a7a0..5c7e89dbc08f 100644 --- a/flang/include/flang/Optimizer/Builder/BoxValue.h +++ b/flang/include/flang/Optimizer/Builder/BoxValue.h @@ -78,7 +78,7 @@ class CharBoxValue : public AbstractBox { public: CharBoxValue(mlir::Value addr, mlir::Value len) : AbstractBox{addr}, len{len} { - if (addr && addr.getType().template isa()) + if (addr && mlir::isa(addr.getType())) fir::emitFatalError(addr.getLoc(), "BoxChar should not be in CharBoxValue"); } @@ -221,7 +221,7 @@ public: auto type = getAddr().getType(); if (auto pointedTy = fir::dyn_cast_ptrEleTy(type)) type = pointedTy; - return type.cast(); + return mlir::cast(type); } /// Return the part of the address type after memory and box types. That is /// the element type, maybe wrapped in a fir.array type. @@ -243,22 +243,22 @@ public: /// Get the scalar type related to the described entity mlir::Type getEleTy() const { auto type = getBaseTy(); - if (auto seqTy = type.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(type)) return seqTy.getEleTy(); return type; } /// Is the entity an array or an assumed rank ? - bool hasRank() const { return getBaseTy().isa(); } + bool hasRank() const { return mlir::isa(getBaseTy()); } /// Is this an assumed rank ? bool hasAssumedRank() const { - auto seqTy = getBaseTy().dyn_cast(); + auto seqTy = mlir::dyn_cast(getBaseTy()); return seqTy && seqTy.hasUnknownShape(); } /// Returns the rank of the entity. Beware that zero will be returned for /// both scalars and assumed rank. unsigned rank() const { - if (auto seqTy = getBaseTy().dyn_cast()) + if (auto seqTy = mlir::dyn_cast(getBaseTy())) return seqTy.getDimension(); return 0; } @@ -267,7 +267,7 @@ public: bool isCharacter() const { return fir::isa_char(getEleTy()); } /// Is this a derived type entity ? - bool isDerived() const { return getEleTy().isa(); } + bool isDerived() const { return mlir::isa(getEleTy()); } bool isDerivedWithLenParameters() const { return fir::isRecordWithTypeParameters(getEleTy()); @@ -377,11 +377,11 @@ public: } /// Is this a Fortran pointer ? bool isPointer() const { - return getBoxTy().getEleTy().isa(); + return mlir::isa(getBoxTy().getEleTy()); } /// Is this an allocatable ? bool isAllocatable() const { - return getBoxTy().getEleTy().isa(); + return mlir::isa(getBoxTy().getEleTy()); } // Replace the fir.ref, keeping any non-deferred parameters. MutableBoxValue clone(mlir::Value newBox) const { @@ -488,7 +488,7 @@ public: if (const auto *b = getUnboxed()) { if (*b) { auto type = b->getType(); - if (type.template isa()) + if (mlir::isa(type)) fir::emitFatalError(b->getLoc(), "BoxChar should be unboxed"); type = fir::unwrapSequenceType(fir::unwrapRefType(type)); if (fir::isa_char(type)) diff --git a/flang/include/flang/Optimizer/Builder/Factory.h b/flang/include/flang/Optimizer/Builder/Factory.h index ec294d26ac96..4e5c52ac44e0 100644 --- a/flang/include/flang/Optimizer/Builder/Factory.h +++ b/flang/include/flang/Optimizer/Builder/Factory.h @@ -43,9 +43,9 @@ template void genCharacterCopy(mlir::Value src, mlir::Value srcLen, mlir::Value dst, mlir::Value dstLen, B &builder, mlir::Location loc) { auto srcTy = - fir::dyn_cast_ptrEleTy(src.getType()).template cast(); + mlir::cast(fir::dyn_cast_ptrEleTy(src.getType())); auto dstTy = - fir::dyn_cast_ptrEleTy(dst.getType()).template cast(); + mlir::cast(fir::dyn_cast_ptrEleTy(dst.getType())); if (!srcLen && !dstLen && srcTy.getFKind() == dstTy.getFKind() && srcTy.getLen() == dstTy.getLen()) { // same size, so just use load and store @@ -61,8 +61,8 @@ void genCharacterCopy(mlir::Value src, mlir::Value srcLen, mlir::Value dst, fir::CharacterType::getSingleton(ty.getContext(), ty.getFKind()))); }; auto toEleTy = [&](fir::ReferenceType ty) { - auto seqTy = ty.getEleTy().cast(); - return seqTy.getEleTy().cast(); + auto seqTy = mlir::cast(ty.getEleTy()); + return mlir::cast(seqTy.getEleTy()); }; auto toCoorTy = [&](fir::ReferenceType ty) { return fir::ReferenceType::get(toEleTy(ty)); @@ -190,8 +190,8 @@ originateIndices(mlir::Location loc, B &builder, mlir::Type memTy, if (origins.empty()) { assert(!shapeVal || mlir::isa(shapeVal.getDefiningOp())); auto ty = fir::dyn_cast_ptrOrBoxEleTy(memTy); - assert(ty && ty.isa()); - auto seqTy = ty.cast(); + assert(ty && mlir::isa(ty)); + auto seqTy = mlir::cast(ty); auto one = builder.template create(loc, 1); const auto dimension = seqTy.getDimension(); if (shapeVal) { diff --git a/flang/include/flang/Optimizer/Builder/HLFIRTools.h b/flang/include/flang/Optimizer/Builder/HLFIRTools.h index 035035601e2f..6c36f7e84db6 100644 --- a/flang/include/flang/Optimizer/Builder/HLFIRTools.h +++ b/flang/include/flang/Optimizer/Builder/HLFIRTools.h @@ -77,12 +77,12 @@ public: /// Return the rank of this entity or -1 if it is an assumed rank. int getRank() const { mlir::Type type = fir::unwrapPassByRefType(fir::unwrapRefType(getType())); - if (auto seqTy = type.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(type)) { if (seqTy.hasUnknownShape()) return -1; return seqTy.getDimension(); } - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.getRank(); return 0; } @@ -99,17 +99,17 @@ public: bool hasLengthParameters() const { mlir::Type eleTy = getFortranElementType(); - return eleTy.isa() || + return mlir::isa(eleTy) || fir::isRecordWithTypeParameters(eleTy); } bool isCharacter() const { - return getFortranElementType().isa(); + return mlir::isa(getFortranElementType()); } bool hasIntrinsicType() const { mlir::Type eleTy = getFortranElementType(); - return fir::isa_trivial(eleTy) || eleTy.isa(); + return fir::isa_trivial(eleTy) || mlir::isa(eleTy); } bool isDerivedWithLengthParameters() const { @@ -124,8 +124,8 @@ public: if (auto varIface = getIfVariableInterface()) { if (auto shape = varIface.getShape()) { auto shapeTy = shape.getType(); - return shapeTy.isa() || - shapeTy.isa(); + return mlir::isa(shapeTy) || + mlir::isa(shapeTy); } return false; } diff --git a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h index 604f2bd969ee..b7d060926761 100644 --- a/flang/include/flang/Optimizer/Builder/IntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/IntrinsicCall.h @@ -663,8 +663,8 @@ static inline mlir::FunctionType genFuncType(mlir::MLIRContext *context, //===----------------------------------------------------------------------===// static inline mlir::Type getConvertedElementType(mlir::MLIRContext *context, mlir::Type eleTy) { - if (eleTy.isa() && !eleTy.isSignlessInteger()) { - const auto intTy{eleTy.dyn_cast()}; + if (mlir::isa(eleTy) && !eleTy.isSignlessInteger()) { + const auto intTy{mlir::dyn_cast(eleTy)}; auto newEleTy{mlir::IntegerType::get(context, intTy.getWidth())}; return newEleTy; } diff --git a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h index 1e87bf0f6ad1..a7c4c075d818 100644 --- a/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h +++ b/flang/include/flang/Optimizer/Builder/PPCIntrinsicCall.h @@ -180,10 +180,10 @@ struct VecTypeInfo { // Returns a VecTypeInfo with element type and length of given fir vector type. // Preserves signness of fir vector type if element type of integer. static inline VecTypeInfo getVecTypeFromFirType(mlir::Type firTy) { - assert(firTy.isa()); + assert(mlir::isa(firTy)); VecTypeInfo vecTyInfo; - vecTyInfo.eleTy = firTy.dyn_cast().getEleTy(); - vecTyInfo.len = firTy.dyn_cast().getLen(); + vecTyInfo.eleTy = mlir::dyn_cast(firTy).getEleTy(); + vecTyInfo.len = mlir::dyn_cast(firTy).getLen(); return vecTyInfo; } diff --git a/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td b/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td index 544fc3cdf75e..0ef37a37ce94 100644 --- a/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td +++ b/flang/include/flang/Optimizer/Dialect/CanonicalizationPatterns.td @@ -21,17 +21,18 @@ include "flang/Optimizer/Dialect/FIROps.td" def IdenticalTypePred : Constraint>; def IntegerTypePred : Constraint>; -def IndexTypePred : Constraint()">>; +def IndexTypePred : Constraint($0.getType())">>; // Widths are monotonic. // $0.bits >= $1.bits >= $2.bits or $0.bits <= $1.bits <= $2.bits def MonotonicTypePred - : Constraint() && " - " $1.getType().isa() && " - " $2.getType().isa()) || " - " ($0.getType().isa() && " - " $1.getType().isa() && " - " $2.getType().isa())) && " + : Constraint($0.getType()) && " + " mlir::isa($1.getType()) && " + " mlir::isa($2.getType())) || " + " (mlir::isa($0.getType()) && " + " mlir::isa($1.getType()) && " + " mlir::isa($2.getType()))) && " "(($0.getType().getIntOrFloatBitWidth() <= " " $1.getType().getIntOrFloatBitWidth() && " " $1.getType().getIntOrFloatBitWidth() <= " @@ -42,8 +43,8 @@ def MonotonicTypePred " $2.getType().getIntOrFloatBitWidth()))">>; def IntPred : Constraint() && " - "$1.getType().isa()">>; + "mlir::isa($0.getType()) && " + "mlir::isa($1.getType())">>; // If both are int type and the first is smaller than the second. // $0.bits <= $1.bits @@ -101,8 +102,8 @@ def CombineConvertTruncOptPattern def createConstantOp : NativeCodeCall<"$_builder.create" "($_loc, $_builder.getIndexType(), " - "rewriter.getIndexAttr($1.dyn_cast()" - ".getInt()))">; + "rewriter.getIndexAttr(" + "mlir::dyn_cast($1).getInt()))">; def ForwardConstantConvertPattern : Pat<(fir_ConvertOp:$res (Arith_ConstantOp:$cnt $attr)), diff --git a/flang/include/flang/Optimizer/Dialect/FIROps.td b/flang/include/flang/Optimizer/Dialect/FIROps.td index 92790a691e47..496193e25cab 100644 --- a/flang/include/flang/Optimizer/Dialect/FIROps.td +++ b/flang/include/flang/Optimizer/Dialect/FIROps.td @@ -2708,14 +2708,14 @@ def fir_ConvertOp : fir_OneResultOp<"convert", [NoMemoryEffect]> { let hasCanonicalizer = 1; } -def FortranTypeAttr : Attr()">, - Or<[CPred<"$_self.cast().getValue().isa()">]>]>, - "Fortran surface type"> { +def FortranTypeAttr : Attr($_self)">, + Or<[CPred<"mlir::isa(mlir::cast($_self).getValue())" + >]>]>, "Fortran surface type"> { let storageType = [{ ::mlir::TypeAttr }]; let returnType = "mlir::Type"; - let convertFromStorage = "$_self.getValue().cast()"; + let convertFromStorage = "mlir::cast($_self.getValue())"; } def fir_TypeDescOp : fir_OneResultOp<"type_desc", [NoMemoryEffect]> { diff --git a/flang/include/flang/Optimizer/Dialect/FIRType.h b/flang/include/flang/Optimizer/Dialect/FIRType.h index 7fcd9c1babf2..b4344435db9f 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRType.h +++ b/flang/include/flang/Optimizer/Dialect/FIRType.h @@ -97,35 +97,36 @@ bool isa_fir_or_std_type(mlir::Type t); /// Is `t` a FIR dialect type that implies a memory (de)reference? inline bool isa_ref_type(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a boxed type? inline bool isa_box_type(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a type that is always trivially pass-by-reference? Specifically, this /// is testing if `t` is a ReferenceType or any box type. Compare this to /// conformsWithPassByRef(), which includes pointers and allocatables. inline bool isa_passbyref_type(mlir::Type t) { - return t.isa() || isa_box_type(t); + return mlir::isa(t) || + isa_box_type(t); } /// Is `t` a type that can conform to be pass-by-reference? Depending on the /// context, these types may simply demote to pass-by-reference or a reference /// to them may have to be passed instead. Functions are always referent. inline bool conformsWithPassByRef(mlir::Type t) { - return isa_ref_type(t) || isa_box_type(t) || t.isa(); + return isa_ref_type(t) || isa_box_type(t) || mlir::isa(t); } /// Is `t` a derived (record) type? -inline bool isa_derived(mlir::Type t) { return t.isa(); } +inline bool isa_derived(mlir::Type t) { return mlir::isa(t); } /// Is `t` type(c_ptr) or type(c_funptr)? inline bool isa_builtin_cptr_type(mlir::Type t) { - if (auto recTy = t.dyn_cast_or_null()) + if (auto recTy = mlir::dyn_cast_or_null(t)) return recTy.getName().ends_with("T__builtin_c_ptr") || recTy.getName().ends_with("T__builtin_c_funptr"); return false; @@ -133,7 +134,7 @@ inline bool isa_builtin_cptr_type(mlir::Type t) { /// Is `t` a FIR dialect aggregate type? inline bool isa_aggregate(mlir::Type t) { - return t.isa() || fir::isa_derived(t); + return mlir::isa(t) || fir::isa_derived(t); } /// Extract the `Type` pointed to from a FIR memory reference type. If `t` is @@ -146,17 +147,17 @@ mlir::Type dyn_cast_ptrOrBoxEleTy(mlir::Type t); /// Is `t` a FIR Real or MLIR Float type? inline bool isa_real(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` an integral type? inline bool isa_integer(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a vector type? inline bool isa_vector(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } mlir::Type parseFirType(FIROpsDialect *, mlir::DialectAsmParser &parser); @@ -169,22 +170,22 @@ void verifyIntegralType(mlir::Type type); /// Is `t` a FIR or MLIR Complex type? inline bool isa_complex(mlir::Type t) { - return t.isa(); + return mlir::isa(t); } /// Is `t` a CHARACTER type? Does not check the length. -inline bool isa_char(mlir::Type t) { return t.isa(); } +inline bool isa_char(mlir::Type t) { return mlir::isa(t); } /// Is `t` a trivial intrinsic type? CHARACTER is excluded because it /// is a dependent type. inline bool isa_trivial(mlir::Type t) { return isa_integer(t) || isa_real(t) || isa_complex(t) || isa_vector(t) || - t.isa(); + mlir::isa(t); } /// Is `t` a CHARACTER type with a LEN other than 1? inline bool isa_char_string(mlir::Type t) { - if (auto ct = t.dyn_cast_or_null()) + if (auto ct = mlir::dyn_cast_or_null(t)) return ct.getLen() != fir::CharacterType::singleton(); return false; } @@ -198,7 +199,7 @@ bool isa_unknown_size_box(mlir::Type t); /// Returns true iff `t` is a fir.char type and has an unknown length. inline bool characterWithDynamicLen(mlir::Type t) { - if (auto charTy = t.dyn_cast()) + if (auto charTy = mlir::dyn_cast(t)) return charTy.hasDynamicLen(); return false; } @@ -213,11 +214,11 @@ inline bool sequenceWithNonConstantShape(fir::SequenceType seqTy) { bool hasDynamicSize(mlir::Type t); inline unsigned getRankOfShapeType(mlir::Type t) { - if (auto shTy = t.dyn_cast()) + if (auto shTy = mlir::dyn_cast(t)) return shTy.getRank(); - if (auto shTy = t.dyn_cast()) + if (auto shTy = mlir::dyn_cast(t)) return shTy.getRank(); - if (auto shTy = t.dyn_cast()) + if (auto shTy = mlir::dyn_cast(t)) return shTy.getRank(); return 0; } @@ -225,14 +226,14 @@ inline unsigned getRankOfShapeType(mlir::Type t) { /// Get the memory reference type of the data pointer from the box type, inline mlir::Type boxMemRefType(fir::BaseBoxType t) { auto eleTy = t.getEleTy(); - if (!eleTy.isa()) + if (!mlir::isa(eleTy)) eleTy = fir::ReferenceType::get(t); return eleTy; } /// If `t` is a SequenceType return its element type, otherwise return `t`. inline mlir::Type unwrapSequenceType(mlir::Type t) { - if (auto seqTy = t.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(t)) return seqTy.getEleTy(); return t; } @@ -278,7 +279,7 @@ inline fir::SequenceType unwrapUntilSeqType(mlir::Type t) { t = ty; continue; } - if (auto seqTy = t.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(t)) return seqTy; return {}; } @@ -287,8 +288,8 @@ inline fir::SequenceType unwrapUntilSeqType(mlir::Type t) { /// Unwrap the referential and sequential outer types (if any). Returns the /// the element if type is fir::RecordType inline fir::RecordType unwrapIfDerived(fir::BaseBoxType boxTy) { - return fir::unwrapSequenceType(fir::unwrapRefType(boxTy.getEleTy())) - .template dyn_cast(); + return mlir::dyn_cast( + fir::unwrapSequenceType(fir::unwrapRefType(boxTy.getEleTy()))); } /// Return true iff `boxTy` wraps a fir::RecordType with length parameters @@ -377,7 +378,7 @@ bool isRecordWithDescriptorMember(mlir::Type ty); /// Return true iff `ty` is a RecordType with type parameters. inline bool isRecordWithTypeParameters(mlir::Type ty) { - if (auto recTy = ty.dyn_cast_or_null()) + if (auto recTy = mlir::dyn_cast_or_null(ty)) return recTy.isDependentType(); return false; } @@ -401,14 +402,14 @@ mlir::Type fromRealTypeID(mlir::MLIRContext *context, llvm::Type::TypeID typeID, int getTypeCode(mlir::Type ty, const KindMapping &kindMap); inline bool BaseBoxType::classof(mlir::Type type) { - return type.isa(); + return mlir::isa(type); } /// Return true iff `ty` is none or fir.array. inline bool isNoneOrSeqNone(mlir::Type type) { - if (auto seqTy = type.dyn_cast()) - return seqTy.getEleTy().isa(); - return type.isa(); + if (auto seqTy = mlir::dyn_cast(type)) + return mlir::isa(seqTy.getEleTy()); + return mlir::isa(type); } /// Return a fir.box or fir.class if the type is polymorphic. If the type @@ -428,16 +429,16 @@ inline mlir::Type wrapInClassOrBoxType(mlir::Type eleTy, /// !fir.array<2xf32> -> !fir.array<2xnone> /// !fir.heap> -> !fir.heap> inline mlir::Type updateTypeForUnlimitedPolymorphic(mlir::Type ty) { - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return fir::SequenceType::get( seqTy.getShape(), updateTypeForUnlimitedPolymorphic(seqTy.getEleTy())); - if (auto heapTy = ty.dyn_cast()) + if (auto heapTy = mlir::dyn_cast(ty)) return fir::HeapType::get( updateTypeForUnlimitedPolymorphic(heapTy.getEleTy())); - if (auto pointerTy = ty.dyn_cast()) + if (auto pointerTy = mlir::dyn_cast(ty)) return fir::PointerType::get( updateTypeForUnlimitedPolymorphic(pointerTy.getEleTy())); - if (!ty.isa()) + if (!mlir::isa(ty)) return mlir::NoneType::get(ty.getContext()); return ty; } @@ -451,18 +452,19 @@ mlir::Type changeElementType(mlir::Type type, mlir::Type newElementType, /// Is `t` an address to fir.box or class type? inline bool isBoxAddress(mlir::Type t) { - return fir::isa_ref_type(t) && fir::unwrapRefType(t).isa(); + return fir::isa_ref_type(t) && + mlir::isa(fir::unwrapRefType(t)); } /// Is `t` a fir.box or class address or value type? inline bool isBoxAddressOrValue(mlir::Type t) { - return fir::unwrapRefType(t).isa(); + return mlir::isa(fir::unwrapRefType(t)); } /// Is this a fir.boxproc address type? inline bool isBoxProcAddressType(mlir::Type t) { t = fir::dyn_cast_ptrEleTy(t); - return t && t.isa(); + return t && mlir::isa(t); } /// Return a string representation of `ty`. diff --git a/flang/include/flang/Optimizer/Dialect/FIRTypes.td b/flang/include/flang/Optimizer/Dialect/FIRTypes.td index 3b876e4642da..7378ed93944c 100644 --- a/flang/include/flang/Optimizer/Dialect/FIRTypes.td +++ b/flang/include/flang/Optimizer/Dialect/FIRTypes.td @@ -578,7 +578,7 @@ def fir_VoidType : FIR_Type<"Void", "void"> { // Whether a type is a BaseBoxType def IsBaseBoxTypePred - : CPred<"$_self.isa<::fir::BaseBoxType>()">; + : CPred<"mlir::isa<::fir::BaseBoxType>($_self)">; def fir_BaseBoxType : Type; // Generalized FIR and standard dialect types representing intrinsic types diff --git a/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td b/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td index 6405afbf1bfb..3f78a93a2515 100644 --- a/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td +++ b/flang/include/flang/Optimizer/Dialect/FortranVariableInterface.td @@ -75,7 +75,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// variable. mlir::Type getElementOrSequenceType() { mlir::Type type = fir::unwrapPassByRefType(fir::unwrapRefType(getBase().getType())); - if (auto boxCharType = type.dyn_cast()) + if (auto boxCharType = mlir::dyn_cast(type)) return boxCharType.getEleTy(); return type; } @@ -87,13 +87,13 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is the variable an array? bool isArray() { - return getElementOrSequenceType().isa(); + return mlir::isa(getElementOrSequenceType()); } /// Return the rank of the entity if it is known at compile time. std::optional getRank() { if (auto sequenceType = - getElementOrSequenceType().dyn_cast()) { + mlir::dyn_cast(getElementOrSequenceType())) { if (sequenceType.hasUnknownShape()) return {}; return sequenceType.getDimension(); @@ -133,7 +133,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is this a Fortran character variable? bool isCharacter() { - return getElementType().isa(); + return mlir::isa(getElementType()); } /// Is this a Fortran character variable with an explicit length? @@ -149,7 +149,7 @@ def fir_FortranVariableOpInterface : OpInterface<"FortranVariableOpInterface"> { /// Is this variable represented as a fir.box or fir.class value? bool isBoxValue() { - return getBase().getType().isa(); + return mlir::isa(getBase().getType()); } /// Is this variable represented as a fir.box or fir.class address? diff --git a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h index aa68d0811c48..3830237f96f3 100644 --- a/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h +++ b/flang/include/flang/Optimizer/HLFIR/HLFIRDialect.h @@ -40,9 +40,9 @@ namespace hlfir { inline mlir::Type getFortranElementType(mlir::Type type) { type = fir::unwrapSequenceType( fir::unwrapPassByRefType(fir::unwrapRefType(type))); - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.getEleTy(); - if (auto boxCharType = type.dyn_cast()) + if (auto boxCharType = mlir::dyn_cast(type)) return boxCharType.getEleTy(); return type; } @@ -51,12 +51,12 @@ inline mlir::Type getFortranElementType(mlir::Type type) { /// fir.array type. Otherwise, returns the Fortran element typeof the entity. inline mlir::Type getFortranElementOrSequenceType(mlir::Type type) { type = fir::unwrapPassByRefType(fir::unwrapRefType(type)); - if (auto exprType = type.dyn_cast()) { + if (auto exprType = mlir::dyn_cast(type)) { if (exprType.isArray()) return fir::SequenceType::get(exprType.getShape(), exprType.getEleTy()); return exprType.getEleTy(); } - if (auto boxCharType = type.dyn_cast()) + if (auto boxCharType = mlir::dyn_cast(type)) return boxCharType.getEleTy(); return type; } @@ -64,16 +64,16 @@ inline mlir::Type getFortranElementOrSequenceType(mlir::Type type) { /// Is this a fir.box or fir.class address type? inline bool isBoxAddressType(mlir::Type type) { type = fir::dyn_cast_ptrEleTy(type); - return type && type.isa(); + return type && mlir::isa(type); } /// Is this a fir.box or fir.class address or value type? inline bool isBoxAddressOrValueType(mlir::Type type) { - return fir::unwrapRefType(type).isa(); + return mlir::isa(fir::unwrapRefType(type)); } inline bool isPolymorphicType(mlir::Type type) { - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.isPolymorphic(); return fir::isPolymorphicType(type); } @@ -81,14 +81,14 @@ inline bool isPolymorphicType(mlir::Type type) { /// Is this an SSA value type for the value of a Fortran procedure /// designator ? inline bool isFortranProcedureValue(mlir::Type type) { - return type.isa() || - (type.isa() && + return mlir::isa(type) || + (mlir::isa(type) && fir::isCharacterProcedureTuple(type, /*acceptRawFunc=*/false)); } /// Is this an SSA value type for the value of a Fortran expression? inline bool isFortranValueType(mlir::Type type) { - return type.isa() || fir::isa_trivial(type) || + return mlir::isa(type) || fir::isa_trivial(type) || isFortranProcedureValue(type); } diff --git a/flang/include/flang/Optimizer/Support/Utils.h b/flang/include/flang/Optimizer/Support/Utils.h index 2b4fa50e0e42..2da6f24da40e 100644 --- a/flang/include/flang/Optimizer/Support/Utils.h +++ b/flang/include/flang/Optimizer/Support/Utils.h @@ -29,7 +29,9 @@ namespace fir { /// Return the integer value of a arith::ConstantOp. inline std::int64_t toInt(mlir::arith::ConstantOp cop) { - return cop.getValue().cast().getValue().getSExtValue(); + return mlir::cast(cop.getValue()) + .getValue() + .getSExtValue(); } // Reconstruct binding tables for dynamic dispatch. diff --git a/flang/include/flang/Tools/PointerModels.h b/flang/include/flang/Tools/PointerModels.h index 7acaf2f9fda5..c3c0977d6e54 100644 --- a/flang/include/flang/Tools/PointerModels.h +++ b/flang/include/flang/Tools/PointerModels.h @@ -20,7 +20,7 @@ struct OpenMPPointerLikeModel : public mlir::omp::PointerLikeType::ExternalModel< OpenMPPointerLikeModel, T> { mlir::Type getElementType(mlir::Type pointer) const { - return pointer.cast().getElementType(); + return mlir::cast(pointer).getElementType(); } }; @@ -29,7 +29,7 @@ struct OpenACCPointerLikeModel : public mlir::acc::PointerLikeType::ExternalModel< OpenACCPointerLikeModel, T> { mlir::Type getElementType(mlir::Type pointer) const { - return pointer.cast().getElementType(); + return mlir::cast(pointer).getElementType(); } }; diff --git a/flang/lib/Lower/Allocatable.cpp b/flang/lib/Lower/Allocatable.cpp index 8e84ea2fc5d5..a1957c0eb1bb 100644 --- a/flang/lib/Lower/Allocatable.cpp +++ b/flang/lib/Lower/Allocatable.cpp @@ -162,7 +162,7 @@ static void genRuntimeInitCharacter(fir::FirOpBuilder &builder, args.push_back(builder.createConvert(loc, inputTypes[0], box.getAddr())); args.push_back(builder.createConvert(loc, inputTypes[1], len)); if (kind == 0) - kind = box.getEleTy().cast().getFKind(); + kind = mlir::cast(box.getEleTy()).getFKind(); args.push_back(builder.createIntegerConstant(loc, inputTypes[2], kind)); int rank = box.rank(); args.push_back(builder.createIntegerConstant(loc, inputTypes[3], rank)); @@ -879,7 +879,7 @@ void Fortran::lower::genDeallocateIfAllocated( builder.genIfThen(loc, isAllocated) .genThen([&]() { if (mlir::Type eleType = box.getEleTy(); - eleType.isa() && box.isPolymorphic()) { + mlir::isa(eleType) && box.isPolymorphic()) { mlir::Value declaredTypeDesc = builder.create( loc, mlir::TypeAttr::get(eleType)); genDeallocateBox(converter, box, loc, sym, declaredTypeDesc); @@ -918,7 +918,7 @@ void Fortran::lower::genDeallocateStmt( mlir::Value declaredTypeDesc = {}; if (box.isPolymorphic()) { mlir::Type eleType = box.getEleTy(); - if (eleType.isa()) + if (mlir::isa(eleType)) if (const Fortran::semantics::DerivedTypeSpec *derivedTypeSpec = symbol.GetType()->AsDerived()) { declaredTypeDesc = @@ -1007,7 +1007,7 @@ createMutableProperties(Fortran::lower::AbstractConverter &converter, fir::MutableProperties mutableProperties; std::string name = converter.mangleName(sym); mlir::Type baseAddrTy = converter.genType(sym); - if (auto boxType = baseAddrTy.dyn_cast()) + if (auto boxType = mlir::dyn_cast(baseAddrTy)) baseAddrTy = boxType.getEleTy(); // Allocate and set a variable to hold the address. // It will be set to null in setUnallocatedStatus. @@ -1032,9 +1032,9 @@ createMutableProperties(Fortran::lower::AbstractConverter &converter, mlir::Type eleTy = baseAddrTy; if (auto newTy = fir::dyn_cast_ptrEleTy(eleTy)) eleTy = newTy; - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) eleTy = seqTy.getEleTy(); - if (auto record = eleTy.dyn_cast()) + if (auto record = mlir::dyn_cast(eleTy)) if (record.getNumLenParams() != 0) TODO(loc, "deferred length type parameters."); if (fir::isa_char(eleTy) && nonDeferredParams.empty()) { diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index 92a701a7b98c..c05bf010b2bd 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -683,7 +683,7 @@ public: auto if_builder = builder->genIfThenElse(loc, isAllocated); if_builder.genThen([&]() { std::string name = mangleName(sym) + ".alloc"; - if (auto seqTy = symType.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(symType)) { fir::ExtendedValue read = fir::factory::genMutableBoxRead( *builder, loc, box, /*mayBePolymorphic=*/false); if (auto read_arr_box = read.getBoxOf()) { @@ -1132,7 +1132,7 @@ private: fir::ExtendedValue lhs = symBoxToExtendedValue(lhs_sb); fir::ExtendedValue rhs = symBoxToExtendedValue(rhs_sb); mlir::Type symType = genType(sym); - if (auto seqTy = symType.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(symType)) { Fortran::lower::StatementContext stmtCtx; Fortran::lower::createSomeArrayAssignment(*this, lhs, rhs, localSymbols, stmtCtx); @@ -1355,7 +1355,7 @@ private: return; } mlir::Type selectorType = selector.getType(); - bool realSelector = selectorType.isa(); + bool realSelector = mlir::isa(selectorType); assert((inArithmeticIfContext || !realSelector) && "invalid selector type"); mlir::Value zero; if (inArithmeticIfContext) @@ -1630,7 +1630,7 @@ private: stmtCtx); stmtCtx.finalizeAndReset(); // Raise an exception if REAL expr is a NaN. - if (expr.getType().isa()) + if (mlir::isa(expr.getType())) expr = builder->create(toLocation(), expr, expr); // An empty valueList indicates to genMultiwayBranch that the branch is // an ArithmeticIfStmt that has two branches on value 0 or 0.0. @@ -2807,7 +2807,7 @@ private: auto caseValue = valueList.begin(); auto caseBlock = blockList.begin(); for (mlir::Attribute attr : attrList) { - if (attr.isa()) { + if (mlir::isa(attr)) { genBranch(*caseBlock++); break; } @@ -2825,7 +2825,7 @@ private: rhsVal.second); }; mlir::Block *newBlock = insertBlock(*caseBlock); - if (attr.isa()) { + if (mlir::isa(attr)) { mlir::Block *newBlock2 = insertBlock(*caseBlock); mlir::Value cond = genCond(*caseValue++, mlir::arith::CmpIPredicate::sge); @@ -2838,12 +2838,12 @@ private: continue; } mlir::arith::CmpIPredicate pred; - if (attr.isa()) { + if (mlir::isa(attr)) { pred = mlir::arith::CmpIPredicate::eq; - } else if (attr.isa()) { + } else if (mlir::isa(attr)) { pred = mlir::arith::CmpIPredicate::sge; } else { - assert(attr.isa() && "unexpected predicate"); + assert(mlir::isa(attr) && "unexpected predicate"); pred = mlir::arith::CmpIPredicate::sle; } mlir::Value cond = genCond(*caseValue++, pred); @@ -3105,7 +3105,7 @@ private: bool isPointer = fir::isPointerType(baseTy); bool isAllocatable = fir::isAllocatableType(baseTy); bool isArray = - fir::dyn_cast_ptrOrBoxEleTy(baseTy).isa(); + mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(baseTy)); const fir::BoxValue *selectorBox = selector.getBoxOf(); if (std::holds_alternative(guard.u)) { // CLASS DEFAULT @@ -3114,12 +3114,12 @@ private: std::get_if(&guard.u)) { // TYPE IS fir::ExactTypeAttr attr = - typeGuardAttr.dyn_cast(); + mlir::dyn_cast(typeGuardAttr); mlir::Value exactValue; mlir::Type addrTy = attr.getType(); if (isArray) { - auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(baseTy) - .dyn_cast(); + auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(baseTy)); addrTy = fir::SequenceType::get(seqTy.getShape(), attr.getType()); } if (isPointer) @@ -3141,7 +3141,7 @@ private: addAssocEntitySymbol(selectorBox->clone(exact)); } else if (intrinsic->category() == Fortran::common::TypeCategory::Character) { - auto charTy = attr.getType().dyn_cast(); + auto charTy = mlir::dyn_cast(attr.getType()); mlir::Value charLen = fir::factory::CharacterExprHelper(*builder, loc) .readLengthFromBox(fir::getBase(selector), charTy); @@ -3158,11 +3158,12 @@ private: } else if (std::holds_alternative( guard.u)) { // CLASS IS - fir::SubclassAttr attr = typeGuardAttr.dyn_cast(); + fir::SubclassAttr attr = + mlir::dyn_cast(typeGuardAttr); mlir::Type addrTy = attr.getType(); if (isArray) { - auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(baseTy) - .dyn_cast(); + auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(baseTy)); addrTy = fir::SequenceType::get(seqTy.getShape(), attr.getType()); } if (isPointer) @@ -4157,7 +4158,7 @@ private: } else if (isDerivedCategory(lhsType->category())) { // Handle parent component. if (Fortran::lower::isParentComponent(assign.lhs)) { - if (!fir::getBase(lhs).getType().isa()) + if (!mlir::isa(fir::getBase(lhs).getType())) lhs = fir::getBase(builder->createBox(loc, lhs)); lhs = Fortran::lower::updateBoxForParentComponent(*this, lhs, assign.lhs); @@ -5508,7 +5509,7 @@ Fortran::lower::LoweringBridge::LoweringBridge( default: break; } - if (!diag.getLocation().isa()) + if (!mlir::isa(diag.getLocation())) os << diag.getLocation() << ": "; os << diag << '\n'; os.flush(); diff --git a/flang/lib/Lower/CallInterface.cpp b/flang/lib/Lower/CallInterface.cpp index 5ad244600328..c1f54ad39287 100644 --- a/flang/lib/Lower/CallInterface.cpp +++ b/flang/lib/Lower/CallInterface.cpp @@ -1182,7 +1182,7 @@ private: Property prop = Property::BaseAddress; if (isValueAttr) { bool isBuiltinCptrType = fir::isa_builtin_cptr_type(type); - if (isBindC || (!type.isa() && + if (isBindC || (!mlir::isa(type) && !obj.attrs.test(Attrs::Optional) && (dynamicType.category() != Fortran::common::TypeCategory::Derived || @@ -1190,7 +1190,7 @@ private: passBy = PassEntityBy::Value; prop = Property::Value; if (isBuiltinCptrType) { - auto recTy = type.dyn_cast(); + auto recTy = mlir::dyn_cast(type); mlir::Type fieldTy = recTy.getTypeList()[0].second; passType = fir::ReferenceType::get(fieldTy); } else { @@ -1714,7 +1714,7 @@ mlir::Type Fortran::lower::getDummyProcedureType( } bool Fortran::lower::isCPtrArgByValueType(mlir::Type ty) { - return ty.isa() && + return mlir::isa(ty) && fir::isa_integer(fir::unwrapRefType(ty)); } diff --git a/flang/lib/Lower/ConvertArrayConstructor.cpp b/flang/lib/Lower/ConvertArrayConstructor.cpp index 24aa9beba6bf..a5b5838fe6b6 100644 --- a/flang/lib/Lower/ConvertArrayConstructor.cpp +++ b/flang/lib/Lower/ConvertArrayConstructor.cpp @@ -336,7 +336,7 @@ public: if (!extent) extent = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (missingLengthParameters) { - if (declaredType.getEleTy().isa()) + if (mlir::isa(declaredType.getEleTy())) emboxLengths.push_back(builder.createIntegerConstant( loc, builder.getCharacterLengthType(), 0)); else @@ -357,7 +357,7 @@ public: bool useSimplePushRuntime(hlfir::Entity value) { return value.isScalar() && - !arrayConstructorElementType.isa() && + !mlir::isa(arrayConstructorElementType) && !fir::isRecordWithAllocatableMember(arrayConstructorElementType) && !fir::isRecordWithTypeParameters(arrayConstructorElementType); } @@ -370,7 +370,7 @@ public: auto [addrExv, cleanUp] = hlfir::convertToAddress( loc, builder, value, arrayConstructorElementType); mlir::Value addr = fir::getBase(addrExv); - if (addr.getType().isa()) + if (mlir::isa(addr.getType())) addr = builder.create(loc, addr); fir::runtime::genPushArrayConstructorSimpleScalar( loc, builder, arrayConstructorVector, addr); @@ -564,7 +564,7 @@ struct LengthAndTypeCollector> { /// lowering an ac-value and must be delayed? static bool missingLengthParameters(mlir::Type elementType, llvm::ArrayRef lengths) { - return (elementType.isa() || + return (mlir::isa(elementType) || fir::isRecordWithTypeParameters(elementType)) && lengths.empty(); } @@ -702,7 +702,8 @@ static ArrayCtorLoweringStrategy selectArrayCtorLoweringStrategy( // Based on what was gathered and the result of the analysis, select and // instantiate the right lowering strategy for the array constructor. if (!extent || needToEvaluateOneExprToGetLengthParameters || - analysis.anyArrayExpr || declaredType.getEleTy().isa()) + analysis.anyArrayExpr || + mlir::isa(declaredType.getEleTy())) return RuntimeTempStrategy( loc, builder, stmtCtx, symMap, declaredType, extent ? std::optional(extent) : std::nullopt, lengths, diff --git a/flang/lib/Lower/ConvertCall.cpp b/flang/lib/Lower/ConvertCall.cpp index c6f7d3410ad5..e4a0cc8d4730 100644 --- a/flang/lib/Lower/ConvertCall.cpp +++ b/flang/lib/Lower/ConvertCall.cpp @@ -49,15 +49,15 @@ static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, llvm::ArrayRef extents, llvm::ArrayRef lengths) { mlir::Type type = base.getType(); - if (type.isa()) + if (mlir::isa(type)) return fir::BoxValue(base, /*lbounds=*/{}, lengths, extents); type = fir::unwrapRefType(type); - if (type.isa()) + if (mlir::isa(type)) return fir::MutableBoxValue(base, lengths, /*mutableProperties*/ {}); - if (auto seqTy = type.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(type)) { if (seqTy.getDimension() != extents.size()) fir::emitFatalError(loc, "incorrect number of extents for array"); - if (seqTy.getEleTy().isa()) { + if (mlir::isa(seqTy.getEleTy())) { if (lengths.empty()) fir::emitFatalError(loc, "missing length for character"); assert(lengths.size() == 1); @@ -65,7 +65,7 @@ static fir::ExtendedValue toExtendedValue(mlir::Location loc, mlir::Value base, } return fir::ArrayBoxValue(base, extents); } - if (type.isa()) { + if (mlir::isa(type)) { if (lengths.empty()) fir::emitFatalError(loc, "missing length for character"); assert(lengths.size() == 1); @@ -193,7 +193,7 @@ static mlir::Value remapActualToDummyDescriptor( llvm::SmallVector lengths; mlir::Type dummyBoxType = caller.getDummyArgumentType(arg); mlir::Type dummyBaseType = fir::unwrapPassByRefType(dummyBoxType); - if (dummyBaseType.isa()) + if (mlir::isa(dummyBaseType)) caller.walkDummyArgumentExtents( arg, [&](const Fortran::lower::SomeExpr &e, bool isAssumedSizeExtent) { extents.emplace_back(lowerSpecExpr(e, isAssumedSizeExtent)); @@ -338,7 +338,7 @@ std::pair Fortran::lower::genCallOpAndResult( if (!caller.callerAllocateResult()) return {}; mlir::Type type = caller.getResultStorageType(); - if (type.isa()) + if (mlir::isa(type)) caller.walkResultExtents( [&](const Fortran::lower::SomeExpr &e, bool isAssumedSizeExtent) { assert(!isAssumedSizeExtent && "result cannot be assumed-size"); @@ -353,7 +353,7 @@ std::pair Fortran::lower::genCallOpAndResult( // Result length parameters should not be provided to box storage // allocation and save_results, but they are still useful information to // keep in the ExtendedValue if non-deferred. - if (!type.isa()) { + if (!mlir::isa(type)) { if (fir::isa_char(fir::unwrapSequenceType(type)) && lengths.empty()) { // Calling an assumed length function. This is only possible if this // is a call to a character dummy procedure. @@ -478,7 +478,7 @@ std::pair Fortran::lower::genCallOpAndResult( // FIR. if (funcPointer) { operands.push_back( - funcPointer.getType().isa() + mlir::isa(funcPointer.getType()) ? builder.create(loc, funcType, funcPointer) : builder.createConvert(loc, funcType, funcPointer)); } @@ -492,8 +492,8 @@ std::pair Fortran::lower::genCallOpAndResult( // arguments of any type and vice versa. mlir::Value cast; auto *context = builder.getContext(); - if (snd.isa() && - fst.getType().isa()) { + if (mlir::isa(snd) && + mlir::isa(fst.getType())) { auto funcTy = mlir::FunctionType::get(context, std::nullopt, std::nullopt); auto boxProcTy = builder.getBoxProcType(funcTy); @@ -734,9 +734,9 @@ std::pair Fortran::lower::genCallOpAndResult( // Call a BIND(C) function that return a char. if (caller.characterize().IsBindC() && - funcType.getResults()[0].isa()) { + mlir::isa(funcType.getResults()[0])) { fir::CharacterType charTy = - funcType.getResults()[0].dyn_cast(); + mlir::dyn_cast(funcType.getResults()[0]); mlir::Value len = builder.createIntegerConstant( loc, builder.getCharacterLengthType(), charTy.getLen()); return {fir::CharBoxValue{callResult, len}, /*resultIsFinalized=*/false}; @@ -890,7 +890,7 @@ extendedValueToHlfirEntity(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type firBaseTy = firBase.getType(); if (fir::isa_trivial(firBaseTy)) return hlfir::EntityWithAttributes{firBase}; - if (auto charTy = firBase.getType().dyn_cast()) { + if (auto charTy = mlir::dyn_cast(firBase.getType())) { // CHAR() intrinsic and BIND(C) procedures returning CHARACTER(1) // are lowered to a fir.char that is not in memory. // This tends to cause a lot of bugs because the rest of the @@ -1061,7 +1061,7 @@ static hlfir::Entity fixProcedureDummyMismatch(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity actual, mlir::Type dummyType) { - if (actual.getType().isa() && + if (mlir::isa(actual.getType()) && fir::isCharacterProcedureTuple(dummyType)) { mlir::Value length = builder.create(loc, builder.getCharacterLengthType()); @@ -1070,7 +1070,7 @@ static hlfir::Entity fixProcedureDummyMismatch(mlir::Location loc, return hlfir::Entity{tuple}; } assert(fir::isCharacterProcedureTuple(actual.getType()) && - dummyType.isa() && + mlir::isa(dummyType) && "unsupported dummy procedure mismatch with the actual argument"); mlir::Value boxProc = fir::factory::extractCharacterProcedureTuple( builder, loc, actual, /*openBoxProc=*/false) @@ -1143,7 +1143,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( assert(actual.isProcedure()); // Do nothing if this is a procedure argument. It is already a // fir.boxproc/fir.tuple as it should. - if (!actual.getType().isa() && + if (!mlir::isa(actual.getType()) && actual.getType() != dummyType) // The actual argument may be a procedure that returns character (a // fir.tuple) while the dummy is not. Extract the tuple @@ -1164,7 +1164,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( // dynamic type matters to determine the contiguity. const bool mustSetDynamicTypeToDummyType = passingPolymorphicToNonPolymorphic && - (actual.isArray() || dummyType.isa()); + (actual.isArray() || mlir::isa(dummyType)); // The simple contiguity of the actual is "lost" when passing a polymorphic // to a non polymorphic entity because the dummy dynamic type matters for @@ -1236,7 +1236,7 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( preparedDummy.pushExprAssociateCleanUp(associate); } else if (mustDoCopyInOut) { // Copy-in non contiguous variables. - assert(entity.getType().isa() && + assert(mlir::isa(entity.getType()) && "expect non simply contiguous variables to be boxes"); if (actualIsAssumedRank) TODO(loc, "copy-in and copy-out of assumed-rank arguments"); @@ -1294,13 +1294,14 @@ static PreparedDummyArgument preparePresentUserCallActualArgument( // Step 3: now that the dummy argument storage has been prepared, package // it according to the interface. mlir::Value addr; - if (dummyTypeWithActualRank.isa()) { + if (mlir::isa(dummyTypeWithActualRank)) { addr = hlfir::genVariableBoxChar(loc, builder, entity); - } else if (dummyTypeWithActualRank.isa()) { + } else if (mlir::isa(dummyTypeWithActualRank)) { entity = hlfir::genVariableBox(loc, builder, entity); // Ensures the box has the right attributes and that it holds an // addendum if needed. - fir::BaseBoxType actualBoxType = entity.getType().cast(); + fir::BaseBoxType actualBoxType = + mlir::cast(entity.getType()); mlir::Type boxEleType = actualBoxType.getEleTy(); // For now, assume it is not OK to pass the allocatable/pointer // descriptor to a non pointer/allocatable dummy. That is a strict @@ -1567,7 +1568,7 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, // callee side, and it is illegal to use NULL without a MOLD if any // dummy length parameters are assumed. mlir::Type boxTy = fir::dyn_cast_ptrEleTy(argTy); - assert(boxTy && boxTy.isa() && + assert(boxTy && mlir::isa(boxTy) && "must be a fir.box type"); mlir::Value boxStorage = fir::factory::genNullBoxStorage(builder, loc, boxTy); @@ -1635,7 +1636,8 @@ genUserCall(Fortran::lower::PreparedActualArguments &loweredActuals, caller, callSiteType, callContext.resultType, callContext.isElementalProcWithArrayArgs()); // For procedure pointer function result, just return the call. - if (callContext.resultType && callContext.resultType->isa()) + if (callContext.resultType && + mlir::isa(*callContext.resultType)) return hlfir::EntityWithAttributes(fir::getBase(result)); /// Clean-up associations and copy-in. @@ -2115,9 +2117,9 @@ public: hlfir::getFortranElementType(*callContext.resultType); // Get result length parameters. llvm::SmallVector typeParams; - if (elementType.isa() || + if (mlir::isa(elementType) || fir::isRecordWithTypeParameters(elementType)) { - auto charType = elementType.dyn_cast(); + auto charType = mlir::dyn_cast(elementType); if (charType && charType.hasConstantLen()) typeParams.push_back(builder.createIntegerConstant( loc, builder.getIndexType(), charType.getLen())); @@ -2523,7 +2525,7 @@ genIntrinsicRef(const Fortran::evaluate::SpecificIntrinsic *intrinsic, } std::optional result = genHLFIRIntrinsicRefCore( loweredActuals, intrinsic, argLowering, callContext); - if (result && result->getType().isa()) { + if (result && mlir::isa(result->getType())) { fir::FirOpBuilder *bldr = &callContext.getBuilder(); callContext.stmtCtx.attachCleanup( [=]() { bldr->create(loc, *result); }); diff --git a/flang/lib/Lower/ConvertConstant.cpp b/flang/lib/Lower/ConvertConstant.cpp index ed389bbe4ae5..653e874a969c 100644 --- a/flang/lib/Lower/ConvertConstant.cpp +++ b/flang/lib/Lower/ConvertConstant.cpp @@ -184,8 +184,8 @@ private: if (!attributeElementType || attributes.empty()) return {}; - assert(symTy.isa() && "expecting an array global"); - auto arrTy = symTy.cast(); + assert(mlir::isa(symTy) && "expecting an array global"); + auto arrTy = mlir::cast(symTy); llvm::SmallVector tensorShape(arrTy.getShape()); std::reverse(tensorShape.begin(), tensorShape.end()); auto tensorTy = @@ -423,14 +423,14 @@ static mlir::Value genStructureComponentInit( // address field, which ought to be an intptr_t on the target. mlir::Value addr = fir::getBase( Fortran::lower::genExtAddrInInitializer(converter, loc, expr)); - if (addr.getType().isa()) + if (mlir::isa(addr.getType())) addr = builder.create(loc, addr); assert((fir::isa_ref_type(addr.getType()) || - addr.getType().isa()) && + mlir::isa(addr.getType())) && "expect reference type for address field"); assert(fir::isa_derived(componentTy) && "expect C_PTR, C_FUNPTR to be a record"); - auto cPtrRecTy = componentTy.cast(); + auto cPtrRecTy = mlir::cast(componentTy); llvm::StringRef addrFieldName = Fortran::lower::builtin::cptrFieldName; mlir::Type addrFieldTy = cPtrRecTy.getType(addrFieldName); auto addrField = builder.create( @@ -460,7 +460,7 @@ static mlir::Value genInlinedStructureCtorLitImpl( Fortran::lower::AbstractConverter &converter, mlir::Location loc, const Fortran::evaluate::StructureConstructor &ctor, mlir::Type type) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - auto recTy = type.cast(); + auto recTy = mlir::cast(type); if (!converter.getLoweringOptions().getLowerToHighLevelFIR()) { mlir::Value res = builder.create(loc, recTy); @@ -587,7 +587,7 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, } while (con.IncrementSubscripts(subscripts)); } else if constexpr (T::category == Fortran::common::TypeCategory::Derived) { do { - mlir::Type eleTy = arrayTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); mlir::Value elementVal = genScalarLit(converter, loc, con.At(subscripts), eleTy, /*outlineInReadOnlyMemory=*/false); @@ -597,7 +597,7 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, } else { llvm::SmallVector rangeStartIdx; uint64_t rangeSize = 0; - mlir::Type eleTy = arrayTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); do { auto getElementVal = [&]() { return builder.createConvert(loc, eleTy, @@ -620,12 +620,11 @@ genInlinedArrayLit(Fortran::lower::AbstractConverter &converter, llvm::SmallVector rangeBounds; llvm::SmallVector idx = createIdx(); for (size_t i = 0; i < idx.size(); ++i) { - rangeBounds.push_back(rangeStartIdx[i] - .cast() + rangeBounds.push_back(mlir::cast(rangeStartIdx[i]) .getValue() .getSExtValue()); rangeBounds.push_back( - idx[i].cast().getValue().getSExtValue()); + mlir::cast(idx[i]).getValue().getSExtValue()); } array = builder.create( loc, arrayTy, array, getElementVal(), @@ -647,7 +646,7 @@ genOutlineArrayLit(Fortran::lower::AbstractConverter &converter, mlir::Location loc, mlir::Type arrayTy, const Fortran::evaluate::Constant &constant) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - mlir::Type eleTy = arrayTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrayTy).getEleTy(); llvm::StringRef globalName = converter.getUniqueLitName( loc, std::make_unique(toEvExpr(constant)), eleTy); diff --git a/flang/lib/Lower/ConvertExpr.cpp b/flang/lib/Lower/ConvertExpr.cpp index fb7807718ff8..9567685aa3d2 100644 --- a/flang/lib/Lower/ConvertExpr.cpp +++ b/flang/lib/Lower/ConvertExpr.cpp @@ -267,7 +267,7 @@ arrayLoadExtValue(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type ty = fir::applyPathToType(arrTy, path); if (!ty) fir::emitFatalError(loc, "path does not apply to type"); - if (!ty.isa()) { + if (!mlir::isa(ty)) { if (fir::isa_char(ty)) { mlir::Value len = newLen; if (!len) @@ -282,7 +282,7 @@ arrayLoadExtValue(fir::FirOpBuilder &builder, mlir::Location loc, } return newBase; } - arrTy = ty.cast(); + arrTy = mlir::cast(ty); } auto arrayToExtendedValue = @@ -412,15 +412,15 @@ static fir::ExtendedValue genLoad(fir::FirOpBuilder &builder, return addr.match( [](const fir::CharBoxValue &box) -> fir::ExtendedValue { return box; }, [&](const fir::PolymorphicValue &p) -> fir::ExtendedValue { - if (fir::unwrapRefType(fir::getBase(p).getType()) - .isa()) + if (mlir::isa( + fir::unwrapRefType(fir::getBase(p).getType()))) return p; mlir::Value load = builder.create(loc, fir::getBase(p)); return fir::PolymorphicValue(load, p.getSourceBox()); }, [&](const fir::UnboxedValue &v) -> fir::ExtendedValue { - if (fir::unwrapRefType(fir::getBase(v).getType()) - .isa()) + if (mlir::isa( + fir::unwrapRefType(fir::getBase(v).getType()))) return v; return builder.create(loc, fir::getBase(v)); }, @@ -536,8 +536,8 @@ static mlir::Value createBoxProcCharTuple(Fortran::lower::AbstractConverter &converter, mlir::Type argTy, mlir::Value funcAddr, mlir::Value charLen) { - auto boxTy = - argTy.cast().getType(0).cast(); + auto boxTy = mlir::cast( + mlir::cast(argTy).getType(0)); mlir::Location loc = converter.getCurrentLocation(); auto &builder = converter.getFirOpBuilder(); @@ -549,7 +549,7 @@ createBoxProcCharTuple(Fortran::lower::AbstractConverter &converter, mlir::Type toTy = boxTy.getEleTy(); if (fir::isa_ref_type(fromTy)) funcAddr = builder.createConvert(loc, toTy, funcAddr); - else if (fromTy.isa()) + else if (mlir::isa(fromTy)) funcAddr = builder.create(loc, toTy, funcAddr); auto boxProc = [&]() -> mlir::Value { @@ -575,7 +575,7 @@ absentBoxToUnallocatedBox(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value isPresent) { mlir::Value box = fir::getBase(exv); mlir::Type boxType = box.getType(); - assert(boxType.isa() && "argument must be a fir.box"); + assert(mlir::isa(boxType) && "argument must be a fir.box"); mlir::Value emptyBox = fir::factory::createUnallocatedBox(builder, loc, boxType, std::nullopt); auto safeToReadBox = @@ -915,7 +915,7 @@ public: if (inInitializer) return Fortran::lower::genInlinedStructureCtorLit(converter, loc, ctor); mlir::Type ty = translateSomeExprToFIRType(converter, toEvExpr(ctor)); - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); auto fieldTy = fir::FieldType::get(ty.getContext()); mlir::Value res = builder.createTemporary(loc, recTy); mlir::Value box = builder.createBox(loc, fir::ExtendedValue{res}); @@ -1172,8 +1172,8 @@ public: if (!charBox) fir::emitFatalError(loc, "expected scalar character"); mlir::Value charAddr = charBox->getAddr(); - auto charType = - fir::unwrapPassByRefType(charAddr.getType()).cast(); + auto charType = mlir::cast( + fir::unwrapPassByRefType(charAddr.getType())); if (charType.hasConstantLen()) { // Erase previous constant length from the base type. fir::CharacterType::LenType newLen = fir::CharacterType::unknownLen(); @@ -1441,7 +1441,7 @@ public: auto fldTy = fir::FieldType::get(&converter.getMLIRContext()); // FIXME: need to thread the LEN type parameters here. for (const Fortran::evaluate::Component *field : list) { - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); const Fortran::semantics::Symbol &sym = getLastSym(*field); std::string name = converter.getRecordTypeFieldName(sym); coorArgs.push_back(builder.create( @@ -1478,7 +1478,7 @@ public: mlir::Type genSubType(mlir::Type arrTy, unsigned dims) { mlir::Type unwrapTy = fir::dyn_cast_ptrOrBoxEleTy(arrTy); assert(unwrapTy && "must be a pointer or box type"); - auto seqTy = unwrapTy.cast(); + auto seqTy = mlir::cast(unwrapTy); llvm::ArrayRef shape = seqTy.getShape(); assert(shape.size() > 0 && "removing columns for sequence sans shape"); assert(dims <= shape.size() && "removing more columns than exist"); @@ -1550,9 +1550,9 @@ public: } mlir::Type eleTy = fir::dyn_cast_ptrOrBoxEleTy(base.getType()); - if (auto classTy = eleTy.dyn_cast()) + if (auto classTy = mlir::dyn_cast(eleTy)) eleTy = classTy.getEleTy(); - auto seqTy = eleTy.cast(); + auto seqTy = mlir::cast(eleTy); assert(args.size() == seqTy.getDimension()); mlir::Type ty = builder.getRefType(seqTy.getEleTy()); auto addr = builder.create(loc, ty, base, args); @@ -1571,7 +1571,7 @@ public: mlir::Location loc = getLoc(); mlir::Value addr = fir::getBase(array); mlir::Type arrTy = fir::dyn_cast_ptrEleTy(addr.getType()); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); mlir::Type seqTy = builder.getRefType(builder.getVarLenSeqTy(eleTy)); mlir::Type refTy = builder.getRefType(eleTy); mlir::Value base = builder.createConvert(loc, seqTy, addr); @@ -1656,7 +1656,7 @@ public: mlir::Location loc = getLoc(); mlir::Value addr = fir::getBase(exv); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(addr.getType()); - mlir::Type eleTy = arrTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(arrTy).getEleTy(); mlir::Type refTy = builder.getRefType(eleTy); mlir::IndexType idxTy = builder.getIndexType(); llvm::SmallVector arrayCoorArgs; @@ -1766,8 +1766,9 @@ public: mlir::Location loc = getLoc(); ExtValue exv = genBoxArg(expr); auto exvTy = fir::getBase(exv).getType(); - if (exvTy.isa()) { - auto boxProcTy = builder.getBoxProcType(exvTy.cast()); + if (mlir::isa(exvTy)) { + auto boxProcTy = + builder.getBoxProcType(mlir::cast(exvTy)); return builder.create(loc, boxProcTy, fir::getBase(exv)); } @@ -1861,7 +1862,7 @@ public: // IS_CONTIGUOUS may require an assumed size TYPE(*) to be passed to // the intrinsic library utility as a fir.box. if (argRules.lowerAs == fir::LowerIntrinsicArgAs::Box && - !fir::getBase(exv).getType().isa()) { + !mlir::isa(fir::getBase(exv).getType())) { operands.emplace_back( fir::factory::createBoxValue(builder, loc, exv)); continue; @@ -2005,7 +2006,7 @@ public: fir::getTypeParams(mold); mlir::Value charLen; mlir::Type elementType = fir::unwrapSequenceType(type); - if (auto charType = elementType.dyn_cast()) { + if (auto charType = mlir::dyn_cast(elementType)) { charLen = allocMemTypeParams.empty() ? fir::factory::readCharLen(builder, loc, mold) : allocMemTypeParams[0]; @@ -2017,7 +2018,7 @@ public: mlir::Value temp = builder.create( loc, type, tempName, allocMemTypeParams, extents); - if (fir::unwrapSequenceType(type).isa()) + if (mlir::isa(fir::unwrapSequenceType(type))) return fir::CharArrayBoxValue{temp, charLen, extents}; return fir::ArrayBoxValue{temp, extents}; } @@ -2166,7 +2167,7 @@ public: // We have to initialize the temp if it may have components // that need initialization. If there are no components // requiring initialization, then the call is a no-op. - if (getElementTypeOf(temp).isa()) { + if (mlir::isa(getElementTypeOf(temp))) { mlir::Value tempBox = fir::getBase(builder.createBox(loc, temp)); fir::runtime::genDerivedTypeInitialize(builder, loc, tempBox); } @@ -2312,7 +2313,7 @@ public: if (!copyOutPair.restrictCopyAndFreeAtRuntime) { doCopyOut(); - if (fir::getElementTypeOf(copyOutPair.temp).isa()) { + if (mlir::isa(fir::getElementTypeOf(copyOutPair.temp))) { // Destroy components of the temporary (if any). // If there are no components requiring destruction, then the call // is a no-op. @@ -2330,7 +2331,8 @@ public: builder.genIfThen(loc, *copyOutPair.restrictCopyAndFreeAtRuntime) .genThen([&]() { doCopyOut(); - if (fir::getElementTypeOf(copyOutPair.temp).isa()) { + if (mlir::isa( + fir::getElementTypeOf(copyOutPair.temp))) { // Destroy components of the temporary (if any). // If there are no components requiring destruction, then the call // is a no-op. @@ -2381,7 +2383,7 @@ public: mlir::Value actualArgBase = fir::getBase(actualArg); mlir::Value isPresent = builder.create( loc, builder.getI1Type(), actualArgBase); - if (!actualArgBase.getType().isa()) + if (!mlir::isa(actualArgBase.getType())) return {actualArg, isPresent}; ExtValue safeToReadBox = absentBoxToUnallocatedBox(builder, loc, actualArg, isPresent); @@ -2408,7 +2410,7 @@ public: fir::getAdaptToByRefAttr(builder)}); return fir::CharBoxValue{temp, len}; } - assert((fir::isa_trivial(type) || type.isa()) && + assert((fir::isa_trivial(type) || mlir::isa(type)) && "must be simple scalar"); return builder.createTemporary(loc, type, llvm::ArrayRef{ @@ -2585,7 +2587,7 @@ public: // callee side, and it is illegal to use NULL without a MOLD if any // dummy length parameters are assumed. mlir::Type boxTy = fir::dyn_cast_ptrEleTy(argTy); - assert(boxTy && boxTy.isa() && + assert(boxTy && mlir::isa(boxTy) && "must be a fir.box type"); mlir::Value boxStorage = builder.createTemporary(loc, boxTy); mlir::Value nullBox = fir::factory::createUnallocatedBox( @@ -2643,10 +2645,11 @@ public: // If a character procedure was passed instead, handle the // mismatch. auto funcTy = - x.getAddr().getType().dyn_cast(); + mlir::dyn_cast(x.getAddr().getType()); if (funcTy && funcTy.getNumResults() == 1 && - funcTy.getResult(0).isa()) { - auto boxTy = funcTy.getResult(0).cast(); + mlir::isa(funcTy.getResult(0))) { + auto boxTy = + mlir::cast(funcTy.getResult(0)); mlir::Value ref = builder.createConvert( loc, builder.getRefType(boxTy.getEleTy()), x.getAddr()); auto len = builder.create( @@ -2667,7 +2670,7 @@ public: // free-casting the base address to be a !fir.char reference and // setting the LEN argument to undefined. What could go wrong? auto dataPtr = fir::getBase(x); - assert(!dataPtr.getType().template isa()); + assert(!mlir::isa(dataPtr.getType())); return builder.convertWithSemantics( loc, argTy, dataPtr, /*allowCharacterConversion=*/true); @@ -2742,7 +2745,7 @@ public: loc, fir::ClassType::get(mlir::NoneType::get(builder.getContext())), box); - } else if (box.getType().isa() && + } else if (mlir::isa(box.getType()) && fir::isPolymorphicType(argTy)) { box = builder.create(loc, argTy, box, mlir::Value{}, /*slice=*/mlir::Value{}); @@ -2791,7 +2794,7 @@ public: : builder.createBox(getLoc(), genTempExtAddr(*expr), fir::isPolymorphicType(argTy), fir::isAssumedType(argTy)); - if (box.getType().isa() && + if (mlir::isa(box.getType()) && fir::isPolymorphicType(argTy) && !fir::isAssumedType(argTy)) { mlir::Type actualTy = argTy; if (Fortran::lower::isParentComponent(*expr)) @@ -3030,10 +3033,11 @@ private: Fortran::common::ScopedSet(semant, PushVal); static bool isAdjustedArrayElementType(mlir::Type t) { - return fir::isa_char(t) || fir::isa_derived(t) || t.isa(); + return fir::isa_char(t) || fir::isa_derived(t) || + mlir::isa(t); } static bool elementTypeWasAdjusted(mlir::Type t) { - if (auto ty = t.dyn_cast()) + if (auto ty = mlir::dyn_cast(t)) return isAdjustedArrayElementType(ty.getEleTy()); return false; } @@ -3050,15 +3054,15 @@ static void genScalarUserDefinedAssignmentCall(fir::FirOpBuilder &builder, auto prepareUserDefinedArg = [](fir::FirOpBuilder &builder, mlir::Location loc, const fir::ExtendedValue &value, mlir::Type argType) -> mlir::Value { - if (argType.isa()) { + if (mlir::isa(argType)) { const fir::CharBoxValue *charBox = value.getCharBox(); assert(charBox && "argument type mismatch in elemental user assignment"); return fir::factory::CharacterExprHelper{builder, loc}.createEmbox( *charBox); } - if (argType.isa()) { + if (mlir::isa(argType)) { mlir::Value box = - builder.createBox(loc, value, argType.isa()); + builder.createBox(loc, value, mlir::isa(argType)); return builder.createConvert(loc, argType, box); } // Simple pass by address. @@ -3170,7 +3174,7 @@ convertToArrayBoxValue(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value val, mlir::Value len) { mlir::Type ty = fir::unwrapRefType(val.getType()); mlir::IndexType idxTy = builder.getIndexType(); - auto seqTy = ty.cast(); + auto seqTy = mlir::cast(ty); auto undef = builder.create(loc, idxTy); llvm::SmallVector extents(seqTy.getDimension(), undef); if (fir::isa_char(seqTy.getEleTy())) @@ -3462,7 +3466,7 @@ public: [&](const auto &e) { auto f = genarr(e); ExtValue exv = f(IterationSpace{}); - if (fir::getBase(exv).getType().template isa()) + if (mlir::isa(fir::getBase(exv).getType())) return exv; fir::emitFatalError(getLoc(), "array must be emboxed"); }, @@ -3487,10 +3491,9 @@ public: tempRes, dest.getSlice(), dest.getTypeparams()); - auto arrTy = - fir::dyn_cast_ptrEleTy(tempRes.getType()).cast(); - if (auto charTy = - arrTy.getEleTy().template dyn_cast()) { + auto arrTy = mlir::cast( + fir::dyn_cast_ptrEleTy(tempRes.getType())); + if (auto charTy = mlir::dyn_cast(arrTy.getEleTy())) { if (fir::characterWithDynamicLen(charTy)) TODO(loc, "CHARACTER does not have constant LEN"); mlir::Value len = builder.createIntegerConstant( @@ -3912,17 +3915,18 @@ private: mlir::Value convertElementForUpdate(mlir::Location loc, mlir::Type eleTy, mlir::Value origVal) { if (auto origEleTy = fir::dyn_cast_ptrEleTy(origVal.getType())) - if (origEleTy.isa()) { + if (mlir::isa(origEleTy)) { // If origVal is a box variable, load it so it is in the value domain. origVal = builder.create(loc, origVal); } - if (origVal.getType().isa() && !eleTy.isa()) { + if (mlir::isa(origVal.getType()) && + !mlir::isa(eleTy)) { if (isPointerAssignment()) TODO(loc, "lhs of pointer assignment returned unexpected value"); TODO(loc, "invalid box conversion in elemental computation"); } - if (isPointerAssignment() && eleTy.isa() && - !origVal.getType().isa()) { + if (isPointerAssignment() && mlir::isa(eleTy) && + !mlir::isa(origVal.getType())) { // This is a pointer assignment and the rhs is a raw reference to a TARGET // in memory. Embox the reference so it can be stored to the boxed // POINTER variable. @@ -3930,7 +3934,7 @@ private: if (auto eleTy = fir::dyn_cast_ptrEleTy(origVal.getType()); fir::hasDynamicSize(eleTy)) TODO(loc, "TARGET of pointer assignment with runtime size/shape"); - auto memrefTy = fir::boxMemRefType(eleTy.cast()); + auto memrefTy = fir::boxMemRefType(mlir::cast(eleTy)); auto castTo = builder.createConvert(loc, memrefTy, origVal); origVal = builder.create(loc, eleTy, castTo); } @@ -3982,7 +3986,7 @@ private: auto arrayOp = builder.create( loc, resRefTy, innerArg, iterSpace.iterVec(), fir::factory::getTypeParams(loc, builder, destination)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { llvm::SmallVector substringBounds; populateBounds(substringBounds, substring); mlir::Value dstLen = fir::factory::genLenOfCharacter( @@ -3996,7 +4000,7 @@ private: loc, destination, builder, arrayOp, exv, eleTy, innerArg); return abstractArrayExtValue(amend /*FIXME: typeparams?*/); } - assert(eleTy.isa() && "must be an array"); + assert(mlir::isa(eleTy) && "must be an array"); TODO(loc, "array (as element) assignment"); } // By value semantics. The element is being assigned by value. @@ -4060,7 +4064,7 @@ private: llvm::SmallVector getShape(ArrayOperand array) { if (array.slice) return computeSliceShape(array.slice); - if (array.memref.getType().isa()) + if (mlir::isa(array.memref.getType())) return fir::factory::readExtents(builder, getLoc(), fir::BoxValue{array.memref}); return fir::factory::getExtents(array.shape); @@ -4133,7 +4137,7 @@ private: mlir::Location loc = getLoc(); return [=, builder = &converter.getFirOpBuilder()](IterSpace iters) { mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(tmp.getType()); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); mlir::Type eleRefTy = builder->getRefType(eleTy); mlir::IntegerType i1Ty = builder->getI1Type(); // Adjust indices for any shift of the origin of the array. @@ -4442,15 +4446,15 @@ private: TODO(loc, "polymorphic array temporary"); if (ccLoadDest) return (*ccLoadDest)(shape); - auto seqTy = type.dyn_cast(); + auto seqTy = mlir::dyn_cast(type); assert(seqTy && "must be an array"); // TODO: Need to thread the LEN parameters here. For character, they may // differ from the operands length (e.g concatenation). So the array loads // type parameters are not enough. - if (auto charTy = seqTy.getEleTy().dyn_cast()) + if (auto charTy = mlir::dyn_cast(seqTy.getEleTy())) if (charTy.hasDynamicLen()) TODO(loc, "character array expression temp with dynamic length"); - if (auto recTy = seqTy.getEleTy().dyn_cast()) + if (auto recTy = mlir::dyn_cast(seqTy.getEleTy())) if (recTy.getNumLenParams() > 0) TODO(loc, "derived type array expression temp with LEN parameters"); if (mlir::Type eleTy = fir::unwrapSequenceType(type); @@ -4827,7 +4831,7 @@ private: }); } else { ExtValue exv = asScalarRef(*expr); - if (fir::getBase(exv).getType().isa()) { + if (mlir::isa(fir::getBase(exv).getType())) { operands.emplace_back( [=](IterSpace iters) -> ExtValue { return exv; }); } else { @@ -5565,7 +5569,7 @@ private: } static mlir::Type unwrapBoxEleTy(mlir::Type ty) { - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return fir::unwrapRefType(boxTy.getEleTy()); return ty; } @@ -5575,7 +5579,7 @@ private: ty = unwrapBoxEleTy(ty); mlir::Location loc = getLoc(); mlir::IndexType idxTy = builder.getIndexType(); - for (auto extent : ty.cast().getShape()) { + for (auto extent : mlir::cast(ty).getShape()) { auto v = extent == fir::SequenceType::getUnknownExtent() ? builder.create(loc, idxTy).getResult() : builder.createIntegerConstant(loc, idxTy, extent); @@ -5638,7 +5642,8 @@ private: mlir::Location loc = getLoc(); mlir::Value memref = fir::getBase(extMemref); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(memref.getType()); - assert(arrTy.isa() && "memory ref must be an array"); + assert(mlir::isa(arrTy) && + "memory ref must be an array"); mlir::Value shape = builder.createShape(loc, extMemref); mlir::Value slice; if (components.isSlice()) { @@ -5688,12 +5693,12 @@ private: components.suffixComponents); } if (components.hasComponents()) { - auto seqTy = arrTy.cast(); + auto seqTy = mlir::cast(arrTy); mlir::Type eleTy = fir::applyPathToType(seqTy.getEleTy(), components.suffixComponents); if (!eleTy) fir::emitFatalError(loc, "slicing path is ill-formed"); - if (auto realTy = eleTy.dyn_cast()) + if (auto realTy = mlir::dyn_cast(eleTy)) eleTy = Fortran::lower::convertReal(realTy.getContext(), realTy.getFKind()); @@ -5713,13 +5718,14 @@ private: // value. The value of the box is forwarded in the continuation. mlir::Type reduceTy = reduceRank(arrTy, slice); mlir::Type boxTy = fir::BoxType::get(reduceTy); - if (memref.getType().isa() && !components.hasComponents()) + if (mlir::isa(memref.getType()) && + !components.hasComponents()) boxTy = fir::ClassType::get(reduceTy); if (components.substring) { // Adjust char length to substring size. fir::CharacterType charTy = fir::factory::CharacterExprHelper::getCharType(reduceTy); - auto seqTy = reduceTy.cast(); + auto seqTy = mlir::cast(reduceTy); // TODO: Use a constant for fir.char LEN if we can compute it. boxTy = fir::BoxType::get( fir::SequenceType::get(fir::CharacterType::getUnknownLen( @@ -5734,7 +5740,7 @@ private: nonDeferredLenParams = fir::factory::getNonDeferredLenParams(extMemref); } mlir::Value embox = - memref.getType().isa() + mlir::isa(memref.getType()) ? builder.create(loc, boxTy, memref, shape, slice) .getResult() : builder @@ -5745,7 +5751,7 @@ private: return fir::BoxValue(embox, lbounds, nonDeferredLenParams); }; } - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); if (isReferentiallyOpaque()) { // Semantics are an opaque reference to an array. // This case forwards a continuation that will generate the address @@ -5760,12 +5766,12 @@ private: mlir::Value coor = builder.create( loc, refEleTy, memref, shape, slice, indices, fir::getTypeParams(extMemref)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { llvm::SmallVector substringBounds; populateBounds(substringBounds, components.substring); if (!substringBounds.empty()) { mlir::Value dstLen = fir::factory::genLenOfCharacter( - builder, loc, arrTy.cast(), memref, + builder, loc, mlir::cast(arrTy), memref, fir::getTypeParams(extMemref), iters.iterVec(), substringBounds); fir::CharBoxValue dstChar(coor, dstLen); @@ -5863,7 +5869,7 @@ private: mlir::Type eleRefTy = builder.getRefType(eleTy); mlir::Value arrayOp = builder.create( loc, eleRefTy, arrLd, iters.iterVec(), arrLdTypeParams); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { llvm::SmallVector substringBounds; populateBounds(substringBounds, components.substring); if (!substringBounds.empty()) { @@ -5896,7 +5902,7 @@ private: const bool hasOptionalAttr = fir::valueHasFirAttribute(base, fir::getOptionalAttrName()); mlir::Type baseType = fir::unwrapRefType(base.getType()); - const bool isBox = baseType.isa(); + const bool isBox = mlir::isa(baseType); const bool isAllocOrPtr = Fortran::evaluate::IsAllocatableOrPointerObject(expr); mlir::Type arrType = fir::unwrapPassByRefType(baseType); @@ -5989,7 +5995,7 @@ private: if (slice) { auto slOp = mlir::dyn_cast(slice.getDefiningOp()); assert(slOp && "expected slice op"); - auto seqTy = arrTy.dyn_cast(); + auto seqTy = mlir::dyn_cast(arrTy); assert(seqTy && "expected array type"); mlir::Operation::operand_range triples = slOp.getTriples(); fir::SequenceType::Shape shape; @@ -6053,7 +6059,7 @@ private: mlir::IndexType idxTy = builder.getIndexType(); mlir::Value multiplier = builder.createIntegerConstant(loc, idxTy, 1); if (fir::hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { // Array of char with dynamic LEN parameter. Downcast to an array // of singleton char, and scale by the len type parameter from // `exv`. @@ -6074,7 +6080,7 @@ private: }); fir::CharacterType newEleTy = fir::CharacterType::getSingleton( eleTy.getContext(), charTy.getFKind()); - if (auto seqTy = resTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(resTy)) { assert(eleTy == seqTy.getEleTy()); resTy = fir::SequenceType::get(seqTy.getShape(), newEleTy); } @@ -6161,7 +6167,7 @@ private: if (!eleSz) { // Compute the element size at runtime. assert(fir::hasDynamicSize(eleTy)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { auto charBytes = builder.getKindMap().getCharacterBitsize(charTy.getFKind()) / 8; mlir::Value bytes = @@ -6181,7 +6187,7 @@ private: auto computeCoordinate = [&](mlir::Value buff, mlir::Value off) { mlir::Type refTy = eleRefTy; if (fir::hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { // Scale a simple pointer using dynamic length and offset values. auto chTy = fir::CharacterType::getSingleton(charTy.getContext(), charTy.getFKind()); @@ -6308,7 +6314,7 @@ private: builder.createConvert(loc, idxTy, fir::getBase(asScalar(x.upper()))); mlir::Value step = builder.createConvert(loc, idxTy, fir::getBase(asScalar(x.stride()))); - auto seqTy = resTy.template cast(); + auto seqTy = mlir::cast(resTy); mlir::Type eleTy = fir::unwrapSequenceType(seqTy); auto loop = builder.create(loc, lo, up, step, /*unordered=*/false, @@ -6375,7 +6381,7 @@ private: auto evExpr = toEvExpr(x); mlir::Type resTy = translateSomeExprToFIRType(converter, evExpr); mlir::IndexType idxTy = builder.getIndexType(); - auto seqTy = resTy.template cast(); + auto seqTy = mlir::cast(resTy); mlir::Type eleTy = fir::unwrapSequenceType(resTy); mlir::Value buffSize = builder.createTemporary(loc, idxTy, ".buff.size"); mlir::Value zero = builder.createIntegerConstant(loc, idxTy, 0); @@ -6719,7 +6725,7 @@ private: auto fieldTy = fir::FieldType::get(builder.getContext()); std::string name = converter.getRecordTypeFieldName(getLastSym(*x)); - if (auto recTy = ty.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(ty)) { ty = recTy.getType(name); auto fld = builder.create( loc, fieldTy, name, recTy, fir::getTypeParams(arrayExv)); @@ -6728,7 +6734,7 @@ private: // Need an intermediate dereference if the boxed value // appears in the middle of the component path or if it is // on the right and this is not a pointer assignment. - if (auto boxTy = ty.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(ty)) { auto currentFunc = components.getExtendCoorRef(); auto loc = getLoc(); auto *bldr = &converter.getFirOpBuilder(); @@ -6739,9 +6745,9 @@ private: deref = true; } } - } else if (auto boxTy = ty.dyn_cast()) { + } else if (auto boxTy = mlir::dyn_cast(ty)) { ty = fir::unwrapRefType(boxTy.getEleTy()); - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); ty = recTy.getType(name); auto fld = builder.create( loc, fieldTy, name, recTy, fir::getTypeParams(arrayExv)); @@ -6790,7 +6796,7 @@ private: auto arrayOp = builder.create( loc, eleRefTy, innerArg, iters.iterVec(), fir::factory::getTypeParams(loc, builder, load)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { mlir::Value dstLen = fir::factory::genLenOfCharacter( builder, loc, load, iters.iterVec(), substringBounds); fir::ArrayAmendOp amend = createCharArrayAmend( @@ -6806,13 +6812,13 @@ private: return arrayLoadExtValue(builder, loc, load, iters.iterVec(), amend); } - assert(eleTy.isa()); + assert(mlir::isa(eleTy)); TODO(loc, "array (as element) assignment"); } if (components.hasExtendCoorRef()) { auto eleBoxTy = fir::applyPathToType(innerArg.getType(), iters.iterVec()); - if (!eleBoxTy || !eleBoxTy.isa()) + if (!eleBoxTy || !mlir::isa(eleBoxTy)) TODO(loc, "assignment in a FORALL involving a designator with a " "POINTER or ALLOCATABLE component part-ref"); auto arrayOp = builder.create( @@ -6824,7 +6830,7 @@ private: // assignment, then insert the dereference of the box before any // conversion and store. if (!isPointerAssignment()) { - if (auto boxTy = eleTy.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(eleTy)) { eleTy = fir::boxMemRefType(boxTy); addr = builder.create(loc, eleTy, addr); eleTy = fir::unwrapRefType(eleTy); @@ -6885,7 +6891,7 @@ private: } if (components.hasExtendCoorRef()) { auto eleBoxTy = fir::applyPathToType(load.getType(), iters.iterVec()); - if (!eleBoxTy || !eleBoxTy.isa()) + if (!eleBoxTy || !mlir::isa(eleBoxTy)) TODO(loc, "assignment in a FORALL involving a designator with a " "POINTER or ALLOCATABLE component part-ref"); auto access = builder.create( @@ -6897,7 +6903,7 @@ private: } if (isPointerAssignment()) { auto eleTy = fir::applyPathToType(load.getType(), iters.iterVec()); - if (!eleTy.isa()) { + if (!mlir::isa(eleTy)) { // Rhs is a regular expression that will need to be boxed before // assigning to the boxed variable. auto typeParams = fir::factory::getTypeParams(loc, builder, load); @@ -7615,7 +7621,7 @@ mlir::Value Fortran::lower::addCrayPointerInst(mlir::Location loc, auto box = builder.create(loc, boxTy, ptrVal, empty, empty, emptyRange); mlir::Value addrof = - (ptrTy.isa()) + (mlir::isa(ptrTy)) ? builder.create(loc, ptrTy, box) : builder.create(loc, builder.getRefType(ptrTy), box); diff --git a/flang/lib/Lower/ConvertExprToHLFIR.cpp b/flang/lib/Lower/ConvertExprToHLFIR.cpp index 6e57b31d022b..93bdf650f9ff 100644 --- a/flang/lib/Lower/ConvertExprToHLFIR.cpp +++ b/flang/lib/Lower/ConvertExprToHLFIR.cpp @@ -138,8 +138,8 @@ public: mlir::Location loc = getLoc(); mlir::Type idxTy = builder.getIndexType(); llvm::SmallVector extents; - auto seqTy = hlfir::getFortranElementOrSequenceType(fieldType) - .cast(); + auto seqTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(fieldType)); for (auto extent : seqTy.getShape()) { if (extent == fir::SequenceType::getUnknownExtent()) { // We have already generated invalid hlfir.declare @@ -199,7 +199,7 @@ private: const T &designatorNode) { // Get base's shape if its a sequence type with no previously computed // result shape - if (partInfo.base && resultValueType.isa() && + if (partInfo.base && mlir::isa(resultValueType) && !partInfo.resultShape) partInfo.resultShape = hlfir::genShape(getLoc(), getBuilder(), *partInfo.base); @@ -209,7 +209,7 @@ private: return fir::ClassType::get(resultValueType); // Character scalar with dynamic length needs a fir.boxchar to hold the // designator length. - auto charType = resultValueType.dyn_cast(); + auto charType = mlir::dyn_cast(resultValueType); if (charType && charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); // Arrays with non default lower bounds or dynamic length or dynamic extent @@ -218,7 +218,7 @@ private: hasNonDefaultLowerBounds(partInfo)) return fir::BoxType::get(resultValueType); // Non simply contiguous ref require a fir.box to carry the byte stride. - if (resultValueType.isa() && + if (mlir::isa(resultValueType) && !Fortran::evaluate::IsSimplyContiguous( designatorNode, getConverter().getFoldingContext())) return fir::BoxType::get(resultValueType); @@ -398,8 +398,8 @@ private: partInfo.typeParams[0] = fir::factory::genMaxWithZero(builder, loc, rawLen); } - auto kind = hlfir::getFortranElementType(baseStringType) - .cast() + auto kind = mlir::cast( + hlfir::getFortranElementType(baseStringType)) .getFKind(); auto newCharTy = fir::CharacterType::get( baseStringType.getContext(), kind, @@ -579,7 +579,7 @@ private: return createVectorSubscriptElementAddrOp(partInfo, baseType, resultExtents); - mlir::Type resultType = baseType.cast().getEleTy(); + mlir::Type resultType = mlir::cast(baseType).getEleTy(); if (!resultTypeShape.empty()) { // Ranked array section. The result shape comes from the array section // subscripts. @@ -612,8 +612,8 @@ private: } static bool hasNonDefaultLowerBounds(const PartInfo &partInfo) { return partInfo.resultShape && - (partInfo.resultShape.getType().isa() || - partInfo.resultShape.getType().isa()); + mlir::isa( + partInfo.resultShape.getType()); } mlir::Type visit(const Fortran::evaluate::Component &component, @@ -705,7 +705,7 @@ private: const Fortran::semantics::Symbol &componentSym = component.GetLastSymbol(); partInfo.componentName = converter.getRecordTypeFieldName(componentSym); auto recordType = - hlfir::getFortranElementType(baseType).cast(); + mlir::cast(hlfir::getFortranElementType(baseType)); if (recordType.isDependentType()) TODO(getLoc(), "Designate derived type with length parameters in HLFIR"); mlir::Type fieldType = recordType.getType(partInfo.componentName); @@ -718,7 +718,7 @@ private: if (fir::isRecordWithTypeParameters(fieldEleType)) TODO(loc, "lower a component that is a parameterized derived type to HLFIR"); - if (auto charTy = fieldEleType.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(fieldEleType)) { mlir::Location loc = getLoc(); mlir::Type idxTy = builder.getIndexType(); if (charTy.hasConstantLen()) @@ -811,7 +811,7 @@ private: } } builder.setInsertionPoint(elementalAddrOp); - return baseType.cast().getEleTy(); + return mlir::cast(baseType).getEleTy(); } /// Yield the designator for the final part-ref inside the @@ -1665,7 +1665,7 @@ private: mlir::Location loc = getLoc(); fir::FirOpBuilder &builder = getBuilder(); mlir::Type ty = translateSomeExprToFIRType(converter, toEvExpr(ctor)); - auto recTy = ty.cast(); + auto recTy = mlir::cast(ty); if (recTy.isDependentType()) TODO(loc, "structure constructor for derived type with length parameters " diff --git a/flang/lib/Lower/ConvertProcedureDesignator.cpp b/flang/lib/Lower/ConvertProcedureDesignator.cpp index 2446be3a1908..aa0d7ce54788 100644 --- a/flang/lib/Lower/ConvertProcedureDesignator.cpp +++ b/flang/lib/Lower/ConvertProcedureDesignator.cpp @@ -107,11 +107,11 @@ static hlfir::EntityWithAttributes designateProcedurePointerComponent( procComponentSym); /// Passed argument may be a descriptor. This is a scalar reference, so the /// base address can be directly addressed. - if (base.getType().isa()) + if (mlir::isa(base.getType())) base = builder.create(loc, base); std::string fieldName = converter.getRecordTypeFieldName(procComponentSym); auto recordType = - hlfir::getFortranElementType(base.getType()).cast(); + mlir::cast(hlfir::getFortranElementType(base.getType())); mlir::Type fieldType = recordType.getType(fieldName); // Note: semantics turns x%p() into x%t%p() when the procedure pointer // component is part of parent component t. @@ -164,7 +164,7 @@ hlfir::EntityWithAttributes Fortran::lower::convertProcedureDesignatorToHLFIR( fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Value funcAddr = fir::getBase(procExv); - if (!funcAddr.getType().isa()) { + if (!mlir::isa(funcAddr.getType())) { mlir::Type boxTy = Fortran::lower::getUntypedBoxProcType(&converter.getMLIRContext()); if (auto host = Fortran::lower::argumentHostAssocs(converter, funcAddr)) diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index 21db0cac11bf..edf1f24a08e5 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -389,13 +389,13 @@ static mlir::Value genDefaultInitializerValue( fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Type scalarType = symTy; fir::SequenceType sequenceType; - if (auto ty = symTy.dyn_cast()) { + if (auto ty = mlir::dyn_cast(symTy)) { sequenceType = ty; scalarType = ty.getEleTy(); } // Build a scalar default value of the symbol type, looping through the // components to build each component initial value. - auto recTy = scalarType.cast(); + auto recTy = mlir::cast(scalarType); mlir::Value initialValue = builder.create(loc, scalarType); const Fortran::semantics::DeclTypeSpec *declTy = sym.GetType(); assert(declTy && "var with default initialization must have a type"); @@ -493,9 +493,9 @@ static fir::GlobalOp defineGlobal(Fortran::lower::AbstractConverter &converter, // with a tensor mlir type. This optimization currently only supports // Fortran arrays of integer, real, complex, or logical. The tensor // type does not support nested structures. - if (symTy.isa() && + if (mlir::isa(symTy) && !Fortran::semantics::IsAllocatableOrPointer(sym)) { - mlir::Type eleTy = symTy.cast().getEleTy(); + mlir::Type eleTy = mlir::cast(symTy).getEleTy(); if (eleTy.isa()) { const auto *details = @@ -1292,7 +1292,7 @@ static void finalizeCommonBlockDefinition( fir::GlobalOp global, const Fortran::semantics::MutableSymbolVector &cmnBlkMems) { fir::FirOpBuilder &builder = converter.getFirOpBuilder(); - mlir::TupleType commonTy = global.getType().cast(); + mlir::TupleType commonTy = mlir::cast(global.getType()); auto initFunc = [&](fir::FirOpBuilder &builder) { mlir::IndexType idxTy = builder.getIndexType(); mlir::Value cb = builder.create(loc, commonTy); @@ -1407,7 +1407,7 @@ static bool lowerToBoxValue(const Fortran::semantics::Symbol &sym, mlir::Value dummyArg, Fortran::lower::AbstractConverter &converter) { // Only dummy arguments coming as fir.box can be tracked in an BoxValue. - if (!dummyArg || !dummyArg.getType().isa()) + if (!dummyArg || !mlir::isa(dummyArg.getType())) return false; // Non contiguous arrays must be tracked in an BoxValue. if (sym.Rank() > 0 && !Fortran::evaluate::IsSimplyContiguous( @@ -1905,7 +1905,7 @@ void Fortran::lower::mapSymbolAttributes( // Do not keep scalar characters as fir.box (even when optional). // Lowering and FIR is not meant to deal with scalar characters as // fir.box outside of calls. - auto boxTy = dummyArg.getType().dyn_cast(); + auto boxTy = mlir::dyn_cast(dummyArg.getType()); mlir::Type refTy = builder.getRefType(boxTy.getEleTy()); mlir::Type lenType = builder.getCharacterLengthType(); mlir::Value addr, len; @@ -1984,8 +1984,8 @@ void Fortran::lower::mapSymbolAttributes( // a non pointer/allocatable symbol to be mapped to a MutableBox. mlir::Type ty = converter.genType(var); bool isPolymorphic = false; - if (auto boxTy = ty.dyn_cast()) { - isPolymorphic = ty.isa(); + if (auto boxTy = mlir::dyn_cast(ty)) { + isPolymorphic = mlir::isa(ty); ty = boxTy.getEleTy(); } Fortran::lower::genDeclareSymbol( @@ -2092,7 +2092,7 @@ void Fortran::lower::mapSymbolAttributes( mlir::Value addr = preAlloc; if (arg) - if (auto boxTy = arg.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(arg.getType())) { // Contiguous assumed shape that can be tracked without a fir.box. mlir::Type refTy = builder.getRefType(boxTy.getEleTy()); addr = builder.create(loc, refTy, arg); @@ -2134,7 +2134,7 @@ void Fortran::lower::mapSymbolAttributes( } else if (!len) { // Assumed length fir.box (possible for contiguous assumed shapes). // Read length from box. - assert(arg && arg.getType().isa() && + assert(arg && mlir::isa(arg.getType()) && "must be character dummy fir.box"); len = charHelp.readLengthFromBox(arg); } diff --git a/flang/lib/Lower/CustomIntrinsicCall.cpp b/flang/lib/Lower/CustomIntrinsicCall.cpp index 439fc3d915b4..30c6ce7f53b3 100644 --- a/flang/lib/Lower/CustomIntrinsicCall.cpp +++ b/flang/lib/Lower/CustomIntrinsicCall.cpp @@ -227,22 +227,23 @@ lowerIshftc(fir::FirOpBuilder &builder, mlir::Location loc, args.push_back(getOperand(1, loadOperand)); auto iPC = isPresentCheck(2); assert(iPC.has_value()); - args.push_back(builder - .genIfOp(loc, {resultType}, *iPC, - /*withElseRegion=*/true) - .genThen([&]() { - fir::ExtendedValue sizeExv = getOperand(2, loadOperand); - mlir::Value size = builder.createConvert( - loc, resultType, fir::getBase(sizeExv)); - builder.create(loc, size); - }) - .genElse([&]() { - mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, - resultType.cast().getWidth()); - builder.create(loc, bitSize); - }) - .getResults()[0]); + args.push_back( + builder + .genIfOp(loc, {resultType}, *iPC, + /*withElseRegion=*/true) + .genThen([&]() { + fir::ExtendedValue sizeExv = getOperand(2, loadOperand); + mlir::Value size = + builder.createConvert(loc, resultType, fir::getBase(sizeExv)); + builder.create(loc, size); + }) + .genElse([&]() { + mlir::Value bitSize = builder.createIntegerConstant( + loc, resultType, + mlir::cast(resultType).getWidth()); + builder.create(loc, bitSize); + }) + .getResults()[0]); return genIntrinsicCall(builder, loc, name, resultType, args, stmtCtx); } @@ -282,7 +283,7 @@ lowerAssociated(fir::FirOpBuilder &builder, mlir::Location loc, builder.create(loc, builder.getI1Type(), targetBase); mlir::Type targetType = fir::unwrapRefType(targetBase.getType()); mlir::Type targetValueType = fir::unwrapPassByRefType(targetType); - mlir::Type boxType = targetType.isa() + mlir::Type boxType = mlir::isa(targetType) ? targetType : fir::BoxType::get(targetValueType); fir::BoxValue targetBox = diff --git a/flang/lib/Lower/DirectivesCommon.h b/flang/lib/Lower/DirectivesCommon.h index 3ebf3fd965da..42bd3868196b 100644 --- a/flang/lib/Lower/DirectivesCommon.h +++ b/flang/lib/Lower/DirectivesCommon.h @@ -642,14 +642,14 @@ getDataOperandBaseAddr(Fortran::lower::AbstractConverter &converter, isPresent = builder.create(loc, builder.getI1Type(), rawInput); - if (auto boxTy = - fir::unwrapRefType(symAddr.getType()).dyn_cast()) { - if (boxTy.getEleTy().isa()) + if (auto boxTy = mlir::dyn_cast( + fir::unwrapRefType(symAddr.getType()))) { + if (mlir::isa(boxTy.getEleTy())) TODO(loc, "derived type"); // Load the box when baseAddr is a `fir.ref>` or a // `fir.ref>` type. - if (symAddr.getType().isa()) { + if (mlir::isa(symAddr.getType())) { if (Fortran::semantics::IsOptional(sym)) { mlir::Value addr = builder.genIfOp(loc, {boxTy}, isPresent, /*withElseRegion=*/true) @@ -722,7 +722,7 @@ genBoundsOpsFromBox(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type idxTy = builder.getIndexType(); mlir::Type boundTy = builder.getType(); - assert(info.addr.getType().isa() && + assert(mlir::isa(info.addr.getType()) && "expect fir.box or fir.class"); if (info.isPresent) { @@ -909,7 +909,8 @@ genBoundsOps(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value stride = one; bool strideInBytes = false; - if (fir::unwrapRefType(info.addr.getType()).isa()) { + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { if (info.isPresent) { stride = builder @@ -1020,8 +1021,8 @@ genBoundsOps(fir::FirOpBuilder &builder, mlir::Location loc, } } - if (info.isPresent && - fir::unwrapRefType(info.addr.getType()).isa()) { + if (info.isPresent && mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { extent = builder .genIfOp(loc, idxTy, info.isPresent, /*withElseRegion=*/true) @@ -1157,7 +1158,7 @@ AddrAndBoundsInfo gatherDataOperandAddrAndBounds( converter.genExprAddr(operandLocation, designator, stmtCtx); info.addr = fir::getBase(compExv); info.rawInput = info.addr; - if (fir::unwrapRefType(info.addr.getType()).isa()) + if (mlir::isa(fir::unwrapRefType(info.addr.getType()))) bounds = genBaseBoundsOps(builder, operandLocation, converter, compExv, /*isAssumedSize=*/false); @@ -1199,13 +1200,14 @@ AddrAndBoundsInfo gatherDataOperandAddrAndBounds( fir::ExtendedValue dataExv = converter.getSymbolExtendedValue(*symRef); info = getDataOperandBaseAddr(converter, builder, *symRef, operandLocation); - if (fir::unwrapRefType(info.addr.getType()).isa()) { + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { bounds = genBoundsOpsFromBox( builder, operandLocation, converter, dataExv, info); } bool dataExvIsAssumedSize = Fortran::semantics::IsAssumedSizeArray(symRef->get().GetUltimate()); - if (fir::unwrapRefType(info.addr.getType()).isa()) + if (mlir::isa(fir::unwrapRefType(info.addr.getType()))) bounds = genBaseBoundsOps( builder, operandLocation, converter, dataExv, dataExvIsAssumedSize); asFortran << symRef->get().name().ToString(); diff --git a/flang/lib/Lower/HlfirIntrinsics.cpp b/flang/lib/Lower/HlfirIntrinsics.cpp index bda04fa9689b..310b62697f71 100644 --- a/flang/lib/Lower/HlfirIntrinsics.cpp +++ b/flang/lib/Lower/HlfirIntrinsics.cpp @@ -265,7 +265,7 @@ HlfirTransformationalIntrinsic::computeResultType(mlir::Value argArray, mlir::Type stmtResultType) { mlir::Type normalisedResult = hlfir::getFortranElementOrSequenceType(stmtResultType); - if (auto array = normalisedResult.dyn_cast()) { + if (auto array = mlir::dyn_cast(normalisedResult)) { hlfir::ExprType::Shape resultShape = hlfir::ExprType::Shape{array.getShape()}; mlir::Type elementType = array.getEleTy(); @@ -341,7 +341,7 @@ mlir::Value HlfirTransposeLowering::lowerImpl( hlfir::ExprType::Shape resultShape; mlir::Type normalisedResult = hlfir::getFortranElementOrSequenceType(stmtResultType); - auto array = normalisedResult.cast(); + auto array = mlir::cast(normalisedResult); llvm::ArrayRef arrayShape = array.getShape(); assert(arrayShape.size() == 2 && "arguments to transpose have a rank of 2"); mlir::Type elementType = array.getEleTy(); diff --git a/flang/lib/Lower/HostAssociations.cpp b/flang/lib/Lower/HostAssociations.cpp index 2e2656356719..75a5bed56655 100644 --- a/flang/lib/Lower/HostAssociations.cpp +++ b/flang/lib/Lower/HostAssociations.cpp @@ -219,7 +219,7 @@ public: static mlir::Type getType(Fortran::lower::AbstractConverter &converter, const Fortran::semantics::Symbol &sym) { fir::KindTy kind = - converter.genType(sym).cast().getFKind(); + mlir::cast(converter.genType(sym)).getFKind(); return fir::BoxCharType::get(&converter.getMLIRContext(), kind); } @@ -293,7 +293,7 @@ public: mlir::Location loc = args.loc; mlir::Value box = args.valueInTuple; if (Fortran::semantics::IsOptional(sym)) { - auto boxTy = box.getType().cast(); + auto boxTy = mlir::cast(box.getType()); auto eleTy = boxTy.getEleTy(); if (!fir::isa_ref_type(eleTy)) eleTy = builder.getRefType(eleTy); @@ -381,8 +381,8 @@ public: const Fortran::semantics::Symbol &sym) { mlir::Type type = converter.genType(sym); bool isPolymorphic = Fortran::semantics::IsPolymorphic(sym); - assert((type.isa() || - (isPolymorphic && type.isa())) && + assert((mlir::isa(type) || + (isPolymorphic && mlir::isa(type))) && "must be a sequence type"); if (isPolymorphic) return type; @@ -459,7 +459,7 @@ public: // (absent boxes are null descriptor addresses, not descriptors containing // a null base address). if (Fortran::semantics::IsOptional(sym)) { - auto boxTy = box.getType().cast(); + auto boxTy = mlir::cast(box.getType()); auto eleTy = boxTy.getEleTy(); if (!fir::isa_ref_type(eleTy)) eleTy = builder.getRefType(eleTy); @@ -527,7 +527,7 @@ walkCaptureCategories(T visitor, Fortran::lower::AbstractConverter &converter, // `t` should be the result of getArgumentType, which has a type of // `!fir.ref>`. static mlir::TupleType unwrapTupleTy(mlir::Type t) { - return fir::dyn_cast_ptrEleTy(t).cast(); + return mlir::cast(fir::dyn_cast_ptrEleTy(t)); } static mlir::Value genTupleCoor(fir::FirOpBuilder &builder, mlir::Location loc, @@ -535,7 +535,7 @@ static mlir::Value genTupleCoor(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value offset) { // fir.ref and fir.ptr are forbidden. Use // fir.llvm_ptr if needed. - auto ty = varTy.isa() + auto ty = mlir::isa(varTy) ? mlir::Type(fir::LLVMPointerType::get(varTy)) : mlir::Type(builder.getRefType(varTy)); return builder.create(loc, ty, tupleArg, offset); diff --git a/flang/lib/Lower/IO.cpp b/flang/lib/Lower/IO.cpp index ac82276bcddb..ed0afad9197d 100644 --- a/flang/lib/Lower/IO.cpp +++ b/flang/lib/Lower/IO.cpp @@ -168,7 +168,7 @@ static constexpr fir::runtime::FuncTypeBuilderFunc getTypeModel() { } inline int64_t getLength(mlir::Type argTy) { - return argTy.cast().getShape()[0]; + return mlir::cast(argTy).getShape()[0]; } /// Get (or generate) the MLIR FuncOp for a given IO runtime function. @@ -656,11 +656,11 @@ static void genNamelistIO(Fortran::lower::AbstractConverter &converter, static mlir::func::FuncOp getOutputFunc(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type type, bool isFormatted) { - if (fir::unwrapPassByRefType(type).isa()) + if (mlir::isa(fir::unwrapPassByRefType(type))) return getIORuntimeFunc(loc, builder); if (!isFormatted) return getIORuntimeFunc(loc, builder); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { switch (ty.getWidth()) { case 1: return getIORuntimeFunc(loc, builder); @@ -677,14 +677,14 @@ static mlir::func::FuncOp getOutputFunc(mlir::Location loc, } llvm_unreachable("unknown OutputInteger kind"); } - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { if (auto width = ty.getWidth(); width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } auto kindMap = fir::getKindMapping(builder.getModule()); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { // COMPLEX(KIND=k) corresponds to a pair of REAL(KIND=k). auto width = kindMap.getRealBitsize(ty.getFKind()); if (width == 32) @@ -692,7 +692,7 @@ static mlir::func::FuncOp getOutputFunc(mlir::Location loc, else if (width == 64) return getIORuntimeFunc(loc, builder); } - if (type.isa()) + if (mlir::isa(type)) return getIORuntimeFunc(loc, builder); if (fir::factory::CharacterExprHelper::isCharacterScalar(type)) { // TODO: What would it mean if the default CHARACTER KIND is set to a wide @@ -731,14 +731,14 @@ static void genOutputItemList( mlir::func::FuncOp outputFunc = getOutputFunc(loc, builder, itemTy, isFormatted); mlir::Type argType = outputFunc.getFunctionType().getInput(1); - assert((isFormatted || argType.isa()) && + assert((isFormatted || mlir::isa(argType)) && "expect descriptor for unformatted IO runtime"); llvm::SmallVector outputFuncArgs = {cookie}; fir::factory::CharacterExprHelper helper{builder, loc}; - if (argType.isa()) { + if (mlir::isa(argType)) { mlir::Value box = fir::getBase(converter.genExprBox(loc, *expr, stmtCtx)); outputFuncArgs.push_back(builder.createConvert(loc, argType, box)); - if (fir::unwrapPassByRefType(itemTy).isa()) + if (mlir::isa(fir::unwrapPassByRefType(itemTy))) outputFuncArgs.push_back(getNonTbpDefinedIoTableAddr(converter)); } else if (helper.isCharacterScalar(itemTy)) { fir::ExtendedValue exv = converter.genExprAddr(loc, expr, stmtCtx); @@ -773,29 +773,29 @@ static void genOutputItemList( static mlir::func::FuncOp getInputFunc(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type type, bool isFormatted) { - if (fir::unwrapPassByRefType(type).isa()) + if (mlir::isa(fir::unwrapPassByRefType(type))) return getIORuntimeFunc(loc, builder); if (!isFormatted) return getIORuntimeFunc(loc, builder); - if (auto ty = type.dyn_cast()) + if (auto ty = mlir::dyn_cast(type)) return ty.getWidth() == 1 ? getIORuntimeFunc(loc, builder) : getIORuntimeFunc(loc, builder); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { if (auto width = ty.getWidth(); width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } auto kindMap = fir::getKindMapping(builder.getModule()); - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { auto width = kindMap.getRealBitsize(ty.getFKind()); if (width == 32) return getIORuntimeFunc(loc, builder); else if (width == 64) return getIORuntimeFunc(loc, builder); } - if (type.isa()) + if (mlir::isa(type)) return getIORuntimeFunc(loc, builder); if (fir::factory::CharacterExprHelper::isCharacterScalar(type)) { auto asciiKind = kindMap.defaultCharacterKind(); @@ -830,12 +830,12 @@ createIoRuntimeCallForItem(Fortran::lower::AbstractConverter &converter, fir::FirOpBuilder &builder = converter.getFirOpBuilder(); mlir::Type argType = inputFunc.getFunctionType().getInput(1); llvm::SmallVector inputFuncArgs = {cookie}; - if (argType.isa()) { + if (mlir::isa(argType)) { mlir::Value box = fir::getBase(item); - auto boxTy = box.getType().dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getType()); assert(boxTy && "must be previously emboxed"); inputFuncArgs.push_back(builder.createConvert(loc, argType, box)); - if (fir::unwrapPassByRefType(boxTy).isa()) + if (mlir::isa(fir::unwrapPassByRefType(boxTy))) inputFuncArgs.push_back(getNonTbpDefinedIoTableAddr(converter)); } else { mlir::Value itemAddr = fir::getBase(item); @@ -846,16 +846,16 @@ createIoRuntimeCallForItem(Fortran::lower::AbstractConverter &converter, mlir::Value len = fir::getLen(item); inputFuncArgs.push_back(builder.createConvert( loc, inputFunc.getFunctionType().getInput(2), len)); - } else if (itemTy.isa()) { + } else if (mlir::isa(itemTy)) { inputFuncArgs.push_back(builder.create( loc, builder.getI32IntegerAttr( - itemTy.cast().getWidth() / 8))); + mlir::cast(itemTy).getWidth() / 8))); } } auto call = builder.create(loc, inputFunc, inputFuncArgs); auto itemAddr = fir::getBase(item); auto itemTy = fir::unwrapRefType(itemAddr.getType()); - if (itemTy.isa()) + if (mlir::isa(itemTy)) boolRefToLogical(loc, builder, itemAddr); return call.getResult(0); } @@ -886,7 +886,7 @@ static void genInputItemList(Fortran::lower::AbstractConverter &converter, mlir::func::FuncOp inputFunc = getInputFunc( loc, builder, vectorSubscriptBox.getElementType(), isFormatted); const bool mustBox = - inputFunc.getFunctionType().getInput(1).isa(); + mlir::isa(inputFunc.getFunctionType().getInput(1)); if (!checkResult) { auto elementalGenerator = [&](const fir::ExtendedValue &element) { createIoRuntimeCallForItem(converter, loc, inputFunc, cookie, @@ -911,9 +911,10 @@ static void genInputItemList(Fortran::lower::AbstractConverter &converter, mlir::Type itemTy = converter.genType(*expr); mlir::func::FuncOp inputFunc = getInputFunc(loc, builder, itemTy, isFormatted); - auto itemExv = inputFunc.getFunctionType().getInput(1).isa() - ? converter.genExprBox(loc, *expr, stmtCtx) - : converter.genExprAddr(loc, expr, stmtCtx); + auto itemExv = + mlir::isa(inputFunc.getFunctionType().getInput(1)) + ? converter.genExprBox(loc, *expr, stmtCtx) + : converter.genExprAddr(loc, expr, stmtCtx); ok = createIoRuntimeCallForItem(converter, loc, inputFunc, cookie, itemExv); } } @@ -1772,8 +1773,8 @@ static mlir::Value genIOUnitNumber(Fortran::lower::AbstractConverter &converter, auto &builder = converter.getFirOpBuilder(); auto rawUnit = fir::getBase(converter.genExprValue(loc, iounit, stmtCtx)); unsigned rawUnitWidth = - rawUnit.getType().cast().getWidth(); - unsigned runtimeArgWidth = ty.cast().getWidth(); + mlir::cast(rawUnit.getType()).getWidth(); + unsigned runtimeArgWidth = mlir::cast(ty).getWidth(); // The IO runtime supports `int` unit numbers, if the unit number may // overflow when passed to the IO runtime, check that the unit number is // in range before calling the BeginXXX. @@ -2331,7 +2332,7 @@ mlir::Value genInquireSpec( if (!eleTy) fir::emitFatalError(loc, "internal error: expected a memory reference type"); - auto width = eleTy.cast().getWidth(); + auto width = mlir::cast(eleTy).getWidth(); mlir::IndexType idxTy = builder.getIndexType(); mlir::Value kind = builder.createIntegerConstant(loc, idxTy, width / 8); llvm::SmallVector args = { diff --git a/flang/lib/Lower/OpenACC.cpp b/flang/lib/Lower/OpenACC.cpp index b56bdedc07bf..eae2afc760e6 100644 --- a/flang/lib/Lower/OpenACC.cpp +++ b/flang/lib/Lower/OpenACC.cpp @@ -65,7 +65,7 @@ static Op createDataEntryOp(fir::FirOpBuilder &builder, mlir::Location loc, mlir::acc::DataClause dataClause, mlir::Type retTy, mlir::Value isPresent = {}) { mlir::Value varPtrPtr; - if (auto boxTy = baseAddr.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(baseAddr.getType())) { if (isPresent) { mlir::Type ifRetTy = boxTy.getEleTy(); if (!fir::isa_ref_type(ifRetTy)) @@ -2658,7 +2658,7 @@ genACCHostDataOp(Fortran::lower::AbstractConverter &converter, if (ifCond) { if (auto cst = mlir::dyn_cast(ifCond.getDefiningOp())) - if (auto boolAttr = cst.getValue().dyn_cast()) { + if (auto boolAttr = mlir::dyn_cast(cst.getValue())) { if (boolAttr.getValue()) { // get rid of the if condition if it is always true. ifCond = mlir::Value(); diff --git a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp index 4c51b61f6bf0..79525d6dfe7a 100644 --- a/flang/lib/Lower/OpenMP/ClauseProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ClauseProcessor.cpp @@ -23,10 +23,10 @@ namespace omp { /// Check for unsupported map operand types. static void checkMapType(mlir::Location location, mlir::Type type) { - if (auto refType = type.dyn_cast()) + if (auto refType = mlir::dyn_cast(type)) type = refType.getElementType(); - if (auto boxType = type.dyn_cast_or_null()) - if (!boxType.getElementType().isa()) + if (auto boxType = mlir::dyn_cast_or_null(type)) + if (!mlir::isa(boxType.getElementType())) TODO(location, "OMPD_target_data MapOperand BoxType"); } @@ -814,7 +814,7 @@ createMapInfoOp(fir::FirOpBuilder &builder, mlir::Location loc, llvm::ArrayRef members, uint64_t mapType, mlir::omp::VariableCaptureKind mapCaptureType, mlir::Type retTy, bool isVal) { - if (auto boxTy = baseAddr.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(baseAddr.getType())) { baseAddr = builder.create(loc, baseAddr); retTy = baseAddr.getType(); } diff --git a/flang/lib/Lower/OpenMP/OpenMP.cpp b/flang/lib/Lower/OpenMP/OpenMP.cpp index f454f5a45a51..64ec5ae65c82 100644 --- a/flang/lib/Lower/OpenMP/OpenMP.cpp +++ b/flang/lib/Lower/OpenMP/OpenMP.cpp @@ -84,7 +84,7 @@ static fir::GlobalOp globalInitialization( // Create default initialization for non-character scalar. if (Fortran::semantics::IsAllocatableOrObjectPointer(&sym)) { - mlir::Type baseAddrType = ty.dyn_cast().getEleTy(); + mlir::Type baseAddrType = mlir::dyn_cast(ty).getEleTy(); Fortran::lower::createGlobalInitialization( firOpBuilder, global, [&](fir::FirOpBuilder &b) { mlir::Value nullAddr = @@ -778,7 +778,7 @@ static void genBodyOfTargetDataOp( for (auto [argIndex, argSymbol] : llvm::enumerate(useDeviceSymbols)) { const mlir::BlockArgument &arg = region.front().getArgument(argIndex); fir::ExtendedValue extVal = converter.getSymbolExtendedValue(*argSymbol); - if (auto refType = arg.getType().dyn_cast()) { + if (auto refType = mlir::dyn_cast(arg.getType())) { if (fir::isa_builtin_cptr_type(refType.getElementType())) { converter.bindSymbol(*argSymbol, arg); } else { @@ -1570,13 +1570,15 @@ genTargetOp(Fortran::lower::AbstractConverter &converter, Fortran::lower::AddrAndBoundsInfo info = getDataOperandBaseAddr( converter, firOpBuilder, sym, converter.getCurrentLocation()); - if (fir::unwrapRefType(info.addr.getType()).isa()) + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) bounds = Fortran::lower::genBoundsOpsFromBox( firOpBuilder, converter.getCurrentLocation(), converter, dataExv, info); - if (fir::unwrapRefType(info.addr.getType()).isa()) { + if (mlir::isa( + fir::unwrapRefType(info.addr.getType()))) { bool dataExvIsAssumedSize = Fortran::semantics::IsAssumedSizeArray(sym.GetUltimate()); bounds = Fortran::lower::genBaseBoundsOps()) + if (auto refType = mlir::dyn_cast(baseOp.getType())) eleType = refType.getElementType(); // If a variable is specified in declare target link and if device diff --git a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp index 895340549f7c..38edd1b46821 100644 --- a/flang/lib/Lower/OpenMP/ReductionProcessor.cpp +++ b/flang/lib/Lower/OpenMP/ReductionProcessor.cpp @@ -138,7 +138,7 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, TODO(loc, "Reduction of some types is not supported"); switch (redId) { case ReductionIdentifier::MAX: { - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, type, llvm::APFloat::getLargest(sem, /*Negative=*/true)); @@ -148,7 +148,7 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, return builder.createIntegerConstant(loc, type, minInt); } case ReductionIdentifier::MIN: { - if (auto ty = type.dyn_cast()) { + if (auto ty = mlir::dyn_cast(type)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, type, llvm::APFloat::getLargest(sem, /*Negative=*/false)); @@ -188,12 +188,12 @@ ReductionProcessor::getReductionInitValue(mlir::Location loc, mlir::Type type, return fir::factory::Complex{builder, loc}.createComplex(type, initRe, initIm); } - if (type.isa()) + if (mlir::isa(type)) return builder.create( loc, type, builder.getFloatAttr(type, (double)getOperationIdentity(redId, loc))); - if (type.isa()) { + if (mlir::isa(type)) { mlir::Value intConst = builder.create( loc, builder.getI1Type(), builder.getIntegerAttr(builder.getI1Type(), @@ -474,11 +474,11 @@ createReductionCleanupRegion(fir::FirOpBuilder &builder, mlir::Location loc, // like fir::unwrapSeqOrBoxedSeqType except it also works for non-sequence boxes static mlir::Type unwrapSeqOrBoxedType(mlir::Type ty) { - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return seqTy.getEleTy(); - if (auto boxTy = ty.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(ty)) { auto eleTy = fir::unwrapRefType(boxTy.getEleTy()); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); return eleTy; } @@ -790,7 +790,7 @@ void ReductionProcessor::addDeclareReduction( for (mlir::Value symVal : reductionVars) { auto redType = mlir::cast(symVal.getType()); const auto &kindMap = firOpBuilder.getKindMap(); - if (redType.getEleTy().isa()) + if (mlir::isa(redType.getEleTy())) decl = createDeclareReduction(firOpBuilder, getReductionName(intrinsicOp, kindMap, firOpBuilder.getI1Type(), @@ -816,7 +816,7 @@ void ReductionProcessor::addDeclareReduction( mlir::Value symVal = converter.getSymbolAddress(*symbol); if (auto declOp = symVal.getDefiningOp()) symVal = declOp.getBase(); - auto redType = symVal.getType().cast(); + auto redType = mlir::cast(symVal.getType()); if (!redType.getEleTy().isIntOrIndexOrFloat()) TODO(currentLocation, "User Defined Reduction on non-trivial type"); decl = createDeclareReduction( diff --git a/flang/lib/Lower/VectorSubscripts.cpp b/flang/lib/Lower/VectorSubscripts.cpp index 7439b9f7df8f..d7a311d32d59 100644 --- a/flang/lib/Lower/VectorSubscripts.cpp +++ b/flang/lib/Lower/VectorSubscripts.cpp @@ -105,7 +105,7 @@ private: } mlir::Type gen(const Fortran::evaluate::Component &component) { - auto recTy = gen(component.base()).cast(); + auto recTy = mlir::cast(gen(component.base())); const Fortran::semantics::Symbol &componentSymbol = component.GetLastSymbol(); // Parent components will not be found here, they are not part diff --git a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp index c403b9effbfa..f723e8f66e3e 100644 --- a/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp +++ b/flang/lib/Optimizer/Analysis/AliasAnalysis.cpp @@ -68,7 +68,7 @@ bool AliasAnalysis::Source::isPointerReference(mlir::Type ty) { if (!eleTy) return false; - return fir::isPointerType(eleTy) || eleTy.isa(); + return fir::isPointerType(eleTy) || mlir::isa(eleTy); } bool AliasAnalysis::Source::isTargetOrPointer() const { @@ -81,7 +81,7 @@ bool AliasAnalysis::Source::isRecordWithPointerComponent() const { if (!eleTy) return false; // TO DO: Look for pointer components - return eleTy.isa(); + return mlir::isa(eleTy); } AliasResult AliasAnalysis::alias(Value lhs, Value rhs) { diff --git a/flang/lib/Optimizer/Builder/BoxValue.cpp b/flang/lib/Optimizer/Builder/BoxValue.cpp index 361fa59e2040..a90ce5570de7 100644 --- a/flang/lib/Optimizer/Builder/BoxValue.cpp +++ b/flang/lib/Optimizer/Builder/BoxValue.cpp @@ -191,7 +191,7 @@ bool fir::MutableBoxValue::verify() const { mlir::Type type = fir::dyn_cast_ptrEleTy(getAddr().getType()); if (!type) return false; - auto box = type.dyn_cast(); + auto box = mlir::dyn_cast(type); if (!box) return false; // A boxed value always takes a memory reference, @@ -210,7 +210,7 @@ bool fir::MutableBoxValue::verify() const { /// Debug verifier for BoxValue ctor. There is no guarantee this will /// always be called. bool fir::BoxValue::verify() const { - if (!addr.getType().isa()) + if (!mlir::isa(addr.getType())) return false; if (!lbounds.empty() && lbounds.size() != rank()) return false; diff --git a/flang/lib/Optimizer/Builder/Character.cpp b/flang/lib/Optimizer/Builder/Character.cpp index af0786809cc2..b7a7453efdb3 100644 --- a/flang/lib/Optimizer/Builder/Character.cpp +++ b/flang/lib/Optimizer/Builder/Character.cpp @@ -26,11 +26,11 @@ /// Unwrap all the ref and box types and return the inner element type. static mlir::Type unwrapBoxAndRef(mlir::Type type) { - if (auto boxType = type.dyn_cast()) + if (auto boxType = mlir::dyn_cast(type)) return boxType.getEleTy(); while (true) { type = fir::unwrapRefType(type); - if (auto boxTy = type.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(type)) type = boxTy.getEleTy(); else break; @@ -41,19 +41,19 @@ static mlir::Type unwrapBoxAndRef(mlir::Type type) { /// Unwrap base fir.char type. static fir::CharacterType recoverCharacterType(mlir::Type type) { type = fir::unwrapSequenceType(unwrapBoxAndRef(type)); - if (auto charTy = type.dyn_cast()) + if (auto charTy = mlir::dyn_cast(type)) return charTy; llvm::report_fatal_error("expected a character type"); } bool fir::factory::CharacterExprHelper::isCharacterScalar(mlir::Type type) { type = unwrapBoxAndRef(type); - return !type.isa() && fir::isa_char(type); + return !mlir::isa(type) && fir::isa_char(type); } bool fir::factory::CharacterExprHelper::isArray(mlir::Type type) { type = unwrapBoxAndRef(type); - if (auto seqTy = type.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(type)) return fir::isa_char(seqTy.getEleTy()); return false; } @@ -92,7 +92,8 @@ getCompileTimeLength(const fir::CharBoxValue &box) { /// Detect the precondition that the value `str` does not reside in memory. Such /// values will have a type `!fir.array<...x!fir.char>` or `!fir.char`. LLVM_ATTRIBUTE_UNUSED static bool needToMaterialize(mlir::Value str) { - return str.getType().isa() || fir::isa_char(str.getType()); + return mlir::isa(str.getType()) || + fir::isa_char(str.getType()); } /// This is called only if `str` does not reside in memory. Such a bare string @@ -103,7 +104,7 @@ fir::factory::CharacterExprHelper::materializeValue(mlir::Value str) { assert(needToMaterialize(str)); auto ty = str.getType(); assert(isCharacterScalar(ty) && "expected scalar character"); - auto charTy = ty.dyn_cast(); + auto charTy = mlir::dyn_cast(ty); if (!charTy || charTy.getLen() == fir::CharacterType::unknownLen()) { LLVM_DEBUG(llvm::dbgs() << "cannot materialize: " << str << '\n'); llvm_unreachable("must be a !fir.char type"); @@ -129,7 +130,7 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, if (auto eleType = fir::dyn_cast_ptrEleTy(type)) type = eleType; - if (auto arrayType = type.dyn_cast()) { + if (auto arrayType = mlir::dyn_cast(type)) { type = arrayType.getEleTy(); auto indexType = builder.getIndexType(); for (auto extent : arrayType.getShape()) { @@ -145,10 +146,10 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, mlir::emitError(loc, "cannot retrieve array extents from type"); } - if (auto charTy = type.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(type)) { if (!resultLen && charTy.getLen() != fir::CharacterType::unknownLen()) resultLen = builder.createIntegerConstant(loc, lenType, charTy.getLen()); - } else if (auto boxCharType = type.dyn_cast()) { + } else if (auto boxCharType = mlir::dyn_cast(type)) { auto refType = builder.getRefType(boxCharType.getEleTy()); // If the embox is accessible, use its operand to avoid filling // the generated fir with embox/unbox. @@ -168,7 +169,7 @@ fir::factory::CharacterExprHelper::toExtendedValue(mlir::Value character, if (!resultLen) { resultLen = boxCharLen; } - } else if (type.isa()) { + } else if (mlir::isa(type)) { mlir::emitError(loc, "descriptor or derived type not yet handled"); } else { llvm_unreachable("Cannot translate mlir::Value to character ExtendedValue"); @@ -221,7 +222,7 @@ fir::factory::CharacterExprHelper::createEmbox(const fir::CharBoxValue &box) { fir::CharBoxValue fir::factory::CharacterExprHelper::toScalarCharacter( const fir::CharArrayBoxValue &box) { - if (box.getBuffer().getType().isa()) + if (mlir::isa(box.getBuffer().getType())) TODO(loc, "concatenating non contiguous character array into a scalar"); // TODO: add a fast path multiplying new length at compile time if the info is @@ -655,7 +656,7 @@ fir::factory::CharacterExprHelper::createUnboxChar(mlir::Value boxChar) { } bool fir::factory::CharacterExprHelper::isCharacterLiteral(mlir::Type type) { - if (auto seqType = type.dyn_cast()) + if (auto seqType = mlir::dyn_cast(type)) return (seqType.getShape().size() == 1) && fir::isa_char(seqType.getEleTy()); return false; @@ -728,9 +729,9 @@ mlir::Value fir::factory::CharacterExprHelper::getLength(mlir::Value memref) { if (charType.hasConstantLen()) return builder.createIntegerConstant(loc, builder.getCharacterLengthType(), charType.getLen()); - if (memrefType.isa()) + if (mlir::isa(memrefType)) return readLengthFromBox(memref); - if (memrefType.isa()) + if (mlir::isa(memrefType)) return createUnboxChar(memref).second; // Length cannot be deduced from memref. @@ -742,14 +743,14 @@ fir::factory::extractCharacterProcedureTuple(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value tuple, bool openBoxProc) { - mlir::TupleType tupleType = tuple.getType().cast(); + mlir::TupleType tupleType = mlir::cast(tuple.getType()); mlir::Value addr = builder.create( loc, tupleType.getType(0), tuple, builder.getArrayAttr( {builder.getIntegerAttr(builder.getIndexType(), 0)})); mlir::Value proc = [&]() -> mlir::Value { if (openBoxProc) - if (auto addrTy = addr.getType().dyn_cast()) + if (auto addrTy = mlir::dyn_cast(addr.getType())) return builder.create(loc, addrTy.getEleTy(), addr); return addr; }(); @@ -763,7 +764,7 @@ fir::factory::extractCharacterProcedureTuple(fir::FirOpBuilder &builder, mlir::Value fir::factory::createCharacterProcedureTuple( fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type argTy, mlir::Value addr, mlir::Value len) { - mlir::TupleType tupleType = argTy.cast(); + mlir::TupleType tupleType = mlir::cast(argTy); addr = builder.createConvert(loc, tupleType.getType(0), addr); if (len) len = builder.createConvert(loc, tupleType.getType(1), len); @@ -866,7 +867,7 @@ fir::factory::convertCharacterKind(fir::FirOpBuilder &builder, auto kindMap = builder.getKindMap(); mlir::Value boxCharAddr = srcBoxChar.getAddr(); auto fromTy = boxCharAddr.getType(); - if (auto charTy = fromTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(fromTy)) { // boxchar is a value, not a variable. Turn it into a temporary. // As a value, it ought to have a constant LEN value. assert(charTy.hasConstantLen() && "must have constant length"); @@ -875,7 +876,7 @@ fir::factory::convertCharacterKind(fir::FirOpBuilder &builder, boxCharAddr = tmp; } auto fromBits = kindMap.getCharacterBitsize( - fir::unwrapRefType(fromTy).cast().getFKind()); + mlir::cast(fir::unwrapRefType(fromTy)).getFKind()); auto toBits = kindMap.getCharacterBitsize(toKind); if (toBits < fromBits) { // Scale by relative ratio to give a buffer of the same length. diff --git a/flang/lib/Optimizer/Builder/Complex.cpp b/flang/lib/Optimizer/Builder/Complex.cpp index e97cb3067808..cbcd4f850014 100644 --- a/flang/lib/Optimizer/Builder/Complex.cpp +++ b/flang/lib/Optimizer/Builder/Complex.cpp @@ -14,7 +14,8 @@ mlir::Type fir::factory::Complex::getComplexPartType(mlir::Type complexType) const { - return builder.getRealType(complexType.cast().getFKind()); + return builder.getRealType( + mlir::cast(complexType).getFKind()); } mlir::Type fir::factory::Complex::getComplexPartType(mlir::Value cplx) const { diff --git a/flang/lib/Optimizer/Builder/FIRBuilder.cpp b/flang/lib/Optimizer/Builder/FIRBuilder.cpp index a0fbae5b614c..a6da38763726 100644 --- a/flang/lib/Optimizer/Builder/FIRBuilder.cpp +++ b/flang/lib/Optimizer/Builder/FIRBuilder.cpp @@ -90,7 +90,7 @@ fir::FirOpBuilder::getNamedGlobal(mlir::ModuleOp modOp, } mlir::Type fir::FirOpBuilder::getRefType(mlir::Type eleTy) { - assert(!eleTy.isa() && "cannot be a reference type"); + assert(!mlir::isa(eleTy) && "cannot be a reference type"); return fir::ReferenceType::get(eleTy); } @@ -147,7 +147,7 @@ mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, llvm::APFloat::integerPart val) { auto apf = [&]() -> llvm::APFloat { - if (auto ty = fltTy.dyn_cast()) + if (auto ty = mlir::dyn_cast(fltTy)) return llvm::APFloat(kindMap.getFloatSemantics(ty.getFKind()), val); if (fltTy.isF16()) return llvm::APFloat(llvm::APFloat::IEEEhalf(), val); @@ -169,7 +169,7 @@ fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, mlir::Type fltTy, const llvm::APFloat &value) { - if (fltTy.isa()) { + if (mlir::isa(fltTy)) { auto attr = getFloatAttr(fltTy, value); return create(loc, fltTy, attr); } @@ -178,7 +178,7 @@ mlir::Value fir::FirOpBuilder::createRealConstant(mlir::Location loc, static llvm::SmallVector elideExtentsAlreadyInType(mlir::Type type, mlir::ValueRange shape) { - auto arrTy = type.dyn_cast(); + auto arrTy = mlir::dyn_cast(type); if (shape.empty() || !arrTy) return {}; // elide the constant dimensions before construction @@ -195,7 +195,7 @@ static llvm::SmallVector elideLengthsAlreadyInType(mlir::Type type, mlir::ValueRange lenParams) { if (lenParams.empty()) return {}; - if (auto arrTy = type.dyn_cast()) + if (auto arrTy = mlir::dyn_cast(type)) type = arrTy.getEleTy(); if (fir::hasDynamicSize(type)) return lenParams; @@ -264,7 +264,7 @@ mlir::Value fir::FirOpBuilder::createTemporaryAlloc( mlir::Location loc, mlir::Type type, llvm::StringRef name, mlir::ValueRange lenParams, mlir::ValueRange shape, llvm::ArrayRef attrs) { - assert(!type.isa() && "cannot be a reference"); + assert(!mlir::isa(type) && "cannot be a reference"); // If the alloca is inside an OpenMP Op which will be outlined then pin // the alloca here. const bool pinned = @@ -310,7 +310,7 @@ mlir::Value fir::FirOpBuilder::createHeapTemporary( llvm::SmallVector dynamicLength = elideLengthsAlreadyInType(type, lenParams); - assert(!type.isa() && "cannot be a reference"); + assert(!mlir::isa(type) && "cannot be a reference"); return create(loc, type, /*unique_name=*/llvm::StringRef{}, name, dynamicLength, dynamicShape, attrs); } @@ -376,8 +376,9 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( // imaginary part is zero auto eleTy = helper.getComplexPartType(toTy); auto cast = createConvert(loc, eleTy, val); - llvm::APFloat zero{ - kindMap.getFloatSemantics(toTy.cast().getFKind()), 0}; + llvm::APFloat zero{kindMap.getFloatSemantics( + mlir::cast(toTy).getFKind()), + 0}; auto imag = createRealConstant(loc, eleTy, zero); return helper.createComplex(toTy, cast, imag); } @@ -388,14 +389,14 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( return createConvert(loc, toTy, rp); } if (allowCharacterConversion) { - if (fromTy.isa()) { + if (mlir::isa(fromTy)) { // Extract the address of the character string and pass it fir::factory::CharacterExprHelper charHelper{*this, loc}; std::pair unboxchar = charHelper.createUnboxChar(val); return createConvert(loc, toTy, unboxchar.first); } - if (auto boxType = toTy.dyn_cast()) { + if (auto boxType = mlir::dyn_cast(toTy)) { // Extract the address of the actual argument and create a boxed // character value with an undefined length // TODO: We should really calculate the total size of the actual @@ -415,10 +416,10 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( "element types expected to match")); return create(loc, toTy, val); } - if (fir::isa_ref_type(fromTy) && toTy.isa()) { + if (fir::isa_ref_type(fromTy) && mlir::isa(toTy)) { // Call is expecting a boxed procedure, not a reference to other data type. // Convert the reference to a procedure and embox it. - mlir::Type procTy = toTy.cast().getEleTy(); + mlir::Type procTy = mlir::cast(toTy).getEleTy(); mlir::Value proc = createConvert(loc, procTy, val); return create(loc, toTy, proc); } @@ -428,7 +429,7 @@ mlir::Value fir::FirOpBuilder::convertWithSemantics( if (((fir::isPolymorphicType(fromTy) && (fir::isAllocatableType(fromTy) || fir::isPointerType(fromTy)) && fir::isPolymorphicType(toTy)) || - (fir::isPolymorphicType(fromTy) && toTy.isa())) && + (fir::isPolymorphicType(fromTy) && mlir::isa(toTy))) && !(fir::isUnlimitedPolymorphicType(fromTy) && fir::isAssumedType(toTy))) return create(loc, toTy, val, mlir::Value{}, /*slice=*/mlir::Value{}); @@ -581,7 +582,7 @@ mlir::Value fir::FirOpBuilder::createBox(mlir::Location loc, bool isPolymorphic, bool isAssumedType) { mlir::Value itemAddr = fir::getBase(exv); - if (itemAddr.getType().isa()) + if (mlir::isa(itemAddr.getType())) return itemAddr; auto elementType = fir::dyn_cast_ptrEleTy(itemAddr.getType()); if (!elementType) { @@ -592,7 +593,7 @@ mlir::Value fir::FirOpBuilder::createBox(mlir::Location loc, mlir::Type boxTy; mlir::Value tdesc; // Avoid to wrap a box/class with box/class. - if (elementType.isa()) { + if (mlir::isa(elementType)) { boxTy = elementType; } else { boxTy = fir::BoxType::get(elementType); @@ -709,7 +710,7 @@ mlir::Value fir::FirOpBuilder::genAbsentOp(mlir::Location loc, return create(loc, argTy); auto boxProc = - create(loc, argTy.cast().getType(0)); + create(loc, mlir::cast(argTy).getType(0)); mlir::Value charLen = create(loc, getCharacterLengthType()); return fir::factory::createCharacterProcedureTuple(*this, loc, argTy, boxProc, charLen); @@ -958,14 +959,14 @@ static llvm::SmallVector getFromBox(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Type valTy, mlir::Value boxVal) { - if (auto boxTy = valTy.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(valTy)) { auto eleTy = fir::unwrapAllRefAndSeqType(boxTy.getEleTy()); - if (auto recTy = eleTy.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(eleTy)) { if (recTy.getNumLenParams() > 0) { // Walk each type parameter in the record and get the value. TODO(loc, "generate code to get LEN type parameters"); } - } else if (auto charTy = eleTy.dyn_cast()) { + } else if (auto charTy = mlir::dyn_cast(eleTy)) { if (charTy.hasDynamicLen()) { auto idxTy = builder.getIndexType(); auto eleSz = builder.create(loc, idxTy, boxVal); @@ -1012,7 +1013,7 @@ llvm::SmallVector fir::factory::getTypeParams(mlir::Location loc, fir::FirOpBuilder &builder, fir::ArrayLoadOp load) { mlir::Type memTy = load.getMemref().getType(); - if (auto boxTy = memTy.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(memTy)) return getFromBox(loc, builder, boxTy, load.getMemref()); return load.getTypeparams(); } @@ -1039,7 +1040,7 @@ std::string fir::factory::uniqueCGIdent(llvm::StringRef prefix, mlir::Value fir::factory::locationToFilename(fir::FirOpBuilder &builder, mlir::Location loc) { - if (auto flc = loc.dyn_cast()) { + if (auto flc = mlir::dyn_cast(loc)) { // must be encoded as asciiz, C string auto fn = flc.getFilename().str() + '\0'; return fir::getBase(createStringLiteral(builder, loc, fn)); @@ -1050,7 +1051,7 @@ mlir::Value fir::factory::locationToFilename(fir::FirOpBuilder &builder, mlir::Value fir::factory::locationToLineNo(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type type) { - if (auto flc = loc.dyn_cast()) + if (auto flc = mlir::dyn_cast(loc)) return builder.createIntegerConstant(loc, type, flc.getLine()); return builder.createIntegerConstant(loc, type, 0); } @@ -1108,10 +1109,10 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( auto fieldTy = component.getType(); if (auto ty = fir::dyn_cast_ptrEleTy(fieldTy)) fieldTy = ty; - if (fieldTy.isa()) { + if (mlir::isa(fieldTy)) { llvm::SmallVector nonDeferredTypeParams; auto eleTy = fir::unwrapSequenceType(fir::dyn_cast_ptrOrBoxEleTy(fieldTy)); - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { auto lenTy = builder.getCharacterLengthType(); if (charTy.hasConstantLen()) nonDeferredTypeParams.emplace_back( @@ -1120,7 +1121,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( // on a PDT length parameter. There is no way to make a difference with // deferred length here yet. } - if (auto recTy = eleTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(eleTy)) if (recTy.getNumLenParams() > 0) TODO(loc, "allocatable and pointer components non deferred length " "parameters"); @@ -1129,7 +1130,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( /*mutableProperties=*/{}); } llvm::SmallVector extents; - if (auto seqTy = fieldTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(fieldTy)) { fieldTy = seqTy.getEleTy(); auto idxTy = builder.getIndexType(); for (auto extent : seqTy.getShape()) { @@ -1138,7 +1139,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( extents.emplace_back(builder.createIntegerConstant(loc, idxTy, extent)); } } - if (auto charTy = fieldTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(fieldTy)) { auto cstLen = charTy.getLen(); if (cstLen == fir::CharacterType::unknownLen()) TODO(loc, "get character component length from length type parameters"); @@ -1148,7 +1149,7 @@ fir::ExtendedValue fir::factory::componentToExtendedValue( return fir::CharArrayBoxValue{component, len, extents}; return fir::CharBoxValue{component, len}; } - if (auto recordTy = fieldTy.dyn_cast()) + if (auto recordTy = mlir::dyn_cast(fieldTy)) if (recordTy.getNumLenParams() != 0) TODO(loc, "lower component ref that is a derived type with length parameter"); @@ -1211,14 +1212,14 @@ void fir::factory::genScalarAssignment(fir::FirOpBuilder &builder, assert(lhs.rank() == 0 && rhs.rank() == 0 && "must be scalars"); auto type = fir::unwrapSequenceType( fir::unwrapPassByRefType(fir::getBase(lhs).getType())); - if (type.isa()) { + if (mlir::isa(type)) { const fir::CharBoxValue *toChar = lhs.getCharBox(); const fir::CharBoxValue *fromChar = rhs.getCharBox(); assert(toChar && fromChar); fir::factory::CharacterExprHelper helper{builder, loc}; helper.createAssign(fir::ExtendedValue{*toChar}, fir::ExtendedValue{*fromChar}); - } else if (type.isa()) { + } else if (mlir::isa(type)) { fir::factory::genRecordAssignment(builder, loc, lhs, rhs, needFinalization, isTemporaryLHS); } else { @@ -1239,10 +1240,10 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, const fir::ExtendedValue &rhs, bool isTemporaryLHS) { auto lbaseType = fir::unwrapPassByRefType(fir::getBase(lhs).getType()); - auto lhsType = lbaseType.dyn_cast(); + auto lhsType = mlir::dyn_cast(lbaseType); assert(lhsType && "lhs must be a scalar record type"); auto rbaseType = fir::unwrapPassByRefType(fir::getBase(rhs).getType()); - auto rhsType = rbaseType.dyn_cast(); + auto rhsType = mlir::dyn_cast(rbaseType); assert(rhsType && "rhs must be a scalar record type"); auto fieldIndexType = fir::FieldType::get(lhsType.getContext()); for (auto [lhsPair, rhsPair] : @@ -1261,7 +1262,7 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, mlir::Value toCoor = builder.create( loc, fieldRefType, fir::getBase(lhs), field); std::optional outerLoop; - if (auto sequenceType = lFieldTy.dyn_cast()) { + if (auto sequenceType = mlir::dyn_cast(lFieldTy)) { // Create loops to assign array components elements by elements. // Note that, since these are components, they either do not overlap, // or are the same and exactly overlap. They also have compile time @@ -1288,10 +1289,9 @@ static void genComponentByComponentAssignment(fir::FirOpBuilder &builder, fromCoor, indices); } if (auto fieldEleTy = fir::unwrapSequenceType(lFieldTy); - fieldEleTy.isa()) { - assert(fieldEleTy.cast() - .getEleTy() - .isa() && + mlir::isa(fieldEleTy)) { + assert(mlir::isa( + mlir::cast(fieldEleTy).getEleTy()) && "allocatable members require deep copy"); auto fromPointerValue = builder.create(loc, fromCoor); auto castTo = builder.createConvert(loc, fieldEleTy, fromPointerValue); @@ -1320,11 +1320,11 @@ static bool recordTypeCanBeMemCopied(fir::RecordType recordType) { for (auto [_, fieldType] : recordType.getTypeList()) { // Derived type component may have user assignment (so far, we cannot tell // in FIR, so assume it is always the case, TODO: get the actual info). - if (fir::unwrapSequenceType(fieldType).isa()) + if (mlir::isa(fir::unwrapSequenceType(fieldType))) return false; // Allocatable components need deep copy. - if (auto boxType = fieldType.dyn_cast()) - if (boxType.getEleTy().isa()) + if (auto boxType = mlir::dyn_cast(fieldType)) + if (mlir::isa(boxType.getEleTy())) return false; } // Constant size components without user defined assignment and pointers can @@ -1353,9 +1353,10 @@ void fir::factory::genRecordAssignment(fir::FirOpBuilder &builder, // Box operands may be polymorphic, it is not entirely clear from 10.2.1.3 // if the assignment is performed on the dynamic of declared type. Use the // runtime assuming it is performed on the dynamic type. - bool hasBoxOperands = fir::getBase(lhs).getType().isa() || - fir::getBase(rhs).getType().isa(); - auto recTy = baseTy.dyn_cast(); + bool hasBoxOperands = + mlir::isa(fir::getBase(lhs).getType()) || + mlir::isa(fir::getBase(rhs).getType()); + auto recTy = mlir::dyn_cast(baseTy); assert(recTy && "must be a record type"); if ((needFinalization && mayHaveFinalizer(recTy, builder)) || hasBoxOperands || !recordTypeCanBeMemCopied(recTy)) { @@ -1401,7 +1402,7 @@ mlir::Value fir::factory::genLenOfCharacter( llvm::ArrayRef path, llvm::ArrayRef substring) { llvm::SmallVector typeParams(arrLoad.getTypeparams()); return genLenOfCharacter(builder, loc, - arrLoad.getType().cast(), + mlir::cast(arrLoad.getType()), arrLoad.getMemref(), typeParams, path, substring); } @@ -1429,7 +1430,7 @@ mlir::Value fir::factory::genLenOfCharacter( lower = builder.createConvert(loc, idxTy, substring.front()); auto eleTy = fir::applyPathToType(seqTy, path); if (!fir::hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { // Use LEN from the type. return builder.createIntegerConstant(loc, idxTy, charTy.getLen()); } @@ -1438,9 +1439,9 @@ mlir::Value fir::factory::genLenOfCharacter( "application of path did not result in a !fir.char"); } if (fir::isa_box_type(memref.getType())) { - if (memref.getType().isa()) + if (mlir::isa(memref.getType())) return builder.create(loc, idxTy, memref); - if (memref.getType().isa()) + if (mlir::isa(memref.getType())) return CharacterExprHelper(builder, loc).readLengthFromBox(memref); fir::emitFatalError(loc, "memref has wrong type"); } @@ -1457,7 +1458,7 @@ mlir::Value fir::factory::genLenOfCharacter( mlir::Value fir::factory::createZeroValue(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type type) { mlir::Type i1 = builder.getIntegerType(1); - if (type.isa() || type == i1) + if (mlir::isa(type) || type == i1) return builder.createConvert(loc, type, builder.createBool(loc, false)); if (fir::isa_integer(type)) return builder.createIntegerConstant(loc, type, 0); @@ -1507,7 +1508,7 @@ mlir::Value fir::factory::genMaxWithZero(fir::FirOpBuilder &builder, mlir::Value zero = builder.createIntegerConstant(loc, value.getType(), 0); if (mlir::Operation *definingOp = value.getDefiningOp()) if (auto cst = mlir::dyn_cast(definingOp)) - if (auto intAttr = cst.getValue().dyn_cast()) + if (auto intAttr = mlir::dyn_cast(cst.getValue())) return intAttr.getInt() > 0 ? value : zero; mlir::Value valueIsGreater = builder.create( loc, mlir::arith::CmpIPredicate::sgt, value, zero); @@ -1519,8 +1520,8 @@ mlir::Value fir::factory::genCPtrOrCFunptrAddr(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value cPtr, mlir::Type ty) { - assert(ty.isa()); - auto recTy = ty.dyn_cast(); + assert(mlir::isa(ty)); + auto recTy = mlir::dyn_cast(ty); assert(recTy.getTypeList().size() == 1); auto fieldName = recTy.getTypeList()[0].first; mlir::Type fieldTy = recTy.getTypeList()[0].second; @@ -1582,7 +1583,7 @@ mlir::Value fir::factory::genCPtrOrCFunptrValue(fir::FirOpBuilder &builder, mlir::Value fir::factory::createNullBoxProc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type boxType) { - auto boxTy{boxType.dyn_cast()}; + auto boxTy{mlir::dyn_cast(boxType)}; if (!boxTy) fir::emitFatalError(loc, "Procedure pointer must be of BoxProcType"); auto boxEleTy{fir::unwrapRefType(boxTy.getEleTy())}; diff --git a/flang/lib/Optimizer/Builder/HLFIRTools.cpp b/flang/lib/Optimizer/Builder/HLFIRTools.cpp index db638ceb4070..44779427ab55 100644 --- a/flang/lib/Optimizer/Builder/HLFIRTools.cpp +++ b/flang/lib/Optimizer/Builder/HLFIRTools.cpp @@ -38,10 +38,10 @@ hlfir::getExplicitExtentsFromShape(mlir::Value shape, } else if (mlir::dyn_cast_or_null(shapeOp)) { return {}; } else if (auto s = mlir::dyn_cast_or_null(shapeOp)) { - hlfir::ExprType expr = s.getExpr().getType().cast(); + hlfir::ExprType expr = mlir::cast(s.getExpr().getType()); llvm::ArrayRef exprShape = expr.getShape(); mlir::Type indexTy = builder.getIndexType(); - fir::ShapeType shapeTy = shape.getType().cast(); + fir::ShapeType shapeTy = mlir::cast(shape.getType()); result.reserve(shapeTy.getRank()); for (unsigned i = 0; i < shapeTy.getRank(); ++i) { int64_t extent = exprShape[i]; @@ -99,7 +99,7 @@ genLboundsAndExtentsFromBox(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity boxEntity, llvm::SmallVectorImpl &lbounds, llvm::SmallVectorImpl *extents) { - assert(boxEntity.getType().isa() && "must be a box"); + assert(mlir::isa(boxEntity.getType()) && "must be a box"); mlir::Type idxTy = builder.getIndexType(); const int rank = boxEntity.getRank(); for (int i = 0; i < rank; ++i) { @@ -154,7 +154,7 @@ static mlir::Value genCharacterVariableLength(mlir::Location loc, hlfir::Entity var) { if (mlir::Value len = tryGettingNonDeferredCharLen(var)) return len; - auto charType = var.getFortranElementType().cast(); + auto charType = mlir::cast(var.getFortranElementType()); if (charType.hasConstantLen()) return builder.createIntegerConstant(loc, builder.getIndexType(), charType.getLen()); @@ -172,7 +172,7 @@ static fir::CharBoxValue genUnboxChar(mlir::Location loc, if (auto emboxChar = boxChar.getDefiningOp()) return {emboxChar.getMemref(), emboxChar.getLen()}; mlir::Type refType = fir::ReferenceType::get( - boxChar.getType().cast().getEleTy()); + mlir::cast(boxChar.getType()).getEleTy()); auto unboxed = builder.create( loc, refType, builder.getIndexType(), boxChar); mlir::Value addr = unboxed.getResult(0); @@ -252,8 +252,8 @@ hlfir::genAssociateExpr(mlir::Location loc, fir::FirOpBuilder &builder, // and the other static). mlir::Type varEleTy = getFortranElementType(variableType); mlir::Type valueEleTy = getFortranElementType(value.getType()); - if (varEleTy != valueEleTy && !(valueEleTy.isa() && - varEleTy.isa())) { + if (varEleTy != valueEleTy && !(mlir::isa(valueEleTy) && + mlir::isa(varEleTy))) { assert(value.isScalar() && fir::isa_trivial(value.getType())); source = builder.createConvert(loc, fir::unwrapPassByRefType(variableType), value); @@ -278,9 +278,9 @@ mlir::Value hlfir::genVariableRawAddress(mlir::Location loc, if (var.isMutableBox()) baseAddr = builder.create(loc, baseAddr); // Get raw address. - if (var.getType().isa()) + if (mlir::isa(var.getType())) baseAddr = genUnboxChar(loc, builder, var.getBase()).getAddr(); - if (baseAddr.getType().isa()) + if (mlir::isa(baseAddr.getType())) baseAddr = builder.create(loc, baseAddr); return baseAddr; } @@ -289,13 +289,13 @@ mlir::Value hlfir::genVariableBoxChar(mlir::Location loc, fir::FirOpBuilder &builder, hlfir::Entity var) { assert(var.isVariable() && "only address of variables can be taken"); - if (var.getType().isa()) + if (mlir::isa(var.getType())) return var; mlir::Value addr = genVariableRawAddress(loc, builder, var); llvm::SmallVector lengths; genLengthParameters(loc, builder, var, lengths); assert(lengths.size() == 1); - auto charType = var.getFortranElementType().cast(); + auto charType = mlir::cast(var.getFortranElementType()); auto boxCharType = fir::BoxCharType::get(builder.getContext(), charType.getFKind()); auto scalarAddr = @@ -309,7 +309,7 @@ hlfir::Entity hlfir::genVariableBox(mlir::Location loc, hlfir::Entity var) { assert(var.isVariable() && "must be a variable"); var = hlfir::derefPointersAndAllocatables(loc, builder, var); - if (var.getType().isa()) + if (mlir::isa(var.getType())) return var; // Note: if the var is not a fir.box/fir.class at that point, it has default // lower bounds and is not polymorphic. @@ -317,11 +317,11 @@ hlfir::Entity hlfir::genVariableBox(mlir::Location loc, var.isArray() ? hlfir::genShape(loc, builder, var) : mlir::Value{}; llvm::SmallVector typeParams; auto maybeCharType = - var.getFortranElementType().dyn_cast(); + mlir::dyn_cast(var.getFortranElementType()); if (!maybeCharType || maybeCharType.hasDynamicLen()) hlfir::genLengthParameters(loc, builder, var, typeParams); mlir::Value addr = var.getBase(); - if (var.getType().isa()) + if (mlir::isa(var.getType())) addr = genVariableRawAddress(loc, builder, var); mlir::Type boxType = fir::BoxType::get(var.getElementOrSequenceType()); auto embox = @@ -348,7 +348,7 @@ hlfir::Entity hlfir::getElementAt(mlir::Location loc, return entity; llvm::SmallVector lenParams; genLengthParameters(loc, builder, entity, lenParams); - if (entity.getType().isa()) + if (mlir::isa(entity.getType())) return hlfir::Entity{builder.create( loc, entity, oneBasedIndices, lenParams)}; // Build hlfir.designate. The lower bounds may need to be added to @@ -394,7 +394,7 @@ static mlir::Value genUBound(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVector> hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, Entity entity) { - if (entity.getType().isa()) + if (mlir::isa(entity.getType())) TODO(loc, "bounds of expressions in hlfir"); auto [exv, cleanup] = translateToExtendedValue(loc, builder, entity); assert(!cleanup && "translation of entity should not yield cleanup"); @@ -415,8 +415,8 @@ hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVector> hlfir::genBounds(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value shape) { - assert((shape.getType().isa() || - shape.getType().isa()) && + assert((mlir::isa(shape.getType()) || + mlir::isa(shape.getType())) && "shape must contain extents"); auto extents = hlfir::getExplicitExtentsFromShape(shape, builder); auto lowers = getExplicitLboundsFromShape(shape); @@ -474,7 +474,7 @@ static mlir::Value computeVariableExtent(mlir::Location loc, if (typeExtent != fir::SequenceType::getUnknownExtent()) return builder.createIntegerConstant(loc, idxTy, typeExtent); } - assert(variable.getType().isa() && + assert(mlir::isa(variable.getType()) && "array variable with dynamic extent must be boxed"); mlir::Value dimVal = builder.createIntegerConstant(loc, idxTy, dim); auto dimInfo = builder.create(loc, idxTy, idxTy, idxTy, @@ -496,9 +496,8 @@ llvm::SmallVector getVariableExtents(mlir::Location loc, variable = hlfir::derefPointersAndAllocatables(loc, builder, variable); // Use the type shape information, and/or the fir.box/fir.class shape // information if any extents are not static. - fir::SequenceType seqTy = - hlfir::getFortranElementOrSequenceType(variable.getType()) - .cast(); + fir::SequenceType seqTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(variable.getType())); unsigned rank = seqTy.getShape().size(); for (unsigned dim = 0; dim < rank; ++dim) extents.push_back( @@ -507,7 +506,7 @@ llvm::SmallVector getVariableExtents(mlir::Location loc, } static mlir::Value tryRetrievingShapeOrShift(hlfir::Entity entity) { - if (entity.getType().isa()) { + if (mlir::isa(entity.getType())) { if (auto elemental = entity.getDefiningOp()) return elemental.getShape(); return mlir::Value{}; @@ -523,13 +522,13 @@ mlir::Value hlfir::genShape(mlir::Location loc, fir::FirOpBuilder &builder, entity = followShapeInducingSource(entity); assert(entity && "what?"); if (auto shape = tryRetrievingShapeOrShift(entity)) { - if (shape.getType().isa()) + if (mlir::isa(shape.getType())) return shape; - if (shape.getType().isa()) + if (mlir::isa(shape.getType())) if (auto s = shape.getDefiningOp()) return builder.create(loc, s.getExtents()); } - if (entity.getType().isa()) + if (mlir::isa(entity.getType())) return builder.create(loc, entity.getBase()); // There is no shape lying around for this entity. Retrieve the extents and // build a new fir.shape. @@ -563,9 +562,8 @@ mlir::Value hlfir::genExtent(mlir::Location loc, fir::FirOpBuilder &builder, entity = hlfir::derefPointersAndAllocatables(loc, builder, entity); // Use the type shape information, and/or the fir.box/fir.class shape // information if any extents are not static. - fir::SequenceType seqTy = - hlfir::getFortranElementOrSequenceType(entity.getType()) - .cast(); + fir::SequenceType seqTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(entity.getType())); return computeVariableExtent(loc, builder, entity, seqTy, dim); } TODO(loc, "get extent from HLFIR expr without producer holding the shape"); @@ -584,7 +582,7 @@ mlir::Value hlfir::genLBound(mlir::Location loc, fir::FirOpBuilder &builder, } if (entity.isMutableBox()) entity = hlfir::derefPointersAndAllocatables(loc, builder, entity); - assert(entity.getType().isa() && "must be a box"); + assert(mlir::isa(entity.getType()) && "must be a box"); mlir::Type idxTy = builder.getIndexType(); mlir::Value dimVal = builder.createIntegerConstant(loc, idxTy, dim); auto dimInfo = @@ -597,7 +595,7 @@ void hlfir::genLengthParameters(mlir::Location loc, fir::FirOpBuilder &builder, llvm::SmallVectorImpl &result) { if (!entity.hasLengthParameters()) return; - if (entity.getType().isa()) { + if (mlir::isa(entity.getType())) { mlir::Value expr = entity; if (auto reassoc = expr.getDefiningOp()) expr = reassoc.getVal(); @@ -654,8 +652,8 @@ static mlir::Value asEmboxShape(mlir::Location loc, fir::FirOpBuilder &builder, // fir.shape_shift) since this information is already in the input fir.box, // it only accepts fir.shift because local lower bounds may not be reflected // in the fir.box. - if (fir::getBase(exv).getType().isa() && - !shape.getType().isa()) + if (mlir::isa(fir::getBase(exv).getType()) && + !mlir::isa(shape.getType())) return builder.createShape(loc, exv); return shape; } @@ -686,7 +684,7 @@ hlfir::Entity hlfir::derefPointersAndAllocatables(mlir::Location loc, if (!entity.isPolymorphic() && !entity.hasLengthParameters()) return hlfir::Entity{builder.create(loc, boxLoad)}; mlir::Type elementType = boxLoad.getFortranElementType(); - if (auto charType = elementType.dyn_cast()) { + if (auto charType = mlir::dyn_cast(elementType)) { mlir::Value base = builder.create(loc, boxLoad); if (charType.hasConstantLen()) return hlfir::Entity{base}; @@ -716,7 +714,7 @@ mlir::Type hlfir::getVariableElementType(hlfir::Entity variable) { mlir::Type eleTy = variable.getFortranElementType(); if (variable.isPolymorphic()) return fir::ClassType::get(eleTy); - if (auto charType = eleTy.dyn_cast()) { + if (auto charType = mlir::dyn_cast(eleTy)) { if (charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); } else if (fir::isRecordWithTypeParameters(eleTy)) { @@ -737,7 +735,7 @@ mlir::Type hlfir::getEntityElementType(hlfir::Entity entity) { static hlfir::ExprType getArrayExprType(mlir::Type elementType, mlir::Value shape, bool isPolymorphic) { - unsigned rank = shape.getType().cast().getRank(); + unsigned rank = mlir::cast(shape.getType()).getRank(); hlfir::ExprType::Shape typeShape(rank, hlfir::ExprType::getUnknownExtent()); if (auto shapeOp = shape.getDefiningOp()) for (auto extent : llvm::enumerate(shapeOp.getExtents())) @@ -859,7 +857,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, return fir::MutableBoxValue(base, getExplicitTypeParams(variable), fir::MutableProperties{}); - if (base.getType().isa()) { + if (mlir::isa(base.getType())) { if (!variable.isSimplyContiguous() || variable.isPolymorphic() || variable.isDerivedWithLengthParameters() || variable.isOptional()) { llvm::SmallVector nonDefaultLbounds = @@ -874,7 +872,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, if (variable.isScalar()) { if (variable.isCharacter()) { - if (base.getType().isa()) + if (mlir::isa(base.getType())) return genUnboxChar(loc, builder, base); mlir::Value len = genCharacterVariableLength(loc, builder, variable); return fir::CharBoxValue{base, len}; @@ -883,7 +881,7 @@ translateVariableToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, } llvm::SmallVector extents; llvm::SmallVector nonDefaultLbounds; - if (variable.getType().isa() && + if (mlir::isa(variable.getType()) && !variable.getIfVariableInterface()) { // This special case avoids generating two sets of identical // fir.box_dim to get both the lower bounds and extents. @@ -923,7 +921,7 @@ hlfir::translateToExtendedValue(mlir::Location loc, fir::FirOpBuilder &builder, return {static_cast(entity), std::nullopt}; } - if (entity.getType().isa()) { + if (mlir::isa(entity.getType())) { mlir::NamedAttribute byRefAttr = fir::getAdaptToByRefAttr(builder); hlfir::AssociateOp associate = hlfir::genAssociateExpr( loc, builder, entity, entity.getType(), "", byRefAttr); diff --git a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp index e28d14cd318d..9d72e76e2369 100644 --- a/flang/lib/Optimizer/Builder/IntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/IntrinsicCall.cpp @@ -786,7 +786,7 @@ mlir::Value genLibSplitComplexArgsCall(fir::FirOpBuilder &builder, auto getSplitComplexArgsType = [&builder, &args]() -> mlir::FunctionType { mlir::Type ctype = args[0].getType(); - auto fKind = ctype.cast().getFKind(); + auto fKind = mlir::cast(ctype).getFKind(); mlir::Type ftype; if (fKind == 2) @@ -894,8 +894,8 @@ mlir::Value genComplexMathOp(fir::FirOpBuilder &builder, mlir::Location loc, LLVM_DEBUG(llvm::dbgs() << "Generating '" << mathLibFuncName << "' operation with type "; mathLibFuncType.dump(); llvm::dbgs() << "\n"); - auto type = mathLibFuncType.getInput(0).cast(); - auto kind = type.getElementType().cast().getFKind(); + auto type = mlir::cast(mathLibFuncType.getInput(0)); + auto kind = mlir::cast(type.getElementType()).getFKind(); auto realTy = builder.getRealType(kind); auto mComplexTy = mlir::ComplexType::get(realTy); @@ -1394,14 +1394,14 @@ private: // Floating point can be mlir::FloatType or fir::real static unsigned getFloatingPointWidth(mlir::Type t) { - if (auto f{t.dyn_cast()}) + if (auto f{mlir::dyn_cast(t)}) return f.getWidth(); // FIXME: Get width another way for fir.real/complex // - use fir/KindMapping.h and llvm::Type // - or use evaluate/type.h - if (auto r{t.dyn_cast()}) + if (auto r{mlir::dyn_cast(t)}) return r.getFKind() * 4; - if (auto cplx{t.dyn_cast()}) + if (auto cplx{mlir::dyn_cast(t)}) return cplx.getFKind() * 4; llvm_unreachable("not a floating-point type"); } @@ -1410,8 +1410,8 @@ private: if (from == to) return Conversion::None; - if (auto fromIntTy{from.dyn_cast()}) { - if (auto toIntTy{to.dyn_cast()}) { + if (auto fromIntTy{mlir::dyn_cast(from)}) { + if (auto toIntTy{mlir::dyn_cast(to)}) { return fromIntTy.getWidth() > toIntTy.getWidth() ? Conversion::Narrow : Conversion::Extend; } @@ -1423,8 +1423,8 @@ private: : Conversion::Extend; } - if (auto fromCplxTy{from.dyn_cast()}) { - if (auto toCplxTy{to.dyn_cast()}) { + if (auto fromCplxTy{mlir::dyn_cast(from)}) { + if (auto toCplxTy{mlir::dyn_cast(to)}) { return getFloatingPointWidth(fromCplxTy) > getFloatingPointWidth(toCplxTy) ? Conversion::Narrow @@ -1550,10 +1550,10 @@ fir::ExtendedValue toExtendedValue(mlir::Value val, fir::FirOpBuilder &builder, if (charHelper.isCharacterScalar(type)) return charHelper.toExtendedValue(val); - if (auto refType = type.dyn_cast()) + if (auto refType = mlir::dyn_cast(type)) type = refType.getEleTy(); - if (auto arrayType = type.dyn_cast()) { + if (auto arrayType = mlir::dyn_cast(type)) { type = arrayType.getEleTy(); for (fir::SequenceType::Extent extent : arrayType.getShape()) { if (extent == fir::SequenceType::getUnknownExtent()) @@ -1566,7 +1566,8 @@ fir::ExtendedValue toExtendedValue(mlir::Value val, fir::FirOpBuilder &builder, // have been used in the interface). if (extents.size() + 1 < arrayType.getShape().size()) mlir::emitError(loc, "cannot retrieve array extents from type"); - } else if (type.isa() || type.isa()) { + } else if (mlir::isa(type) || + mlir::isa(type)) { fir::emitFatalError(loc, "not yet implemented: descriptor or derived type"); } @@ -1580,10 +1581,10 @@ mlir::Value toValue(const fir::ExtendedValue &val, fir::FirOpBuilder &builder, if (const fir::CharBoxValue *charBox = val.getCharBox()) { mlir::Value buffer = charBox->getBuffer(); auto buffTy = buffer.getType(); - if (buffTy.isa()) + if (mlir::isa(buffTy)) fir::emitFatalError( loc, "A character's buffer type cannot be a function type."); - if (buffTy.isa()) + if (mlir::isa(buffTy)) return buffer; return fir::factory::CharacterExprHelper{builder, loc}.createEmboxChar( buffer, charBox->getLen()); @@ -1827,27 +1828,27 @@ IntrinsicLibrary::invokeGenerator(SubroutineGenerator generator, /// Note: mlir has Type::dump(ostream) methods but it may add "!" that is not /// suitable for function names. static std::string typeToString(mlir::Type t) { - if (auto refT{t.dyn_cast()}) + if (auto refT{mlir::dyn_cast(t)}) return "ref_" + typeToString(refT.getEleTy()); - if (auto i{t.dyn_cast()}) { + if (auto i{mlir::dyn_cast(t)}) { return "i" + std::to_string(i.getWidth()); } - if (auto cplx{t.dyn_cast()}) { + if (auto cplx{mlir::dyn_cast(t)}) { return "z" + std::to_string(cplx.getFKind()); } - if (auto real{t.dyn_cast()}) { + if (auto real{mlir::dyn_cast(t)}) { return "r" + std::to_string(real.getFKind()); } - if (auto f{t.dyn_cast()}) { + if (auto f{mlir::dyn_cast(t)}) { return "f" + std::to_string(f.getWidth()); } - if (auto logical{t.dyn_cast()}) { + if (auto logical{mlir::dyn_cast(t)}) { return "l" + std::to_string(logical.getFKind()); } - if (auto character{t.dyn_cast()}) { + if (auto character{mlir::dyn_cast(t)}) { return "c" + std::to_string(character.getFKind()); } - if (auto boxCharacter{t.dyn_cast()}) { + if (auto boxCharacter{mlir::dyn_cast(t)}) { return "bc" + std::to_string(boxCharacter.getEleTy().getFKind()); } llvm_unreachable("no mangling for type"); @@ -1907,7 +1908,7 @@ mlir::func::FuncOp IntrinsicLibrary::getWrapper(GeneratorType generator, mlir::Location localLoc = localBuilder->getUnknownLoc(); llvm::SmallVector localArguments; for (mlir::BlockArgument bArg : function.front().getArguments()) { - auto refType = bArg.getType().dyn_cast(); + auto refType = mlir::dyn_cast(bArg.getType()); if (loadRefArguments && refType) { auto loaded = localBuilder->create(localLoc, bArg); localArguments.push_back(loaded); @@ -2060,7 +2061,7 @@ mlir::SymbolRefAttr IntrinsicLibrary::getUnrestrictedIntrinsicSymbolRefAttr( if (!funcOp) { llvm::SmallVector argTypes; for (mlir::Type type : signature.getInputs()) { - if (auto refType = type.dyn_cast()) + if (auto refType = mlir::dyn_cast(type)) argTypes.push_back(refType.getEleTy()); else argTypes.push_back(type); @@ -2145,7 +2146,7 @@ mlir::Value IntrinsicLibrary::genAbs(mlir::Type resultType, // math::AbsFOp but it does not support all fir floating point types. return genRuntimeCall("abs", resultType, args); } - if (auto intType = type.dyn_cast()) { + if (auto intType = mlir::dyn_cast(type)) { // At the time of this implementation there is no abs op in mlir. // So, implement abs here without branching. mlir::Value shift = @@ -2379,8 +2380,8 @@ IntrinsicLibrary::genAssociated(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); mlir::Type ptrTy = fir::getBase(args[0]).getType(); - if (ptrTy && - (fir::isBoxProcAddressType(ptrTy) || ptrTy.isa())) { + if (ptrTy && (fir::isBoxProcAddressType(ptrTy) || + mlir::isa(ptrTy))) { mlir::Value pointerBoxProc = fir::isBoxProcAddressType(ptrTy) ? builder.create(loc, fir::getBase(args[0])) @@ -2392,7 +2393,7 @@ IntrinsicLibrary::genAssociated(mlir::Type resultType, mlir::Value target = fir::getBase(args[1]); if (fir::isBoxProcAddressType(target.getType())) target = builder.create(loc, target); - if (target.getType().isa()) + if (mlir::isa(target.getType())) target = builder.create(loc, target); mlir::Type intPtrTy = builder.getIntPtrType(); mlir::Value pointerInt = @@ -2649,7 +2650,7 @@ static mlir::Value getAddrFromBox(fir::FirOpBuilder &builder, mlir::Value argValue = fir::getBase(arg); mlir::Value addr{nullptr}; if (isFunc) { - auto funcTy = argValue.getType().cast().getEleTy(); + auto funcTy = mlir::cast(argValue.getType()).getEleTy(); addr = builder.create(loc, funcTy, argValue); } else { const auto *box = arg.getBoxOf(); @@ -3029,7 +3030,7 @@ void IntrinsicLibrary::genDateAndTime(llvm::ArrayRef args) { mlir::Value IntrinsicLibrary::genDim(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (resultType.isa()) { + if (mlir::isa(resultType)) { mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); auto diff = builder.create(loc, args[0], args[1]); auto cmp = builder.create( @@ -3574,7 +3575,7 @@ IntrinsicLibrary::genReduction(FN func, FD funcDim, llvm::StringRef errMsg, if (absentDim || rank == 1) { mlir::Type ty = array.getType(); mlir::Type arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); if (fir::isa_complex(eleTy)) { mlir::Value result = builder.createTemporary(loc, eleTy); func(builder, loc, array, mask, result); @@ -3646,7 +3647,7 @@ mlir::Value IntrinsicLibrary::genIbits(mlir::Type resultType, mlir::Value pos = builder.createConvert(loc, resultType, args[1]); mlir::Value len = builder.createConvert(loc, resultType, args[2]); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); auto shiftCount = builder.create(loc, bitSize, len); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value ones = builder.createAllOnesInteger(loc, resultType); @@ -3686,7 +3687,7 @@ IntrinsicLibrary::genIchar(mlir::Type resultType, mlir::Value buffer = charBox->getBuffer(); mlir::Type bufferTy = buffer.getType(); mlir::Value charVal; - if (auto charTy = bufferTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(bufferTy)) { assert(charTy.singleton()); charVal = buffer; } else { @@ -3759,7 +3760,7 @@ void IntrinsicLibrary::genRaiseExcept(int except, mlir::Value cond) { static std::pair getFieldRef(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value rec) { auto recType = - fir::unwrapPassByRefType(rec.getType()).dyn_cast(); + mlir::dyn_cast(fir::unwrapPassByRefType(rec.getType())); assert(recType.getTypeList().size() == 1 && "expected exactly one component"); auto [fieldName, fieldTy] = recType.getTypeList().front(); mlir::Value field = builder.create( @@ -3808,7 +3809,7 @@ mlir::Value IntrinsicLibrary::genIeeeClass(mlir::Type resultType, assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = realVal.getType().dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); const unsigned intWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(intWidth); mlir::Value intVal = @@ -4056,8 +4057,10 @@ IntrinsicLibrary::genIeeeCopySign(mlir::Type resultType, assert(args.size() == 2); mlir::Value xRealVal = args[0]; mlir::Value yRealVal = args[1]; - mlir::FloatType xRealType = xRealVal.getType().dyn_cast(); - mlir::FloatType yRealType = yRealVal.getType().dyn_cast(); + mlir::FloatType xRealType = + mlir::dyn_cast(xRealVal.getType()); + mlir::FloatType yRealType = + mlir::dyn_cast(yRealVal.getType()); if (yRealType == mlir::FloatType::getBF16(builder.getContext())) { // Workaround: CopySignOp and BitcastOp don't work for kind 3 arg Y. @@ -4106,7 +4109,7 @@ void IntrinsicLibrary::genIeeeGetFlag(llvm::ArrayRef args) { mlir::Value flag = fir::getBase(args[0]); mlir::Value flagValue = fir::getBase(args[1]); mlir::Type resultTy = - flagValue.getType().dyn_cast().getEleTy(); + mlir::dyn_cast(flagValue.getType()).getEleTy(); mlir::Type i32Ty = builder.getIntegerType(32); mlir::Value zero = builder.createIntegerConstant(loc, i32Ty, 0); auto [fieldRef, ignore] = getFieldRef(builder, loc, flag); @@ -4130,7 +4133,7 @@ void IntrinsicLibrary::genIeeeGetHaltingMode( mlir::Value flag = fir::getBase(args[0]); mlir::Value halting = fir::getBase(args[1]); mlir::Type resultTy = - halting.getType().dyn_cast().getEleTy(); + mlir::dyn_cast(halting.getType()).getEleTy(); mlir::Type i32Ty = builder.getIntegerType(32); mlir::Value zero = builder.createIntegerConstant(loc, i32Ty, 0); auto [fieldRef, ignore] = getFieldRef(builder, loc, flag); @@ -4248,7 +4251,7 @@ mlir::Value IntrinsicLibrary::genIeeeLogb(mlir::Type resultType, // : ieee_copy_sign(X, 1.0) // +infinity or NaN assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = realVal.getType().dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); int bitWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(realType.getWidth()); mlir::Value intVal = @@ -4545,7 +4548,7 @@ mlir::Value IntrinsicLibrary::genIeeeSignbit(mlir::Type resultType, // Check if the sign bit of arg X is set. assert(args.size() == 1); mlir::Value realVal = args[0]; - mlir::FloatType realType = realVal.getType().dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(realVal.getType()); int bitWidth = realType.getWidth(); if (realType == mlir::FloatType::getBF16(builder.getContext())) { // Workaround: can't bitcast or convert real(3) to integer(2) or real(2). @@ -4642,7 +4645,7 @@ mlir::Value IntrinsicLibrary::genIeeeValue(mlir::Type resultType, // A compiler generated call has one argument: // - arg[0] is an index constant assert(args.size() == 1 || args.size() == 2); - mlir::FloatType realType = resultType.dyn_cast(); + mlir::FloatType realType = mlir::dyn_cast(resultType); int bitWidth = realType.getWidth(); mlir::Type intType = builder.getIntegerType(bitWidth); mlir::Type valueTy = bitWidth <= 64 ? intType : builder.getIntegerType(64); @@ -4884,7 +4887,7 @@ mlir::Value IntrinsicLibrary::genIshft(mlir::Type resultType, // : I << abs(SHIFT) assert(args.size() == 2); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value shift = builder.createConvert(loc, resultType, args[1]); mlir::Value absShift = genAbs(resultType, {shift}); @@ -4920,7 +4923,7 @@ mlir::Value IntrinsicLibrary::genIshftc(mlir::Type resultType, // Return: SHIFT == 0 || SIZE == abs(SHIFT) ? I : (unchanged | left | right) assert(args.size() == 3); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); mlir::Value I = args[0]; mlir::Value shift = builder.createConvert(loc, resultType, args[1]); mlir::Value size = @@ -5027,7 +5030,7 @@ IntrinsicLibrary::genLoc(mlir::Type resultType, mlir::Value box = fir::getBase(args[0]); assert(fir::isa_box_type(box.getType()) && "argument must have been lowered to box type"); - bool isFunc = box.getType().isa(); + bool isFunc = mlir::isa(box.getType()); if (!isOptional(box)) { mlir::Value argAddr = getAddrFromBox(builder, loc, args[0], isFunc); return builder.createConvert(loc, resultType, argAddr); @@ -5156,7 +5159,7 @@ IntrinsicLibrary::genMerge(mlir::Type, auto convertToStaticType = [&](mlir::Value polymorphic, mlir::Value other) -> mlir::Value { mlir::Type otherType = other.getType(); - if (otherType.isa()) + if (mlir::isa(otherType)) return builder.create(loc, otherType, polymorphic, /*shape*/ mlir::Value{}, /*slice=*/mlir::Value{}); @@ -5209,7 +5212,7 @@ mlir::Value IntrinsicLibrary::genMergeBits(mlir::Type resultType, mlir::Value IntrinsicLibrary::genMod(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (resultType.isa()) + if (mlir::isa(resultType)) return builder.create(loc, args[0], args[1]); // Use runtime. @@ -5231,7 +5234,7 @@ mlir::Value IntrinsicLibrary::genModulo(mlir::Type resultType, // - Otherwise, when A/P < 0 and MOD(A,P) !=0, then MODULO(A, P) = // A-FLOOR(A/P)*P = A-(INT(A/P)-1)*P = A-INT(A/P)*P+P = MOD(A,P)+P // Note that A/P < 0 if and only if A and P signs are different. - if (resultType.isa()) { + if (mlir::isa(resultType)) { auto remainder = builder.create(loc, args[0], args[1]); auto argXor = builder.create(loc, args[0], args[1]); @@ -5344,7 +5347,7 @@ void IntrinsicLibrary::genMvbits(llvm::ArrayRef args) { mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); mlir::Value ones = builder.createAllOnesInteger(loc, resultType); mlir::Value bitSize = builder.createIntegerConstant( - loc, resultType, resultType.cast().getWidth()); + loc, resultType, mlir::cast(resultType).getWidth()); auto shiftCount = builder.create(loc, bitSize, len); auto mask = builder.create(loc, ones, shiftCount); auto unchangedTmp1 = builder.create(loc, mask, topos); @@ -5628,7 +5631,7 @@ IntrinsicLibrary::genReshape(mlir::Type resultType, assert(fir::BoxValue(shape).rank() == 1); mlir::Type shapeTy = shape.getType(); mlir::Type shapeArrTy = fir::dyn_cast_ptrOrBoxEleTy(shapeTy); - auto resultRank = shapeArrTy.cast().getShape()[0]; + auto resultRank = mlir::cast(shapeArrTy).getShape()[0]; if (resultRank == fir::SequenceType::getUnknownExtent()) TODO(loc, "intrinsic: reshape requires computing rank of result"); @@ -5921,7 +5924,7 @@ void IntrinsicLibrary::genSignalSubroutine( mlir::Value IntrinsicLibrary::genSign(mlir::Type resultType, llvm::ArrayRef args) { assert(args.size() == 2); - if (resultType.isa()) { + if (mlir::isa(resultType)) { mlir::Value abs = genAbs(resultType, {args[0]}); mlir::Value zero = builder.createIntegerConstant(loc, resultType, 0); auto neg = builder.create(loc, zero, abs); diff --git a/flang/lib/Optimizer/Builder/MutableBox.cpp b/flang/lib/Optimizer/Builder/MutableBox.cpp index d4012e9c3d9d..76b920dba869 100644 --- a/flang/lib/Optimizer/Builder/MutableBox.cpp +++ b/flang/lib/Optimizer/Builder/MutableBox.cpp @@ -28,7 +28,7 @@ createNewFirBox(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, mlir::Value addr, mlir::ValueRange lbounds, mlir::ValueRange extents, mlir::ValueRange lengths, mlir::Value tdesc = {}) { - if (addr.getType().isa()) + if (mlir::isa(addr.getType())) // The entity is already boxed. return builder.createConvert(loc, box.getBoxTy(), addr); @@ -53,20 +53,21 @@ createNewFirBox(fir::FirOpBuilder &builder, mlir::Location loc, // error in the embox). llvm::SmallVector cleanedLengths; auto cleanedAddr = addr; - if (auto charTy = box.getEleTy().dyn_cast()) { + if (auto charTy = mlir::dyn_cast(box.getEleTy())) { // Cast address to box type so that both input and output type have // unknown or constant lengths. auto bt = box.getBaseTy(); auto addrTy = addr.getType(); - auto type = addrTy.isa() ? fir::HeapType::get(bt) - : addrTy.isa() ? fir::PointerType::get(bt) - : builder.getRefType(bt); + auto type = mlir::isa(addrTy) ? fir::HeapType::get(bt) + : mlir::isa(addrTy) + ? fir::PointerType::get(bt) + : builder.getRefType(bt); cleanedAddr = builder.createConvert(loc, type, addr); if (charTy.getLen() == fir::CharacterType::unknownLen()) cleanedLengths.append(lengths.begin(), lengths.end()); } else if (fir::isUnlimitedPolymorphicType(box.getBoxTy())) { - if (auto charTy = fir::dyn_cast_ptrEleTy(addr.getType()) - .dyn_cast()) { + if (auto charTy = mlir::dyn_cast( + fir::dyn_cast_ptrEleTy(addr.getType()))) { if (charTy.getLen() == fir::CharacterType::unknownLen()) cleanedLengths.append(lengths.begin(), lengths.end()); } @@ -328,18 +329,18 @@ private: mlir::Value fir::factory::createUnallocatedBox( fir::FirOpBuilder &builder, mlir::Location loc, mlir::Type boxType, mlir::ValueRange nonDeferredParams, mlir::Value typeSourceBox) { - auto baseAddrType = boxType.dyn_cast().getEleTy(); + auto baseAddrType = mlir::dyn_cast(boxType).getEleTy(); if (!fir::isa_ref_type(baseAddrType)) baseAddrType = builder.getRefType(baseAddrType); auto type = fir::unwrapRefType(baseAddrType); auto eleTy = fir::unwrapSequenceType(type); - if (auto recTy = eleTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(eleTy)) if (recTy.getNumLenParams() > 0) TODO(loc, "creating unallocated fir.box of derived type with length " "parameters"); auto nullAddr = builder.createNullConstant(loc, baseAddrType); mlir::Value shape; - if (auto seqTy = type.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(type)) { auto zero = builder.createIntegerConstant(loc, builder.getIndexType(), 0); llvm::SmallVector extents(seqTy.getDimension(), zero); shape = builder.createShape( @@ -348,7 +349,7 @@ mlir::Value fir::factory::createUnallocatedBox( // Provide dummy length parameters if they are dynamic. If a length parameter // is deferred. It is set to zero here and will be set on allocation. llvm::SmallVector lenParams; - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { if (charTy.getLen() == fir::CharacterType::unknownLen()) { if (!nonDeferredParams.empty()) { lenParams.push_back(nonDeferredParams[0]); @@ -592,7 +593,7 @@ void fir::factory::associateMutableBoxWithRemap( auto cast = [&](mlir::Value addr) -> mlir::Value { // Cast base addr to new sequence type. auto ty = fir::dyn_cast_ptrEleTy(addr.getType()); - if (auto seqTy = ty.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(ty)) { fir::SequenceType::Shape shape(newRank, fir::SequenceType::getUnknownExtent()); ty = fir::SequenceType::get(shape, seqTy.getEleTy()); @@ -673,10 +674,10 @@ void fir::factory::disassociateMutableBox(fir::FirOpBuilder &builder, if (box.isPolymorphic() && polymorphicSetType) { // 7.3.2.3 point 7. The dynamic type of a disassociated pointer is the // same as its declared type. - auto boxTy = box.getBoxTy().dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getBoxTy()); auto eleTy = fir::unwrapPassByRefType(boxTy.getEleTy()); mlir::Type derivedType = fir::getDerivedType(eleTy); - if (auto recTy = derivedType.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(derivedType)) { fir::runtime::genNullifyDerivedType(builder, loc, box.getAddr(), recTy, box.rank()); return; @@ -690,7 +691,7 @@ getNewLengths(fir::FirOpBuilder &builder, mlir::Location loc, const fir::MutableBoxValue &box, mlir::ValueRange lenParams) { llvm::SmallVector lengths; auto idxTy = builder.getIndexType(); - if (auto charTy = box.getEleTy().dyn_cast()) { + if (auto charTy = mlir::dyn_cast(box.getEleTy())) { if (charTy.getLen() == fir::CharacterType::unknownLen()) { if (box.hasNonDeferredLenParams()) { lengths.emplace_back( @@ -717,7 +718,7 @@ static mlir::Value allocateAndInitNewStorage(fir::FirOpBuilder &builder, auto lengths = getNewLengths(builder, loc, box, lenParams); auto newStorage = builder.create( loc, box.getBaseTy(), allocName, lengths, extents); - if (box.getEleTy().isa()) { + if (mlir::isa(box.getEleTy())) { // TODO: skip runtime initialization if this is not required. Currently, // there is no way to know here if a derived type needs it or not. But the // information is available at compile time and could be reflected here @@ -742,7 +743,7 @@ void fir::factory::genInlinedAllocation( lengths, safeExtents); MutablePropertyWriter{builder, loc, box}.updateMutableBox( heap, lbounds, safeExtents, lengths); - if (box.getEleTy().isa()) { + if (mlir::isa(box.getEleTy())) { // TODO: skip runtime initialization if this is not required. Currently, // there is no way to know here if a derived type needs it or not. But the // information is available at compile time and could be reflected here diff --git a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp index 160118e2c050..7f09e8822844 100644 --- a/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp +++ b/flang/lib/Optimizer/Builder/PPCIntrinsicCall.cpp @@ -1119,7 +1119,7 @@ PPCIntrinsicLibrary::genVecAbs(mlir::Type resultType, funcOp = builder.createFunction(loc, fname, ftype); auto callOp{builder.create(loc, funcOp, argBases[0])}; return callOp.getResult(0); - } else if (auto eleTy = vTypeInfo.eleTy.dyn_cast()) { + } else if (auto eleTy = mlir::dyn_cast(vTypeInfo.eleTy)) { // vec_abs(arg1) = max(0 - arg1, arg1) auto newVecTy{mlir::VectorType::get(vTypeInfo.len, eleTy)}; @@ -1173,12 +1173,13 @@ fir::ExtendedValue PPCIntrinsicLibrary::genVecAddAndMulSubXor( assert(args.size() == 2); auto argBases{getBasesForArgs(args)}; auto argsTy{getTypesForArgs(argBases)}; - assert(argsTy[0].isa() && argsTy[1].isa()); + assert(mlir::isa(argsTy[0]) && + mlir::isa(argsTy[1])); auto vecTyInfo{getVecTypeFromFir(argBases[0])}; - const auto isInteger{vecTyInfo.eleTy.isa()}; - const auto isFloat{vecTyInfo.eleTy.isa()}; + const auto isInteger{mlir::isa(vecTyInfo.eleTy)}; + const auto isFloat{mlir::isa(vecTyInfo.eleTy)}; assert((isInteger || isFloat) && "unknown vector type"); auto vargs{convertVecArgs(builder, loc, vecTyInfo, argBases)}; @@ -1212,7 +1213,7 @@ fir::ExtendedValue PPCIntrinsicLibrary::genVecAddAndMulSubXor( arg2 = vargs[1]; } else if (isFloat) { // bitcast the arguments to integer - auto wd{vecTyInfo.eleTy.dyn_cast().getWidth()}; + auto wd{mlir::dyn_cast(vecTyInfo.eleTy).getWidth()}; auto ftype{builder.getIntegerType(wd)}; auto bcVecTy{mlir::VectorType::get(vecTyInfo.len, ftype)}; arg1 = builder.create(loc, bcVecTy, vargs[0]); @@ -1450,7 +1451,7 @@ PPCIntrinsicLibrary::genVecCmp(mlir::Type resultType, mlir::Value res{nullptr}; - if (auto eTy = vecTyInfo.eleTy.dyn_cast()) { + if (auto eTy = mlir::dyn_cast(vecTyInfo.eleTy)) { constexpr int firstArg{0}; constexpr int secondArg{1}; std::map> argOrder{ @@ -1559,7 +1560,7 @@ PPCIntrinsicLibrary::genVecConvert(mlir::Type resultType, case VecOp::Ctf: { assert(args.size() == 2); auto convArg{builder.createConvert(loc, i32Ty, argBases[1])}; - auto eTy{vecTyInfo.eleTy.dyn_cast()}; + auto eTy{mlir::dyn_cast(vecTyInfo.eleTy)}; assert(eTy && "Unsupported vector type"); const auto isUnsigned{eTy.isUnsignedInteger()}; const auto width{eTy.getWidth()}; @@ -1587,10 +1588,9 @@ PPCIntrinsicLibrary::genVecConvert(mlir::Type resultType, : builder.create(loc, ty, vArg1)}; // construct vector<1./(1< - auto constInt{ + auto constInt{mlir::dyn_cast_or_null( mlir::dyn_cast(argBases[1].getDefiningOp()) - .getValue() - .dyn_cast_or_null()}; + .getValue())}; assert(constInt && "expected integer constant argument"); double f{1.0 / (1 << constInt.getInt())}; llvm::SmallVector vals{f, f}; @@ -1815,7 +1815,7 @@ static mlir::Value addOffsetToAddress(fir::FirOpBuilder &builder, static mlir::Value reverseVectorElements(fir::FirOpBuilder &builder, mlir::Location loc, mlir::Value v, int64_t len) { - assert(v.getType().isa()); + assert(mlir::isa(v.getType())); assert(len > 0); llvm::SmallVector mask; for (int64_t i = 0; i < len; ++i) { @@ -2144,10 +2144,9 @@ PPCIntrinsicLibrary::genVecPerm(mlir::Type resultType, } case VecOp::Permi: { // arg3 is a constant - auto constIntOp{ + auto constIntOp{mlir::dyn_cast_or_null( mlir::dyn_cast(argBases[2].getDefiningOp()) - .getValue() - .dyn_cast_or_null()}; + .getValue())}; assert(constIntOp && "expected integer constant argument"); auto constInt{constIntOp.getInt()}; // arg1, arg2, and result type share same VecTypeInfo @@ -2321,10 +2320,9 @@ PPCIntrinsicLibrary::genVecShift(mlir::Type resultType, } } else if (vop == VecOp::Sld || vop == VecOp::Sldw) { assert(args.size() == 3); - auto constIntOp = + auto constIntOp = mlir::dyn_cast_or_null( mlir::dyn_cast(argBases[2].getDefiningOp()) - .getValue() - .dyn_cast_or_null(); + .getValue()); assert(constIntOp && "expected integer constant argument"); // Bitcast to vector<16xi8> @@ -2797,16 +2795,16 @@ void PPCIntrinsicLibrary::genMmaIntr(llvm::ArrayRef args) { auto vType{v.getType()}; mlir::Type targetType{intrFuncType.getInput(j)}; if (vType != targetType) { - if (targetType.isa()) { + if (mlir::isa(targetType)) { // Perform vector type conversion for arguments passed by value. - auto eleTy{vType.dyn_cast().getEleTy()}; - auto len{vType.dyn_cast().getLen()}; + auto eleTy{mlir::dyn_cast(vType).getEleTy()}; + auto len{mlir::dyn_cast(vType).getLen()}; mlir::VectorType mlirType = mlir::VectorType::get(len, eleTy); auto v0{builder.createConvert(loc, mlirType, v)}; auto v1{builder.create(loc, targetType, v0)}; intrArgs.push_back(v1); - } else if (targetType.isa() && - vType.isa()) { + } else if (mlir::isa(targetType) && + mlir::isa(vType)) { auto v0{builder.createConvert(loc, targetType, v)}; intrArgs.push_back(v0); } else { @@ -2861,7 +2859,7 @@ void PPCIntrinsicLibrary::genVecStore(llvm::ArrayRef args) { if (arg1TyInfo.isFloat32()) { stTy = mlir::VectorType::get(len, i32ty); fname = "llvm.ppc.altivec.stvewx"; - } else if (arg1TyInfo.eleTy.isa()) { + } else if (mlir::isa(arg1TyInfo.eleTy)) { stTy = mlir::VectorType::get(len, mlir::IntegerType::get(context, width)); switch (width) { diff --git a/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp b/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp index abff0e150ab4..70a88ff18cb1 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Allocatable.cpp @@ -27,7 +27,7 @@ mlir::Value fir::runtime::genMoveAlloc(fir::FirOpBuilder &builder, if (fir::isPolymorphicType(from.getType()) && !fir::isUnlimitedPolymorphicType(from.getType())) { fir::ClassType clTy = - fir::dyn_cast_ptrEleTy(from.getType()).dyn_cast(); + mlir::dyn_cast(fir::dyn_cast_ptrEleTy(from.getType())); mlir::Type derivedType = fir::unwrapInnerType(clTy.getEleTy()); declaredTypeDesc = builder.create(loc, mlir::TypeAttr::get(derivedType)); diff --git a/flang/lib/Optimizer/Builder/Runtime/Character.cpp b/flang/lib/Optimizer/Builder/Runtime/Character.cpp index f3663439fdd5..b16819915d5a 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Character.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Character.cpp @@ -39,15 +39,15 @@ static void genCharacterSearch(FN func, fir::FirOpBuilder &builder, /// Helper function to recover the KIND from the FIR type. static int discoverKind(mlir::Type ty) { - if (auto charTy = ty.dyn_cast()) + if (auto charTy = mlir::dyn_cast(ty)) return charTy.getFKind(); if (auto eleTy = fir::dyn_cast_ptrEleTy(ty)) return discoverKind(eleTy); - if (auto arrTy = ty.dyn_cast()) + if (auto arrTy = mlir::dyn_cast(ty)) return discoverKind(arrTy.getEleTy()); - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return discoverKind(boxTy.getEleTy()); - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return discoverKind(boxTy.getEleTy()); llvm_unreachable("unexpected character type"); } diff --git a/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp b/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp index 57c47da0f3f8..8b78a1688c73 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Intrinsics.cpp @@ -228,7 +228,8 @@ void fir::runtime::genSystemClock(fir::FirOpBuilder &builder, fir::IfOp ifOp{}; const bool isOptionalArg = fir::valueHasFirAttribute(arg, fir::getOptionalAttrName()); - if (type.dyn_cast() || type.dyn_cast()) { + if (mlir::dyn_cast(type) || + mlir::dyn_cast(type)) { // Check for a disassociated pointer or an unallocated allocatable. assert(!isOptionalArg && "invalid optional argument"); ifOp = builder.create(loc, builder.genIsNotNullAddr(loc, arg), @@ -242,7 +243,8 @@ void fir::runtime::genSystemClock(fir::FirOpBuilder &builder, builder.setInsertionPointToStart(&ifOp.getThenRegion().front()); mlir::Type kindTy = func.getFunctionType().getInput(0); int integerKind = 8; - if (auto intType = fir::unwrapRefType(type).dyn_cast()) + if (auto intType = + mlir::dyn_cast(fir::unwrapRefType(type))) integerKind = intType.getWidth() / 8; mlir::Value kind = builder.createIntegerConstant(loc, kindTy, integerKind); mlir::Value res = diff --git a/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp b/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp index 4d33282a35d9..e5d0fb0fb27a 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Ragged.cpp @@ -32,7 +32,8 @@ void fir::runtime::genRaggedArrayAllocate(mlir::Location loc, // Position of the bufferPointer in the header struct. auto one = builder.createIntegerConstant(loc, i32Ty, 1); auto eleTy = fir::unwrapSequenceType(fir::unwrapRefType(header.getType())); - auto ptrTy = builder.getRefType(eleTy.cast().getType(1)); + auto ptrTy = + builder.getRefType(mlir::cast(eleTy).getType(1)); auto ptr = builder.create(loc, ptrTy, header, one); auto heap = builder.create(loc, ptr); auto cmp = builder.genIsNullAddr(loc, heap); diff --git a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp index 66fbaddcbda1..d4076067bf10 100644 --- a/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/Reduction.cpp @@ -666,7 +666,7 @@ void fir::runtime::genMaxloc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); fir::factory::CharacterExprHelper charHelper{builder, loc}; if (eleTy.isF32()) func = fir::runtime::getRuntimeFunc(loc, builder); @@ -713,7 +713,7 @@ mlir::Value fir::runtime::genMaxval(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -781,7 +781,7 @@ void fir::runtime::genMinloc(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); fir::factory::CharacterExprHelper charHelper{builder, loc}; if (eleTy.isF32()) func = fir::runtime::getRuntimeFunc(loc, builder); @@ -853,7 +853,7 @@ mlir::Value fir::runtime::genMinval(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -895,7 +895,7 @@ void fir::runtime::genNorm2Dim(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); if (eleTy.isF128()) func = fir::runtime::getRuntimeFunc(loc, builder); else @@ -917,7 +917,7 @@ mlir::Value fir::runtime::genNorm2(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -968,7 +968,7 @@ mlir::Value fir::runtime::genProduct(fir::FirOpBuilder &builder, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -1069,7 +1069,7 @@ mlir::Value fir::runtime::genDotProduct(fir::FirOpBuilder &builder, else if (eleTy.isInteger(builder.getKindMap().getIntegerBitsize(16))) func = fir::runtime::getRuntimeFunc(loc, builder); - else if (eleTy.isa()) + else if (mlir::isa(eleTy)) func = fir::runtime::getRuntimeFunc(loc, builder); else @@ -1111,7 +1111,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; auto ty = arrayBox.getType(); auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); - auto eleTy = arrTy.cast().getEleTy(); + auto eleTy = mlir::cast(arrTy).getEleTy(); auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); if (eleTy.isF32()) @@ -1173,7 +1173,7 @@ mlir::Value fir::runtime::genSum(fir::FirOpBuilder &builder, mlir::Location loc, mlir::func::FuncOp func; \ auto ty = arrayBox.getType(); \ auto arrTy = fir::dyn_cast_ptrOrBoxEleTy(ty); \ - auto eleTy = arrTy.cast().getEleTy(); \ + auto eleTy = mlir::cast(arrTy).getEleTy(); \ auto dim = builder.createIntegerConstant(loc, builder.getIndexType(), 0); \ \ if (eleTy.isInteger(builder.getKindMap().getIntegerBitsize(1))) \ diff --git a/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp b/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp index 48173033ecbe..5229d40f2250 100644 --- a/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp +++ b/flang/lib/Optimizer/CodeGen/BoxedProcedure.cpp @@ -51,9 +51,9 @@ public: /// not at all depending on the implementation target's characteristics and /// preference. bool needsConversion(mlir::Type ty) { - if (ty.isa()) + if (mlir::isa(ty)) return true; - if (auto funcTy = ty.dyn_cast()) { + if (auto funcTy = mlir::dyn_cast(ty)) { for (auto t : funcTy.getInputs()) if (needsConversion(t)) return true; @@ -62,13 +62,13 @@ public: return true; return false; } - if (auto tupleTy = ty.dyn_cast()) { + if (auto tupleTy = mlir::dyn_cast(ty)) { for (auto t : tupleTy.getTypes()) if (needsConversion(t)) return true; return false; } - if (auto recTy = ty.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(ty)) { auto visited = visitedTypes.find(ty); if (visited != visitedTypes.end()) return visited->second; @@ -97,11 +97,11 @@ public: visitedTypes.find(ty)->second = result; return result; } - if (auto boxTy = ty.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(ty)) return needsConversion(boxTy.getEleTy()); if (isa_ref_type(ty)) return needsConversion(unwrapRefType(ty)); - if (auto t = ty.dyn_cast()) + if (auto t = mlir::dyn_cast(ty)) return needsConversion(unwrapSequenceType(ty)); return false; } @@ -246,7 +246,7 @@ public: if (typeConverter.needsConversion(ty)) { rewriter.startOpModification(func); auto toTy = - typeConverter.convertType(ty).cast(); + mlir::cast(typeConverter.convertType(ty)); if (!func.empty()) for (auto e : llvm::enumerate(toTy.getInputs())) { unsigned i = e.index(); @@ -263,7 +263,7 @@ public: // Rewrite all `fir.emboxproc` ops to either `fir.convert` or a thunk // as required. mlir::Type toTy = typeConverter.convertType( - embox.getType().cast().getEleTy()); + mlir::cast(embox.getType()).getEleTy()); rewriter.setInsertionPoint(embox); if (embox.getHost()) { // Create the thunk. diff --git a/flang/lib/Optimizer/CodeGen/CGOps.cpp b/flang/lib/Optimizer/CodeGen/CGOps.cpp index c3bcdeaf86db..44d07d26dd2b 100644 --- a/flang/lib/Optimizer/CodeGen/CGOps.cpp +++ b/flang/lib/Optimizer/CodeGen/CGOps.cpp @@ -41,24 +41,24 @@ unsigned fir::cg::XEmboxOp::getOutRank() { } unsigned fir::cg::XReboxOp::getOutRank() { - if (auto seqTy = - fir::dyn_cast_ptrOrBoxEleTy(getType()).dyn_cast()) + if (auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(getType()))) return seqTy.getDimension(); return 0; } unsigned fir::cg::XReboxOp::getRank() { - if (auto seqTy = fir::dyn_cast_ptrOrBoxEleTy(getBox().getType()) - .dyn_cast()) + if (auto seqTy = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(getBox().getType()))) return seqTy.getDimension(); return 0; } unsigned fir::cg::XArrayCoorOp::getRank() { auto memrefTy = getMemref().getType(); - if (memrefTy.isa()) - if (auto seqty = - fir::dyn_cast_ptrOrBoxEleTy(memrefTy).dyn_cast()) + if (mlir::isa(memrefTy)) + if (auto seqty = mlir::dyn_cast( + fir::dyn_cast_ptrOrBoxEleTy(memrefTy))) return seqty.getDimension(); return getShape().size(); } diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp index 921eac2f8f4b..19628ac71b0b 100644 --- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp +++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp @@ -101,7 +101,7 @@ static int64_t getConstantIntValue(mlir::Value val) { } static unsigned getTypeDescFieldId(mlir::Type ty) { - auto isArray = fir::dyn_cast_ptrOrBoxEleTy(ty).isa(); + auto isArray = mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(ty)); return isArray ? kOptTypePtrPosInBox : kDimsPosInBox; } static unsigned getLenParamFieldId(mlir::Type ty) { @@ -147,7 +147,7 @@ genAllocationScaleSize(OP op, mlir::Type ity, mlir::ConversionPatternRewriter &rewriter) { mlir::Location loc = op.getLoc(); mlir::Type dataTy = op.getInType(); - auto seqTy = dataTy.dyn_cast(); + auto seqTy = mlir::dyn_cast(dataTy); fir::SequenceType::Extent constSize = 1; if (seqTy) { int constRows = seqTy.getConstantRows(); @@ -191,13 +191,13 @@ struct AllocaOpConversion : public fir::FIROpConversion { for (; i < end; ++i) lenParams.push_back(operands[i]); mlir::Type scalarType = fir::unwrapSequenceType(alloc.getInType()); - if (auto chrTy = scalarType.dyn_cast()) { + if (auto chrTy = mlir::dyn_cast(scalarType)) { fir::CharacterType rawCharTy = fir::CharacterType::getUnknownLen( chrTy.getContext(), chrTy.getFKind()); llvmObjectType = convertType(rawCharTy); assert(end == 1); size = integerCast(loc, rewriter, ity, lenParams[0]); - } else if (auto recTy = scalarType.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(scalarType)) { mlir::LLVM::LLVMFuncOp memSizeFn = getDependentTypeMemSizeFn(recTy, alloc, rewriter); if (!memSizeFn) @@ -265,7 +265,8 @@ struct BoxAddrOpConversion : public fir::FIROpConversion { mlir::ConversionPatternRewriter &rewriter) const override { mlir::Value a = adaptor.getOperands()[0]; auto loc = boxaddr.getLoc(); - if (auto argty = boxaddr.getVal().getType().dyn_cast()) { + if (auto argty = + mlir::dyn_cast(boxaddr.getVal().getType())) { TypePair boxTyPair = getBoxTypePair(argty); rewriter.replaceOp(boxaddr, getBaseAddrFromBox(loc, boxTyPair, a, rewriter)); @@ -476,24 +477,25 @@ struct StringLitOpConversion : public fir::FIROpConversion { mlir::ConversionPatternRewriter &rewriter) const override { auto ty = convertType(constop.getType()); auto attr = constop.getValue(); - if (attr.isa()) { + if (mlir::isa(attr)) { rewriter.replaceOpWithNewOp(constop, ty, attr); return mlir::success(); } - auto charTy = constop.getType().cast(); + auto charTy = mlir::cast(constop.getType()); unsigned bits = lowerTy().characterBitsize(charTy); mlir::Type intTy = rewriter.getIntegerType(bits); mlir::Location loc = constop.getLoc(); mlir::Value cst = rewriter.create(loc, ty); - if (auto arr = attr.dyn_cast()) { + if (auto arr = mlir::dyn_cast(attr)) { cst = rewriter.create(loc, ty, arr); - } else if (auto arr = attr.dyn_cast()) { + } else if (auto arr = mlir::dyn_cast(attr)) { for (auto a : llvm::enumerate(arr.getValue())) { // convert each character to a precise bitsize auto elemAttr = mlir::IntegerAttr::get( intTy, - a.value().cast().getValue().zextOrTrunc(bits)); + mlir::cast(a.value()).getValue().zextOrTrunc( + bits)); auto elemCst = rewriter.create(loc, intTy, elemAttr); cst = rewriter.create(loc, cst, elemCst, @@ -528,9 +530,9 @@ struct CallOpConversion : public fir::FIROpConversion { } // namespace static mlir::Type getComplexEleTy(mlir::Type complex) { - if (auto cc = complex.dyn_cast()) + if (auto cc = mlir::dyn_cast(complex)) return cc.getElementType(); - return complex.cast().getElementType(); + return mlir::cast(complex).getElementType(); } namespace { @@ -599,7 +601,7 @@ struct ConstcOpConversion : public fir::FIROpConversion { } inline llvm::APFloat getValue(mlir::Attribute attr) const { - return attr.cast().getValue(); + return mlir::cast(attr).getValue(); } }; @@ -608,7 +610,7 @@ struct ConvertOpConversion : public fir::FIROpConversion { using FIROpConversion::FIROpConversion; static bool isFloatingPointTy(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } mlir::LogicalResult @@ -628,7 +630,8 @@ struct ConvertOpConversion : public fir::FIROpConversion { auto loc = convert.getLoc(); auto i1Type = mlir::IntegerType::get(convert.getContext(), 1); - if (fromFirTy.isa() || toFirTy.isa()) { + if (mlir::isa(fromFirTy) || + mlir::isa(toFirTy)) { // By specification fir::LogicalType value may be any number, // where non-zero value represents .true. and zero value represents // .false. @@ -641,7 +644,8 @@ struct ConvertOpConversion : public fir::FIROpConversion { // Conversion from narrow logical to wide logical may be implemented // as a zero or sign extension of the input, but it may use value // normalization as well. - if (!fromTy.isa() || !toTy.isa()) + if (!mlir::isa(fromTy) || + !mlir::isa(toTy)) return mlir::emitError(loc) << "unsupported types for logical conversion: " << fromTy << " -> " << toTy; @@ -722,13 +726,13 @@ struct ConvertOpConversion : public fir::FIROpConversion { rewriter.replaceOp(convert, v); return mlir::success(); } - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } - } else if (fromTy.isa()) { + } else if (mlir::isa(fromTy)) { // Integer to integer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { auto fromBits = mlir::LLVM::getPrimitiveTypeSizeInBits(fromTy); auto toBits = mlir::LLVM::getPrimitiveTypeSizeInBits(toTy); assert(fromBits != toBits); @@ -749,18 +753,18 @@ struct ConvertOpConversion : public fir::FIROpConversion { return mlir::success(); } // Integer to pointer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } - } else if (fromTy.isa()) { + } else if (mlir::isa(fromTy)) { // Pointer to integer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } // Pointer to pointer conversion. - if (toTy.isa()) { + if (mlir::isa(toTy)) { rewriter.replaceOpWithNewOp(convert, toTy, op0); return mlir::success(); } @@ -842,11 +846,11 @@ struct EmboxCharOpConversion : public fir::FIROpConversion { auto llvmStruct = rewriter.create(loc, llvmStructTy); mlir::Type lenTy = - llvmStructTy.cast().getBody()[1]; + mlir::cast(llvmStructTy).getBody()[1]; mlir::Value lenAfterCast = integerCast(loc, rewriter, lenTy, charBufferLen); mlir::Type addrTy = - llvmStructTy.cast().getBody()[0]; + mlir::cast(llvmStructTy).getBody()[0]; if (addrTy != charBuffer.getType()) charBuffer = rewriter.create(loc, addrTy, charBuffer); @@ -979,9 +983,10 @@ static mlir::SymbolRefAttr getFree(fir::FreeMemOp op, static unsigned getDimension(mlir::LLVM::LLVMArrayType ty) { unsigned result = 1; - for (auto eleTy = ty.getElementType().dyn_cast(); - eleTy; - eleTy = eleTy.getElementType().dyn_cast()) + for (auto eleTy = + mlir::dyn_cast(ty.getElementType()); + eleTy; eleTy = mlir::dyn_cast( + eleTy.getElementType())) ++result; return result; } @@ -1052,9 +1057,9 @@ struct EmboxCommonConversion : public fir::FIROpConversion { static int getCFIAttr(fir::BaseBoxType boxTy) { auto eleTy = boxTy.getEleTy(); - if (eleTy.isa()) + if (mlir::isa(eleTy)) return CFI_attribute_pointer; - if (eleTy.isa()) + if (mlir::isa(eleTy)) return CFI_attribute_allocatable; return CFI_attribute_other; } @@ -1082,27 +1087,29 @@ struct EmboxCommonConversion : public fir::FIROpConversion { auto i64Ty = mlir::IntegerType::get(rewriter.getContext(), 64); if (auto eleTy = fir::dyn_cast_ptrEleTy(boxEleTy)) boxEleTy = eleTy; - if (auto seqTy = boxEleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(boxEleTy)) return getSizeAndTypeCode(loc, rewriter, seqTy.getEleTy(), lenParams); - if (boxEleTy.isa()) // unlimited polymorphic or assumed type + if (mlir::isa( + boxEleTy)) // unlimited polymorphic or assumed type return {rewriter.create(loc, i64Ty, 0), this->genConstantOffset(loc, rewriter, CFI_type_other)}; mlir::Value typeCodeVal = this->genConstantOffset( loc, rewriter, fir::getTypeCode(boxEleTy, this->lowerTy().getKindMap())); - if (fir::isa_integer(boxEleTy) || boxEleTy.dyn_cast() || - fir::isa_real(boxEleTy) || fir::isa_complex(boxEleTy)) + if (fir::isa_integer(boxEleTy) || + mlir::dyn_cast(boxEleTy) || fir::isa_real(boxEleTy) || + fir::isa_complex(boxEleTy)) return {genTypeStrideInBytes(loc, i64Ty, rewriter, this->convertType(boxEleTy)), typeCodeVal}; - if (auto charTy = boxEleTy.dyn_cast()) + if (auto charTy = mlir::dyn_cast(boxEleTy)) return {getCharacterByteSize(loc, rewriter, charTy, lenParams), typeCodeVal}; if (fir::isa_ref_type(boxEleTy)) { auto ptrTy = ::getLlvmPtrType(rewriter.getContext()); return {genTypeStrideInBytes(loc, i64Ty, rewriter, ptrTy), typeCodeVal}; } - if (boxEleTy.isa()) + if (mlir::isa(boxEleTy)) return {genTypeStrideInBytes(loc, i64Ty, rewriter, this->convertType(boxEleTy)), typeCodeVal}; @@ -1211,8 +1218,8 @@ struct EmboxCommonConversion : public fir::FIROpConversion { if (!typeDesc) { if (useInputType) { mlir::Type innerType = fir::unwrapInnerType(inputType); - if (innerType && innerType.template isa()) { - auto recTy = innerType.template dyn_cast(); + if (innerType && mlir::isa(innerType)) { + auto recTy = mlir::dyn_cast(innerType); typeDesc = getTypeDescriptor(mod, rewriter, loc, recTy); } else { // Unlimited polymorphic type descriptor with no record type. Set @@ -1250,7 +1257,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::ValueRange lenParams, mlir::Value sourceBox = {}, mlir::Type sourceBoxType = {}) const { auto loc = box.getLoc(); - auto boxTy = box.getType().template dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getType()); bool useInputType = fir::isPolymorphicType(boxTy) && !fir::isUnlimitedPolymorphicType(inputType); llvm::SmallVector typeparams = lenParams; @@ -1293,8 +1300,8 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::ValueRange lenParams, mlir::Value typeDesc = {}) const { auto loc = box.getLoc(); - auto boxTy = box.getType().dyn_cast(); - auto inputBoxTy = box.getBox().getType().dyn_cast(); + auto boxTy = mlir::dyn_cast(box.getType()); + auto inputBoxTy = mlir::dyn_cast(box.getBox().getType()); auto inputBoxTyPair = this->getBoxTypePair(inputBoxTy); llvm::SmallVector typeparams = lenParams; if (!box.getSubstr().empty() && fir::hasDynamicSize(boxTy.getEleTy())) @@ -1343,7 +1350,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { mlir::Type resultTy = llvmBaseObjectType; // Fortran is column major, llvm GEP is row major: reverse the indices here. for (mlir::Value interiorIndex : llvm::reverse(cstInteriorIndices)) { - auto arrayTy = resultTy.dyn_cast(); + auto arrayTy = mlir::dyn_cast(resultTy); if (!arrayTy) fir::emitFatalError( loc, @@ -1355,7 +1362,7 @@ struct EmboxCommonConversion : public fir::FIROpConversion { convertSubcomponentIndices(loc, resultTy, componentIndices, &resultTy); gepArgs.append(gepIndices.begin(), gepIndices.end()); if (substringOffset) { - if (auto arrayTy = resultTy.dyn_cast()) { + if (auto arrayTy = mlir::dyn_cast(resultTy)) { gepArgs.push_back(*substringOffset); resultTy = arrayTy.getElementType(); } else { @@ -1504,18 +1511,18 @@ struct XEmboxOpConversion : public EmboxCommonConversion { unsigned constRows = 0; mlir::Value ptrOffset = zero; mlir::Type memEleTy = fir::dyn_cast_ptrEleTy(xbox.getMemref().getType()); - assert(memEleTy.isa()); - auto seqTy = memEleTy.cast(); + assert(mlir::isa(memEleTy)); + auto seqTy = mlir::cast(memEleTy); mlir::Type seqEleTy = seqTy.getEleTy(); // Adjust the element scaling factor if the element is a dependent type. if (fir::hasDynamicSize(seqEleTy)) { - if (auto charTy = seqEleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(seqEleTy)) { // The GEP pointer type decays to llvm.ptr. // The scaling factor is the runtime value of the length. assert(!adaptor.getLenParams().empty()); prevPtrOff = FIROpConversion::integerCast( loc, rewriter, i64Ty, adaptor.getLenParams().back()); - } else if (seqEleTy.isa()) { + } else if (mlir::isa(seqEleTy)) { // prevPtrOff = ; TODO(loc, "generate call to calculate size of PDT"); } else { @@ -1540,7 +1547,7 @@ struct XEmboxOpConversion : public EmboxCommonConversion { } else if (hasSubstr) { // We have a substring. The step value needs to be the number of bytes // per CHARACTER element. - auto charTy = seqEleTy.cast(); + auto charTy = mlir::cast(seqEleTy); if (fir::hasDynamicSize(charTy)) { prevDimByteStride = getCharacterByteSize(loc, rewriter, charTy, adaptor.getLenParams()); @@ -1589,7 +1596,7 @@ struct XEmboxOpConversion : public EmboxCommonConversion { // Lower bound is normalized to 0 for BIND(C) interoperability. mlir::Value lb = zero; const bool isaPointerOrAllocatable = - eleTy.isa() || eleTy.isa(); + mlir::isa(eleTy); // Lower bound is defaults to 1 for POINTER, ALLOCATABLE, and // denormalized descriptors. if (isaPointerOrAllocatable || !normalizedLowerBound(xbox)) @@ -1695,7 +1702,7 @@ struct XReboxOpConversion : public EmboxCommonConversion { // Create new descriptor and fill its non-shape related data. llvm::SmallVector lenParams; mlir::Type inputEleTy = getInputEleTy(rebox); - if (auto charTy = inputEleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(inputEleTy)) { if (charTy.hasConstantLen()) { mlir::Value len = genConstantIndex(loc, idxTy, rewriter, charTy.getLen()); @@ -1712,15 +1719,15 @@ struct XReboxOpConversion : public EmboxCommonConversion { } lenParams.emplace_back(len); } - } else if (auto recTy = inputEleTy.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(inputEleTy)) { if (recTy.getNumLenParams() != 0) TODO(loc, "reboxing descriptor of derived type with length parameters"); } // Rebox on polymorphic entities needs to carry over the dynamic type. mlir::Value typeDescAddr; - if (inputBoxTyPair.fir.isa() && - rebox.getType().isa()) + if (mlir::isa(inputBoxTyPair.fir) && + mlir::isa(rebox.getType())) typeDescAddr = loadTypeDescAddress(loc, inputBoxTyPair, loweredBox, rewriter); @@ -1908,7 +1915,7 @@ private: /// Return scalar element type of the input box. static mlir::Type getInputEleTy(fir::cg::XReboxOp rebox) { auto ty = fir::dyn_cast_ptrOrBoxEleTy(rebox.getBox().getType()); - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return seqTy.getEleTy(); return ty; } @@ -1936,7 +1943,7 @@ struct ValueOpCommon { assert(ty && "type is null"); const auto end = indices.size(); for (std::remove_const_t i = 0; i < end; ++i) { - if (auto seq = ty.dyn_cast()) { + if (auto seq = mlir::dyn_cast(ty)) { const auto dim = getDimension(seq); if (dim > 1) { auto ub = std::min(i + dim, end); @@ -1944,7 +1951,7 @@ struct ValueOpCommon { i += dim - 1; } ty = getArrayElementType(seq); - } else if (auto st = ty.dyn_cast()) { + } else if (auto st = mlir::dyn_cast(ty)) { ty = st.getBody()[indices[i]]; } else { llvm_unreachable("index into invalid type"); @@ -1963,7 +1970,7 @@ struct ValueOpCommon { auto fieldName = i->cast().getValue(); ++i; auto ty = i->cast().getValue(); - auto index = ty.cast().getFieldIndex(fieldName); + auto index = mlir::cast(ty).getFieldIndex(fieldName); indices.push_back(index); } } @@ -1973,7 +1980,7 @@ struct ValueOpCommon { private: static mlir::Type getArrayElementType(mlir::LLVM::LLVMArrayType ty) { auto eleTy = ty.getElementType(); - while (auto arrTy = eleTy.dyn_cast()) + while (auto arrTy = mlir::dyn_cast(eleTy)) eleTy = arrTy.getElementType(); return eleTy; } @@ -2041,7 +2048,7 @@ struct InsertOnRangeOpConversion auto type = adaptor.getOperands()[0].getType(); // Iteratively extract the array dimensions from the type. - while (auto t = type.dyn_cast()) { + while (auto t = mlir::dyn_cast(type)) { dims.push_back(t.getNumElements()); type = t.getElementType(); } @@ -2107,7 +2114,8 @@ struct XArrayCoorOpConversion mlir::Value offset = genConstantIndex(loc, idxTy, rewriter, 0); const bool isShifted = !coor.getShift().empty(); const bool isSliced = !coor.getSlice().empty(); - const bool baseIsBoxed = coor.getMemref().getType().isa(); + const bool baseIsBoxed = + mlir::isa(coor.getMemref().getType()); TypePair baseBoxTyPair = baseIsBoxed ? getBoxTypePair(coor.getMemref().getType()) : TypePair{}; mlir::LLVM::IntegerOverflowFlags nsw = @@ -2185,7 +2193,8 @@ struct XArrayCoorOpConversion // components. mlir::Type elementType = getLlvmObjectTypeFromBoxType(coor.getMemref().getType()); - while (auto arrayTy = elementType.dyn_cast()) + while (auto arrayTy = + mlir::dyn_cast(elementType)) elementType = arrayTy.getElementType(); args.clear(); args.push_back(0); @@ -2275,11 +2284,12 @@ struct CoordinateOpConversion } // Boxed type - get the base pointer from the box - if (baseObjectTy.dyn_cast()) + if (mlir::dyn_cast(baseObjectTy)) return doRewriteBox(coor, operands, loc, rewriter); // Reference, pointer or a heap type - if (baseObjectTy.isa()) + if (mlir::isa( + baseObjectTy)) return doRewriteRefOrPtr(coor, llvmObjectTy, operands, loc, rewriter); return rewriter.notifyMatchFailure( @@ -2295,7 +2305,7 @@ struct CoordinateOpConversion } static bool hasSubDimensions(mlir::Type type) { - return type.isa(); + return mlir::isa(type); } /// Check whether this form of `!fir.coordinate_of` is supported. These @@ -2310,14 +2320,14 @@ struct CoordinateOpConversion bool ptrEle = false; for (; i < numOfCoors; ++i) { mlir::Value nxtOpnd = coors[i]; - if (auto arrTy = type.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(type)) { subEle = true; i += arrTy.getDimension() - 1; type = arrTy.getEleTy(); - } else if (auto recTy = type.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(type)) { subEle = true; type = recTy.getType(getFieldNumber(recTy, nxtOpnd)); - } else if (auto tupTy = type.dyn_cast()) { + } else if (auto tupTy = mlir::dyn_cast(type)) { subEle = true; type = tupTy.getType(getConstantIntValue(nxtOpnd)); } else { @@ -2335,14 +2345,14 @@ struct CoordinateOpConversion static bool arraysHaveKnownShape(mlir::Type type, mlir::ValueRange coors) { for (std::size_t i = 0, sz = coors.size(); i < sz; ++i) { mlir::Value nxtOpnd = coors[i]; - if (auto arrTy = type.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(type)) { if (fir::sequenceWithNonConstantShape(arrTy)) return false; i += arrTy.getDimension() - 1; type = arrTy.getEleTy(); - } else if (auto strTy = type.dyn_cast()) { + } else if (auto strTy = mlir::dyn_cast(type)) { type = strTy.getType(getFieldNumber(strTy, nxtOpnd)); - } else if (auto strTy = type.dyn_cast()) { + } else if (auto strTy = mlir::dyn_cast(type)) { type = strTy.getType(getConstantIntValue(nxtOpnd)); } else { return true; @@ -2357,7 +2367,8 @@ private: mlir::Location loc, mlir::ConversionPatternRewriter &rewriter) const { mlir::Type boxObjTy = coor.getBaseType(); - assert(boxObjTy.dyn_cast() && "This is not a `fir.box`"); + assert(mlir::dyn_cast(boxObjTy) && + "This is not a `fir.box`"); TypePair boxTyPair = getBoxTypePair(boxObjTy); mlir::Value boxBaseAddr = operands[0]; @@ -2399,7 +2410,7 @@ private: mlir::LLVM::IntegerOverflowFlags::nsw; for (unsigned i = 1, last = operands.size(); i < last; ++i) { - if (auto arrTy = cpnTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(cpnTy)) { if (i != 1) TODO(loc, "fir.array nested inside other array and/or derived type"); // Applies byte strides from the box. Ignore lower bound from box @@ -2421,7 +2432,7 @@ private: llvm::ArrayRef{off}); i += arrTy.getDimension() - 1; cpnTy = arrTy.getEleTy(); - } else if (auto recTy = cpnTy.dyn_cast()) { + } else if (auto recTy = mlir::dyn_cast(cpnTy)) { mlir::Value nxtOpnd = operands[i]; cpnTy = recTy.getType(getFieldNumber(recTy, nxtOpnd)); auto llvmRecTy = lowerTy().convertType(recTy); @@ -2456,7 +2467,7 @@ private: // If only the column is `?`, then we can simply place the column value in // the 0-th GEP position. - if (auto arrTy = cpnTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(cpnTy)) { if (!hasKnownShape) { const unsigned sz = arrTy.getDimension(); if (arraysHaveKnownShape(arrTy.getEleTy(), @@ -2500,29 +2511,29 @@ private: dims = dimsLeft - 1; continue; } - cpnTy = cpnTy.cast().getEleTy(); + cpnTy = mlir::cast(cpnTy).getEleTy(); // append array range in reverse (FIR arrays are column-major) offs.append(arrIdx.rbegin(), arrIdx.rend()); arrIdx.clear(); dims.reset(); continue; } - if (auto arrTy = cpnTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(cpnTy)) { int d = arrTy.getDimension() - 1; if (d > 0) { dims = d; arrIdx.push_back(nxtOpnd); continue; } - cpnTy = cpnTy.cast().getEleTy(); + cpnTy = mlir::cast(cpnTy).getEleTy(); offs.push_back(nxtOpnd); continue; } // check if the i-th coordinate relates to a field - if (auto recTy = cpnTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(cpnTy)) cpnTy = recTy.getType(getFieldNumber(recTy, nxtOpnd)); - else if (auto tupTy = cpnTy.dyn_cast()) + else if (auto tupTy = mlir::dyn_cast(cpnTy)) cpnTy = tupTy.getType(getConstantIntValue(nxtOpnd)); else cpnTy = nullptr; @@ -2551,7 +2562,7 @@ struct FieldIndexOpConversion : public fir::FIROpConversion { mlir::LogicalResult matchAndRewrite(fir::FieldIndexOp field, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { - auto recTy = field.getOnType().cast(); + auto recTy = mlir::cast(field.getOnType()); unsigned index = recTy.getFieldIndex(field.getFieldId()); if (!fir::hasDynamicSize(recTy)) { @@ -2604,8 +2615,8 @@ struct TypeDescOpConversion : public fir::FIROpConversion { matchAndRewrite(fir::TypeDescOp typeDescOp, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { mlir::Type inTy = typeDescOp.getInType(); - assert(inTy.isa() && "expecting fir.type"); - auto recordType = inTy.dyn_cast(); + assert(mlir::isa(inTy) && "expecting fir.type"); + auto recordType = mlir::dyn_cast(inTy); auto module = typeDescOp.getOperation()->getParentOfType(); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recordType.getName()); @@ -2732,7 +2743,7 @@ struct GlobalOpConversion : public fir::FIROpConversion { mlir::Type vecType = mlir::VectorType::get( insertOp.getType().getShape(), constant.getType()); auto denseAttr = mlir::DenseElementsAttr::get( - vecType.cast(), constant.getValue()); + mlir::cast(vecType), constant.getValue()); rewriter.setInsertionPointAfter(insertOp); rewriter.replaceOpWithNewOp( insertOp, seqTyAttr, denseAttr); @@ -2808,7 +2819,7 @@ struct LoadOpConversion : public fir::FIROpConversion { matchAndRewrite(fir::LoadOp load, OpAdaptor adaptor, mlir::ConversionPatternRewriter &rewriter) const override { mlir::Type llvmLoadTy = convertObjectType(load.getType()); - if (auto boxTy = load.getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(load.getType())) { // fir.box is a special case because it is considered as an ssa values in // fir, but it is lowered as a pointer to a descriptor. So // fir.ref and fir.box end up being the same llvm types and @@ -2921,7 +2932,7 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { llvm::ArrayRef cases = caseOp.getCases().getValue(); // Type can be CHARACTER, INTEGER, or LOGICAL (C1145) auto ty = caseOp.getSelector().getType(); - if (ty.isa()) { + if (mlir::isa(ty)) { TODO(caseOp.getLoc(), "fir.select_case codegen with character type"); return mlir::failure(); } @@ -2935,25 +2946,25 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { *caseOp.getCompareOperands(adaptor.getOperands(), t); mlir::Value caseArg = *(cmpOps.value().begin()); mlir::Attribute attr = cases[t]; - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::eq, selector, caseArg); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, caseArg, selector); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, selector, caseArg); genCaseLadderStep(loc, cmp, dest, destOps, rewriter); continue; } - if (attr.isa()) { + if (mlir::isa(attr)) { auto cmp = rewriter.create( loc, mlir::LLVM::ICmpPredicate::sle, caseArg, selector); auto *thisBlock = rewriter.getInsertionBlock(); @@ -2969,7 +2980,7 @@ struct SelectCaseOpConversion : public fir::FIROpConversion { rewriter.setInsertionPointToEnd(newBlock2); continue; } - assert(attr.isa()); + assert(mlir::isa(attr)); assert((t + 1 == conds) && "unit must be last"); genBrOp(caseOp, dest, destOps, rewriter); } @@ -2997,7 +3008,7 @@ static void selectMatchAndRewrite(const fir::LLVMTypeConverter &lowering, mlir::Block *dest = select.getSuccessor(t); auto destOps = select.getSuccessorOperands(adaptor.getOperands(), t); const mlir::Attribute &attr = cases[t]; - if (auto intAttr = attr.template dyn_cast()) { + if (auto intAttr = mlir::dyn_cast(attr)) { destinations.push_back(dest); destinationsOperands.push_back(destOps ? *destOps : mlir::ValueRange{}); caseValues.push_back(intAttr.getInt()); @@ -3071,7 +3082,7 @@ struct StoreOpConversion : public fir::FIROpConversion { mlir::Location loc = store.getLoc(); mlir::Type storeTy = store.getValue().getType(); mlir::LLVM::StoreOp newStoreOp; - if (auto boxTy = storeTy.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(storeTy)) { // fir.box value is actually in memory, load it first before storing it. mlir::Type llvmBoxTy = lowerTy().convertBoxTypeAsStruct(boxTy); auto val = rewriter.create(loc, llvmBoxTy, @@ -3186,9 +3197,9 @@ struct IsPresentOpConversion : public fir::FIROpConversion { mlir::Location loc = isPresent.getLoc(); auto ptr = adaptor.getOperands()[0]; - if (isPresent.getVal().getType().isa()) { + if (mlir::isa(isPresent.getVal().getType())) { [[maybe_unused]] auto structTy = - ptr.getType().cast(); + mlir::cast(ptr.getType()); assert(!structTy.isOpaque() && !structTy.getBody().empty()); ptr = rewriter.create(loc, ptr, 0); @@ -3214,8 +3225,8 @@ struct AbsentOpConversion : public fir::FIROpConversion { mlir::Type ty = convertType(absent.getType()); mlir::Location loc = absent.getLoc(); - if (absent.getType().isa()) { - auto structTy = ty.cast(); + if (mlir::isa(absent.getType())) { + auto structTy = mlir::cast(ty); assert(!structTy.isOpaque() && !structTy.getBody().empty()); auto undefStruct = rewriter.create(loc, ty); auto nullField = diff --git a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp index 26871d888815..00c5f77cde7c 100644 --- a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp +++ b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp @@ -20,7 +20,7 @@ static inline mlir::Type getLlvmPtrType(mlir::MLIRContext *context, } static unsigned getTypeDescFieldId(mlir::Type ty) { - auto isArray = fir::dyn_cast_ptrOrBoxEleTy(ty).isa(); + auto isArray = mlir::isa(fir::dyn_cast_ptrOrBoxEleTy(ty)); return isArray ? kOptTypePtrPosInBox : kDimsPosInBox; } @@ -37,7 +37,7 @@ ConvertFIRToLLVMPattern::ConvertFIRToLLVMPattern( // reference. mlir::Type ConvertFIRToLLVMPattern::convertObjectType(mlir::Type firType) const { - if (auto boxTy = firType.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(firType)) return lowerTy().convertBoxTypeAsStruct(boxTy); return lowerTy().convertType(firType); } @@ -69,7 +69,7 @@ ConvertFIRToLLVMPattern::integerCast(mlir::Location loc, auto valTy = val.getType(); // If the value was not yet lowered, lower its type so that it can // be used in getPrimitiveTypeSizeInBits. - if (!valTy.isa()) + if (!mlir::isa(valTy)) valTy = convertType(valTy); auto toSize = mlir::LLVM::getPrimitiveTypeSizeInBits(ty); auto fromSize = mlir::LLVM::getPrimitiveTypeSizeInBits(valTy); @@ -91,7 +91,7 @@ ConvertFIRToLLVMPattern::getBoxTypePair(mlir::Type firBoxTy) const { mlir::Value ConvertFIRToLLVMPattern::getValueFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, mlir::Type resultTy, mlir::ConversionPatternRewriter &rewriter, int boxValue) const { - if (box.getType().isa()) { + if (mlir::isa(box.getType())) { auto pty = getLlvmPtrType(resultTy.getContext()); auto p = rewriter.create( loc, pty, boxTy.llvm, box, @@ -133,7 +133,7 @@ llvm::SmallVector ConvertFIRToLLVMPattern::getDimsFromBox( mlir::Value ConvertFIRToLLVMPattern::loadDimFieldFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, mlir::Value dim, int off, mlir::Type ty, mlir::ConversionPatternRewriter &rewriter) const { - assert(box.getType().isa() && + assert(mlir::isa(box.getType()) && "descriptor inquiry with runtime dim can only be done on descriptor " "in memory"); mlir::LLVM::GEPOp p = genGEP(loc, boxTy.llvm, rewriter, box, 0, @@ -146,7 +146,7 @@ mlir::Value ConvertFIRToLLVMPattern::loadDimFieldFromBox( mlir::Value ConvertFIRToLLVMPattern::getDimFieldFromBox( mlir::Location loc, TypePair boxTy, mlir::Value box, int dim, int off, mlir::Type ty, mlir::ConversionPatternRewriter &rewriter) const { - if (box.getType().isa()) { + if (mlir::isa(box.getType())) { mlir::LLVM::GEPOp p = genGEP(loc, boxTy.llvm, rewriter, box, 0, static_cast(kDimsPosInBox), dim, off); auto loadOp = rewriter.create(loc, ty, p); @@ -184,12 +184,12 @@ mlir::Value ConvertFIRToLLVMPattern::getElementSizeFromBox( mlir::Type ConvertFIRToLLVMPattern::getBoxEleTy( mlir::Type type, llvm::ArrayRef indexes) const { for (unsigned i : indexes) { - if (auto t = type.dyn_cast()) { + if (auto t = mlir::dyn_cast(type)) { assert(!t.isOpaque() && i < t.getBody().size()); type = t.getBody()[i]; - } else if (auto t = type.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(type)) { type = t.getElementType(); - } else if (auto t = type.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(type)) { type = t.getElementType(); } else { fir::emitFatalError(mlir::UnknownLoc::get(type.getContext()), diff --git a/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp b/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp index 665bf09b8fc3..ce7ee22d5d77 100644 --- a/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp +++ b/flang/lib/Optimizer/CodeGen/PreCGRewrite.cpp @@ -86,10 +86,10 @@ public: // If the embox does not include a shape, then do not convert it if (auto shapeVal = embox.getShape()) return rewriteDynamicShape(embox, rewriter, shapeVal); - if (embox.getType().isa()) + if (mlir::isa(embox.getType())) TODO(embox.getLoc(), "embox conversion for fir.class type"); - if (auto boxTy = embox.getType().dyn_cast()) - if (auto seqTy = boxTy.getEleTy().dyn_cast()) + if (auto boxTy = mlir::dyn_cast(embox.getType())) + if (auto seqTy = mlir::dyn_cast(boxTy.getEleTy())) if (!seqTy.hasDynamicExtents()) return rewriteStaticShape(embox, rewriter, seqTy); return mlir::failure(); @@ -294,10 +294,9 @@ public: target.addIllegalOp(); target.addIllegalOp(); target.addDynamicallyLegalOp([](fir::EmboxOp embox) { - return !(embox.getShape() || embox.getType() - .cast() - .getEleTy() - .isa()); + return !(embox.getShape() || + mlir::isa( + mlir::cast(embox.getType()).getEleTy())); }); mlir::RewritePatternSet patterns(&context); fir::populatePreCGRewritePatterns(patterns); diff --git a/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp b/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp index b1b0e9b766a6..a21384e8d594 100644 --- a/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp +++ b/flang/lib/Optimizer/CodeGen/TBAABuilder.cpp @@ -120,7 +120,7 @@ void TBAABuilder::attachTBAATag(AliasAnalysisOpInterface op, Type baseFIRType, // with both data and descriptor accesses. // Conservatively set any-access tag if there is any descriptor member. tbaaTagSym = getAnyAccessTag(func); - } else if (baseFIRType.isa()) { + } else if (mlir::isa(baseFIRType)) { tbaaTagSym = getBoxAccessTag(baseFIRType, accessFIRType, gep, func); } else { tbaaTagSym = getDataAccessTag(baseFIRType, accessFIRType, gep, func); diff --git a/flang/lib/Optimizer/CodeGen/Target.cpp b/flang/lib/Optimizer/CodeGen/Target.cpp index cea7a1f97f41..652e2bddc1b8 100644 --- a/flang/lib/Optimizer/CodeGen/Target.cpp +++ b/flang/lib/Optimizer/CodeGen/Target.cpp @@ -41,9 +41,9 @@ llvm::StringRef Attributes::getIntExtensionAttrName() const { static const llvm::fltSemantics &floatToSemantics(const KindMapping &kindMap, mlir::Type type) { assert(isa_real(type)); - if (auto ty = type.dyn_cast()) + if (auto ty = mlir::dyn_cast(type)) return kindMap.getFloatSemantics(ty.getFKind()); - return type.cast().getFloatSemantics(); + return mlir::cast(type).getFloatSemantics(); } static void typeTodo(const llvm::fltSemantics *sem, mlir::Location loc, diff --git a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp index 7bf31ec38695..616de78d0026 100644 --- a/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp +++ b/flang/lib/Optimizer/CodeGen/TargetRewrite.cpp @@ -137,7 +137,7 @@ public: if (!hasPortableSignature(dispatch.getFunctionType(), op)) convertCallOp(dispatch); } else if (auto addr = mlir::dyn_cast(op)) { - if (addr.getType().isa() && + if (mlir::isa(addr.getType()) && !hasPortableSignature(addr.getType(), op)) convertAddrOp(addr); } @@ -601,7 +601,7 @@ public: /// Taking the address of a function. Modify the signature as needed. void convertAddrOp(fir::AddrOfOp addrOp) { rewriter->setInsertionPoint(addrOp); - auto addrTy = addrOp.getType().cast(); + auto addrTy = mlir::cast(addrOp.getType()); fir::CodeGenSpecifics::Marshalling newInTyAndAttrs; llvm::SmallVector newResTys; auto loc = addrOp.getLoc(); @@ -705,22 +705,23 @@ public: /// return `true`. Otherwise, the signature is not portable and `false` is /// returned. bool hasPortableSignature(mlir::Type signature, mlir::Operation *op) { - assert(signature.isa()); - auto func = signature.dyn_cast(); + assert(mlir::isa(signature)); + auto func = mlir::dyn_cast(signature); bool hasCCallingConv = isFuncWithCCallingConvention(op); for (auto ty : func.getResults()) - if ((ty.isa() && !noCharacterConversion) || + if ((mlir::isa(ty) && !noCharacterConversion) || (fir::isa_complex(ty) && !noComplexConversion) || - (ty.isa() && hasCCallingConv)) { + (mlir::isa(ty) && hasCCallingConv)) { LLVM_DEBUG(llvm::dbgs() << "rewrite " << signature << " for target\n"); return false; } for (auto ty : func.getInputs()) - if (((ty.isa() || fir::isCharacterProcedureTuple(ty)) && + if (((mlir::isa(ty) || + fir::isCharacterProcedureTuple(ty)) && !noCharacterConversion) || (fir::isa_complex(ty) && !noComplexConversion) || - (ty.isa() && hasCCallingConv) || - (ty.isa() && !noStructConversion)) { + (mlir::isa(ty) && hasCCallingConv) || + (mlir::isa(ty) && !noStructConversion)) { LLVM_DEBUG(llvm::dbgs() << "rewrite " << signature << " for target\n"); return false; } @@ -740,7 +741,7 @@ public: /// Rewrite the signatures and body of the `FuncOp`s in the module for /// the immediately subsequent target code gen. void convertSignature(mlir::func::FuncOp func) { - auto funcTy = func.getFunctionType().cast(); + auto funcTy = mlir::cast(func.getFunctionType()); if (hasPortableSignature(funcTy, func) && !hasHostAssociations(func)) return; llvm::SmallVector newResTys; diff --git a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp index 8fa423f35806..fb2ec3f0b2f5 100644 --- a/flang/lib/Optimizer/CodeGen/TypeConverter.cpp +++ b/flang/lib/Optimizer/CodeGen/TypeConverter.cpp @@ -103,10 +103,10 @@ LLVMTypeConverter::LLVMTypeConverter(mlir::ModuleOp module, bool applyTBAA, for (auto mem : tuple.getTypes()) { // Prevent fir.box from degenerating to a pointer to a descriptor in the // context of a tuple type. - if (auto box = mem.dyn_cast()) + if (auto box = mlir::dyn_cast(mem)) members.push_back(convertBoxTypeAsStruct(box)); else - members.push_back(convertType(mem).cast()); + members.push_back(mlir::cast(convertType(mem))); } return mlir::LLVM::LLVMStructType::getLiteral(&getContext(), members, /*isPacked=*/false); @@ -181,10 +181,10 @@ std::optional LLVMTypeConverter::convertRecordType( for (auto mem : derived.getTypeList()) { // Prevent fir.box from degenerating to a pointer to a descriptor in the // context of a record type. - if (auto box = mem.second.dyn_cast()) + if (auto box = mlir::dyn_cast(mem.second)) members.push_back(convertBoxTypeAsStruct(box)); else - members.push_back(convertType(mem.second).cast()); + members.push_back(mlir::cast(convertType(mem.second))); } if (mlir::failed(st.setBody(members, /*isPacked=*/false))) return mlir::failure(); @@ -196,7 +196,7 @@ std::optional LLVMTypeConverter::convertRecordType( // Extended descriptors are required for derived types. bool LLVMTypeConverter::requiresExtendedDesc(mlir::Type boxElementType) const { auto eleTy = fir::unwrapSequenceType(boxElementType); - return eleTy.isa(); + return mlir::isa(eleTy); } // This corresponds to the descriptor as defined in ISO_Fortran_binding.h and @@ -211,7 +211,8 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, ele = removeIndirection; auto eleTy = convertType(ele); // base_addr* - if (ele.isa() && eleTy.isa()) + if (mlir::isa(ele) && + mlir::isa(eleTy)) dataDescFields.push_back(eleTy); else dataDescFields.push_back( @@ -236,7 +237,7 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, getDescFieldTypeModel()(&getContext())); // [dims] if (rank == unknownRank()) { - if (auto seqTy = ele.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ele)) rank = seqTy.getDimension(); else rank = 0; @@ -252,7 +253,8 @@ mlir::Type LLVMTypeConverter::convertBoxTypeAsStruct(BaseBoxType box, auto rowTy = getExtendedDescFieldTypeModel()(&getContext()); dataDescFields.push_back(mlir::LLVM::LLVMArrayType::get(rowTy, 1)); - if (auto recTy = fir::unwrapSequenceType(ele).dyn_cast()) + if (auto recTy = + mlir::dyn_cast(fir::unwrapSequenceType(ele))) if (recTy.getNumLenParams() > 0) { // The descriptor design needs to be clarified regarding the number of // length parameters in the addendum. Since it can change for diff --git a/flang/lib/Optimizer/Dialect/FIRAttr.cpp b/flang/lib/Optimizer/Dialect/FIRAttr.cpp index e43710f5627e..9ea3a0568f69 100644 --- a/flang/lib/Optimizer/Dialect/FIRAttr.cpp +++ b/flang/lib/Optimizer/Dialect/FIRAttr.cpp @@ -264,23 +264,23 @@ void fir::FortranVariableFlagsAttr::print(mlir::AsmPrinter &printer) const { void fir::printFirAttribute(FIROpsDialect *dialect, mlir::Attribute attr, mlir::DialectAsmPrinter &p) { auto &os = p.getStream(); - if (auto exact = attr.dyn_cast()) { + if (auto exact = mlir::dyn_cast(attr)) { os << fir::ExactTypeAttr::getAttrName() << '<'; p.printType(exact.getType()); os << '>'; - } else if (auto sub = attr.dyn_cast()) { + } else if (auto sub = mlir::dyn_cast(attr)) { os << fir::SubclassAttr::getAttrName() << '<'; p.printType(sub.getType()); os << '>'; - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::PointIntervalAttr::getAttrName(); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::ClosedIntervalAttr::getAttrName(); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::LowerBoundAttr::getAttrName(); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { os << fir::UpperBoundAttr::getAttrName(); - } else if (auto a = attr.dyn_cast_or_null()) { + } else if (auto a = mlir::dyn_cast_or_null(attr)) { os << fir::RealAttr::getAttrName() << '<' << a.getFKind() << ", i x"; llvm::SmallString<40> ss; a.getValue().bitcastToAPInt().toStringUnsigned(ss, 16); diff --git a/flang/lib/Optimizer/Dialect/FIROps.cpp b/flang/lib/Optimizer/Dialect/FIROps.cpp index 24af94f9b90a..a39087aeb358 100644 --- a/flang/lib/Optimizer/Dialect/FIROps.cpp +++ b/flang/lib/Optimizer/Dialect/FIROps.cpp @@ -57,7 +57,7 @@ static void propagateAttributes(mlir::Operation *fromOp, static bool verifyInType(mlir::Type inType, llvm::SmallVectorImpl &visited, unsigned dynamicExtents = 0) { - if (auto st = inType.dyn_cast()) { + if (auto st = mlir::dyn_cast(inType)) { auto shape = st.getShape(); if (shape.size() == 0) return true; @@ -67,7 +67,7 @@ static bool verifyInType(mlir::Type inType, if (dynamicExtents-- == 0) return true; } - } else if (auto rt = inType.dyn_cast()) { + } else if (auto rt = mlir::dyn_cast(inType)) { // don't recurse if we're already visiting this one if (llvm::is_contained(visited, rt.getName())) return false; @@ -84,13 +84,13 @@ static bool verifyInType(mlir::Type inType, static bool verifyTypeParamCount(mlir::Type inType, unsigned numParams) { auto ty = fir::unwrapSequenceType(inType); if (numParams > 0) { - if (auto recTy = ty.dyn_cast()) + if (auto recTy = mlir::dyn_cast(ty)) return numParams != recTy.getNumLenParams(); - if (auto chrTy = ty.dyn_cast()) + if (auto chrTy = mlir::dyn_cast(ty)) return !(numParams == 1 && chrTy.hasDynamicLen()); return true; } - if (auto chrTy = ty.dyn_cast()) + if (auto chrTy = mlir::dyn_cast(ty)) return !chrTy.hasConstantLen(); return false; } @@ -171,13 +171,13 @@ static void printAllocatableOp(mlir::OpAsmPrinter &p, OP &op) { /// Create a legal memory reference as return type static mlir::Type wrapAllocaResultType(mlir::Type intype) { // FIR semantics: memory references to memory references are disallowed - if (intype.isa()) + if (mlir::isa(intype)) return {}; return fir::ReferenceType::get(intype); } mlir::Type fir::AllocaOp::getAllocatedType() { - return getType().cast().getEleTy(); + return mlir::cast(getType()).getEleTy(); } mlir::Type fir::AllocaOp::getRefTy(mlir::Type ty) { @@ -270,7 +270,7 @@ mlir::LogicalResult fir::AllocaOp::verify() { if (verifyTypeParamCount(getInType(), numLenParams())) return emitOpError("LEN params do not correspond to type"); mlir::Type outType = getType(); - if (!outType.isa()) + if (!mlir::isa(outType)) return emitOpError("must be a !fir.ref type"); if (fir::isa_unknown_size_box(fir::dyn_cast_ptrEleTy(outType))) return emitOpError("cannot allocate !fir.box of unknown rank or type"); @@ -286,14 +286,14 @@ static mlir::Type wrapAllocMemResultType(mlir::Type intype) { // Fortran semantics: C852 an entity cannot be both ALLOCATABLE and POINTER // 8.5.3 note 1 prohibits ALLOCATABLE procedures as well // FIR semantics: one may not allocate a memory reference value - if (intype.isa()) + if (mlir::isa(intype)) return {}; return fir::HeapType::get(intype); } mlir::Type fir::AllocMemOp::getAllocatedType() { - return getType().cast().getEleTy(); + return mlir::cast(getType()).getEleTy(); } mlir::Type fir::AllocMemOp::getRefTy(mlir::Type ty) { @@ -348,7 +348,7 @@ mlir::LogicalResult fir::AllocMemOp::verify() { if (verifyTypeParamCount(getInType(), numLenParams())) return emitOpError("LEN params do not correspond to type"); mlir::Type outType = getType(); - if (!outType.dyn_cast()) + if (!mlir::dyn_cast(outType)) return emitOpError("must be a !fir.heap type"); if (fir::isa_unknown_size_box(fir::dyn_cast_ptrEleTy(outType))) return emitOpError("cannot allocate !fir.box of unknown rank or type"); @@ -364,13 +364,13 @@ mlir::LogicalResult fir::AllocMemOp::verify() { static bool validTypeParams(mlir::Type dynTy, mlir::ValueRange typeParams) { dynTy = fir::unwrapAllRefAndSeqType(dynTy); // A box value will contain type parameter values itself. - if (dynTy.isa()) + if (mlir::isa(dynTy)) return typeParams.size() == 0; // Derived type must have all type parameters satisfied. - if (auto recTy = dynTy.dyn_cast()) + if (auto recTy = mlir::dyn_cast(dynTy)) return typeParams.size() == recTy.getNumLenParams(); // Characters with non-constant LEN must have a type parameter value. - if (auto charTy = dynTy.dyn_cast()) + if (auto charTy = mlir::dyn_cast(dynTy)) if (charTy.hasDynamicLen()) return typeParams.size() == 1; // Otherwise, any type parameters are invalid. @@ -379,7 +379,7 @@ static bool validTypeParams(mlir::Type dynTy, mlir::ValueRange typeParams) { mlir::LogicalResult fir::ArrayCoorOp::verify() { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - auto arrTy = eleTy.dyn_cast(); + auto arrTy = mlir::dyn_cast(eleTy); if (!arrTy) return emitOpError("must be a reference to an array"); auto arrDim = arrTy.getDimension(); @@ -387,14 +387,14 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { if (auto shapeOp = getShape()) { auto shapeTy = shapeOp.getType(); unsigned shapeTyRank = 0; - if (auto s = shapeTy.dyn_cast()) { + if (auto s = mlir::dyn_cast(shapeTy)) { shapeTyRank = s.getRank(); - } else if (auto ss = shapeTy.dyn_cast()) { + } else if (auto ss = mlir::dyn_cast(shapeTy)) { shapeTyRank = ss.getRank(); } else { - auto s = shapeTy.cast(); + auto s = mlir::cast(shapeTy); shapeTyRank = s.getRank(); - if (!getMemref().getType().isa()) + if (!mlir::isa(getMemref().getType())) return emitOpError("shift can only be provided with fir.box memref"); } if (arrDim && arrDim != shapeTyRank) @@ -407,7 +407,7 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { if (auto sl = mlir::dyn_cast_or_null(sliceOp.getDefiningOp())) if (!sl.getSubstr().empty()) return emitOpError("array_coor cannot take a slice with substring"); - if (auto sliceTy = sliceOp.getType().dyn_cast()) + if (auto sliceTy = mlir::dyn_cast(sliceOp.getType())) if (sliceTy.getRank() != arrDim) return emitOpError("rank of dimension in slice mismatched"); } @@ -422,13 +422,13 @@ mlir::LogicalResult fir::ArrayCoorOp::verify() { //===----------------------------------------------------------------------===// static mlir::Type adjustedElementType(mlir::Type t) { - if (auto ty = t.dyn_cast()) { + if (auto ty = mlir::dyn_cast(t)) { auto eleTy = ty.getEleTy(); if (fir::isa_char(eleTy)) return eleTy; if (fir::isa_derived(eleTy)) return eleTy; - if (eleTy.isa()) + if (mlir::isa(eleTy)) return eleTy; } return t; @@ -448,7 +448,7 @@ std::vector fir::ArrayLoadOp::getExtents() { mlir::LogicalResult fir::ArrayLoadOp::verify() { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - auto arrTy = eleTy.dyn_cast(); + auto arrTy = mlir::dyn_cast(eleTy); if (!arrTy) return emitOpError("must be a reference to an array"); auto arrDim = arrTy.getDimension(); @@ -456,14 +456,14 @@ mlir::LogicalResult fir::ArrayLoadOp::verify() { if (auto shapeOp = getShape()) { auto shapeTy = shapeOp.getType(); unsigned shapeTyRank = 0u; - if (auto s = shapeTy.dyn_cast()) { + if (auto s = mlir::dyn_cast(shapeTy)) { shapeTyRank = s.getRank(); - } else if (auto ss = shapeTy.dyn_cast()) { + } else if (auto ss = mlir::dyn_cast(shapeTy)) { shapeTyRank = ss.getRank(); } else { - auto s = shapeTy.cast(); + auto s = mlir::cast(shapeTy); shapeTyRank = s.getRank(); - if (!getMemref().getType().isa()) + if (!mlir::isa(getMemref().getType())) return emitOpError("shift can only be provided with fir.box memref"); } if (arrDim && arrDim != shapeTyRank) @@ -474,7 +474,7 @@ mlir::LogicalResult fir::ArrayLoadOp::verify() { if (auto sl = mlir::dyn_cast_or_null(sliceOp.getDefiningOp())) if (!sl.getSubstr().empty()) return emitOpError("array_load cannot take a slice with substring"); - if (auto sliceTy = sliceOp.getType().dyn_cast()) + if (auto sliceTy = mlir::dyn_cast(sliceOp.getType())) if (sliceTy.getRank() != arrDim) return emitOpError("rank of dimension in slice mismatched"); } @@ -502,7 +502,7 @@ mlir::LogicalResult fir::ArrayMergeStoreOp::verify() { // This is an intra-object merge, where the slice is projecting the // subfields that are to be overwritten by the merge operation. auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(getMemref().getType()); - if (auto seqTy = eleTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(eleTy)) { auto projTy = fir::applyPathToType(seqTy.getEleTy(), sliceOp.getFields()); if (fir::unwrapSequenceType(getOriginal().getType()) != projTy) @@ -540,7 +540,7 @@ mlir::Type validArraySubobject(A op) { } mlir::LogicalResult fir::ArrayFetchOp::verify() { - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -562,7 +562,7 @@ mlir::LogicalResult fir::ArrayFetchOp::verify() { //===----------------------------------------------------------------------===// mlir::LogicalResult fir::ArrayAccessOp::verify() { - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); std::size_t indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -584,7 +584,7 @@ mlir::LogicalResult fir::ArrayAccessOp::verify() { mlir::LogicalResult fir::ArrayUpdateOp::verify() { if (fir::isa_ref_type(getMerge().getType())) return emitOpError("does not support reference type for merge"); - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices != dimension of array"); @@ -604,7 +604,7 @@ mlir::LogicalResult fir::ArrayUpdateOp::verify() { //===----------------------------------------------------------------------===// mlir::LogicalResult fir::ArrayModifyOp::verify() { - auto arrTy = getSequence().getType().cast(); + auto arrTy = mlir::cast(getSequence().getType()); auto indSize = getIndices().size(); if (indSize < arrTy.getDimension()) return emitOpError("number of indices must match array dimension"); @@ -740,7 +740,7 @@ mlir::ParseResult fir::CallOp::parse(mlir::OpAsmParser &parser, parser.parseType(type)) return mlir::failure(); - auto funcType = type.dyn_cast(); + auto funcType = mlir::dyn_cast(type); if (!funcType) return parser.emitError(parser.getNameLoc(), "expected function type"); if (isDirect) { @@ -785,7 +785,7 @@ void fir::CallOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, mlir::LogicalResult fir::CharConvertOp::verify() { auto unwrap = [&](mlir::Type t) { t = fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t)); - return t.dyn_cast(); + return mlir::dyn_cast(t); }; auto inTy = unwrap(getFrom().getType()); auto outTy = unwrap(getTo().getType()); @@ -832,13 +832,13 @@ static mlir::ParseResult parseCmpOp(mlir::OpAsmParser &parser, parser.resolveOperands(ops, type, result.operands)) return mlir::failure(); - if (!predicateNameAttr.isa()) + if (!mlir::isa(predicateNameAttr)) return parser.emitError(parser.getNameLoc(), "expected string comparison predicate attribute"); // Rewrite string attribute to an enum value. llvm::StringRef predicateName = - predicateNameAttr.cast().getValue(); + mlir::cast(predicateNameAttr).getValue(); auto predicate = fir::CmpcOp::getPredicateByName(predicateName); auto builder = parser.getBuilder(); mlir::Type i1Type = builder.getI1Type(); @@ -906,7 +906,7 @@ void fir::ConstcOp::print(mlir::OpAsmPrinter &p) { } mlir::LogicalResult fir::ConstcOp::verify() { - if (!getType().isa()) + if (!mlir::isa(getType())) return emitOpError("must be a !fir.complex type"); return mlir::success(); } @@ -929,15 +929,16 @@ mlir::OpFoldResult fir::ConvertOp::fold(FoldAdaptor adaptor) { if (matchPattern(getValue(), mlir::m_Op())) { auto inner = mlir::cast(getValue().getDefiningOp()); // (convert (convert 'a : logical -> i1) : i1 -> logical) ==> forward 'a - if (auto toTy = getType().dyn_cast()) - if (auto fromTy = inner.getValue().getType().dyn_cast()) - if (inner.getType().isa() && (toTy == fromTy)) + if (auto toTy = mlir::dyn_cast(getType())) + if (auto fromTy = + mlir::dyn_cast(inner.getValue().getType())) + if (mlir::isa(inner.getType()) && (toTy == fromTy)) return inner.getValue(); // (convert (convert 'a : i1 -> logical) : logical -> i1) ==> forward 'a - if (auto toTy = getType().dyn_cast()) + if (auto toTy = mlir::dyn_cast(getType())) if (auto fromTy = - inner.getValue().getType().dyn_cast()) - if (inner.getType().isa() && (toTy == fromTy) && + mlir::dyn_cast(inner.getValue().getType())) + if (mlir::isa(inner.getType()) && (toTy == fromTy) && (fromTy.getWidth() == 1)) return inner.getValue(); } @@ -945,7 +946,7 @@ mlir::OpFoldResult fir::ConvertOp::fold(FoldAdaptor adaptor) { } bool fir::ConvertOp::isInteger(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } bool fir::ConvertOp::isIntegerCompatible(mlir::Type ty) { @@ -953,13 +954,13 @@ bool fir::ConvertOp::isIntegerCompatible(mlir::Type ty) { } bool fir::ConvertOp::isFloatCompatible(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } bool fir::ConvertOp::isPointerCompatible(mlir::Type ty) { - return ty.isa(); + return mlir::isa(ty); } static std::optional getVectorElementType(mlir::Type ty) { @@ -1026,12 +1027,14 @@ bool fir::ConvertOp::canBeConverted(mlir::Type inType, mlir::Type outType) { (isFloatCompatible(inType) && isFloatCompatible(outType)) || (isIntegerCompatible(inType) && isPointerCompatible(outType)) || (isPointerCompatible(inType) && isIntegerCompatible(outType)) || - (inType.isa() && outType.isa()) || - (inType.isa() && outType.isa()) || + (mlir::isa(inType) && + mlir::isa(outType)) || + (mlir::isa(inType) && + mlir::isa(outType)) || (fir::isa_complex(inType) && fir::isa_complex(outType)) || (fir::isBoxedRecordType(inType) && fir::isPolymorphicType(outType)) || (fir::isPolymorphicType(inType) && fir::isPolymorphicType(outType)) || - (fir::isPolymorphicType(inType) && outType.isa()) || + (fir::isPolymorphicType(inType) && mlir::isa(outType)) || areVectorsCompatible(inType, outType); } @@ -1079,7 +1082,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { const mlir::Type refTy = getRef().getType(); if (fir::isa_ref_type(refTy)) { auto eleTy = fir::dyn_cast_ptrEleTy(refTy); - if (auto arrTy = eleTy.dyn_cast()) { + if (auto arrTy = mlir::dyn_cast(eleTy)) { if (arrTy.hasUnknownShape()) return emitOpError("cannot find coordinate in unknown shape"); if (arrTy.getConstantRows() < arrTy.getDimension() - 1) @@ -1094,8 +1097,8 @@ mlir::LogicalResult fir::CoordinateOp::verify() { const unsigned numCoors = getCoor().size(); for (auto coorOperand : llvm::enumerate(getCoor())) { auto co = coorOperand.value(); - if (dimension == 0 && eleTy.isa()) { - dimension = eleTy.cast().getDimension(); + if (dimension == 0 && mlir::isa(eleTy)) { + dimension = mlir::cast(eleTy).getDimension(); if (dimension == 0) return emitOpError("cannot apply to array of unknown rank"); } @@ -1104,7 +1107,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { // Recovering a LEN type parameter only makes sense from a boxed // value. For a bare reference, the LEN type parameters must be // passed as additional arguments to `index`. - if (refTy.isa()) { + if (mlir::isa(refTy)) { if (coorOperand.index() != numCoors - 1) return emitOpError("len_param_index must be last argument"); if (getNumOperands() != 2) @@ -1117,7 +1120,7 @@ mlir::LogicalResult fir::CoordinateOp::verify() { } else if (auto index = mlir::dyn_cast(defOp)) { if (eleTy != index.getOnType()) emitOpError("field_index type not compatible with reference type"); - if (auto recTy = eleTy.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(eleTy)) { eleTy = recTy.getType(index.getFieldName()); continue; } @@ -1126,21 +1129,21 @@ mlir::LogicalResult fir::CoordinateOp::verify() { } if (dimension) { if (--dimension == 0) - eleTy = eleTy.cast().getEleTy(); + eleTy = mlir::cast(eleTy).getEleTy(); } else { - if (auto t = eleTy.dyn_cast()) { + if (auto t = mlir::dyn_cast(eleTy)) { // FIXME: Generally, we don't know which field of the tuple is being // referred to unless the operand is a constant. Just assume everything // is good in the tuple case for now. return mlir::success(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { // FIXME: This is the same as the tuple case. return mlir::success(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { eleTy = t.getElementType(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { eleTy = t.getElementType(); - } else if (auto t = eleTy.dyn_cast()) { + } else if (auto t = mlir::dyn_cast(eleTy)) { if (t.getLen() == fir::CharacterType::singleton()) return emitOpError("cannot apply to character singleton"); eleTy = fir::CharacterType::getSingleton(t.getContext(), t.getFKind()); @@ -1216,17 +1219,17 @@ mlir::LogicalResult fir::TypeInfoOp::verify() { mlir::LogicalResult fir::EmboxOp::verify() { auto eleTy = fir::dyn_cast_ptrEleTy(getMemref().getType()); bool isArray = false; - if (auto seqTy = eleTy.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(eleTy)) { eleTy = seqTy.getEleTy(); isArray = true; } if (hasLenParams()) { auto lenPs = numLenParams(); - if (auto rt = eleTy.dyn_cast()) { + if (auto rt = mlir::dyn_cast(eleTy)) { if (lenPs != rt.getNumLenParams()) return emitOpError("number of LEN params does not correspond" " to the !fir.type type"); - } else if (auto strTy = eleTy.dyn_cast()) { + } else if (auto strTy = mlir::dyn_cast(eleTy)) { if (strTy.getLen() != fir::CharacterType::unknownLen()) return emitOpError("CHARACTER already has static LEN"); } else { @@ -1240,7 +1243,7 @@ mlir::LogicalResult fir::EmboxOp::verify() { return emitOpError("shape must not be provided for a scalar"); if (getSlice() && !isArray) return emitOpError("slice must not be provided for a scalar"); - if (getSourceBox() && !getResult().getType().isa()) + if (getSourceBox() && !mlir::isa(getResult().getType())) return emitOpError("source_box must be used with fir.class result type"); return mlir::success(); } @@ -1251,7 +1254,7 @@ mlir::LogicalResult fir::EmboxOp::verify() { mlir::LogicalResult fir::EmboxCharOp::verify() { auto eleTy = fir::dyn_cast_ptrEleTy(getMemref().getType()); - if (!eleTy.dyn_cast_or_null()) + if (!mlir::dyn_cast_or_null(eleTy)) return mlir::failure(); return mlir::success(); } @@ -1263,8 +1266,8 @@ mlir::LogicalResult fir::EmboxCharOp::verify() { mlir::LogicalResult fir::EmboxProcOp::verify() { // host bindings (optional) must be a reference to a tuple if (auto h = getHost()) { - if (auto r = h.getType().dyn_cast()) - if (r.getEleTy().isa()) + if (auto r = mlir::dyn_cast(h.getType())) + if (mlir::isa(r.getEleTy())) return mlir::success(); return mlir::failure(); } @@ -1300,7 +1303,7 @@ void fir::TypeDescOp::print(mlir::OpAsmPrinter &p) { mlir::LogicalResult fir::TypeDescOp::verify() { mlir::Type resultTy = getType(); - if (auto tdesc = resultTy.dyn_cast()) { + if (auto tdesc = mlir::dyn_cast(resultTy)) { if (tdesc.getOfTy() != getInType()) return emitOpError("wrapped type mismatched"); return mlir::success(); @@ -1527,7 +1530,7 @@ mlir::ParseResult parseFieldLikeOp(mlir::OpAsmParser &parser, return mlir::failure(); result.addAttribute(fir::FieldIndexOp::getFieldAttrName(), builder.getStringAttr(fieldName)); - if (!recty.dyn_cast()) + if (!mlir::dyn_cast(recty)) return mlir::failure(); result.addAttribute(fir::FieldIndexOp::getTypeAttrName(), mlir::TypeAttr::get(recty)); @@ -1671,7 +1674,7 @@ mlir::LogicalResult fir::InsertOnRangeOp::verify() { //===----------------------------------------------------------------------===// static bool checkIsIntegerConstant(mlir::Attribute attr, std::int64_t conVal) { - if (auto iattr = attr.dyn_cast()) + if (auto iattr = mlir::dyn_cast(attr)) return iattr.getInt() == conVal; return false; } @@ -1690,7 +1693,7 @@ struct UndoComplexPattern : public mlir::RewritePattern { matchAndRewrite(mlir::Operation *op, mlir::PatternRewriter &rewriter) const override { auto insval = mlir::dyn_cast_or_null(op); - if (!insval || !insval.getType().isa()) + if (!insval || !mlir::isa(insval.getType())) return mlir::failure(); auto insval2 = mlir::dyn_cast_or_null( insval.getAdt().getDefiningOp()); @@ -1819,7 +1822,7 @@ mlir::ParseResult fir::IterWhileOp::parse(mlir::OpAsmParser &parser, parser.parseRParen()) return mlir::failure(); // Type list must be "(index, i1)". - if (typeList.size() != 2 || !typeList[0].isa() || + if (typeList.size() != 2 || !mlir::isa(typeList[0]) || !typeList[1].isSignlessInteger(1)) return mlir::failure(); result.addTypes(typeList); @@ -1873,7 +1876,7 @@ mlir::LogicalResult fir::IterWhileOp::verify() { auto opNumResults = getNumResults(); if (getFinalValue()) { // Result type must be "(index, i1, ...)". - if (!getResult(0).getType().isa()) + if (!mlir::isa(getResult(0).getType())) return emitOpError("result #0 expected to be index"); if (!getResult(1).getType().isSignlessInteger(1)) return emitOpError("result #1 expected to be i1"); @@ -2316,7 +2319,7 @@ void fir::DTEntryOp::print(mlir::OpAsmPrinter &p) { /// Example: return f32 for !fir.box>. static mlir::Type getBoxScalarEleTy(mlir::Type boxTy) { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(boxTy); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); return eleTy; } @@ -2324,8 +2327,8 @@ static mlir::Type getBoxScalarEleTy(mlir::Type boxTy) { /// Test if \p t1 and \p t2 are compatible character types (if they can /// represent the same type at runtime). static bool areCompatibleCharacterTypes(mlir::Type t1, mlir::Type t2) { - auto c1 = t1.dyn_cast(); - auto c2 = t2.dyn_cast(); + auto c1 = mlir::dyn_cast(t1); + auto c2 = mlir::dyn_cast(t2); if (!c1 || !c2) return false; if (c1.hasDynamicLen() || c2.hasDynamicLen()) @@ -2347,10 +2350,10 @@ mlir::LogicalResult fir::ReboxOp::verify() { if (auto sliceVal = getSlice()) { // Slicing case - if (sliceVal.getType().cast().getRank() != inputRank) + if (mlir::cast(sliceVal.getType()).getRank() != inputRank) return emitOpError("slice operand rank must match box operand rank"); if (auto shapeVal = getShape()) { - if (auto shiftTy = shapeVal.getType().dyn_cast()) { + if (auto shiftTy = mlir::dyn_cast(shapeVal.getType())) { if (shiftTy.getRank() != inputRank) return emitOpError("shape operand and input box ranks must match " "when there is a slice"); @@ -2370,12 +2373,12 @@ mlir::LogicalResult fir::ReboxOp::verify() { unsigned shapeRank = inputRank; if (auto shapeVal = getShape()) { auto ty = shapeVal.getType(); - if (auto shapeTy = ty.dyn_cast()) { + if (auto shapeTy = mlir::dyn_cast(ty)) { shapeRank = shapeTy.getRank(); - } else if (auto shapeShiftTy = ty.dyn_cast()) { + } else if (auto shapeShiftTy = mlir::dyn_cast(ty)) { shapeRank = shapeShiftTy.getRank(); } else { - auto shiftTy = ty.cast(); + auto shiftTy = mlir::cast(ty); shapeRank = shiftTy.getRank(); if (shapeRank != inputRank) return emitOpError("shape operand and input box ranks must match " @@ -2394,11 +2397,13 @@ mlir::LogicalResult fir::ReboxOp::verify() { // the types is a character with dynamic length, the other type can be any // character type. const bool typeCanMismatch = - inputEleTy.isa() || outEleTy.isa() || - (inputEleTy.isa() && outEleTy.isa()) || - (getSlice() && inputEleTy.isa()) || + mlir::isa(inputEleTy) || + mlir::isa(outEleTy) || + (mlir::isa(inputEleTy) && + mlir::isa(outEleTy)) || + (getSlice() && mlir::isa(inputEleTy)) || (getSlice() && fir::isa_complex(inputEleTy) && - outEleTy.isa()) || + mlir::isa(outEleTy)) || areCompatibleCharacterTypes(inputEleTy, outEleTy); if (!typeCanMismatch) return emitOpError( @@ -2435,7 +2440,7 @@ mlir::LogicalResult fir::SaveResultOp::verify() { if (fir::isa_unknown_size_box(resultType)) return emitOpError("cannot save !fir.box of unknown rank or type"); - if (resultType.isa()) { + if (mlir::isa(resultType)) { if (getShape() || !getTypeparams().empty()) return emitOpError( "must not have shape or length operands if the value is a fir.box"); @@ -2446,14 +2451,14 @@ mlir::LogicalResult fir::SaveResultOp::verify() { unsigned shapeTyRank = 0; if (auto shapeVal = getShape()) { auto shapeTy = shapeVal.getType(); - if (auto s = shapeTy.dyn_cast()) + if (auto s = mlir::dyn_cast(shapeTy)) shapeTyRank = s.getRank(); else - shapeTyRank = shapeTy.cast().getRank(); + shapeTyRank = mlir::cast(shapeTy).getRank(); } auto eleTy = resultType; - if (auto seqTy = resultType.dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(resultType)) { if (seqTy.getDimension() != shapeTyRank) emitOpError("shape operand must be provided and have the value rank " "when the value is a fir.array"); @@ -2464,11 +2469,11 @@ mlir::LogicalResult fir::SaveResultOp::verify() { "shape operand should only be provided if the value is a fir.array"); } - if (auto recTy = eleTy.dyn_cast()) { + if (auto recTy = mlir::dyn_cast(eleTy)) { if (recTy.getNumLenParams() != getTypeparams().size()) emitOpError("length parameters number must match with the value type " "length parameters"); - } else if (auto charTy = eleTy.dyn_cast()) { + } else if (auto charTy = mlir::dyn_cast(eleTy)) { if (getTypeparams().size() > 1) emitOpError("no more than one length parameter must be provided for " "character value"); @@ -2508,7 +2513,7 @@ static mlir::LogicalResult verifyIntegralSwitchTerminator(OpT op) { if (op.targetOffsetSize() != count) return op.emitOpError("incorrect number of successor operand groups"); for (decltype(count) i = 0; i != count; ++i) { - if (!cases[i].template isa()) + if (!mlir::isa(cases[i])) return op.emitOpError("invalid case alternative"); } return mlir::success(); @@ -2620,7 +2625,7 @@ getMutableSuccessorOperands(unsigned pos, mlir::MutableOperandRange operands, *owner->getAttrDictionary().getNamed(offsetAttr); return getSubOperands( pos, operands, - targetOffsetAttr.getValue().cast(), + mlir::cast(targetOffsetAttr.getValue()), mlir::MutableOperandRange::OperandSegment(pos, targetOffsetAttr)); } @@ -2742,9 +2747,9 @@ mlir::ParseResult fir::SelectCaseOp::parse(mlir::OpAsmParser &parser, parser.parseComma()) return mlir::failure(); attrs.push_back(attr); - if (attr.dyn_cast_or_null()) { + if (mlir::dyn_cast_or_null(attr)) { argOffs.push_back(0); - } else if (attr.dyn_cast_or_null()) { + } else if (mlir::dyn_cast_or_null(attr)) { mlir::OpAsmParser::UnresolvedOperand oper1; mlir::OpAsmParser::UnresolvedOperand oper2; if (parser.parseOperand(oper1) || parser.parseComma() || @@ -2806,11 +2811,11 @@ void fir::SelectCaseOp::print(mlir::OpAsmPrinter &p) { if (i) p << ", "; p << cases[i] << ", "; - if (!cases[i].isa()) { + if (!mlir::isa(cases[i])) { auto caseArgs = *getCompareOperands(i); p.printOperand(*caseArgs.begin()); p << ", "; - if (cases[i].isa()) { + if (mlir::isa(cases[i])) { p.printOperand(*(++caseArgs.begin())); p << ", "; } @@ -2848,10 +2853,10 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, llvm::SmallVector operOffs; int32_t operSize = 0; for (auto attr : compareAttrs) { - if (attr.isa()) { + if (mlir::isa(attr)) { operOffs.push_back(2); operSize += 2; - } else if (attr.isa()) { + } else if (mlir::isa(attr)) { operOffs.push_back(0); } else { operOffs.push_back(1); @@ -2900,10 +2905,10 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, llvm::SmallVector cmpOpers; auto iter = cmpOpList.begin(); for (auto &attr : compareAttrs) { - if (attr.isa()) { + if (mlir::isa(attr)) { cmpOpers.push_back(mlir::ValueRange({iter, iter + 2})); iter += 2; - } else if (attr.isa()) { + } else if (mlir::isa(attr)) { cmpOpers.push_back(mlir::ValueRange{}); } else { cmpOpers.push_back(mlir::ValueRange({iter, iter + 1})); @@ -2915,10 +2920,8 @@ void fir::SelectCaseOp::build(mlir::OpBuilder &builder, } mlir::LogicalResult fir::SelectCaseOp::verify() { - if (!getSelector() - .getType() - .isa()) + if (!mlir::isa(getSelector().getType())) return emitOpError("must be an integer, character, or logical"); auto cases = getOperation()->getAttrOfType(getCasesAttr()).getValue(); @@ -2933,9 +2936,11 @@ mlir::LogicalResult fir::SelectCaseOp::verify() { return emitOpError("incorrect number of successor operand groups"); for (decltype(count) i = 0; i != count; ++i) { auto &attr = cases[i]; - if (!(attr.isa() || - attr.isa() || attr.isa() || - attr.isa() || attr.isa())) + if (!(mlir::isa(attr) || + mlir::isa(attr) || + mlir::isa(attr) || + mlir::isa(attr) || + mlir::isa(attr))) return emitOpError("incorrect select case attribute type"); } return mlir::success(); @@ -3111,14 +3116,14 @@ void fir::SelectTypeOp::print(mlir::OpAsmPrinter &p) { } mlir::LogicalResult fir::SelectTypeOp::verify() { - if (!(getSelector().getType().isa())) + if (!mlir::isa(getSelector().getType())) return emitOpError("must be a fir.class or fir.box type"); - if (auto boxType = getSelector().getType().dyn_cast()) - if (!boxType.getEleTy().isa()) + if (auto boxType = mlir::dyn_cast(getSelector().getType())) + if (!mlir::isa(boxType.getEleTy())) return emitOpError("selector must be polymorphic"); auto typeGuardAttr = getCases(); for (unsigned idx = 0; idx < typeGuardAttr.size(); ++idx) - if (typeGuardAttr[idx].isa() && + if (mlir::isa(typeGuardAttr[idx]) && idx != typeGuardAttr.size() - 1) return emitOpError("default must be the last attribute"); auto count = getNumDest(); @@ -3129,9 +3134,8 @@ mlir::LogicalResult fir::SelectTypeOp::verify() { if (targetOffsetSize() != count) return emitOpError("incorrect number of successor operand groups"); for (unsigned i = 0; i != count; ++i) { - if (!(typeGuardAttr[i].isa() || - typeGuardAttr[i].isa() || - typeGuardAttr[i].isa())) + if (!mlir::isa( + typeGuardAttr[i])) return emitOpError("invalid type-case alternative"); } return mlir::success(); @@ -3175,7 +3179,7 @@ void fir::SelectTypeOp::build(mlir::OpBuilder &builder, mlir::LogicalResult fir::ShapeOp::verify() { auto size = getExtents().size(); - auto shapeTy = getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(getType()); assert(shapeTy && "must be a shape type"); if (shapeTy.getRank() != size) return emitOpError("shape type rank mismatch"); @@ -3198,7 +3202,7 @@ mlir::LogicalResult fir::ShapeShiftOp::verify() { return emitOpError("incorrect number of args"); if (size % 2 != 0) return emitOpError("requires a multiple of 2 args"); - auto shapeTy = getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(getType()); assert(shapeTy && "must be a shape shift type"); if (shapeTy.getRank() * 2 != size) return emitOpError("shape type rank mismatch"); @@ -3211,7 +3215,7 @@ mlir::LogicalResult fir::ShapeShiftOp::verify() { mlir::LogicalResult fir::ShiftOp::verify() { auto size = getOrigins().size(); - auto shiftTy = getType().dyn_cast(); + auto shiftTy = mlir::dyn_cast(getType()); assert(shiftTy && "must be a shift type"); if (shiftTy.getRank() != size) return emitOpError("shift type rank mismatch"); @@ -3251,7 +3255,7 @@ mlir::LogicalResult fir::SliceOp::verify() { return emitOpError("incorrect number of args for triple"); if (size % 3 != 0) return emitOpError("requires a multiple of 3 args"); - auto sliceTy = getType().dyn_cast(); + auto sliceTy = mlir::dyn_cast(getType()); assert(sliceTy && "must be a slice type"); if (sliceTy.getRank() * 3 != size) return emitOpError("slice type rank mismatch"); @@ -3309,8 +3313,8 @@ void fir::StoreOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, //===----------------------------------------------------------------------===// inline fir::CharacterType::KindTy stringLitOpGetKind(fir::StringLitOp op) { - auto eleTy = op.getType().cast().getEleTy(); - return eleTy.cast().getFKind(); + auto eleTy = mlir::cast(op.getType()).getEleTy(); + return mlir::cast(eleTy).getFKind(); } bool fir::StringLitOp::isWideValue() { return stringLitOpGetKind(*this) != 1; } @@ -3390,13 +3394,13 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, llvm::SMLoc trailingTypeLoc; if (parser.parseAttribute(val, "fake", attrs)) return mlir::failure(); - if (auto v = val.dyn_cast()) + if (auto v = mlir::dyn_cast(val)) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::value(), v)); - else if (auto v = val.dyn_cast()) + else if (auto v = mlir::dyn_cast(val)) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::xlist(), v)); - else if (auto v = val.dyn_cast()) + else if (auto v = mlir::dyn_cast(val)) result.attributes.push_back( builder.getNamedAttr(fir::StringLitOp::xlist(), v)); else @@ -3409,7 +3413,7 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, parser.parseRParen() || parser.getCurrentLocation(&trailingTypeLoc) || parser.parseColonType(type)) return mlir::failure(); - auto charTy = type.dyn_cast(); + auto charTy = mlir::dyn_cast(type); if (!charTy) return parser.emitError(trailingTypeLoc, "must have character type"); type = fir::CharacterType::get(builder.getContext(), charTy.getFKind(), @@ -3421,19 +3425,19 @@ mlir::ParseResult fir::StringLitOp::parse(mlir::OpAsmParser &parser, void fir::StringLitOp::print(mlir::OpAsmPrinter &p) { p << ' ' << getValue() << '('; - p << getSize().cast().getValue() << ") : "; + p << mlir::cast(getSize()).getValue() << ") : "; p.printType(getType()); } mlir::LogicalResult fir::StringLitOp::verify() { - if (getSize().cast().getValue().isNegative()) + if (mlir::cast(getSize()).getValue().isNegative()) return emitOpError("size must be non-negative"); if (auto xl = getOperation()->getAttr(fir::StringLitOp::xlist())) { - if (auto xList = xl.dyn_cast()) { + if (auto xList = mlir::dyn_cast(xl)) { for (auto a : xList) - if (!a.isa()) + if (!mlir::isa(a)) return emitOpError("values in initializer must be integers"); - } else if (xl.isa()) { + } else if (mlir::isa(xl)) { // do nothing } else { return emitOpError("has unexpected attribute"); @@ -3448,7 +3452,7 @@ mlir::LogicalResult fir::StringLitOp::verify() { mlir::LogicalResult fir::UnboxProcOp::verify() { if (auto eleTy = fir::dyn_cast_ptrEleTy(getRefTuple().getType())) - if (eleTy.isa()) + if (mlir::isa(eleTy)) return mlir::success(); return emitOpError("second output argument has bad type"); } @@ -3527,7 +3531,7 @@ void fir::IfOp::getEntrySuccessorRegions( void fir::IfOp::getRegionInvocationBounds( llvm::ArrayRef operands, llvm::SmallVectorImpl &invocationBounds) { - if (auto cond = operands[0].dyn_cast_or_null()) { + if (auto cond = mlir::dyn_cast_or_null(operands[0])) { // If the condition is known, then one region is known to be executed once // and the other zero times. invocationBounds.emplace_back(0, cond.getValue() ? 1 : 0); @@ -3646,8 +3650,8 @@ void fir::BoxOffsetOp::build(mlir::OpBuilder &builder, //===----------------------------------------------------------------------===// mlir::ParseResult fir::isValidCaseAttr(mlir::Attribute attr) { - if (attr.isa()) + if (mlir::isa(attr)) return mlir::success(); return mlir::failure(); } @@ -3657,9 +3661,9 @@ unsigned fir::getCaseArgumentOffset(llvm::ArrayRef cases, unsigned o = 0; for (unsigned i = 0; i < dest; ++i) { auto &attr = cases[i]; - if (!attr.dyn_cast_or_null()) { + if (!mlir::dyn_cast_or_null(attr)) { ++o; - if (attr.dyn_cast_or_null()) + if (mlir::dyn_cast_or_null(attr)) ++o; } } @@ -3722,7 +3726,7 @@ fir::GlobalOp fir::createGlobalOp(mlir::Location loc, mlir::ModuleOp module, bool fir::hasHostAssociationArgument(mlir::func::FuncOp func) { if (auto allArgAttrs = func.getAllArgAttrs()) for (auto attr : allArgAttrs) - if (auto dict = attr.template dyn_cast_or_null()) + if (auto dict = mlir::dyn_cast_or_null(attr)) if (dict.get(fir::getHostAssocAttrName())) return true; return false; @@ -3772,7 +3776,7 @@ valueCheckFirAttributes(mlir::Value value, }; // If this is a fir.box that was loaded, the fir attributes will be on the // related fir.ref creation. - if (value.getType().isa()) + if (mlir::isa(value.getType())) if (auto definingOp = value.getDefiningOp()) if (auto loadOp = mlir::dyn_cast(definingOp)) value = loadOp.getMemref(); @@ -3837,10 +3841,10 @@ bool fir::anyFuncArgsHaveAttr(mlir::func::FuncOp func, llvm::StringRef attr) { std::optional fir::getIntIfConstant(mlir::Value value) { if (auto *definingOp = value.getDefiningOp()) { if (auto cst = mlir::dyn_cast(definingOp)) - if (auto intAttr = cst.getValue().dyn_cast()) + if (auto intAttr = mlir::dyn_cast(cst.getValue())) return intAttr.getInt(); if (auto llConstOp = mlir::dyn_cast(definingOp)) - if (auto attr = llConstOp.getValue().dyn_cast()) + if (auto attr = mlir::dyn_cast(llConstOp.getValue())) return attr.getValue().getSExtValue(); } return {}; @@ -4002,15 +4006,15 @@ mlir::LogicalResult fir::CUDAKernelOp::verify() { mlir::LogicalResult fir::CUDAAllocateOp::verify() { if (getPinned() && getStream()) return emitOpError("pinned and stream cannot appears at the same time"); - if (!fir::unwrapRefType(getBox().getType()).isa()) + if (!mlir::isa(fir::unwrapRefType(getBox().getType()))) return emitOpError( "expect box to be a reference to a class or box type value"); if (getSource() && - !fir::unwrapRefType(getSource().getType()).isa()) + !mlir::isa(fir::unwrapRefType(getSource().getType()))) return emitOpError( "expect source to be a reference to/or a class or box type value"); if (getErrmsg() && - !fir::unwrapRefType(getErrmsg().getType()).isa()) + !mlir::isa(fir::unwrapRefType(getErrmsg().getType()))) return emitOpError( "expect errmsg to be a reference to/or a box type value"); if (getErrmsg() && !getHasStat()) @@ -4019,11 +4023,11 @@ mlir::LogicalResult fir::CUDAAllocateOp::verify() { } mlir::LogicalResult fir::CUDADeallocateOp::verify() { - if (!fir::unwrapRefType(getBox().getType()).isa()) + if (!mlir::isa(fir::unwrapRefType(getBox().getType()))) return emitOpError( "expect box to be a reference to class or box type value"); if (getErrmsg() && - !fir::unwrapRefType(getErrmsg().getType()).isa()) + !mlir::isa(fir::unwrapRefType(getErrmsg().getType()))) return emitOpError( "expect errmsg to be a reference to/or a box type value"); if (getErrmsg() && !getHasStat()) diff --git a/flang/lib/Optimizer/Dialect/FIRType.cpp b/flang/lib/Optimizer/Dialect/FIRType.cpp index 5c4cad6d2083..38a6a09d1808 100644 --- a/flang/lib/Optimizer/Dialect/FIRType.cpp +++ b/flang/lib/Optimizer/Dialect/FIRType.cpp @@ -61,14 +61,13 @@ TYPE parseTypeSingleton(mlir::AsmParser &parser) { /// Is `ty` a standard or FIR integer type? static bool isaIntegerType(mlir::Type ty) { // TODO: why aren't we using isa_integer? investigatation required. - return ty.isa() || ty.isa(); + return mlir::isa(ty); } bool verifyRecordMemberType(mlir::Type ty) { - return !(ty.isa() || ty.isa() || - ty.isa() || ty.isa() || - ty.isa() || ty.isa() || ty.isa() || - ty.isa() || ty.isa()); + return !mlir::isa( + ty); } bool verifySameLists(llvm::ArrayRef a1, @@ -194,7 +193,7 @@ bool isa_std_type(mlir::Type t) { } bool isa_fir_or_std_type(mlir::Type t) { - if (auto funcType = t.dyn_cast()) + if (auto funcType = mlir::dyn_cast(t)) return llvm::all_of(funcType.getInputs(), isa_fir_or_std_type) && llvm::all_of(funcType.getResults(), isa_fir_or_std_type); return isa_fir_type(t) || isa_std_type(t); @@ -203,7 +202,7 @@ bool isa_fir_or_std_type(mlir::Type t) { mlir::Type getDerivedType(mlir::Type ty) { return llvm::TypeSwitch(ty) .Case([](auto p) { - if (auto seq = p.getEleTy().template dyn_cast()) + if (auto seq = mlir::dyn_cast(p.getEleTy())) return seq.getEleTy(); return p.getEleTy(); }) @@ -228,12 +227,12 @@ mlir::Type dyn_cast_ptrOrBoxEleTy(mlir::Type t) { static bool hasDynamicSize(fir::RecordType recTy) { for (auto field : recTy.getTypeList()) { - if (auto arr = field.second.dyn_cast()) { + if (auto arr = mlir::dyn_cast(field.second)) { if (sequenceWithNonConstantShape(arr)) return true; } else if (characterWithDynamicLen(field.second)) { return true; - } else if (auto rec = field.second.dyn_cast()) { + } else if (auto rec = mlir::dyn_cast(field.second)) { if (hasDynamicSize(rec)) return true; } @@ -242,14 +241,14 @@ static bool hasDynamicSize(fir::RecordType recTy) { } bool hasDynamicSize(mlir::Type t) { - if (auto arr = t.dyn_cast()) { + if (auto arr = mlir::dyn_cast(t)) { if (sequenceWithNonConstantShape(arr)) return true; t = arr.getEleTy(); } if (characterWithDynamicLen(t)) return true; - if (auto rec = t.dyn_cast()) + if (auto rec = mlir::dyn_cast(t)) return hasDynamicSize(rec); return false; } @@ -269,33 +268,33 @@ mlir::Type extractSequenceType(mlir::Type ty) { bool isPointerType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) - return boxTy.getEleTy().isa(); + if (auto boxTy = mlir::dyn_cast(ty)) + return mlir::isa(boxTy.getEleTy()); return false; } bool isAllocatableType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) - return boxTy.getEleTy().isa(); + if (auto boxTy = mlir::dyn_cast(ty)) + return mlir::isa(boxTy.getEleTy()); return false; } bool isBoxNone(mlir::Type ty) { - if (auto box = ty.dyn_cast()) - return box.getEleTy().isa(); + if (auto box = mlir::dyn_cast(ty)) + return mlir::isa(box.getEleTy()); return false; } bool isBoxedRecordType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) { - if (boxTy.getEleTy().isa()) + if (auto boxTy = mlir::dyn_cast(ty)) { + if (mlir::isa(boxTy.getEleTy())) return true; mlir::Type innerType = boxTy.unwrapInnerType(); - return innerType && innerType.isa(); + return innerType && mlir::isa(innerType); } return false; } @@ -303,13 +302,13 @@ bool isBoxedRecordType(mlir::Type ty) { bool isScalarBoxedRecordType(mlir::Type ty) { if (auto refTy = fir::dyn_cast_ptrEleTy(ty)) ty = refTy; - if (auto boxTy = ty.dyn_cast()) { - if (boxTy.getEleTy().isa()) + if (auto boxTy = mlir::dyn_cast(ty)) { + if (mlir::isa(boxTy.getEleTy())) return true; - if (auto heapTy = boxTy.getEleTy().dyn_cast()) - return heapTy.getEleTy().isa(); - if (auto ptrTy = boxTy.getEleTy().dyn_cast()) - return ptrTy.getEleTy().isa(); + if (auto heapTy = mlir::dyn_cast(boxTy.getEleTy())) + return mlir::isa(heapTy.getEleTy()); + if (auto ptrTy = mlir::dyn_cast(boxTy.getEleTy())) + return mlir::isa(ptrTy.getEleTy()); } return false; } @@ -363,10 +362,10 @@ bool isPolymorphicType(mlir::Type ty) { bool isUnlimitedPolymorphicType(mlir::Type ty) { // CLASS(*) if (auto clTy = mlir::dyn_cast(fir::unwrapRefType(ty))) { - if (clTy.getEleTy().isa()) + if (mlir::isa(clTy.getEleTy())) return true; mlir::Type innerType = clTy.unwrapInnerType(); - return innerType && innerType.isa(); + return innerType && mlir::isa(innerType); } // TYPE(*) return isAssumedType(ty); @@ -376,7 +375,7 @@ mlir::Type unwrapInnerType(mlir::Type ty) { return llvm::TypeSwitch(ty) .Case([](auto t) { mlir::Type eleTy = t.getEleTy(); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); return eleTy; }) @@ -385,13 +384,14 @@ mlir::Type unwrapInnerType(mlir::Type ty) { } bool isRecordWithAllocatableMember(mlir::Type ty) { - if (auto recTy = ty.dyn_cast()) + if (auto recTy = mlir::dyn_cast(ty)) for (auto [field, memTy] : recTy.getTypeList()) { if (fir::isAllocatableType(memTy)) return true; // A record type cannot recursively include itself as a direct member. // There must be an intervening `ptr` type, so recursion is safe here. - if (memTy.isa() && isRecordWithAllocatableMember(memTy)) + if (mlir::isa(memTy) && + isRecordWithAllocatableMember(memTy)) return true; } return false; @@ -399,11 +399,12 @@ bool isRecordWithAllocatableMember(mlir::Type ty) { bool isRecordWithDescriptorMember(mlir::Type ty) { ty = unwrapSequenceType(ty); - if (auto recTy = ty.dyn_cast()) + if (auto recTy = mlir::dyn_cast(ty)) for (auto [field, memTy] : recTy.getTypeList()) { if (mlir::isa(memTy)) return true; - if (memTy.isa() && isRecordWithDescriptorMember(memTy)) + if (mlir::isa(memTy) && + isRecordWithDescriptorMember(memTy)) return true; } return false; @@ -412,7 +413,7 @@ bool isRecordWithDescriptorMember(mlir::Type ty) { mlir::Type unwrapAllRefAndSeqType(mlir::Type ty) { while (true) { mlir::Type nt = unwrapSequenceType(unwrapRefType(ty)); - if (auto vecTy = nt.dyn_cast()) + if (auto vecTy = mlir::dyn_cast(nt)) nt = vecTy.getEleTy(); if (nt == ty) return ty; @@ -421,11 +422,11 @@ mlir::Type unwrapAllRefAndSeqType(mlir::Type ty) { } mlir::Type unwrapSeqOrBoxedSeqType(mlir::Type ty) { - if (auto seqTy = ty.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(ty)) return seqTy.getEleTy(); - if (auto boxTy = ty.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(ty)) { auto eleTy = unwrapRefType(boxTy.getEleTy()); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getEleTy(); } return ty; @@ -433,7 +434,7 @@ mlir::Type unwrapSeqOrBoxedSeqType(mlir::Type ty) { unsigned getBoxRank(mlir::Type boxTy) { auto eleTy = fir::dyn_cast_ptrOrBoxEleTy(boxTy); - if (auto seqTy = eleTy.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(eleTy)) return seqTy.getDimension(); return 0; } @@ -441,7 +442,7 @@ unsigned getBoxRank(mlir::Type boxTy) { /// Return the ISO_C_BINDING intrinsic module value of type \p ty. int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { unsigned width = 0; - if (mlir::IntegerType intTy = ty.dyn_cast()) { + if (mlir::IntegerType intTy = mlir::dyn_cast(ty)) { switch (intTy.getWidth()) { case 8: return CFI_type_int8_t; @@ -456,7 +457,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported integer type"); } - if (fir::LogicalType logicalTy = ty.dyn_cast()) { + if (fir::LogicalType logicalTy = mlir::dyn_cast(ty)) { switch (kindMap.getLogicalBitsize(logicalTy.getFKind())) { case 8: return CFI_type_Bool; @@ -469,7 +470,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported logical type"); } - if (mlir::FloatType floatTy = ty.dyn_cast()) { + if (mlir::FloatType floatTy = mlir::dyn_cast(ty)) { switch (floatTy.getWidth()) { case 16: return floatTy.isBF16() ? CFI_type_bfloat : CFI_type_half_float; @@ -485,13 +486,14 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { llvm_unreachable("unsupported real type"); } if (fir::isa_complex(ty)) { - if (mlir::ComplexType complexTy = ty.dyn_cast()) { + if (mlir::ComplexType complexTy = mlir::dyn_cast(ty)) { mlir::FloatType floatTy = - complexTy.getElementType().cast(); + mlir::cast(complexTy.getElementType()); if (floatTy.isBF16()) return CFI_type_bfloat_Complex; width = floatTy.getWidth(); - } else if (fir::ComplexType complexTy = ty.dyn_cast()) { + } else if (fir::ComplexType complexTy = + mlir::dyn_cast(ty)) { auto FKind = complexTy.getFKind(); if (FKind == 3) return CFI_type_bfloat_Complex; @@ -511,7 +513,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } llvm_unreachable("unsupported complex size"); } - if (fir::CharacterType charTy = ty.dyn_cast()) { + if (fir::CharacterType charTy = mlir::dyn_cast(ty)) { switch (kindMap.getCharacterBitsize(charTy.getFKind())) { case 8: return CFI_type_char; @@ -524,7 +526,7 @@ int getTypeCode(mlir::Type ty, const fir::KindMapping &kindMap) { } if (fir::isa_ref_type(ty)) return CFI_type_cptr; - if (ty.isa()) + if (mlir::isa(ty)) return CFI_type_struct; llvm_unreachable("unsupported type"); } @@ -542,12 +544,12 @@ std::string getTypeAsString(mlir::Type ty, const fir::KindMapping &kindMap, name << "idx"; } else if (ty.isIntOrIndex()) { name << 'i' << ty.getIntOrFloatBitWidth(); - } else if (ty.isa()) { + } else if (mlir::isa(ty)) { name << 'f' << ty.getIntOrFloatBitWidth(); } else if (fir::isa_complex(ty)) { name << 'z'; if (auto cplxTy = mlir::dyn_cast_or_null(ty)) { - auto floatTy = cplxTy.getElementType().cast(); + auto floatTy = mlir::cast(cplxTy.getElementType()); name << floatTy.getWidth(); } else if (auto cplxTy = mlir::dyn_cast_or_null(ty)) { name << kindMap.getRealBitsize(cplxTy.getFKind()); @@ -644,7 +646,7 @@ static llvm::SmallPtrSet } // namespace void fir::verifyIntegralType(mlir::Type type) { - if (isaIntegerType(type) || type.isa()) + if (isaIntegerType(type) || mlir::isa(type)) return; llvm::report_fatal_error("expected integral type"); } @@ -656,9 +658,9 @@ void fir::printFirType(FIROpsDialect *, mlir::Type ty, } bool fir::isa_unknown_size_box(mlir::Type t) { - if (auto boxTy = t.dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(t)) { auto valueType = fir::unwrapPassByRefType(boxTy); - if (auto seqTy = valueType.dyn_cast()) + if (auto seqTy = mlir::dyn_cast(valueType)) if (seqTy.hasUnknownShape()) return true; } @@ -684,10 +686,10 @@ void fir::BoxProcType::print(mlir::AsmPrinter &printer) const { mlir::LogicalResult BoxProcType::verify(llvm::function_ref emitError, mlir::Type eleTy) { - if (eleTy.isa()) + if (mlir::isa(eleTy)) return mlir::success(); - if (auto refTy = eleTy.dyn_cast()) - if (refTy.isa()) + if (auto refTy = mlir::dyn_cast(eleTy)) + if (mlir::isa(refTy)) return mlir::success(); return emitError() << "invalid type for boxproc" << eleTy << '\n'; } @@ -705,7 +707,7 @@ static bool cannotBePointerOrHeapElementType(mlir::Type eleTy) { mlir::LogicalResult fir::BoxType::verify(llvm::function_ref emitError, mlir::Type eleTy) { - if (eleTy.isa()) + if (mlir::isa(eleTy)) return emitError() << "invalid element type\n"; // TODO return mlir::success(); @@ -1236,10 +1238,10 @@ bool fir::VectorType::isValidElementType(mlir::Type t) { } bool fir::isCharacterProcedureTuple(mlir::Type ty, bool acceptRawFunc) { - mlir::TupleType tuple = ty.dyn_cast(); + mlir::TupleType tuple = mlir::dyn_cast(ty); return tuple && tuple.size() == 2 && - (tuple.getType(0).isa() || - (acceptRawFunc && tuple.getType(0).isa())) && + (mlir::isa(tuple.getType(0)) || + (acceptRawFunc && mlir::isa(tuple.getType(0)))) && fir::isa_integer(tuple.getType(1)); } @@ -1247,7 +1249,8 @@ bool fir::hasAbstractResult(mlir::FunctionType ty) { if (ty.getNumResults() == 0) return false; auto resultType = ty.getResult(0); - return resultType.isa(); + return mlir::isa( + resultType); } /// Convert llvm::Type::TypeID to mlir::Type. \p kind is provided for error diff --git a/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp b/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp index 94f1689dfb05..70b1a2f3d844 100644 --- a/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp +++ b/flang/lib/Optimizer/Dialect/FortranVariableInterface.cpp @@ -18,7 +18,7 @@ mlir::LogicalResult fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { const unsigned numExplicitTypeParams = getExplicitTypeParams().size(); mlir::Type memType = memref.getType(); - const bool sourceIsBoxValue = memType.isa(); + const bool sourceIsBoxValue = mlir::isa(memType); const bool sourceIsBoxAddress = fir::isBoxAddress(memType); const bool sourceIsBox = sourceIsBoxValue || sourceIsBoxAddress; if (isCharacter()) { @@ -29,7 +29,8 @@ fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { return emitOpError("must be provided exactly one type parameter when its " "base is a character that is not a box"); - } else if (auto recordType = getElementType().dyn_cast()) { + } else if (auto recordType = + mlir::dyn_cast(getElementType())) { if (numExplicitTypeParams < recordType.getNumLenParams() && !sourceIsBox) return emitOpError("must be provided all the derived type length " "parameters when the base is not a box"); @@ -45,16 +46,16 @@ fir::FortranVariableOpInterface::verifyDeclareLikeOpImpl(mlir::Value memref) { if (sourceIsBoxAddress) return emitOpError("for box address must not have a shape operand"); unsigned shapeRank = 0; - if (auto shapeType = shape.getType().dyn_cast()) { + if (auto shapeType = mlir::dyn_cast(shape.getType())) { shapeRank = shapeType.getRank(); } else if (auto shapeShiftType = - shape.getType().dyn_cast()) { + mlir::dyn_cast(shape.getType())) { shapeRank = shapeShiftType.getRank(); } else { if (!sourceIsBoxValue) emitOpError("of array entity with a raw address base must have a " "shape operand that is a shape or shapeshift"); - shapeRank = shape.getType().cast().getRank(); + shapeRank = mlir::cast(shape.getType()).getRank(); } std::optional rank = getRank(); diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp index 08b2b0538c73..0b61c0edce62 100644 --- a/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIRDialect.cpp @@ -84,7 +84,8 @@ bool hlfir::isFortranVariableType(mlir::Type type) { return llvm::TypeSwitch(type) .Case([](auto p) { mlir::Type eleType = p.getEleTy(); - return eleType.isa() || !fir::hasDynamicSize(eleType); + return mlir::isa(eleType) || + !fir::hasDynamicSize(eleType); }) .Case([](auto) { return true; }) .Case([](auto) { return true; }) @@ -93,15 +94,15 @@ bool hlfir::isFortranVariableType(mlir::Type type) { bool hlfir::isFortranScalarCharacterType(mlir::Type type) { return isFortranScalarCharacterExprType(type) || - type.isa() || - fir::unwrapPassByRefType(fir::unwrapRefType(type)) - .isa(); + mlir::isa(type) || + mlir::isa( + fir::unwrapPassByRefType(fir::unwrapRefType(type))); } bool hlfir::isFortranScalarCharacterExprType(mlir::Type type) { - if (auto exprType = type.dyn_cast()) + if (auto exprType = mlir::dyn_cast(type)) return exprType.isScalar() && - exprType.getElementType().isa(); + mlir::isa(exprType.getElementType()); return false; } @@ -121,8 +122,8 @@ bool hlfir::isFortranScalarNumericalType(mlir::Type type) { bool hlfir::isFortranNumericalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = - getFortranElementOrSequenceType(type).dyn_cast()) + if (auto arrayTy = mlir::dyn_cast( + getFortranElementOrSequenceType(type))) return isFortranScalarNumericalType(arrayTy.getEleTy()); return false; } @@ -130,8 +131,8 @@ bool hlfir::isFortranNumericalArrayObject(mlir::Type type) { bool hlfir::isFortranNumericalOrLogicalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = - getFortranElementOrSequenceType(type).dyn_cast()) { + if (auto arrayTy = mlir::dyn_cast( + getFortranElementOrSequenceType(type))) { mlir::Type eleTy = arrayTy.getEleTy(); return isFortranScalarNumericalType(eleTy) || mlir::isa(eleTy); @@ -142,7 +143,8 @@ bool hlfir::isFortranNumericalOrLogicalArrayObject(mlir::Type type) { bool hlfir::isFortranArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - return !!getFortranElementOrSequenceType(type).dyn_cast(); + return !!mlir::dyn_cast( + getFortranElementOrSequenceType(type)); } bool hlfir::isPassByRefOrIntegerType(mlir::Type type) { @@ -151,7 +153,7 @@ bool hlfir::isPassByRefOrIntegerType(mlir::Type type) { } bool hlfir::isI1Type(mlir::Type type) { - if (mlir::IntegerType integer = type.dyn_cast()) + if (mlir::IntegerType integer = mlir::dyn_cast(type)) if (integer.getWidth() == 1) return true; return false; @@ -160,8 +162,8 @@ bool hlfir::isI1Type(mlir::Type type) { bool hlfir::isFortranLogicalArrayObject(mlir::Type type) { if (isBoxAddressType(type)) return false; - if (auto arrayTy = - getFortranElementOrSequenceType(type).dyn_cast()) { + if (auto arrayTy = mlir::dyn_cast( + getFortranElementOrSequenceType(type))) { mlir::Type eleTy = arrayTy.getEleTy(); return mlir::isa(eleTy); } diff --git a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp index 8bad4e445082..0d62ca4954e6 100644 --- a/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp +++ b/flang/lib/Optimizer/HLFIR/IR/HLFIROps.cpp @@ -74,8 +74,8 @@ getIntrinsicEffects(mlir::Operation *self, /// Is this a fir.[ref/ptr/heap]>> type? static bool isAllocatableBoxRef(mlir::Type type) { fir::BaseBoxType boxType = - fir::dyn_cast_ptrEleTy(type).dyn_cast_or_null(); - return boxType && boxType.getEleTy().isa(); + mlir::dyn_cast_or_null(fir::dyn_cast_ptrEleTy(type)); + return boxType && mlir::isa(boxType.getEleTy()); } mlir::LogicalResult hlfir::AssignOp::verify() { @@ -84,7 +84,7 @@ mlir::LogicalResult hlfir::AssignOp::verify() { return emitOpError("lhs must be an allocatable when `realloc` is set"); if (mustKeepLhsLengthInAllocatableAssignment() && !(isAllocatableAssignment() && - hlfir::getFortranElementType(lhsType).isa())) + mlir::isa(hlfir::getFortranElementType(lhsType)))) return emitOpError("`realloc` must be set and lhs must be a character " "allocatable when `keep_lhs_length_if_realloc` is set"); return mlir::success(); @@ -99,13 +99,13 @@ mlir::LogicalResult hlfir::AssignOp::verify() { mlir::Type hlfir::DeclareOp::getHLFIRVariableType(mlir::Type inputType, bool hasExplicitLowerBounds) { mlir::Type type = fir::unwrapRefType(inputType); - if (type.isa()) + if (mlir::isa(type)) return inputType; - if (auto charType = type.dyn_cast()) + if (auto charType = mlir::dyn_cast(type)) if (charType.hasDynamicLen()) return fir::BoxCharType::get(charType.getContext(), charType.getFKind()); - auto seqType = type.dyn_cast(); + auto seqType = mlir::dyn_cast(type); bool hasDynamicExtents = seqType && fir::sequenceWithNonConstantShape(seqType); mlir::Type eleType = seqType ? seqType.getEleTy() : type; @@ -117,7 +117,8 @@ mlir::Type hlfir::DeclareOp::getHLFIRVariableType(mlir::Type inputType, } static bool hasExplicitLowerBounds(mlir::Value shape) { - return shape && shape.getType().isa(); + return shape && + mlir::isa(shape.getType()); } void hlfir::DeclareOp::build(mlir::OpBuilder &builder, @@ -288,7 +289,7 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { bool hasBoxComponent; if (getComponent()) { auto component = getComponent().value(); - auto recType = baseElementType.dyn_cast(); + auto recType = mlir::dyn_cast(baseElementType); if (!recType) return emitOpError( "component must be provided only when the memref is a derived type"); @@ -300,14 +301,14 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { } mlir::Type fieldType = recType.getType(fieldIdx); mlir::Type componentBaseType = getFortranElementOrSequenceType(fieldType); - hasBoxComponent = fieldType.isa(); - if (componentBaseType.isa() && - baseType.isa() && + hasBoxComponent = mlir::isa(fieldType); + if (mlir::isa(componentBaseType) && + mlir::isa(baseType) && (numSubscripts == 0 || subscriptsRank > 0)) return emitOpError("indices must be provided and must not contain " "triplets when both memref and component are arrays"); if (numSubscripts != 0) { - if (!componentBaseType.isa()) + if (!mlir::isa(componentBaseType)) return emitOpError("indices must not be provided if component appears " "and is not an array component"); if (!getComponentShape()) @@ -315,9 +316,9 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { "component_shape must be provided when indexing a component"); mlir::Type compShapeType = getComponentShape().getType(); unsigned componentRank = - componentBaseType.cast().getDimension(); - auto shapeType = compShapeType.dyn_cast(); - auto shapeShiftType = compShapeType.dyn_cast(); + mlir::cast(componentBaseType).getDimension(); + auto shapeType = mlir::dyn_cast(compShapeType); + auto shapeShiftType = mlir::dyn_cast(compShapeType); if (!((shapeType && shapeType.getRank() == componentRank) || (shapeShiftType && shapeShiftType.getRank() == componentRank))) return emitOpError("component_shape must be a fir.shape or " @@ -325,33 +326,33 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { if (numSubscripts > componentRank) return emitOpError("indices number must match array component rank"); } - if (auto baseSeqType = baseType.dyn_cast()) + if (auto baseSeqType = mlir::dyn_cast(baseType)) // This case must come first to cover "array%array_comp(i, j)" that has // subscripts for the component but whose rank come from the base. outputRank = baseSeqType.getDimension(); else if (numSubscripts != 0) outputRank = subscriptsRank; else if (auto componentSeqType = - componentBaseType.dyn_cast()) + mlir::dyn_cast(componentBaseType)) outputRank = componentSeqType.getDimension(); outputElementType = fir::unwrapSequenceType(componentBaseType); } else { outputElementType = baseElementType; unsigned baseTypeRank = - baseType.isa() - ? baseType.cast().getDimension() + mlir::isa(baseType) + ? mlir::cast(baseType).getDimension() : 0; if (numSubscripts != 0) { if (baseTypeRank != numSubscripts) return emitOpError("indices number must match memref rank"); outputRank = subscriptsRank; - } else if (auto baseSeqType = baseType.dyn_cast()) { + } else if (auto baseSeqType = mlir::dyn_cast(baseType)) { outputRank = baseSeqType.getDimension(); } } if (!getSubstring().empty()) { - if (!outputElementType.isa()) + if (!mlir::isa(outputElementType)) return emitOpError("memref or component must have character type if " "substring indices are provided"); if (getSubstring().size() != 2) @@ -361,16 +362,16 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { if (!fir::isa_complex(outputElementType)) return emitOpError("memref or component must have complex type if " "complex_part is provided"); - if (auto firCplx = outputElementType.dyn_cast()) + if (auto firCplx = mlir::dyn_cast(outputElementType)) outputElementType = firCplx.getElementType(); else outputElementType = - outputElementType.cast().getElementType(); + mlir::cast(outputElementType).getElementType(); } mlir::Type resultBaseType = getFortranElementOrSequenceType(getResult().getType()); unsigned resultRank = 0; - if (auto resultSeqType = resultBaseType.dyn_cast()) + if (auto resultSeqType = mlir::dyn_cast(resultBaseType)) resultRank = resultSeqType.getDimension(); if (resultRank != outputRank) return emitOpError("result type rank is not consistent with operands, " @@ -380,10 +381,10 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { // result type must match the one that was inferred here, except the character // length may differ because of substrings. if (resultElementType != outputElementType && - !(resultElementType.isa() && - outputElementType.isa()) && - !(resultElementType.isa() && - outputElementType.isa())) + !(mlir::isa(resultElementType) && + mlir::isa(outputElementType)) && + !(mlir::isa(resultElementType) && + mlir::isa(outputElementType))) return emitOpError( "result element type is not consistent with operands, expected ") << outputElementType; @@ -401,22 +402,22 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { return emitOpError("shape must be provided if and only if the result is " "an array that is not a box address"); if (resultRank != 0) { - auto shapeType = getShape().getType().dyn_cast(); + auto shapeType = mlir::dyn_cast(getShape().getType()); auto shapeShiftType = - getShape().getType().dyn_cast(); + mlir::dyn_cast(getShape().getType()); if (!((shapeType && shapeType.getRank() == resultRank) || (shapeShiftType && shapeShiftType.getRank() == resultRank))) return emitOpError("shape must be a fir.shape or fir.shapeshift with " "the rank of the result"); } auto numLenParam = getTypeparams().size(); - if (outputElementType.isa()) { + if (mlir::isa(outputElementType)) { if (numLenParam != 1) return emitOpError("must be provided one length parameter when the " "result is a character"); } else if (fir::isRecordWithTypeParameters(outputElementType)) { if (numLenParam != - outputElementType.cast().getNumLenParams()) + mlir::cast(outputElementType).getNumLenParams()) return emitOpError("must be provided the same number of length " "parameters as in the result derived type"); } else if (numLenParam != 0) { @@ -434,18 +435,18 @@ mlir::LogicalResult hlfir::DesignateOp::verify() { mlir::LogicalResult hlfir::ParentComponentOp::verify() { mlir::Type baseType = hlfir::getFortranElementOrSequenceType(getMemref().getType()); - auto maybeInputSeqType = baseType.dyn_cast(); + auto maybeInputSeqType = mlir::dyn_cast(baseType); unsigned inputTypeRank = maybeInputSeqType ? maybeInputSeqType.getDimension() : 0; unsigned shapeRank = 0; if (mlir::Value shape = getShape()) - if (auto shapeType = shape.getType().dyn_cast()) + if (auto shapeType = mlir::dyn_cast(shape.getType())) shapeRank = shapeType.getRank(); if (inputTypeRank != shapeRank) return emitOpError( "must be provided a shape if and only if the base is an array"); mlir::Type outputBaseType = hlfir::getFortranElementOrSequenceType(getType()); - auto maybeOutputSeqType = outputBaseType.dyn_cast(); + auto maybeOutputSeqType = mlir::dyn_cast(outputBaseType); unsigned outputTypeRank = maybeOutputSeqType ? maybeOutputSeqType.getDimension() : 0; if (inputTypeRank != outputTypeRank) @@ -459,23 +460,23 @@ mlir::LogicalResult hlfir::ParentComponentOp::verify() { return emitOpError( "result type extents are inconsistent with memref type"); fir::RecordType baseRecType = - hlfir::getFortranElementType(baseType).dyn_cast(); - fir::RecordType outRecType = - hlfir::getFortranElementType(outputBaseType).dyn_cast(); + mlir::dyn_cast(hlfir::getFortranElementType(baseType)); + fir::RecordType outRecType = mlir::dyn_cast( + hlfir::getFortranElementType(outputBaseType)); if (!baseRecType || !outRecType) return emitOpError("result type and input type must be derived types"); // Note: result should not be a fir.class: its dynamic type is being set to // the parent type and allowing fir.class would break the operation codegen: // it would keep the input dynamic type. - if (getType().isa()) + if (mlir::isa(getType())) return emitOpError("result type must not be polymorphic"); // The array results are known to not be dis-contiguous in most cases (the // exception being if the parent type was extended by a type without any // components): require a fir.box to be used for the result to carry the // strides. - if (!getType().isa() && + if (!mlir::isa(getType()) && (outputTypeRank != 0 || fir::isRecordWithTypeParameters(outRecType))) return emitOpError("result type must be a fir.box if the result is an " "array or has length parameters"); @@ -496,9 +497,8 @@ verifyLogicalReductionOp(LogicalReductionOp reductionOp) { mlir::Value mask = reductionOp->getMask(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType maskTy = - hlfir::getFortranElementOrSequenceType(mask.getType()) - .cast(); + fir::SequenceType maskTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(mask.getType())); mlir::Type logicalTy = maskTy.getEleTy(); llvm::ArrayRef maskShape = maskTy.getShape(); @@ -576,9 +576,8 @@ mlir::LogicalResult hlfir::CountOp::verify() { mlir::Value mask = getMask(); mlir::Value dim = getDim(); - fir::SequenceType maskTy = - hlfir::getFortranElementOrSequenceType(mask.getType()) - .cast(); + fir::SequenceType maskTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(mask.getType())); llvm::ArrayRef maskShape = maskTy.getShape(); mlir::Type resultType = results[0]; @@ -613,13 +612,14 @@ void hlfir::CountOp::getEffects( //===----------------------------------------------------------------------===// static unsigned getCharacterKind(mlir::Type t) { - return hlfir::getFortranElementType(t).cast().getFKind(); + return mlir::cast(hlfir::getFortranElementType(t)) + .getFKind(); } static std::optional getCharacterLengthIfStatic(mlir::Type t) { if (auto charType = - hlfir::getFortranElementType(t).dyn_cast()) + mlir::dyn_cast(hlfir::getFortranElementType(t))) if (charType.hasConstantLen()) return charType.getLen(); return std::nullopt; @@ -672,15 +672,13 @@ verifyArrayAndMaskForReductionOp(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value mask = reductionOp->getMask(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); llvm::ArrayRef arrayShape = arrayTy.getShape(); if (mask) { - fir::SequenceType maskSeq = - hlfir::getFortranElementOrSequenceType(mask.getType()) - .dyn_cast(); + fir::SequenceType maskSeq = mlir::dyn_cast( + hlfir::getFortranElementOrSequenceType(mask.getType())); llvm::ArrayRef maskShape; if (maskSeq) @@ -720,9 +718,8 @@ verifyNumericalReductionOp(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); mlir::Type numTy = arrayTy.getEleTy(); llvm::ArrayRef arrayShape = arrayTy.getShape(); @@ -790,13 +787,12 @@ verifyCharacterReductionOp(CharacterReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); mlir::Type numTy = arrayTy.getEleTy(); llvm::ArrayRef arrayShape = arrayTy.getShape(); - auto resultExpr = results[0].cast(); + auto resultExpr = mlir::cast(results[0]); mlir::Type resultType = resultExpr.getEleTy(); assert(mlir::isa(resultType) && "result must be character"); @@ -881,9 +877,8 @@ verifyResultForMinMaxLoc(NumericalReductionOp reductionOp) { mlir::Value array = reductionOp->getArray(); mlir::Value dim = reductionOp->getDim(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); llvm::ArrayRef arrayShape = arrayTy.getShape(); mlir::Type resultType = results[0]; @@ -993,12 +988,10 @@ void hlfir::SumOp::getEffects( mlir::LogicalResult hlfir::DotProductOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = - hlfir::getFortranElementOrSequenceType(lhs.getType()) - .cast(); - fir::SequenceType rhsTy = - hlfir::getFortranElementOrSequenceType(rhs.getType()) - .cast(); + fir::SequenceType lhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(lhs.getType())); + fir::SequenceType rhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(rhs.getType())); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); @@ -1051,19 +1044,17 @@ void hlfir::DotProductOp::getEffects( mlir::LogicalResult hlfir::MatmulOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = - hlfir::getFortranElementOrSequenceType(lhs.getType()) - .cast(); - fir::SequenceType rhsTy = - hlfir::getFortranElementOrSequenceType(rhs.getType()) - .cast(); + fir::SequenceType lhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(lhs.getType())); + fir::SequenceType rhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(rhs.getType())); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); std::size_t rhsRank = rhsShape.size(); mlir::Type lhsEleTy = lhsTy.getEleTy(); mlir::Type rhsEleTy = rhsTy.getEleTy(); - hlfir::ExprType resultTy = getResult().getType().cast(); + hlfir::ExprType resultTy = mlir::cast(getResult().getType()); llvm::ArrayRef resultShape = resultTy.getShape(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1180,13 +1171,12 @@ void hlfir::MatmulOp::getEffects( mlir::LogicalResult hlfir::TransposeOp::verify() { mlir::Value array = getArray(); - fir::SequenceType arrayTy = - hlfir::getFortranElementOrSequenceType(array.getType()) - .cast(); + fir::SequenceType arrayTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(array.getType())); llvm::ArrayRef inShape = arrayTy.getShape(); std::size_t rank = inShape.size(); mlir::Type eleTy = arrayTy.getEleTy(); - hlfir::ExprType resultTy = getResult().getType().cast(); + hlfir::ExprType resultTy = mlir::cast(getResult().getType()); llvm::ArrayRef resultShape = resultTy.getShape(); std::size_t resultRank = resultShape.size(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1224,19 +1214,17 @@ void hlfir::TransposeOp::getEffects( mlir::LogicalResult hlfir::MatmulTransposeOp::verify() { mlir::Value lhs = getLhs(); mlir::Value rhs = getRhs(); - fir::SequenceType lhsTy = - hlfir::getFortranElementOrSequenceType(lhs.getType()) - .cast(); - fir::SequenceType rhsTy = - hlfir::getFortranElementOrSequenceType(rhs.getType()) - .cast(); + fir::SequenceType lhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(lhs.getType())); + fir::SequenceType rhsTy = mlir::cast( + hlfir::getFortranElementOrSequenceType(rhs.getType())); llvm::ArrayRef lhsShape = lhsTy.getShape(); llvm::ArrayRef rhsShape = rhsTy.getShape(); std::size_t lhsRank = lhsShape.size(); std::size_t rhsRank = rhsShape.size(); mlir::Type lhsEleTy = lhsTy.getEleTy(); mlir::Type rhsEleTy = rhsTy.getEleTy(); - hlfir::ExprType resultTy = getResult().getType().cast(); + hlfir::ExprType resultTy = mlir::cast(getResult().getType()); llvm::ArrayRef resultShape = resultTy.getShape(); mlir::Type resultEleTy = resultTy.getEleTy(); @@ -1381,7 +1369,7 @@ void hlfir::AsExprOp::build(mlir::OpBuilder &builder, hlfir::ExprType::Shape typeShape; bool isPolymorphic = fir::isPolymorphicType(var.getType()); mlir::Type type = getFortranElementOrSequenceType(var.getType()); - if (auto seqType = type.dyn_cast()) { + if (auto seqType = mlir::dyn_cast(type)) { typeShape.append(seqType.getShape().begin(), seqType.getShape().end()); type = seqType.getEleTy(); } @@ -1427,7 +1415,7 @@ static void buildElemental(mlir::OpBuilder &builder, isUnordered ? builder.getUnitAttr() : nullptr); mlir::Region *bodyRegion = odsState.addRegion(); bodyRegion->push_back(new mlir::Block{}); - if (auto shapeType = shape.getType().dyn_cast()) { + if (auto shapeType = mlir::dyn_cast(shape.getType())) { unsigned dim = shapeType.getRank(); mlir::Type indexType = builder.getIndexType(); for (unsigned d = 0; d < dim; ++d) @@ -1468,7 +1456,7 @@ void hlfir::ApplyOp::build(mlir::OpBuilder &builder, mlir::ValueRange indices, mlir::ValueRange typeparams) { mlir::Type resultType = expr.getType(); - if (auto exprType = resultType.dyn_cast()) + if (auto exprType = mlir::dyn_cast(resultType)) resultType = exprType.getElementExprType(); build(builder, odsState, resultType, expr, indices, typeparams); } @@ -1517,20 +1505,20 @@ void hlfir::CopyInOp::build(mlir::OpBuilder &builder, void hlfir::ShapeOfOp::build(mlir::OpBuilder &builder, mlir::OperationState &result, mlir::Value expr) { - hlfir::ExprType exprTy = expr.getType().cast(); + hlfir::ExprType exprTy = mlir::cast(expr.getType()); mlir::Type type = fir::ShapeType::get(builder.getContext(), exprTy.getRank()); build(builder, result, type, expr); } std::size_t hlfir::ShapeOfOp::getRank() { mlir::Type resTy = getResult().getType(); - fir::ShapeType shape = resTy.cast(); + fir::ShapeType shape = mlir::cast(resTy); return shape.getRank(); } mlir::LogicalResult hlfir::ShapeOfOp::verify() { mlir::Value expr = getExpr(); - hlfir::ExprType exprTy = expr.getType().cast(); + hlfir::ExprType exprTy = mlir::cast(expr.getType()); std::size_t exprRank = exprTy.getShape().size(); if (exprRank == 0) @@ -1549,7 +1537,8 @@ hlfir::ShapeOfOp::canonicalize(ShapeOfOp shapeOf, // if extent information is available at compile time, immediately fold the // hlfir.shape_of into a fir.shape mlir::Location loc = shapeOf.getLoc(); - hlfir::ExprType expr = shapeOf.getExpr().getType().cast(); + hlfir::ExprType expr = + mlir::cast(shapeOf.getExpr().getType()); mlir::Value shape = hlfir::genExprShape(rewriter, loc, expr); if (!shape) @@ -1574,7 +1563,7 @@ void hlfir::GetExtentOp::build(mlir::OpBuilder &builder, } mlir::LogicalResult hlfir::GetExtentOp::verify() { - fir::ShapeType shapeTy = getShape().getType().cast(); + fir::ShapeType shapeTy = mlir::cast(getShape().getType()); std::uint64_t rank = shapeTy.getRank(); llvm::APInt dim = getDim(); if (dim.sge(rank)) @@ -1709,10 +1698,11 @@ mlir::LogicalResult hlfir::ElementalAddrOp::verify() { return emitOpError("body region must be terminated by an hlfir.yield"); mlir::Type elementAddrType = yieldOp.getEntity().getType(); if (!hlfir::isFortranVariableType(elementAddrType) || - hlfir::getFortranElementOrSequenceType(elementAddrType) - .isa()) + mlir::isa( + hlfir::getFortranElementOrSequenceType(elementAddrType))) return emitOpError("body must compute the address of a scalar entity"); - unsigned shapeRank = getShape().getType().cast().getRank(); + unsigned shapeRank = + mlir::cast(getShape().getType()).getRank(); if (shapeRank != getIndices().size()) return emitOpError("body number of indices must match shape rank"); return mlir::success(); @@ -1817,8 +1807,8 @@ static bool yieldsLogical(mlir::Region ®ion, bool mustBeScalarI1) { if (mustBeScalarI1) return hlfir::isI1Type(yieldType); return hlfir::isMaskArgument(yieldType) && - hlfir::getFortranElementOrSequenceType(yieldType) - .isa(); + mlir::isa( + hlfir::getFortranElementOrSequenceType(yieldType)); } mlir::LogicalResult hlfir::ForallMaskOp::verify() { diff --git a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp index 1c4f82e2de81..d4e4835ee726 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/BufferizeHLFIR.cpp @@ -77,7 +77,7 @@ static mlir::Value packageBufferizedExpr(mlir::Location loc, /// currently enforced by the verifiers that only accept HLFIR value or /// variable types which do not include tuples. static hlfir::Entity getBufferizedExprStorage(mlir::Value bufferizedExpr) { - auto tupleType = bufferizedExpr.getType().dyn_cast(); + auto tupleType = mlir::dyn_cast(bufferizedExpr.getType()); if (!tupleType) return hlfir::Entity{bufferizedExpr}; assert(tupleType.size() == 2 && "unexpected tuple type"); @@ -90,7 +90,7 @@ static hlfir::Entity getBufferizedExprStorage(mlir::Value bufferizedExpr) { /// Helper to extract the clean-up flag from a tuple created by /// packageBufferizedExpr. static mlir::Value getBufferizedExprMustFreeFlag(mlir::Value bufferizedExpr) { - auto tupleType = bufferizedExpr.getType().dyn_cast(); + auto tupleType = mlir::dyn_cast(bufferizedExpr.getType()); if (!tupleType) return bufferizedExpr; assert(tupleType.size() == 2 && "unexpected tuple type"); @@ -218,7 +218,7 @@ struct ShapeOfOpConversion } else { // everything else failed so try to create a shape from static type info hlfir::ExprType exprTy = - adaptor.getExpr().getType().dyn_cast_or_null(); + mlir::dyn_cast_or_null(adaptor.getExpr().getType()); if (exprTy) shape = hlfir::genExprShape(builder, loc, exprTy); } @@ -480,10 +480,10 @@ struct AssociateOpConversion assert(mlir::isa(sourceVar.getType()) && fir::isAllocatableType(sourceVar.getType())); assert(sourceVar.getType() == assocType); - } else if ((sourceVar.getType().isa() && - !assocType.isa()) || - ((sourceVar.getType().isa() && - !assocType.isa()))) { + } else if ((mlir::isa(sourceVar.getType()) && + !mlir::isa(assocType)) || + ((mlir::isa(sourceVar.getType()) && + !mlir::isa(assocType)))) { sourceVar = builder.create(loc, assocType, sourceVar); } else { sourceVar = builder.createConvert(loc, assocType, sourceVar); @@ -590,13 +590,13 @@ static void genBufferDestruction(mlir::Location loc, fir::FirOpBuilder &builder, // for MERGE with polymorphic results. if (mustFinalize) TODO(loc, "finalizing polymorphic temporary in HLFIR"); - } else if (var.getType().isa()) { + } else if (mlir::isa(var.getType())) { if (mustFinalize && !mlir::isa(var.getType())) fir::emitFatalError(loc, "non-finalizable variable"); addr = builder.create(loc, heapType, var); } else { - if (!var.getType().isa()) + if (!mlir::isa(var.getType())) addr = builder.create(loc, heapType, var); if (mustFinalize || deallocComponents) { @@ -831,7 +831,7 @@ struct ElementalOpConversion // the assign, insert an hlfir.destroy to mark the expression end-of-life. // If the expression creation allocated a buffer on the heap inside the // loop, this will ensure the buffer properly deallocated. - if (elementValue.getType().isa() && + if (mlir::isa(elementValue.getType()) && wasCreatedInCurrentBlock(elementValue, builder)) builder.create(loc, elementValue); } @@ -926,11 +926,12 @@ public: hlfir::EndAssociateOp, hlfir::SetLengthOp>(); target.markUnknownOpDynamicallyLegal([](mlir::Operation *op) { - return llvm::all_of( - op->getResultTypes(), - [](mlir::Type ty) { return !ty.isa(); }) && + return llvm::all_of(op->getResultTypes(), + [](mlir::Type ty) { + return !mlir::isa(ty); + }) && llvm::all_of(op->getOperandTypes(), [](mlir::Type ty) { - return !ty.isa(); + return !mlir::isa(ty); }); }); if (mlir::failed( diff --git a/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp b/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp index cd534bae4ad2..517285dce133 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/ConvertToFIR.cpp @@ -34,7 +34,7 @@ using namespace mlir; static mlir::Value genAllocatableTempFromSourceBox(mlir::Location loc, fir::FirOpBuilder &builder, mlir::Value sourceBox) { - assert(sourceBox.getType().isa() && + assert(mlir::isa(sourceBox.getType()) && "must be a base box type"); // Use the runtime to make a quick and dirty temp with the rhs value. // Overkill for scalar rhs that could be done in much more clever ways. @@ -44,7 +44,7 @@ static mlir::Value genAllocatableTempFromSourceBox(mlir::Location loc, // This has the huge benefit of dealing with all cases, including // polymorphic entities. mlir::Type fromHeapType = fir::HeapType::get(fir::unwrapRefType( - sourceBox.getType().cast().getEleTy())); + mlir::cast(sourceBox.getType()).getEleTy())); mlir::Type fromBoxHeapType = fir::BoxType::get(fromHeapType); mlir::Value fromMutableBox = fir::factory::genNullBoxStorage(builder, loc, fromBoxHeapType); @@ -69,7 +69,7 @@ public: auto module = assignOp->getParentOfType(); fir::FirOpBuilder builder(rewriter, module); - if (rhs.getType().isa()) { + if (mlir::isa(rhs.getType())) { mlir::emitError(loc, "hlfir must be bufferized with --bufferize-hlfir " "pass before being converted to FIR"); return mlir::failure(); @@ -343,16 +343,15 @@ public: auto firBase = firDeclareOp.getResult(); mlir::Value hlfirBase; mlir::Type hlfirBaseType = declareOp.getBase().getType(); - if (hlfirBaseType.isa()) { + if (mlir::isa(hlfirBaseType)) { fir::FirOpBuilder builder(rewriter, declareOp.getOperation()); // Helper to generate the hlfir fir.box with the local lower bounds and // type parameters. auto genHlfirBox = [&]() -> mlir::Value { - if (!firBase.getType().isa()) { + if (!mlir::isa(firBase.getType())) { llvm::SmallVector typeParams; - auto maybeCharType = - fir::unwrapSequenceType(fir::unwrapPassByRefType(hlfirBaseType)) - .dyn_cast(); + auto maybeCharType = mlir::dyn_cast( + fir::unwrapSequenceType(fir::unwrapPassByRefType(hlfirBaseType))); if (!maybeCharType || maybeCharType.hasDynamicLen()) typeParams.append(declareOp.getTypeparams().begin(), declareOp.getTypeparams().end()); @@ -399,7 +398,7 @@ public: }) .getResults()[0]; } - } else if (hlfirBaseType.isa()) { + } else if (mlir::isa(hlfirBaseType)) { assert(declareOp.getTypeparams().size() == 1 && "must contain character length"); hlfirBase = rewriter.create( @@ -480,11 +479,12 @@ public: // - scalar%scalar_component [substring|complex_part] or // - scalar%static_size_array_comp // - scalar%array(indices) [substring| complex part] - mlir::Type componentType = baseEleTy.cast().getType( - designate.getComponent().value()); + mlir::Type componentType = + mlir::cast(baseEleTy).getType( + designate.getComponent().value()); mlir::Type coorTy = fir::ReferenceType::get(componentType); base = builder.create(loc, coorTy, base, fieldIndex); - if (componentType.isa()) { + if (mlir::isa(componentType)) { auto variableInterface = mlir::cast( designate.getOperation()); if (variableInterface.isAllocatable() || @@ -500,14 +500,14 @@ public: } else { // array%component[(indices) substring|complex part] cases. // Component ref of array bases are dealt with below in embox/rebox. - assert(designateResultType.isa()); + assert(mlir::isa(designateResultType)); } } - if (designateResultType.isa()) { + if (mlir::isa(designateResultType)) { // Generate embox or rebox. mlir::Type eleTy = fir::unwrapPassByRefType(designateResultType); - bool isScalarDesignator = !eleTy.isa(); + bool isScalarDesignator = !mlir::isa(eleTy); mlir::Value sourceBox; if (isScalarDesignator) { // The base box will be used for emboxing the scalar element. @@ -583,7 +583,7 @@ public: assert(sliceFields.empty() && substring.empty()); llvm::SmallVector resultType{designateResultType}; mlir::Value resultBox; - if (base.getType().isa()) + if (mlir::isa(base.getType())) resultBox = builder.create(loc, resultType, base, shape, slice); else @@ -598,7 +598,8 @@ public: // first element of a contiguous array section with compile time constant // shape. The base may be an array, or a scalar. mlir::Type resultAddressType = designateResultType; - if (auto boxCharType = designateResultType.dyn_cast()) + if (auto boxCharType = + mlir::dyn_cast(designateResultType)) resultAddressType = fir::ReferenceType::get(boxCharType.getEleTy()); // Array element indexing. @@ -620,7 +621,7 @@ public: // Scalar complex part ref if (designate.getComplexPart()) { // Sequence types should have already been handled by this point - assert(!designateResultType.isa()); + assert(!mlir::isa(designateResultType)); auto index = builder.createIntegerConstant(loc, builder.getIndexType(), *designate.getComplexPart()); auto coorTy = fir::ReferenceType::get(resultEleTy); @@ -628,7 +629,7 @@ public: } // Cast/embox the computed scalar address if needed. - if (designateResultType.isa()) { + if (mlir::isa(designateResultType)) { assert(designate.getTypeparams().size() == 1 && "must have character length"); auto emboxChar = builder.create( @@ -671,13 +672,13 @@ public: mlir::PatternRewriter &rewriter) const override { mlir::Location loc = parentComponent.getLoc(); mlir::Type resultType = parentComponent.getType(); - if (!parentComponent.getType().isa()) { + if (!mlir::isa(parentComponent.getType())) { mlir::Value baseAddr = parentComponent.getMemref(); // Scalar parent component ref without any length type parameters. The // input may be a fir.class if it is polymorphic, since this is a scalar // and the output will be monomorphic, the base address can be extracted // from the fir.class. - if (baseAddr.getType().isa()) + if (mlir::isa(baseAddr.getType())) baseAddr = rewriter.create(loc, baseAddr); rewriter.replaceOpWithNewOp(parentComponent, resultType, baseAddr); @@ -686,7 +687,7 @@ public: // Array parent component ref or PDTs. hlfir::Entity base{parentComponent.getMemref()}; mlir::Value baseAddr = base.getBase(); - if (!baseAddr.getType().isa()) { + if (!mlir::isa(baseAddr.getType())) { // Embox cannot directly be used to address parent components: it expects // the output type to match the input type when there are no slices. When // the types have at least one component, a slice to the first element can @@ -748,7 +749,7 @@ public: // the hlfir.shape_of operation which led to the creation of this get_extent // operation should now have been lowered to a fir.shape operation if (auto s = mlir::dyn_cast_or_null(shapeOp)) { - fir::ShapeType shapeTy = shape.getType().cast(); + fir::ShapeType shapeTy = mlir::cast(shape.getType()); llvm::APInt dim = getExtentOp.getDim(); uint64_t dimVal = dim.getLimitedValue(shapeTy.getRank()); mlir::Value extent = s.getExtents()[dimVal]; diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp index 0142fb0cfb0b..e9dbb7095d0e 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIRIntrinsics.cpp @@ -185,7 +185,7 @@ protected: // the width for use in runtime intrinsic calls. static unsigned getKindForType(mlir::Type ty) { mlir::Type eltty = hlfir::getFortranElementType(ty); - unsigned width = eltty.cast().getWidth(); + unsigned width = mlir::cast(eltty).getWidth(); return width / 8; } diff --git a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp index 84101353a740..63b52c0cd0bc 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/LowerHLFIROrderedAssignments.cpp @@ -1090,7 +1090,7 @@ void OrderedAssignmentRewriter::generateSaveEntity( mlir::Value loopExtent = computeLoopNestIterationNumber(loc, builder, loopNest); auto sequenceType = - builder.getVarLenSeqTy(entityType).cast(); + mlir::cast(builder.getVarLenSeqTy(entityType)); temp = insertSavedEntity(region, fir::factory::HomogeneousScalarStack{ loc, builder, sequenceType, loopExtent, diff --git a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp index 685c73d67625..8d68c7021608 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/OptimizedBufferization.cpp @@ -249,7 +249,7 @@ static bool areIdenticalOrDisjointSlices(mlir::Value ref1, mlir::Value ref2) { auto isPositiveConstant = [](mlir::Value v) -> bool { if (auto conOp = mlir::dyn_cast(v.getDefiningOp())) - if (auto iattr = conOp.getValue().dyn_cast()) + if (auto iattr = mlir::dyn_cast(conOp.getValue())) return iattr.getInt() > 0; return false; }; @@ -601,7 +601,7 @@ mlir::LogicalResult VariableAssignBufferization::matchAndRewrite( // TODO: ExprType check is here to avoid conflicts with // ElementalAssignBufferization pattern. We need to combine // these matchers into a single one that applies to AssignOp. - if (rhs.getType().isa()) + if (mlir::isa(rhs.getType())) return rewriter.notifyMatchFailure(assign, "RHS is not in memory"); if (!rhs.isArray()) @@ -834,7 +834,7 @@ public: unsigned rank = mlir::cast(mloc.getType()).getShape()[0]; mlir::Type arrayType = array.getType(); - if (!arrayType.isa()) + if (!mlir::isa(arrayType)) return rewriter.notifyMatchFailure( mloc, "Currently requires a boxed type input"); mlir::Type elementType = hlfir::getFortranElementType(arrayType); @@ -850,7 +850,7 @@ public: auto init = [isMax](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); llvm::APFloat limit = llvm::APFloat::getInf(sem, /*Negative=*/isMax); return builder.createRealConstant(loc, elementType, limit); @@ -901,7 +901,7 @@ public: // Compare with the max reduction value mlir::Value cmp; - if (elementType.isa()) { + if (mlir::isa(elementType)) { // For FP reductions we want the first smallest value to be used, that // is not NaN. A OGL/OLT condition will usually work for this unless all // the values are Nan or Inf. This follows the same logic as @@ -918,7 +918,7 @@ public: loc, mlir::arith::CmpFPredicate::OEQ, elem, elem); cmpNan = builder.create(loc, cmpNan, cmpNan2); cmp = builder.create(loc, cmp, cmpNan); - } else if (elementType.isa()) { + } else if (mlir::isa(elementType)) { cmp = builder.create( loc, isMax ? mlir::arith::CmpIPredicate::sgt diff --git a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp index 2751575ce982..b761563eba0f 100644 --- a/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp +++ b/flang/lib/Optimizer/HLFIR/Transforms/SimplifyHLFIRIntrinsics.cpp @@ -103,7 +103,8 @@ public: // by hlfir.elemental) target.addDynamicallyLegalOp( [](hlfir::TransposeOp transpose) { - return transpose.getType().cast().isPolymorphic(); + return mlir::cast(transpose.getType()) + .isPolymorphic(); }); target.markUnknownOpDynamicallyLegal( [](mlir::Operation *) { return true; }); diff --git a/flang/lib/Optimizer/Transforms/AbstractResult.cpp b/flang/lib/Optimizer/Transforms/AbstractResult.cpp index eb4dd637bb16..85472cdc5103 100644 --- a/flang/lib/Optimizer/Transforms/AbstractResult.cpp +++ b/flang/lib/Optimizer/Transforms/AbstractResult.cpp @@ -65,14 +65,14 @@ static mlir::FunctionType getCPtrFunctionType(mlir::FunctionType funcTy) { auto resultType = funcTy.getResult(0); assert(fir::isa_builtin_cptr_type(resultType)); llvm::SmallVector outputTypes; - auto recTy = resultType.dyn_cast(); + auto recTy = mlir::dyn_cast(resultType); outputTypes.emplace_back(recTy.getTypeList()[0].second); return mlir::FunctionType::get(funcTy.getContext(), funcTy.getInputs(), outputTypes); } static bool mustEmboxResult(mlir::Type resultType, bool shouldBoxResult) { - return resultType.isa() && + return mlir::isa(resultType) && shouldBoxResult; } @@ -114,7 +114,7 @@ public: bool isResultBuiltinCPtr = fir::isa_builtin_cptr_type(result.getType()); Op newOp; if (isResultBuiltinCPtr) { - auto recTy = result.getType().template dyn_cast(); + auto recTy = mlir::dyn_cast(result.getType()); newResultTypes.emplace_back(recTy.getTypeList()[0].second); } @@ -261,7 +261,7 @@ public: mlir::LogicalResult matchAndRewrite(fir::AddrOfOp addrOf, mlir::PatternRewriter &rewriter) const override { - auto oldFuncTy = addrOf.getType().cast(); + auto oldFuncTy = mlir::cast(addrOf.getType()); mlir::FunctionType newFuncTy; // TODO: This should be generalized for derived types, and it is // architecture and OS dependent. @@ -296,7 +296,7 @@ public: auto loc = func.getLoc(); auto *context = &getContext(); // Convert function type itself if it has an abstract result. - auto funcTy = func.getFunctionType().cast(); + auto funcTy = mlir::cast(func.getFunctionType()); if (hasAbstractResult(funcTy)) { // TODO: This should be generalized for derived types, and it is // architecture and OS dependent. @@ -343,11 +343,11 @@ public: return mlir::TypeSwitch(type) .Case([](fir::BoxProcType boxProc) { return fir::hasAbstractResult( - boxProc.getEleTy().cast()); + mlir::cast(boxProc.getEleTy())); }) .Case([](fir::PointerType pointer) { return fir::hasAbstractResult( - pointer.getEleTy().cast()); + mlir::cast(pointer.getEleTy())); }) .Default([](auto &&) { return false; }); } @@ -411,7 +411,7 @@ public: return !hasAbstractResult(call.getFunctionType()); }); target.addDynamicallyLegalOp([](fir::AddrOfOp addrOf) { - if (auto funTy = addrOf.getType().dyn_cast()) + if (auto funTy = mlir::dyn_cast(addrOf.getType())) return !hasAbstractResult(funTy); return true; }); diff --git a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp index 68584bef055b..18d98a11ef3c 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp @@ -69,7 +69,7 @@ void AddDebugInfoPass::runOnOperation() { // In that case, 'inputFilename' may be empty. Location embedded in the // module will be used to get file name and its directory. if (inputFilename.empty()) { - if (auto fileLoc = module.getLoc().dyn_cast()) { + if (auto fileLoc = mlir::dyn_cast(module.getLoc())) { fileName = llvm::sys::path::filename(fileLoc.getFilename().getValue()); filePath = llvm::sys::path::parent_path(fileLoc.getFilename().getValue()); } else @@ -94,14 +94,14 @@ void AddDebugInfoPass::runOnOperation() { mlir::Location l = funcOp->getLoc(); // If fused location has already been created then nothing to do // Otherwise, create a fused location. - if (l.dyn_cast()) + if (mlir::dyn_cast(l)) return; unsigned int CC = (funcOp.getName() == fir::NameUniquer::doProgramEntry()) ? llvm::dwarf::getCallingConvention("DW_CC_program") : llvm::dwarf::getCallingConvention("DW_CC_normal"); - if (auto funcLoc = l.dyn_cast()) { + if (auto funcLoc = mlir::dyn_cast(l)) { fileName = llvm::sys::path::filename(funcLoc.getFilename().getValue()); filePath = llvm::sys::path::parent_path(funcLoc.getFilename().getValue()); } diff --git a/flang/lib/Optimizer/Transforms/AffineDemotion.cpp b/flang/lib/Optimizer/Transforms/AffineDemotion.cpp index da29ae880700..b4523a060f5a 100644 --- a/flang/lib/Optimizer/Transforms/AffineDemotion.cpp +++ b/flang/lib/Optimizer/Transforms/AffineDemotion.cpp @@ -98,14 +98,15 @@ public: mlir::LogicalResult matchAndRewrite(fir::ConvertOp op, mlir::PatternRewriter &rewriter) const override { - if (op.getRes().getType().isa()) { + if (mlir::isa(op.getRes().getType())) { // due to index calculation moving to affine maps we still need to // add converts for sequence types this has a side effect of losing // some information about arrays with known dimensions by creating: // fir.convert %arg0 : (!fir.ref>) -> // !fir.ref> - if (auto refTy = op.getValue().getType().dyn_cast()) - if (auto arrTy = refTy.getEleTy().dyn_cast()) { + if (auto refTy = + mlir::dyn_cast(op.getValue().getType())) + if (auto arrTy = mlir::dyn_cast(refTy.getEleTy())) { fir::SequenceType::Shape flatShape = { fir::SequenceType::getUnknownExtent()}; auto flatArrTy = fir::SequenceType::get(flatShape, arrTy.getEleTy()); @@ -158,7 +159,7 @@ public: mlir::ConversionTarget target(*context); target.addIllegalOp(); target.addDynamicallyLegalOp([](fir::ConvertOp op) { - if (op.getRes().getType().isa()) + if (mlir::isa(op.getRes().getType())) return false; return true; }); diff --git a/flang/lib/Optimizer/Transforms/AffinePromotion.cpp b/flang/lib/Optimizer/Transforms/AffinePromotion.cpp index 64531cb1868e..7d0131ac6fa4 100644 --- a/flang/lib/Optimizer/Transforms/AffinePromotion.cpp +++ b/flang/lib/Optimizer/Transforms/AffinePromotion.cpp @@ -111,7 +111,7 @@ private: bool analyzeReference(mlir::Value memref, mlir::Operation *op) { if (auto acoOp = memref.getDefiningOp()) { - if (acoOp.getMemref().getType().isa()) { + if (mlir::isa(acoOp.getMemref().getType())) { // TODO: Look if and how fir.box can be promoted to affine. LLVM_DEBUG(llvm::dbgs() << "AffineLoopAnalysis: cannot promote loop, " "array memory operation uses fir.box\n"; @@ -222,7 +222,7 @@ private: return affineBinaryOp(mlir::AffineExprKind::Mod, op.getLhs(), op.getRhs()); if (auto op = value.getDefiningOp()) - if (auto intConstant = op.getValue().dyn_cast()) + if (auto intConstant = mlir::dyn_cast(op.getValue())) return toAffineExpr(intConstant.getInt()); if (auto blockArg = mlir::dyn_cast(value)) { affineArgs.push_back(value); @@ -331,15 +331,16 @@ static mlir::AffineMap createArrayIndexAffineMap(unsigned dimensions, static std::optional constantIntegerLike(const mlir::Value value) { if (auto definition = value.getDefiningOp()) - if (auto stepAttr = definition.getValue().dyn_cast()) + if (auto stepAttr = mlir::dyn_cast(definition.getValue())) return stepAttr.getInt(); return {}; } static mlir::Type coordinateArrayElement(fir::ArrayCoorOp op) { if (auto refType = - op.getMemref().getType().dyn_cast_or_null()) { - if (auto seqType = refType.getEleTy().dyn_cast_or_null()) { + mlir::dyn_cast_or_null(op.getMemref().getType())) { + if (auto seqType = + mlir::dyn_cast_or_null(refType.getEleTy())) { return seqType.getEleTy(); } } diff --git a/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp b/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp index a08d58383d3a..ebc186222525 100644 --- a/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp +++ b/flang/lib/Optimizer/Transforms/ArrayValueCopy.cpp @@ -461,9 +461,9 @@ void ArrayCopyAnalysisBase::arrayMentions( } static bool hasPointerType(mlir::Type type) { - if (auto boxTy = type.dyn_cast()) + if (auto boxTy = mlir::dyn_cast(type)) type = boxTy.getEleTy(); - return type.isa(); + return mlir::isa(type); } // This is a NF performance hack. It makes a simple test that the slices of the @@ -512,7 +512,7 @@ static bool mutuallyExclusiveSliceRange(ArrayLoadOp ld, ArrayMergeStoreOp st) { auto isPositiveConstant = [](mlir::Value v) -> bool { if (auto conOp = mlir::dyn_cast(v.getDefiningOp())) - if (auto iattr = conOp.getValue().dyn_cast()) + if (auto iattr = mlir::dyn_cast(conOp.getValue())) return iattr.getInt() > 0; return false; }; @@ -725,8 +725,8 @@ static bool conservativeCallConflict(llvm::ArrayRef reaches) { return llvm::any_of(reaches, [](mlir::Operation *op) { if (auto call = mlir::dyn_cast(op)) - if (auto callee = - call.getCallableForCallee().dyn_cast()) { + if (auto callee = mlir::dyn_cast( + call.getCallableForCallee())) { auto module = op->getParentOfType(); return isInternalProcedure( module.lookupSymbol(callee)); @@ -891,9 +891,9 @@ static mlir::Value getOrReadExtentsAndShapeOp( if (arrLoad->hasAttr(fir::getOptionalAttrName())) fir::emitFatalError( loc, "shapes from array load of OPTIONAL arrays must not be used"); - if (auto boxTy = arrLoad.getMemref().getType().dyn_cast()) { + if (auto boxTy = mlir::dyn_cast(arrLoad.getMemref().getType())) { auto rank = - dyn_cast_ptrOrBoxEleTy(boxTy).cast().getDimension(); + mlir::cast(dyn_cast_ptrOrBoxEleTy(boxTy)).getDimension(); auto idxTy = rewriter.getIndexType(); for (decltype(rank) dim = 0; dim < rank; ++dim) { auto dimVal = rewriter.create(loc, dim); @@ -929,7 +929,7 @@ static mlir::Type toRefType(mlir::Type ty) { static llvm::SmallVector getTypeParamsIfRawData(mlir::Location loc, FirOpBuilder &builder, ArrayLoadOp arrLoad, mlir::Type ty) { - if (ty.isa()) + if (mlir::isa(ty)) return {}; return fir::factory::getTypeParams(loc, builder, arrLoad); } @@ -947,8 +947,8 @@ static mlir::Value genCoorOp(mlir::PatternRewriter &rewriter, originated = factory::originateIndices(loc, rewriter, alloc.getType(), shape, indices); auto seqTy = dyn_cast_ptrOrBoxEleTy(alloc.getType()); - assert(seqTy && seqTy.isa()); - const auto dimension = seqTy.cast().getDimension(); + assert(seqTy && mlir::isa(seqTy)); + const auto dimension = mlir::cast(seqTy).getDimension(); auto module = load->getParentOfType(); FirOpBuilder builder(rewriter, module); auto typeparams = getTypeParamsIfRawData(loc, builder, load, alloc.getType()); @@ -967,7 +967,7 @@ static mlir::Value getCharacterLen(mlir::Location loc, FirOpBuilder &builder, ArrayLoadOp load, CharacterType charTy) { auto charLenTy = builder.getCharacterLengthType(); if (charTy.hasDynamicLen()) { - if (load.getMemref().getType().isa()) { + if (mlir::isa(load.getMemref().getType())) { // The loaded array is an emboxed value. Get the CHARACTER length from // the box value. auto eleSzInBytes = @@ -1027,7 +1027,7 @@ void genArrayCopy(mlir::Location loc, mlir::PatternRewriter &rewriter, getTypeParamsIfRawData(loc, builder, arrLoad, dst.getType())); auto eleTy = unwrapSequenceType(unwrapPassByRefType(dst.getType())); // Copy from (to) object to (from) temp copy of same object. - if (auto charTy = eleTy.dyn_cast()) { + if (auto charTy = mlir::dyn_cast(eleTy)) { auto len = getCharacterLen(loc, builder, arrLoad, charTy); CharBoxValue toChar(toAddr, len); CharBoxValue fromChar(fromAddr, len); @@ -1049,8 +1049,8 @@ genArrayLoadTypeParameters(mlir::Location loc, mlir::PatternRewriter &rewriter, auto eleTy = unwrapSequenceType(unwrapPassByRefType(load.getMemref().getType())); if (hasDynamicSize(eleTy)) { - if (auto charTy = eleTy.dyn_cast()) { - assert(load.getMemref().getType().isa()); + if (auto charTy = mlir::dyn_cast(eleTy)) { + assert(mlir::isa(load.getMemref().getType())); auto module = load->getParentOfType(); FirOpBuilder builder(rewriter, module); return {getCharacterLen(loc, builder, load, charTy)}; @@ -1067,7 +1067,7 @@ findNonconstantExtents(mlir::Type memrefTy, llvm::ArrayRef extents) { llvm::SmallVector nce; auto arrTy = unwrapPassByRefType(memrefTy); - auto seqTy = arrTy.cast(); + auto seqTy = mlir::cast(arrTy); for (auto [s, x] : llvm::zip(seqTy.getShape(), extents)) if (s == SequenceType::getUnknownExtent()) nce.emplace_back(x); diff --git a/flang/lib/Optimizer/Transforms/CharacterConversion.cpp b/flang/lib/Optimizer/Transforms/CharacterConversion.cpp index 87ea72dbca9b..44baad73aa25 100644 --- a/flang/lib/Optimizer/Transforms/CharacterConversion.cpp +++ b/flang/lib/Optimizer/Transforms/CharacterConversion.cpp @@ -60,8 +60,8 @@ public: // For each code point in the `from` string, convert naively to the `to` // string code point. Conversion is done blindly on size only, not value. auto getCharBits = [&](mlir::Type t) { - auto chrTy = fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t)) - .cast(); + auto chrTy = mlir::cast( + fir::unwrapSequenceType(fir::dyn_cast_ptrEleTy(t))); return kindMap.getCharacterBitsize(chrTy.getFKind()); }; auto fromBits = getCharBits(conv.getFrom().getType()); diff --git a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp index 0afc9c24b45b..38cdc2b1388d 100644 --- a/flang/lib/Optimizer/Transforms/LoopVersioning.cpp +++ b/flang/lib/Optimizer/Transforms/LoopVersioning.cpp @@ -147,7 +147,7 @@ struct ArgsUsageInLoop { static fir::SequenceType getAsSequenceType(mlir::Value *v) { mlir::Type argTy = fir::unwrapPassByRefType(fir::unwrapRefType(v->getType())); - return argTy.dyn_cast(); + return mlir::dyn_cast(argTy); } /// if a value comes from a fir.declare, follow it to the original source, diff --git a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp index 40b452a6202b..ada67b4201e1 100644 --- a/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp +++ b/flang/lib/Optimizer/Transforms/MemoryAllocation.cpp @@ -65,7 +65,7 @@ keepStackAllocation(fir::AllocaOp alloca, mlir::Block *entry, // TODO: Generalize the algorithm and placement of the freemem nodes. if (alloca->getBlock() != entry) return true; - if (auto seqTy = alloca.getInType().dyn_cast()) { + if (auto seqTy = mlir::dyn_cast(alloca.getInType())) { if (fir::hasDynamicSize(seqTy)) { // Move all arrays with runtime determined size to the heap. if (options.dynamicArrayOnHeap) diff --git a/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp b/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp index 93efea434cb1..d933dc58f375 100644 --- a/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp +++ b/flang/lib/Optimizer/Transforms/PolymorphicOpConversion.cpp @@ -97,8 +97,8 @@ struct DispatchOpConv : public OpConversionPattern { // Get derived type information. mlir::Type declaredType = fir::getDerivedType(dispatch.getObject().getType().getEleTy()); - assert(declaredType.isa() && "expecting fir.type"); - auto recordType = declaredType.dyn_cast(); + assert(mlir::isa(declaredType) && "expecting fir.type"); + auto recordType = mlir::dyn_cast(declaredType); // Lookup for the binding table. auto bindingsIter = bindingTables.find(recordType.getName()); @@ -157,7 +157,7 @@ struct DispatchOpConv : public OpConversionPattern { // Load the bindings descriptor. auto bindingsCompName = Fortran::semantics::bindingDescCompName; - fir::RecordType typeDescRecTy = typeDescTy.cast(); + fir::RecordType typeDescRecTy = mlir::cast(typeDescTy); mlir::Value field = rewriter.create( loc, fieldTy, bindingsCompName, typeDescRecTy, mlir::ValueRange{}); mlir::Type coorTy = @@ -168,8 +168,8 @@ struct DispatchOpConv : public OpConversionPattern { // Load the correct binding. mlir::Value bindings = rewriter.create(loc, bindingBox); - fir::RecordType bindingTy = - fir::unwrapIfDerived(bindingBox.getType().cast()); + fir::RecordType bindingTy = fir::unwrapIfDerived( + mlir::cast(bindingBox.getType())); mlir::Type bindingAddrTy = fir::ReferenceType::get(bindingTy); mlir::Value bindingIdxVal = rewriter.create( loc, rewriter.getIndexType(), rewriter.getIndexAttr(bindingIdx)); @@ -181,7 +181,7 @@ struct DispatchOpConv : public OpConversionPattern { mlir::Value procField = rewriter.create( loc, fieldTy, procCompName, bindingTy, mlir::ValueRange{}); fir::RecordType procTy = - bindingTy.getType(procCompName).cast(); + mlir::cast(bindingTy.getType(procCompName)); mlir::Type procRefTy = fir::ReferenceType::get(procTy); mlir::Value procRef = rewriter.create( loc, procRefTy, bindingAddr, procField); @@ -298,13 +298,13 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( // before in the list to respect point 3. above. Otherwise it is just // added in order at the end. for (unsigned t = 0; t < typeGuardNum; ++t) { - if (auto a = typeGuards[t].dyn_cast()) { + if (auto a = mlir::dyn_cast(typeGuards[t])) { orderedTypeGuards.push_back(t); continue; } - if (auto a = typeGuards[t].dyn_cast()) { - if (auto recTy = a.getType().dyn_cast()) { + if (auto a = mlir::dyn_cast(typeGuards[t])) { + if (auto recTy = mlir::dyn_cast(a.getType())) { auto dt = mod.lookupSymbol(recTy.getName()); assert(dt && "dispatch table not found"); llvm::SmallSet ancestors = @@ -313,8 +313,8 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( auto it = orderedClassIsGuards.begin(); while (it != orderedClassIsGuards.end()) { fir::SubclassAttr sAttr = - typeGuards[*it].dyn_cast(); - if (auto ty = sAttr.getType().dyn_cast()) { + mlir::dyn_cast(typeGuards[*it]); + if (auto ty = mlir::dyn_cast(sAttr.getType())) { if (ancestors.contains(ty.getName())) break; } @@ -339,7 +339,7 @@ mlir::LogicalResult SelectTypeConv::matchAndRewrite( auto *dest = selectType.getSuccessor(idx); std::optional destOps = selectType.getSuccessorOperands(operands, idx); - if (typeGuards[idx].dyn_cast()) + if (mlir::dyn_cast(typeGuards[idx])) rewriter.replaceOpWithNewOp( selectType, dest, destOps.value_or(mlir::ValueRange{})); else if (mlir::failed(genTypeLadderStep(loc, selector, typeGuards[idx], @@ -357,9 +357,9 @@ mlir::LogicalResult SelectTypeConv::genTypeLadderStep( fir::KindMapping &kindMap) const { mlir::Value cmp; // TYPE IS type guard comparison are all done inlined. - if (auto a = attr.dyn_cast()) { + if (auto a = mlir::dyn_cast(attr)) { if (fir::isa_trivial(a.getType()) || - a.getType().isa()) { + mlir::isa(a.getType())) { // For type guard statement with Intrinsic type spec the type code of // the descriptor is compared. int code = fir::getTypeCode(a.getType(), kindMap); @@ -383,10 +383,10 @@ mlir::LogicalResult SelectTypeConv::genTypeLadderStep( cmp = res; } // CLASS IS type guard statement is done with a runtime call. - } else if (auto a = attr.dyn_cast()) { + } else if (auto a = mlir::dyn_cast(attr)) { // Retrieve the type descriptor from the type guard statement record type. - assert(a.getType().isa() && "expect fir.record type"); - fir::RecordType recTy = a.getType().dyn_cast(); + assert(mlir::isa(a.getType()) && "expect fir.record type"); + fir::RecordType recTy = mlir::dyn_cast(a.getType()); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recTy.getName()); auto typeDescGlobal = mod.lookupSymbol(typeDescName); @@ -438,8 +438,8 @@ mlir::Value SelectTypeConv::genTypeDescCompare(mlir::Location loc, mlir::Value selector, mlir::Type ty, mlir::ModuleOp mod, mlir::PatternRewriter &rewriter) const { - assert(ty.isa() && "expect fir.record type"); - fir::RecordType recTy = ty.dyn_cast(); + assert(mlir::isa(ty) && "expect fir.record type"); + fir::RecordType recTy = mlir::dyn_cast(ty); std::string typeDescName = fir::NameUniquer::getTypeDescriptorName(recTy.getName()); auto typeDescGlobal = mod.lookupSymbol(typeDescName); diff --git a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp index a4f2f5238e40..601bf04ce5e9 100644 --- a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp +++ b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp @@ -215,8 +215,8 @@ static unsigned getDimCount(mlir::Value val) { // the first ConvertOp that has non-opaque box type that we meet // going through the ConvertOp chain. if (mlir::Value emboxVal = findBoxDef(val)) - if (auto boxTy = emboxVal.getType().dyn_cast()) - if (auto seqTy = boxTy.getEleTy().dyn_cast()) + if (auto boxTy = mlir::dyn_cast(emboxVal.getType())) + if (auto seqTy = mlir::dyn_cast(boxTy.getEleTy())) return seqTy.getDimension(); return 0; } @@ -237,9 +237,9 @@ static std::optional getArgElementType(mlir::Value val) { val = defOp->getOperand(0); // The convert operation is expected to convert from one // box type to another box type. - auto boxType = val.getType().cast(); + auto boxType = mlir::cast(val.getType()); auto elementType = fir::unwrapSeqOrBoxedSeqType(boxType); - if (!elementType.isa()) + if (!mlir::isa(elementType)) return elementType; } while (true); } @@ -381,7 +381,7 @@ static void genRuntimeSumBody(fir::FirOpBuilder &builder, // end function RTNAME(Sum)x_simplified auto zero = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant(loc, elementType, llvm::APFloat::getZero(sem)); @@ -392,9 +392,9 @@ static void genRuntimeSumBody(fir::FirOpBuilder &builder, auto genBodyOp = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType, mlir::Value elem1, mlir::Value elem2) -> mlir::Value { - if (elementType.isa()) + if (mlir::isa(elementType)) return builder.create(loc, elem1, elem2); - if (elementType.isa()) + if (mlir::isa(elementType)) return builder.create(loc, elem1, elem2); llvm_unreachable("unsupported type"); @@ -414,7 +414,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, mlir::Type elementType) { auto init = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); return builder.createRealConstant( loc, elementType, llvm::APFloat::getLargest(sem, /*Negative=*/true)); @@ -427,7 +427,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, auto genBodyOp = [](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType, mlir::Value elem1, mlir::Value elem2) -> mlir::Value { - if (elementType.isa()) { + if (mlir::isa(elementType)) { // arith.maxf later converted to llvm.intr.maxnum does not work // correctly for NaNs and -0.0 (see maxnum/minnum pattern matching // in LLVM's InstCombine pass). Moreover, llvm.intr.maxnum @@ -439,7 +439,7 @@ static void genRuntimeMaxvalBody(fir::FirOpBuilder &builder, loc, mlir::arith::CmpFPredicate::OGT, elem1, elem2); return builder.create(loc, compare, elem1, elem2); } - if (elementType.isa()) + if (mlir::isa(elementType)) return builder.create(loc, elem1, elem2); llvm_unreachable("unsupported type"); @@ -662,7 +662,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, mlir::Type resultElemTy, bool isDim) { auto init = [isMax](fir::FirOpBuilder builder, mlir::Location loc, mlir::Type elementType) { - if (auto ty = elementType.dyn_cast()) { + if (auto ty = mlir::dyn_cast(elementType)) { const llvm::fltSemantics &sem = ty.getFloatSemantics(); llvm::APFloat limit = llvm::APFloat::getInf(sem, /*Negative=*/isMax); return builder.createRealConstant(loc, elementType, limit); @@ -744,7 +744,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, mlir::Value elem = builder.create(loc, addr); mlir::Value cmp; - if (elementType.isa()) { + if (mlir::isa(elementType)) { // For FP reductions we want the first smallest value to be used, that // is not NaN. A OGL/OLT condition will usually work for this unless all // the values are Nan or Inf. This follows the same logic as @@ -761,7 +761,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, loc, mlir::arith::CmpFPredicate::OEQ, elem, elem); cmpNan = builder.create(loc, cmpNan, cmpNan2); cmp = builder.create(loc, cmp, cmpNan); - } else if (elementType.isa()) { + } else if (mlir::isa(elementType)) { cmp = builder.create( loc, isMax ? mlir::arith::CmpIPredicate::sgt @@ -839,7 +839,7 @@ static void genRuntimeMinMaxlocBody(fir::FirOpBuilder &builder, builder.setInsertionPointToStart(&ifOp.getElseRegion().front()); mlir::Value basicValue; - if (elementType.isa()) { + if (mlir::isa(elementType)) { basicValue = builder.createIntegerConstant(loc, elementType, 0); } else { basicValue = builder.createRealConstant(loc, elementType, 0); @@ -921,7 +921,7 @@ static void genRuntimeDotBody(fir::FirOpBuilder &builder, mlir::IndexType idxTy = builder.getIndexType(); mlir::Value zero = - resultElementType.isa() + mlir::isa(resultElementType) ? builder.createRealConstant(loc, resultElementType, 0.0) : builder.createIntegerConstant(loc, resultElementType, 0); @@ -978,10 +978,10 @@ static void genRuntimeDotBody(fir::FirOpBuilder &builder, // Convert to the result type. elem2 = builder.create(loc, resultElementType, elem2); - if (resultElementType.isa()) + if (mlir::isa(resultElementType)) sumVal = builder.create( loc, builder.create(loc, elem1, elem2), sumVal); - else if (resultElementType.isa()) + else if (mlir::isa(resultElementType)) sumVal = builder.create( loc, builder.create(loc, elem1, elem2), sumVal); else @@ -1056,8 +1056,8 @@ void SimplifyIntrinsicsPass::simplifyIntOrFloatReduction( mlir::Type resultType = call.getResult(0).getType(); - if (!resultType.isa() && - !resultType.isa()) + if (!mlir::isa(resultType) && + !mlir::isa(resultType)) return; auto argType = getArgElementType(args[0]); @@ -1103,7 +1103,8 @@ void SimplifyIntrinsicsPass::simplifyLogicalDim0Reduction( fir::FirOpBuilder builder{getSimplificationBuilder(call, kindMap)}; // Treating logicals as integers makes things a lot easier - fir::LogicalType logicalType = {elementType.dyn_cast()}; + fir::LogicalType logicalType = { + mlir::dyn_cast(elementType)}; fir::KindTy kind = logicalType.getFKind(); mlir::Type intElementType = builder.getIntegerType(kind * 8); @@ -1138,7 +1139,8 @@ void SimplifyIntrinsicsPass::simplifyLogicalDim1Reduction( fir::FirOpBuilder builder{getSimplificationBuilder(call, kindMap)}; // Treating logicals as integers makes things a lot easier - fir::LogicalType logicalType = {elementType.dyn_cast()}; + fir::LogicalType logicalType = { + mlir::dyn_cast(elementType)}; fir::KindTy kind = logicalType.getFKind(); mlir::Type intElementType = builder.getIntegerType(kind * 8); @@ -1182,7 +1184,7 @@ void SimplifyIntrinsicsPass::simplifyMinMaxlocReduction( auto inputBox = findBoxDef(args[1]); mlir::Type inputType = hlfir::getFortranElementType(inputBox.getType()); - if (inputType.isa()) + if (mlir::isa(inputType)) return; int maskRank; @@ -1193,7 +1195,8 @@ void SimplifyIntrinsicsPass::simplifyMinMaxlocReduction( } else { maskRank = getDimCount(mask); mlir::Type maskElemTy = hlfir::getFortranElementType(maskDef.getType()); - fir::LogicalType logicalFirType = {maskElemTy.dyn_cast()}; + fir::LogicalType logicalFirType = { + mlir::dyn_cast(maskElemTy)}; kind = logicalFirType.getFKind(); // Convert fir::LogicalType to mlir::Type logicalElemType = logicalFirType; @@ -1302,7 +1305,8 @@ void SimplifyIntrinsicsPass::runOnOperation() { std::string fmfString{builder.getFastMathFlagsString()}; mlir::Type type = call.getResult(0).getType(); - if (!type.isa() && !type.isa()) + if (!mlir::isa(type) && + !mlir::isa(type)) return; // Try to find the element types of the boxed arguments. diff --git a/flang/lib/Optimizer/Transforms/StackArrays.cpp b/flang/lib/Optimizer/Transforms/StackArrays.cpp index c81524dd16a7..16bbb1c35646 100644 --- a/flang/lib/Optimizer/Transforms/StackArrays.cpp +++ b/flang/lib/Optimizer/Transforms/StackArrays.cpp @@ -351,7 +351,7 @@ void AllocationAnalysis::visitOperation(mlir::Operation *op, } auto retTy = allocmem.getAllocatedType(); - if (!retTy.isa()) { + if (!mlir::isa(retTy)) { LLVM_DEBUG(llvm::dbgs() << "--Allocation is not for an array: skipping\n"); return; diff --git a/flang/unittests/Optimizer/Builder/ComplexTest.cpp b/flang/unittests/Optimizer/Builder/ComplexTest.cpp index 5364eec904ff..17171512470a 100644 --- a/flang/unittests/Optimizer/Builder/ComplexTest.cpp +++ b/flang/unittests/Optimizer/Builder/ComplexTest.cpp @@ -96,6 +96,6 @@ TEST_F(ComplexTest, verifyConvertWithSemantics) { // Convert complex to integer mlir::Value v2 = firBuilder->convertWithSemantics(loc, integerTy1, v1); - EXPECT_TRUE(v2.getType().isa()); + EXPECT_TRUE(mlir::isa(v2.getType())); EXPECT_TRUE(mlir::dyn_cast(v2.getDefiningOp())); } diff --git a/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp b/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp index 7e7206dbf934..d0a9342914a3 100644 --- a/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp +++ b/flang/unittests/Optimizer/Builder/DoLoopHelperTest.cpp @@ -34,7 +34,7 @@ public: void checkConstantValue(const mlir::Value &value, int64_t v) { EXPECT_TRUE(mlir::isa(value.getDefiningOp())); auto cstOp = dyn_cast(value.getDefiningOp()); - auto valueAttr = cstOp.getValue().dyn_cast_or_null(); + auto valueAttr = dyn_cast_or_null(cstOp.getValue()); EXPECT_EQ(v, valueAttr.getInt()); } diff --git a/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp b/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp index b6a1f9c9db8f..e5e5454ee88a 100644 --- a/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp +++ b/flang/unittests/Optimizer/Builder/FIRBuilderTest.cpp @@ -54,7 +54,7 @@ static void checkIntegerConstant(mlir::Value value, mlir::Type ty, int64_t v) { EXPECT_TRUE(mlir::isa(value.getDefiningOp())); auto cstOp = dyn_cast(value.getDefiningOp()); EXPECT_EQ(ty, cstOp.getType()); - auto valueAttr = cstOp.getValue().dyn_cast_or_null(); + auto valueAttr = mlir::dyn_cast_or_null(cstOp.getValue()); EXPECT_EQ(v, valueAttr.getInt()); } @@ -151,7 +151,7 @@ TEST_F(FIRBuilderTest, createRealZeroConstant) { auto cstOp = dyn_cast(cst.getDefiningOp()); EXPECT_EQ(realTy, cstOp.getType()); EXPECT_EQ( - 0u, cstOp.getValue().cast().getValue().convertToDouble()); + 0u, mlir::cast(cstOp.getValue()).getValue().convertToDouble()); } TEST_F(FIRBuilderTest, createBool) { @@ -164,8 +164,8 @@ TEST_F(FIRBuilderTest, createBool) { TEST_F(FIRBuilderTest, getVarLenSeqTy) { auto builder = getBuilder(); auto ty = builder.getVarLenSeqTy(builder.getI64Type()); - EXPECT_TRUE(ty.isa()); - fir::SequenceType seqTy = ty.dyn_cast(); + EXPECT_TRUE(mlir::isa(ty)); + fir::SequenceType seqTy = mlir::dyn_cast(ty); EXPECT_EQ(1u, seqTy.getDimension()); EXPECT_TRUE(fir::unwrapSequenceType(ty).isInteger(64)); } @@ -216,9 +216,9 @@ TEST_F(FIRBuilderTest, createGlobal2) { EXPECT_FALSE(global.getConstant().has_value()); EXPECT_EQ(i32Type, global.getType()); EXPECT_TRUE(global.getInitVal().has_value()); - EXPECT_TRUE(global.getInitVal().value().isa()); - EXPECT_EQ( - 16, global.getInitVal().value().cast().getValue()); + EXPECT_TRUE(mlir::isa(global.getInitVal().value())); + EXPECT_EQ(16, + mlir::cast(global.getInitVal().value()).getValue()); EXPECT_TRUE(global.getLinkName().has_value()); EXPECT_EQ( builder.createLinkOnceLinkage().getValue(), global.getLinkName().value()); @@ -271,12 +271,12 @@ TEST_F(FIRBuilderTest, locationToFilename) { auto stringLitOps = global.getRegion().front().getOps(); EXPECT_TRUE(llvm::hasSingleElement(stringLitOps)); for (auto stringLit : stringLitOps) { - EXPECT_EQ(10, stringLit.getSize().cast().getValue()); - EXPECT_TRUE(stringLit.getValue().isa()); + EXPECT_EQ( + 10, mlir::cast(stringLit.getSize()).getValue()); + EXPECT_TRUE(mlir::isa(stringLit.getValue())); EXPECT_EQ(0, strcmp("file1.f90\0", - stringLit.getValue() - .dyn_cast() + mlir::dyn_cast(stringLit.getValue()) .getValue() .str() .c_str())); @@ -288,9 +288,9 @@ TEST_F(FIRBuilderTest, createStringLitOp) { llvm::StringRef data("mystringlitdata"); auto loc = builder.getUnknownLoc(); auto op = builder.createStringLitOp(loc, data); - EXPECT_EQ(15, op.getSize().cast().getValue()); - EXPECT_TRUE(op.getValue().isa()); - EXPECT_EQ(data, op.getValue().dyn_cast().getValue()); + EXPECT_EQ(15, mlir::cast(op.getSize()).getValue()); + EXPECT_TRUE(mlir::isa(op.getValue())); + EXPECT_EQ(data, mlir::dyn_cast(op.getValue()).getValue()); } TEST_F(FIRBuilderTest, createStringLiteral) { @@ -318,9 +318,11 @@ TEST_F(FIRBuilderTest, createStringLiteral) { auto stringLitOps = global.getRegion().front().getOps(); EXPECT_TRUE(llvm::hasSingleElement(stringLitOps)); for (auto stringLit : stringLitOps) { - EXPECT_EQ(16, stringLit.getSize().cast().getValue()); - EXPECT_TRUE(stringLit.getValue().isa()); - EXPECT_EQ(strValue, stringLit.getValue().dyn_cast().getValue()); + EXPECT_EQ( + 16, mlir::cast(stringLit.getSize()).getValue()); + EXPECT_TRUE(mlir::isa(stringLit.getValue())); + EXPECT_EQ( + strValue, mlir::dyn_cast(stringLit.getValue()).getValue()); } } @@ -344,7 +346,7 @@ TEST_F(FIRBuilderTest, allocateLocal) { static void checkShapeOp(mlir::Value shape, mlir::Value c10, mlir::Value c100) { EXPECT_TRUE(mlir::isa(shape.getDefiningOp())); fir::ShapeOp op = dyn_cast(shape.getDefiningOp()); - auto shapeTy = op.getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(op.getType()); EXPECT_EQ(2u, shapeTy.getRank()); EXPECT_EQ(2u, op.getExtents().size()); EXPECT_EQ(c10, op.getExtents()[0]); @@ -372,7 +374,7 @@ TEST_F(FIRBuilderTest, genShapeWithExtentsAndShapeShift) { auto shape = builder.genShape(loc, shifts, extents); EXPECT_TRUE(mlir::isa(shape.getDefiningOp())); fir::ShapeShiftOp op = dyn_cast(shape.getDefiningOp()); - auto shapeTy = op.getType().dyn_cast(); + auto shapeTy = mlir::dyn_cast(op.getType()); EXPECT_EQ(2u, shapeTy.getRank()); EXPECT_EQ(2u, op.getExtents().size()); EXPECT_EQ(2u, op.getOrigins().size()); @@ -428,7 +430,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst = mlir::dyn_cast_or_null(zeroInt.getDefiningOp()); EXPECT_TRUE(cst); - auto intAttr = cst.getValue().dyn_cast(); + auto intAttr = mlir::dyn_cast(cst.getValue()); EXPECT_TRUE(intAttr && intAttr.getInt() == 0); mlir::Type f32Ty = mlir::FloatType::getF32(builder.getContext()); @@ -437,7 +439,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst2 = mlir::dyn_cast_or_null( zeroFloat.getDefiningOp()); EXPECT_TRUE(cst2); - auto floatAttr = cst2.getValue().dyn_cast(); + auto floatAttr = mlir::dyn_cast(cst2.getValue()); EXPECT_TRUE(floatAttr && floatAttr.getValueAsDouble() == 0.); mlir::Type boolTy = mlir::IntegerType::get(builder.getContext(), 1); @@ -446,7 +448,7 @@ TEST_F(FIRBuilderTest, createZeroValue) { auto cst3 = mlir::dyn_cast_or_null( flaseBool.getDefiningOp()); EXPECT_TRUE(cst3); - auto intAttr2 = cst.getValue().dyn_cast(); + auto intAttr2 = mlir::dyn_cast(cst.getValue()); EXPECT_TRUE(intAttr2 && intAttr2.getInt() == 0); } @@ -482,7 +484,7 @@ TEST_F(FIRBuilderTest, getBaseTypeOf) { llvm::SmallVector arrays; auto extent = builder.create(loc, builder.getIndexType()); llvm::SmallVector extents( - arrayType.dyn_cast().getDimension(), + mlir::dyn_cast(arrayType).getDimension(), extent.getResult()); arrays.emplace_back(fir::ArrayBoxValue(ptrValArray, extents)); arrays.emplace_back(fir::BoxValue(boxValArray)); diff --git a/flang/unittests/Optimizer/RTBuilder.cpp b/flang/unittests/Optimizer/RTBuilder.cpp index 7fff7f71fc3b..d6cf96c4351c 100644 --- a/flang/unittests/Optimizer/RTBuilder.cpp +++ b/flang/unittests/Optimizer/RTBuilder.cpp @@ -27,7 +27,7 @@ TEST(RTBuilderTest, ComplexRuntimeInterface) { mlir::Type c99_cacosf_signature{ fir::runtime::RuntimeTableKey::getTypeModel()( &ctx)}; - auto c99_cacosf_funcTy = c99_cacosf_signature.cast(); + auto c99_cacosf_funcTy = mlir::cast(c99_cacosf_signature); EXPECT_EQ(c99_cacosf_funcTy.getNumInputs(), 1u); EXPECT_EQ(c99_cacosf_funcTy.getNumResults(), 1u); auto cplx_ty = fir::ComplexType::get(&ctx, 4); diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td index da12e7c83b22..64c538367267 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgOps.td @@ -138,10 +138,10 @@ def Linalg_SoftmaxOp : Linalg_Op<"softmax", let extraClassDeclaration = [{ ShapedType getInputOperandType() { - return getInput().getType().cast(); + return cast(getInput().getType()); } ShapedType getOutputOperandType() { - return getOutput().getType().cast(); + return cast(getOutput().getType()); } int64_t getInputOperandRank() { return getInputOperandType().getRank(); diff --git a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td index ab9b78e755d9..d9569d9d294d 100644 --- a/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td +++ b/mlir/include/mlir/Dialect/OpenMP/OpenMPOpsInterfaces.td @@ -234,8 +234,8 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getIsTargetDevice", (ins), [{}], [{ if (Attribute isTargetDevice = $_op->getAttr("omp.is_target_device")) - if (isTargetDevice.isa()) - return isTargetDevice.dyn_cast().getValue(); + if (::llvm::isa(isTargetDevice)) + return ::llvm::dyn_cast(isTargetDevice).getValue(); return false; }]>, InterfaceMethod< @@ -259,7 +259,7 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getIsGPU", (ins), [{}], [{ if (Attribute isTargetCGAttr = $_op->getAttr("omp.is_gpu")) - if (auto isTargetCGVal = isTargetCGAttr.dyn_cast()) + if (auto isTargetCGVal = ::llvm::dyn_cast(isTargetCGAttr)) return isTargetCGVal.getValue(); return false; }]>, @@ -332,7 +332,7 @@ def OffloadModuleInterface : OpInterface<"OffloadModuleInterface"> { /*methodName=*/"getRequires", (ins), [{}], [{ if (Attribute requiresAttr = $_op->getAttr("omp.requires")) - if (auto requiresVal = requiresAttr.dyn_cast()) + if (auto requiresVal = ::llvm::dyn_cast(requiresAttr)) return requiresVal.getValue(); return mlir::omp::ClauseRequires::none; }]>, diff --git a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td index 88f2e1acfeeb..e477d9a0ca3f 100644 --- a/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td +++ b/mlir/include/mlir/Dialect/XeGPU/IR/XeGPUOps.td @@ -164,10 +164,10 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// source operand. They overide static shape from source memref type. ArrayRef getStaticSizes() { auto attr = getConstShapeAttr(); - if (getSourceType().isa() || attr) + if (llvm::isa(getSourceType()) || attr) return attr; - auto memrefType = getSourceType().dyn_cast(); + auto memrefType = llvm::dyn_cast(getSourceType()); assert(memrefType && "Incorrect use of getStaticSizes"); return memrefType.getShape(); } @@ -179,10 +179,10 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// source operand. They overide static strides from source memref type. ArrayRef getStaticStrides() { auto attr = getConstStridesAttr(); - if (getSourceType().isa() || attr) + if (llvm::isa(getSourceType()) || attr) return attr; - auto memrefType = getSourceType().dyn_cast(); + auto memrefType = llvm::dyn_cast(getSourceType()); assert(memrefType && "Incorrect use of getStaticStrides"); auto [strides, offset] = getStridesAndOffset(memrefType); // reuse the storage of ConstStridesAttr since strides from @@ -196,7 +196,7 @@ def XeGPU_CreateNdDescOp: XeGPU_Op<"create_nd_tdesc", [Pure, ViewLikeOpInterface /// `static_shape` and `static_strides` attributes. std::array getArrayAttrMaxRanks() { unsigned rank; - if (auto ty = getSourceType().dyn_cast()) { + if (auto ty = llvm::dyn_cast(getSourceType())) { rank = ty.getRank(); } else { rank = (unsigned)getMixedOffsets().size(); diff --git a/mlir/include/mlir/IR/BuiltinLocationAttributes.td b/mlir/include/mlir/IR/BuiltinLocationAttributes.td index dfcc180071f7..5a72404dea15 100644 --- a/mlir/include/mlir/IR/BuiltinLocationAttributes.td +++ b/mlir/include/mlir/IR/BuiltinLocationAttributes.td @@ -228,7 +228,8 @@ def OpaqueLoc : Builtin_LocationAttr<"OpaqueLoc"> { template static T getUnderlyingLocation(Location location) { assert(isa(location)); return reinterpret_cast( - location.cast().getUnderlyingLocation()); + mlir::cast(static_cast(location)) + .getUnderlyingLocation()); } /// Returns a pointer to some data structure that opaque location stores. @@ -237,15 +238,17 @@ def OpaqueLoc : Builtin_LocationAttr<"OpaqueLoc"> { template static T getUnderlyingLocationOrNull(Location location) { return isa(location) - ? reinterpret_cast( - location.cast().getUnderlyingLocation()) - : T(nullptr); + ? reinterpret_cast(mlir::cast( + static_cast(location)) + .getUnderlyingLocation()) + : T(nullptr); } /// Checks whether provided location is opaque location and contains a /// pointer to an object of particular type. template static bool isa(Location location) { - auto opaque_loc = location.dyn_cast(); + auto opaque_loc = + mlir::dyn_cast(static_cast(location)); return opaque_loc && opaque_loc.getUnderlyingTypeID() == TypeID::get(); } }]; diff --git a/mlir/include/mlir/IR/Value.h b/mlir/include/mlir/IR/Value.h index cdbc6cc37436..a7344c64e673 100644 --- a/mlir/include/mlir/IR/Value.h +++ b/mlir/include/mlir/IR/Value.h @@ -98,25 +98,25 @@ public: constexpr Value(detail::ValueImpl *impl = nullptr) : impl(impl) {} template - [[deprecated("Use isa() instead")]] + [[deprecated("Use mlir::isa() instead")]] bool isa() const { return llvm::isa(*this); } template - [[deprecated("Use dyn_cast() instead")]] + [[deprecated("Use mlir::dyn_cast() instead")]] U dyn_cast() const { return llvm::dyn_cast(*this); } template - [[deprecated("Use dyn_cast_or_null() instead")]] + [[deprecated("Use mlir::dyn_cast_or_null() instead")]] U dyn_cast_or_null() const { return llvm::dyn_cast_or_null(*this); } template - [[deprecated("Use cast() instead")]] + [[deprecated("Use mlir::cast() instead")]] U cast() const { return llvm::cast(*this); } diff --git a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp index 4a15976d40c7..c2a83f90bcbe 100644 --- a/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp +++ b/mlir/lib/Conversion/ComplexToStandard/ComplexToStandard.cpp @@ -857,7 +857,7 @@ struct SqrtOpConversion : public OpConversionPattern { ImplicitLocOpBuilder b(op.getLoc(), rewriter); auto type = cast(op.getType()); - auto elementType = type.getElementType().cast(); + auto elementType = cast(type.getElementType()); arith::FastMathFlags fmf = op.getFastMathFlagsAttr().getValue(); auto cst = [&](APFloat v) { diff --git a/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp b/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp index ee09c73bb3c4..f1ec2be72a33 100644 --- a/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp +++ b/mlir/lib/Dialect/Polynomial/IR/PolynomialAttributes.cpp @@ -172,7 +172,7 @@ Attribute RingAttr::parse(AsmParser &parser, Type type) { if (failed(parser.parseEqual())) return {}; - IntegerType iType = ty.dyn_cast(); + IntegerType iType = mlir::dyn_cast(ty); if (!iType) { parser.emitError(parser.getCurrentLocation(), "coefficientType must specify an integer type"); diff --git a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp index 69999f0918c1..802a64b0805e 100644 --- a/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp +++ b/mlir/lib/Dialect/Vector/Transforms/VectorLinearize.cpp @@ -140,7 +140,7 @@ struct LinearizeVectorExtractStridedSlice final ConversionPatternRewriter &rewriter) const override { Type dstType = getTypeConverter()->convertType(extractOp.getType()); assert(!(extractOp.getVector().getType().isScalable() || - dstType.cast().isScalable()) && + cast(dstType).isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(extractOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -172,7 +172,7 @@ struct LinearizeVectorExtractStridedSlice final // Get total number of extracted slices. int64_t nExtractedSlices = 1; for (Attribute size : sizes) { - nExtractedSlices *= size.cast().getInt(); + nExtractedSlices *= cast(size).getInt(); } // Compute the strides of the source vector considering first k dimensions. llvm::SmallVector sourceStrides(kD, extractGranularitySize); @@ -189,7 +189,7 @@ struct LinearizeVectorExtractStridedSlice final // Compute extractedStrides. for (int i = kD - 2; i >= 0; --i) { extractedStrides[i] = - extractedStrides[i + 1] * sizes[i + 1].cast().getInt(); + extractedStrides[i + 1] * cast(sizes[i + 1]).getInt(); } // Iterate over all extracted slices from 0 to nExtractedSlices - 1 // and compute the multi-dimensional index and the corresponding linearized @@ -207,7 +207,7 @@ struct LinearizeVectorExtractStridedSlice final int64_t linearizedIndex = 0; for (int64_t j = 0; j < kD; ++j) { linearizedIndex += - (offsets[j].cast().getInt() + multiDimIndex[j]) * + (cast(offsets[j]).getInt() + multiDimIndex[j]) * sourceStrides[j]; } // Fill the indices array form linearizedIndex to linearizedIndex + @@ -254,7 +254,7 @@ struct LinearizeVectorShuffle final Type dstType = getTypeConverter()->convertType(shuffleOp.getType()); assert(!(shuffleOp.getV1VectorType().isScalable() || shuffleOp.getV2VectorType().isScalable() || - dstType.cast().isScalable()) && + cast(dstType).isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(shuffleOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -324,7 +324,7 @@ struct LinearizeVectorExtract final ConversionPatternRewriter &rewriter) const override { Type dstTy = getTypeConverter()->convertType(extractOp.getType()); assert(!(extractOp.getVector().getType().isScalable() || - dstTy.cast().isScalable()) && + cast(dstTy).isScalable()) && "scalable vectors are not supported."); if (!isLessThanTargetBitWidth(extractOp, targetVectorBitWidth)) return rewriter.notifyMatchFailure( @@ -405,9 +405,7 @@ void mlir::vector::populateVectorLinearizeShuffleLikeOpsPatterns( [=](vector::ShuffleOp shuffleOp) -> bool { return isLessThanTargetBitWidth(shuffleOp, targetBitWidth) ? (typeConverter.isLegal(shuffleOp) && - shuffleOp.getResult() - .getType() - .cast() + cast(shuffleOp.getResult().getType()) .getRank() == 1) : true; }); -- GitLab From aafed3408e7269c42f974189198a47eb6dd2fc84 Mon Sep 17 00:00:00 2001 From: Florian Hahn Date: Sun, 28 Apr 2024 21:56:55 +0100 Subject: [PATCH 167/301] [VPlan] Make createScalarIVSteps return VPScalarIVStepsRecipe (NFC). This avoids the need for using getVPSingleValue/getDefiningRecipe at the place the return value is used. --- .../Transforms/Vectorize/VPlanTransforms.cpp | 30 ++++++++----------- 1 file changed, 13 insertions(+), 17 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp index d7bc128dcfe6..a7337f7aa94d 100644 --- a/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp +++ b/llvm/lib/Transforms/Vectorize/VPlanTransforms.cpp @@ -506,13 +506,12 @@ static void removeDeadRecipes(VPlan &Plan) { } } -static VPValue *createScalarIVSteps(VPlan &Plan, - InductionDescriptor::InductionKind Kind, - Instruction::BinaryOps InductionOpcode, - FPMathOperator *FPBinOp, - ScalarEvolution &SE, Instruction *TruncI, - VPValue *StartV, VPValue *Step, - VPBasicBlock::iterator IP) { +static VPScalarIVStepsRecipe * +createScalarIVSteps(VPlan &Plan, InductionDescriptor::InductionKind Kind, + Instruction::BinaryOps InductionOpcode, + FPMathOperator *FPBinOp, ScalarEvolution &SE, + Instruction *TruncI, VPValue *StartV, VPValue *Step, + VPBasicBlock::iterator IP) { VPBasicBlock *HeaderVPBB = Plan.getVectorLoopRegion()->getEntryBasicBlock(); VPCanonicalIVPHIRecipe *CanonicalIV = Plan.getCanonicalIV(); VPSingleDefRecipe *BaseIV = CanonicalIV; @@ -579,16 +578,13 @@ static void legalizeAndOptimizeInductions(VPlan &Plan, ScalarEvolution &SE) { VPValue *StartV = Plan.getOrAddLiveIn(ConstantInt::get(ID.getStep()->getType(), 0)); VPValue *StepV = PtrIV->getOperand(1); - VPRecipeBase *Steps = - createScalarIVSteps(Plan, InductionDescriptor::IK_IntInduction, - Instruction::Add, nullptr, SE, nullptr, StartV, - StepV, InsertPt) - ->getDefiningRecipe(); + VPScalarIVStepsRecipe *Steps = createScalarIVSteps( + Plan, InductionDescriptor::IK_IntInduction, Instruction::Add, nullptr, + SE, nullptr, StartV, StepV, InsertPt); - auto *Recipe = - new VPInstruction(VPInstruction::PtrAdd, - {PtrIV->getStartValue(), Steps->getVPSingleValue()}, - PtrIV->getDebugLoc(), "next.gep"); + auto *Recipe = new VPInstruction(VPInstruction::PtrAdd, + {PtrIV->getStartValue(), Steps}, + PtrIV->getDebugLoc(), "next.gep"); Recipe->insertAfter(Steps); PtrIV->replaceAllUsesWith(Recipe); @@ -606,7 +602,7 @@ static void legalizeAndOptimizeInductions(VPlan &Plan, ScalarEvolution &SE) { continue; const InductionDescriptor &ID = WideIV->getInductionDescriptor(); - VPValue *Steps = createScalarIVSteps( + VPScalarIVStepsRecipe *Steps = createScalarIVSteps( Plan, ID.getKind(), ID.getInductionOpcode(), dyn_cast_or_null(ID.getInductionBinOp()), SE, WideIV->getTruncInst(), WideIV->getStartValue(), WideIV->getStepValue(), -- GitLab From 9c1de620344b2518bb171be51066e1ec9a5be623 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Sun, 28 Apr 2024 14:05:12 -0700 Subject: [PATCH 168/301] [clang-format][NFC] Return early in isWordLike() for non-Verilog (#90363) --- clang/lib/Format/FormatToken.h | 8 ++++++-- clang/lib/Format/TokenAnnotator.cpp | 13 ++++++++----- 2 files changed, 14 insertions(+), 7 deletions(-) diff --git a/clang/lib/Format/FormatToken.h b/clang/lib/Format/FormatToken.h index f651e6228c20..28b6488e54a4 100644 --- a/clang/lib/Format/FormatToken.h +++ b/clang/lib/Format/FormatToken.h @@ -1623,10 +1623,10 @@ struct AdditionalKeywords { IdentifierInfo *kw_then; /// Returns \c true if \p Tok is a keyword or an identifier. - bool isWordLike(const FormatToken &Tok) const { + bool isWordLike(const FormatToken &Tok, bool IsVerilog = true) const { // getIdentifierinfo returns non-null for keywords as well as identifiers. return Tok.Tok.getIdentifierInfo() && - !Tok.isOneOf(kw_verilogHash, kw_verilogHashHash, kw_apostrophe); + (!IsVerilog || !isVerilogKeywordSymbol(Tok)); } /// Returns \c true if \p Tok is a true JavaScript identifier, returns @@ -1755,6 +1755,10 @@ struct AdditionalKeywords { } } + bool isVerilogKeywordSymbol(const FormatToken &Tok) const { + return Tok.isOneOf(kw_verilogHash, kw_verilogHashHash, kw_apostrophe); + } + bool isVerilogWordOperator(const FormatToken &Tok) const { return Tok.isOneOf(kw_before, kw_intersect, kw_dist, kw_iff, kw_inside, kw_with); diff --git a/clang/lib/Format/TokenAnnotator.cpp b/clang/lib/Format/TokenAnnotator.cpp index 63629fa74318..d366ae2080bc 100644 --- a/clang/lib/Format/TokenAnnotator.cpp +++ b/clang/lib/Format/TokenAnnotator.cpp @@ -4780,9 +4780,14 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, if (Left.Finalized) return Right.hasWhitespaceBefore(); + const bool IsVerilog = Style.isVerilog(); + assert(!IsVerilog || !IsCpp); + // Never ever merge two words. - if (Keywords.isWordLike(Right) && Keywords.isWordLike(Left)) + if (Keywords.isWordLike(Right, IsVerilog) && + Keywords.isWordLike(Left, IsVerilog)) { return true; + } // Leave a space between * and /* to avoid C4138 `comment end` found outside // of comment. @@ -5063,12 +5068,10 @@ bool TokenAnnotator::spaceRequiredBefore(const AnnotatedLine &Line, Right.is(TT_TemplateOpener)) { return true; } - } else if (Style.isVerilog()) { + } else if (IsVerilog) { // An escaped identifier ends with whitespace. - if (Style.isVerilog() && Left.is(tok::identifier) && - Left.TokenText[0] == '\\') { + if (Left.is(tok::identifier) && Left.TokenText[0] == '\\') return true; - } // Add space between things in a primitive's state table unless in a // transition like `(0?)`. if ((Left.is(TT_VerilogTableItem) && -- GitLab From aa596fa4d974f75ed8d2db3f4880ec0e5be3e176 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Sun, 28 Apr 2024 14:06:12 -0700 Subject: [PATCH 169/301] [clang-format] Set Change.TokenLength to ColumnWidth (#90378) Fixes #37705. Fixes #47333. Fixes #47624. Fixes #58850. Fixes #75929. Fixes #87885. Fixes #89916. --- clang/lib/Format/WhitespaceManager.cpp | 11 +++++--- clang/unittests/Format/FormatTest.cpp | 39 ++++++++++++++++++++++++++ 2 files changed, 46 insertions(+), 4 deletions(-) diff --git a/clang/lib/Format/WhitespaceManager.cpp b/clang/lib/Format/WhitespaceManager.cpp index cc9bcce6c414..44fd807ec27e 100644 --- a/clang/lib/Format/WhitespaceManager.cpp +++ b/clang/lib/Format/WhitespaceManager.cpp @@ -131,6 +131,7 @@ void WhitespaceManager::calculateLineBreakInformation() { for (unsigned I = 1, e = Changes.size(); I != e; ++I) { auto &C = Changes[I]; auto &P = Changes[I - 1]; + auto &PrevTokLength = P.TokenLength; SourceLocation OriginalWhitespaceStart = C.OriginalWhitespaceRange.getBegin(); SourceLocation PreviousOriginalWhitespaceEnd = @@ -169,21 +170,23 @@ void WhitespaceManager::calculateLineBreakInformation() { // line of the token. auto NewlinePos = Text.find_first_of('\n'); if (NewlinePos == StringRef::npos) { - P.TokenLength = OriginalWhitespaceStartOffset - + PrevTokLength = OriginalWhitespaceStartOffset - PreviousOriginalWhitespaceEndOffset + C.PreviousLinePostfix.size() + P.CurrentLinePrefix.size(); + if (!P.IsInsideToken) + PrevTokLength = std::min(PrevTokLength, P.Tok->ColumnWidth); } else { - P.TokenLength = NewlinePos + P.CurrentLinePrefix.size(); + PrevTokLength = NewlinePos + P.CurrentLinePrefix.size(); } // If there are multiple changes in this token, sum up all the changes until // the end of the line. if (P.IsInsideToken && P.NewlinesBefore == 0) - LastOutsideTokenChange->TokenLength += P.TokenLength + P.Spaces; + LastOutsideTokenChange->TokenLength += PrevTokLength + P.Spaces; else LastOutsideTokenChange = &P; - C.PreviousEndOfTokenColumn = P.StartOfTokenColumn + P.TokenLength; + C.PreviousEndOfTokenColumn = P.StartOfTokenColumn + PrevTokLength; P.IsTrailingComment = (C.NewlinesBefore > 0 || C.Tok->is(tok::eof) || diff --git a/clang/unittests/Format/FormatTest.cpp b/clang/unittests/Format/FormatTest.cpp index 8ecc1188a127..32ba6b6853c7 100644 --- a/clang/unittests/Format/FormatTest.cpp +++ b/clang/unittests/Format/FormatTest.cpp @@ -27363,6 +27363,45 @@ TEST_F(FormatTest, BreakAdjacentStringLiterals) { verifyFormat(Code, Style); } +TEST_F(FormatTest, AlignUTFCommentsAndStringLiterals) { + verifyFormat( + "int rus; // А теперь комментарии, например, на русском, 2-байта\n" + "int long_rus; // Верхний коммент еще не превысил границу в 80, однако\n" + " // уже отодвинут. Перенос, при этом, отрабатывает верно"); + + auto Style = getLLVMStyle(); + Style.ColumnLimit = 15; + verifyNoChange("#define test \\\n" + " /* 测试 */ \\\n" + " \"aa\" \\\n" + " \"bb\"", + Style); + + Style.ColumnLimit = 25; + verifyFormat("struct foo {\n" + " int iiiiii; ///< iiiiii\n" + " int b; ///< ыыы\n" + " int c; ///< ыыыы\n" + "};", + Style); + + Style.ColumnLimit = 35; + verifyFormat("#define SENSOR_DESC_1 \\\n" + " \"{\" \\\n" + " \"unit_of_measurement: \\\"°C\\\",\" \\\n" + " \"}\"", + Style); + + Style.ColumnLimit = 80; + Style.AlignArrayOfStructures = FormatStyle::AIAS_Left; + verifyFormat("Languages languages = {\n" + " Language{{'e', 'n'}, U\"Test English\" },\n" + " Language{{'l', 'v'}, U\"Test Latviešu\"},\n" + " Language{{'r', 'u'}, U\"Test Русский\" },\n" + "};", + Style); +} + } // namespace } // namespace test } // namespace format -- GitLab From 145176dc0c93566ce4aef721044d49ab8ba50f87 Mon Sep 17 00:00:00 2001 From: Jeremy Kun Date: Sun, 28 Apr 2024 14:58:44 -0700 Subject: [PATCH 170/301] polynomial: Add basic ops (#89525) Adds a few basic polynomial ops. - add, sub, mul - mul_scalar - leading_term, monomial_mul, monomial (useful for lowering `mul` to standard MLIR) - from_tensor, to_tensor, constant --------- Co-authored-by: Jeremy Kun Co-authored-by: Oleksandr "Alex" Zinenko --- .../mlir/Dialect/Polynomial/IR/Polynomial.h | 5 +- .../mlir/Dialect/Polynomial/IR/Polynomial.td | 296 +++++++++++++++++- .../Polynomial/IR/PolynomialDialect.cpp | 9 + .../Dialect/Polynomial/IR/PolynomialOps.cpp | 95 +++++- mlir/test/Dialect/Polynomial/ops.mlir | 82 +++++ mlir/test/Dialect/Polynomial/ops_errors.mlir | 53 ++++ mlir/test/Dialect/Polynomial/types.mlir | 14 + 7 files changed, 534 insertions(+), 20 deletions(-) create mode 100644 mlir/test/Dialect/Polynomial/ops.mlir create mode 100644 mlir/test/Dialect/Polynomial/ops_errors.mlir diff --git a/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.h b/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.h index 39b05b9d3ad1..3325a6fa3f9f 100644 --- a/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.h +++ b/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.h @@ -51,9 +51,6 @@ public: return (exponent.ult(other.exponent)); } - // Prints polynomial to 'os'. - void print(raw_ostream &os) const; - friend ::llvm::hash_code hash_value(const Monomial &arg); public: @@ -102,6 +99,8 @@ public: unsigned getDegree() const; + ArrayRef getTerms() const { return terms; } + friend ::llvm::hash_code hash_value(const Polynomial &arg); private: diff --git a/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.td b/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.td index 5d8da8399b01..d3e3ac55677f 100644 --- a/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.td +++ b/mlir/include/mlir/Dialect/Polynomial/IR/Polynomial.td @@ -35,18 +35,18 @@ def Polynomial_Dialect : Dialect { ```mlir // A constant polynomial in a ring with i32 coefficients and no polynomial modulus - #ring = #polynomial.ring + #ring = #polynomial.ring %a = polynomial.constant <1 + x**2 - 3x**3> : polynomial.polynomial<#ring> // A constant polynomial in a ring with i32 coefficients, modulo (x^1024 + 1) #modulus = #polynomial.polynomial<1 + x**1024> - #ring = #polynomial.ring + #ring = #polynomial.ring %a = polynomial.constant <1 + x**2 - 3x**3> : polynomial.polynomial<#ring> // A constant polynomial in a ring with i32 coefficients, with a polynomial // modulus of (x^1024 + 1) and a coefficient modulus of 17. #modulus = #polynomial.polynomial<1 + x**1024> - #ring = #polynomial.ring + #ring = #polynomial.ring %a = polynomial.constant <1 + x**2 - 3x**3> : polynomial.polynomial<#ring> ``` }]; @@ -63,7 +63,21 @@ class Polynomial_Attr traits = []> def Polynomial_PolynomialAttr : Polynomial_Attr<"Polynomial", "polynomial"> { let summary = "An attribute containing a single-variable polynomial."; let description = [{ - #poly = #polynomial.poly + A polynomial attribute represents a single-variable polynomial, which + is used to define the modulus of a `RingAttr`, as well as to define constants + and perform constant folding for `polynomial` ops. + + The polynomial must be expressed as a list of monomial terms, with addition + or subtraction between them. The choice of variable name is arbitrary, but + must be consistent across all the monomials used to define a single + attribute. The order of monomial terms is arbitrary, each monomial degree + must occur at most once. + + Example: + + ```mlir + #poly = #polynomial.polynomial + ``` }]; let parameters = (ins "Polynomial":$polynomial); let hasCustomAssemblyFormat = 1; @@ -79,10 +93,10 @@ def Polynomial_RingAttr : Polynomial_Attr<"Ring", "ring"> { integral, whose coefficients are taken modulo some statically known modulus (`coefficientModulus`). - Additionally, a polynomial ring can specify an _ideal_, which converts + Additionally, a polynomial ring can specify a _polynomialModulus_, which converts polynomial arithmetic to the analogue of modular integer arithmetic, where each polynomial is represented as its remainder when dividing by the - modulus. For single-variable polynomials, an "ideal" is always specificed + modulus. For single-variable polynomials, an "polynomialModulus" is always specificed via a single polynomial, which we call `polynomialModulus`. An expressive example is polynomials with i32 coefficients, whose @@ -122,32 +136,284 @@ class Polynomial_Type def Polynomial_PolynomialType : Polynomial_Type<"Polynomial", "polynomial"> { let summary = "An element of a polynomial ring."; - let description = [{ A type for polynomials in a polynomial quotient ring. }]; - let parameters = (ins Polynomial_RingAttr:$ring); let assemblyFormat = "`<` $ring `>`"; } +def PolynomialLike: TypeOrContainer; + class Polynomial_Op traits = []> : - Op; + Op { + let assemblyFormat = "operands attr-dict `:` functional-type(operands, results)"; +} class Polynomial_UnaryOp traits = []> : Polynomial_Op { let arguments = (ins Polynomial_PolynomialType:$operand); let results = (outs Polynomial_PolynomialType:$result); - - let assemblyFormat = "$operand attr-dict `:` qualified(type($result))"; } class Polynomial_BinaryOp traits = []> : - Polynomial_Op { - let arguments = (ins Polynomial_PolynomialType:$lhs, Polynomial_PolynomialType:$rhs); - let results = (outs Polynomial_PolynomialType:$result); + Polynomial_Op { + let arguments = (ins PolynomialLike:$lhs, PolynomialLike:$rhs); + let results = (outs PolynomialLike:$result); + let assemblyFormat = "operands attr-dict `:` type($result)"; +} + +def Polynomial_AddOp : Polynomial_BinaryOp<"add", [Commutative]> { + let summary = "Addition operation between polynomials."; + let description = [{ + Performs polynomial addition on the operands. The operands may be single + polynomials or containers of identically-typed polynomials, i.e., polynomials + from the same underlying ring with the same coefficient types. + + Addition is defined to occur in the ring defined by the ring attribute of + the two operands, meaning the addition is taken modulo the coefficientModulus + and the polynomialModulus of the ring. + + Example: + + ```mlir + // add two polynomials modulo x^1024 - 1 + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %0 = polynomial.constant #polynomial.polynomial<1 + x**2> : !polynomial.polynomial<#ring> + %1 = polynomial.constant #polynomial.polynomial : !polynomial.polynomial<#ring> + %2 = polynomial.add %0, %1 : !polynomial.polynomial<#ring> + ``` + }]; +} + +def Polynomial_SubOp : Polynomial_BinaryOp<"sub"> { + let summary = "Subtraction operation between polynomials."; + let description = [{ + Performs polynomial subtraction on the operands. The operands may be single + polynomials or containers of identically-typed polynomials, i.e., polynomials + from the same underlying ring with the same coefficient types. + + Subtraction is defined to occur in the ring defined by the ring attribute of + the two operands, meaning the subtraction is taken modulo the coefficientModulus + and the polynomialModulus of the ring. + + Example: - let assemblyFormat = "$lhs `,` $rhs attr-dict `:` qualified(type($result))"; + ```mlir + // subtract two polynomials modulo x^1024 - 1 + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %0 = polynomial.constant #polynomial.polynomial<1 + x**2> : !polynomial.polynomial<#ring> + %1 = polynomial.constant #polynomial.polynomial : !polynomial.polynomial<#ring> + %2 = polynomial.sub %0, %1 : !polynomial.polynomial<#ring> + ``` + }]; +} + +def Polynomial_MulOp : Polynomial_BinaryOp<"mul", [Commutative]> { + let summary = "Multiplication operation between polynomials."; + let description = [{ + Performs polynomial multiplication on the operands. The operands may be single + polynomials or containers of identically-typed polynomials, i.e., polynomials + from the same underlying ring with the same coefficient types. + + Multiplication is defined to occur in the ring defined by the ring attribute of + the two operands, meaning the multiplication is taken modulo the coefficientModulus + and the polynomialModulus of the ring. + + Example: + + ```mlir + // multiply two polynomials modulo x^1024 - 1 + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %0 = polynomial.constant #polynomial.polynomial<1 + x**2> : !polynomial.polynomial<#ring> + %1 = polynomial.constant #polynomial.polynomial : !polynomial.polynomial<#ring> + %2 = polynomial.mul %0, %1 : !polynomial.polynomial<#ring> + ``` + }]; +} + +def Polynomial_MulScalarOp : Polynomial_Op<"mul_scalar", [ + ElementwiseMappable, AllTypesMatch<["polynomial", "output"]>]> { + let summary = "Multiplication by a scalar of the field."; + let description = [{ + Multiplies the polynomial operand's coefficients by a given scalar value. + The operation is defined to occur in the ring defined by the ring attribute + of the two operands, meaning the multiplication is taken modulo the + coefficientModulus of the ring. + + The `scalar` input must have the same type as the polynomial ring's + coefficientType. + + Example: + + ```mlir + // multiply two polynomials modulo x^1024 - 1 + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %0 = polynomial.constant #polynomial.polynomial<1 + x**2> : !polynomial.polynomial<#ring> + %1 = arith.constant 3 : i32 + %2 = polynomial.mul_scalar %0, %1 : !polynomial.polynomial<#ring>, i32 + ``` + }]; + + let arguments = (ins + PolynomialLike:$polynomial, + AnyInteger:$scalar + ); + let results = (outs + PolynomialLike:$output + ); + let assemblyFormat = "operands attr-dict `:` type($polynomial) `,` type($scalar)"; + let hasVerifier = 1; +} + +def Polynomial_LeadingTermOp: Polynomial_Op<"leading_term"> { + let summary = "Compute the leading term of the polynomial."; + let description = [{ + The degree of a polynomial is the largest $k$ for which the coefficient + `a_k` of `x^k` is nonzero. The leading term is the term `a_k * x^k`, which + this op represents as a pair of results. The first is the degree `k` as an + index, and the second is the coefficient, whose type matches the + coefficient type of the polynomial's ring attribute. + + Example: + + ```mlir + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %0 = polynomial.constant #polynomial.polynomial<1 + x**2> : !polynomial.polynomial<#ring> + %1, %2 = polynomial.leading_term %0 : !polynomial.polynomial<#ring> -> (index, i32) + ``` + }]; + let arguments = (ins Polynomial_PolynomialType:$input); + let results = (outs Index:$degree, AnyInteger:$coefficient); + let assemblyFormat = "operands attr-dict `:` type($input) `->` `(` type($degree) `,` type($coefficient) `)`"; +} + +def Polynomial_MonomialOp: Polynomial_Op<"monomial"> { + let summary = "Create a polynomial that consists of a single monomial."; + let description = [{ + Construct a polynomial that consists of a single monomial term, from its + degree and coefficient as dynamic inputs. + + The coefficient type of the output polynomial's ring attribute must match + the `coefficient` input type. + + Example: + + ```mlir + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %deg = arith.constant 1023 : index + %five = arith.constant 5 : i32 + %0 = polynomial.monomial %five, %deg : (i32, index) -> !polynomial.polynomial<#ring> + ``` + }]; + let arguments = (ins AnyInteger:$coefficient, Index:$degree); + let results = (outs Polynomial_PolynomialType:$output); +} + +def Polynomial_MonicMonomialMulOp: Polynomial_Op<"monic_monomial_mul", [AllTypesMatch<["input", "output"]>]> { + let summary = "Multiply a polynomial by a monic monomial."; + let description = [{ + Multiply a polynomial by a monic monomial, meaning a polynomial of the form + `1 * x^k` for an index operand `k`. + + In some special rings of polynomials, such as a ring of polynomials + modulo `x^n - 1`, `monomial_mul` can be interpreted as a cyclic shift of + the coefficients of the polynomial. For some rings, this results in + optimized lowerings that involve rotations and rescaling of the + coefficients of the input. + }]; + let arguments = (ins PolynomialLike:$input, Index:$monomialDegree); + let results = (outs PolynomialLike:$output); +} + +def Polynomial_FromTensorOp : Polynomial_Op<"from_tensor", [Pure]> { + let summary = "Creates a polynomial from integer coefficients stored in a tensor."; + let description = [{ + `polynomial.from_tensor` creates a polynomial value from a tensor of coefficients. + The input tensor must list the coefficients in degree-increasing order. + + The input one-dimensional tensor may have size at most the degree of the + ring's polynomialModulus generator polynomial, with smaller dimension implying that + all higher-degree terms have coefficient zero. + + Example: + + ```mlir + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %two = arith.constant 2 : i32 + %five = arith.constant 5 : i32 + %coeffs = tensor.from_elements %two, %two, %five : tensor<3xi32> + %poly = polynomial.from_tensor %coeffs : tensor<3xi32> -> !polynomial.polynomial<#ring> + ``` + }]; + let arguments = (ins RankedTensorOf<[AnyInteger]>:$input); + let results = (outs Polynomial_PolynomialType:$output); + + let assemblyFormat = "$input attr-dict `:` type($input) `->` type($output)"; + + let builders = [ + // Builder that infers coefficient modulus from tensor bit width, + // and uses whatever input ring is provided by the caller. + OpBuilder<(ins "::mlir::Value":$input, "::mlir::polynomial::RingAttr":$ring)> + ]; + let hasVerifier = 1; +} + +def Polynomial_ToTensorOp : Polynomial_Op<"to_tensor", [Pure]> { + let summary = "Creates a tensor containing the coefficients of a polynomial."; + let description = [{ + `polynomial.to_tensor` creates a dense tensor value containing the + coefficients of the input polynomial. The output tensor contains the + coefficients in degree-increasing order. + + Operations that act on the coefficients of a polynomial, such as extracting + a specific coefficient or extracting a range of coefficients, should be + implemented by composing `to_tensor` with the relevant `tensor` dialect + ops. + + The output tensor has shape equal to the degree of the polynomial ring + attribute's polynomialModulus, including zeroes. + + Example: + + ```mlir + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %two = arith.constant 2 : i32 + %five = arith.constant 5 : i32 + %coeffs = tensor.from_elements %two, %two, %five : tensor<3xi32> + %poly = polynomial.from_tensor %coeffs : tensor<3xi32> -> !polynomial.polynomial<#ring> + %tensor = polynomial.to_tensor %poly : !polynomial.polynomial<#ring> -> tensor<1024xi32> + ``` + }]; + let arguments = (ins Polynomial_PolynomialType:$input); + let results = (outs RankedTensorOf<[AnyInteger]>:$output); + let assemblyFormat = "$input attr-dict `:` type($input) `->` type($output)"; + + let hasVerifier = 1; +} + +def Polynomial_ConstantOp : Polynomial_Op<"constant", [Pure]> { + let summary = "Define a constant polynomial via an attribute."; + let description = [{ + Example: + + ```mlir + #poly = #polynomial.polynomial + #ring = #polynomial.ring + %0 = polynomial.constant #polynomial.polynomial<1 + x**2> : !polynomial.polynomial<#ring> + ``` + }]; + let arguments = (ins Polynomial_PolynomialAttr:$input); + let results = (outs Polynomial_PolynomialType:$output); + let assemblyFormat = "$input attr-dict `:` type($output)"; } #endif // POLYNOMIAL_OPS diff --git a/mlir/lib/Dialect/Polynomial/IR/PolynomialDialect.cpp b/mlir/lib/Dialect/Polynomial/IR/PolynomialDialect.cpp index a672a59b8a46..825b80d70f80 100644 --- a/mlir/lib/Dialect/Polynomial/IR/PolynomialDialect.cpp +++ b/mlir/lib/Dialect/Polynomial/IR/PolynomialDialect.cpp @@ -8,9 +8,18 @@ #include "mlir/Dialect/Polynomial/IR/Polynomial.h" +#include "mlir/Dialect/Arith/IR/Arith.h" #include "mlir/Dialect/Polynomial/IR/PolynomialAttributes.h" #include "mlir/Dialect/Polynomial/IR/PolynomialOps.h" #include "mlir/Dialect/Polynomial/IR/PolynomialTypes.h" +#include "mlir/IR/Builders.h" +#include "mlir/IR/BuiltinOps.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/Dialect.h" +#include "mlir/IR/PatternMatch.h" +#include "mlir/Interfaces/InferTypeOpInterface.h" +#include "mlir/Support/LogicalResult.h" +#include "llvm/ADT/APInt.h" #include "llvm/ADT/TypeSwitch.h" using namespace mlir; diff --git a/mlir/lib/Dialect/Polynomial/IR/PolynomialOps.cpp b/mlir/lib/Dialect/Polynomial/IR/PolynomialOps.cpp index 96c59a28b8fd..8e2bb5f27dc6 100644 --- a/mlir/lib/Dialect/Polynomial/IR/PolynomialOps.cpp +++ b/mlir/lib/Dialect/Polynomial/IR/PolynomialOps.cpp @@ -6,10 +6,101 @@ // //===----------------------------------------------------------------------===// +#include "mlir/Dialect/Polynomial/IR/PolynomialOps.h" #include "mlir/Dialect/Polynomial/IR/Polynomial.h" +#include "mlir/Dialect/Polynomial/IR/PolynomialAttributes.h" +#include "mlir/Dialect/Polynomial/IR/PolynomialTypes.h" +#include "mlir/IR/Builders.h" +#include "mlir/IR/BuiltinTypes.h" +#include "mlir/IR/Dialect.h" +#include "mlir/Support/LogicalResult.h" +#include "llvm/ADT/APInt.h" using namespace mlir; using namespace mlir::polynomial; -#define GET_OP_CLASSES -#include "mlir/Dialect/Polynomial/IR/Polynomial.cpp.inc" +void FromTensorOp::build(OpBuilder &builder, OperationState &result, + Value input, RingAttr ring) { + TensorType tensorType = dyn_cast(input.getType()); + auto bitWidth = tensorType.getElementTypeBitWidth(); + APInt cmod(1 + bitWidth, 1); + cmod = cmod << bitWidth; + Type resultType = PolynomialType::get(builder.getContext(), ring); + build(builder, result, resultType, input); +} + +LogicalResult FromTensorOp::verify() { + ArrayRef tensorShape = getInput().getType().getShape(); + RingAttr ring = getOutput().getType().getRing(); + unsigned polyDegree = ring.getPolynomialModulus().getPolynomial().getDegree(); + bool compatible = tensorShape.size() == 1 && tensorShape[0] <= polyDegree; + if (!compatible) { + InFlightDiagnostic diag = emitOpError() + << "input type " << getInput().getType() + << " does not match output type " + << getOutput().getType(); + diag.attachNote() << "the input type must be a tensor of shape [d] where d " + "is at most the degree of the polynomialModulus of " + "the output type's ring attribute"; + return diag; + } + + APInt coefficientModulus = ring.getCoefficientModulus().getValue(); + unsigned cmodBitWidth = coefficientModulus.ceilLogBase2(); + unsigned inputBitWidth = getInput().getType().getElementTypeBitWidth(); + + if (inputBitWidth > cmodBitWidth) { + InFlightDiagnostic diag = emitOpError() + << "input tensor element type " + << getInput().getType().getElementType() + << " is too large to fit in the coefficients of " + << getOutput().getType(); + diag.attachNote() << "the input tensor's elements must be rescaled" + " to fit before using from_tensor"; + return diag; + } + + return success(); +} + +LogicalResult ToTensorOp::verify() { + ArrayRef tensorShape = getOutput().getType().getShape(); + unsigned polyDegree = getInput() + .getType() + .getRing() + .getPolynomialModulus() + .getPolynomial() + .getDegree(); + bool compatible = tensorShape.size() == 1 && tensorShape[0] == polyDegree; + + if (compatible) + return success(); + + InFlightDiagnostic diag = + emitOpError() << "input type " << getInput().getType() + << " does not match output type " << getOutput().getType(); + diag.attachNote() << "the output type must be a tensor of shape [d] where d " + "is at most the degree of the polynomialModulus of " + "the input type's ring attribute"; + return diag; +} + +LogicalResult MulScalarOp::verify() { + Type argType = getPolynomial().getType(); + PolynomialType polyType; + + if (auto shapedPolyType = dyn_cast(argType)) { + polyType = cast(shapedPolyType.getElementType()); + } else { + polyType = cast(argType); + } + + Type coefficientType = polyType.getRing().getCoefficientType(); + + if (coefficientType != getScalar().getType()) + return emitOpError() << "polynomial coefficient type " << coefficientType + << " does not match scalar type " + << getScalar().getType(); + + return success(); +} diff --git a/mlir/test/Dialect/Polynomial/ops.mlir b/mlir/test/Dialect/Polynomial/ops.mlir new file mode 100644 index 000000000000..ea1b279fa1ff --- /dev/null +++ b/mlir/test/Dialect/Polynomial/ops.mlir @@ -0,0 +1,82 @@ +// RUN: mlir-opt %s | FileCheck %s + +// This simply tests for syntax. + +#my_poly = #polynomial.polynomial<1 + x**1024> +#my_poly_2 = #polynomial.polynomial<2> +#my_poly_3 = #polynomial.polynomial<3x> +#my_poly_4 = #polynomial.polynomial +#ring1 = #polynomial.ring +#one_plus_x_squared = #polynomial.polynomial<1 + x**2> + +#ideal = #polynomial.polynomial<-1 + x**1024> +#ring = #polynomial.ring +!poly_ty = !polynomial.polynomial<#ring> + +module { + func.func @test_multiply() -> !polynomial.polynomial<#ring1> { + %c0 = arith.constant 0 : index + %two = arith.constant 2 : i16 + %five = arith.constant 5 : i16 + %coeffs1 = tensor.from_elements %two, %two, %five : tensor<3xi16> + %coeffs2 = tensor.from_elements %five, %five, %two : tensor<3xi16> + + %poly1 = polynomial.from_tensor %coeffs1 : tensor<3xi16> -> !polynomial.polynomial<#ring1> + %poly2 = polynomial.from_tensor %coeffs2 : tensor<3xi16> -> !polynomial.polynomial<#ring1> + + %3 = polynomial.mul %poly1, %poly2 : !polynomial.polynomial<#ring1> + + return %3 : !polynomial.polynomial<#ring1> + } + + func.func @test_elementwise(%p0 : !polynomial.polynomial<#ring1>, %p1: !polynomial.polynomial<#ring1>) { + %tp0 = tensor.from_elements %p0, %p1 : tensor<2x!polynomial.polynomial<#ring1>> + %tp1 = tensor.from_elements %p1, %p0 : tensor<2x!polynomial.polynomial<#ring1>> + + %c = arith.constant 2 : i32 + %mul_const_sclr = polynomial.mul_scalar %tp0, %c : tensor<2x!polynomial.polynomial<#ring1>>, i32 + + %add = polynomial.add %tp0, %tp1 : tensor<2x!polynomial.polynomial<#ring1>> + %sub = polynomial.sub %tp0, %tp1 : tensor<2x!polynomial.polynomial<#ring1>> + %mul = polynomial.mul %tp0, %tp1 : tensor<2x!polynomial.polynomial<#ring1>> + + return + } + + func.func @test_to_from_tensor(%p0 : !polynomial.polynomial<#ring1>) { + %c0 = arith.constant 0 : index + %two = arith.constant 2 : i16 + %coeffs1 = tensor.from_elements %two, %two : tensor<2xi16> + // CHECK: from_tensor + %poly = polynomial.from_tensor %coeffs1 : tensor<2xi16> -> !polynomial.polynomial<#ring1> + // CHECK: to_tensor + %tensor = polynomial.to_tensor %poly : !polynomial.polynomial<#ring1> -> tensor<1024xi16> + + return + } + + func.func @test_degree(%p0 : !polynomial.polynomial<#ring1>) { + %0, %1 = polynomial.leading_term %p0 : !polynomial.polynomial<#ring1> -> (index, i32) + return + } + + func.func @test_monomial() { + %deg = arith.constant 1023 : index + %five = arith.constant 5 : i16 + %0 = polynomial.monomial %five, %deg : (i16, index) -> !polynomial.polynomial<#ring1> + return + } + + func.func @test_monic_monomial_mul() { + %five = arith.constant 5 : index + %0 = polynomial.constant #one_plus_x_squared : !polynomial.polynomial<#ring1> + %1 = polynomial.monic_monomial_mul %0, %five : (!polynomial.polynomial<#ring1>, index) -> !polynomial.polynomial<#ring1> + return + } + + func.func @test_constant() { + %0 = polynomial.constant #one_plus_x_squared : !polynomial.polynomial<#ring1> + %1 = polynomial.constant <1 + x**2> : !polynomial.polynomial<#ring1> + return + } +} diff --git a/mlir/test/Dialect/Polynomial/ops_errors.mlir b/mlir/test/Dialect/Polynomial/ops_errors.mlir new file mode 100644 index 000000000000..c34a7de30e5f --- /dev/null +++ b/mlir/test/Dialect/Polynomial/ops_errors.mlir @@ -0,0 +1,53 @@ +// RUN: mlir-opt --split-input-file --verify-diagnostics %s + +#my_poly = #polynomial.polynomial<1 + x**1024> +#ring = #polynomial.ring +!ty = !polynomial.polynomial<#ring> + +func.func @test_from_tensor_too_large_coeffs() { + %two = arith.constant 2 : i32 + %coeffs1 = tensor.from_elements %two, %two : tensor<2xi32> + // expected-error@below {{is too large to fit in the coefficients}} + // expected-note@below {{rescaled to fit}} + %poly = polynomial.from_tensor %coeffs1 : tensor<2xi32> -> !ty + return +} + +// ----- + +#my_poly = #polynomial.polynomial<1 + x**4> +#ring = #polynomial.ring +!ty = !polynomial.polynomial<#ring> +func.func @test_from_tensor_wrong_tensor_type() { + %two = arith.constant 2 : i32 + %coeffs1 = tensor.from_elements %two, %two, %two, %two, %two : tensor<5xi32> + // expected-error@below {{input type 'tensor<5xi32>' does not match output type '!polynomial.polynomial<#polynomial.ring>>'}} + // expected-note@below {{at most the degree of the polynomialModulus of the output type's ring attribute}} + %poly = polynomial.from_tensor %coeffs1 : tensor<5xi32> -> !ty + return +} + +// ----- + +#my_poly = #polynomial.polynomial<1 + x**4> +#ring = #polynomial.ring +!ty = !polynomial.polynomial<#ring> +func.func @test_to_tensor_wrong_output_tensor_type(%arg0 : !ty) { + // expected-error@below {{input type '!polynomial.polynomial<#polynomial.ring>>' does not match output type 'tensor<5xi32>'}} + // expected-note@below {{at most the degree of the polynomialModulus of the input type's ring attribute}} + %tensor = polynomial.to_tensor %arg0 : !ty -> tensor<5xi32> + return +} + +// ----- + +#my_poly = #polynomial.polynomial<1 + x**1024> +#ring = #polynomial.ring +!ty = !polynomial.polynomial<#ring> + +func.func @test_mul_scalar_wrong_type(%arg0: !ty) -> !ty { + %scalar = arith.constant 2 : i32 // should be i16 + // expected-error@below {{polynomial coefficient type 'i16' does not match scalar type 'i32'}} + %poly = polynomial.mul_scalar %arg0, %scalar : !ty, i32 + return %poly : !ty +} diff --git a/mlir/test/Dialect/Polynomial/types.mlir b/mlir/test/Dialect/Polynomial/types.mlir index 64b74d9d36bb..00296a36e890 100644 --- a/mlir/test/Dialect/Polynomial/types.mlir +++ b/mlir/test/Dialect/Polynomial/types.mlir @@ -40,3 +40,17 @@ func.func @test_non_x_variable_64_bit(%0: !ty2) -> !ty2 { func.func @test_linear_poly(%0: !ty3) -> !ty3 { return %0 : !ty3 } + +// CHECK-LABEL: func @test_negative_leading_1 +// CHECK-SAME: !polynomial.polynomial< +// CHECK-SAME: #polynomial.ring< +// CHECK-SAME: coefficientType=i32, +// CHECK-SAME: coefficientModulus=2837465 : i32, +// CHECK-SAME: polynomialModulus=#polynomial.polynomial<-1 + x**1024>>> +#my_poly_4 = #polynomial.polynomial<-1 + x**1024> +#ring4 = #polynomial.ring +!ty4 = !polynomial.polynomial<#ring4> +func.func @test_negative_leading_1(%0: !ty4) -> !ty4 { + return %0 : !ty4 +} + -- GitLab From 35b89dda2b9734917824b1457f149192669b314c Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 29 Apr 2024 08:40:26 +0800 Subject: [PATCH 171/301] [X86][EVEX512] Check hasEVEX512 for canExtendTo512DQ (#90390) Fixes #90356 --- llvm/lib/Target/X86/X86Subtarget.h | 3 +- llvm/test/CodeGen/X86/avx512bwvl-arith.ll | 35 +++++++++++++++++++++-- 2 files changed, 35 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Target/X86/X86Subtarget.h b/llvm/lib/Target/X86/X86Subtarget.h index a458b5f9ec8f..4d55a084b730 100644 --- a/llvm/lib/Target/X86/X86Subtarget.h +++ b/llvm/lib/Target/X86/X86Subtarget.h @@ -244,7 +244,8 @@ public: // TODO: Currently we're always allowing widening on CPUs without VLX, // because for many cases we don't have a better option. bool canExtendTo512DQ() const { - return hasAVX512() && (!hasVLX() || getPreferVectorWidth() >= 512); + return hasAVX512() && hasEVEX512() && + (!hasVLX() || getPreferVectorWidth() >= 512); } bool canExtendTo512BW() const { return hasBWI() && canExtendTo512DQ(); diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll index 4988fc35b10e..fdc25f44b156 100644 --- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll +++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,-evex512 | FileCheck %s +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,EVEX256 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,-evex512 | FileCheck %s --check-prefixes=CHECK,EVEX512 ; 256-bit @@ -236,3 +236,34 @@ define <8 x i16> @vpmullw128_test(<8 x i16> %i, <8 x i16> %j) { ret <8 x i16> %x } +define i16 @PR90356(<16 x i1> %a) { +; EVEX256-LABEL: PR90356: +; EVEX256: # %bb.0: +; EVEX256-NEXT: vpsllw $7, %xmm0, %xmm0 +; EVEX256-NEXT: vpmovb2m %xmm0, %k1 +; EVEX256-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; EVEX256-NEXT: movb $63, %al +; EVEX256-NEXT: kmovd %eax, %k1 +; EVEX256-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} +; EVEX256-NEXT: vptestmd %zmm0, %zmm0, %k0 +; EVEX256-NEXT: kmovd %k0, %eax +; EVEX256-NEXT: # kill: def $ax killed $ax killed $eax +; EVEX256-NEXT: vzeroupper +; EVEX256-NEXT: retq +; +; EVEX512-LABEL: PR90356: +; EVEX512: # %bb.0: +; EVEX512-NEXT: vpsllw $7, %xmm0, %xmm0 +; EVEX512-NEXT: vpmovb2m %xmm0, %k0 +; EVEX512-NEXT: vpmovm2w %k0, %ymm0 +; EVEX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; EVEX512-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; EVEX512-NEXT: vpmovw2m %ymm0, %k0 +; EVEX512-NEXT: kmovd %k0, %eax +; EVEX512-NEXT: # kill: def $ax killed $ax killed $eax +; EVEX512-NEXT: vzeroupper +; EVEX512-NEXT: retq + %1 = shufflevector <16 x i1> %a, <16 x i1> zeroinitializer, <16 x i32> + %2 = bitcast <16 x i1> %1 to i16 + ret i16 %2 +} -- GitLab From feaddc10194e54a5ef977320134956ad91591324 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 29 Apr 2024 09:44:45 +0900 Subject: [PATCH 172/301] [InstCombine] Preserve inbounds when canonicalizing gep+add (#90160) When canonicalizing gep+add into gep+gep we can preserve inbounds if the add is also nsw and both add operands are non-negative (or both negative, but I don't think that's practically relevant). Proof: https://alive2.llvm.org/ce/z/tJLBta --- .../InstCombine/InstructionCombining.cpp | 34 ++++++++++++++----- llvm/test/Transforms/InstCombine/array.ll | 8 ++--- 2 files changed, 30 insertions(+), 12 deletions(-) diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index 58b2d8e9dec1..0858116cd911 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -2948,6 +2948,14 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) { return nullptr; if (GEP.getNumIndices() == 1) { + // We can only preserve inbounds if the original gep is inbounds, the add + // is nsw, and the add operands are non-negative. + auto CanPreserveInBounds = [&](bool AddIsNSW, Value *Idx1, Value *Idx2) { + SimplifyQuery Q = SQ.getWithInstruction(&GEP); + return GEP.isInBounds() && AddIsNSW && isKnownNonNegative(Idx1, Q) && + isKnownNonNegative(Idx2, Q); + }; + // Try to replace ADD + GEP with GEP + GEP. Value *Idx1, *Idx2; if (match(GEP.getOperand(1), @@ -2957,10 +2965,15 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) { // as: // %newptr = getelementptr i32, ptr %ptr, i64 %idx1 // %newgep = getelementptr i32, ptr %newptr, i64 %idx2 - auto *NewPtr = Builder.CreateGEP(GEP.getResultElementType(), - GEP.getPointerOperand(), Idx1); - return GetElementPtrInst::Create(GEP.getResultElementType(), NewPtr, - Idx2); + bool IsInBounds = CanPreserveInBounds( + cast(GEP.getOperand(1))->hasNoSignedWrap(), + Idx1, Idx2); + auto *NewPtr = + Builder.CreateGEP(GEP.getResultElementType(), GEP.getPointerOperand(), + Idx1, "", IsInBounds); + return replaceInstUsesWith( + GEP, Builder.CreateGEP(GEP.getResultElementType(), NewPtr, Idx2, "", + IsInBounds)); } ConstantInt *C; if (match(GEP.getOperand(1), m_OneUse(m_SExtLike(m_OneUse(m_NSWAdd( @@ -2971,12 +2984,17 @@ Instruction *InstCombinerImpl::visitGetElementPtrInst(GetElementPtrInst &GEP) { // as: // %newptr = getelementptr i32, ptr %ptr, i32 %idx1 // %newgep = getelementptr i32, ptr %newptr, i32 idx2 + bool IsInBounds = CanPreserveInBounds( + /*IsNSW=*/true, Idx1, C); auto *NewPtr = Builder.CreateGEP( GEP.getResultElementType(), GEP.getPointerOperand(), - Builder.CreateSExt(Idx1, GEP.getOperand(1)->getType())); - return GetElementPtrInst::Create( - GEP.getResultElementType(), NewPtr, - Builder.CreateSExt(C, GEP.getOperand(1)->getType())); + Builder.CreateSExt(Idx1, GEP.getOperand(1)->getType()), "", + IsInBounds); + return replaceInstUsesWith( + GEP, + Builder.CreateGEP(GEP.getResultElementType(), NewPtr, + Builder.CreateSExt(C, GEP.getOperand(1)->getType()), + "", IsInBounds)); } } diff --git a/llvm/test/Transforms/InstCombine/array.ll b/llvm/test/Transforms/InstCombine/array.ll index f439d4da6080..4f4ae17bebc5 100644 --- a/llvm/test/Transforms/InstCombine/array.ll +++ b/llvm/test/Transforms/InstCombine/array.ll @@ -116,8 +116,8 @@ define ptr @gep_inbounds_add_nsw_nonneg(ptr %ptr, i64 %a, i64 %b) { ; CHECK-NEXT: call void @llvm.assume(i1 [[A_NNEG]]) ; CHECK-NEXT: [[B_NNEG:%.*]] = icmp sgt i64 [[B]], -1 ; CHECK-NEXT: call void @llvm.assume(i1 [[B_NNEG]]) -; CHECK-NEXT: [[TMP1:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[A]] -; CHECK-NEXT: [[GEP:%.*]] = getelementptr i32, ptr [[TMP1]], i64 [[B]] +; CHECK-NEXT: [[TMP1:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i64 [[A]] +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i32, ptr [[TMP1]], i64 [[B]] ; CHECK-NEXT: ret ptr [[GEP]] ; %a.nneg = icmp sgt i64 %a, -1 @@ -207,8 +207,8 @@ define ptr @gep_inbounds_sext_add_nonneg(ptr %ptr, i32 %a) { ; CHECK-NEXT: [[A_NNEG:%.*]] = icmp sgt i32 [[A]], -1 ; CHECK-NEXT: call void @llvm.assume(i1 [[A_NNEG]]) ; CHECK-NEXT: [[TMP1:%.*]] = zext nneg i32 [[A]] to i64 -; CHECK-NEXT: [[TMP2:%.*]] = getelementptr i32, ptr [[PTR]], i64 [[TMP1]] -; CHECK-NEXT: [[GEP:%.*]] = getelementptr i8, ptr [[TMP2]], i64 40 +; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[PTR]], i64 [[TMP1]] +; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i8, ptr [[TMP2]], i64 40 ; CHECK-NEXT: ret ptr [[GEP]] ; %a.nneg = icmp sgt i32 %a, -1 -- GitLab From 3c553fc9e0503240c9fa6d937de0cbcb956303ce Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 29 Apr 2024 09:53:09 +0900 Subject: [PATCH 173/301] [InstCombine] Infer nuw on mul nsw with non-negative operands (#90170) If a mul nsw has non-negative operands, it's also nuw. Proof: https://alive2.llvm.org/ce/z/2Dz9Uu Fixes https://github.com/llvm/llvm-project/issues/90020. --- llvm/include/llvm/Analysis/ValueTracking.h | 3 ++- llvm/include/llvm/Transforms/InstCombine/InstCombiner.h | 7 ++++--- llvm/lib/Analysis/ValueTracking.cpp | 8 +++++++- llvm/lib/Transforms/InstCombine/InstCombineInternal.h | 5 +++-- llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp | 2 +- llvm/test/Transforms/InstCombine/mul.ll | 2 +- 6 files changed, 18 insertions(+), 9 deletions(-) diff --git a/llvm/include/llvm/Analysis/ValueTracking.h b/llvm/include/llvm/Analysis/ValueTracking.h index 571e44cdac26..afd18e7e56ba 100644 --- a/llvm/include/llvm/Analysis/ValueTracking.h +++ b/llvm/include/llvm/Analysis/ValueTracking.h @@ -860,7 +860,8 @@ enum class OverflowResult { }; OverflowResult computeOverflowForUnsignedMul(const Value *LHS, const Value *RHS, - const SimplifyQuery &SQ); + const SimplifyQuery &SQ, + bool IsNSW = false); OverflowResult computeOverflowForSignedMul(const Value *LHS, const Value *RHS, const SimplifyQuery &SQ); OverflowResult diff --git a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h index ea1f4fc3b85d..855d1aeddfae 100644 --- a/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h +++ b/llvm/include/llvm/Transforms/InstCombine/InstCombiner.h @@ -461,9 +461,10 @@ public: OverflowResult computeOverflowForUnsignedMul(const Value *LHS, const Value *RHS, - const Instruction *CxtI) const { - return llvm::computeOverflowForUnsignedMul(LHS, RHS, - SQ.getWithInstruction(CxtI)); + const Instruction *CxtI, + bool IsNSW = false) const { + return llvm::computeOverflowForUnsignedMul( + LHS, RHS, SQ.getWithInstruction(CxtI), IsNSW); } OverflowResult computeOverflowForSignedMul(const Value *LHS, const Value *RHS, diff --git a/llvm/lib/Analysis/ValueTracking.cpp b/llvm/lib/Analysis/ValueTracking.cpp index de38eddaa98f..1b461e7cfd01 100644 --- a/llvm/lib/Analysis/ValueTracking.cpp +++ b/llvm/lib/Analysis/ValueTracking.cpp @@ -6686,9 +6686,15 @@ llvm::computeConstantRangeIncludingKnownBits(const WithCache &V, OverflowResult llvm::computeOverflowForUnsignedMul(const Value *LHS, const Value *RHS, - const SimplifyQuery &SQ) { + const SimplifyQuery &SQ, + bool IsNSW) { KnownBits LHSKnown = computeKnownBits(LHS, /*Depth=*/0, SQ); KnownBits RHSKnown = computeKnownBits(RHS, /*Depth=*/0, SQ); + + // mul nsw of two non-negative numbers is also nuw. + if (IsNSW && LHSKnown.isNonNegative() && RHSKnown.isNonNegative()) + return OverflowResult::NeverOverflows; + ConstantRange LHSRange = ConstantRange::fromKnownBits(LHSKnown, false); ConstantRange RHSRange = ConstantRange::fromKnownBits(RHSKnown, false); return mapOverflowResult(LHSRange.unsignedMulMayOverflow(RHSRange)); diff --git a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h index aafb4cf6ca6a..db7838bbe3c2 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineInternal.h +++ b/llvm/lib/Transforms/InstCombine/InstCombineInternal.h @@ -354,8 +354,9 @@ private: } bool willNotOverflowUnsignedMul(const Value *LHS, const Value *RHS, - const Instruction &CxtI) const { - return computeOverflowForUnsignedMul(LHS, RHS, &CxtI) == + const Instruction &CxtI, + bool IsNSW = false) const { + return computeOverflowForUnsignedMul(LHS, RHS, &CxtI, IsNSW) == OverflowResult::NeverOverflows; } diff --git a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp index 4ed4c36e21e0..ca1b1921404d 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineMulDivRem.cpp @@ -530,7 +530,7 @@ Instruction *InstCombinerImpl::visitMul(BinaryOperator &I) { I.setHasNoSignedWrap(true); } - if (!HasNUW && willNotOverflowUnsignedMul(Op0, Op1, I)) { + if (!HasNUW && willNotOverflowUnsignedMul(Op0, Op1, I, I.hasNoSignedWrap())) { Changed = true; I.setHasNoUnsignedWrap(true); } diff --git a/llvm/test/Transforms/InstCombine/mul.ll b/llvm/test/Transforms/InstCombine/mul.ll index 4c1ce10171dd..4fb3c0b1ad49 100644 --- a/llvm/test/Transforms/InstCombine/mul.ll +++ b/llvm/test/Transforms/InstCombine/mul.ll @@ -2146,7 +2146,7 @@ define i8 @mul_nsw_nonneg(i8 %x, i8 %y) { ; CHECK-NEXT: call void @llvm.assume(i1 [[X_NNEG]]) ; CHECK-NEXT: [[Y_NNEG:%.*]] = icmp sgt i8 [[Y:%.*]], -1 ; CHECK-NEXT: call void @llvm.assume(i1 [[Y_NNEG]]) -; CHECK-NEXT: [[MUL:%.*]] = mul nsw i8 [[X]], [[Y]] +; CHECK-NEXT: [[MUL:%.*]] = mul nuw nsw i8 [[X]], [[Y]] ; CHECK-NEXT: ret i8 [[MUL]] ; %x.nneg = icmp sge i8 %x, 0 -- GitLab From 2951dba98beb97a73da3443dcdb2eb09069e1aca Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Mon, 29 Apr 2024 09:00:45 +0800 Subject: [PATCH 174/301] [X86] Fix prefix type, NFC --- llvm/test/CodeGen/X86/avx512bwvl-arith.ll | 42 +++++++++++------------ 1 file changed, 21 insertions(+), 21 deletions(-) diff --git a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll index fdc25f44b156..33819c9e0102 100644 --- a/llvm/test/CodeGen/X86/avx512bwvl-arith.ll +++ b/llvm/test/CodeGen/X86/avx512bwvl-arith.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,EVEX256 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,-evex512 | FileCheck %s --check-prefixes=CHECK,EVEX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl | FileCheck %s --check-prefixes=CHECK,EVEX512 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+avx512bw,+avx512vl,-evex512 | FileCheck %s --check-prefixes=CHECK,EVEX256 ; 256-bit @@ -237,32 +237,32 @@ define <8 x i16> @vpmullw128_test(<8 x i16> %i, <8 x i16> %j) { } define i16 @PR90356(<16 x i1> %a) { -; EVEX256-LABEL: PR90356: -; EVEX256: # %bb.0: -; EVEX256-NEXT: vpsllw $7, %xmm0, %xmm0 -; EVEX256-NEXT: vpmovb2m %xmm0, %k1 -; EVEX256-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} -; EVEX256-NEXT: movb $63, %al -; EVEX256-NEXT: kmovd %eax, %k1 -; EVEX256-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} -; EVEX256-NEXT: vptestmd %zmm0, %zmm0, %k0 -; EVEX256-NEXT: kmovd %k0, %eax -; EVEX256-NEXT: # kill: def $ax killed $ax killed $eax -; EVEX256-NEXT: vzeroupper -; EVEX256-NEXT: retq -; ; EVEX512-LABEL: PR90356: ; EVEX512: # %bb.0: ; EVEX512-NEXT: vpsllw $7, %xmm0, %xmm0 -; EVEX512-NEXT: vpmovb2m %xmm0, %k0 -; EVEX512-NEXT: vpmovm2w %k0, %ymm0 -; EVEX512-NEXT: vpxor %xmm1, %xmm1, %xmm1 -; EVEX512-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] -; EVEX512-NEXT: vpmovw2m %ymm0, %k0 +; EVEX512-NEXT: vpmovb2m %xmm0, %k1 +; EVEX512-NEXT: vpternlogd $255, %zmm0, %zmm0, %zmm0 {%k1} {z} +; EVEX512-NEXT: movb $63, %al +; EVEX512-NEXT: kmovd %eax, %k1 +; EVEX512-NEXT: vpexpandq %zmm0, %zmm0 {%k1} {z} +; EVEX512-NEXT: vptestmd %zmm0, %zmm0, %k0 ; EVEX512-NEXT: kmovd %k0, %eax ; EVEX512-NEXT: # kill: def $ax killed $ax killed $eax ; EVEX512-NEXT: vzeroupper ; EVEX512-NEXT: retq +; +; EVEX256-LABEL: PR90356: +; EVEX256: # %bb.0: +; EVEX256-NEXT: vpsllw $7, %xmm0, %xmm0 +; EVEX256-NEXT: vpmovb2m %xmm0, %k0 +; EVEX256-NEXT: vpmovm2w %k0, %ymm0 +; EVEX256-NEXT: vpxor %xmm1, %xmm1, %xmm1 +; EVEX256-NEXT: vpblendd {{.*#+}} ymm0 = ymm0[0,1,2,3,4,5],ymm1[6,7] +; EVEX256-NEXT: vpmovw2m %ymm0, %k0 +; EVEX256-NEXT: kmovd %k0, %eax +; EVEX256-NEXT: # kill: def $ax killed $ax killed $eax +; EVEX256-NEXT: vzeroupper +; EVEX256-NEXT: retq %1 = shufflevector <16 x i1> %a, <16 x i1> zeroinitializer, <16 x i32> %2 = bitcast <16 x i1> %1 to i16 ret i16 %2 -- GitLab From da213d77c026ded4e13911959c4a6ff24a6a0d73 Mon Sep 17 00:00:00 2001 From: Jie Fu Date: Mon, 29 Apr 2024 09:39:55 +0800 Subject: [PATCH 175/301] [MLIR] Fix linking error of PolynomialDialect on MacOS (NFC) ld64.lld: error: undefined symbol: mlir::detail::verifyInferredResultTypes(mlir::Operation*) >>> referenced by tools/mlir/lib/Dialect/Polynomial/IR/CMakeFiles/obj.MLIRPolynomialDialect.dir/PolynomialDialect.cpp.o:(symbol mlir::Op::Impl, mlir::OpTrait::ZeroSuccessors, mlir::OpTrait::NOperands<2u>::Impl, mlir::OpTrait::OpInvariants, mlir::OpTrait::IsCommutative, mlir::ConditionallySpeculatable::Trait, mlir::OpTrait::AlwaysSpeculatableImplTrait, mlir::MemoryEffectOpInterface::Trait, mlir::OpTrait::SameOperandsAndResultType, mlir::OpTrait::Elementwise, mlir::OpTrait::Scalarizable, mlir::OpTrait::Vectorizable, mlir::OpTrait::Tensorizable, mlir::InferTypeOpInterface::Trait>::verifyRegionInvariants(mlir::Operation*)+0x14) >>> referenced by tools/mlir/lib/Dialect/Polynomial/IR/CMakeFiles/obj.MLIRPolynomialDialect.dir/PolynomialDialect.cpp.o:(symbol mlir::Op::Impl, mlir::OpTrait::ZeroSuccessors, mlir::OpTrait::NOperands<2u>::Impl, mlir::OpTrait::OpInvariants, mlir::ConditionallySpeculatable::Trait, mlir::OpTrait::AlwaysSpeculatableImplTrait, mlir::MemoryEffectOpInterface::Trait, mlir::InferTypeOpInterface::Trait>::verifyRegionInvariants(mlir::Operation*)+0x14) --- mlir/lib/Dialect/Polynomial/IR/CMakeLists.txt | 1 + 1 file changed, 1 insertion(+) diff --git a/mlir/lib/Dialect/Polynomial/IR/CMakeLists.txt b/mlir/lib/Dialect/Polynomial/IR/CMakeLists.txt index 7f5b3255d5d9..d6e703b8b359 100644 --- a/mlir/lib/Dialect/Polynomial/IR/CMakeLists.txt +++ b/mlir/lib/Dialect/Polynomial/IR/CMakeLists.txt @@ -16,4 +16,5 @@ add_mlir_dialect_library(MLIRPolynomialDialect MLIRSupport MLIRDialect MLIRIR + MLIRInferTypeOpInterface ) -- GitLab From 42bc4f692dfe699b90f4609b7ad7c6708cf3fc43 Mon Sep 17 00:00:00 2001 From: Phoebe Wang Date: Wed, 24 Apr 2024 15:11:41 +0800 Subject: [PATCH 176/301] Reland "[X86] X86LowerTileCopy: Find dead register to use to prevent save-reload of tile register (#83628)" Fixes compile time regression in previous commit. --- llvm/lib/Target/X86/X86LowerTileCopy.cpp | 73 ++++++++++++++----- .../CodeGen/X86/AMX/amx-lower-tile-copy.ll | 10 --- 2 files changed, 54 insertions(+), 29 deletions(-) diff --git a/llvm/lib/Target/X86/X86LowerTileCopy.cpp b/llvm/lib/Target/X86/X86LowerTileCopy.cpp index e7afc49240e5..fd05e16ac1ce 100644 --- a/llvm/lib/Target/X86/X86LowerTileCopy.cpp +++ b/llvm/lib/Target/X86/X86LowerTileCopy.cpp @@ -20,6 +20,7 @@ #include "X86InstrBuilder.h" #include "X86InstrInfo.h" #include "X86Subtarget.h" +#include "llvm/CodeGen/LiveRegUnits.h" #include "llvm/CodeGen/MachineBasicBlock.h" #include "llvm/CodeGen/MachineFrameInfo.h" #include "llvm/CodeGen/MachineFunction.h" @@ -72,10 +73,28 @@ FunctionPass *llvm::createX86LowerTileCopyPass() { bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) { const X86Subtarget &ST = MF.getSubtarget(); const X86InstrInfo *TII = ST.getInstrInfo(); + const TargetRegisterInfo *TRI = ST.getRegisterInfo(); + BitVector GR64Regs = + TRI->getAllocatableSet(MF, TRI->getRegClass(X86::GR64RegClassID)); + BitVector TILERegs = + TRI->getAllocatableSet(MF, TRI->getRegClass(X86::TILERegClassID)); bool Changed = false; for (MachineBasicBlock &MBB : MF) { - for (MachineInstr &MI : llvm::make_early_inc_range(MBB)) { + // There won't be a tile copy if no tile register live in. + bool HasTileCopy = false; + for (const auto &LI : MBB.liveins()) { + if (TILERegs.test(LI.PhysReg)) { + HasTileCopy = true; + break; + } + } + if (!HasTileCopy) + continue; + LiveRegUnits UsedRegs(*TRI); + UsedRegs.addLiveOuts(MBB); + for (MachineInstr &MI : llvm::make_early_inc_range(reverse(MBB))) { + UsedRegs.stepBackward(MI); if (!MI.isCopy()) continue; MachineOperand &DstMO = MI.getOperand(0); @@ -85,27 +104,41 @@ bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) { if (!X86::TILERegClass.contains(DstReg, SrcReg)) continue; - const TargetRegisterInfo *TRI = ST.getRegisterInfo(); // Allocate stack slot for tile register unsigned Size = TRI->getSpillSize(X86::TILERegClass); Align Alignment = TRI->getSpillAlign(X86::TILERegClass); int TileSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment); - // Allocate stack slot for stride register - Size = TRI->getSpillSize(X86::GR64RegClass); - Alignment = TRI->getSpillAlign(X86::GR64RegClass); - int StrideSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment); - // TODO: Pick a killed regiter to avoid save/reload. There is problem - // to get live interval in this stage. - Register GR64Cand = X86::RAX; + int StrideSS = 0; + + // Pick a killed register to avoid a save/reload. + Register GR64Cand = X86::NoRegister; + for (auto RegT : GR64Regs.set_bits()) { + if (UsedRegs.available(RegT)) { + GR64Cand = RegT; + break; + } + } const DebugLoc &DL = MI.getDebugLoc(); - // mov %rax (%sp) - BuildMI(MBB, MI, DL, TII->get(X86::IMPLICIT_DEF), GR64Cand); - addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), StrideSS) - .addReg(GR64Cand); - // mov 64 %rax - BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64); + if (GR64Cand) { + // mov 64 %reg + BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), GR64Cand).addImm(64); + } else { + // No available register? Save RAX and reload it after use. + + // Allocate stack slot for stride register + Size = TRI->getSpillSize(X86::GR64RegClass); + Alignment = TRI->getSpillAlign(X86::GR64RegClass); + StrideSS = MF.getFrameInfo().CreateSpillStackObject(Size, Alignment); + + // mov %reg (%sp) + addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64mr)), + StrideSS) + .addReg(X86::RAX); + // mov 64 %reg + BuildMI(MBB, MI, DL, TII->get(X86::MOV64ri), X86::RAX).addImm(64); + } // tilestored %tmm, (%sp, %idx) #define GET_EGPR_IF_ENABLED(OPC) (ST.hasEGPR() ? OPC##_EVEX : OPC) unsigned Opc = GET_EGPR_IF_ENABLED(X86::TILESTORED); @@ -120,10 +153,12 @@ bool X86LowerTileCopy::runOnMachineFunction(MachineFunction &MF) { #undef GET_EGPR_IF_ENABLED NewMI = addFrameReference(BuildMI(MBB, MI, DL, TII->get(Opc), DstReg), TileSS); - // restore %rax - // mov (%sp) %rax - addFrameReference(BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand), - StrideSS); + if (!GR64Cand) { + // restore %rax + // mov (%sp) %rax + addFrameReference( + BuildMI(MBB, MI, DL, TII->get(X86::MOV64rm), GR64Cand), StrideSS); + } MI.eraseFromParent(); Changed = true; } diff --git a/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll b/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll index 4686361ad2fc..a0085afbaf02 100644 --- a/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll +++ b/llvm/test/CodeGen/X86/AMX/amx-lower-tile-copy.ll @@ -44,12 +44,8 @@ define dso_local void @test1(ptr%buf) nounwind { ; CHECK-NEXT: tileloadd 3024(%rsp,%rax), %tmm3 # 1024-byte Folded Reload ; CHECK-NEXT: tileloadd (%rbx,%r15), %tmm0 ; CHECK-NEXT: tileloadd (%rbx,%r15), %tmm1 -; CHECK-NEXT: # implicit-def: $rax -; CHECK-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; CHECK-NEXT: movabsq $64, %rax ; CHECK-NEXT: tilestored %tmm3, 1024(%rsp,%rax) # 1024-byte Folded Spill ; CHECK-NEXT: tileloadd {{[-0-9]+}}(%r{{[sb]}}p), %tmm2 # 1024-byte Folded Reload -; CHECK-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload ; CHECK-NEXT: tdpbssd %tmm1, %tmm0, %tmm2 ; CHECK-NEXT: tilestored %tmm2, (%rbx,%r15) ; CHECK-NEXT: incl %r14d @@ -111,16 +107,10 @@ define dso_local void @test1(ptr%buf) nounwind { ; EGPR-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7b,0x4b,0x9c,0x04,0xd0,0x0b,0x00,0x00] ; EGPR-NEXT: tileloadd (%rbx,%r15), %tmm0 # EVEX TO VEX Compression encoding: [0xc4,0xa2,0x7b,0x4b,0x04,0x3b] ; EGPR-NEXT: tileloadd (%rbx,%r15), %tmm1 # EVEX TO VEX Compression encoding: [0xc4,0xa2,0x7b,0x4b,0x0c,0x3b] -; EGPR-NEXT: # implicit-def: $rax -; EGPR-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; EGPR-NEXT: # encoding: [0x48,0x89,0x84,0x24,0xb8,0x03,0x00,0x00] -; EGPR-NEXT: movabsq $64, %rax # encoding: [0x48,0xb8,0x40,0x00,0x00,0x00,0x00,0x00,0x00,0x00] ; EGPR-NEXT: tilestored %tmm3, 1024(%rsp,%rax) # 1024-byte Folded Spill ; EGPR-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7a,0x4b,0x9c,0x04,0x00,0x04,0x00,0x00] ; EGPR-NEXT: tileloadd {{[-0-9]+}}(%r{{[sb]}}p), %tmm2 # 1024-byte Folded Reload ; EGPR-NEXT: # EVEX TO VEX Compression encoding: [0xc4,0xe2,0x7b,0x4b,0x94,0x24,0x00,0x04,0x00,0x00] -; EGPR-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rax # 8-byte Reload -; EGPR-NEXT: # encoding: [0x48,0x8b,0x84,0x24,0xb8,0x03,0x00,0x00] ; EGPR-NEXT: tdpbssd %tmm1, %tmm0, %tmm2 # encoding: [0xc4,0xe2,0x73,0x5e,0xd0] ; EGPR-NEXT: tilestored %tmm2, (%rbx,%r15) # EVEX TO VEX Compression encoding: [0xc4,0xa2,0x7a,0x4b,0x14,0x3b] ; EGPR-NEXT: incl %r14d # encoding: [0x41,0xff,0xc6] -- GitLab From 53cda4ca3b97b3787e5bf8738119dab2d5bd1889 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 28 Apr 2024 20:18:03 -0700 Subject: [PATCH 177/301] [Transforms] Use LLVMContext::MD_loop (NFC) --- llvm/lib/Transforms/Utils/BasicBlockUtils.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp index 4941f92b94f0..51fc28ef90ef 100644 --- a/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp +++ b/llvm/lib/Transforms/Utils/BasicBlockUtils.cpp @@ -1405,13 +1405,13 @@ SplitBlockPredecessorsImpl(BasicBlock *BB, ArrayRef Preds, if (OldLatch) { BasicBlock *NewLatch = L->getLoopLatch(); if (NewLatch != OldLatch) { - MDNode *MD = OldLatch->getTerminator()->getMetadata("llvm.loop"); - NewLatch->getTerminator()->setMetadata("llvm.loop", MD); + MDNode *MD = OldLatch->getTerminator()->getMetadata(LLVMContext::MD_loop); + NewLatch->getTerminator()->setMetadata(LLVMContext::MD_loop, MD); // It's still possible that OldLatch is the latch of another inner loop, // in which case we do not remove the metadata. Loop *IL = LI->getLoopFor(OldLatch); if (IL && IL->getLoopLatch() != OldLatch) - OldLatch->getTerminator()->setMetadata("llvm.loop", nullptr); + OldLatch->getTerminator()->setMetadata(LLVMContext::MD_loop, nullptr); } } -- GitLab From 3785d7424680e0bcb914a485af61be51559ab1ba Mon Sep 17 00:00:00 2001 From: Kareem Ergawy Date: Mon, 29 Apr 2024 05:46:37 +0200 Subject: [PATCH 178/301] =?UTF-8?q?[flang][OpenMP][LLVMIR]=20Support=20CFG?= =?UTF-8?q?=20and=20LLVM=20IR=20conversion=20for=20`omp.p=E2=80=A6=20(#901?= =?UTF-8?q?64)?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit …rivate` Adds support for CFG conversion and conversion to LLVM IR for `omp.private` ops. This bridges a gap between FIR and LLVM to provide more support for lowering `omp.private` ops for things like allocatables. --- flang/include/flang/Tools/CLOptions.inc | 2 +- flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp | 3 ++ flang/test/Driver/bbc-mlir-pass-pipeline.f90 | 8 ++- .../test/Driver/mlir-debug-pass-pipeline.f90 | 12 +++-- flang/test/Driver/mlir-pass-pipeline.f90 | 12 +++-- flang/test/Fir/basic-program.fir | 14 +++-- .../OpenMP/cfg-conversion-omp.private.f90 | 54 +++++++++++++++++++ 7 files changed, 92 insertions(+), 13 deletions(-) create mode 100644 flang/test/Lower/OpenMP/cfg-conversion-omp.private.f90 diff --git a/flang/include/flang/Tools/CLOptions.inc b/flang/include/flang/Tools/CLOptions.inc index 8f197038f2ba..34af9f1c21f8 100644 --- a/flang/include/flang/Tools/CLOptions.inc +++ b/flang/include/flang/Tools/CLOptions.inc @@ -104,7 +104,7 @@ void addNestedPassToOps(mlir::PassManager &pm, PassConstructor ctor) { void addNestedPassToAllTopLevelOperations( mlir::PassManager &pm, PassConstructor ctor) { addNestedPassToOps(pm, ctor); + mlir::omp::PrivateClauseOp, fir::GlobalOp>(pm, ctor); } void addNestedPassToAllTopLevelOperationsConditionally(mlir::PassManager &pm, diff --git a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp index 00c5f77cde7c..d6dac4998fdc 100644 --- a/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp +++ b/flang/lib/Optimizer/CodeGen/FIROpPatterns.cpp @@ -243,6 +243,9 @@ ConvertFIRToLLVMPattern::getBlockForAllocaInsert(mlir::Operation *op) const { return iface.getAllocaBlock(); if (auto llvmFuncOp = mlir::dyn_cast(op)) return &llvmFuncOp.front(); + if (auto ompPrivateOp = mlir::dyn_cast(op)) + return &ompPrivateOp.getAllocRegion().front(); + return getBlockForAllocaInsert(op->getParentOp()); } diff --git a/flang/test/Driver/bbc-mlir-pass-pipeline.f90 b/flang/test/Driver/bbc-mlir-pass-pipeline.f90 index 7a35e26dc478..caa86e66e62b 100644 --- a/flang/test/Driver/bbc-mlir-pass-pipeline.f90 +++ b/flang/test/Driver/bbc-mlir-pass-pipeline.f90 @@ -17,7 +17,7 @@ end program ! CHECK-NEXT: (S) 0 num-cse'd - Number of operations CSE'd ! CHECK-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -! CHECK-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! CHECK-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! CHECK-NEXT: 'fir.global' Pipeline ! CHECK-NEXT: CharacterConversion ! CHECK-NEXT: 'func.func' Pipeline @@ -25,6 +25,8 @@ end program ! CHECK-NEXT: CharacterConversion ! CHECK-NEXT: 'omp.declare_reduction' Pipeline ! CHECK-NEXT: CharacterConversion +! CHECK-NEXT: 'omp.private' Pipeline +! CHECK-NEXT: CharacterConversion ! CHECK-NEXT: Canonicalizer ! CHECK-NEXT: SimplifyRegionLite @@ -43,7 +45,7 @@ end program ! CHECK-NEXT: (S) 0 num-cse'd - Number of operations CSE'd ! CHECK-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -! CHECK-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! CHECK-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! CHECK-NEXT: 'fir.global' Pipeline ! CHECK-NEXT: CFGConversion ! CHECK-NEXT: 'func.func' Pipeline @@ -51,6 +53,8 @@ end program ! CHECK-NEXT: CFGConversion ! CHECK-NEXT: 'omp.declare_reduction' Pipeline ! CHECK-NEXT: CFGConversion +! CHECK-NEXT: 'omp.private' Pipeline +! CHECK-NEXT: CFGConversion ! CHECK-NEXT: SCFToControlFlow ! CHECK-NEXT: Canonicalizer diff --git a/flang/test/Driver/mlir-debug-pass-pipeline.f90 b/flang/test/Driver/mlir-debug-pass-pipeline.f90 index 28d70bc15264..2c81441e7ec9 100644 --- a/flang/test/Driver/mlir-debug-pass-pipeline.f90 +++ b/flang/test/Driver/mlir-debug-pass-pipeline.f90 @@ -39,7 +39,7 @@ end program ! ALL-NEXT: (S) 0 num-cse'd - Number of operations CSE'd ! ALL-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! ALL-NEXT: 'fir.global' Pipeline ! ALL-NEXT: CharacterConversion ! ALL-NEXT: 'func.func' Pipeline @@ -47,6 +47,8 @@ end program ! ALL-NEXT: CharacterConversion ! ALL-NEXT: 'omp.declare_reduction' Pipeline ! ALL-NEXT: CharacterConversion +! ALL-NEXT: 'omp.private' Pipeline +! ALL-NEXT: CharacterConversion ! ALL-NEXT: Canonicalizer ! ALL-NEXT: SimplifyRegionLite @@ -63,7 +65,7 @@ end program ! ALL-NEXT: (S) 0 num-cse'd - Number of operations CSE'd ! ALL-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! ALL-NEXT: 'fir.global' Pipeline ! ALL-NEXT: CFGConversion ! ALL-NEXT: 'func.func' Pipeline @@ -71,6 +73,8 @@ end program ! ALL-NEXT: CFGConversion ! ALL-NEXT: 'omp.declare_reduction' Pipeline ! ALL-NEXT: CFGConversion +! ALL-NEXT: 'omp.private' Pipeline +! ALL-NEXT: CFGConversion ! ALL-NEXT: SCFToControlFlow ! ALL-NEXT: Canonicalizer ! ALL-NEXT: SimplifyRegionLite @@ -79,13 +83,15 @@ end program ! ALL-NEXT: (S) 0 num-dce'd - Number of operations DCE'd ! ALL-NEXT: BoxedProcedurePass -! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! ALL-NEXT: 'fir.global' Pipeline ! ALL-NEXT: AbstractResultOpt ! ALL-NEXT: 'func.func' Pipeline ! ALL-NEXT: AbstractResultOpt ! ALL-NEXT: 'omp.declare_reduction' Pipeline ! ALL-NEXT: AbstractResultOpt +! ALL-NEXT: 'omp.private' Pipeline +! ALL-NEXT: AbstractResultOpt ! ALL-NEXT: CodeGenRewrite ! ALL-NEXT: (S) 0 num-dce'd - Number of operations eliminated diff --git a/flang/test/Driver/mlir-pass-pipeline.f90 b/flang/test/Driver/mlir-pass-pipeline.f90 index 41f3c203e435..320467a2ac2a 100644 --- a/flang/test/Driver/mlir-pass-pipeline.f90 +++ b/flang/test/Driver/mlir-pass-pipeline.f90 @@ -28,7 +28,7 @@ end program ! ALL-NEXT: (S) 0 num-cse'd - Number of operations CSE'd ! ALL-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! ALL-NEXT: 'fir.global' Pipeline ! ALL-NEXT: CharacterConversion ! ALL-NEXT: 'func.func' Pipeline @@ -36,6 +36,8 @@ end program ! ALL-NEXT: CharacterConversion ! ALL-NEXT: 'omp.declare_reduction' Pipeline ! ALL-NEXT: CharacterConversion +! ALL-NEXT: 'omp.private' Pipeline +! ALL-NEXT: CharacterConversion ! ALL-NEXT: Canonicalizer ! ALL-NEXT: SimplifyRegionLite @@ -57,7 +59,7 @@ end program ! O2-NEXT: 'func.func' Pipeline ! O2-NEXT: PolymorphicOpConversion ! O2-NEXT: AddAliasTags -! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! ALL-NEXT: 'fir.global' Pipeline ! ALL-NEXT: CFGConversion ! ALL-NEXT: 'func.func' Pipeline @@ -65,6 +67,8 @@ end program ! ALL-NEXT: CFGConversion ! ALL-NEXT: 'omp.declare_reduction' Pipeline ! ALL-NEXT: CFGConversion +! ALL-NEXT: 'omp.private' Pipeline +! ALL-NEXT: CFGConversion ! ALL-NEXT: SCFToControlFlow ! ALL-NEXT: Canonicalizer @@ -74,13 +78,15 @@ end program ! ALL-NEXT: (S) 0 num-dce'd - Number of operations DCE'd ! ALL-NEXT: BoxedProcedurePass -! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +! ALL-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] ! ALL-NEXT: 'fir.global' Pipeline ! ALL-NEXT: AbstractResultOpt ! ALL-NEXT: 'func.func' Pipeline ! ALL-NEXT: AbstractResultOpt ! ALL-NEXT: 'omp.declare_reduction' Pipeline ! ALL-NEXT: AbstractResultOpt +! ALL-NEXT: 'omp.private' Pipeline +! ALL-NEXT: AbstractResultOpt ! ALL-NEXT: CodeGenRewrite ! ALL-NEXT: (S) 0 num-dce'd - Number of operations eliminated diff --git a/flang/test/Fir/basic-program.fir b/flang/test/Fir/basic-program.fir index 7508963a3d51..d54b0895cc33 100644 --- a/flang/test/Fir/basic-program.fir +++ b/flang/test/Fir/basic-program.fir @@ -34,7 +34,7 @@ func.func @_QQmain() { // PASSES-NEXT: (S) 0 num-cse'd - Number of operations CSE'd // PASSES-NEXT: (S) 0 num-dce'd - Number of operations DCE'd -// PASSES-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +// PASSES-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] // PASSES-NEXT: 'fir.global' Pipeline // PASSES-NEXT: CharacterConversion // PASSES-NEXT: 'func.func' Pipeline @@ -42,6 +42,8 @@ func.func @_QQmain() { // PASSES-NEXT: CharacterConversion // PASSES-NEXT: 'omp.declare_reduction' Pipeline // PASSES-NEXT: CharacterConversion +// PASSES-NEXT: 'omp.private' Pipeline +// PASSES-NEXT: CharacterConversion // PASSES-NEXT: Canonicalizer // PASSES-NEXT: SimplifyRegionLite @@ -65,13 +67,15 @@ func.func @_QQmain() { // PASSES-NEXT: AddAliasTags -// PASSES-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] +// PASSES-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] // PASSES-NEXT: 'fir.global' Pipeline // PASSES-NEXT: CFGConversion // PASSES-NEXT: 'func.func' Pipeline // PASSES-NEXT: CFGConversion // PASSES-NEXT: 'omp.declare_reduction' Pipeline // PASSES-NEXT: CFGConversion +// PASSES-NEXT: 'omp.private' Pipeline +// PASSES-NEXT: CFGConversion // PASSES-NEXT: SCFToControlFlow // PASSES-NEXT: Canonicalizer @@ -81,13 +85,15 @@ func.func @_QQmain() { // PASSES-NEXT: (S) 0 num-dce'd - Number of operations DCE'd // PASSES-NEXT: BoxedProcedurePass -// PASSES-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction'] -// PASSES-NEXT: 'fir.global' Pipeline +// PASSES-NEXT: Pipeline Collection : ['fir.global', 'func.func', 'omp.declare_reduction', 'omp.private'] +// PASSES-NEXT: 'fir.global' Pipeline // PASSES-NEXT: AbstractResultOpt // PASSES-NEXT: 'func.func' Pipeline // PASSES-NEXT: AbstractResultOpt // PASSES-NEXT: 'omp.declare_reduction' Pipeline // PASSES-NEXT: AbstractResultOpt +// PASSES-NEXT: 'omp.private' Pipeline +// PASSES-NEXT: AbstractResultOpt // PASSES-NEXT: CodeGenRewrite // PASSES-NEXT: (S) 0 num-dce'd - Number of operations eliminated diff --git a/flang/test/Lower/OpenMP/cfg-conversion-omp.private.f90 b/flang/test/Lower/OpenMP/cfg-conversion-omp.private.f90 new file mode 100644 index 000000000000..7f1087a7ebe3 --- /dev/null +++ b/flang/test/Lower/OpenMP/cfg-conversion-omp.private.f90 @@ -0,0 +1,54 @@ +! Tests that CFG & LLVM conversion is applied to `omp.private` ops. + +! RUN: split-file %s %t && cd %t + +! RUN: %flang_fc1 -emit-hlfir -fopenmp -mmlir --openmp-enable-delayed-privatization \ +! RUN: -o - test.f90 2>&1 | \ +! RUN: fir-opt --cfg-conversion -o test.cfg-conv.mlir +! RUN: FileCheck --input-file=test.cfg-conv.mlir %s --check-prefix="CFGConv" + +! RUN: fir-opt --convert-hlfir-to-fir --cg-rewrite --fir-to-llvm-ir test.cfg-conv.mlir -o - | \ +! RUN: FileCheck %s --check-prefix="LLVMDialect" + +!--- test.f90 +subroutine delayed_privatization_allocatable + implicit none + integer, allocatable :: var1 + +!$omp parallel private(var1) + var1 = 10 +!$omp end parallel +end subroutine + +! CFGConv-LABEL: omp.private {type = private} +! CFGConv-SAME: @[[PRIVATIZER_SYM:.*]] : [[TYPE:!fir.ref>>]] alloc { + +! CFGConv-NEXT: ^bb0(%[[PRIV_ARG:.*]]: [[TYPE]]): + +! CFGConv-NEXT: %[[PRIV_ALLOC:.*]] = fir.alloca !fir.box> {bindc_name = "var1", pinned, uniq_name = "_QFdelayed_privatization_allocatableEvar1"} + +! CFGConv-NEXT: %[[PRIV_ARG_VAL:.*]] = fir.load %[[PRIV_ARG]] : !fir.ref>> +! CFGConv-NEXT: %[[PRIV_ARG_BOX:.*]] = fir.box_addr %[[PRIV_ARG_VAL]] : (!fir.box>) -> !fir.heap +! CFGConv-NEXT: %[[PRIV_ARG_ADDR:.*]] = fir.convert %[[PRIV_ARG_BOX]] : (!fir.heap) -> i64 +! CFGConv-NEXT: %[[C0:.*]] = arith.constant 0 : i64 +! CFGConv-NEXT: %[[ALLOC_COND:.*]] = arith.cmpi ne, %[[PRIV_ARG_ADDR]], %[[C0]] : i64 +! CFGConv-NEXT: cf.cond_br %[[ALLOC_COND]], ^[[ALLOC_MEM_BB:.*]], ^[[ZERO_MEM_BB:.*]] +! CFGConv-NEXT: ^[[ALLOC_MEM_BB]]: +! CFGConv-NEXT: fir.allocmem +! CFGConv: cf.br ^[[DECL_BB:.*]] +! CFGConv: ^[[ZERO_MEM_BB]]: +! CFGConv-NEXT: fir.zero_bits +! CFGConv: cf.br ^[[DECL_BB:.*]] +! CFGConv-NEXT: ^[[DECL_BB]]: +! CFGConv-NEXT: hlfir.declare +! CFGConv-NEXT: omp.yield + + +! LLVMDialect-LABEL: omp.private {type = private} +! LLVMDialect-SAME: @[[PRIVATIZER_SYM:.*]] : [[TYPE:!llvm.ptr]] alloc { + +! LLVMDialect-NEXT: ^bb0(%[[PRIV_ARG:.*]]: [[TYPE]]): +! LLVMDialect: llvm.alloca +! LLVMDialect: llvm.call @malloc + +! LLVMDialect-NOT: hlfir.declare -- GitLab From fa8fda85c6792d9078922ab8658c321c4939e63a Mon Sep 17 00:00:00 2001 From: Adrian Kuegel Date: Mon, 29 Apr 2024 05:32:10 +0000 Subject: [PATCH 179/301] [mlir][Bazel] Add missing dependency after 145176dc0c93566ce4aef721044d49ab8ba50f87 --- utils/bazel/llvm-project-overlay/mlir/BUILD.bazel | 1 + 1 file changed, 1 insertion(+) diff --git a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel index 6a6f8fc13410..52c874c344c5 100644 --- a/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel +++ b/utils/bazel/llvm-project-overlay/mlir/BUILD.bazel @@ -6697,6 +6697,7 @@ cc_library( ]), includes = ["include"], deps = [ + ":ArithDialect", ":IR", ":InferTypeOpInterface", ":PolynomialAttributesIncGen", -- GitLab From 501cfd5243c025b22075e1f13817a0a37fef96a6 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 28 Apr 2024 22:36:59 -0700 Subject: [PATCH 180/301] [X86] Use static_asserts instead of assert (NFC) Identified with misc-static-assert. --- .../lib/Target/X86/MCTargetDesc/X86BaseInfo.h | 21 ++++++++++--------- llvm/lib/Target/X86/X86RegisterInfo.cpp | 9 ++++---- 2 files changed, 16 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h index c0a75e215a40..8e4015783641 100644 --- a/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h +++ b/llvm/lib/Target/X86/MCTargetDesc/X86BaseInfo.h @@ -1168,33 +1168,34 @@ inline int getMemoryOperandNo(uint64_t TSFlags) { /// \returns true if the register is a XMM. inline bool isXMMReg(unsigned RegNo) { - assert(X86::XMM15 - X86::XMM0 == 15 && - "XMM0-15 registers are not continuous"); - assert(X86::XMM31 - X86::XMM16 == 15 && - "XMM16-31 registers are not continuous"); + static_assert(X86::XMM15 - X86::XMM0 == 15, + "XMM0-15 registers are not continuous"); + static_assert(X86::XMM31 - X86::XMM16 == 15, + "XMM16-31 registers are not continuous"); return (RegNo >= X86::XMM0 && RegNo <= X86::XMM15) || (RegNo >= X86::XMM16 && RegNo <= X86::XMM31); } /// \returns true if the register is a YMM. inline bool isYMMReg(unsigned RegNo) { - assert(X86::YMM15 - X86::YMM0 == 15 && - "YMM0-15 registers are not continuous"); - assert(X86::YMM31 - X86::YMM16 == 15 && - "YMM16-31 registers are not continuous"); + static_assert(X86::YMM15 - X86::YMM0 == 15, + "YMM0-15 registers are not continuous"); + static_assert(X86::YMM31 - X86::YMM16 == 15, + "YMM16-31 registers are not continuous"); return (RegNo >= X86::YMM0 && RegNo <= X86::YMM15) || (RegNo >= X86::YMM16 && RegNo <= X86::YMM31); } /// \returns true if the register is a ZMM. inline bool isZMMReg(unsigned RegNo) { - assert(X86::ZMM31 - X86::ZMM0 == 31 && "ZMM registers are not continuous"); + static_assert(X86::ZMM31 - X86::ZMM0 == 31, + "ZMM registers are not continuous"); return RegNo >= X86::ZMM0 && RegNo <= X86::ZMM31; } /// \returns true if \p RegNo is an apx extended register. inline bool isApxExtendedReg(unsigned RegNo) { - assert(X86::R31WH - X86::R16 == 95 && "EGPRs are not continuous"); + static_assert(X86::R31WH - X86::R16 == 95, "EGPRs are not continuous"); return RegNo >= X86::R16 && RegNo <= X86::R31WH; } diff --git a/llvm/lib/Target/X86/X86RegisterInfo.cpp b/llvm/lib/Target/X86/X86RegisterInfo.cpp index be0cf1596d0d..555ede9e9540 100644 --- a/llvm/lib/Target/X86/X86RegisterInfo.cpp +++ b/llvm/lib/Target/X86/X86RegisterInfo.cpp @@ -649,10 +649,11 @@ unsigned X86RegisterInfo::getNumSupportedRegs(const MachineFunction &MF) const { // APX registers (R16-R31) // // and try to return the minimum number of registers supported by the target. - assert((X86::R15WH + 1 == X86 ::YMM0) && (X86::YMM15 + 1 == X86::K0) && - (X86::K6_K7 + 1 == X86::TMMCFG) && (X86::TMM7 + 1 == X86::R16) && - (X86::R31WH + 1 == X86::NUM_TARGET_REGS) && - "Register number may be incorrect"); + static_assert((X86::R15WH + 1 == X86::YMM0) && (X86::YMM15 + 1 == X86::K0) && + (X86::K6_K7 + 1 == X86::TMMCFG) && + (X86::TMM7 + 1 == X86::R16) && + (X86::R31WH + 1 == X86::NUM_TARGET_REGS), + "Register number may be incorrect"); const X86Subtarget &ST = MF.getSubtarget(); if (ST.hasEGPR()) -- GitLab From 6cd6bde3090a405e4091ef6f743cb2e56b376a55 Mon Sep 17 00:00:00 2001 From: Shih-Po Hung Date: Mon, 29 Apr 2024 13:48:08 +0800 Subject: [PATCH 181/301] [RISCV] Remove -riscv-v-fixed-length-vector-lmul-max from arith tests (#89886) This patch splits off from #89170 to clean up the tests. --- .../test/Analysis/CostModel/RISCV/arith-fp.ll | 62 +++++++++---------- .../Analysis/CostModel/RISCV/arith-int.ll | 52 ++++++++-------- 2 files changed, 57 insertions(+), 57 deletions(-) diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll b/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll index 306277e46fa5..1dde88f366a3 100644 --- a/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll +++ b/llvm/test/Analysis/CostModel/RISCV/arith-fp.ll @@ -1,5 +1,5 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-min=128 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s +; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh -riscv-v-vector-bits-min=128 < %s | FileCheck %s ; Check that we don't crash querying costs when vectors are not enabled. ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 @@ -252,8 +252,8 @@ define i32 @fdiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F16 = fdiv <2 x half> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F16 = fdiv <4 x half> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F16 = fdiv <8 x half> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F16 = fdiv <16 x half> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V32F16 = fdiv <32 x half> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F16 = fdiv <16 x half> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V32F16 = fdiv <32 x half> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1F16 = fdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F16 = fdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4F16 = fdiv undef, undef @@ -263,8 +263,8 @@ define i32 @fdiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F32 = fdiv <1 x float> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F32 = fdiv <2 x float> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F32 = fdiv <4 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F32 = fdiv <8 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V16F32 = fdiv <16 x float> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = fdiv <8 x float> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F32 = fdiv <16 x float> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1F32 = fdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F32 = fdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4F32 = fdiv undef, undef @@ -272,8 +272,8 @@ define i32 @fdiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV16F32 = fdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V1F64 = fdiv <1 x double> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V2F64 = fdiv <2 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V4F64 = fdiv <4 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %V8F64 = fdiv <8 x double> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = fdiv <4 x double> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F64 = fdiv <8 x double> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV1F64 = fdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV2F64 = fdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %NXV4F64 = fdiv undef, undef @@ -332,8 +332,8 @@ define i32 @frem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2F16 = frem <2 x half> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F16 = frem <4 x half> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F16 = frem <8 x half> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F16 = frem <16 x half> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 96 for instruction: %V32F16 = frem <32 x half> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16F16 = frem <16 x half> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 127 for instruction: %V32F16 = frem <32 x half> undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV1F16 = frem undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV2F16 = frem undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV4F16 = frem undef, undef @@ -343,8 +343,8 @@ define i32 @frem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F32 = frem <1 x float> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2F32 = frem <2 x float> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F32 = frem <4 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F32 = frem <8 x float> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 48 for instruction: %V16F32 = frem <16 x float> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F32 = frem <8 x float> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 63 for instruction: %V16F32 = frem <16 x float> undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV1F32 = frem undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV2F32 = frem undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV4F32 = frem undef, undef @@ -352,8 +352,8 @@ define i32 @frem() { ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV16F32 = frem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %V1F64 = frem <1 x double> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 7 for instruction: %V2F64 = frem <2 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %V4F64 = frem <4 x double> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %V8F64 = frem <8 x double> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %V4F64 = frem <4 x double> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 31 for instruction: %V8F64 = frem <8 x double> undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV1F64 = frem undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV2F64 = frem undef, undef ; CHECK-NEXT: Cost Model: Invalid cost for instruction: %NXV4F64 = frem undef, undef @@ -492,8 +492,8 @@ define i32 @fcopysign() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F16 = call <2 x half> @llvm.copysign.v2f16(<2 x half> undef, <2 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F16 = call <4 x half> @llvm.copysign.v4f16(<4 x half> undef, <4 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F16 = call <8 x half> @llvm.copysign.v8f16(<8 x half> undef, <8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F16 = call <16 x half> @llvm.copysign.v16f16(<16 x half> undef, <16 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32F16 = call <32 x half> @llvm.copysign.v32f16(<32 x half> undef, <32 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F16 = call <16 x half> @llvm.copysign.v16f16(<16 x half> undef, <16 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32F16 = call <32 x half> @llvm.copysign.v32f16(<32 x half> undef, <32 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1F16 = call @llvm.copysign.nxv1f16( undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F16 = call @llvm.copysign.nxv2f16( undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F16 = call @llvm.copysign.nxv4f16( undef, undef) @@ -503,8 +503,8 @@ define i32 @fcopysign() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1F32 = call <1 x float> @llvm.copysign.v1f32(<1 x float> undef, <1 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F32 = call <2 x float> @llvm.copysign.v2f32(<2 x float> undef, <2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F32 = call <4 x float> @llvm.copysign.v4f32(<4 x float> undef, <4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = call <8 x float> @llvm.copysign.v8f32(<8 x float> undef, <8 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F32 = call <16 x float> @llvm.copysign.v16f32(<16 x float> undef, <16 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = call <8 x float> @llvm.copysign.v8f32(<8 x float> undef, <8 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F32 = call <16 x float> @llvm.copysign.v16f32(<16 x float> undef, <16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1F32 = call @llvm.copysign.nxv1f32( undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F32 = call @llvm.copysign.nxv2f32( undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F32 = call @llvm.copysign.nxv4f32( undef, undef) @@ -512,8 +512,8 @@ define i32 @fcopysign() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16F32 = call @llvm.copysign.nxv16f32( undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1F64 = call <1 x double> @llvm.copysign.v1f64(<1 x double> undef, <1 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F64 = call <2 x double> @llvm.copysign.v2f64(<2 x double> undef, <2 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = call <4 x double> @llvm.copysign.v4f64(<4 x double> undef, <4 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = call <8 x double> @llvm.copysign.v8f64(<8 x double> undef, <8 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = call <4 x double> @llvm.copysign.v4f64(<4 x double> undef, <4 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F64 = call <8 x double> @llvm.copysign.v8f64(<8 x double> undef, <8 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1F64 = call @llvm.copysign.nxv1f64( undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F64 = call @llvm.copysign.nxv2f64( undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F64 = call @llvm.copysign.nxv4f64( undef, undef) @@ -572,8 +572,8 @@ define i32 @fma() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F16 = call <2 x half> @llvm.fma.v2f16(<2 x half> undef, <2 x half> undef, <2 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F16 = call <4 x half> @llvm.fma.v4f16(<4 x half> undef, <4 x half> undef, <4 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F16 = call <8 x half> @llvm.fma.v8f16(<8 x half> undef, <8 x half> undef, <8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16F16 = call <16 x half> @llvm.fma.v16f16(<16 x half> undef, <16 x half> undef, <16 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32F16 = call <32 x half> @llvm.fma.v32f16(<32 x half> undef, <32 x half> undef, <32 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F16 = call <16 x half> @llvm.fma.v16f16(<16 x half> undef, <16 x half> undef, <16 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32F16 = call <32 x half> @llvm.fma.v32f16(<32 x half> undef, <32 x half> undef, <32 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1F16 = call @llvm.fma.nxv1f16( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F16 = call @llvm.fma.nxv2f16( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F16 = call @llvm.fma.nxv4f16( undef, undef, undef) @@ -583,8 +583,8 @@ define i32 @fma() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1F32 = call <1 x float> @llvm.fma.v1f32(<1 x float> undef, <1 x float> undef, <1 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F32 = call <2 x float> @llvm.fma.v2f32(<2 x float> undef, <2 x float> undef, <2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F32 = call <4 x float> @llvm.fma.v4f32(<4 x float> undef, <4 x float> undef, <4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8F32 = call <8 x float> @llvm.fma.v8f32(<8 x float> undef, <8 x float> undef, <8 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16F32 = call <16 x float> @llvm.fma.v16f32(<16 x float> undef, <16 x float> undef, <16 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F32 = call <8 x float> @llvm.fma.v8f32(<8 x float> undef, <8 x float> undef, <8 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16F32 = call <16 x float> @llvm.fma.v16f32(<16 x float> undef, <16 x float> undef, <16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1F32 = call @llvm.fma.nxv1f32( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F32 = call @llvm.fma.nxv2f32( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F32 = call @llvm.fma.nxv4f32( undef, undef, undef) @@ -592,8 +592,8 @@ define i32 @fma() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16F32 = call @llvm.fma.nxv16f32( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1F64 = call <1 x double> @llvm.fma.v1f64(<1 x double> undef, <1 x double> undef, <1 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2F64 = call <2 x double> @llvm.fma.v2f64(<2 x double> undef, <2 x double> undef, <2 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4F64 = call <4 x double> @llvm.fma.v4f64(<4 x double> undef, <4 x double> undef, <4 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8F64 = call <8 x double> @llvm.fma.v8f64(<8 x double> undef, <8 x double> undef, <8 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4F64 = call <4 x double> @llvm.fma.v4f64(<4 x double> undef, <4 x double> undef, <4 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8F64 = call <8 x double> @llvm.fma.v8f64(<8 x double> undef, <8 x double> undef, <8 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1F64 = call @llvm.fma.nxv1f64( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2F64 = call @llvm.fma.nxv2f64( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4F64 = call @llvm.fma.nxv4f64( undef, undef, undef) @@ -651,15 +651,15 @@ define void @fmuladd() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %4 = call <2 x half> @llvm.fmuladd.v2f16(<2 x half> undef, <2 x half> undef, <2 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = call <4 x half> @llvm.fmuladd.v4f16(<4 x half> undef, <4 x half> undef, <4 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %6 = call <8 x half> @llvm.fmuladd.v8f16(<8 x half> undef, <8 x half> undef, <8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %7 = call <16 x half> @llvm.fmuladd.v16f16(<16 x half> undef, <16 x half> undef, <16 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %7 = call <16 x half> @llvm.fmuladd.v16f16(<16 x half> undef, <16 x half> undef, <16 x half> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %8 = call <2 x float> @llvm.fmuladd.v2f32(<2 x float> undef, <2 x float> undef, <2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %9 = call <4 x float> @llvm.fmuladd.v4f32(<4 x float> undef, <4 x float> undef, <4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %10 = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> undef, <8 x float> undef, <8 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %11 = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> undef, <16 x float> undef, <16 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %10 = call <8 x float> @llvm.fmuladd.v8f32(<8 x float> undef, <8 x float> undef, <8 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %11 = call <16 x float> @llvm.fmuladd.v16f32(<16 x float> undef, <16 x float> undef, <16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %12 = call <2 x double> @llvm.fmuladd.v2f64(<2 x double> undef, <2 x double> undef, <2 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %13 = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> undef, <4 x double> undef, <4 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %14 = call <8 x double> @llvm.fmuladd.v8f64(<8 x double> undef, <8 x double> undef, <8 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %15 = call <16 x double> @llvm.fmuladd.v16f64(<16 x double> undef, <16 x double> undef, <16 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %13 = call <4 x double> @llvm.fmuladd.v4f64(<4 x double> undef, <4 x double> undef, <4 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %14 = call <8 x double> @llvm.fmuladd.v8f64(<8 x double> undef, <8 x double> undef, <8 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %15 = call <16 x double> @llvm.fmuladd.v16f64(<16 x double> undef, <16 x double> undef, <16 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %16 = call @llvm.fmuladd.nxv1f16( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %17 = call @llvm.fmuladd.nxv2f16( undef, undef, undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %18 = call @llvm.fmuladd.nxv4f16( undef, undef, undef) diff --git a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll index 00f2cd7b63a4..b4afbb513166 100644 --- a/llvm/test/Analysis/CostModel/RISCV/arith-int.ll +++ b/llvm/test/Analysis/CostModel/RISCV/arith-int.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py -; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s -; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mcpu=sifive-x280 -riscv-v-fixed-length-vector-lmul-max=1 < %s | FileCheck %s --check-prefix=SIFIVE-X280 +; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mattr=+v,+f,+d,+zfh,+zvfh < %s | FileCheck %s +; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 -mcpu=sifive-x280 < %s | FileCheck %s --check-prefix=SIFIVE-X280 ; Check that we don't crash querying costs when vectors are not enabled. ; RUN: opt -passes="print" 2>&1 -disable-output -mtriple=riscv64 @@ -709,8 +709,8 @@ define i32 @udiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = udiv <2 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = udiv <4 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = udiv <8 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = udiv <16 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I16 = udiv <32 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = udiv <16 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = udiv <32 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = udiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = udiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = udiv undef, undef @@ -720,8 +720,8 @@ define i32 @udiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = udiv <1 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = udiv <2 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = udiv <4 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = udiv <8 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I32 = udiv <16 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = udiv <8 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = udiv <16 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = udiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = udiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = udiv undef, undef @@ -729,8 +729,8 @@ define i32 @udiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = udiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = udiv <1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = udiv <2 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = udiv <4 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = udiv <8 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = udiv <4 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = udiv <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = udiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = udiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = udiv undef, undef @@ -825,8 +825,8 @@ define i32 @urem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = urem <2 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = urem <4 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = urem <8 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = urem <16 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I16 = urem <32 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = urem <16 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = urem <32 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = urem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = urem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = urem undef, undef @@ -836,8 +836,8 @@ define i32 @urem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = urem <1 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = urem <2 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = urem <4 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = urem <8 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I32 = urem <16 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = urem <8 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = urem <16 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = urem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = urem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = urem undef, undef @@ -845,8 +845,8 @@ define i32 @urem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = urem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = urem <1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = urem <2 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = urem <4 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = urem <8 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = urem <4 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = urem <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = urem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = urem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = urem undef, undef @@ -941,8 +941,8 @@ define i32 @sdiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = sdiv <2 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = sdiv <4 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = sdiv <8 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = sdiv <16 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I16 = sdiv <32 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = sdiv <16 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = sdiv <32 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = sdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = sdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = sdiv undef, undef @@ -952,8 +952,8 @@ define i32 @sdiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = sdiv <1 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = sdiv <2 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = sdiv <4 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = sdiv <8 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I32 = sdiv <16 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = sdiv <8 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = sdiv <16 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = sdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = sdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = sdiv undef, undef @@ -961,8 +961,8 @@ define i32 @sdiv() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = sdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = sdiv <1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = sdiv <2 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = sdiv <4 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = sdiv <8 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = sdiv <4 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = sdiv <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = sdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = sdiv undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = sdiv undef, undef @@ -1057,8 +1057,8 @@ define i32 @srem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I16 = srem <2 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I16 = srem <4 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I16 = srem <8 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V16I16 = srem <16 x i16> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V32I16 = srem <32 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I16 = srem <16 x i16> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V32I16 = srem <32 x i16> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I16 = srem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I16 = srem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I16 = srem undef, undef @@ -1068,8 +1068,8 @@ define i32 @srem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I32 = srem <1 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I32 = srem <2 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I32 = srem <4 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V8I32 = srem <8 x i32> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V16I32 = srem <16 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I32 = srem <8 x i32> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V16I32 = srem <16 x i32> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I32 = srem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I32 = srem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I32 = srem undef, undef @@ -1077,8 +1077,8 @@ define i32 @srem() { ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV16I32 = srem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V1I64 = srem <1 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V2I64 = srem <2 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %V4I64 = srem <4 x i64> undef, undef -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %V8I64 = srem <8 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V4I64 = srem <4 x i64> undef, undef +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %V8I64 = srem <8 x i64> undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV1I64 = srem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV2I64 = srem undef, undef ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %NXV4I64 = srem undef, undef -- GitLab From b3c55b707110084a9f50a16aade34c3be6fa18da Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Bj=C3=B6rn=20Pettersson?= Date: Mon, 29 Apr 2024 07:56:49 +0200 Subject: [PATCH 182/301] [SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921) [SelectionDAG] Handle more opcodes in canCreateUndefOrPoison Handle SELECT_CC similarly as SETCC. Handle these operations that only propagate poison/undef based on the input operands: SADDSAT, UADDSAT, SSUBSAT, USUBSAT, MULHU, MULHS, SMIN, SMAX, UMIN, UMAX These operations may create poison based on shift amount and exact flag being violated: SRL, SRA One goal here is to allow pushing freeze through these operations when allowed, as well as letting analyses such as isGuaranteedNotToBeUndefOrPoison to not break on such operations. Since some problems have been observed with pushing freeze through SRA/SRL we block that explicitly in DAGCombiner::visitFreeze now. That way we can still model SRA/SRL properly in SelectionDAG::canCreateUndefOrPoison, e.g. when used by isGuaranteedNotToBeUndefOrPoison, even if we do not want to push freeze through those instructions. --- llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 6 + .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 16 +- llvm/test/CodeGen/AMDGPU/div_i128.ll | 96 ++-- llvm/test/CodeGen/AMDGPU/rem_i128.ll | 475 +++++++++--------- .../X86/div-rem-pair-recomposition-signed.ll | 396 ++++++++------- llvm/test/CodeGen/X86/freeze-binary.ll | 50 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 80 ++- 7 files changed, 556 insertions(+), 563 deletions(-) diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index b6d5b309ceb9..326a004d06f2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15459,6 +15459,12 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false)) return N0; + // We currently avoid folding freeze over SRA/SRL, due to the problems seen + // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for + // example https://reviews.llvm.org/D136529#4120959. + if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) + return SDValue(); + // Fold freeze(op(x, ...)) -> op(freeze(x), ...). // Try to push freeze through instructions that propagate but don't produce // poison as far as possible. If an operand of freeze follows three diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index dde10fd4b8c8..dfbfaa8c894f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5137,6 +5137,16 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::FREEZE: case ISD::CONCAT_VECTORS: case ISD::INSERT_SUBVECTOR: + case ISD::SADDSAT: + case ISD::UADDSAT: + case ISD::SSUBSAT: + case ISD::USUBSAT: + case ISD::MULHU: + case ISD::MULHS: + case ISD::SMIN: + case ISD::SMAX: + case ISD::UMIN: + case ISD::UMAX: case ISD::AND: case ISD::XOR: case ISD::ROTL: @@ -5157,6 +5167,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::BUILD_PAIR: return false; + case ISD::SELECT_CC: case ISD::SETCC: { // Integer setcc cannot create undef or poison. if (Op.getOperand(0).getValueType().isInteger()) @@ -5166,7 +5177,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, // based on options and flags. The options and flags also cause special // nonan condition codes to be used. Those condition codes may be preserved // even if the nonan flag is dropped somewhere. - ISD::CondCode CCCode = cast(Op.getOperand(2))->get(); + unsigned CCOp = Opcode == ISD::SETCC ? 2 : 4; + ISD::CondCode CCCode = cast(Op.getOperand(CCOp))->get(); if (((unsigned)CCCode & 0x10U)) return true; @@ -5183,6 +5195,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, return false; case ISD::SHL: + case ISD::SRL: + case ISD::SRA: // If the max shift amount isn't in range, then the shift can create poison. return !getValidMaximumShiftAmountConstant(Op, DemandedElts); diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index cf99b5d80e13..b2f9bf89d9ec 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -282,21 +282,21 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v16, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v15 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v10, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v14 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v4 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v10, v4, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v6, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v10, v4, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 ; GFX9-O0-NEXT: v_xor_b32_e64 v1, v5, v1 @@ -312,21 +312,21 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v7 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v8 -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v11 +; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 killed $vgpr7_vgpr8 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v11 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v12 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v3 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v5, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v8, v3, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v8, vcc, v8, v5, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v3, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v7, vcc, v2, v5, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v8 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v7 +; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v7 ; GFX9-O0-NEXT: v_xor_b32_e64 v5, v5, v6 ; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v4 ; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec @@ -339,18 +339,26 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v13 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v14 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v12 ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v2 ; GFX9-O0-NEXT: v_or_b32_e64 v3, v8, v7 @@ -403,7 +411,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[12:13], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[12:13] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[12:13] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 @@ -439,7 +448,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[8:9] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[8:9] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v11 @@ -690,10 +700,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload @@ -903,14 +913,14 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(9) ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) @@ -1028,10 +1038,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll index 6ba66ccf7186..b068d87c4d6f 100644 --- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll @@ -242,130 +242,137 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0: ; %bb.0: ; %_udiv-special-cases ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-O0-NEXT: ; implicit-def: $vgpr8 : SGPR spill to VGPR lane -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v6 -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v2 -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v1 -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v0 +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v2 +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v0 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: s_waitcnt vmcnt(1) +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v2 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v6 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v7 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v9 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec -; GFX9-O0-NEXT: s_waitcnt vmcnt(1) -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v3 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: s_mov_b32 s4, 63 -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v14 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v15 -; GFX9-O0-NEXT: v_ashrrev_i64 v[12:13], s4, v[6:7] -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v11, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v8 +; GFX9-O0-NEXT: v_ashrrev_i64 v[11:12], s4, v[10:11] +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v12 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v13 -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v9 -; GFX9-O0-NEXT: v_ashrrev_i64 v[6:7], s4, v[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v15 -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v13 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v10 -; GFX9-O0-NEXT: v_mov_b32_e32 v11, v14 -; GFX9-O0-NEXT: v_xor_b32_e64 v13, v11, v12 +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v7 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, v6 +; GFX9-O0-NEXT: v_ashrrev_i64 v[15:16], s4, v[13:14] +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v12 +; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v10 +; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-O0-NEXT: v_xor_b32_e64 v13, v8, v12 ; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v5 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v10 -; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v15, v4, v12 -; GFX9-O0-NEXT: ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v16, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v7 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v4 -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v8 -; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v7, v5, v6 +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v2 +; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v10 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v12 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v16 +; GFX9-O0-NEXT: v_xor_b32_e64 v9, v8, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v15 +; GFX9-O0-NEXT: v_xor_b32_e64 v7, v7, v6 ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v4 -; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v2, v2, v6 -; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v15 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-O0-NEXT: v_xor_b32_e64 v9, v9, v3 +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: v_xor_b32_e64 v4, v4, v6 +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr1_vgpr2 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v11, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v14 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v12 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v10, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v11, v12, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v10, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v2 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 -; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec +; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v4 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v8 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v6 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v3, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v5, v6, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v4, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v3, vcc, v2, v3, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v13 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v14 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 ; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill @@ -438,7 +445,8 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[12:13], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[12:13] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[12:13] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 @@ -474,7 +482,8 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[8:9] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[8:9] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v11 @@ -589,27 +598,27 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_readlane_b32 s5, v0, 5 ; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-O0-NEXT: ; %bb.2: ; %Flow -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(6) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_5 ; GFX9-O0-NEXT: .LBB0_3: ; %Flow2 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -624,22 +633,22 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_9 ; GFX9-O0-NEXT: .LBB0_4: ; %udiv-loop-exit -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 1 ; GFX9-O0-NEXT: s_waitcnt vmcnt(2) ; GFX9-O0-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1] @@ -679,27 +688,27 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_readlane_b32 s4, v8, 6 ; GFX9-O0-NEXT: v_readlane_b32 s5, v8, 7 ; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5] -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_4 ; GFX9-O0-NEXT: .LBB0_6: ; %udiv-do-while ; GFX9-O0-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -709,30 +718,30 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: v_readlane_b32 s6, v16, 8 ; GFX9-O0-NEXT: v_readlane_b32 s7, v16, 9 -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 63 ; GFX9-O0-NEXT: s_waitcnt vmcnt(16) ; GFX9-O0-NEXT: v_lshrrev_b64 v[29:30], s4, v[2:3] @@ -872,24 +881,24 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v2 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v0 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v15 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v14 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v13 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v12 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[6:7], s[4:5] ; GFX9-O0-NEXT: v_writelane_b32 v16, s6, 4 ; GFX9-O0-NEXT: v_writelane_b32 v16, s7, 5 @@ -899,42 +908,42 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX9-O0-NEXT: s_cbranch_execnz .LBB0_6 ; GFX9-O0-NEXT: s_branch .LBB0_1 ; GFX9-O0-NEXT: .LBB0_7: ; %udiv-preheader -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] @@ -1018,12 +1027,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v13, v17 ; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v15, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 @@ -1034,30 +1043,30 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_6 ; GFX9-O0-NEXT: .LBB0_8: ; %udiv-bb1 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -1099,14 +1108,14 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v2 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v1 -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v10 -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b32 s4, 0x7f ; GFX9-O0-NEXT: v_sub_u32_e64 v3, s4, v4 ; GFX9-O0-NEXT: v_lshlrev_b64 v[5:6], v3, v[11:12] @@ -1152,12 +1161,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v3 -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v10 ; GFX9-O0-NEXT: v_or_b32_e64 v3, v3, v4 @@ -1172,18 +1181,18 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v4, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, s7 -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[6:7], exec ; GFX9-O0-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5] ; GFX9-O0-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7] @@ -1203,18 +1212,18 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 32 ; GFX9-O0-NEXT: s_waitcnt vmcnt(2) ; GFX9-O0-NEXT: v_lshrrev_b64 v[0:1], s4, v[5:6] @@ -1486,11 +1495,11 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v5 ; GFX9-O0-NEXT: ; kill: killed $vgpr4 ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll index bf7c1c00c71d..33cc8e96f663 100644 --- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll +++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll @@ -178,18 +178,18 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: pushl %edi ; X86-NEXT: pushl %esi ; X86-NEXT: subl $152, %esp -; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: movl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: sarl $31, %eax -; X86-NEXT: movl %ebp, %edx -; X86-NEXT: sarl $31, %edx +; X86-NEXT: movl %edx, %ebx +; X86-NEXT: sarl $31, %ebx ; X86-NEXT: movl %eax, %esi ; X86-NEXT: xorl %ecx, %esi -; X86-NEXT: movl %esi, %edi +; X86-NEXT: movl %esi, %ebp ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: movl %ecx, %edi ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %eax, %esi @@ -198,28 +198,29 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %eax, %ebx -; X86-NEXT: movl %ebx, (%esp) # 4-byte Spill ; X86-NEXT: sbbl %eax, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edx, %edi -; X86-NEXT: xorl %ebp, %edi -; X86-NEXT: movl %edx, %ebx -; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebx -; X86-NEXT: movl %edx, %esi -; X86-NEXT: xorl {{[0-9]+}}(%esp), %esi -; X86-NEXT: movl %edx, %ebp +; X86-NEXT: movl %edi, (%esp) # 4-byte Spill +; X86-NEXT: sbbl %eax, %ebp +; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, %esi +; X86-NEXT: xorl %edx, %esi +; X86-NEXT: movl %ebx, %edx +; X86-NEXT: xorl {{[0-9]+}}(%esp), %edx +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: xorl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %ebx, %ebp ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: subl %edx, %ebp -; X86-NEXT: sbbl %edx, %esi -; X86-NEXT: sbbl %edx, %ebx -; X86-NEXT: sbbl %edx, %edi -; X86-NEXT: xorl %eax, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %esi, %eax -; X86-NEXT: orl %edi, %eax +; X86-NEXT: subl %ebx, %ebp +; X86-NEXT: sbbl %ebx, %edi +; X86-NEXT: sbbl %ebx, %edx +; X86-NEXT: sbbl %ebx, %esi +; X86-NEXT: xorl %eax, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edi, %eax +; X86-NEXT: orl %esi, %eax ; X86-NEXT: movl %ebp, %ecx -; X86-NEXT: orl %ebx, %ecx +; X86-NEXT: orl %edx, %ecx +; X86-NEXT: movl %edx, %ebx ; X86-NEXT: orl %eax, %ecx ; X86-NEXT: sete %cl ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload @@ -230,91 +231,87 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: sete %al ; X86-NEXT: orb %cl, %al ; X86-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill -; X86-NEXT: bsrl %edi, %edx +; X86-NEXT: bsrl %esi, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: bsrl %ebx, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx -; X86-NEXT: testl %edi, %edi +; X86-NEXT: testl %esi, %esi ; X86-NEXT: cmovnel %edx, %ecx -; X86-NEXT: bsrl %esi, %edx +; X86-NEXT: bsrl %edi, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: bsrl %ebp, %ebp ; X86-NEXT: xorl $31, %ebp ; X86-NEXT: addl $32, %ebp -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: testl %esi, %esi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: testl %edi, %edi ; X86-NEXT: cmovnel %edx, %ebp ; X86-NEXT: addl $64, %ebp ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %edi, %ebx +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %esi, %ebx ; X86-NEXT: cmovnel %ecx, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: bsrl %edi, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: bsrl %ebx, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NEXT: bsrl %eax, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx -; X86-NEXT: testl %edi, %edi +; X86-NEXT: testl %ebx, %ebx ; X86-NEXT: cmovnel %edx, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: bsrl %ebx, %esi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: bsrl %edi, %esi ; X86-NEXT: xorl $31, %esi ; X86-NEXT: bsrl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: xorl $31, %edx ; X86-NEXT: addl $32, %edx -; X86-NEXT: testl %ebx, %ebx +; X86-NEXT: testl %edi, %edi ; X86-NEXT: cmovnel %esi, %edx ; X86-NEXT: addl $64, %edx ; X86-NEXT: movl %eax, %esi -; X86-NEXT: orl %edi, %esi -; X86-NEXT: movl %edi, %ebx +; X86-NEXT: orl %ebx, %esi ; X86-NEXT: cmovnel %ecx, %edx ; X86-NEXT: xorl %esi, %esi ; X86-NEXT: subl %edx, %ebp +; X86-NEXT: movl $0, %edi +; X86-NEXT: sbbl %edi, %edi ; X86-NEXT: movl $0, %edx ; X86-NEXT: sbbl %edx, %edx ; X86-NEXT: movl $0, %eax ; X86-NEXT: sbbl %eax, %eax -; X86-NEXT: movl $0, %edi -; X86-NEXT: sbbl %edi, %edi ; X86-NEXT: movl $127, %ecx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: cmpl %ebp, %ecx +; X86-NEXT: movl %edx, %ebp +; X86-NEXT: movl $0, %ecx +; X86-NEXT: sbbl %edi, %ecx ; X86-NEXT: movl $0, %ecx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %edx, %ecx ; X86-NEXT: movl $0, %ecx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx -; X86-NEXT: movl $0, %ecx -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %edi, %ecx ; X86-NEXT: setb %cl ; X86-NEXT: orb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Folded Reload -; X86-NEXT: movl %ebx, %edi -; X86-NEXT: cmovnel %esi, %edi -; X86-NEXT: movl (%esp), %edx # 4-byte Reload +; X86-NEXT: movl %ebx, %edx ; X86-NEXT: cmovnel %esi, %edx +; X86-NEXT: movl (%esp), %ebx # 4-byte Reload +; X86-NEXT: cmovnel %esi, %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: cmovnel %esi, %eax ; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: jne .LBB4_1 -; X86-NEXT: # %bb.8: # %_udiv-special-cases -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload -; X86-NEXT: xorl $127, %ebp -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: jne .LBB4_8 +; X86-NEXT: # %bb.1: # %_udiv-special-cases +; X86-NEXT: movl %edi, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: xorl $127, %edi +; X86-NEXT: orl %ebp, %edi +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: orl %ebp, %ecx -; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: je .LBB4_9 -; X86-NEXT: # %bb.5: # %udiv-bb1 +; X86-NEXT: orl %edi, %ecx +; X86-NEXT: je .LBB4_8 +; X86-NEXT: # %bb.2: # %udiv-bb1 ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload @@ -344,225 +341,224 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: shll %cl, %edx ; X86-NEXT: notb %cl ; X86-NEXT: movl 140(%esp,%edi), %eax -; X86-NEXT: movl %eax, %esi -; X86-NEXT: shrl %esi -; X86-NEXT: shrl %cl, %esi -; X86-NEXT: orl %edx, %esi -; X86-NEXT: movl %esi, %edx -; X86-NEXT: movl 136(%esp,%edi), %esi +; X86-NEXT: movl %eax, %ebx +; X86-NEXT: shrl %ebx +; X86-NEXT: shrl %cl, %ebx +; X86-NEXT: orl %edx, %ebx +; X86-NEXT: movl 136(%esp,%edi), %edx ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %esi, %eax -; X86-NEXT: shll %cl, %esi +; X86-NEXT: shldl %cl, %edx, %eax +; X86-NEXT: shll %cl, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: addl $1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: adcl $0, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: adcl $0, %edi -; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: jae .LBB4_2 +; X86-NEXT: adcl $0, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: adcl $0, %edx +; X86-NEXT: jae .LBB4_3 ; X86-NEXT: # %bb.6: -; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: xorl %edi, %edi ; X86-NEXT: xorl %ecx, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: jmp .LBB4_7 -; X86-NEXT: .LBB4_1: -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: jmp .LBB4_9 -; X86-NEXT: .LBB4_2: # %udiv-preheader -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) -; X86-NEXT: movl (%esp), %ebx # 4-byte Reload -; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: movl %ebx, {{[0-9]+}}(%esp) +; X86-NEXT: .LBB4_3: # %udiv-preheader +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) +; X86-NEXT: movl (%esp), %esi # 4-byte Reload +; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movb %bl, %ch +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movb %dl, %ch ; X86-NEXT: andb $7, %ch -; X86-NEXT: movb %bl, %cl +; X86-NEXT: movb %dl, %cl ; X86-NEXT: shrb $3, %cl ; X86-NEXT: andb $15, %cl -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movzbl %cl, %ebx -; X86-NEXT: movl 100(%esp,%ebx), %ebp -; X86-NEXT: movl %ebp, (%esp) # 4-byte Spill -; X86-NEXT: movl 96(%esp,%ebx), %edi -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, %edx +; X86-NEXT: movzbl %cl, %edx +; X86-NEXT: movl 100(%esp,%edx), %esi +; X86-NEXT: movl %esi, (%esp) # 4-byte Spill +; X86-NEXT: movl 96(%esp,%edx), %edi +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edi, %ebp ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrdl %cl, %ebp, %edx -; X86-NEXT: movl %edx, %ebp -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl 88(%esp,%ebx), %edx -; X86-NEXT: movl 92(%esp,%ebx), %ebx -; X86-NEXT: movl %ebx, %eax -; X86-NEXT: shrl %cl, %eax +; X86-NEXT: shrdl %cl, %esi, %ebp +; X86-NEXT: movl 88(%esp,%edx), %ebx +; X86-NEXT: movl 92(%esp,%edx), %esi +; X86-NEXT: movl %esi, %edx +; X86-NEXT: shrl %cl, %edx ; X86-NEXT: notb %cl ; X86-NEXT: addl %edi, %edi ; X86-NEXT: shll %cl, %edi -; X86-NEXT: orl %eax, %edi +; X86-NEXT: orl %edx, %edi ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movb %ch, %cl ; X86-NEXT: shrl %cl, (%esp) # 4-byte Folded Spill -; X86-NEXT: shrdl %cl, %ebx, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: addl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shrdl %cl, %esi, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: addl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: adcl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: adcl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: adcl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: .p2align 4, 0x90 -; X86-NEXT: .LBB4_3: # %udiv-do-while +; X86-NEXT: .LBB4_4: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebp, %edx +; X86-NEXT: movl %ebp, %esi ; X86-NEXT: shldl $1, %ebp, (%esp) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload -; X86-NEXT: shldl $1, %ebp, %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: shldl $1, %ebx, %ebp -; X86-NEXT: shldl $1, %edi, %ebx +; X86-NEXT: shldl $1, %ebp, %esi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: shldl $1, %edx, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: shldl $1, %edi, %edx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: shldl $1, %ecx, %edi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: orl %eax, %edi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: orl %ebx, %edi ; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: shldl $1, %edi, %ecx -; X86-NEXT: orl %eax, %ecx +; X86-NEXT: shldl $1, %eax, %ecx +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: shldl $1, %esi, %edi -; X86-NEXT: orl %eax, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: addl %esi, %esi -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: cmpl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: shldl $1, %ecx, %eax +; X86-NEXT: orl %ebx, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: addl %ecx, %ecx +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: sbbl %ebp, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl %edx, %ecx +; X86-NEXT: sbbl %esi, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: sbbl (%esp), %ecx # 4-byte Folded Reload ; X86-NEXT: sarl $31, %ecx -; X86-NEXT: movl %ecx, %esi -; X86-NEXT: andl $1, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ecx, %esi -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: andl $1, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload ; X86-NEXT: movl %ecx, %edi ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: subl %ecx, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: subl %ecx, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: sbbl %eax, %ebp ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %edi, %edx -; X86-NEXT: movl %edx, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: sbbl %esi, (%esp) # 4-byte Folded Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: sbbl %edi, %esi +; X86-NEXT: movl %esi, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: sbbl %ebx, (%esp) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: addl $-1, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: adcl $-1, %edi ; X86-NEXT: adcl $-1, %edx -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %edx, %eax +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: adcl $-1, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: adcl $-1, %esi +; X86-NEXT: movl %edx, %edi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %esi, %edi ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: orl %edi, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: orl %eax, %ecx -; X86-NEXT: jne .LBB4_3 -; X86-NEXT: # %bb.4: +; X86-NEXT: jne .LBB4_4 +; X86-NEXT: # %bb.5: ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: .LBB4_7: # %udiv-loop-exit ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: shldl $1, %edx, %edi -; X86-NEXT: orl %ecx, %edi -; X86-NEXT: shldl $1, %eax, %edx +; X86-NEXT: .LBB4_7: # %udiv-loop-exit +; X86-NEXT: shldl $1, %ebx, %edx ; X86-NEXT: orl %ecx, %edx +; X86-NEXT: shldl $1, %eax, %ebx +; X86-NEXT: orl %ecx, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: shldl $1, %esi, %eax ; X86-NEXT: orl %ecx, %eax ; X86-NEXT: addl %esi, %esi -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: .LBB4_9: # %udiv-end -; X86-NEXT: xorl %ebx, %edi -; X86-NEXT: xorl %ebx, %edx -; X86-NEXT: xorl %ebx, %eax -; X86-NEXT: xorl %ebx, %esi -; X86-NEXT: subl %ebx, %esi +; X86-NEXT: orl %edi, %esi +; X86-NEXT: .LBB4_8: # %udiv-end +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: xorl %ecx, %edx +; X86-NEXT: xorl %ecx, %ebx +; X86-NEXT: xorl %ecx, %eax +; X86-NEXT: xorl %ecx, %esi +; X86-NEXT: subl %ecx, %esi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %ebx, %eax +; X86-NEXT: sbbl %ecx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %ebx, %edx -; X86-NEXT: sbbl %ebx, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %esi, (%ebp) -; X86-NEXT: movl %eax, 4(%ebp) -; X86-NEXT: movl %edx, 8(%ebp) -; X86-NEXT: movl %edi, 12(%ebp) -; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: sbbl %ecx, %ebx +; X86-NEXT: sbbl %ecx, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %esi, (%ecx) +; X86-NEXT: movl %eax, 4(%ecx) +; X86-NEXT: movl %ebx, 8(%ecx) +; X86-NEXT: movl %edx, 12(%ecx) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: mull %ecx ; X86-NEXT: movl %edx, %ebx -; X86-NEXT: mull %edi -; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, %eax -; X86-NEXT: mull %edi +; X86-NEXT: mull %ecx ; X86-NEXT: movl %eax, (%esp) # 4-byte Spill -; X86-NEXT: movl %edx, %edi -; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload -; X86-NEXT: adcl $0, %ecx +; X86-NEXT: movl %edx, %ecx +; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: adcl $0, %ebx ; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: mull %esi -; X86-NEXT: addl %edi, %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: adcl %ecx, %edx -; X86-NEXT: movl %edx, %edi +; X86-NEXT: adcl %ebx, %edx +; X86-NEXT: movl %edx, %ebx ; X86-NEXT: setb %cl ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: addl %edi, %eax +; X86-NEXT: addl %ebx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movzbl %cl, %eax ; X86-NEXT: adcl %eax, %edx ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: imull %eax, %ecx -; X86-NEXT: mull %ebx +; X86-NEXT: mull %edi ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: imull {{[0-9]+}}(%esp), %ebx -; X86-NEXT: addl %edx, %ebx -; X86-NEXT: addl %ecx, %ebx +; X86-NEXT: imull {{[0-9]+}}(%esp), %edi +; X86-NEXT: addl %edx, %edi +; X86-NEXT: addl %ecx, %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: imull %esi, %ecx @@ -572,7 +568,7 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: addl %edx, %ebp ; X86-NEXT: addl %ecx, %ebp ; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: adcl %ebx, %ebp +; X86-NEXT: adcl %edi, %ebp ; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll index b212e9438e1b..c79da37988e4 100644 --- a/llvm/test/CodeGen/X86/freeze-binary.ll +++ b/llvm/test/CodeGen/X86/freeze-binary.ll @@ -459,8 +459,7 @@ define i32 @freeze_ashr(i32 %a0) nounwind { ; X64-LABEL: freeze_ashr: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: sarl $3, %eax -; X64-NEXT: sarl $3, %eax +; X64-NEXT: sarl $6, %eax ; X64-NEXT: retq %x = ashr i32 %a0, 3 %y = freeze i32 %x @@ -531,30 +530,12 @@ define i32 @freeze_ashr_outofrange(i32 %a0) nounwind { define <8 x i16> @freeze_ashr_vec(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_ashr_vec: ; X86: # %bb.0: -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psraw $1, %xmm2 -; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] -; X86-NEXT: movdqa %xmm1, %xmm3 -; X86-NEXT: pandn %xmm2, %xmm3 -; X86-NEXT: psraw $3, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: por %xmm3, %xmm0 -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psraw $3, %xmm2 -; X86-NEXT: psraw $1, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: pandn %xmm2, %xmm1 -; X86-NEXT: por %xmm1, %xmm0 +; X86-NEXT: psraw $4, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_ashr_vec: ; X64: # %bb.0: -; X64-NEXT: vpsraw $1, %xmm0, %xmm1 -; X64-NEXT: vpsraw $3, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; X64-NEXT: vpsraw $3, %xmm0, %xmm1 -; X64-NEXT: vpsraw $1, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; X64-NEXT: vpsraw $4, %xmm0, %xmm0 ; X64-NEXT: retq %x = ashr <8 x i16> %a0, %y = freeze <8 x i16> %x @@ -592,8 +573,7 @@ define i32 @freeze_lshr(i32 %a0) nounwind { ; X64-LABEL: freeze_lshr: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: shrl $2, %eax -; X64-NEXT: shrl %eax +; X64-NEXT: shrl $3, %eax ; X64-NEXT: retq %x = lshr i32 %a0, 2 %y = freeze i32 %x @@ -664,30 +644,12 @@ define i32 @freeze_lshr_outofrange(i32 %a0) nounwind { define <8 x i16> @freeze_lshr_vec(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_lshr_vec: ; X86: # %bb.0: -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psrlw $1, %xmm2 -; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] -; X86-NEXT: movdqa %xmm1, %xmm3 -; X86-NEXT: pandn %xmm2, %xmm3 -; X86-NEXT: psrlw $2, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: por %xmm3, %xmm0 -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psrlw $2, %xmm2 -; X86-NEXT: psrlw $1, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: pandn %xmm2, %xmm1 -; X86-NEXT: por %xmm1, %xmm0 +; X86-NEXT: psrlw $3, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_lshr_vec: ; X64: # %bb.0: -; X64-NEXT: vpsrlw $1, %xmm0, %xmm1 -; X64-NEXT: vpsrlw $2, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; X64-NEXT: vpsrlw $2, %xmm0, %xmm1 -; X64-NEXT: vpsrlw $1, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; X64-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X64-NEXT: retq %x = lshr <8 x i16> %a0, %y = freeze <8 x i16> %x diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll index 2fdf6ef224ca..366dad1612b4 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll @@ -684,22 +684,21 @@ define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwin ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4 ; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5 ; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4 -; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5 -; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 -; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5 ; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 ; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1 -; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5 +; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 +; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2 +; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5 -; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5 -; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512F-NEXT: vpternlogq $226, %zmm5, %zmm4, %zmm1 ; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -715,22 +714,21 @@ define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwin ; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4 ; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpminsb %ymm2, %ymm3, %ymm5 -; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm5 ; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpminsb %ymm2, %ymm3, %ymm5 +; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm5, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512VL-FALLBACK-NEXT: vpternlogq $226, %zmm5, %zmm4, %zmm1 ; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -772,20 +770,19 @@ define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounw ; AVX512F-NEXT: vpminub %ymm1, %ymm0, %ymm6 ; AVX512F-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7 ; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5 -; AVX512F-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 -; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 ; AVX512F-NEXT: vpsubb %ymm6, %ymm1, %ymm1 -; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 +; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2 +; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4 -; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512F-NEXT: vpandq %zmm6, %zmm4, %zmm4 -; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512F-NEXT: vpternlogq $184, %zmm4, %zmm5, %zmm1 ; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -803,20 +800,19 @@ define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounw ; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm6 ; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpsubb %ymm6, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm4, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512VL-FALLBACK-NEXT: vpternlogq $184, %zmm4, %zmm5, %zmm1 ; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 -- GitLab From dc7834b76c187bdf3b260c66445b750ed8d99507 Mon Sep 17 00:00:00 2001 From: Kazu Hirata Date: Sun, 28 Apr 2024 23:13:18 -0700 Subject: [PATCH 183/301] [ProfileData] Use static_assert instead of assert (NFC) Identified with misc-static-assert. --- llvm/lib/ProfileData/InstrProfWriter.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/ProfileData/InstrProfWriter.cpp b/llvm/lib/ProfileData/InstrProfWriter.cpp index e1846fcbffee..b61c59aacc0f 100644 --- a/llvm/lib/ProfileData/InstrProfWriter.cpp +++ b/llvm/lib/ProfileData/InstrProfWriter.cpp @@ -657,8 +657,8 @@ Error InstrProfWriter::writeImpl(ProfOStream &OS) { : IndexedInstrProf::ProfVersion::CurrentVersion; // The WritePrevVersion handling will either need to be removed or updated // if the version is advanced beyond 12. - assert(IndexedInstrProf::ProfVersion::CurrentVersion == - IndexedInstrProf::ProfVersion::Version12); + static_assert(IndexedInstrProf::ProfVersion::CurrentVersion == + IndexedInstrProf::ProfVersion::Version12); if (static_cast(ProfileKind & InstrProfKind::IRInstrumentation)) Header.Version |= VARIANT_MASK_IR_PROF; if (static_cast(ProfileKind & InstrProfKind::ContextSensitive)) -- GitLab From ec6c0a2b7da4a23a33de049ab9a07fd30fff56b8 Mon Sep 17 00:00:00 2001 From: WANG Rui Date: Sun, 28 Apr 2024 17:43:15 +0800 Subject: [PATCH 184/301] [LoongArch] Pre-commit tests for OptWInstrs. NFC --- llvm/test/CodeGen/LoongArch/sextw-removal.ll | 921 +++++++++++++++++++ 1 file changed, 921 insertions(+) create mode 100644 llvm/test/CodeGen/LoongArch/sextw-removal.ll diff --git a/llvm/test/CodeGen/LoongArch/sextw-removal.ll b/llvm/test/CodeGen/LoongArch/sextw-removal.ll new file mode 100644 index 000000000000..6db9c1608b3c --- /dev/null +++ b/llvm/test/CodeGen/LoongArch/sextw-removal.ll @@ -0,0 +1,921 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s --mtriple=loongarch64 | FileCheck %s --check-prefixes=CHECK + +define void @test1(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test1: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -32 +; CHECK-NEXT: st.d $ra, $sp, 24 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: move $fp, $a1 +; CHECK-NEXT: sra.w $s0, $a0, $a1 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB0_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $s0, 0 +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: sll.w $s0, $s0, $fp +; CHECK-NEXT: bnez $a0, .LBB0_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $fp, $sp, 16 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 32 +; CHECK-NEXT: ret +bb: + %i = ashr i32 %arg, %arg1 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ] + %i4 = tail call signext i32 @bar(i32 signext %i3) + %i5 = shl i32 %i3, %arg1 + %i6 = icmp eq i32 %i4, 0 + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} + +declare signext i32 @bar(i32 signext) + +define signext i32 @test2(ptr %p, i32 signext %b) nounwind { +; CHECK-LABEL: test2: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a0, $a0, 0 +; CHECK-NEXT: ori $a2, $zero, 1 +; CHECK-NEXT: sll.w $a1, $a2, $a1 +; CHECK-NEXT: andn $a0, $a0, $a1 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret + %a = load i32, ptr %p + %shl = shl i32 1, %b + %neg = xor i32 %shl, -1 + %and1 = and i32 %neg, %a + ret i32 %and1 +} + +define signext i32 @test3(ptr %p, i32 signext %b) nounwind { +; CHECK-LABEL: test3: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a0, $a0, 0 +; CHECK-NEXT: ori $a2, $zero, 1 +; CHECK-NEXT: sll.w $a1, $a2, $a1 +; CHECK-NEXT: orn $a0, $a0, $a1 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret + %a = load i32, ptr %p + %shl = shl i32 1, %b + %neg = xor i32 %shl, -1 + %and1 = or i32 %neg, %a + ret i32 %and1 +} + +define signext i32 @test4(ptr %p, i32 signext %b) nounwind { +; CHECK-LABEL: test4: +; CHECK: # %bb.0: +; CHECK-NEXT: ld.w $a0, $a0, 0 +; CHECK-NEXT: ori $a2, $zero, 1 +; CHECK-NEXT: sll.w $a1, $a2, $a1 +; CHECK-NEXT: xor $a0, $a1, $a0 +; CHECK-NEXT: nor $a0, $a0, $zero +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret + %a = load i32, ptr %p + %shl = shl i32 1, %b + %neg = xor i32 %shl, -1 + %and1 = xor i32 %neg, %a + ret i32 %and1 +} + +define void @test5(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test5: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -48 +; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s0, $sp, 24 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s1, $sp, 16 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s2, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: sra.w $a1, $a0, $a1 +; CHECK-NEXT: lu12i.w $a0, 349525 +; CHECK-NEXT: ori $fp, $a0, 1365 +; CHECK-NEXT: lu12i.w $a0, 209715 +; CHECK-NEXT: ori $s0, $a0, 819 +; CHECK-NEXT: lu12i.w $a0, 61680 +; CHECK-NEXT: ori $s1, $a0, 3855 +; CHECK-NEXT: lu12i.w $a0, 4112 +; CHECK-NEXT: ori $s2, $a0, 257 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB4_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $a1, 0 +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: srli.d $a1, $a0, 1 +; CHECK-NEXT: and $a1, $a1, $fp +; CHECK-NEXT: sub.d $a1, $a0, $a1 +; CHECK-NEXT: and $a2, $a1, $s0 +; CHECK-NEXT: srli.d $a1, $a1, 2 +; CHECK-NEXT: and $a1, $a1, $s0 +; CHECK-NEXT: add.d $a1, $a2, $a1 +; CHECK-NEXT: srli.d $a2, $a1, 4 +; CHECK-NEXT: add.d $a1, $a1, $a2 +; CHECK-NEXT: and $a1, $a1, $s1 +; CHECK-NEXT: mul.d $a1, $a1, $s2 +; CHECK-NEXT: bstrpick.d $a1, $a1, 31, 24 +; CHECK-NEXT: bnez $a0, .LBB4_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $s2, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $s1, $sp, 16 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $s0, $sp, 24 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 48 +; CHECK-NEXT: ret +bb: + %i = ashr i32 %arg, %arg1 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ] + %i4 = tail call signext i32 @bar(i32 signext %i3) + %i5 = tail call i32 @llvm.ctpop.i32(i32 %i4) + %i6 = icmp eq i32 %i4, 0 + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} + +declare i32 @llvm.ctpop.i32(i32) + +define void @test6(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test6: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -32 +; CHECK-NEXT: st.d $ra, $sp, 24 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: sra.w $fp, $a0, $a1 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB5_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $fp, 0 +; CHECK-NEXT: bl %plt(baz) +; CHECK-NEXT: bstrpick.d $s0, $a0, 31, 0 +; CHECK-NEXT: move $a0, $s0 +; CHECK-NEXT: bl %plt(__fixsfsi) +; CHECK-NEXT: move $fp, $a0 +; CHECK-NEXT: move $a0, $s0 +; CHECK-NEXT: move $a1, $zero +; CHECK-NEXT: bl %plt(__nesf2) +; CHECK-NEXT: bnez $a0, .LBB5_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $fp, $sp, 16 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 32 +; CHECK-NEXT: ret +bb: + %i = ashr i32 %arg, %arg1 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ] + %i4 = tail call float @baz(i32 signext %i3) + %i5 = fptosi float %i4 to i32 + %i6 = fcmp oeq float %i4, zeroinitializer + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} +declare float @baz(i32 signext %i3) + +define void @test7(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test7: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -48 +; CHECK-NEXT: st.d $ra, $sp, 40 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 32 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s0, $sp, 24 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s1, $sp, 16 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s2, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: sra.w $a0, $a0, $a1 +; CHECK-NEXT: lu12i.w $a1, 349525 +; CHECK-NEXT: ori $a1, $a1, 1365 +; CHECK-NEXT: lu32i.d $a1, 349525 +; CHECK-NEXT: lu52i.d $fp, $a1, 1365 +; CHECK-NEXT: lu12i.w $a1, 209715 +; CHECK-NEXT: ori $a1, $a1, 819 +; CHECK-NEXT: lu32i.d $a1, 209715 +; CHECK-NEXT: lu52i.d $s0, $a1, 819 +; CHECK-NEXT: lu12i.w $a1, 61680 +; CHECK-NEXT: ori $a1, $a1, 3855 +; CHECK-NEXT: lu32i.d $a1, -61681 +; CHECK-NEXT: lu52i.d $s1, $a1, 240 +; CHECK-NEXT: lu12i.w $a1, 4112 +; CHECK-NEXT: ori $a1, $a1, 257 +; CHECK-NEXT: lu32i.d $a1, 65793 +; CHECK-NEXT: lu52i.d $s2, $a1, 16 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB6_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: bl %plt(foo) +; CHECK-NEXT: srli.d $a1, $a0, 1 +; CHECK-NEXT: and $a1, $a1, $fp +; CHECK-NEXT: sub.d $a0, $a0, $a1 +; CHECK-NEXT: and $a1, $a0, $s0 +; CHECK-NEXT: srli.d $a0, $a0, 2 +; CHECK-NEXT: and $a0, $a0, $s0 +; CHECK-NEXT: add.d $a0, $a1, $a0 +; CHECK-NEXT: srli.d $a1, $a0, 4 +; CHECK-NEXT: add.d $a0, $a0, $a1 +; CHECK-NEXT: and $a0, $a0, $s1 +; CHECK-NEXT: mul.d $a0, $a0, $s2 +; CHECK-NEXT: srli.d $a0, $a0, 56 +; CHECK-NEXT: bnez $a0, .LBB6_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $s2, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $s1, $sp, 16 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $s0, $sp, 24 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $fp, $sp, 32 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 40 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 48 +; CHECK-NEXT: ret +bb: + %i = ashr i32 %arg, %arg1 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i6, %bb2 ] + %i4 = tail call signext i64 @foo(i32 signext %i3) + %i5 = tail call i64 @llvm.ctpop.i64(i64 %i4) + %i6 = trunc i64 %i5 to i32 + %i7 = icmp eq i32 %i6, 0 + br i1 %i7, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} + +declare i64 @llvm.ctpop.i64(i64) + +define void @test8(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test8: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill +; CHECK-NEXT: sra.w $a0, $a0, $a1 +; CHECK-NEXT: addi.w $fp, $zero, -256 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB7_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: bl %plt(foo) +; CHECK-NEXT: or $a0, $a0, $fp +; CHECK-NEXT: bnez $a0, .LBB7_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret +bb: + %i = ashr i32 %arg, %arg1 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i6, %bb2 ] + %i4 = tail call signext i64 @foo(i32 signext %i3) + %i5 = or i64 %i4, -256 + %i6 = trunc i64 %i5 to i32 + %i7 = icmp eq i32 %i6, 0 + br i1 %i7, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} + +declare i64 @foo(i32 signext) + +define void @test9(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test9: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill +; CHECK-NEXT: sra.w $a1, $a0, $a1 +; CHECK-NEXT: ori $fp, $zero, 254 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB8_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $a1, 0 +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: slti $a1, $a0, 255 +; CHECK-NEXT: blt $fp, $a0, .LBB8_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret +bb: + %i = ashr i32 %arg, %arg1 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i7, %bb2 ] + %i4 = tail call signext i32 @bar(i32 signext %i3) + %i5 = icmp slt i32 %i4, 255 + %i6 = sext i1 %i5 to i32 + %i7 = sub i32 0, %i6 + br i1 %i5, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} + +define void @test10(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test10: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill +; CHECK-NEXT: sra.w $fp, $a0, $a1 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB9_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $fp, 0 +; CHECK-NEXT: bl %plt(baz) +; CHECK-NEXT: move $fp, $a0 +; CHECK-NEXT: bstrpick.d $a0, $a0, 31, 0 +; CHECK-NEXT: move $a1, $zero +; CHECK-NEXT: bl %plt(__nesf2) +; CHECK-NEXT: bnez $a0, .LBB9_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret +bb: + %i = ashr i32 %arg, %arg1 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ] + %i4 = tail call float @baz(i32 signext %i3) + %i5 = bitcast float %i4 to i32 + %i6 = fcmp oeq float %i4, zeroinitializer + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} + +define signext i32 @test11(i64 %arg1, i64 %arg2, i64 %arg3) { +; CHECK-LABEL: test11: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi.d $a2, $a2, -1 +; CHECK-NEXT: ori $a3, $zero, 256 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB10_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: andi $a0, $a0, 1234 +; CHECK-NEXT: addi.d $a2, $a2, 1 +; CHECK-NEXT: add.d $a0, $a0, $a1 +; CHECK-NEXT: bltu $a2, $a3, .LBB10_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +entry: + br label %bb2 + +bb2: ; preds = %bb2, %entry + %i1 = phi i64 [ %arg1, %entry ], [ %i5, %bb2 ] + %i2 = phi i64 [ %arg3, %entry ], [ %i3, %bb2 ] + %i3 = add i64 %i2, 1 + %i4 = and i64 %i1, 1234 + %i5 = add i64 %i4, %arg2 + %i6 = icmp ugt i64 %i2, 255 + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + %i7 = trunc i64 %i5 to i32 + ret i32 %i7 +} + +define signext i32 @test12(i64 %arg1, i64 %arg2, i64 %arg3) { +; CHECK-LABEL: test12: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi.d $a2, $a2, -1 +; CHECK-NEXT: ori $a3, $zero, 256 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB11_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: xor $a0, $a0, $a1 +; CHECK-NEXT: mul.d $a4, $a0, $a1 +; CHECK-NEXT: add.d $a0, $a0, $a4 +; CHECK-NEXT: and $a4, $a4, $a0 +; CHECK-NEXT: addi.d $a2, $a2, 1 +; CHECK-NEXT: add.d $a0, $a4, $a1 +; CHECK-NEXT: bltu $a2, $a3, .LBB11_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: addi.w $a0, $a4, 0 +; CHECK-NEXT: ret +entry: + br label %bb2 + +bb2: ; preds = %bb2, %entry + %i1 = phi i64 [ %arg1, %entry ], [ %i6, %bb2 ] + %i2 = phi i64 [ %arg3, %entry ], [ %i3, %bb2 ] + %i3 = add i64 %i2, 1 + %i4 = xor i64 %i1, %arg2 + %i5 = mul i64 %i4, %arg2 + %i9 = add i64 %i4, %i5 + %i8 = and i64 %i5, %i9 + %i6 = add i64 %i8, %arg2 + %i7 = icmp ugt i64 %i2, 255 + br i1 %i7, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + %r = trunc i64 %i8 to i32 + ret i32 %r +} + +define signext i32 @test13(i64 %arg1, i64 %arg2, i64 %arg3) { +; CHECK-LABEL: test13: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi.d $a2, $a2, -1 +; CHECK-NEXT: ori $a3, $zero, 256 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB12_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: div.d $a0, $a0, $a1 +; CHECK-NEXT: addi.d $a2, $a2, 1 +; CHECK-NEXT: add.d $a0, $a0, $a1 +; CHECK-NEXT: bltu $a2, $a3, .LBB12_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +entry: + br label %bb2 + +bb2: ; preds = %bb2, %entry + %i1 = phi i64 [ %arg1, %entry ], [ %i5, %bb2 ] + %i2 = phi i64 [ %arg3, %entry ], [ %i3, %bb2 ] + %i3 = add i64 %i2, 1 + %i4 = sdiv i64 %i1, %arg2 + %i5 = add i64 %i4, %arg2 + %i6 = icmp ugt i64 %i2, 255 + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + %i8 = trunc i64 %i5 to i32 + ret i32 %i8 +} + + +define signext i32 @test14(i32 signext %0, i32 signext %1) { +; CHECK-LABEL: test14: +; CHECK: # %bb.0: +; CHECK-NEXT: ori $a2, $zero, 2 +; CHECK-NEXT: blt $a1, $a2, .LBB13_4 +; CHECK-NEXT: # %bb.1: # %.preheader +; CHECK-NEXT: ori $a3, $zero, 1 +; CHECK-NEXT: addi.w $a2, $zero, -1 +; CHECK-NEXT: lu32i.d $a2, 0 +; CHECK-NEXT: ori $a4, $zero, 1000 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB13_2: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a5, $a0, 0 +; CHECK-NEXT: blt $a4, $a5, .LBB13_5 +; CHECK-NEXT: # %bb.3: # in Loop: Header=BB13_2 Depth=1 +; CHECK-NEXT: add.d $a0, $a3, $a0 +; CHECK-NEXT: addi.w $a3, $a3, 1 +; CHECK-NEXT: blt $a3, $a1, .LBB13_2 +; CHECK-NEXT: .LBB13_4: +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB13_5: +; CHECK-NEXT: addi.w $a0, $a2, 0 +; CHECK-NEXT: ret + %3 = icmp sgt i32 %1, 1 + br i1 %3, label %4, label %12 + +4: ; preds = %2, %8 + %5 = phi i32 [ %10, %8 ], [ 1, %2 ] + %6 = phi i32 [ %9, %8 ], [ %0, %2 ] + %7 = icmp sgt i32 %6, 1000 + br i1 %7, label %12, label %8 + +8: ; preds = %4 + %9 = add nsw i32 %5, %6 + %10 = add nuw nsw i32 %5, 1 + %11 = icmp slt i32 %10, %1 + br i1 %11, label %4, label %12 + +12: ; preds = %8, %4, %2 + %13 = phi i32 [ %0, %2 ], [ -1, %4 ], [ %9, %8 ] + ret i32 %13 +} + +define signext i32 @test14b(i32 %0, i32 signext %1) { +; CHECK-LABEL: test14b: +; CHECK: # %bb.0: +; CHECK-NEXT: ori $a2, $zero, 2 +; CHECK-NEXT: blt $a1, $a2, .LBB14_4 +; CHECK-NEXT: # %bb.1: # %.preheader +; CHECK-NEXT: ori $a3, $zero, 1 +; CHECK-NEXT: addi.w $a2, $zero, -1 +; CHECK-NEXT: lu32i.d $a2, 0 +; CHECK-NEXT: ori $a4, $zero, 1000 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB14_2: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a5, $a0, 0 +; CHECK-NEXT: blt $a4, $a5, .LBB14_5 +; CHECK-NEXT: # %bb.3: # in Loop: Header=BB14_2 Depth=1 +; CHECK-NEXT: add.d $a0, $a3, $a0 +; CHECK-NEXT: addi.w $a3, $a3, 1 +; CHECK-NEXT: blt $a3, $a1, .LBB14_2 +; CHECK-NEXT: .LBB14_4: +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB14_5: +; CHECK-NEXT: addi.w $a0, $a2, 0 +; CHECK-NEXT: ret + %3 = icmp sgt i32 %1, 1 + br i1 %3, label %4, label %12 + +4: ; preds = %2, %8 + %5 = phi i32 [ %10, %8 ], [ 1, %2 ] + %6 = phi i32 [ %9, %8 ], [ %0, %2 ] + %7 = icmp sgt i32 %6, 1000 + br i1 %7, label %12, label %8 + +8: ; preds = %4 + %9 = add nsw i32 %5, %6 + %10 = add nuw nsw i32 %5, 1 + %11 = icmp slt i32 %10, %1 + br i1 %11, label %4, label %12 + +12: ; preds = %8, %4, %2 + %13 = phi i32 [ %0, %2 ], [ -1, %4 ], [ %9, %8 ] + ret i32 %13 +} + +define signext i32 @test14c(i32 zeroext %0, i32 signext %1) { +; CHECK-LABEL: test14c: +; CHECK: # %bb.0: +; CHECK-NEXT: ori $a2, $zero, 2 +; CHECK-NEXT: blt $a1, $a2, .LBB15_4 +; CHECK-NEXT: # %bb.1: # %.preheader +; CHECK-NEXT: ori $a3, $zero, 1 +; CHECK-NEXT: addi.w $a2, $zero, -1 +; CHECK-NEXT: lu32i.d $a2, 0 +; CHECK-NEXT: ori $a4, $zero, 1000 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB15_2: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a5, $a0, 0 +; CHECK-NEXT: blt $a4, $a5, .LBB15_5 +; CHECK-NEXT: # %bb.3: # in Loop: Header=BB15_2 Depth=1 +; CHECK-NEXT: add.d $a0, $a3, $a0 +; CHECK-NEXT: addi.w $a3, $a3, 1 +; CHECK-NEXT: blt $a3, $a1, .LBB15_2 +; CHECK-NEXT: .LBB15_4: +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB15_5: +; CHECK-NEXT: addi.w $a0, $a2, 0 +; CHECK-NEXT: ret + %3 = icmp sgt i32 %1, 1 + br i1 %3, label %4, label %12 + +4: ; preds = %2, %8 + %5 = phi i32 [ %10, %8 ], [ 1, %2 ] + %6 = phi i32 [ %9, %8 ], [ %0, %2 ] + %7 = icmp sgt i32 %6, 1000 + br i1 %7, label %12, label %8 + +8: ; preds = %4 + %9 = add nsw i32 %5, %6 + %10 = add nuw nsw i32 %5, 1 + %11 = icmp slt i32 %10, %1 + br i1 %11, label %4, label %12 + +12: ; preds = %8, %4, %2 + %13 = phi i32 [ %0, %2 ], [ -1, %4 ], [ %9, %8 ] + ret i32 %13 +} + +define signext i32 @test14d(i31 zeroext %0, i32 signext %1) { +; CHECK-LABEL: test14d: +; CHECK: # %bb.0: +; CHECK-NEXT: ori $a2, $zero, 2 +; CHECK-NEXT: blt $a1, $a2, .LBB16_4 +; CHECK-NEXT: # %bb.1: # %.preheader +; CHECK-NEXT: ori $a3, $zero, 1 +; CHECK-NEXT: addi.w $a2, $zero, -1 +; CHECK-NEXT: lu32i.d $a2, 0 +; CHECK-NEXT: ori $a4, $zero, 1000 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB16_2: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a5, $a0, 0 +; CHECK-NEXT: blt $a4, $a5, .LBB16_5 +; CHECK-NEXT: # %bb.3: # in Loop: Header=BB16_2 Depth=1 +; CHECK-NEXT: add.d $a0, $a3, $a0 +; CHECK-NEXT: addi.w $a3, $a3, 1 +; CHECK-NEXT: blt $a3, $a1, .LBB16_2 +; CHECK-NEXT: .LBB16_4: +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB16_5: +; CHECK-NEXT: addi.w $a0, $a2, 0 +; CHECK-NEXT: ret + %zext = zext i31 %0 to i32 + %3 = icmp sgt i32 %1, 1 + br i1 %3, label %4, label %12 + +4: ; preds = %2, %8 + %5 = phi i32 [ %10, %8 ], [ 1, %2 ] + %6 = phi i32 [ %9, %8 ], [ %zext, %2 ] + %7 = icmp sgt i32 %6, 1000 + br i1 %7, label %12, label %8 + +8: ; preds = %4 + %9 = add nsw i32 %5, %6 + %10 = add nuw nsw i32 %5, 1 + %11 = icmp slt i32 %10, %1 + br i1 %11, label %4, label %12 + +12: ; preds = %8, %4, %2 + %13 = phi i32 [ %zext, %2 ], [ -1, %4 ], [ %9, %8 ] + ret i32 %13 +} + +define signext i32 @test15(i64 %arg1, i64 %arg2, i64 %arg3, ptr %arg4) { +; CHECK-LABEL: test15: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: addi.d $a2, $a2, -1 +; CHECK-NEXT: ori $a4, $zero, 256 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB17_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: andi $a0, $a0, 1234 +; CHECK-NEXT: add.d $a0, $a0, $a1 +; CHECK-NEXT: addi.d $a2, $a2, 1 +; CHECK-NEXT: st.w $a0, $a3, 0 +; CHECK-NEXT: bltu $a2, $a4, .LBB17_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +entry: + br label %bb2 + +bb2: ; preds = %bb2, %entry + %i1 = phi i64 [ %arg1, %entry ], [ %i5, %bb2 ] + %i2 = phi i64 [ %arg3, %entry ], [ %i3, %bb2 ] + %i3 = add i64 %i2, 1 + %i4 = and i64 %i1, 1234 + %i5 = add i64 %i4, %arg2 + %i8 = trunc i64 %i5 to i32 + store i32 %i8, ptr %arg4 + %i6 = icmp ugt i64 %i2, 255 + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + %i7 = trunc i64 %i5 to i32 + ret i32 %i7 +} + +define signext i32 @bug(i32 signext %x) { +; CHECK-LABEL: bug: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: beqz $a0, .LBB18_2 +; CHECK-NEXT: # %bb.1: # %if.end +; CHECK-NEXT: bstrpick.d $a1, $a0, 31, 16 +; CHECK-NEXT: sltui $a1, $a1, 1 +; CHECK-NEXT: slli.d $a2, $a0, 16 +; CHECK-NEXT: masknez $a0, $a0, $a1 +; CHECK-NEXT: maskeqz $a2, $a2, $a1 +; CHECK-NEXT: or $a0, $a2, $a0 +; CHECK-NEXT: ori $a2, $zero, 32 +; CHECK-NEXT: masknez $a2, $a2, $a1 +; CHECK-NEXT: ori $a3, $zero, 16 +; CHECK-NEXT: maskeqz $a1, $a3, $a1 +; CHECK-NEXT: or $a1, $a1, $a2 +; CHECK-NEXT: bstrpick.d $a2, $a0, 31, 24 +; CHECK-NEXT: sltui $a2, $a2, 1 +; CHECK-NEXT: slli.d $a3, $a0, 8 +; CHECK-NEXT: addi.d $a4, $a1, -8 +; CHECK-NEXT: masknez $a0, $a0, $a2 +; CHECK-NEXT: maskeqz $a3, $a3, $a2 +; CHECK-NEXT: or $a0, $a3, $a0 +; CHECK-NEXT: masknez $a1, $a1, $a2 +; CHECK-NEXT: maskeqz $a2, $a4, $a2 +; CHECK-NEXT: or $a1, $a2, $a1 +; CHECK-NEXT: bstrpick.d $a2, $a0, 31, 28 +; CHECK-NEXT: sltui $a2, $a2, 1 +; CHECK-NEXT: slli.d $a3, $a0, 4 +; CHECK-NEXT: addi.d $a4, $a1, -4 +; CHECK-NEXT: masknez $a0, $a0, $a2 +; CHECK-NEXT: maskeqz $a3, $a3, $a2 +; CHECK-NEXT: or $a0, $a3, $a0 +; CHECK-NEXT: masknez $a1, $a1, $a2 +; CHECK-NEXT: maskeqz $a2, $a4, $a2 +; CHECK-NEXT: or $a1, $a2, $a1 +; CHECK-NEXT: bstrpick.d $a2, $a0, 31, 30 +; CHECK-NEXT: sltui $a2, $a2, 1 +; CHECK-NEXT: slli.d $a3, $a0, 2 +; CHECK-NEXT: addi.d $a4, $a1, -2 +; CHECK-NEXT: masknez $a0, $a0, $a2 +; CHECK-NEXT: maskeqz $a3, $a3, $a2 +; CHECK-NEXT: or $a0, $a3, $a0 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: masknez $a1, $a1, $a2 +; CHECK-NEXT: maskeqz $a2, $a4, $a2 +; CHECK-NEXT: or $a1, $a2, $a1 +; CHECK-NEXT: srai.d $a0, $a0, 31 +; CHECK-NEXT: nor $a0, $a0, $zero +; CHECK-NEXT: add.d $a0, $a1, $a0 +; CHECK-NEXT: addi.w $a0, $a0, 0 +; CHECK-NEXT: ret +; CHECK-NEXT: .LBB18_2: +; CHECK-NEXT: addi.w $a0, $zero, 0 +; CHECK-NEXT: ret +entry: + %tobool.not = icmp eq i32 %x, 0 + br i1 %tobool.not, label %cleanup, label %if.end + +if.end: ; preds = %entry + %tobool1.not = icmp ult i32 %x, 65536 + %shl = shl i32 %x, 16 + %spec.select = select i1 %tobool1.not, i32 %shl, i32 %x + %spec.select43 = select i1 %tobool1.not, i32 16, i32 32 + %tobool5.not = icmp ult i32 %spec.select, 16777216 + %shl7 = shl i32 %spec.select, 8 + %sub8 = add nsw i32 %spec.select43, -8 + %x.addr.1 = select i1 %tobool5.not, i32 %shl7, i32 %spec.select + %r.1 = select i1 %tobool5.not, i32 %sub8, i32 %spec.select43 + %tobool11.not = icmp ult i32 %x.addr.1, 268435456 + %shl13 = shl i32 %x.addr.1, 4 + %sub14 = add nsw i32 %r.1, -4 + %x.addr.2 = select i1 %tobool11.not, i32 %shl13, i32 %x.addr.1 + %r.2 = select i1 %tobool11.not, i32 %sub14, i32 %r.1 + %tobool17.not = icmp ult i32 %x.addr.2, 1073741824 + %shl19 = shl i32 %x.addr.2, 2 + %sub20 = add nsw i32 %r.2, -2 + %x.addr.3 = select i1 %tobool17.not, i32 %shl19, i32 %x.addr.2 + %r.3 = select i1 %tobool17.not, i32 %sub20, i32 %r.2 + %x.addr.3.lobit = ashr i32 %x.addr.3, 31 + %x.addr.3.lobit.not = xor i32 %x.addr.3.lobit, -1 + %r.4 = add nsw i32 %r.3, %x.addr.3.lobit.not + br label %cleanup + +cleanup: ; preds = %entry, %if.end + %retval.0 = phi i32 [ %r.4, %if.end ], [ 0, %entry ] + ret i32 %retval.0 +} + +define void @test16(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test16: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -32 +; CHECK-NEXT: st.d $ra, $sp, 24 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: move $fp, $a1 +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: move $s0, $a0 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB19_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $s0, 0 +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: sll.w $s0, $s0, $fp +; CHECK-NEXT: bnez $a0, .LBB19_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $fp, $sp, 16 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 32 +; CHECK-NEXT: ret +bb: + %i = call signext i32 @bar(i32 signext %arg) + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %i, %bb ], [ %i5, %bb2 ] + %i4 = tail call signext i32 @bar(i32 signext %i3) + %i5 = shl i32 %i3, %arg1 + %i6 = icmp eq i32 %i4, 0 + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} + +define void @test17(i32 signext %arg, i32 signext %arg1) nounwind { +; CHECK-LABEL: test17: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -32 +; CHECK-NEXT: st.d $ra, $sp, 24 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 16 # 8-byte Folded Spill +; CHECK-NEXT: st.d $s0, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: move $fp, $a1 +; CHECK-NEXT: bl %plt(bat) +; CHECK-NEXT: move $s0, $a0 +; CHECK-NEXT: .p2align 4, , 16 +; CHECK-NEXT: .LBB20_1: # %bb2 +; CHECK-NEXT: # =>This Inner Loop Header: Depth=1 +; CHECK-NEXT: addi.w $a0, $s0, 0 +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: sll.w $s0, $s0, $fp +; CHECK-NEXT: bnez $a0, .LBB20_1 +; CHECK-NEXT: # %bb.2: # %bb7 +; CHECK-NEXT: ld.d $s0, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $fp, $sp, 16 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 24 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 32 +; CHECK-NEXT: ret +bb: + %i = call zeroext i16 @bat(i32 signext %arg) + %zext = zext i16 %i to i32 + br label %bb2 + +bb2: ; preds = %bb2, %bb + %i3 = phi i32 [ %zext, %bb ], [ %i5, %bb2 ] + %i4 = tail call signext i32 @bar(i32 signext %i3) + %i5 = shl i32 %i3, %arg1 + %i6 = icmp eq i32 %i4, 0 + br i1 %i6, label %bb7, label %bb2 + +bb7: ; preds = %bb2 + ret void +} +declare zeroext i16 @bat(i32 signext) + +define signext i32 @sextw_sh2add(i1 zeroext %0, ptr %1, i32 signext %2, i32 signext %3, i32 signext %4) { +; CHECK-LABEL: sextw_sh2add: +; CHECK: # %bb.0: +; CHECK-NEXT: alsl.d $a2, $a2, $a3, 2 +; CHECK-NEXT: beqz $a0, .LBB21_2 +; CHECK-NEXT: # %bb.1: +; CHECK-NEXT: st.w $a2, $a1, 0 +; CHECK-NEXT: .LBB21_2: +; CHECK-NEXT: add.w $a0, $a2, $a4 +; CHECK-NEXT: ret + %6 = shl i32 %2, 2 + %7 = add i32 %6, %3 + br i1 %0, label %8, label %9 + +8: ; preds = %5 + store i32 %7, ptr %1, align 4 + br label %9 + +9: ; preds = %5, %8 + %10 = add i32 %7, %4 + ret i32 %10 +} + +define signext i32 @test19(i64 %arg, i1 zeroext %c1, i1 zeroext %c2, ptr %p) nounwind { +; CHECK-LABEL: test19: +; CHECK: # %bb.0: # %bb +; CHECK-NEXT: addi.d $sp, $sp, -16 +; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill +; CHECK-NEXT: st.d $fp, $sp, 0 # 8-byte Folded Spill +; CHECK-NEXT: ori $a0, $zero, 35 +; CHECK-NEXT: lu32i.d $a0, 1 +; CHECK-NEXT: maskeqz $fp, $a0, $a1 +; CHECK-NEXT: st.d $fp, $a3, 0 +; CHECK-NEXT: beqz $a2, .LBB22_2 +; CHECK-NEXT: # %bb.1: # %bb2 +; CHECK-NEXT: move $a0, $zero +; CHECK-NEXT: bl %plt(bar) +; CHECK-NEXT: move $fp, $a0 +; CHECK-NEXT: .LBB22_2: # %bb7 +; CHECK-NEXT: bl %plt(side_effect) +; CHECK-NEXT: addi.w $a0, $fp, 0 +; CHECK-NEXT: ld.d $fp, $sp, 0 # 8-byte Folded Reload +; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload +; CHECK-NEXT: addi.d $sp, $sp, 16 +; CHECK-NEXT: ret +bb: + %sel = select i1 %c1, i64 4294967331, i64 0 + store i64 %sel, ptr %p, align 8 + br i1 %c2, label %bb2, label %bb7 + +bb2: ; preds = %bb2, %bb + %i4 = call signext i32 @bar(i32 0) + %i4.sext = sext i32 %i4 to i64 + br label %bb7 + +bb7: ; preds = %bb2 + %phi = phi i64 [ %sel, %bb ], [ %i4.sext, %bb2 ] + %trunc = trunc i64 %phi to i32 + call void @side_effect() + ret i32 %trunc +} + + declare void @side_effect(i64) -- GitLab From 66274eb9f7e7fc4b023343476c4d066e4413180a Mon Sep 17 00:00:00 2001 From: Tim Creech Date: Mon, 29 Apr 2024 02:54:14 -0400 Subject: [PATCH 185/301] Improve documented sampling profiler steps to best known methods (#88438) 1. Add `-fdebug-info-for-profiling -funique-internal-linkage-names`, which improve the usefulness of debug info for profiling. 2. Recommend the use of `br_inst_retired.near_taken:uppp`, which provides the most precise results on supporting hardware. Mention `branches:u` as a more portable backup. Both should portray execution counts better than the default event (`cycles`) and have a better chance of working as an unprivileged user due to the `:u` modifier. --- clang/docs/UsersManual.rst | 71 +++++++++++++++++++++++++++++--------- 1 file changed, 55 insertions(+), 16 deletions(-) diff --git a/clang/docs/UsersManual.rst b/clang/docs/UsersManual.rst index d0326f01d251..a7fc7ec87a16 100644 --- a/clang/docs/UsersManual.rst +++ b/clang/docs/UsersManual.rst @@ -2319,6 +2319,8 @@ are listed below. on ELF targets when using the integrated assembler. This flag currently only has an effect on ELF targets. +.. _funique_internal_linkage_names: + .. option:: -f[no]-unique-internal-linkage-names Controls whether Clang emits a unique (best-effort) symbol name for internal @@ -2448,27 +2450,41 @@ usual build cycle when using sample profilers for optimization: usual build flags that you always build your application with. The only requirement is that DWARF debug info including source line information is generated. This DWARF information is important for the profiler to be able - to map instructions back to source line locations. + to map instructions back to source line locations. The usefulness of this + DWARF information can be improved with the ``-fdebug-info-for-profiling`` + and ``-funique-internal-linkage-names`` options. - On Linux, ``-g`` or just ``-gline-tables-only`` is sufficient: + On Linux: .. code-block:: console - $ clang++ -O2 -gline-tables-only code.cc -o code + $ clang++ -O2 -gline-tables-only \ + -fdebug-info-for-profiling -funique-internal-linkage-names \ + code.cc -o code While MSVC-style targets default to CodeView debug information, DWARF debug information is required to generate source-level LLVM profiles. Use ``-gdwarf`` to include DWARF debug information: - .. code-block:: console + .. code-block:: winbatch + + > clang-cl /O2 -gdwarf -gline-tables-only ^ + /clang:-fdebug-info-for-profiling /clang:-funique-internal-linkage-names ^ + code.cc /Fe:code /fuse-ld=lld /link /debug:dwarf + +.. note:: - $ clang-cl -O2 -gdwarf -gline-tables-only coff-profile.cpp -fuse-ld=lld -link -debug:dwarf + :ref:`-funique-internal-linkage-names ` + generates unique names based on given command-line source file paths. If + your build system uses absolute source paths and these paths may change + between steps 1 and 4, then the uniqued function names may change and result + in unused profile data. Consider omitting this option in such cases. 2. Run the executable under a sampling profiler. The specific profiler you use does not really matter, as long as its output can be converted into the format that the LLVM optimizer understands. - Two such profilers are the the Linux Perf profiler + Two such profilers are the Linux Perf profiler (https://perf.wiki.kernel.org/) and Intel's Sampling Enabling Product (SEP), available as part of `Intel VTune `_. @@ -2482,7 +2498,9 @@ usual build cycle when using sample profilers for optimization: .. code-block:: console - $ perf record -b ./code + $ perf record -b -e BR_INST_RETIRED.NEAR_TAKEN:uppp ./code + + If the event above is unavailable, ``branches:u`` is probably next-best. Note the use of the ``-b`` flag. This tells Perf to use the Last Branch Record (LBR) to record call chains. While this is not strictly required, @@ -2532,21 +2550,42 @@ usual build cycle when using sample profilers for optimization: that executes faster than the original one. Note that you are not required to build the code with the exact same arguments that you used in the first step. The only requirement is that you build the code - with ``-gline-tables-only`` and ``-fprofile-sample-use``. + with the same debug info options and ``-fprofile-sample-use``. + + On Linux: .. code-block:: console - $ clang++ -O2 -gline-tables-only -fprofile-sample-use=code.prof code.cc -o code + $ clang++ -O2 -gline-tables-only \ + -fdebug-info-for-profiling -funique-internal-linkage-names \ + -fprofile-sample-use=code.prof code.cc -o code - [OPTIONAL] Sampling-based profiles can have inaccuracies or missing block/ - edge counters. The profile inference algorithm (profi) can be used to infer - missing blocks and edge counts, and improve the quality of profile data. - Enable it with ``-fsample-profile-use-profi``. + On Windows: - .. code-block:: console + .. code-block:: winbatch + + > clang-cl /O2 -gdwarf -gline-tables-only ^ + /clang:-fdebug-info-for-profiling /clang:-funique-internal-linkage-names ^ + /fprofile-sample-use=code.prof code.cc /Fe:code /fuse-ld=lld /link /debug:dwarf + + [OPTIONAL] Sampling-based profiles can have inaccuracies or missing block/ + edge counters. The profile inference algorithm (profi) can be used to infer + missing blocks and edge counts, and improve the quality of profile data. + Enable it with ``-fsample-profile-use-profi``. For example, on Linux: + + .. code-block:: console + + $ clang++ -fsample-profile-use-profi -O2 -gline-tables-only \ + -fdebug-info-for-profiling -funique-internal-linkage-names \ + -fprofile-sample-use=code.prof code.cc -o code + + On Windows: + + .. code-block:: winbatch - $ clang++ -O2 -gline-tables-only -fprofile-sample-use=code.prof \ - -fsample-profile-use-profi code.cc -o code + > clang-cl /clang:-fsample-profile-use-profi /O2 -gdwarf -gline-tables-only ^ + /clang:-fdebug-info-for-profiling /clang:-funique-internal-linkage-names ^ + /fprofile-sample-use=code.prof code.cc /Fe:code /fuse-ld=lld /link /debug:dwarf Sample Profile Formats """""""""""""""""""""" -- GitLab From e2b8af7e149c38e3b7ab0d25f86792fcbdd06507 Mon Sep 17 00:00:00 2001 From: Luke Lau Date: Mon, 29 Apr 2024 15:08:38 +0800 Subject: [PATCH 186/301] [RISCV] Don't use MachineInstr::isIdenticalTo in hasSameAVL (#90431) MachineInstr::isIdenticalTo compares that the operands and flags are the same IIUC, but I think we actually want to check that it's the same MachineInstr * with respect to position in the block etc. --- llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp index b5fd508fa77d..b27e1dd258eb 100644 --- a/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp +++ b/llvm/lib/Target/RISCV/RISCVInsertVSETVLI.cpp @@ -568,8 +568,8 @@ public: bool hasSameAVL(const VSETVLIInfo &Other) const { if (hasAVLReg() && Other.hasAVLReg()) - return getAVLDefMI().isIdenticalTo(Other.getAVLDefMI()) && - getAVLReg() == Other.getAVLReg(); + return AVLRegDef.DefMI == Other.AVLRegDef.DefMI && + AVLRegDef.DefReg == Other.AVLRegDef.DefReg; if (hasAVLImm() && Other.hasAVLImm()) return getAVLImm() == Other.getAVLImm(); -- GitLab From 4a8f2f2e1aab027a559c71d4e055db3205ec2e32 Mon Sep 17 00:00:00 2001 From: Qiu Chaofan Date: Mon, 29 Apr 2024 15:09:54 +0800 Subject: [PATCH 187/301] [Legalizer] Expand fmaximum and fminimum (#67301) According to langref, llvm.maximum/minimum has -0.0 < +0.0 semantics and propagates NaN. Expand the nodes on targets not supporting the operation, by adding extra check for NaN and using is_fpclass to check zero signs. --- llvm/include/llvm/CodeGen/TargetLowering.h | 3 + llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp | 6 + .../SelectionDAG/LegalizeVectorOps.cpp | 7 + .../CodeGen/SelectionDAG/TargetLowering.cpp | 58 ++ llvm/lib/Target/ARM/ARMISelLowering.cpp | 14 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 11 +- .../CodeGen/ARM/minnum-maxnum-intrinsics.ll | 28 +- .../CodeGen/PowerPC/fminimum-fmaximum-f128.ll | 97 ++ .../test/CodeGen/PowerPC/fminimum-fmaximum.ll | 847 ++++++++++++++++++ 9 files changed, 1040 insertions(+), 31 deletions(-) create mode 100644 llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll create mode 100644 llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 2dd978c7b584..6b8090b09b04 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -5238,6 +5238,9 @@ public: /// Expand fminnum/fmaxnum into fminnum_ieee/fmaxnum_ieee with quieted inputs. SDValue expandFMINNUM_FMAXNUM(SDNode *N, SelectionDAG &DAG) const; + /// Expand fminimum/fmaximum into multiple comparison with selects. + SDValue expandFMINIMUM_FMAXIMUM(SDNode *N, SelectionDAG &DAG) const; + /// Expand FP_TO_[US]INT_SAT into FP_TO_[US]INT and selects or min/max. /// \param N Node to expand /// \returns The expansion result diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp index c381870ae5f4..46e54b5366d6 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp @@ -3556,6 +3556,12 @@ bool SelectionDAGLegalize::ExpandNode(SDNode *Node) { Results.push_back(Expanded); break; } + case ISD::FMINIMUM: + case ISD::FMAXIMUM: { + if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(Node, DAG)) + Results.push_back(Expanded); + break; + } case ISD::FSIN: case ISD::FCOS: { EVT VT = Node->getValueType(0); diff --git a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp index 1de43a4f60e3..8f87ee8e0939 100644 --- a/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp @@ -1049,6 +1049,13 @@ void VectorLegalizer::Expand(SDNode *Node, SmallVectorImpl &Results) { return; } break; + case ISD::FMINIMUM: + case ISD::FMAXIMUM: + if (SDValue Expanded = TLI.expandFMINIMUM_FMAXIMUM(Node, DAG)) { + Results.push_back(Expanded); + return; + } + break; case ISD::SMIN: case ISD::SMAX: case ISD::UMIN: diff --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp index c938b3996be3..cdc1227fd572 100644 --- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp @@ -8381,6 +8381,64 @@ SDValue TargetLowering::expandFMINNUM_FMAXNUM(SDNode *Node, return SDValue(); } +SDValue TargetLowering::expandFMINIMUM_FMAXIMUM(SDNode *N, + SelectionDAG &DAG) const { + SDLoc DL(N); + SDValue LHS = N->getOperand(0); + SDValue RHS = N->getOperand(1); + unsigned Opc = N->getOpcode(); + EVT VT = N->getValueType(0); + EVT CCVT = getSetCCResultType(DAG.getDataLayout(), *DAG.getContext(), VT); + bool IsMax = Opc == ISD::FMAXIMUM; + + if (VT.isVector() && + isOperationLegalOrCustomOrPromote(Opc, VT.getScalarType())) + return SDValue(); + + // First, implement comparison not propagating NaN. If no native fmin or fmax + // available, use plain select with setcc instead. + SDValue MinMax; + unsigned CompOpcIeee = IsMax ? ISD::FMAXNUM_IEEE : ISD::FMINNUM_IEEE; + unsigned CompOpc = IsMax ? ISD::FMAXNUM : ISD::FMINNUM; + if (isOperationLegalOrCustom(CompOpcIeee, VT)) { + MinMax = DAG.getNode(CompOpcIeee, DL, VT, LHS, RHS); + } else if (isOperationLegalOrCustom(CompOpc, VT)) { + MinMax = DAG.getNode(CompOpc, DL, VT, LHS, RHS); + } else { + // NaN (if exists) will be propagated later, so orderness doesn't matter. + SDValue Compare = + DAG.getSetCC(DL, CCVT, LHS, RHS, IsMax ? ISD::SETGT : ISD::SETLT); + MinMax = DAG.getSelect(DL, VT, Compare, LHS, RHS); + } + + // Propagate any NaN of both operands + if (!N->getFlags().hasNoNaNs() && + (!DAG.isKnownNeverNaN(RHS) || !DAG.isKnownNeverNaN(LHS))) { + ConstantFP *FPNaN = ConstantFP::get( + *DAG.getContext(), APFloat::getNaN(DAG.EVTToAPFloatSemantics(VT))); + MinMax = DAG.getSelect(DL, VT, DAG.getSetCC(DL, CCVT, LHS, RHS, ISD::SETUO), + DAG.getConstantFP(*FPNaN, DL, VT), MinMax); + } + + // fminimum/fmaximum requires -0.0 less than +0.0 + if (!N->getFlags().hasNoSignedZeros() && !DAG.isKnownNeverZeroFloat(RHS) && + !DAG.isKnownNeverZeroFloat(LHS)) { + SDValue IsZero = DAG.getSetCC(DL, CCVT, MinMax, + DAG.getConstantFP(0.0, DL, VT), ISD::SETEQ); + SDValue TestZero = + DAG.getTargetConstant(IsMax ? fcPosZero : fcNegZero, DL, MVT::i32); + SDValue LCmp = DAG.getSelect( + DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, LHS, TestZero), LHS, + MinMax); + SDValue RCmp = DAG.getSelect( + DL, VT, DAG.getNode(ISD::IS_FPCLASS, DL, CCVT, RHS, TestZero), RHS, + LCmp); + MinMax = DAG.getSelect(DL, VT, IsZero, RCmp, MinMax); + } + + return MinMax; +} + /// Returns a true value if if this FPClassTest can be performed with an ordered /// fcmp to 0, and a false value if it's an unordered fcmp to 0. Returns /// std::nullopt if it cannot be performed as a compare with 0. diff --git a/llvm/lib/Target/ARM/ARMISelLowering.cpp b/llvm/lib/Target/ARM/ARMISelLowering.cpp index d0e9f61c0bd1..f67a68acbf23 100644 --- a/llvm/lib/Target/ARM/ARMISelLowering.cpp +++ b/llvm/lib/Target/ARM/ARMISelLowering.cpp @@ -1555,15 +1555,11 @@ ARMTargetLowering::ARMTargetLowering(const TargetMachine &TM, if (Subtarget->hasNEON()) { // vmin and vmax aren't available in a scalar form, so we can use - // a NEON instruction with an undef lane instead. This has a performance - // penalty on some cores, so we don't do this unless we have been - // asked to by the core tuning model. - if (Subtarget->useNEONForSinglePrecisionFP()) { - setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); - setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal); - setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); - setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal); - } + // a NEON instruction with an undef lane instead. + setOperationAction(ISD::FMINIMUM, MVT::f32, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f32, Legal); + setOperationAction(ISD::FMINIMUM, MVT::f16, Legal); + setOperationAction(ISD::FMAXIMUM, MVT::f16, Legal); setOperationAction(ISD::FMINIMUM, MVT::v2f32, Legal); setOperationAction(ISD::FMAXIMUM, MVT::v2f32, Legal); setOperationAction(ISD::FMINIMUM, MVT::v4f32, Legal); diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index 3ab9e7d69105..ebc2d04e9371 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -524,8 +524,8 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, if (Subtarget.is64Bit()) setOperationAction(ISD::FPOWI, MVT::i32, Custom); - if (!Subtarget.hasStdExtZfa()) - setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f16, Custom); + setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f16, + Subtarget.hasStdExtZfa() ? Legal : Custom); } if (Subtarget.hasStdExtFOrZfinx()) { @@ -548,10 +548,12 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, setOperationAction(ISD::FP_TO_FP16, MVT::f32, Custom); setOperationAction(ISD::FP16_TO_FP, MVT::f32, Custom); - if (Subtarget.hasStdExtZfa()) + if (Subtarget.hasStdExtZfa()) { setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal); - else + setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f32, Legal); + } else { setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f32, Custom); + } } if (Subtarget.hasStdExtFOrZfinx() && Subtarget.is64Bit()) @@ -566,6 +568,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM, if (Subtarget.hasStdExtZfa()) { setOperationAction(FPRndMode, MVT::f64, Legal); setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal); + setOperationAction({ISD::FMAXIMUM, ISD::FMINIMUM}, MVT::f64, Legal); } else { if (Subtarget.is64Bit()) setOperationAction(FPRndMode, MVT::f64, Custom); diff --git a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll index be741f536ac7..528bfe041173 100644 --- a/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll +++ b/llvm/test/CodeGen/ARM/minnum-maxnum-intrinsics.ll @@ -46,12 +46,10 @@ define float @fminnum32_intrinsic(float %x, float %y) { define float @fminnum32_nsz_intrinsic(float %x, float %y) { ; ARMV7-LABEL: fminnum32_nsz_intrinsic: ; ARMV7: @ %bb.0: -; ARMV7-NEXT: vmov s0, r0 -; ARMV7-NEXT: vmov s2, r1 -; ARMV7-NEXT: vcmp.f32 s0, s2 -; ARMV7-NEXT: vmrs APSR_nzcv, fpscr -; ARMV7-NEXT: vmovlt.f32 s2, s0 -; ARMV7-NEXT: vmov r0, s2 +; ARMV7-NEXT: vmov s0, r1 +; ARMV7-NEXT: vmov s2, r0 +; ARMV7-NEXT: vmin.f32 d0, d1, d0 +; ARMV7-NEXT: vmov r0, s0 ; ARMV7-NEXT: bx lr ; ; ARMV8-LABEL: fminnum32_nsz_intrinsic: @@ -78,9 +76,7 @@ define float @fminnum32_non_zero_intrinsic(float %x) { ; ARMV7: @ %bb.0: ; ARMV7-NEXT: vmov.f32 s0, #-1.000000e+00 ; ARMV7-NEXT: vmov s2, r0 -; ARMV7-NEXT: vcmp.f32 s2, s0 -; ARMV7-NEXT: vmrs APSR_nzcv, fpscr -; ARMV7-NEXT: vmovlt.f32 s0, s2 +; ARMV7-NEXT: vmin.f32 d0, d1, d0 ; ARMV7-NEXT: vmov r0, s0 ; ARMV7-NEXT: bx lr ; @@ -136,12 +132,10 @@ define float @fmaxnum32_intrinsic(float %x, float %y) { define float @fmaxnum32_nsz_intrinsic(float %x, float %y) { ; ARMV7-LABEL: fmaxnum32_nsz_intrinsic: ; ARMV7: @ %bb.0: -; ARMV7-NEXT: vmov s0, r0 -; ARMV7-NEXT: vmov s2, r1 -; ARMV7-NEXT: vcmp.f32 s0, s2 -; ARMV7-NEXT: vmrs APSR_nzcv, fpscr -; ARMV7-NEXT: vmovgt.f32 s2, s0 -; ARMV7-NEXT: vmov r0, s2 +; ARMV7-NEXT: vmov s0, r1 +; ARMV7-NEXT: vmov s2, r0 +; ARMV7-NEXT: vmax.f32 d0, d1, d0 +; ARMV7-NEXT: vmov r0, s0 ; ARMV7-NEXT: bx lr ; ; ARMV8-LABEL: fmaxnum32_nsz_intrinsic: @@ -210,9 +204,7 @@ define float @fmaxnum32_non_zero_intrinsic(float %x) { ; ARMV7: @ %bb.0: ; ARMV7-NEXT: vmov.f32 s0, #1.000000e+00 ; ARMV7-NEXT: vmov s2, r0 -; ARMV7-NEXT: vcmp.f32 s2, s0 -; ARMV7-NEXT: vmrs APSR_nzcv, fpscr -; ARMV7-NEXT: vmovgt.f32 s0, s2 +; ARMV7-NEXT: vmax.f32 d0, d1, d0 ; ARMV7-NEXT: vmov r0, s0 ; ARMV7-NEXT: bx lr ; diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll new file mode 100644 index 000000000000..6d9eb1337682 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum-f128.ll @@ -0,0 +1,97 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr9 < %s | FileCheck %s + +define fp128 @f128_minimum(fp128 %a, fp128 %b) { +; CHECK-LABEL: f128_minimum: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xscmpuqp 0, 2, 3 +; CHECK-NEXT: vmr 4, 2 +; CHECK-NEXT: bge 0, .LBB0_8 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: bun 0, .LBB0_9 +; CHECK-NEXT: .LBB0_2: # %entry +; CHECK-NEXT: xststdcqp 0, 2, 4 +; CHECK-NEXT: bc 4, 2, .LBB0_10 +; CHECK-NEXT: .LBB0_3: # %entry +; CHECK-NEXT: xststdcqp 0, 3, 4 +; CHECK-NEXT: bc 12, 2, .LBB0_5 +; CHECK-NEXT: .LBB0_4: # %entry +; CHECK-NEXT: vmr 3, 2 +; CHECK-NEXT: .LBB0_5: # %entry +; CHECK-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI0_1@toc@l +; CHECK-NEXT: lxv 34, 0(3) +; CHECK-NEXT: xscmpuqp 0, 4, 2 +; CHECK-NEXT: beq 0, .LBB0_7 +; CHECK-NEXT: # %bb.6: # %entry +; CHECK-NEXT: vmr 3, 4 +; CHECK-NEXT: .LBB0_7: # %entry +; CHECK-NEXT: vmr 2, 3 +; CHECK-NEXT: blr +; CHECK-NEXT: .LBB0_8: # %entry +; CHECK-NEXT: vmr 4, 3 +; CHECK-NEXT: bnu 0, .LBB0_2 +; CHECK-NEXT: .LBB0_9: +; CHECK-NEXT: addis 3, 2, .LCPI0_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI0_0@toc@l +; CHECK-NEXT: lxv 36, 0(3) +; CHECK-NEXT: xststdcqp 0, 2, 4 +; CHECK-NEXT: bc 12, 2, .LBB0_3 +; CHECK-NEXT: .LBB0_10: # %entry +; CHECK-NEXT: vmr 2, 4 +; CHECK-NEXT: xststdcqp 0, 3, 4 +; CHECK-NEXT: bc 4, 2, .LBB0_4 +; CHECK-NEXT: b .LBB0_5 +entry: + %m = call fp128 @llvm.minimum.f128(fp128 %a, fp128 %b) + ret fp128 %m +} + +define fp128 @f128_maximum(fp128 %a, fp128 %b) { +; CHECK-LABEL: f128_maximum: +; CHECK: # %bb.0: # %entry +; CHECK-NEXT: xscmpuqp 0, 2, 3 +; CHECK-NEXT: vmr 4, 2 +; CHECK-NEXT: ble 0, .LBB1_8 +; CHECK-NEXT: # %bb.1: # %entry +; CHECK-NEXT: bun 0, .LBB1_9 +; CHECK-NEXT: .LBB1_2: # %entry +; CHECK-NEXT: xststdcqp 0, 2, 8 +; CHECK-NEXT: bc 4, 2, .LBB1_10 +; CHECK-NEXT: .LBB1_3: # %entry +; CHECK-NEXT: xststdcqp 0, 3, 8 +; CHECK-NEXT: bc 12, 2, .LBB1_5 +; CHECK-NEXT: .LBB1_4: # %entry +; CHECK-NEXT: vmr 3, 2 +; CHECK-NEXT: .LBB1_5: # %entry +; CHECK-NEXT: addis 3, 2, .LCPI1_1@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI1_1@toc@l +; CHECK-NEXT: lxv 34, 0(3) +; CHECK-NEXT: xscmpuqp 0, 4, 2 +; CHECK-NEXT: beq 0, .LBB1_7 +; CHECK-NEXT: # %bb.6: # %entry +; CHECK-NEXT: vmr 3, 4 +; CHECK-NEXT: .LBB1_7: # %entry +; CHECK-NEXT: vmr 2, 3 +; CHECK-NEXT: blr +; CHECK-NEXT: .LBB1_8: # %entry +; CHECK-NEXT: vmr 4, 3 +; CHECK-NEXT: bnu 0, .LBB1_2 +; CHECK-NEXT: .LBB1_9: +; CHECK-NEXT: addis 3, 2, .LCPI1_0@toc@ha +; CHECK-NEXT: addi 3, 3, .LCPI1_0@toc@l +; CHECK-NEXT: lxv 36, 0(3) +; CHECK-NEXT: xststdcqp 0, 2, 8 +; CHECK-NEXT: bc 12, 2, .LBB1_3 +; CHECK-NEXT: .LBB1_10: # %entry +; CHECK-NEXT: vmr 2, 4 +; CHECK-NEXT: xststdcqp 0, 3, 8 +; CHECK-NEXT: bc 4, 2, .LBB1_4 +; CHECK-NEXT: b .LBB1_5 +entry: + %m = call fp128 @llvm.maximum.f128(fp128 %a, fp128 %b) + ret fp128 %m +} + +declare fp128 @llvm.minimum.f128(fp128, fp128) +declare fp128 @llvm.maximum.f128(fp128, fp128) diff --git a/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll new file mode 100644 index 000000000000..c33875dbfee4 --- /dev/null +++ b/llvm/test/CodeGen/PowerPC/fminimum-fmaximum.ll @@ -0,0 +1,847 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2 +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 -mattr=-vsx < %s | FileCheck %s --check-prefix=NOVSX +; RUN: llc -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s --check-prefix=VSX +; RUN: llc -mtriple=powerpc64-ibm-aix -mcpu=pwr8 < %s | FileCheck %s --check-prefix=AIX + +define float @f32_minimum(float %a, float %b) { +; NOVSX-LABEL: f32_minimum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: fcmpu 0, 1, 2 +; NOVSX-NEXT: fmr 0, 1 +; NOVSX-NEXT: stfs 2, -8(1) +; NOVSX-NEXT: stfs 1, -4(1) +; NOVSX-NEXT: bc 12, 0, .LBB0_2 +; NOVSX-NEXT: # %bb.1: # %entry +; NOVSX-NEXT: fmr 0, 2 +; NOVSX-NEXT: .LBB0_2: # %entry +; NOVSX-NEXT: lwz 3, -4(1) +; NOVSX-NEXT: bc 4, 3, .LBB0_4 +; NOVSX-NEXT: # %bb.3: +; NOVSX-NEXT: addis 4, 2, .LCPI0_0@toc@ha +; NOVSX-NEXT: lfs 0, .LCPI0_0@toc@l(4) +; NOVSX-NEXT: .LBB0_4: # %entry +; NOVSX-NEXT: xoris 3, 3, 32768 +; NOVSX-NEXT: lwz 4, -8(1) +; NOVSX-NEXT: cmplwi 3, 0 +; NOVSX-NEXT: bc 12, 2, .LBB0_6 +; NOVSX-NEXT: # %bb.5: # %entry +; NOVSX-NEXT: fmr 1, 0 +; NOVSX-NEXT: .LBB0_6: # %entry +; NOVSX-NEXT: xoris 3, 4, 32768 +; NOVSX-NEXT: cmplwi 3, 0 +; NOVSX-NEXT: bc 12, 2, .LBB0_8 +; NOVSX-NEXT: # %bb.7: # %entry +; NOVSX-NEXT: fmr 2, 1 +; NOVSX-NEXT: .LBB0_8: # %entry +; NOVSX-NEXT: addis 3, 2, .LCPI0_1@toc@ha +; NOVSX-NEXT: lfs 1, .LCPI0_1@toc@l(3) +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 12, 2, .LBB0_10 +; NOVSX-NEXT: # %bb.9: # %entry +; NOVSX-NEXT: fmr 2, 0 +; NOVSX-NEXT: .LBB0_10: # %entry +; NOVSX-NEXT: fmr 1, 2 +; NOVSX-NEXT: blr +; +; VSX-LABEL: f32_minimum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: xscvdpspn 0, 1 +; VSX-NEXT: fcmpu 0, 1, 2 +; VSX-NEXT: xscvdpspn 3, 2 +; VSX-NEXT: mffprwz 3, 0 +; VSX-NEXT: bc 12, 3, .LBB0_2 +; VSX-NEXT: # %bb.1: # %entry +; VSX-NEXT: xsmindp 0, 1, 2 +; VSX-NEXT: b .LBB0_3 +; VSX-NEXT: .LBB0_2: +; VSX-NEXT: addis 4, 2, .LCPI0_0@toc@ha +; VSX-NEXT: lfs 0, .LCPI0_0@toc@l(4) +; VSX-NEXT: .LBB0_3: # %entry +; VSX-NEXT: xoris 3, 3, 32768 +; VSX-NEXT: mffprwz 4, 3 +; VSX-NEXT: cmplwi 3, 0 +; VSX-NEXT: bc 12, 2, .LBB0_5 +; VSX-NEXT: # %bb.4: # %entry +; VSX-NEXT: fmr 1, 0 +; VSX-NEXT: .LBB0_5: # %entry +; VSX-NEXT: xoris 3, 4, 32768 +; VSX-NEXT: cmplwi 3, 0 +; VSX-NEXT: bc 12, 2, .LBB0_7 +; VSX-NEXT: # %bb.6: # %entry +; VSX-NEXT: fmr 2, 1 +; VSX-NEXT: .LBB0_7: # %entry +; VSX-NEXT: xxlxor 1, 1, 1 +; VSX-NEXT: fcmpu 0, 0, 1 +; VSX-NEXT: bc 12, 2, .LBB0_9 +; VSX-NEXT: # %bb.8: # %entry +; VSX-NEXT: fmr 2, 0 +; VSX-NEXT: .LBB0_9: # %entry +; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: blr +; +; AIX-LABEL: f32_minimum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: xscvdpspn 0, 1 +; AIX-NEXT: fcmpu 0, 1, 2 +; AIX-NEXT: xscvdpspn 3, 2 +; AIX-NEXT: mffprwz 3, 0 +; AIX-NEXT: bc 12, 3, L..BB0_2 +; AIX-NEXT: # %bb.1: # %entry +; AIX-NEXT: xsmindp 0, 1, 2 +; AIX-NEXT: b L..BB0_3 +; AIX-NEXT: L..BB0_2: +; AIX-NEXT: ld 4, L..C0(2) # %const.0 +; AIX-NEXT: lfs 0, 0(4) +; AIX-NEXT: L..BB0_3: # %entry +; AIX-NEXT: xoris 3, 3, 32768 +; AIX-NEXT: mffprwz 4, 3 +; AIX-NEXT: cmplwi 3, 0 +; AIX-NEXT: bc 12, 2, L..BB0_5 +; AIX-NEXT: # %bb.4: # %entry +; AIX-NEXT: fmr 1, 0 +; AIX-NEXT: L..BB0_5: # %entry +; AIX-NEXT: xoris 3, 4, 32768 +; AIX-NEXT: cmplwi 3, 0 +; AIX-NEXT: bc 12, 2, L..BB0_7 +; AIX-NEXT: # %bb.6: # %entry +; AIX-NEXT: fmr 2, 1 +; AIX-NEXT: L..BB0_7: # %entry +; AIX-NEXT: xxlxor 1, 1, 1 +; AIX-NEXT: fcmpu 0, 0, 1 +; AIX-NEXT: bc 12, 2, L..BB0_9 +; AIX-NEXT: # %bb.8: # %entry +; AIX-NEXT: fmr 2, 0 +; AIX-NEXT: L..BB0_9: # %entry +; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: blr +entry: + %m = call float @llvm.minimum.f32(float %a, float %b) + ret float %m +} + +define float @f32_maximum(float %a, float %b) { +; NOVSX-LABEL: f32_maximum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: fcmpu 0, 1, 2 +; NOVSX-NEXT: fmr 0, 1 +; NOVSX-NEXT: stfs 2, -8(1) +; NOVSX-NEXT: stfs 1, -4(1) +; NOVSX-NEXT: bc 12, 1, .LBB1_2 +; NOVSX-NEXT: # %bb.1: # %entry +; NOVSX-NEXT: fmr 0, 2 +; NOVSX-NEXT: .LBB1_2: # %entry +; NOVSX-NEXT: lwz 3, -4(1) +; NOVSX-NEXT: bc 4, 3, .LBB1_4 +; NOVSX-NEXT: # %bb.3: +; NOVSX-NEXT: addis 4, 2, .LCPI1_0@toc@ha +; NOVSX-NEXT: lfs 0, .LCPI1_0@toc@l(4) +; NOVSX-NEXT: .LBB1_4: # %entry +; NOVSX-NEXT: cmpwi 3, 0 +; NOVSX-NEXT: lwz 4, -8(1) +; NOVSX-NEXT: bc 12, 2, .LBB1_6 +; NOVSX-NEXT: # %bb.5: # %entry +; NOVSX-NEXT: fmr 1, 0 +; NOVSX-NEXT: .LBB1_6: # %entry +; NOVSX-NEXT: cmpwi 4, 0 +; NOVSX-NEXT: bc 12, 2, .LBB1_8 +; NOVSX-NEXT: # %bb.7: # %entry +; NOVSX-NEXT: fmr 2, 1 +; NOVSX-NEXT: .LBB1_8: # %entry +; NOVSX-NEXT: addis 3, 2, .LCPI1_1@toc@ha +; NOVSX-NEXT: lfs 1, .LCPI1_1@toc@l(3) +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 12, 2, .LBB1_10 +; NOVSX-NEXT: # %bb.9: # %entry +; NOVSX-NEXT: fmr 2, 0 +; NOVSX-NEXT: .LBB1_10: # %entry +; NOVSX-NEXT: fmr 1, 2 +; NOVSX-NEXT: blr +; +; VSX-LABEL: f32_maximum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: xscvdpspn 0, 1 +; VSX-NEXT: fcmpu 0, 1, 2 +; VSX-NEXT: xscvdpspn 3, 2 +; VSX-NEXT: mffprwz 3, 0 +; VSX-NEXT: bc 12, 3, .LBB1_2 +; VSX-NEXT: # %bb.1: # %entry +; VSX-NEXT: xsmaxdp 0, 1, 2 +; VSX-NEXT: b .LBB1_3 +; VSX-NEXT: .LBB1_2: +; VSX-NEXT: addis 4, 2, .LCPI1_0@toc@ha +; VSX-NEXT: lfs 0, .LCPI1_0@toc@l(4) +; VSX-NEXT: .LBB1_3: # %entry +; VSX-NEXT: mffprwz 4, 3 +; VSX-NEXT: cmpwi 3, 0 +; VSX-NEXT: bc 12, 2, .LBB1_5 +; VSX-NEXT: # %bb.4: # %entry +; VSX-NEXT: fmr 1, 0 +; VSX-NEXT: .LBB1_5: # %entry +; VSX-NEXT: cmpwi 4, 0 +; VSX-NEXT: bc 12, 2, .LBB1_7 +; VSX-NEXT: # %bb.6: # %entry +; VSX-NEXT: fmr 2, 1 +; VSX-NEXT: .LBB1_7: # %entry +; VSX-NEXT: xxlxor 1, 1, 1 +; VSX-NEXT: fcmpu 0, 0, 1 +; VSX-NEXT: bc 12, 2, .LBB1_9 +; VSX-NEXT: # %bb.8: # %entry +; VSX-NEXT: fmr 2, 0 +; VSX-NEXT: .LBB1_9: # %entry +; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: blr +; +; AIX-LABEL: f32_maximum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: xscvdpspn 0, 1 +; AIX-NEXT: fcmpu 0, 1, 2 +; AIX-NEXT: xscvdpspn 3, 2 +; AIX-NEXT: mffprwz 3, 0 +; AIX-NEXT: bc 12, 3, L..BB1_2 +; AIX-NEXT: # %bb.1: # %entry +; AIX-NEXT: xsmaxdp 0, 1, 2 +; AIX-NEXT: b L..BB1_3 +; AIX-NEXT: L..BB1_2: +; AIX-NEXT: ld 4, L..C1(2) # %const.0 +; AIX-NEXT: lfs 0, 0(4) +; AIX-NEXT: L..BB1_3: # %entry +; AIX-NEXT: mffprwz 4, 3 +; AIX-NEXT: cmpwi 3, 0 +; AIX-NEXT: bc 12, 2, L..BB1_5 +; AIX-NEXT: # %bb.4: # %entry +; AIX-NEXT: fmr 1, 0 +; AIX-NEXT: L..BB1_5: # %entry +; AIX-NEXT: cmpwi 4, 0 +; AIX-NEXT: bc 12, 2, L..BB1_7 +; AIX-NEXT: # %bb.6: # %entry +; AIX-NEXT: fmr 2, 1 +; AIX-NEXT: L..BB1_7: # %entry +; AIX-NEXT: xxlxor 1, 1, 1 +; AIX-NEXT: fcmpu 0, 0, 1 +; AIX-NEXT: bc 12, 2, L..BB1_9 +; AIX-NEXT: # %bb.8: # %entry +; AIX-NEXT: fmr 2, 0 +; AIX-NEXT: L..BB1_9: # %entry +; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: blr +entry: + %m = call float @llvm.maximum.f32(float %a, float %b) + ret float %m +} + +define double @f64_minimum(double %a, double %b) { +; NOVSX-LABEL: f64_minimum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: fcmpu 0, 1, 2 +; NOVSX-NEXT: fmr 0, 1 +; NOVSX-NEXT: stfd 2, -16(1) +; NOVSX-NEXT: stfd 1, -8(1) +; NOVSX-NEXT: bc 12, 0, .LBB2_2 +; NOVSX-NEXT: # %bb.1: # %entry +; NOVSX-NEXT: fmr 0, 2 +; NOVSX-NEXT: .LBB2_2: # %entry +; NOVSX-NEXT: ld 3, -8(1) +; NOVSX-NEXT: bc 4, 3, .LBB2_4 +; NOVSX-NEXT: # %bb.3: +; NOVSX-NEXT: addis 4, 2, .LCPI2_0@toc@ha +; NOVSX-NEXT: lfs 0, .LCPI2_0@toc@l(4) +; NOVSX-NEXT: .LBB2_4: # %entry +; NOVSX-NEXT: li 5, 1 +; NOVSX-NEXT: ld 4, -16(1) +; NOVSX-NEXT: rldic 5, 5, 63, 0 +; NOVSX-NEXT: cmpd 3, 5 +; NOVSX-NEXT: bc 12, 2, .LBB2_6 +; NOVSX-NEXT: # %bb.5: # %entry +; NOVSX-NEXT: fmr 1, 0 +; NOVSX-NEXT: .LBB2_6: # %entry +; NOVSX-NEXT: cmpd 4, 5 +; NOVSX-NEXT: bc 12, 2, .LBB2_8 +; NOVSX-NEXT: # %bb.7: # %entry +; NOVSX-NEXT: fmr 2, 1 +; NOVSX-NEXT: .LBB2_8: # %entry +; NOVSX-NEXT: addis 3, 2, .LCPI2_1@toc@ha +; NOVSX-NEXT: lfs 1, .LCPI2_1@toc@l(3) +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 12, 2, .LBB2_10 +; NOVSX-NEXT: # %bb.9: # %entry +; NOVSX-NEXT: fmr 2, 0 +; NOVSX-NEXT: .LBB2_10: # %entry +; NOVSX-NEXT: fmr 1, 2 +; NOVSX-NEXT: blr +; +; VSX-LABEL: f64_minimum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: fcmpu 0, 1, 2 +; VSX-NEXT: mffprd 3, 1 +; VSX-NEXT: bc 12, 3, .LBB2_2 +; VSX-NEXT: # %bb.1: # %entry +; VSX-NEXT: xsmindp 0, 1, 2 +; VSX-NEXT: b .LBB2_3 +; VSX-NEXT: .LBB2_2: +; VSX-NEXT: addis 4, 2, .LCPI2_0@toc@ha +; VSX-NEXT: lfs 0, .LCPI2_0@toc@l(4) +; VSX-NEXT: .LBB2_3: # %entry +; VSX-NEXT: li 5, 1 +; VSX-NEXT: mffprd 4, 2 +; VSX-NEXT: rldic 5, 5, 63, 0 +; VSX-NEXT: cmpd 3, 5 +; VSX-NEXT: bc 12, 2, .LBB2_5 +; VSX-NEXT: # %bb.4: # %entry +; VSX-NEXT: fmr 1, 0 +; VSX-NEXT: .LBB2_5: # %entry +; VSX-NEXT: cmpd 4, 5 +; VSX-NEXT: bc 12, 2, .LBB2_7 +; VSX-NEXT: # %bb.6: # %entry +; VSX-NEXT: fmr 2, 1 +; VSX-NEXT: .LBB2_7: # %entry +; VSX-NEXT: xxlxor 1, 1, 1 +; VSX-NEXT: fcmpu 0, 0, 1 +; VSX-NEXT: bc 12, 2, .LBB2_9 +; VSX-NEXT: # %bb.8: # %entry +; VSX-NEXT: fmr 2, 0 +; VSX-NEXT: .LBB2_9: # %entry +; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: blr +; +; AIX-LABEL: f64_minimum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: fcmpu 0, 1, 2 +; AIX-NEXT: mffprd 3, 1 +; AIX-NEXT: bc 12, 3, L..BB2_2 +; AIX-NEXT: # %bb.1: # %entry +; AIX-NEXT: xsmindp 0, 1, 2 +; AIX-NEXT: b L..BB2_3 +; AIX-NEXT: L..BB2_2: +; AIX-NEXT: ld 4, L..C2(2) # %const.0 +; AIX-NEXT: lfs 0, 0(4) +; AIX-NEXT: L..BB2_3: # %entry +; AIX-NEXT: li 5, 1 +; AIX-NEXT: mffprd 4, 2 +; AIX-NEXT: rldic 5, 5, 63, 0 +; AIX-NEXT: cmpd 3, 5 +; AIX-NEXT: bc 12, 2, L..BB2_5 +; AIX-NEXT: # %bb.4: # %entry +; AIX-NEXT: fmr 1, 0 +; AIX-NEXT: L..BB2_5: # %entry +; AIX-NEXT: cmpd 4, 5 +; AIX-NEXT: bc 12, 2, L..BB2_7 +; AIX-NEXT: # %bb.6: # %entry +; AIX-NEXT: fmr 2, 1 +; AIX-NEXT: L..BB2_7: # %entry +; AIX-NEXT: xxlxor 1, 1, 1 +; AIX-NEXT: fcmpu 0, 0, 1 +; AIX-NEXT: bc 12, 2, L..BB2_9 +; AIX-NEXT: # %bb.8: # %entry +; AIX-NEXT: fmr 2, 0 +; AIX-NEXT: L..BB2_9: # %entry +; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: blr +entry: + %m = call double @llvm.minimum.f64(double %a, double %b) + ret double %m +} + +define double @f64_maximum(double %a, double %b) { +; NOVSX-LABEL: f64_maximum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: fcmpu 0, 1, 2 +; NOVSX-NEXT: fmr 0, 1 +; NOVSX-NEXT: stfd 2, -16(1) +; NOVSX-NEXT: stfd 1, -8(1) +; NOVSX-NEXT: bc 12, 1, .LBB3_2 +; NOVSX-NEXT: # %bb.1: # %entry +; NOVSX-NEXT: fmr 0, 2 +; NOVSX-NEXT: .LBB3_2: # %entry +; NOVSX-NEXT: ld 3, -8(1) +; NOVSX-NEXT: bc 4, 3, .LBB3_4 +; NOVSX-NEXT: # %bb.3: +; NOVSX-NEXT: addis 4, 2, .LCPI3_0@toc@ha +; NOVSX-NEXT: lfs 0, .LCPI3_0@toc@l(4) +; NOVSX-NEXT: .LBB3_4: # %entry +; NOVSX-NEXT: cmpdi 3, 0 +; NOVSX-NEXT: ld 4, -16(1) +; NOVSX-NEXT: bc 12, 2, .LBB3_6 +; NOVSX-NEXT: # %bb.5: # %entry +; NOVSX-NEXT: fmr 1, 0 +; NOVSX-NEXT: .LBB3_6: # %entry +; NOVSX-NEXT: cmpdi 4, 0 +; NOVSX-NEXT: bc 12, 2, .LBB3_8 +; NOVSX-NEXT: # %bb.7: # %entry +; NOVSX-NEXT: fmr 2, 1 +; NOVSX-NEXT: .LBB3_8: # %entry +; NOVSX-NEXT: addis 3, 2, .LCPI3_1@toc@ha +; NOVSX-NEXT: lfs 1, .LCPI3_1@toc@l(3) +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 12, 2, .LBB3_10 +; NOVSX-NEXT: # %bb.9: # %entry +; NOVSX-NEXT: fmr 2, 0 +; NOVSX-NEXT: .LBB3_10: # %entry +; NOVSX-NEXT: fmr 1, 2 +; NOVSX-NEXT: blr +; +; VSX-LABEL: f64_maximum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: fcmpu 0, 1, 2 +; VSX-NEXT: mffprd 3, 1 +; VSX-NEXT: bc 12, 3, .LBB3_2 +; VSX-NEXT: # %bb.1: # %entry +; VSX-NEXT: xsmaxdp 0, 1, 2 +; VSX-NEXT: b .LBB3_3 +; VSX-NEXT: .LBB3_2: +; VSX-NEXT: addis 4, 2, .LCPI3_0@toc@ha +; VSX-NEXT: lfs 0, .LCPI3_0@toc@l(4) +; VSX-NEXT: .LBB3_3: # %entry +; VSX-NEXT: mffprd 4, 2 +; VSX-NEXT: cmpdi 3, 0 +; VSX-NEXT: bc 12, 2, .LBB3_5 +; VSX-NEXT: # %bb.4: # %entry +; VSX-NEXT: fmr 1, 0 +; VSX-NEXT: .LBB3_5: # %entry +; VSX-NEXT: cmpdi 4, 0 +; VSX-NEXT: bc 12, 2, .LBB3_7 +; VSX-NEXT: # %bb.6: # %entry +; VSX-NEXT: fmr 2, 1 +; VSX-NEXT: .LBB3_7: # %entry +; VSX-NEXT: xxlxor 1, 1, 1 +; VSX-NEXT: fcmpu 0, 0, 1 +; VSX-NEXT: bc 12, 2, .LBB3_9 +; VSX-NEXT: # %bb.8: # %entry +; VSX-NEXT: fmr 2, 0 +; VSX-NEXT: .LBB3_9: # %entry +; VSX-NEXT: fmr 1, 2 +; VSX-NEXT: blr +; +; AIX-LABEL: f64_maximum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: fcmpu 0, 1, 2 +; AIX-NEXT: mffprd 3, 1 +; AIX-NEXT: bc 12, 3, L..BB3_2 +; AIX-NEXT: # %bb.1: # %entry +; AIX-NEXT: xsmaxdp 0, 1, 2 +; AIX-NEXT: b L..BB3_3 +; AIX-NEXT: L..BB3_2: +; AIX-NEXT: ld 4, L..C3(2) # %const.0 +; AIX-NEXT: lfs 0, 0(4) +; AIX-NEXT: L..BB3_3: # %entry +; AIX-NEXT: mffprd 4, 2 +; AIX-NEXT: cmpdi 3, 0 +; AIX-NEXT: bc 12, 2, L..BB3_5 +; AIX-NEXT: # %bb.4: # %entry +; AIX-NEXT: fmr 1, 0 +; AIX-NEXT: L..BB3_5: # %entry +; AIX-NEXT: cmpdi 4, 0 +; AIX-NEXT: bc 12, 2, L..BB3_7 +; AIX-NEXT: # %bb.6: # %entry +; AIX-NEXT: fmr 2, 1 +; AIX-NEXT: L..BB3_7: # %entry +; AIX-NEXT: xxlxor 1, 1, 1 +; AIX-NEXT: fcmpu 0, 0, 1 +; AIX-NEXT: bc 12, 2, L..BB3_9 +; AIX-NEXT: # %bb.8: # %entry +; AIX-NEXT: fmr 2, 0 +; AIX-NEXT: L..BB3_9: # %entry +; AIX-NEXT: fmr 1, 2 +; AIX-NEXT: blr +entry: + %m = call double @llvm.maximum.f64(double %a, double %b) + ret double %m +} + +define <4 x float> @v4f32_minimum(<4 x float> %a, <4 x float> %b) { +; NOVSX-LABEL: v4f32_minimum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: vcmpeqfp 0, 3, 3 +; NOVSX-NEXT: vcmpeqfp 1, 2, 2 +; NOVSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha +; NOVSX-NEXT: addi 3, 3, .LCPI4_0@toc@l +; NOVSX-NEXT: vnot 0, 0 +; NOVSX-NEXT: vnot 1, 1 +; NOVSX-NEXT: vspltisb 4, -1 +; NOVSX-NEXT: vcmpgtfp 5, 3, 2 +; NOVSX-NEXT: vslw 4, 4, 4 +; NOVSX-NEXT: vor 0, 1, 0 +; NOVSX-NEXT: lvx 1, 0, 3 +; NOVSX-NEXT: vsel 5, 3, 2, 5 +; NOVSX-NEXT: vsel 5, 5, 1, 0 +; NOVSX-NEXT: vcmpequw 0, 2, 4 +; NOVSX-NEXT: vcmpequw 4, 3, 4 +; NOVSX-NEXT: vsel 2, 5, 2, 0 +; NOVSX-NEXT: vsel 2, 2, 3, 4 +; NOVSX-NEXT: vxor 3, 3, 3 +; NOVSX-NEXT: vcmpeqfp 3, 5, 3 +; NOVSX-NEXT: vsel 2, 5, 2, 3 +; NOVSX-NEXT: blr +; +; VSX-LABEL: v4f32_minimum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: xvcmpeqsp 1, 35, 35 +; VSX-NEXT: xvcmpeqsp 2, 34, 34 +; VSX-NEXT: addis 3, 2, .LCPI4_0@toc@ha +; VSX-NEXT: xxleqv 36, 36, 36 +; VSX-NEXT: xvminsp 0, 34, 35 +; VSX-NEXT: vslw 4, 4, 4 +; VSX-NEXT: addi 3, 3, .LCPI4_0@toc@l +; VSX-NEXT: xxlnor 1, 1, 1 +; VSX-NEXT: xxlnor 2, 2, 2 +; VSX-NEXT: vcmpequw 5, 2, 4 +; VSX-NEXT: xxlor 1, 2, 1 +; VSX-NEXT: lxvd2x 2, 0, 3 +; VSX-NEXT: xxsel 0, 0, 2, 1 +; VSX-NEXT: xxlxor 2, 2, 2 +; VSX-NEXT: xvcmpeqsp 2, 0, 2 +; VSX-NEXT: xxsel 1, 0, 34, 37 +; VSX-NEXT: vcmpequw 2, 3, 4 +; VSX-NEXT: xxsel 1, 1, 35, 34 +; VSX-NEXT: xxsel 34, 0, 1, 2 +; VSX-NEXT: blr +; +; AIX-LABEL: v4f32_minimum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: xvcmpeqsp 1, 35, 35 +; AIX-NEXT: xvcmpeqsp 2, 34, 34 +; AIX-NEXT: ld 3, L..C4(2) # %const.0 +; AIX-NEXT: xxleqv 36, 36, 36 +; AIX-NEXT: xvminsp 0, 34, 35 +; AIX-NEXT: vslw 4, 4, 4 +; AIX-NEXT: xxlnor 1, 1, 1 +; AIX-NEXT: xxlnor 2, 2, 2 +; AIX-NEXT: vcmpequw 5, 2, 4 +; AIX-NEXT: xxlor 1, 2, 1 +; AIX-NEXT: lxvw4x 2, 0, 3 +; AIX-NEXT: xxsel 0, 0, 2, 1 +; AIX-NEXT: xxlxor 2, 2, 2 +; AIX-NEXT: xvcmpeqsp 2, 0, 2 +; AIX-NEXT: xxsel 1, 0, 34, 37 +; AIX-NEXT: vcmpequw 2, 3, 4 +; AIX-NEXT: xxsel 1, 1, 35, 34 +; AIX-NEXT: xxsel 34, 0, 1, 2 +; AIX-NEXT: blr +entry: + %m = call <4 x float> @llvm.minimum.v4f32(<4 x float> %a, <4 x float> %b) + ret <4 x float> %m +} + +define <4 x float> @v4f32_maximum(<4 x float> %a, <4 x float> %b) { +; NOVSX-LABEL: v4f32_maximum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: vcmpeqfp 5, 3, 3 +; NOVSX-NEXT: vcmpeqfp 0, 2, 2 +; NOVSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha +; NOVSX-NEXT: addi 3, 3, .LCPI5_0@toc@l +; NOVSX-NEXT: vnot 5, 5 +; NOVSX-NEXT: vnot 0, 0 +; NOVSX-NEXT: vcmpgtfp 4, 2, 3 +; NOVSX-NEXT: vor 5, 0, 5 +; NOVSX-NEXT: lvx 0, 0, 3 +; NOVSX-NEXT: vsel 4, 3, 2, 4 +; NOVSX-NEXT: vsel 4, 4, 0, 5 +; NOVSX-NEXT: vxor 5, 5, 5 +; NOVSX-NEXT: vcmpequw 0, 2, 5 +; NOVSX-NEXT: vsel 2, 4, 2, 0 +; NOVSX-NEXT: vcmpequw 0, 3, 5 +; NOVSX-NEXT: vsel 2, 2, 3, 0 +; NOVSX-NEXT: vcmpeqfp 3, 4, 5 +; NOVSX-NEXT: vsel 2, 4, 2, 3 +; NOVSX-NEXT: blr +; +; VSX-LABEL: v4f32_maximum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: xvcmpeqsp 1, 35, 35 +; VSX-NEXT: xvcmpeqsp 2, 34, 34 +; VSX-NEXT: addis 3, 2, .LCPI5_0@toc@ha +; VSX-NEXT: addi 3, 3, .LCPI5_0@toc@l +; VSX-NEXT: xxlnor 1, 1, 1 +; VSX-NEXT: xxlnor 2, 2, 2 +; VSX-NEXT: xvmaxsp 0, 34, 35 +; VSX-NEXT: xxlxor 36, 36, 36 +; VSX-NEXT: vcmpequw 5, 2, 4 +; VSX-NEXT: xxlor 1, 2, 1 +; VSX-NEXT: lxvd2x 2, 0, 3 +; VSX-NEXT: xxsel 0, 0, 2, 1 +; VSX-NEXT: xvcmpeqsp 2, 0, 36 +; VSX-NEXT: xxsel 1, 0, 34, 37 +; VSX-NEXT: vcmpequw 2, 3, 4 +; VSX-NEXT: xxsel 1, 1, 35, 34 +; VSX-NEXT: xxsel 34, 0, 1, 2 +; VSX-NEXT: blr +; +; AIX-LABEL: v4f32_maximum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: xvcmpeqsp 1, 35, 35 +; AIX-NEXT: xvcmpeqsp 2, 34, 34 +; AIX-NEXT: ld 3, L..C5(2) # %const.0 +; AIX-NEXT: xvmaxsp 0, 34, 35 +; AIX-NEXT: xxlxor 36, 36, 36 +; AIX-NEXT: xxlnor 1, 1, 1 +; AIX-NEXT: xxlnor 2, 2, 2 +; AIX-NEXT: vcmpequw 5, 2, 4 +; AIX-NEXT: xxlor 1, 2, 1 +; AIX-NEXT: lxvw4x 2, 0, 3 +; AIX-NEXT: xxsel 0, 0, 2, 1 +; AIX-NEXT: xvcmpeqsp 2, 0, 36 +; AIX-NEXT: xxsel 1, 0, 34, 37 +; AIX-NEXT: vcmpequw 2, 3, 4 +; AIX-NEXT: xxsel 1, 1, 35, 34 +; AIX-NEXT: xxsel 34, 0, 1, 2 +; AIX-NEXT: blr +entry: + %m = call <4 x float> @llvm.maximum.v4f32(<4 x float> %a, <4 x float> %b) + ret <4 x float> %m +} + +define <2 x double> @v2f64_minimum(<2 x double> %a, <2 x double> %b) { +; NOVSX-LABEL: v2f64_minimum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: fcmpu 0, 1, 3 +; NOVSX-NEXT: fmr 6, 1 +; NOVSX-NEXT: stfd 4, -16(1) +; NOVSX-NEXT: stfd 2, -8(1) +; NOVSX-NEXT: stfd 3, -32(1) +; NOVSX-NEXT: stfd 1, -24(1) +; NOVSX-NEXT: bc 12, 0, .LBB6_2 +; NOVSX-NEXT: # %bb.1: # %entry +; NOVSX-NEXT: fmr 6, 3 +; NOVSX-NEXT: .LBB6_2: # %entry +; NOVSX-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; NOVSX-NEXT: ld 4, -24(1) +; NOVSX-NEXT: lfs 0, .LCPI6_0@toc@l(3) +; NOVSX-NEXT: fmr 5, 0 +; NOVSX-NEXT: bc 12, 3, .LBB6_4 +; NOVSX-NEXT: # %bb.3: # %entry +; NOVSX-NEXT: fmr 5, 6 +; NOVSX-NEXT: .LBB6_4: # %entry +; NOVSX-NEXT: li 3, 1 +; NOVSX-NEXT: ld 5, -32(1) +; NOVSX-NEXT: rldic 3, 3, 63, 0 +; NOVSX-NEXT: cmpd 4, 3 +; NOVSX-NEXT: bc 12, 2, .LBB6_6 +; NOVSX-NEXT: # %bb.5: # %entry +; NOVSX-NEXT: fmr 1, 5 +; NOVSX-NEXT: .LBB6_6: # %entry +; NOVSX-NEXT: cmpd 5, 3 +; NOVSX-NEXT: bc 12, 2, .LBB6_8 +; NOVSX-NEXT: # %bb.7: # %entry +; NOVSX-NEXT: fmr 3, 1 +; NOVSX-NEXT: .LBB6_8: # %entry +; NOVSX-NEXT: addis 4, 2, .LCPI6_1@toc@ha +; NOVSX-NEXT: lfs 1, .LCPI6_1@toc@l(4) +; NOVSX-NEXT: fcmpu 0, 5, 1 +; NOVSX-NEXT: bc 12, 2, .LBB6_10 +; NOVSX-NEXT: # %bb.9: # %entry +; NOVSX-NEXT: fmr 3, 5 +; NOVSX-NEXT: .LBB6_10: # %entry +; NOVSX-NEXT: fcmpu 0, 2, 4 +; NOVSX-NEXT: fmr 5, 2 +; NOVSX-NEXT: bc 12, 0, .LBB6_12 +; NOVSX-NEXT: # %bb.11: # %entry +; NOVSX-NEXT: fmr 5, 4 +; NOVSX-NEXT: .LBB6_12: # %entry +; NOVSX-NEXT: ld 5, -8(1) +; NOVSX-NEXT: bc 12, 3, .LBB6_14 +; NOVSX-NEXT: # %bb.13: # %entry +; NOVSX-NEXT: fmr 0, 5 +; NOVSX-NEXT: .LBB6_14: # %entry +; NOVSX-NEXT: cmpd 5, 3 +; NOVSX-NEXT: ld 4, -16(1) +; NOVSX-NEXT: bc 4, 2, .LBB6_19 +; NOVSX-NEXT: # %bb.15: # %entry +; NOVSX-NEXT: cmpd 4, 3 +; NOVSX-NEXT: bc 4, 2, .LBB6_20 +; NOVSX-NEXT: .LBB6_16: # %entry +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 12, 2, .LBB6_18 +; NOVSX-NEXT: .LBB6_17: # %entry +; NOVSX-NEXT: fmr 4, 0 +; NOVSX-NEXT: .LBB6_18: # %entry +; NOVSX-NEXT: fmr 1, 3 +; NOVSX-NEXT: fmr 2, 4 +; NOVSX-NEXT: blr +; NOVSX-NEXT: .LBB6_19: # %entry +; NOVSX-NEXT: fmr 2, 0 +; NOVSX-NEXT: cmpd 4, 3 +; NOVSX-NEXT: bc 12, 2, .LBB6_16 +; NOVSX-NEXT: .LBB6_20: # %entry +; NOVSX-NEXT: fmr 4, 2 +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 4, 2, .LBB6_17 +; NOVSX-NEXT: b .LBB6_18 +; +; VSX-LABEL: v2f64_minimum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: addis 3, 2, .LCPI6_0@toc@ha +; VSX-NEXT: xvcmpeqdp 36, 35, 35 +; VSX-NEXT: xvcmpeqdp 37, 34, 34 +; VSX-NEXT: addi 3, 3, .LCPI6_0@toc@l +; VSX-NEXT: xxlnor 36, 36, 36 +; VSX-NEXT: xxlnor 37, 37, 37 +; VSX-NEXT: xvmindp 0, 34, 35 +; VSX-NEXT: lxvd2x 2, 0, 3 +; VSX-NEXT: addis 3, 2, .LCPI6_1@toc@ha +; VSX-NEXT: xxlor 1, 37, 36 +; VSX-NEXT: addi 3, 3, .LCPI6_1@toc@l +; VSX-NEXT: lxvd2x 36, 0, 3 +; VSX-NEXT: vcmpequd 5, 2, 4 +; VSX-NEXT: xxsel 0, 0, 2, 1 +; VSX-NEXT: xxlxor 2, 2, 2 +; VSX-NEXT: xxsel 1, 0, 34, 37 +; VSX-NEXT: vcmpequd 2, 3, 4 +; VSX-NEXT: xxsel 1, 1, 35, 34 +; VSX-NEXT: xvcmpeqdp 34, 0, 2 +; VSX-NEXT: xxsel 34, 0, 1, 34 +; VSX-NEXT: blr +; +; AIX-LABEL: v2f64_minimum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: ld 3, L..C6(2) # %const.0 +; AIX-NEXT: xvcmpeqdp 36, 35, 35 +; AIX-NEXT: xvcmpeqdp 37, 34, 34 +; AIX-NEXT: lxvd2x 2, 0, 3 +; AIX-NEXT: ld 3, L..C7(2) # %const.1 +; AIX-NEXT: xxlnor 36, 36, 36 +; AIX-NEXT: xxlnor 37, 37, 37 +; AIX-NEXT: xvmindp 0, 34, 35 +; AIX-NEXT: xxlor 1, 37, 36 +; AIX-NEXT: lxvd2x 36, 0, 3 +; AIX-NEXT: vcmpequd 5, 2, 4 +; AIX-NEXT: xxsel 0, 0, 2, 1 +; AIX-NEXT: xxlxor 2, 2, 2 +; AIX-NEXT: xxsel 1, 0, 34, 37 +; AIX-NEXT: vcmpequd 2, 3, 4 +; AIX-NEXT: xxsel 1, 1, 35, 34 +; AIX-NEXT: xvcmpeqdp 34, 0, 2 +; AIX-NEXT: xxsel 34, 0, 1, 34 +; AIX-NEXT: blr +entry: + %m = call <2 x double> @llvm.minimum.v2f64(<2 x double> %a, <2 x double> %b) + ret <2 x double> %m +} + +define <2 x double> @v2f64_maximum(<2 x double> %a, <2 x double> %b) { +; NOVSX-LABEL: v2f64_maximum: +; NOVSX: # %bb.0: # %entry +; NOVSX-NEXT: fcmpu 0, 1, 3 +; NOVSX-NEXT: fmr 6, 1 +; NOVSX-NEXT: stfd 4, -16(1) +; NOVSX-NEXT: stfd 2, -8(1) +; NOVSX-NEXT: stfd 3, -32(1) +; NOVSX-NEXT: stfd 1, -24(1) +; NOVSX-NEXT: bc 12, 1, .LBB7_2 +; NOVSX-NEXT: # %bb.1: # %entry +; NOVSX-NEXT: fmr 6, 3 +; NOVSX-NEXT: .LBB7_2: # %entry +; NOVSX-NEXT: addis 4, 2, .LCPI7_0@toc@ha +; NOVSX-NEXT: ld 3, -24(1) +; NOVSX-NEXT: lfs 0, .LCPI7_0@toc@l(4) +; NOVSX-NEXT: fmr 5, 0 +; NOVSX-NEXT: bc 12, 3, .LBB7_4 +; NOVSX-NEXT: # %bb.3: # %entry +; NOVSX-NEXT: fmr 5, 6 +; NOVSX-NEXT: .LBB7_4: # %entry +; NOVSX-NEXT: cmpdi 3, 0 +; NOVSX-NEXT: ld 4, -32(1) +; NOVSX-NEXT: bc 12, 2, .LBB7_6 +; NOVSX-NEXT: # %bb.5: # %entry +; NOVSX-NEXT: fmr 1, 5 +; NOVSX-NEXT: .LBB7_6: # %entry +; NOVSX-NEXT: cmpdi 4, 0 +; NOVSX-NEXT: bc 12, 2, .LBB7_8 +; NOVSX-NEXT: # %bb.7: # %entry +; NOVSX-NEXT: fmr 3, 1 +; NOVSX-NEXT: .LBB7_8: # %entry +; NOVSX-NEXT: addis 3, 2, .LCPI7_1@toc@ha +; NOVSX-NEXT: lfs 1, .LCPI7_1@toc@l(3) +; NOVSX-NEXT: fcmpu 0, 5, 1 +; NOVSX-NEXT: bc 12, 2, .LBB7_10 +; NOVSX-NEXT: # %bb.9: # %entry +; NOVSX-NEXT: fmr 3, 5 +; NOVSX-NEXT: .LBB7_10: # %entry +; NOVSX-NEXT: fcmpu 0, 2, 4 +; NOVSX-NEXT: fmr 5, 2 +; NOVSX-NEXT: bc 12, 1, .LBB7_12 +; NOVSX-NEXT: # %bb.11: # %entry +; NOVSX-NEXT: fmr 5, 4 +; NOVSX-NEXT: .LBB7_12: # %entry +; NOVSX-NEXT: ld 4, -8(1) +; NOVSX-NEXT: bc 12, 3, .LBB7_14 +; NOVSX-NEXT: # %bb.13: # %entry +; NOVSX-NEXT: fmr 0, 5 +; NOVSX-NEXT: .LBB7_14: # %entry +; NOVSX-NEXT: cmpdi 4, 0 +; NOVSX-NEXT: ld 3, -16(1) +; NOVSX-NEXT: bc 4, 2, .LBB7_19 +; NOVSX-NEXT: # %bb.15: # %entry +; NOVSX-NEXT: cmpdi 3, 0 +; NOVSX-NEXT: bc 4, 2, .LBB7_20 +; NOVSX-NEXT: .LBB7_16: # %entry +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 12, 2, .LBB7_18 +; NOVSX-NEXT: .LBB7_17: # %entry +; NOVSX-NEXT: fmr 4, 0 +; NOVSX-NEXT: .LBB7_18: # %entry +; NOVSX-NEXT: fmr 1, 3 +; NOVSX-NEXT: fmr 2, 4 +; NOVSX-NEXT: blr +; NOVSX-NEXT: .LBB7_19: # %entry +; NOVSX-NEXT: fmr 2, 0 +; NOVSX-NEXT: cmpdi 3, 0 +; NOVSX-NEXT: bc 12, 2, .LBB7_16 +; NOVSX-NEXT: .LBB7_20: # %entry +; NOVSX-NEXT: fmr 4, 2 +; NOVSX-NEXT: fcmpu 0, 0, 1 +; NOVSX-NEXT: bc 4, 2, .LBB7_17 +; NOVSX-NEXT: b .LBB7_18 +; +; VSX-LABEL: v2f64_maximum: +; VSX: # %bb.0: # %entry +; VSX-NEXT: addis 3, 2, .LCPI7_0@toc@ha +; VSX-NEXT: xvcmpeqdp 36, 35, 35 +; VSX-NEXT: xvcmpeqdp 37, 34, 34 +; VSX-NEXT: addi 3, 3, .LCPI7_0@toc@l +; VSX-NEXT: xxlnor 36, 36, 36 +; VSX-NEXT: xxlnor 37, 37, 37 +; VSX-NEXT: xvmaxdp 0, 34, 35 +; VSX-NEXT: lxvd2x 2, 0, 3 +; VSX-NEXT: xxlor 1, 37, 36 +; VSX-NEXT: xxlxor 36, 36, 36 +; VSX-NEXT: vcmpequd 5, 2, 4 +; VSX-NEXT: xxsel 0, 0, 2, 1 +; VSX-NEXT: xxsel 1, 0, 34, 37 +; VSX-NEXT: vcmpequd 2, 3, 4 +; VSX-NEXT: xxsel 1, 1, 35, 34 +; VSX-NEXT: xvcmpeqdp 34, 0, 36 +; VSX-NEXT: xxsel 34, 0, 1, 34 +; VSX-NEXT: blr +; +; AIX-LABEL: v2f64_maximum: +; AIX: # %bb.0: # %entry +; AIX-NEXT: ld 3, L..C8(2) # %const.0 +; AIX-NEXT: xvcmpeqdp 36, 35, 35 +; AIX-NEXT: xvcmpeqdp 37, 34, 34 +; AIX-NEXT: lxvd2x 2, 0, 3 +; AIX-NEXT: xxlnor 36, 36, 36 +; AIX-NEXT: xxlnor 37, 37, 37 +; AIX-NEXT: xvmaxdp 0, 34, 35 +; AIX-NEXT: xxlor 1, 37, 36 +; AIX-NEXT: xxlxor 36, 36, 36 +; AIX-NEXT: vcmpequd 5, 2, 4 +; AIX-NEXT: xxsel 0, 0, 2, 1 +; AIX-NEXT: xxsel 1, 0, 34, 37 +; AIX-NEXT: vcmpequd 2, 3, 4 +; AIX-NEXT: xxsel 1, 1, 35, 34 +; AIX-NEXT: xvcmpeqdp 34, 0, 36 +; AIX-NEXT: xxsel 34, 0, 1, 34 +; AIX-NEXT: blr +entry: + %m = call <2 x double> @llvm.maximum.v2f64(<2 x double> %a, <2 x double> %b) + ret <2 x double> %m +} + +declare float @llvm.maximum.f32(float, float) +declare double @llvm.maximum.f64(double, double) +declare <4 x float> @llvm.maximum.v4f32(<4 x float>, <4 x float>) +declare <2 x double> @llvm.maximum.v2f64(<2 x double>, <2 x double>) + +declare float @llvm.minimum.f32(float, float) +declare double @llvm.minimum.f64(double, double) +declare <4 x float> @llvm.minimum.v4f32(<4 x float>, <4 x float>) +declare <2 x double> @llvm.minimum.v2f64(<2 x double>, <2 x double>) -- GitLab From bd9fdce69b4c4cdb572e715c5f453aaf9b77b83a Mon Sep 17 00:00:00 2001 From: Christian Sigg Date: Mon, 29 Apr 2024 09:16:22 +0200 Subject: [PATCH 188/301] [flang] Use `isa/dyn_cast/cast/...` free functions. (#90432) The corresponding member functions are deprecated. --- flang/lib/Lower/ConvertVariable.cpp | 4 ++-- flang/lib/Optimizer/CodeGen/CodeGen.cpp | 8 ++++---- flang/lib/Optimizer/Dialect/FIROps.cpp | 8 +++----- flang/lib/Optimizer/Dialect/FIRType.cpp | 20 +++++++++---------- .../Transforms/SimplifyIntrinsics.cpp | 6 ++---- 5 files changed, 21 insertions(+), 25 deletions(-) diff --git a/flang/lib/Lower/ConvertVariable.cpp b/flang/lib/Lower/ConvertVariable.cpp index edf1f24a08e5..413563fe95ca 100644 --- a/flang/lib/Lower/ConvertVariable.cpp +++ b/flang/lib/Lower/ConvertVariable.cpp @@ -496,8 +496,8 @@ static fir::GlobalOp defineGlobal(Fortran::lower::AbstractConverter &converter, if (mlir::isa(symTy) && !Fortran::semantics::IsAllocatableOrPointer(sym)) { mlir::Type eleTy = mlir::cast(symTy).getEleTy(); - if (eleTy.isa()) { + if (mlir::isa(eleTy)) { const auto *details = sym.detailsIf(); if (details->init()) { diff --git a/flang/lib/Optimizer/CodeGen/CodeGen.cpp b/flang/lib/Optimizer/CodeGen/CodeGen.cpp index 19628ac71b0b..b4705aa47992 100644 --- a/flang/lib/Optimizer/CodeGen/CodeGen.cpp +++ b/flang/lib/Optimizer/CodeGen/CodeGen.cpp @@ -1964,12 +1964,12 @@ struct ValueOpCommon { mlir::ArrayAttr arrAttr) { llvm::SmallVector indices; for (auto i = arrAttr.begin(), e = arrAttr.end(); i != e; ++i) { - if (auto intAttr = i->dyn_cast()) { + if (auto intAttr = mlir::dyn_cast(*i)) { indices.push_back(intAttr.getInt()); } else { - auto fieldName = i->cast().getValue(); + auto fieldName = mlir::cast(*i).getValue(); ++i; - auto ty = i->cast().getValue(); + auto ty = mlir::cast(*i).getValue(); auto index = mlir::cast(ty).getFieldIndex(fieldName); indices.push_back(index); } @@ -3014,7 +3014,7 @@ static void selectMatchAndRewrite(const fir::LLVMTypeConverter &lowering, caseValues.push_back(intAttr.getInt()); continue; } - assert(attr.template dyn_cast_or_null()); + assert(mlir::dyn_cast_or_null(attr)); assert((t + 1 == conds) && "unit must be last"); defaultDestination = dest; defaultOperands = destOps ? *destOps : mlir::ValueRange{}; diff --git a/flang/lib/Optimizer/Dialect/FIROps.cpp b/flang/lib/Optimizer/Dialect/FIROps.cpp index a39087aeb358..6773d0adced0 100644 --- a/flang/lib/Optimizer/Dialect/FIROps.cpp +++ b/flang/lib/Optimizer/Dialect/FIROps.cpp @@ -2498,10 +2498,8 @@ static constexpr llvm::StringRef getTargetOffsetAttr() { template static mlir::LogicalResult verifyIntegralSwitchTerminator(OpT op) { - if (!op.getSelector() - .getType() - .template isa()) + if (!mlir::isa( + op.getSelector().getType())) return op.emitOpError("must be an integer"); auto cases = op->template getAttrOfType(op.getCasesAttr()).getValue(); @@ -2576,7 +2574,7 @@ static void printIntegralSwitchTerminator(OpT op, mlir::OpAsmPrinter &p) { if (i) p << ", "; auto &attr = cases[i]; - if (auto intAttr = attr.template dyn_cast_or_null()) + if (auto intAttr = mlir::dyn_cast_or_null(attr)) p << intAttr.getValue(); else p.printAttribute(attr); diff --git a/flang/lib/Optimizer/Dialect/FIRType.cpp b/flang/lib/Optimizer/Dialect/FIRType.cpp index 38a6a09d1808..d9c387ad950e 100644 --- a/flang/lib/Optimizer/Dialect/FIRType.cpp +++ b/flang/lib/Optimizer/Dialect/FIRType.cpp @@ -695,9 +695,9 @@ BoxProcType::verify(llvm::function_ref emitError, } static bool cannotBePointerOrHeapElementType(mlir::Type eleTy) { - return eleTy.isa(); + ReferenceType, TypeDescType>(eleTy); } //===----------------------------------------------------------------------===// @@ -776,10 +776,10 @@ void fir::CharacterType::print(mlir::AsmPrinter &printer) const { mlir::LogicalResult fir::ClassType::verify(llvm::function_ref emitError, mlir::Type eleTy) { - if (eleTy.isa()) + fir::ComplexType, mlir::ComplexType>(eleTy)) return mlir::success(); return emitError() << "invalid element type\n"; } @@ -1050,8 +1050,8 @@ void fir::ReferenceType::print(mlir::AsmPrinter &printer) const { mlir::LogicalResult fir::ReferenceType::verify( llvm::function_ref emitError, mlir::Type eleTy) { - if (eleTy.isa()) + if (mlir::isa(eleTy)) return emitError() << "cannot build a reference to type: " << eleTy << '\n'; return mlir::success(); } @@ -1126,9 +1126,9 @@ mlir::LogicalResult fir::SequenceType::verify( llvm::ArrayRef shape, mlir::Type eleTy, mlir::AffineMapAttr layoutMap) { // DIMENSION attribute can only be applied to an intrinsic or record type - if (eleTy.isa()) + ReferenceType, TypeDescType, SequenceType>(eleTy)) return emitError() << "cannot build an array of this element type: " << eleTy << '\n'; return mlir::success(); @@ -1199,9 +1199,9 @@ void fir::TypeDescType::print(mlir::AsmPrinter &printer) const { mlir::LogicalResult fir::TypeDescType::verify( llvm::function_ref emitError, mlir::Type eleTy) { - if (eleTy.isa()) + TypeDescType>(eleTy)) return emitError() << "cannot build a type descriptor of type: " << eleTy << '\n'; return mlir::success(); diff --git a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp index 601bf04ce5e9..c61179a7460e 100644 --- a/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp +++ b/flang/lib/Optimizer/Transforms/SimplifyIntrinsics.cpp @@ -1318,11 +1318,9 @@ void SimplifyIntrinsicsPass::runOnOperation() { // Support only floating point and integer arguments // now (e.g. logical is skipped here). - if (!arg1Type->isa() && - !arg1Type->isa()) + if (!mlir::isa(*arg1Type)) return; - if (!arg2Type->isa() && - !arg2Type->isa()) + if (!mlir::isa(*arg2Type)) return; auto typeGenerator = [&type](fir::FirOpBuilder &builder) { -- GitLab From e1622e189e8c0ef457bfac528f90a7a930d9aad2 Mon Sep 17 00:00:00 2001 From: Nikita Popov Date: Mon, 29 Apr 2024 15:50:03 +0900 Subject: [PATCH 189/301] [InstCombine] Add tests for trunc nuw/nsw in icmp (NFC) --- .../InstCombine/icmp-of-trunc-ext.ll | 325 ++++++++++++++++++ 1 file changed, 325 insertions(+) diff --git a/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll b/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll index 7f616bbb2a83..a61694919ab0 100644 --- a/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll +++ b/llvm/test/Transforms/InstCombine/icmp-of-trunc-ext.ll @@ -268,3 +268,328 @@ define i1 @icmp_trunc_x_zext_y_fail_multiuse(i32 %x, i8 %y) { %r = icmp ule i16 %x16, %y16 ret i1 %r } + +define i1 @trunc_unsigned_nuw(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_unsigned_nuw( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nuw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i16 %x to i8 + %yt = trunc nuw i16 %y to i8 + %c = icmp ult i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_unsigned_nsw(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_unsigned_nsw( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i16 %x to i8 + %yt = trunc nsw i16 %y to i8 + %c = icmp ult i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_unsigned_both(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_unsigned_both( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw nsw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nuw nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw nsw i16 %x to i8 + %yt = trunc nuw nsw i16 %y to i8 + %c = icmp ult i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_unsigned_either(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_unsigned_either( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp ult i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i16 %x to i8 + %yt = trunc nsw i16 %y to i8 + %c = icmp ult i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_signed_nuw(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_signed_nuw( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nuw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i16 %x to i8 + %yt = trunc nuw i16 %y to i8 + %c = icmp slt i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_signed_nsw(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_signed_nsw( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i16 %x to i8 + %yt = trunc nsw i16 %y to i8 + %c = icmp slt i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_signed_both(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_signed_both( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw nsw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nuw nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw nsw i16 %x to i8 + %yt = trunc nuw nsw i16 %y to i8 + %c = icmp slt i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_signed_either(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_signed_either( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp slt i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i16 %x to i8 + %yt = trunc nsw i16 %y to i8 + %c = icmp slt i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_equality_nuw(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_equality_nuw( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nuw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i16 %x to i8 + %yt = trunc nuw i16 %y to i8 + %c = icmp eq i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_equality_nsw(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_equality_nsw( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i16 %x to i8 + %yt = trunc nsw i16 %y to i8 + %c = icmp eq i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_equality_both(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_equality_both( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw nsw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nuw nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw nsw i16 %x to i8 + %yt = trunc nuw nsw i16 %y to i8 + %c = icmp eq i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_equality_either(i16 %x, i16 %y) { +; CHECK-LABEL: @trunc_equality_either( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i16 [[X:%.*]] to i8 +; CHECK-NEXT: [[YT:%.*]] = trunc nsw i16 [[Y:%.*]] to i8 +; CHECK-NEXT: [[C:%.*]] = icmp eq i8 [[XT]], [[YT]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i16 %x to i8 + %yt = trunc nsw i16 %y to i8 + %c = icmp eq i8 %xt, %yt + ret i1 %c +} + +define i1 @trunc_unsigned_nuw_zext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_unsigned_nuw_zext( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = zext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ult i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i32 %x to i16 + %ye = zext i8 %y to i16 + %c = icmp ult i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_unsigned_nuw_sext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_unsigned_nuw_sext( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = sext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ult i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i32 %x to i16 + %ye = sext i8 %y to i16 + %c = icmp ult i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_unsigned_nsw_zext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_unsigned_nsw_zext( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = zext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ult i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i32 %x to i16 + %ye = zext i8 %y to i16 + %c = icmp ult i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_unsigned_nsw_sext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_unsigned_nsw_sext( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = sext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ult i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i32 %x to i16 + %ye = sext i8 %y to i16 + %c = icmp ult i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_signed_nsw_sext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_signed_nsw_sext( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = sext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp slt i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i32 %x to i16 + %ye = sext i8 %y to i16 + %c = icmp slt i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_signed_nsw_zext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_signed_nsw_zext( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = zext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp slt i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i32 %x to i16 + %ye = zext i8 %y to i16 + %c = icmp slt i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_signed_nuw_sext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_signed_nuw_sext( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = sext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp slt i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i32 %x to i16 + %ye = sext i8 %y to i16 + %c = icmp slt i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_signed_nuw_zext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_signed_nuw_zext( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = zext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp slt i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i32 %x to i16 + %ye = zext i8 %y to i16 + %c = icmp slt i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_equality_nuw_zext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_equality_nuw_zext( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = zext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ne i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i32 %x to i16 + %ye = zext i8 %y to i16 + %c = icmp ne i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_equality_nuw_sext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_equality_nuw_sext( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = sext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ne i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw i32 %x to i16 + %ye = sext i8 %y to i16 + %c = icmp ne i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_equality_nsw_zext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_equality_nsw_zext( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = zext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ne i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i32 %x to i16 + %ye = zext i8 %y to i16 + %c = icmp ne i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_equality_nsw_sext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_equality_nsw_sext( +; CHECK-NEXT: [[XT:%.*]] = trunc nsw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = sext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ne i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nsw i32 %x to i16 + %ye = sext i8 %y to i16 + %c = icmp ne i16 %xt, %ye + ret i1 %c +} + +define i1 @trunc_equality_both_sext(i32 %x, i8 %y) { +; CHECK-LABEL: @trunc_equality_both_sext( +; CHECK-NEXT: [[XT:%.*]] = trunc nuw nsw i32 [[X:%.*]] to i16 +; CHECK-NEXT: [[YE:%.*]] = sext i8 [[Y:%.*]] to i16 +; CHECK-NEXT: [[C:%.*]] = icmp ne i16 [[XT]], [[YE]] +; CHECK-NEXT: ret i1 [[C]] +; + %xt = trunc nuw nsw i32 %x to i16 + %ye = sext i8 %y to i16 + %c = icmp ne i16 %xt, %ye + ret i1 %c +} -- GitLab From 5f79f7506a495872be431a4607a33fa717fda2eb Mon Sep 17 00:00:00 2001 From: Peter Waller Date: Mon, 29 Apr 2024 08:39:15 +0100 Subject: [PATCH 190/301] [llvm-mca] Add -skip-unsupported-instructions option (#89733) Prior to this patch, if llvm-mca encountered an instruction which parses but has no scheduler info, the instruction is always reported as unsupported, and llvm-mca halts with an error. However, it would still be useful to allow MCA to continue even in the case of instructions lacking scheduling information. Obviously if scheduling information is lacking, it's not possible to give an accurate analysis for those instructions, and therefore a warning is emitted. A user could previously have worked around such unsupported instructions manually by deleting such instructions from the input, but this provides them a way of doing this for bulk inputs where they may not have a list of such unsupported instructions to drop up front. Note that this behaviour of instructions with no scheduling information under -skip-unsupported-instructions is analagous to current instructions which fail to parse: those are currently dropped from the input with a message printed, after which the analysis continues. ~Testing the feature is a little awkward currently, it relies on an instruction which is currently marked as unsupported, which may not remain so; should the situation change it would be necessary to find an alternative unsupported instruction or drop the test.~ A test is added to check that analysis still reports an error if all instructions are removed from the input, to mirror the current behaviour of giving an error if no instructions are supplied. --- llvm/lib/MCA/InstrBuilder.cpp | 3 +- ...kip-unsupported-instructions-none-remain.s | 14 +++++ .../X86/BtVer2/unsupported-instruction.s | 55 ++++++++++++++++++- llvm/tools/llvm-mca/CodeRegion.h | 15 +++++ llvm/tools/llvm-mca/llvm-mca.cpp | 39 +++++++++++-- 5 files changed, 116 insertions(+), 10 deletions(-) create mode 100644 llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s diff --git a/llvm/lib/MCA/InstrBuilder.cpp b/llvm/lib/MCA/InstrBuilder.cpp index 1a82e45763a2..2e3ebe3d9073 100644 --- a/llvm/lib/MCA/InstrBuilder.cpp +++ b/llvm/lib/MCA/InstrBuilder.cpp @@ -542,8 +542,7 @@ InstrBuilder::createInstrDescImpl(const MCInst &MCI, const MCSchedClassDesc &SCDesc = *SM.getSchedClassDesc(SchedClassID); if (SCDesc.NumMicroOps == MCSchedClassDesc::InvalidNumMicroOps) { return make_error>( - "found an unsupported instruction in the input assembly sequence.", - MCI); + "found an unsupported instruction in the input assembly sequence", MCI); } LLVM_DEBUG(dbgs() << "\n\t\tOpcode Name= " << MCII.getName(Opcode) << '\n'); diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s b/llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s new file mode 100644 index 000000000000..a8f78159c199 --- /dev/null +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s @@ -0,0 +1,14 @@ +# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -skip-unsupported-instructions %s |& FileCheck --check-prefixes=CHECK-ALL,CHECK-SKIP %s +# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s |& FileCheck --check-prefixes=CHECK-ALL,CHECK-ERROR %s + +# Test defends that if all instructions are skipped leaving an empty input, an error is printed. + +bzhi %eax, %ebx, %ecx + +# CHECK-ALL-NOT: error + +# CHECK-ERROR: error: found an unsupported instruction in the input assembly sequence, use -skip-unsupported-instructions to ignore. + +# CHECK-SKIP: warning: found an unsupported instruction in the input assembly sequence, skipping with -skip-unsupported-instructions, note accuracy will be impacted: +# CHECK-SKIP: note: instruction: bzhil %eax, %ebx, %ecx +# CHECK-SKIP: error: no assembly instructions found. diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s b/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s index bb88e951c129..eec6de6648a6 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s @@ -1,6 +1,55 @@ -# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s 2>&1 | FileCheck %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -skip-unsupported-instructions -timeline %s |& FileCheck --check-prefix=CHECK-SKIP %s +# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s |& FileCheck --check-prefix=CHECK-ERROR %s + +# Test checks that unsupported instructions exit with an error, unless -skip-unsupported-instructions is passed, in which case the remaining instructions should be analysed. + +# CHECK-SKIP: warning: found an unsupported instruction in the input assembly sequence, skipping with -skip-unsupported-instructions, note accuracy will be impacted: +# CHECK-ERROR: error: found an unsupported instruction in the input assembly sequence, use -skip-unsupported-instructions to ignore. bzhi %eax, %ebx, %ecx -# CHECK: error: found an unsupported instruction in the input assembly sequence. -# CHECK-NEXT: note: instruction: bzhil %eax, %ebx, %ecx +# Supported instruction that may be analysed. +add %eax, %eax + +# CHECK-SKIP: Iterations: 100 +# CHECK-SKIP: Instructions: 100 +# CHECK-SKIP: Total Cycles: 103 +# CHECK-SKIP: Total uOps: 100 + +# CHECK-SKIP: Dispatch Width: 2 +# CHECK-SKIP: uOps Per Cycle: 0.97 +# CHECK-SKIP: IPC: 0.97 +# CHECK-SKIP: Block RThroughput: 0.5 + +# CHECK-SKIP: Instruction Info: +# CHECK-SKIP: [1]: #uOps +# CHECK-SKIP: [2]: Latency +# CHECK-SKIP: [3]: RThroughput +# CHECK-SKIP: [4]: MayLoad +# CHECK-SKIP: [5]: MayStore +# CHECK-SKIP: [6]: HasSideEffects (U) + +# CHECK-SKIP: [1] [2] [3] [4] [5] [6] Instructions: +# CHECK-SKIP: 1 1 0.50 addl %eax, %eax + +# CHECK-SKIP: Timeline view: + +# CHECK-SKIP: [0,0] DeER . . . addl %eax, %eax +# CHECK-SKIP: [1,0] D=eER. . . addl %eax, %eax +# CHECK-SKIP: [2,0] .D=eER . . addl %eax, %eax +# CHECK-SKIP: [3,0] .D==eER . . addl %eax, %eax +# CHECK-SKIP: [4,0] . D==eER . . addl %eax, %eax +# CHECK-SKIP: [5,0] . D===eER . . addl %eax, %eax +# CHECK-SKIP: [6,0] . D===eER. . addl %eax, %eax +# CHECK-SKIP: [7,0] . D====eER . addl %eax, %eax +# CHECK-SKIP: [8,0] . D====eER. addl %eax, %eax +# CHECK-SKIP: [9,0] . D=====eER addl %eax, %eax + +# CHECK-SKIP: Average Wait times (based on the timeline view): +# CHECK-SKIP: [0]: Executions +# CHECK-SKIP: [1]: Average time spent waiting in a scheduler's queue +# CHECK-SKIP: [2]: Average time spent waiting in a scheduler's queue while ready +# CHECK-SKIP: [3]: Average time elapsed from WB until retire stage + +# CHECK-SKIP: [0] [1] [2] [3] +# CHECK-SKIP: 0. 10 3.5 0.1 0.0 addl %eax, %eax diff --git a/llvm/tools/llvm-mca/CodeRegion.h b/llvm/tools/llvm-mca/CodeRegion.h index ce107fd8f3b6..5a2e8baa1f3e 100644 --- a/llvm/tools/llvm-mca/CodeRegion.h +++ b/llvm/tools/llvm-mca/CodeRegion.h @@ -59,6 +59,7 @@ #define LLVM_TOOLS_LLVM_MCA_CODEREGION_H #include "llvm/ADT/ArrayRef.h" +#include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" #include "llvm/ADT/StringMap.h" #include "llvm/ADT/StringRef.h" @@ -97,6 +98,20 @@ public: Instructions.emplace_back(Instruction); } + // Remove the given instructions from the set, for unsupported instructions + // being skipped. Returns an ArrayRef for the updated vector of Instructions. + [[nodiscard]] llvm::ArrayRef + dropInstructions(const llvm::SmallPtrSetImpl &Insts) { + if (Insts.empty()) + return Instructions; + Instructions.erase(std::remove_if(Instructions.begin(), Instructions.end(), + [&Insts](const llvm::MCInst &Inst) { + return Insts.contains(&Inst); + }), + Instructions.end()); + return Instructions; + } + llvm::SMLoc startLoc() const { return RangeStart; } llvm::SMLoc endLoc() const { return RangeEnd; } diff --git a/llvm/tools/llvm-mca/llvm-mca.cpp b/llvm/tools/llvm-mca/llvm-mca.cpp index eb71cffba6dd..e037c06b12a3 100644 --- a/llvm/tools/llvm-mca/llvm-mca.cpp +++ b/llvm/tools/llvm-mca/llvm-mca.cpp @@ -237,6 +237,11 @@ static cl::opt DisableInstrumentManager( "ignores instruments.)."), cl::cat(ViewOptions), cl::init(false)); +static cl::opt SkipUnsupportedInstructions( + "skip-unsupported-instructions", + cl::desc("Make unsupported instruction errors into warnings."), + cl::cat(ViewOptions), cl::init(false)); + namespace { const Target *getTarget(const char *ProgName) { @@ -558,6 +563,7 @@ int main(int argc, char **argv) { assert(MAB && "Unable to create asm backend!"); json::Object JSONOutput; + int NonEmptyRegions = 0; for (const std::unique_ptr &Region : Regions) { // Skip empty code regions. if (Region->empty()) @@ -571,14 +577,13 @@ int main(int argc, char **argv) { IPP->resetState(); - DenseMap> - InstToInstruments; + DenseMap> InstToInstruments; SmallVector> LoweredSequence; + SmallPtrSet DroppedInsts; for (const MCInst &MCI : Insts) { SMLoc Loc = MCI.getLoc(); const SmallVector Instruments = InstrumentRegions.getActiveInstruments(Loc); - InstToInstruments.insert({&MCI, Instruments}); Expected> Inst = IB.createInstruction(MCI, Instruments); @@ -588,7 +593,15 @@ int main(int argc, char **argv) { [&IP, &STI](const mca::InstructionError &IE) { std::string InstructionStr; raw_string_ostream SS(InstructionStr); - WithColor::error() << IE.Message << '\n'; + if (SkipUnsupportedInstructions) + WithColor::warning() + << IE.Message + << ", skipping with -skip-unsupported-instructions, " + "note accuracy will be impacted:\n"; + else + WithColor::error() + << IE.Message + << ", use -skip-unsupported-instructions to ignore.\n"; IP->printInst(&IE.Inst, 0, "", *STI, SS); SS.flush(); WithColor::note() @@ -597,14 +610,25 @@ int main(int argc, char **argv) { // Default case. WithColor::error() << toString(std::move(NewE)); } + if (SkipUnsupportedInstructions) { + DroppedInsts.insert(&MCI); + continue; + } return 1; } IPP->postProcessInstruction(Inst.get(), MCI); - + InstToInstruments.insert({&MCI, Instruments}); LoweredSequence.emplace_back(std::move(Inst.get())); } + Insts = Region->dropInstructions(DroppedInsts); + + // Skip empty regions. + if (Insts.empty()) + continue; + NonEmptyRegions++; + mca::CircularSourceMgr S(LoweredSequence, PrintInstructionTables ? 1 : Iterations); @@ -759,6 +783,11 @@ int main(int argc, char **argv) { ++RegionIdx; } + if (NonEmptyRegions == 0) { + WithColor::error() << "no assembly instructions found.\n"; + return 1; + } + if (PrintJson) TOF->os() << formatv("{0:2}", json::Value(std::move(JSONOutput))) << "\n"; -- GitLab From 41942c852e2be6c7c37f41e5128d446182fc9763 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 29 Apr 2024 08:40:09 +0100 Subject: [PATCH 191/301] [lldb[Docs] Reduce title noise in packets doc (#90183) This removes the "Brief" and "Description" subtitles and merges the text of both so that the contents listing is clearer. --- lldb/docs/resources/lldbgdbremote.md | 529 +++++++++------------------ 1 file changed, 168 insertions(+), 361 deletions(-) diff --git a/lldb/docs/resources/lldbgdbremote.md b/lldb/docs/resources/lldbgdbremote.md index 05e4f714f7f7..a9fa2a432b70 100644 --- a/lldb/docs/resources/lldbgdbremote.md +++ b/lldb/docs/resources/lldbgdbremote.md @@ -27,18 +27,8 @@ standard GDB remote protocol packets. ## QStartNoAckMode -### Brief - Try to enable no ACK mode to skip sending ACKs and NACKs. -### Priority To Implement - -High. Any GDB remote server that can implement this should if the -connection is reliable. This improves packet throughput and increases -the performance of the connection. - -### Description - Having to send an ACK/NACK after every packet slows things down a bit, so we have a way to disable ACK packets to minimize the traffic for reliable communication interfaces (like sockets). Below GDB or LLDB will send this @@ -52,17 +42,15 @@ read packet: $OK#9a send packet: + ``` -## QSupported - -### Brief - -Query the GDB remote server for features it supports - ### Priority To Implement -Optional. +High. Any GDB remote server that can implement this should if the +connection is reliable. This improves packet throughput and increases +the performance of the connection. -### Description +## QSupported + +Query the GDB remote server for features it supports QSupported is a standard GDB Remote Serial Protocol packet, but there are several additions to the response that lldb can parse. @@ -96,21 +84,14 @@ In the example above, three lldb extensions are shown: watchpoints, up to a pointer size, `sizeof(void*)`, a reasonable baseline assumption. +### Priority To Implement -## "A" - launch args packet +Optional. -### Brief +## "A" - launch args packet Launch a program using the supplied arguments -### Priority To Implement - -Low. Only needed if the remote target wants to launch a target after -making a connection to a GDB server that isn't already connected to -an inferior process. - -### Description - We have added support for the "set program arguments" packet where we can start a connection to a remote server and then later supply the path to the executable and the arguments to use when executing: @@ -130,14 +111,16 @@ The above packet helps when you have remote debugging abilities where you could launch a process on a remote host, this isn't needed for bare board debugging. -## qLaunchSuccess +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. -### Brief +## qLaunchSuccess Check whether launching a process with the `A` packet succeeded. -### Description - Returns the status of the last attempt to launch a process. Either `OK` if no error ocurred, or `E` followed by a string describing the error. @@ -148,8 +131,6 @@ High, launching processes is a key part of LLDB's platform mode. ## QEnvironment:NAME=VALUE -### Brief - Setup the environment up for a new child process that will soon be launched using the "A" packet. @@ -161,14 +142,6 @@ scan the environment strings before sending, prefer the `QEnvironmentHexEncoded` packet over `QEnvironment`, if it is available. -### Priority To Implement - -Low. Only needed if the remote target wants to launch a target after -making a connection to a GDB server that isn't already connected to -an inferior process. - -### Description - Both GDB and LLDB support passing down environment variables. Is it ok to respond with a `$#00` (unimplemented): ``` @@ -177,9 +150,13 @@ read packet: $OK#00 ``` This packet can be sent one or more times _prior_ to sending a "A" packet. -## QEnvironmentHexEncoded:HEX-ENCODING(NAME=VALUE) +### Priority To Implement + +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. -### Brief +## QEnvironmentHexEncoded:HEX-ENCODING(NAME=VALUE) Setup the environment up for a new child process that will soon be launched using the "A" packet. @@ -188,14 +165,6 @@ The only difference between this packet and `QEnvironment` is that the environment key-value pair is ascii hex encoded for transmission. This allows values with gdb-remote metacharacters like `#` to be sent. -### Priority To Implement - -Low. Only needed if the remote target wants to launch a target after -making a connection to a GDB server that isn't already connected to -an inferior process. - -### Description - Both GDB and LLDB support passing down environment variables. Is it ok to respond with a `$#00` (unimplemented): ``` @@ -204,9 +173,13 @@ read packet: $OK#00 ``` This packet can be sent one or more times _prior_ to sending a "A" packet. -## QEnableErrorStrings +### Priority To Implement -### Brief +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. + +## QEnableErrorStrings This packet enables reporting of Error strings in remote packet replies from the server to client. If the server supports this @@ -236,19 +209,9 @@ read packet: $OK#00 ## QSetSTDIN:\ / QSetSTDOUT:\ / QSetSTDERR:\ -### Brief - Setup where STDIN, STDOUT, and STDERR go prior to sending an "A" packet. -### Priority To Implement - -Low. Only needed if the remote target wants to launch a target after -making a connection to a GDB server that isn't already connected to -an inferior process. - -### Description - When launching a program through the GDB remote protocol with the "A" packet, you might also want to specify where stdin/out/err go: ``` @@ -258,19 +221,16 @@ QSetSTDERR: ``` These packets must be sent _prior_ to sending a "A" packet. -## QSetWorkingDir:\ - -### Brief - -Set the working directory prior to sending an "A" packet. - ### Priority To Implement Low. Only needed if the remote target wants to launch a target after making a connection to a GDB server that isn't already connected to an inferior process. -### Description + +## QSetWorkingDir:\ + +Set the working directory prior to sending an "A" packet. Or specify the working directory: ``` @@ -278,9 +238,13 @@ QSetWorkingDir: ``` This packet must be sent _prior_ to sending a "A" packet. -## qGetWorkingDir +### Priority To Implement -### Brief +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process. + +## qGetWorkingDir Get the current working directory of the platform stub in ASCII hex encoding. @@ -294,19 +258,8 @@ send: 2f4170706c65496e7465726e616c2f6c6c64622f73657474696e67732f342f546573745 ## QSetDisableASLR:\ -### Brief - Enable or disable ASLR on the next "A" packet. -### Priority To Implement - -Low. Only needed if the remote target wants to launch a target after -making a connection to a GDB server that isn't already connected to -an inferior process and if the target supports disabling ASLR -(Address space layout randomization). - -### Description - Or control if ASLR is enabled/disabled: ``` send packet: QSetDisableASLR:1 @@ -317,9 +270,14 @@ read packet: OK ``` This packet must be sent _prior_ to sending a "A" packet. -## QListThreadsInStopReply +### Priority To Implement -### Brief +Low. Only needed if the remote target wants to launch a target after +making a connection to a GDB server that isn't already connected to +an inferior process and if the target supports disabling ASLR +(Address space layout randomization). + +## QListThreadsInStopReply Enable the `threads:` and `thread-pcs:` data in the question-mark packet ("T packet") responses when the stub reports that a program has @@ -341,8 +299,6 @@ read packet: OK ## jLLDBTraceSupported -### Brief - Get the processor tracing type supported by the gdb-server for the current inferior. Responses might be different depending on the architecture and capabilities of the underlying OS. @@ -376,8 +332,6 @@ read packet: {"name":, "description":}/E;AAAAAAAA ## jLLDBTraceStart -### Brief - Start tracing a process or its threads using a provided tracing technology. The input and output are specified as JSON objects. In case of success, an OK response is returned, or an error otherwise. @@ -530,8 +484,6 @@ read packet: OK/E;AAAAAAAAA ## jLLDBTraceStop -### Brief - Stop tracing a process or its threads using a provided tracing technology. The input and output are specified as JSON objects. In case of success, an OK response is returned, or an error otherwise. @@ -583,8 +535,6 @@ read packet: OK/E;AAAAAAAAA ## jLLDBTraceGetState -### Brief - Get the current state of the process and its threads being traced by a given trace technology. The response is a JSON object with custom information depending on the trace technology. In case of errors, an @@ -690,8 +640,6 @@ read packet: {...object}/E;AAAAAAAAA ## jLLDBTraceGetBinaryData -### Brief - Get binary data given a trace technology and a data identifier. The input is specified as a JSON object and the response has the same format as the "binary memory read" (aka "x") packet. In case of failures, an error @@ -722,29 +670,8 @@ read packet: /E;AAAAAAAAA ## qRegisterInfo\ -### Brief - Discover register information from the remote GDB server. -### Priority To Implement - -High. Any target that can self describe its registers, should do so. -This means if new registers are ever added to a remote target, they -will get picked up automatically, and allows registers to change -depending on the actual CPU type that is used. - -NB: `qRegisterInfo` is deprecated in favor of the standard gdb remote -serial protocol register description method, -`qXfer:features:read:target.xml`. -If `qXfer:features:read:target.xml` is supported, `qRegisterInfo` does -not need to be implemented. The target.xml format is used by most -gdb RSP stubs whereas `qRegisterInfo` was an lldb-only design. -`qRegisterInfo` requires one packet per register and can have undesirable -performance costs at the start of a debug session, whereas target.xml -may be able to describe all registers in a single packet. - -### Description - With LLDB, for register information, remote GDB servers can add support for the "qRegisterInfoN" packet where "N" is a zero based base 16 register number that must start at zero and increase by one @@ -1010,19 +937,26 @@ The keys and values are detailed below: modifying the CPSR register can cause the r8 - r14 and cpsr value to change depending on if the mode has changed. +### Priority To Implement -## qPlatform_shell - -### Brief - -Run a command in a shell on the connected remote machine. +High. Any target that can self describe its registers, should do so. +This means if new registers are ever added to a remote target, they +will get picked up automatically, and allows registers to change +depending on the actual CPU type that is used. -### Priority To Implement +NB: `qRegisterInfo` is deprecated in favor of the standard gdb remote +serial protocol register description method, +`qXfer:features:read:target.xml`. +If `qXfer:features:read:target.xml` is supported, `qRegisterInfo` does +not need to be implemented. The target.xml format is used by most +gdb RSP stubs whereas `qRegisterInfo` was an lldb-only design. +`qRegisterInfo` requires one packet per register and can have undesirable +performance costs at the start of a debug session, whereas target.xml +may be able to describe all registers in a single packet. -High. This command allows LLDB clients to run arbitrary shell -commands on a remote host. +## qPlatform_shell -### Description +Run a command in a shell on the connected remote machine. The request consists of the command to be executed encoded in ASCII characters converted into hex bytes. @@ -1043,18 +977,14 @@ drwxrwxr-x 5 username groupname 4096 Aug 15 21:36 source.cpp -rw-r--r-- 1 username groupname 3190 Aug 12 16:46 Makefile ``` -## qPlatform_mkdir - -### Brief - -Creates a new directory on the connected remote machine. - ### Priority To Implement -Low. This command allows LLDB clients to create new directories on -a remote host. +High. This command allows LLDB clients to run arbitrary shell +commands on a remote host. + +## qPlatform_mkdir -### Description +Creates a new directory on the connected remote machine. Request: `qPlatform_mkdir:,` @@ -1067,20 +997,15 @@ Reply: (mkdir called successfully and returned with the given return code) * `Exx` (An error occurred) +### Priority To Implement -## vFile:chmod / qPlatform_chmod +Low. This command allows LLDB clients to create new directories on +a remote host. -### Brief +## vFile:chmod / qPlatform_chmod Change the permissions of a file on the connected remote machine. -### Priority To Implement - -Low. This command allows LLDB clients to change the permissions of -a file on the remote host. - -### Description - Request: `qPlatform_chmod:,` Reply: @@ -1088,19 +1013,13 @@ Reply: (chmod called successfully and returned with the given return code) * `Exx` (An error occurred) -## qHostInfo - -### Brief - -Get information about the host we are remotely connected to. - ### Priority To Implement -High. This packet is usually very easy to implement and can help -LLDB select the correct plug-ins for the job based on the target -triple information that is supplied. +Low. -### Description +## qHostInfo + +Get information about the host we are remotely connected to. LLDB supports a host info call that gets all sorts of details of the system that is being debugged: @@ -1147,20 +1066,16 @@ Key value pairs are one of: AArch64 can have different page table setups for low and high memory, and therefore a different number of bits used for addressing. -## qGDBServerVersion - -### Brief - -Get version information about this implementation of the gdb-remote -protocol. - ### Priority To Implement High. This packet is usually very easy to implement and can help -LLDB to work around bugs in a server's implementation when they -are found. +LLDB select the correct plug-ins for the job based on the target +triple information that is supplied. + +## qGDBServerVersion -### Description +Get version information about this implementation of the gdb-remote +protocol. The goal of this packet is to provide enough information about an implementation of the gdb-remote-protocol server that lldb can @@ -1192,9 +1107,13 @@ Suggested key names: * `major_version`: major version number * `minor_version`: minor version number -## qProcessInfo +### Priority To Implement -### Brief +High. This packet is usually very easy to implement and can help +LLDB to work around bugs in a server's implementation when they +are found. + +## qProcessInfo Get information about the process we are currently debugging. @@ -1211,8 +1130,6 @@ process to know what you're working with. All numeric fields return base 16 numbers without any "0x" prefix. -### Description - An i386 process: ``` send packet: $qProcessInfo#00 @@ -1249,24 +1166,9 @@ Key value pairs include: ## qShlibInfoAddr -### Brief - Get an address where the dynamic linker stores information about where shared libraries are loaded. -### Priority To Implement - -High if you have a dynamic loader plug-in in LLDB for your target -triple (see the "qHostInfo" packet) that can use this information. -Many times address load randomization can make it hard to detect -where the dynamic loader binary and data structures are located and -some platforms know, or can find out where this information is. - -Low if you have a debug target where all object and symbol files -contain static load addresses. - -### Description - LLDB and GDB both support the `qShlibInfoAddr` packet which is a hint to each debugger as to where to find the dynamic loader information. For darwin binaries that run in user land this is the address of the `all_image_infos` @@ -1278,12 +1180,29 @@ send packet: $qShlibInfoAddr#00 read packet: $7fff5fc40040#00 ``` -## qThreadStopInfo\ +### Priority To Implement -### Brief +High if you have a dynamic loader plug-in in LLDB for your target +triple (see the "qHostInfo" packet) that can use this information. +Many times address load randomization can make it hard to detect +where the dynamic loader binary and data structures are located and +some platforms know, or can find out where this information is. + +Low if you have a debug target where all object and symbol files +contain static load addresses. + +## qThreadStopInfo\ Get information about why a thread, whose ID is ``, is stopped. +LLDB tries to use the `qThreadStopInfo` packet which is formatted as +`qThreadStopInfo%x` where `%x` is the hex thread ID. This requests information +about why a thread is stopped. The response is the same as the stop reply +packets and tells us what happened to the other threads. The standard GDB +remote packets love to think that there is only _one_ reason that _one_ thread +stops at a time. This allows us to see why all threads stopped and allows us +to implement better multi-threaded debugging support. + ### Priority To Implement High if you need to support multi-threaded or multi-core debugging. @@ -1294,34 +1213,10 @@ threads (live system debug) / cores (JTAG) in your program have stopped and allows LLDB to display and control your program correctly. -### Description - -LLDB tries to use the `qThreadStopInfo` packet which is formatted as -`qThreadStopInfo%x` where `%x` is the hex thread ID. This requests information -about why a thread is stopped. The response is the same as the stop reply -packets and tells us what happened to the other threads. The standard GDB -remote packets love to think that there is only _one_ reason that _one_ thread -stops at a time. This allows us to see why all threads stopped and allows us -to implement better multi-threaded debugging support. - ## QThreadSuffixSupported -### Brief - Try to enable thread suffix support for the `g`, `G`, `p`, and `P` packets. -### Priority To Implement - -High. Adding a thread suffix allows us to read and write registers -more efficiently and stops us from having to select a thread with -one packet and then read registers with a second packet. It also -makes sure that no errors can occur where the debugger thinks it -already has a thread selected (see the `Hg` packet from the standard -GDB remote protocol documentation) yet the remote GDB server actually -has another thread selected. - -### Description - When reading thread registers, you currently need to set the current thread, then read the registers. This is kind of cumbersome, so we added the ability to query if the remote GDB server supports adding a `thread:;` @@ -1359,21 +1254,20 @@ read packet: .... We also added support for allocating and deallocating memory. We use this to allocate memory so we can run JITed code. -## _M\,\ - -### Brief - -Allocate memory on the remote target with the specified size and -permissions. - ### Priority To Implement -High if you want LLDB to be able to JIT code and run that code. JIT -code also needs data which is also allocated and tracked. +High. Adding a thread suffix allows us to read and write registers +more efficiently and stops us from having to select a thread with +one packet and then read registers with a second packet. It also +makes sure that no errors can occur where the debugger thinks it +already has a thread selected (see the `Hg` packet from the standard +GDB remote protocol documentation) yet the remote GDB server actually +has another thread selected. -Low if you don't support running JIT'ed code. +## _M\,\ -### Description +Allocate memory on the remote target with the specified size and +permissions. The allocate memory packet starts with `_M,`. It returns a raw big endian address value, or an empty response for unimplemented, or `EXX` for an error @@ -1395,13 +1289,6 @@ You request a size and give the permissions. This packet does NOT need to be implemented if you don't want to support running JITed code. The return value is just the address of the newly allocated memory as raw big endian hex bytes. -## _m\ - -### Brief - -Deallocate memory that was previously allocated using an allocate -memory pack. - ### Priority To Implement High if you want LLDB to be able to JIT code and run that code. JIT @@ -1409,30 +1296,26 @@ code also needs data which is also allocated and tracked. Low if you don't support running JIT'ed code. -### Description +## _m\ + +Deallocate memory that was previously allocated using an allocate +memory pack. The deallocate memory packet is `_m` where you pass in the address you got back from a previous call to the allocate memory packet. It returns `OK` if the memory was successfully deallocated, or `EXX`" for an error, or an empty response if not supported. -## qMemoryRegionInfo:\ - -### Brief +### Priority To Implement -Get information about the address range that contains ``. +High if you want LLDB to be able to JIT code and run that code. JIT +code also needs data which is also allocated and tracked. -### Priority To Implement +Low if you don't support running JIT'ed code. -Medium. This is nice to have, but it isn't necessary. It helps LLDB -do stack unwinding when we branch into memory that isn't executable. -If we can detect that the code we are stopped in isn't executable, -then we can recover registers for stack frames above the current -frame. Otherwise we must assume we are in some JIT'ed code (not JIT -code that LLDB has made) and assume that no registers are available -in higher stack frames. +## qMemoryRegionInfo:\ -### Description +Get information about the address range that contains ``. We added a way to get information for a memory region. The packet is: ``` @@ -1488,9 +1371,17 @@ For instance, with a macOS process which has nothing mapped in the first The lack of `permissions:` indicates that none of read/write/execute are valid for this region. -## "x" - Binary memory read +### Priority To Implement + +Medium. This is nice to have, but it isn't necessary. It helps LLDB +do stack unwinding when we branch into memory that isn't executable. +If we can detect that the code we are stopped in isn't executable, +then we can recover registers for stack frames above the current +frame. Otherwise we must assume we are in some JIT'ed code (not JIT +code that LLDB has made) and assume that no registers are available +in higher stack frames. -### Brief +## "x" - Binary memory read Like the `m` (read) and `M` (write) packets, this is a partner to the `X` (write binary data) packet, `x`. @@ -1524,8 +1415,6 @@ transport layer is assumed. ## Detach and stay stopped -### Description - We extended the "D" packet to specify that the monitor should keep the target suspended on detach. The normal behavior is to resume execution on detach. We will send: @@ -1546,8 +1435,6 @@ D ## QSaveRegisterState / QSaveRegisterState;thread:XXXX; -### Brief - The `QSaveRegisterState` packet tells the remote debugserver to save all registers and return a non-zero unique integer ID that represents these save registers. If thread suffixes are enabled the @@ -1576,8 +1463,6 @@ for the `QRestoreRegisterState` is added. ## QRestoreRegisterState:\ / QRestoreRegisterState:\;thread:XXXX; -### Brief - The `QRestoreRegisterState` packet tells the remote debugserver to restore all registers using the `save_id` which is an unsigned integer that was returned from a previous call to @@ -1601,8 +1486,6 @@ for the `QSaveRegisterState` is added. ## qFileLoadAddress:\ -### Brief - Get the load address of a memory mapped file. The load address is defined as the address of the first memory region what contains data mapped from the specified file. @@ -1620,8 +1503,6 @@ some object file in the rendezvous data structure. ## qModuleInfo:\;\ -### Brief - Get information for a module by given module path and architecture. ### Response @@ -1636,8 +1517,6 @@ UUID directly from inferior's memory. ## jModulesInfo:[{"file":"...",triple:"..."}, ...] -### Brief - Get information for a list of modules by given module path and architecture. @@ -1664,14 +1543,10 @@ the communication link has a non-negligible latency. ## Stop reply packet extensions -### Brief - This section describes some of the additional information you can specify in stop reply packets that help LLDB to know more detailed information about your threads. -### Description - Standard GDB remote stop reply packets are reply packets sent in response to a packet that made the program run. They come in the following forms: @@ -1880,19 +1755,15 @@ your debug session more reliable and informative. ## qfProcessInfo / qsProcessInfo (Platform Extension) -### Brief - Get the first process info (`qfProcessInfo`) or subsequent process info (`qsProcessInfo`) for one or more processes on the remote platform. The first call gets the first match and subsequent calls to `qsProcessInfo` gets the subsequent matches. Return an error `EXX`, where `XX` are two hex digits, when no more matches are available. -### Priority To Implement -Required. The `qfProcessInfo` packet can be followed by a `:` and + The `qfProcessInfo` packet can be followed by a `:` and some key value pairs. The key value pairs in the command are: - * `name` - `ascii-hex` - An ASCII hex string that contains the name of the process that will be matched. * `name_match` - `enum` - @@ -1933,9 +1804,11 @@ send packet: $qsProcessInfo#00 read packet: $E04#00 ``` -## qPathComplete (Platform Extension) +### Priority To Implement + +Required. -### Brief +## qPathComplete (Platform Extension) Get a list of matched disk files/directories by passing a boolean flag and a partial path. @@ -1958,8 +1831,6 @@ Paths denoting a directory should end with a directory separator (`/` or `\`. ## qKillSpawnedProcess (Platform Extension) -### Brief - Kill a process running on the target system. ### Example @@ -1972,13 +1843,9 @@ The request packet has the process ID in base 10. ## qLaunchGDBServer (Platform Extension) -### Brief - Have the remote platform launch a GDB server. -### Priority To Implement - -Required. The `qLaunchGDBServer` packet must be followed by a `:` and +The `qLaunchGDBServer` packet must be followed by a `:` and some key value pairs. The key value pairs in the command are: * `port` - `integer` - A string value containing the decimal port ID or zero if the port should be @@ -1986,11 +1853,6 @@ some key value pairs. The key value pairs in the command are: * `host` - `integer` - The host that connections should be limited to when the GDB server is connected to. -### Description - -The response consists of key/value pairs where the key is separated from the -values with colons and each pair is terminated with a semi colon. - Sample packet/response: ``` send packet: $qLaunchGDBServer:port:0;host:lldb.apple.com;#00 @@ -2004,20 +1866,15 @@ process was separately launched. The `port` key/value pair in the response lets clients know what port number to attach to in case zero was specified as the "port" in the sent command. +### Priority To Implement -## qProcessInfoPID:PID (Platform Extension) +Required. -### Brief +## qProcessInfoPID:PID (Platform Extension) Have the remote platform get detailed information on a process by ID. PID is specified as a decimal integer. -### Priority To Implement - -Optional. - -### Description - The response consists of key/value pairs where the key is separated from the values with colons and each pair is terminated with a semi colon. @@ -2037,9 +1894,11 @@ send packet: $qProcessInfoPID:60050#00 read packet: $pid:60050;ppid:59948;uid:7746;gid:11;euid:7746;egid:11;name:6c6c6462;triple:x86_64-apple-macosx;#00 ``` -## vAttachName +### Priority To Implement + +Optional. -### Brief +## vAttachName Same as `vAttach`, except instead of a `pid` you send a process name. @@ -2051,8 +1910,6 @@ it if attaching to a process by name makes sense for your environment. ## vAttachWait -### Brief - Same as `vAttachName`, except that the stub should wait for the next instance of a process by that name to be launched and attach to that. @@ -2063,8 +1920,6 @@ gracefully if the packet is not supported. ## qAttachOrWaitSupported -### Brief - This is a binary "is it supported" query. Return OK if you support `vAttachOrWait`. @@ -2076,8 +1931,6 @@ will do the right thing. ## vAttachOrWait -### Brief - Same as `vAttachWait`, except that the stub will attach to a process by name if it exists, and if it does not, it will wait for a process of that name to appear and attach to it. @@ -2094,20 +1947,10 @@ support this packet. ## jThreadExtendedInfo -### Brief - This packet, which takes its arguments as JSON and sends its reply as JSON, allows the gdb remote stub to provide additional information about a given thread. -### Priority To Implement - -Low. This packet is only needed if the gdb remote stub wants to -provide interesting additional information about a thread for the -user. - -### Description - This packet takes its arguments in [JSON](http://www.json.org). At a minimum, a thread must be specified, for example: ``` @@ -2155,9 +1998,13 @@ like: jThreadExtendedInfo:{"thread":612910}] ``` -## QEnableCompression +### Priority To Implement + +Low. This packet is only needed if the gdb remote stub wants to +provide interesting additional information about a thread for the +user. -### Brief +## QEnableCompression This packet enables compression of the packets that the debug stub sends to lldb. If the debug stub can support compression, it indictes this in the reply of the @@ -2218,8 +2065,6 @@ Example compression algorithms that may be used include: ## jGetLoadedDynamicLibrariesInfos -### Brief - This packet asks the remote debug stub to send the details about libraries being added/removed from the process as a performance optimization. @@ -2293,8 +2138,6 @@ STUB REPLIES: ${"images": } ``` -### Description - This is similar to the `qXfer:libraries:read` packet, and it could be argued that it should be merged into that packet. A separate packet was created primarily because lldb needs to specify the @@ -2313,18 +2156,8 @@ executable loaded. ## jThreadsInfo -### Brief - Ask for the server for thread stop information of all threads. -### Priority To Implement - -Low. This is a performance optimization, which speeds up debugging by avoiding -multiple round-trips for retrieving thread information. The information from this -packet can be retrieved using a combination of `qThreadStopInfo` and `m` packets. - -### Description - The data in this packet is very similar to the stop reply packets, but is packaged in JSON and uses JSON arrays where applicable. The JSON output looks like: ``` @@ -2379,9 +2212,13 @@ On macOS with debugserver, we expedite the frame pointer backchain for a thread the previous FP and PC), and follow the backchain. Most backtraces on macOS and iOS now don't require us to read any memory! -## jGetSharedCacheInfo +### Priority To Implement -### Brief +Low. This is a performance optimization, which speeds up debugging by avoiding +multiple round-trips for retrieving thread information. The information from this +packet can be retrieved using a combination of `qThreadStopInfo` and `m` packets. + +## jGetSharedCacheInfo This packet asks the remote debug stub to send the details about the inferior's shared cache. The shared cache is a collection of common libraries/frameworks that @@ -2402,17 +2239,8 @@ them from the inferior process. ## qQueryGDBServer -### Brief - Ask the platform for the list of gdbservers we have to connect -### Priority To Implement - -Low. The packet is required to support connecting to gdbserver started -by the platform instance automatically. - -### Description - If the remote platform automatically started one or more gdbserver instance (without lldb asking it) then it have to return the list of port number or socket name for each of them what can be used by lldb to connect to those instances. @@ -2430,29 +2258,28 @@ Example packet: ] ``` -## QSetDetachOnError +### Priority To Implement -### Brief +Low. The packet is required to support connecting to gdbserver started +by the platform instance automatically. + +## QSetDetachOnError Sets what the server should do when the communication channel with LLDB goes down. Either kill the inferior process (`0`) or remove breakpoints and detach (`1`). +The data in this packet is a single a character, which should be `0` if the +inferior process should be killed, or `1` if the server should remove all +breakpoints and detach from the inferior. + ### Priority To Implement Low. Only required if the target wants to keep the inferior process alive when the communication channel goes down. -### Description - -The data in this packet is a single a character, which should be `0` if the -inferior process should be killed, or `1` if the server should remove all -breakpoints and detach from the inferior. - ## jGetDyldProcessState -### Brief - This packet fetches the process launch state, as reported by libdyld on Darwin systems, most importantly to indicate when the system libraries have initialized sufficiently to safely call utility functions. @@ -2476,8 +2303,6 @@ mismatches or extensions. ### vFile:size -#### Brief - Get the size of a file on the target system, filename in ASCII hex. #### Example @@ -2492,8 +2317,6 @@ response is `F` followed by the file size in base 16. ### vFile:mode -#### Brief - Get the mode bits of a file on the target system, filename in ASCII hex. #### Example @@ -2509,8 +2332,6 @@ correspond to `0755` in octal. ### vFile:unlink -#### Brief - Remove a file on the target system. #### Example @@ -2527,8 +2348,6 @@ value of errno if unlink failed. ### vFile:symlink -#### Brief - Create a symbolic link (symlink, soft-link) on the target system. #### Example @@ -2544,8 +2363,6 @@ optionally followed by the value of errno if it failed, also base 16. ### vFile:open -#### Brief - Open a file on the remote system and return the file descriptor of it. #### Example @@ -2568,8 +2385,6 @@ response is `F` followed by the opened file descriptor in base 16. ### vFile:close -#### Brief - Close a previously opened file descriptor. #### Example @@ -2584,8 +2399,6 @@ errno is base 16. ### vFile:pread -#### Brief - Read data from an opened file descriptor. #### Example @@ -2605,8 +2418,6 @@ semicolon, followed by the data in the binary-escaped-data encoding. ### vFile:pwrite -#### Brief - Write data to a previously opened file descriptor. #### Example @@ -2625,8 +2436,6 @@ Response is `F`, followed by the number of bytes written (base 16). ### vFile:MD5 -#### Brief - Generate an MD5 hash of the file at the given path. #### Example @@ -2648,8 +2457,6 @@ or failed to hash. ### vFile:exists -#### Brief - Check whether the file at the given path exists. #### Example -- GitLab From ab12bba0aad800c1805eca2ea937da958c1854c8 Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Mon, 29 Apr 2024 15:51:49 +0800 Subject: [PATCH 192/301] [CGP] Drop poison-generating flags after hoisting (#90382) See the following case: ``` define i8 @src1(i8 %x) { entry: %cmp = icmp eq i8 %x, -1 br i1 %cmp, label %exit, label %if.then if.then: %inc = add nuw nsw i8 %x, 1 br label %exit exit: %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ] ret i8 %retval } define i8 @tgt1(i8 %x) { entry: %inc = add nuw nsw i8 %x, 1 %0 = icmp eq i8 %inc, 0 br i1 %0, label %exit, label %if.then if.then: ; preds = %entry br label %exit exit: ; preds = %if.then, %entry %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ] ret i8 %retval } ``` `optimizeBranch` converts `icmp eq X, -1` into cmp to zero on RISC-V and hoists the add into the entry block. Poison-generating flags should be dropped as they don't still hold. Proof: https://alive2.llvm.org/ce/z/sP7mvK Fixes https://github.com/llvm/llvm-project/issues/90380 --- llvm/lib/CodeGen/CodeGenPrepare.cpp | 2 + .../CodeGenPrepare/ARM/branch-on-zero.ll | 23 ++++++ .../CodeGenPrepare/RISCV/convert-to-eqz.ll | 80 +++++++++++++++++++ 3 files changed, 105 insertions(+) create mode 100644 llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll diff --git a/llvm/lib/CodeGen/CodeGenPrepare.cpp b/llvm/lib/CodeGen/CodeGenPrepare.cpp index 8eaf78157550..339a1f1f2f00 100644 --- a/llvm/lib/CodeGen/CodeGenPrepare.cpp +++ b/llvm/lib/CodeGen/CodeGenPrepare.cpp @@ -8270,6 +8270,7 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI, IRBuilder<> Builder(Branch); if (UI->getParent() != Branch->getParent()) UI->moveBefore(Branch); + UI->dropPoisonGeneratingFlags(); Value *NewCmp = Builder.CreateCmp(ICmpInst::ICMP_EQ, UI, ConstantInt::get(UI->getType(), 0)); LLVM_DEBUG(dbgs() << "Converting " << *Cmp << "\n"); @@ -8283,6 +8284,7 @@ static bool optimizeBranch(BranchInst *Branch, const TargetLowering &TLI, IRBuilder<> Builder(Branch); if (UI->getParent() != Branch->getParent()) UI->moveBefore(Branch); + UI->dropPoisonGeneratingFlags(); Value *NewCmp = Builder.CreateCmp(Cmp->getPredicate(), UI, ConstantInt::get(UI->getType(), 0)); LLVM_DEBUG(dbgs() << "Converting " << *Cmp << "\n"); diff --git a/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll index ff5cef7e781f..25dfb3c53a07 100644 --- a/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll +++ b/llvm/test/Transforms/CodeGenPrepare/ARM/branch-on-zero.ll @@ -211,6 +211,29 @@ else: ret i32 %l } +define i32 @sub10_else_drop_nuw(i32 %a) { +; CHECK-LABEL: @sub10_else_drop_nuw( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[L:%.*]] = sub i32 [[A:%.*]], 10 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i32 [[L]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label [[THEN:%.*]], label [[ELSE:%.*]] +; CHECK: then: +; CHECK-NEXT: ret i32 0 +; CHECK: else: +; CHECK-NEXT: ret i32 [[L]] +; +entry: + %c = icmp eq i32 %a, 10 + br i1 %c, label %then, label %else + +then: + ret i32 0 + +else: + %l = sub nuw i32 %a, 10 + ret i32 %l +} + define i32 @subm10_then(i32 %a) { ; CHECK-LABEL: @subm10_then( ; CHECK-NEXT: entry: diff --git a/llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll b/llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll new file mode 100644 index 000000000000..a6909d149134 --- /dev/null +++ b/llvm/test/Transforms/CodeGenPrepare/RISCV/convert-to-eqz.ll @@ -0,0 +1,80 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -codegenprepare -S -mtriple=riscv64 < %s | FileCheck %s + +define i8 @hoist_add(i8 %x) { +; CHECK-LABEL: define i8 @hoist_add( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[INC:%.*]] = add i8 [[X]], 1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[INC]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT:%.*]], label [[IF_THEN:%.*]] +; CHECK: if.then: +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: [[RETVAL:%.*]] = phi i8 [ [[INC]], [[IF_THEN]] ], [ -1, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i8 [[RETVAL]] +; +entry: + %cmp = icmp eq i8 %x, -1 + br i1 %cmp, label %exit, label %if.then + +if.then: + %inc = add nuw nsw i8 %x, 1 + br label %exit + +exit: + %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ] + ret i8 %retval +} + +define i8 @hoist_lshr(i8 %x) { +; CHECK-LABEL: define i8 @hoist_lshr( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[INC:%.*]] = lshr i8 [[X]], 3 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[INC]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT:%.*]], label [[IF_THEN:%.*]] +; CHECK: if.then: +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: [[RETVAL:%.*]] = phi i8 [ [[INC]], [[IF_THEN]] ], [ -1, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i8 [[RETVAL]] +; +entry: + %cmp = icmp ult i8 %x, 8 + br i1 %cmp, label %exit, label %if.then + +if.then: + %inc = lshr exact i8 %x, 3 + br label %exit + +exit: + %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ] + ret i8 %retval +} + +define i8 @nomove_add(i8 %x) { +; CHECK-LABEL: define i8 @nomove_add( +; CHECK-SAME: i8 [[X:%.*]]) { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[INC:%.*]] = add i8 [[X]], 1 +; CHECK-NEXT: [[TMP0:%.*]] = icmp eq i8 [[INC]], 0 +; CHECK-NEXT: br i1 [[TMP0]], label [[EXIT:%.*]], label [[IF_THEN:%.*]] +; CHECK: if.then: +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: [[RETVAL:%.*]] = phi i8 [ [[INC]], [[IF_THEN]] ], [ -1, [[ENTRY:%.*]] ] +; CHECK-NEXT: ret i8 [[RETVAL]] +; +entry: + %inc = add nuw nsw i8 %x, 1 + %cmp = icmp eq i8 %x, -1 + br i1 %cmp, label %exit, label %if.then + +if.then: + br label %exit + +exit: + %retval = phi i8 [ %inc, %if.then ], [ -1, %entry ] + ret i8 %retval +} -- GitLab From a19a4113df3e9a3ca3747075da6de21901796524 Mon Sep 17 00:00:00 2001 From: Peter Waller Date: Mon, 29 Apr 2024 09:01:38 +0100 Subject: [PATCH 193/301] [llvm-mca] Fix -skip-unsupported-instruction tests on Windows Builder alerted me to the failing test, attempt #1 in the blind. --- .../X86/BtVer2/skip-unsupported-instructions-none-remain.s | 4 ++-- llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s b/llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s index a8f78159c199..0d67f53e12f1 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/skip-unsupported-instructions-none-remain.s @@ -1,5 +1,5 @@ -# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -skip-unsupported-instructions %s |& FileCheck --check-prefixes=CHECK-ALL,CHECK-SKIP %s -# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s |& FileCheck --check-prefixes=CHECK-ALL,CHECK-ERROR %s +# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -skip-unsupported-instructions %s 2>&1 | FileCheck --check-prefixes=CHECK-ALL,CHECK-SKIP %s +# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s 2>&1 | FileCheck --check-prefixes=CHECK-ALL,CHECK-ERROR %s # Test defends that if all instructions are skipped leaving an empty input, an error is printed. diff --git a/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s b/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s index eec6de6648a6..3690a1101be9 100644 --- a/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s +++ b/llvm/test/tools/llvm-mca/X86/BtVer2/unsupported-instruction.s @@ -1,5 +1,5 @@ -# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -skip-unsupported-instructions -timeline %s |& FileCheck --check-prefix=CHECK-SKIP %s -# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s |& FileCheck --check-prefix=CHECK-ERROR %s +# RUN: llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 -skip-unsupported-instructions -timeline %s 2>&1 | FileCheck --check-prefix=CHECK-SKIP %s +# RUN: not llvm-mca -mtriple=x86_64-unknown-unknown -mcpu=btver2 %s 2>&1 | FileCheck --check-prefix=CHECK-ERROR %s # Test checks that unsupported instructions exit with an error, unless -skip-unsupported-instructions is passed, in which case the remaining instructions should be analysed. -- GitLab From f029da5cfce66e2d460d5f54b17582810a9111ad Mon Sep 17 00:00:00 2001 From: Abid Qadeer Date: Mon, 29 Apr 2024 09:44:19 +0100 Subject: [PATCH 194/301] [flang] Improve debug info for functions. (#90083) This PR improves the debug information for functions in the following ways: 1. Get line number information from FuncOp and remove hard-coded line numbers. 2. Use proper type for function signature. I have a added a type converter. Currently, it is very limited but will be enhanced with time. 3. Use de-constructed function name. --- .../lib/Optimizer/Transforms/AddDebugInfo.cpp | 36 ++++++++--- flang/lib/Optimizer/Transforms/CMakeLists.txt | 1 + .../Transforms/DebugTypeGenerator.cpp | 63 +++++++++++++++++++ .../Optimizer/Transforms/DebugTypeGenerator.h | 40 ++++++++++++ flang/test/Transforms/debug-fn-info.f90 | 43 +++++++++++++ .../Transforms/debug-line-table-inc-file.fir | 2 +- 6 files changed, 174 insertions(+), 11 deletions(-) create mode 100644 flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp create mode 100644 flang/lib/Optimizer/Transforms/DebugTypeGenerator.h create mode 100644 flang/test/Transforms/debug-fn-info.f90 diff --git a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp index 18d98a11ef3c..5108469cb6c8 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp @@ -11,6 +11,7 @@ /// This pass populates some debug information for the module and functions. //===----------------------------------------------------------------------===// +#include "DebugTypeGenerator.h" #include "flang/Common/Version.h" #include "flang/Optimizer/Builder/FIRBuilder.h" #include "flang/Optimizer/Builder/Todo.h" @@ -106,14 +107,27 @@ void AddDebugInfoPass::runOnOperation() { filePath = llvm::sys::path::parent_path(funcLoc.getFilename().getValue()); } - mlir::StringAttr funcName = + mlir::StringAttr fullName = mlir::StringAttr::get(context, funcOp.getName()); - mlir::LLVM::DIBasicTypeAttr bT = mlir::LLVM::DIBasicTypeAttr::get( - context, llvm::dwarf::DW_TAG_base_type, "void", /*sizeInBits=*/0, - /*encoding=*/1); - // FIXME: Provide proper type for subroutine + auto result = fir::NameUniquer::deconstruct(funcOp.getName()); + mlir::StringAttr funcName = + mlir::StringAttr::get(context, result.second.name); + + llvm::SmallVector types; + fir::DebugTypeGenerator typeGen(module); + for (auto resTy : funcOp.getResultTypes()) { + auto tyAttr = + typeGen.convertType(resTy, fileAttr, cuAttr, funcOp.getLoc()); + types.push_back(tyAttr); + } + for (auto inTy : funcOp.getArgumentTypes()) { + auto tyAttr = typeGen.convertType(fir::unwrapRefType(inTy), fileAttr, + cuAttr, funcOp.getLoc()); + types.push_back(tyAttr); + } + mlir::LLVM::DISubroutineTypeAttr subTypeAttr = - mlir::LLVM::DISubroutineTypeAttr::get(context, CC, {bT, bT}); + mlir::LLVM::DISubroutineTypeAttr::get(context, CC, types); mlir::LLVM::DIFileAttr funcFileAttr = mlir::LLVM::DIFileAttr::get(context, fileName, filePath); @@ -130,11 +144,13 @@ void AddDebugInfoPass::runOnOperation() { subprogramFlags = subprogramFlags | mlir::LLVM::DISubprogramFlags::Definition; } - // FIXME: Provide proper line and scopeline. + unsigned line = 1; + if (auto funcLoc = l.dyn_cast()) + line = funcLoc.getLine(); + auto spAttr = mlir::LLVM::DISubprogramAttr::get( - context, id, compilationUnit, fileAttr, funcName, funcName, - funcFileAttr, /*line=*/1, /*scopeline=*/1, subprogramFlags, - subTypeAttr); + context, id, compilationUnit, fileAttr, funcName, fullName, + funcFileAttr, line, line, subprogramFlags, subTypeAttr); funcOp->setLoc(builder.getFusedLoc({funcOp->getLoc()}, spAttr)); }); } diff --git a/flang/lib/Optimizer/Transforms/CMakeLists.txt b/flang/lib/Optimizer/Transforms/CMakeLists.txt index fc08d67540ce..5a542f237f8f 100644 --- a/flang/lib/Optimizer/Transforms/CMakeLists.txt +++ b/flang/lib/Optimizer/Transforms/CMakeLists.txt @@ -22,6 +22,7 @@ add_flang_library(FIRTransforms OMPMarkDeclareTarget.cpp VScaleAttr.cpp FunctionAttr.cpp + DebugTypeGenerator.cpp DEPENDS FIRDialect diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp new file mode 100644 index 000000000000..0057e08f8a76 --- /dev/null +++ b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp @@ -0,0 +1,63 @@ +//===-- DebugTypeGenerator.cpp -- type conversion ---------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/ +// +//===----------------------------------------------------------------------===// + +#define DEBUG_TYPE "flang-debug-type-generator" + +#include "DebugTypeGenerator.h" +#include "llvm/ADT/ScopeExit.h" +#include "llvm/BinaryFormat/Dwarf.h" +#include "llvm/Support/Debug.h" + +namespace fir { + +DebugTypeGenerator::DebugTypeGenerator(mlir::ModuleOp m) + : module(m), kindMapping(getKindMapping(m)) { + LLVM_DEBUG(llvm::dbgs() << "DITypeAttr generator\n"); +} + +static mlir::LLVM::DITypeAttr genPlaceholderType(mlir::MLIRContext *context) { + return mlir::LLVM::DIBasicTypeAttr::get( + context, llvm::dwarf::DW_TAG_base_type, "void", 32, 1); +} + +static mlir::LLVM::DITypeAttr genBasicType(mlir::MLIRContext *context, + mlir::StringAttr name, + unsigned bitSize, + unsigned decoding) { + return mlir::LLVM::DIBasicTypeAttr::get( + context, llvm::dwarf::DW_TAG_base_type, name, bitSize, decoding); +} + +mlir::LLVM::DITypeAttr +DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr, + mlir::LLVM::DIScopeAttr scope, + mlir::Location loc) { + mlir::MLIRContext *context = module.getContext(); + if (Ty.isIntOrIndex()) { + return genBasicType(context, mlir::StringAttr::get(context, "integer"), + Ty.getIntOrFloatBitWidth(), llvm::dwarf::DW_ATE_signed); + } else if (Ty.isa() || Ty.isa()) { + return genBasicType(context, mlir::StringAttr::get(context, "real"), + Ty.getIntOrFloatBitWidth(), llvm::dwarf::DW_ATE_float); + } else if (auto logTy = Ty.dyn_cast_or_null()) { + return genBasicType(context, + mlir::StringAttr::get(context, logTy.getMnemonic()), + kindMapping.getLogicalBitsize(logTy.getFKind()), + llvm::dwarf::DW_ATE_boolean); + } else { + // FIXME: These types are currently unhandled. We are generating a + // placeholder type to allow us to test supported bits. + return genPlaceholderType(context); + } +} + +} // namespace fir diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h new file mode 100644 index 000000000000..5a2bb201db47 --- /dev/null +++ b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h @@ -0,0 +1,40 @@ +//===-- DebugTypeGenerator.h -- type conversion ------------------- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/ +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_OPTIMIZER_TRANSFORMS_DEBUGTYPEGENERATOR_H +#define FORTRAN_OPTIMIZER_TRANSFORMS_DEBUGTYPEGENERATOR_H + +#include "flang/Optimizer/Dialect/FIRType.h" +#include "flang/Optimizer/Dialect/Support/FIRContext.h" +#include "flang/Optimizer/Dialect/Support/KindMapping.h" +#include "llvm/Support/Debug.h" + +namespace fir { + +/// This converts FIR/mlir type to DITypeAttr. +class DebugTypeGenerator { +public: + DebugTypeGenerator(mlir::ModuleOp module); + + mlir::LLVM::DITypeAttr convertType(mlir::Type Ty, + mlir::LLVM::DIFileAttr fileAttr, + mlir::LLVM::DIScopeAttr scope, + mlir::Location loc); + +private: + mlir::ModuleOp module; + KindMapping kindMapping; +}; + +} // namespace fir + +#endif // FORTRAN_OPTIMIZER_TRANSFORMS_DEBUGTYPEGENERATOR_H diff --git a/flang/test/Transforms/debug-fn-info.f90 b/flang/test/Transforms/debug-fn-info.f90 new file mode 100644 index 000000000000..c1a817312c95 --- /dev/null +++ b/flang/test/Transforms/debug-fn-info.f90 @@ -0,0 +1,43 @@ +! RUN: %flang_fc1 -emit-fir -debug-info-kind=standalone -mmlir --mlir-print-debuginfo %s -o - | fir-opt --add-debug-info --mlir-print-debuginfo | FileCheck %s + + +! CHECK-DAG: #[[INT8:.*]] = #llvm.di_basic_type +! CHECK-DAG: #[[INT4:.*]] = #llvm.di_basic_type +! CHECK-DAG: #[[REAL8:.*]] = #llvm.di_basic_type +! CHECK-DAG: #[[LOG1:.*]] = #llvm.di_basic_type +! CHECK-DAG: #[[REAL4:.*]] = #llvm.di_basic_type +! CHECK-DAG: #[[LOG4:.*]] = #llvm.di_basic_type +! CHECK: #[[TY1:.*]] = #llvm.di_subroutine_type +! CHECK: #[[TY2:.*]] = #llvm.di_subroutine_type + +program mn + integer(kind=4) :: i4 + integer(kind=8) :: i8 + real(kind=4) :: r4 + real(kind=8) :: r8 + logical(kind=1) :: l1 + logical(kind=4) :: l4 + i8 = fn1(i4, r8, l1) + i4 = fn2(i8, r4, l4) +contains + ! CHECK: #di_subprogram1 = #llvm.di_subprogram + function fn1(a, b, c) result (res) + implicit none + integer(kind=4), intent(in) :: a + real(kind=8), intent(in) :: b + logical(kind=1), intent(in) :: c + integer(kind=8) :: res + res = a + b + end function + +! CHECK: #di_subprogram2 = #llvm.di_subprogram + function fn2(a, b, c) result (res) + implicit none + integer(kind=8), intent(in) :: a + real(kind=4), intent(in) :: b + logical(kind=4), intent(in) :: c + integer(kind=4) :: res + res = a + b + end function +end program + diff --git a/flang/test/Transforms/debug-line-table-inc-file.fir b/flang/test/Transforms/debug-line-table-inc-file.fir index dc75482d4f8a..d7f60a1a86db 100644 --- a/flang/test/Transforms/debug-line-table-inc-file.fir +++ b/flang/test/Transforms/debug-line-table-inc-file.fir @@ -31,7 +31,7 @@ module attributes {} { // CHECK: #[[LOC_INC_FILE:.*]] = loc("{{.*}}inc.f90":1:1) // CHECK: #[[LOC_FILE:.*]] = loc("{{.*}}simple.f90":3:1) // CHECK: #[[DI_CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #[[DI_FILE]], producer = "flang{{.*}}", isOptimized = false, emissionKind = LineTablesOnly> -// CHECK: #[[DI_SP_INC:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "_QPsinc", linkageName = "_QPsinc", file = #[[DI_INC_FILE]], {{.*}}> +// CHECK: #[[DI_SP_INC:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "sinc", linkageName = "_QPsinc", file = #[[DI_INC_FILE]], {{.*}}> // CHECK: #[[DI_SP:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "_QQmain", linkageName = "_QQmain", file = #[[DI_FILE]], {{.*}}> // CHECK: #[[FUSED_LOC_INC_FILE]] = loc(fused<#[[DI_SP_INC]]>[#[[LOC_INC_FILE]]]) // CHECK: #[[FUSED_LOC_FILE]] = loc(fused<#[[DI_SP]]>[#[[LOC_FILE]]]) -- GitLab From 16bd10a38730fed27a3bf111076b8ef7a7e7b3ee Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 29 Apr 2024 09:36:42 +0100 Subject: [PATCH 195/301] Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more... This reverts: b3c55b707110084a9f50a16aade34c3be6fa18da - "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" (because it updates a test case that I don't know how to resolve the conflict for) 8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 - "[DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)" 73472c5996716cda0dbb3ddb788304e0e7e6a323 - "[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)" Due to a test suite failure on AArch64 when compiling for SVE. https://lab.llvm.org/buildbot/#/builders/197/builds/13955 clang: ../llvm/llvm/include/llvm/CodeGen/ValueTypes.h:307: MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed. --- llvm/include/llvm/CodeGen/ISDOpcodes.h | 1 - llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 26 - .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 +- llvm/test/CodeGen/AArch64/combine-mul.ll | 7 +- llvm/test/CodeGen/AMDGPU/div_i128.ll | 96 ++- llvm/test/CodeGen/AMDGPU/rem_i128.ll | 475 +++++++------ .../lasx/ir-instruction/insertelement.ll | 42 +- .../lsx/ir-instruction/insertelement.ll | 42 +- llvm/test/CodeGen/RISCV/alu64.ll | 2 +- .../CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll | 16 +- llvm/test/CodeGen/RISCV/bfloat-convert.ll | 108 +-- llvm/test/CodeGen/RISCV/double-convert.ll | 111 ++-- .../CodeGen/RISCV/double-round-conv-sat.ll | 138 ++-- llvm/test/CodeGen/RISCV/float-convert.ll | 158 ++--- .../CodeGen/RISCV/float-round-conv-sat.ll | 288 ++++---- llvm/test/CodeGen/RISCV/forced-atomics.ll | 4 +- llvm/test/CodeGen/RISCV/fpclamptosat.ll | 4 +- llvm/test/CodeGen/RISCV/half-convert.ll | 268 ++++---- .../test/CodeGen/RISCV/half-round-conv-sat.ll | 624 +++++++++--------- llvm/test/CodeGen/RISCV/iabs.ll | 4 +- .../CodeGen/RISCV/rvv/fpclamptosat_vec.ll | 521 ++++++++------- llvm/test/CodeGen/X86/abdu-vector-128.ll | 54 +- .../CodeGen/X86/apx/kmov-postrapseudos.ll | 10 +- .../CodeGen/X86/avx512-broadcast-arith.ll | 10 +- llvm/test/CodeGen/X86/combine-mul.ll | 8 +- .../X86/div-rem-pair-recomposition-signed.ll | 377 +++++------ llvm/test/CodeGen/X86/fold-masked-merge.ll | 4 +- llvm/test/CodeGen/X86/freeze-binary.ll | 50 +- llvm/test/CodeGen/X86/freeze-combine.ll | 16 +- llvm/test/CodeGen/X86/gfni-funnel-shifts.ll | 4 +- llvm/test/CodeGen/X86/gfni-rotates.ll | 14 +- llvm/test/CodeGen/X86/known-never-zero.ll | 30 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 94 +-- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 32 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 80 +-- llvm/test/CodeGen/X86/pr38539.ll | 202 +++--- llvm/test/CodeGen/X86/pr62286.ll | 31 +- .../CodeGen/X86/scheduler-backtracking.ll | 2 +- llvm/test/CodeGen/X86/sdiv_fix_sat.ll | 250 +++---- .../test/CodeGen/X86/setcc-non-simple-type.ll | 78 +-- llvm/test/CodeGen/X86/vec_saddo.ll | 14 +- llvm/test/CodeGen/X86/vec_ssubo.ll | 14 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 14 +- llvm/test/CodeGen/X86/vec_usubo.ll | 14 +- llvm/test/CodeGen/X86/vector-bo-select.ll | 10 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 86 +-- llvm/test/CodeGen/X86/vector-fshr-256.ll | 28 +- llvm/test/CodeGen/X86/vector-fshr-sub128.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 12 +- 49 files changed, 2298 insertions(+), 2204 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index 6429947958ee..078a936b061a 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -205,7 +205,6 @@ enum NodeType { /// CopyFromReg - This node indicates that the input value is a virtual or /// physical register that is defined outside of the scope of this /// SelectionDAG. The register is available from the RegisterSDNode object. - /// Note that CopyFromReg is considered as also freezing the value. CopyFromReg, /// UNDEF - An undefined node. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index 326a004d06f2..f8949b926922 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15459,12 +15459,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false)) return N0; - // We currently avoid folding freeze over SRA/SRL, due to the problems seen - // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for - // example https://reviews.llvm.org/D136529#4120959. - if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) - return SDValue(); - // Fold freeze(op(x, ...)) -> op(freeze(x), ...). // Try to push freeze through instructions that propagate but don't produce // poison as far as possible. If an operand of freeze follows three @@ -15481,26 +15475,6 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { N0.getOpcode() == ISD::BUILD_PAIR || N0.getOpcode() == ISD::CONCAT_VECTORS; - // Avoid turning a BUILD_VECTOR that can be recognized as "all zeros", "all - // ones" or "constant" into something that depends on FrozenUndef. We can - // instead pick undef values to keep those properties, while at the same time - // folding away the freeze. - // If we implement a more general solution for folding away freeze(undef) in - // the future, then this special handling can be removed. - if (N0.getOpcode() == ISD::BUILD_VECTOR) { - SDLoc DL(N0); - MVT VT = N0.getSimpleValueType(); - if (llvm::ISD::isBuildVectorAllOnes(N0.getNode())) - return DAG.getAllOnesConstant(DL, VT); - if (llvm::ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { - SmallVector NewVecC; - for (const SDValue &Op : N0->op_values()) - NewVecC.push_back( - Op.isUndef() ? DAG.getConstant(0, DL, Op.getValueType()) : Op); - return DAG.getBuildVector(VT, DL, NewVecC); - } - } - SmallSetVector MaybePoisonOperands; for (SDValue Op : N0->ops()) { if (DAG.isGuaranteedNotToBeUndefOrPoison(Op, /*PoisonOnly*/ false, diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index dfbfaa8c894f..224c0c5ee970 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5063,7 +5063,6 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::VALUETYPE: case ISD::FrameIndex: case ISD::TargetFrameIndex: - case ISD::CopyFromReg: return true; case ISD::UNDEF: @@ -5137,16 +5136,6 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::FREEZE: case ISD::CONCAT_VECTORS: case ISD::INSERT_SUBVECTOR: - case ISD::SADDSAT: - case ISD::UADDSAT: - case ISD::SSUBSAT: - case ISD::USUBSAT: - case ISD::MULHU: - case ISD::MULHS: - case ISD::SMIN: - case ISD::SMAX: - case ISD::UMIN: - case ISD::UMAX: case ISD::AND: case ISD::XOR: case ISD::ROTL: @@ -5167,7 +5156,6 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::BUILD_PAIR: return false; - case ISD::SELECT_CC: case ISD::SETCC: { // Integer setcc cannot create undef or poison. if (Op.getOperand(0).getValueType().isInteger()) @@ -5177,8 +5165,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, // based on options and flags. The options and flags also cause special // nonan condition codes to be used. Those condition codes may be preserved // even if the nonan flag is dropped somewhere. - unsigned CCOp = Opcode == ISD::SETCC ? 2 : 4; - ISD::CondCode CCCode = cast(Op.getOperand(CCOp))->get(); + ISD::CondCode CCCode = cast(Op.getOperand(2))->get(); if (((unsigned)CCCode & 0x10U)) return true; @@ -5195,8 +5182,6 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, return false; case ISD::SHL: - case ISD::SRL: - case ISD::SRA: // If the max shift amount isn't in range, then the shift can create poison. return !getValidMaximumShiftAmountConstant(Op, DemandedElts); diff --git a/llvm/test/CodeGen/AArch64/combine-mul.ll b/llvm/test/CodeGen/AArch64/combine-mul.ll index c49e5ae6620a..a2b042530809 100644 --- a/llvm/test/CodeGen/AArch64/combine-mul.ll +++ b/llvm/test/CodeGen/AArch64/combine-mul.ll @@ -44,7 +44,8 @@ define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) { define i64 @combine_mul_self_demandedbits(i64 %x) { ; CHECK-LABEL: combine_mul_self_demandedbits: ; CHECK: // %bb.0: -; CHECK-NEXT: mul x0, x0, x0 +; CHECK-NEXT: mul x8, x0, x0 +; CHECK-NEXT: and x0, x8, #0xfffffffffffffffd ; CHECK-NEXT: ret %1 = mul i64 %x, %x %2 = and i64 %1, -3 @@ -76,7 +77,7 @@ define i8 @one_demanded_bit(i8 %x) { define <2 x i64> @one_demanded_bit_splat(<2 x i64> %x) { ; CHECK-LABEL: one_demanded_bit_splat: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #32 // =0x20 +; CHECK-NEXT: mov w8, #32 ; CHECK-NEXT: shl v0.2d, v0.2d, #5 ; CHECK-NEXT: dup v1.2d, x8 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b @@ -130,7 +131,7 @@ define i32 @squared_demanded_2_low_bits(i32 %x) { define <2 x i64> @squared_demanded_2_low_bits_splat(<2 x i64> %x) { ; CHECK-LABEL: squared_demanded_2_low_bits_splat: ; CHECK: // %bb.0: -; CHECK-NEXT: mov x8, #-2 // =0xfffffffffffffffe +; CHECK-NEXT: mov x8, #-2 ; CHECK-NEXT: dup v1.2d, x8 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index b2f9bf89d9ec..cf99b5d80e13 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -282,21 +282,21 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v16, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v15 -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v10, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v4 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v6, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v10, v4, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v10, v4, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v6, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 ; GFX9-O0-NEXT: v_xor_b32_e64 v1, v5, v1 @@ -312,21 +312,21 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v7 -; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 killed $vgpr7_vgpr8 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v11 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v8 +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v11 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v12 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v3 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v8, vcc, v8, v5, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v3, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v7, vcc, v2, v5, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v5, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v8, v3, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v8 +; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v2 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v7 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v7 ; GFX9-O0-NEXT: v_xor_b32_e64 v5, v5, v6 ; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v4 ; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec @@ -339,26 +339,18 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v14 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v12 ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v2 ; GFX9-O0-NEXT: v_or_b32_e64 v3, v8, v7 @@ -411,8 +403,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 -; GFX9-O0-NEXT: s_mov_b64 s[12:13], s[6:7] -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[12:13] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[6:7] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[12:13] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 @@ -448,8 +439,7 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[8:9] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[6:7] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[8:9] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v11 @@ -700,10 +690,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload @@ -913,14 +903,14 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(9) ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) @@ -1038,10 +1028,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll index b068d87c4d6f..6ba66ccf7186 100644 --- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll @@ -242,137 +242,130 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0: ; %bb.0: ; %_udiv-special-cases ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-O0-NEXT: ; implicit-def: $vgpr8 : SGPR spill to VGPR lane -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v7 -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v2 -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v0 +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v6 +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v2 +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v1 +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v0 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: s_waitcnt vmcnt(1) -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v7 +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v6 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v9 +; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v7 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v3 +; GFX9-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec +; GFX9-O0-NEXT: s_waitcnt vmcnt(1) +; GFX9-O0-NEXT: v_mov_b32_e32 v15, v1 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: s_mov_b32 s4, 63 -; GFX9-O0-NEXT: v_mov_b32_e32 v11, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v8 -; GFX9-O0-NEXT: v_ashrrev_i64 v[11:12], s4, v[10:11] -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v15 +; GFX9-O0-NEXT: v_ashrrev_i64 v[12:13], s4, v[6:7] +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v12 -; GFX9-O0-NEXT: v_mov_b32_e32 v13, v11 -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v13 +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v7 -; GFX9-O0-NEXT: v_mov_b32_e32 v13, v6 -; GFX9-O0-NEXT: v_ashrrev_i64 v[15:16], s4, v[13:14] -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v12 -; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v10 -; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v11 -; GFX9-O0-NEXT: v_xor_b32_e64 v13, v8, v12 +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v9 +; GFX9-O0-NEXT: v_ashrrev_i64 v[6:7], s4, v[6:7] +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v15 +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v13 +; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v10 +; GFX9-O0-NEXT: v_mov_b32_e32 v11, v14 +; GFX9-O0-NEXT: v_xor_b32_e64 v13, v11, v12 ; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v3 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v2 -; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v10 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v12 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v7 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v16 -; GFX9-O0-NEXT: v_xor_b32_e64 v9, v8, v3 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v15 -; GFX9-O0-NEXT: v_xor_b32_e64 v7, v7, v6 -; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 -; GFX9-O0-NEXT: v_xor_b32_e64 v9, v9, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v5 +; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v10 ; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v4, v4, v6 -; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v1 -; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_xor_b32_e64 v15, v4, v12 +; GFX9-O0-NEXT: ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v16, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v7 +; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v4 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v8 +; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec +; GFX9-O0-NEXT: v_xor_b32_e64 v7, v5, v6 +; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 +; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v4 +; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec +; GFX9-O0-NEXT: v_xor_b32_e64 v2, v2, v6 +; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v15 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v11, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v12 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v10, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v11, v12, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v11, v12, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v10, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v4 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v8 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v6 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v3, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v5, v6, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v3, vcc, v2, v3, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v4, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v4 +; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v2 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v3 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v14 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 ; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill @@ -445,8 +438,7 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 -; GFX9-O0-NEXT: s_mov_b64 s[12:13], s[6:7] -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[12:13] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[6:7] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[12:13] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 @@ -482,8 +474,7 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 -; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[8:9] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[6:7] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[8:9] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v11 @@ -598,27 +589,27 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_readlane_b32 s5, v0, 5 ; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-O0-NEXT: ; %bb.2: ; %Flow -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(6) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_5 ; GFX9-O0-NEXT: .LBB0_3: ; %Flow2 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -633,22 +624,22 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_9 ; GFX9-O0-NEXT: .LBB0_4: ; %udiv-loop-exit -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 1 ; GFX9-O0-NEXT: s_waitcnt vmcnt(2) ; GFX9-O0-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1] @@ -688,27 +679,27 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_readlane_b32 s4, v8, 6 ; GFX9-O0-NEXT: v_readlane_b32 s5, v8, 7 ; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5] -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_4 ; GFX9-O0-NEXT: .LBB0_6: ; %udiv-do-while ; GFX9-O0-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -718,30 +709,30 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: v_readlane_b32 s6, v16, 8 ; GFX9-O0-NEXT: v_readlane_b32 s7, v16, 9 -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 63 ; GFX9-O0-NEXT: s_waitcnt vmcnt(16) ; GFX9-O0-NEXT: v_lshrrev_b64 v[29:30], s4, v[2:3] @@ -881,24 +872,24 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v2 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v0 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v15 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v14 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v13 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v12 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[6:7], s[4:5] ; GFX9-O0-NEXT: v_writelane_b32 v16, s6, 4 ; GFX9-O0-NEXT: v_writelane_b32 v16, s7, 5 @@ -908,42 +899,42 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX9-O0-NEXT: s_cbranch_execnz .LBB0_6 ; GFX9-O0-NEXT: s_branch .LBB0_1 ; GFX9-O0-NEXT: .LBB0_7: ; %udiv-preheader -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] @@ -1027,12 +1018,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v13, v17 ; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v15, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 @@ -1043,30 +1034,30 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_6 ; GFX9-O0-NEXT: .LBB0_8: ; %udiv-bb1 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -1108,14 +1099,14 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v2 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v1 -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v10 -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b32 s4, 0x7f ; GFX9-O0-NEXT: v_sub_u32_e64 v3, s4, v4 ; GFX9-O0-NEXT: v_lshlrev_b64 v[5:6], v3, v[11:12] @@ -1161,12 +1152,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v3 -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v10 ; GFX9-O0-NEXT: v_or_b32_e64 v3, v3, v4 @@ -1181,18 +1172,18 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v4, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, s7 -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[6:7], exec ; GFX9-O0-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5] ; GFX9-O0-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7] @@ -1212,18 +1203,18 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 32 ; GFX9-O0-NEXT: s_waitcnt vmcnt(2) ; GFX9-O0-NEXT: v_lshrrev_b64 v[0:1], s4, v[5:6] @@ -1495,11 +1486,11 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v5 ; GFX9-O0-NEXT: ; kill: killed $vgpr4 ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll index 25106b456d2f..6629d3440549 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll @@ -123,9 +123,10 @@ define void @insert_32xi8_idx(ptr %src, ptr %dst, i8 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 4, 0 -; CHECK-NEXT: st.b $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 4, 0 +; CHECK-NEXT: st.b $a2, $a3, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -149,9 +150,10 @@ define void @insert_16xi16_idx(ptr %src, ptr %dst, i16 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 4, 1 -; CHECK-NEXT: st.h $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 4, 1 +; CHECK-NEXT: st.h $a2, $a3, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -175,9 +177,10 @@ define void @insert_8xi32_idx(ptr %src, ptr %dst, i32 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 4, 2 -; CHECK-NEXT: st.w $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 4, 2 +; CHECK-NEXT: st.w $a2, $a3, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -201,9 +204,10 @@ define void @insert_4xi64_idx(ptr %src, ptr %dst, i64 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 4, 3 -; CHECK-NEXT: st.d $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 4, 3 +; CHECK-NEXT: st.d $a2, $a3, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -227,9 +231,10 @@ define void @insert_8xfloat_idx(ptr %src, ptr %dst, float %in, i32 %idx) nounwin ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr1, $a0, 0 ; CHECK-NEXT: xvst $xr1, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 2 -; CHECK-NEXT: fst.s $fa0, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 +; CHECK-NEXT: addi.d $a2, $sp, 0 +; CHECK-NEXT: bstrins.d $a2, $a0, 4, 2 +; CHECK-NEXT: fst.s $fa0, $a2, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -253,9 +258,10 @@ define void @insert_4xdouble_idx(ptr %src, ptr %dst, double %in, i32 %idx) nounw ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr1, $a0, 0 ; CHECK-NEXT: xvst $xr1, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a2, 4, 3 -; CHECK-NEXT: fst.d $fa0, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 +; CHECK-NEXT: addi.d $a2, $sp, 0 +; CHECK-NEXT: bstrins.d $a2, $a0, 4, 3 +; CHECK-NEXT: fst.d $fa0, $a2, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll index 7f232073ae12..19171b7d8ed7 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll @@ -87,9 +87,10 @@ define void @insert_16xi8_idx(ptr %src, ptr %dst, i8 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 3, 0 -; CHECK-NEXT: st.b $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 3, 0 +; CHECK-NEXT: st.b $a2, $a3, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -106,9 +107,10 @@ define void @insert_8xi16_idx(ptr %src, ptr %dst, i16 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 3, 1 -; CHECK-NEXT: st.h $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 3, 1 +; CHECK-NEXT: st.h $a2, $a3, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -125,9 +127,10 @@ define void @insert_4xi32_idx(ptr %src, ptr %dst, i32 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 3, 2 -; CHECK-NEXT: st.w $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 3, 2 +; CHECK-NEXT: st.w $a2, $a3, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -144,9 +147,10 @@ define void @insert_2xi64_idx(ptr %src, ptr %dst, i64 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a3, 3, 3 -; CHECK-NEXT: st.d $a2, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 +; CHECK-NEXT: addi.d $a3, $sp, 0 +; CHECK-NEXT: bstrins.d $a3, $a0, 3, 3 +; CHECK-NEXT: st.d $a2, $a3, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -163,9 +167,10 @@ define void @insert_4xfloat_idx(ptr %src, ptr %dst, float %ins, i32 %idx) nounwi ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr1, $a0, 0 ; CHECK-NEXT: vst $vr1, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a2, 3, 2 -; CHECK-NEXT: fst.s $fa0, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 +; CHECK-NEXT: addi.d $a2, $sp, 0 +; CHECK-NEXT: bstrins.d $a2, $a0, 3, 2 +; CHECK-NEXT: fst.s $fa0, $a2, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -182,9 +187,10 @@ define void @insert_2xdouble_idx(ptr %src, ptr %dst, double %ins, i32 %idx) noun ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr1, $a0, 0 ; CHECK-NEXT: vst $vr1, $sp, 0 -; CHECK-NEXT: addi.d $a0, $sp, 0 -; CHECK-NEXT: bstrins.d $a0, $a2, 3, 3 -; CHECK-NEXT: fst.d $fa0, $a0, 0 +; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 +; CHECK-NEXT: addi.d $a2, $sp, 0 +; CHECK-NEXT: bstrins.d $a2, $a0, 3, 3 +; CHECK-NEXT: fst.d $fa0, $a2, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll index f032756e007b..d2ee80e6aa95 100644 --- a/llvm/test/CodeGen/RISCV/alu64.ll +++ b/llvm/test/CodeGen/RISCV/alu64.ll @@ -57,8 +57,8 @@ define i64 @sltiu(i64 %a) nounwind { ; ; RV32I-LABEL: sltiu: ; RV32I: # %bb.0: -; RV32I-NEXT: sltiu a0, a0, 3 ; RV32I-NEXT: seqz a1, a1 +; RV32I-NEXT: sltiu a0, a0, 3 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll index a5a2ae79966c..f96e1bad2e38 100644 --- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll @@ -372,10 +372,10 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; RV32IA-NEXT: # =>This Loop Header: Depth=1 ; RV32IA-NEXT: # Child Loop BB2_3 Depth 2 ; RV32IA-NEXT: mv a3, a2 -; RV32IA-NEXT: addi a2, a2, 1 -; RV32IA-NEXT: sltu a4, a3, a1 -; RV32IA-NEXT: neg a4, a4 -; RV32IA-NEXT: and a4, a4, a2 +; RV32IA-NEXT: addi a4, a2, 1 +; RV32IA-NEXT: sltu a2, a2, a1 +; RV32IA-NEXT: neg a2, a2 +; RV32IA-NEXT: and a4, a2, a4 ; RV32IA-NEXT: .LBB2_3: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 @@ -607,10 +607,10 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; RV64IA-NEXT: # =>This Loop Header: Depth=1 ; RV64IA-NEXT: # Child Loop BB3_3 Depth 2 ; RV64IA-NEXT: mv a3, a2 -; RV64IA-NEXT: addi a2, a2, 1 -; RV64IA-NEXT: sltu a4, a3, a1 -; RV64IA-NEXT: neg a4, a4 -; RV64IA-NEXT: and a4, a4, a2 +; RV64IA-NEXT: addi a4, a2, 1 +; RV64IA-NEXT: sltu a2, a2, a1 +; RV64IA-NEXT: neg a2, a2 +; RV64IA-NEXT: and a4, a2, a4 ; RV64IA-NEXT: .LBB3_3: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll index 770dcccee882..9e2b0b5c3cbb 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-convert.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-convert.ll @@ -456,80 +456,92 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind { define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind { ; RV32IZFBFMIN-LABEL: fcvt_l_bf16_sat: ; RV32IZFBFMIN: # %bb.0: # %start -; RV32IZFBFMIN-NEXT: addi sp, sp, -16 -; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: addi sp, sp, -32 +; RV32IZFBFMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: lui a0, %hi(.LCPI10_0) +; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0 +; RV32IZFBFMIN-NEXT: flt.s s0, fa5, fs0 +; RV32IZFBFMIN-NEXT: neg s1, s0 ; RV32IZFBFMIN-NEXT: lui a0, 913408 ; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFBFMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFBFMIN-NEXT: fle.s s2, fa5, fs0 +; RV32IZFBFMIN-NEXT: neg s3, s2 ; RV32IZFBFMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFBFMIN-NEXT: call __fixsfdi +; RV32IZFBFMIN-NEXT: and a0, s3, a0 +; RV32IZFBFMIN-NEXT: or a0, s1, a0 +; RV32IZFBFMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IZFBFMIN-NEXT: neg a2, a2 ; RV32IZFBFMIN-NEXT: lui a4, 524288 -; RV32IZFBFMIN-NEXT: lui a2, 524288 -; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_2 +; RV32IZFBFMIN-NEXT: lui a3, 524288 +; RV32IZFBFMIN-NEXT: beqz s2, .LBB10_2 ; RV32IZFBFMIN-NEXT: # %bb.1: # %start -; RV32IZFBFMIN-NEXT: mv a2, a1 +; RV32IZFBFMIN-NEXT: mv a3, a1 ; RV32IZFBFMIN-NEXT: .LBB10_2: # %start -; RV32IZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0) -; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) -; RV32IZFBFMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFBFMIN-NEXT: beqz a3, .LBB10_4 +; RV32IZFBFMIN-NEXT: and a0, a2, a0 +; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_4 ; RV32IZFBFMIN-NEXT: # %bb.3: -; RV32IZFBFMIN-NEXT: addi a2, a4, -1 +; RV32IZFBFMIN-NEXT: addi a3, a4, -1 ; RV32IZFBFMIN-NEXT: .LBB10_4: # %start -; RV32IZFBFMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IZFBFMIN-NEXT: neg a4, a1 -; RV32IZFBFMIN-NEXT: and a1, a4, a2 -; RV32IZFBFMIN-NEXT: neg a2, a3 -; RV32IZFBFMIN-NEXT: neg a3, s0 -; RV32IZFBFMIN-NEXT: and a0, a3, a0 -; RV32IZFBFMIN-NEXT: or a0, a2, a0 -; RV32IZFBFMIN-NEXT: and a0, a4, a0 -; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: addi sp, sp, 16 +; RV32IZFBFMIN-NEXT: and a1, a2, a3 +; RV32IZFBFMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: addi sp, sp, 32 ; RV32IZFBFMIN-NEXT: ret ; ; R32IDZFBFMIN-LABEL: fcvt_l_bf16_sat: ; R32IDZFBFMIN: # %bb.0: # %start -; R32IDZFBFMIN-NEXT: addi sp, sp, -16 -; R32IDZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: addi sp, sp, -32 +; R32IDZFBFMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; R32IDZFBFMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill +; R32IDZFBFMIN-NEXT: lui a0, %hi(.LCPI10_0) +; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0 +; R32IDZFBFMIN-NEXT: flt.s s0, fa5, fs0 +; R32IDZFBFMIN-NEXT: neg s1, s0 ; R32IDZFBFMIN-NEXT: lui a0, 913408 ; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a0 -; R32IDZFBFMIN-NEXT: fle.s s0, fa5, fs0 +; R32IDZFBFMIN-NEXT: fle.s s2, fa5, fs0 +; R32IDZFBFMIN-NEXT: neg s3, s2 ; R32IDZFBFMIN-NEXT: fmv.s fa0, fs0 ; R32IDZFBFMIN-NEXT: call __fixsfdi +; R32IDZFBFMIN-NEXT: and a0, s3, a0 +; R32IDZFBFMIN-NEXT: or a0, s1, a0 +; R32IDZFBFMIN-NEXT: feq.s a2, fs0, fs0 +; R32IDZFBFMIN-NEXT: neg a2, a2 ; R32IDZFBFMIN-NEXT: lui a4, 524288 -; R32IDZFBFMIN-NEXT: lui a2, 524288 -; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_2 +; R32IDZFBFMIN-NEXT: lui a3, 524288 +; R32IDZFBFMIN-NEXT: beqz s2, .LBB10_2 ; R32IDZFBFMIN-NEXT: # %bb.1: # %start -; R32IDZFBFMIN-NEXT: mv a2, a1 +; R32IDZFBFMIN-NEXT: mv a3, a1 ; R32IDZFBFMIN-NEXT: .LBB10_2: # %start -; R32IDZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0) -; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) -; R32IDZFBFMIN-NEXT: flt.s a3, fa5, fs0 -; R32IDZFBFMIN-NEXT: beqz a3, .LBB10_4 +; R32IDZFBFMIN-NEXT: and a0, a2, a0 +; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_4 ; R32IDZFBFMIN-NEXT: # %bb.3: -; R32IDZFBFMIN-NEXT: addi a2, a4, -1 +; R32IDZFBFMIN-NEXT: addi a3, a4, -1 ; R32IDZFBFMIN-NEXT: .LBB10_4: # %start -; R32IDZFBFMIN-NEXT: feq.s a1, fs0, fs0 -; R32IDZFBFMIN-NEXT: neg a4, a1 -; R32IDZFBFMIN-NEXT: and a1, a4, a2 -; R32IDZFBFMIN-NEXT: neg a2, a3 -; R32IDZFBFMIN-NEXT: neg a3, s0 -; R32IDZFBFMIN-NEXT: and a0, a3, a0 -; R32IDZFBFMIN-NEXT: or a0, a2, a0 -; R32IDZFBFMIN-NEXT: and a0, a4, a0 -; R32IDZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: and a1, a2, a3 +; R32IDZFBFMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; R32IDZFBFMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; R32IDZFBFMIN-NEXT: addi sp, sp, 16 +; R32IDZFBFMIN-NEXT: addi sp, sp, 32 ; R32IDZFBFMIN-NEXT: ret ; ; RV32ID-LABEL: fcvt_l_bf16_sat: diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll index 6024a29da33d..c147d6ec6d9b 100644 --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -692,27 +692,28 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a4, 524288 +; RV32IFD-NEXT: lui a3, 524288 +; RV32IFD-NEXT: li a4, 1 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB12_2 +; RV32IFD-NEXT: bne s0, a4, .LBB12_2 ; RV32IFD-NEXT: # %bb.1: # %start ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB12_2: # %start ; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1) -; RV32IFD-NEXT: flt.d a3, fa5, fs0 -; RV32IFD-NEXT: beqz a3, .LBB12_4 +; RV32IFD-NEXT: flt.d a4, fa5, fs0 +; RV32IFD-NEXT: beqz a4, .LBB12_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a4, -1 +; RV32IFD-NEXT: addi a2, a3, -1 ; RV32IFD-NEXT: .LBB12_4: # %start ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a4, a1 -; RV32IFD-NEXT: and a1, a4, a2 -; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a3, a1 +; RV32IFD-NEXT: and a1, a3, a2 +; RV32IFD-NEXT: neg a2, a4 +; RV32IFD-NEXT: neg a4, s0 ; RV32IFD-NEXT: and a0, a4, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -789,32 +790,33 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 -; RV32I-NEXT: lui a3, 278016 -; RV32I-NEXT: addi a3, a3, -1 -; RV32I-NEXT: li a2, -1 -; RV32I-NEXT: call __gtdf2 -; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 802304 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: mv s3, a0 +; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: call __fixdfdi -; RV32I-NEXT: mv s4, a0 -; RV32I-NEXT: mv s5, a1 -; RV32I-NEXT: lui a0, 524288 -; RV32I-NEXT: bgez s3, .LBB12_2 +; RV32I-NEXT: mv s3, a0 +; RV32I-NEXT: mv s4, a1 +; RV32I-NEXT: lui s6, 524288 +; RV32I-NEXT: bgez s2, .LBB12_2 ; RV32I-NEXT: # %bb.1: # %start -; RV32I-NEXT: lui s5, 524288 +; RV32I-NEXT: lui s4, 524288 ; RV32I-NEXT: .LBB12_2: # %start -; RV32I-NEXT: blez s2, .LBB12_4 +; RV32I-NEXT: lui a3, 278016 +; RV32I-NEXT: addi a3, a3, -1 +; RV32I-NEXT: li a2, -1 +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s0 +; RV32I-NEXT: call __gtdf2 +; RV32I-NEXT: mv s5, a0 +; RV32I-NEXT: blez a0, .LBB12_4 ; RV32I-NEXT: # %bb.3: # %start -; RV32I-NEXT: addi s5, a0, -1 +; RV32I-NEXT: addi s4, s6, -1 ; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 @@ -823,11 +825,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 -; RV32I-NEXT: and a1, a0, s5 -; RV32I-NEXT: slti a2, s3, 0 +; RV32I-NEXT: and a1, a0, s4 +; RV32I-NEXT: slti a2, s2, 0 ; RV32I-NEXT: addi a2, a2, -1 -; RV32I-NEXT: and a2, a2, s4 -; RV32I-NEXT: sgtz a3, s2 +; RV32I-NEXT: and a2, a2, s3 +; RV32I-NEXT: sgtz a3, s5 ; RV32I-NEXT: neg a3, a3 ; RV32I-NEXT: or a2, a3, a2 ; RV32I-NEXT: and a0, a0, a2 @@ -838,6 +840,7 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; @@ -946,23 +949,22 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IFD-NEXT: fmv.d fs0, fa0 +; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IFD-NEXT: lui a0, %hi(.LCPI14_0) +; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a0) +; RV32IFD-NEXT: flt.d a0, fa5, fa0 +; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s0, a0 +; RV32IFD-NEXT: neg s1, a0 ; RV32IFD-NEXT: call __fixunsdfdi -; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0) -; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2) -; RV32IFD-NEXT: and a0, s0, a0 -; RV32IFD-NEXT: flt.d a2, fa5, fs0 -; RV32IFD-NEXT: neg a2, a2 -; RV32IFD-NEXT: or a0, a2, a0 -; RV32IFD-NEXT: and a1, s0, a1 -; RV32IFD-NEXT: or a1, a2, a1 +; RV32IFD-NEXT: and a0, s1, a0 +; RV32IFD-NEXT: or a0, s0, a0 +; RV32IFD-NEXT: and a1, s1, a1 +; RV32IFD-NEXT: or a1, s0, a1 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload +; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; @@ -981,24 +983,27 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: mv s1, a1 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: mv s0, a0 +; RV32IZFINXZDINX-NEXT: fle.d a0, a2, s0 +; RV32IZFINXZDINX-NEXT: neg s2, a0 +; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero -; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0) -; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4) -; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a4) -; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 +; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI14_0) +; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI14_0+4)(a2) +; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI14_0)(a2) +; RV32IZFINXZDINX-NEXT: and a0, s2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: and a0, a2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 -; RV32IZFINXZDINX-NEXT: neg a3, a3 -; RV32IZFINXZDINX-NEXT: or a0, a3, a0 -; RV32IZFINXZDINX-NEXT: and a1, a2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a3, a1 +; RV32IZFINXZDINX-NEXT: or a0, a2, a0 +; RV32IZFINXZDINX-NEXT: and a1, s2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a2, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll index 927eee2e9e54..f1c56b320b76 100644 --- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll @@ -53,27 +53,28 @@ define i64 @test_floor_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a4, 524288 +; RV32IFD-NEXT: lui a3, 524288 +; RV32IFD-NEXT: li a4, 1 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB1_2 +; RV32IFD-NEXT: bne s0, a4, .LBB1_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB1_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI1_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_1)(a1) -; RV32IFD-NEXT: flt.d a3, fa5, fs0 -; RV32IFD-NEXT: beqz a3, .LBB1_4 +; RV32IFD-NEXT: flt.d a4, fa5, fs0 +; RV32IFD-NEXT: beqz a4, .LBB1_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a4, -1 +; RV32IFD-NEXT: addi a2, a3, -1 ; RV32IFD-NEXT: .LBB1_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a4, a1 -; RV32IFD-NEXT: and a1, a4, a2 -; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a3, a1 +; RV32IFD-NEXT: and a1, a3, a2 +; RV32IFD-NEXT: neg a2, a4 +; RV32IFD-NEXT: neg a4, s0 ; RV32IFD-NEXT: and a0, a4, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -298,27 +299,28 @@ define i64 @test_ceil_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a4, 524288 +; RV32IFD-NEXT: lui a3, 524288 +; RV32IFD-NEXT: li a4, 1 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB5_2 +; RV32IFD-NEXT: bne s0, a4, .LBB5_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB5_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI5_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_1)(a1) -; RV32IFD-NEXT: flt.d a3, fa5, fs0 -; RV32IFD-NEXT: beqz a3, .LBB5_4 +; RV32IFD-NEXT: flt.d a4, fa5, fs0 +; RV32IFD-NEXT: beqz a4, .LBB5_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a4, -1 +; RV32IFD-NEXT: addi a2, a3, -1 ; RV32IFD-NEXT: .LBB5_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a4, a1 -; RV32IFD-NEXT: and a1, a4, a2 -; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a3, a1 +; RV32IFD-NEXT: and a1, a3, a2 +; RV32IFD-NEXT: neg a2, a4 +; RV32IFD-NEXT: neg a4, s0 ; RV32IFD-NEXT: and a0, a4, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -543,27 +545,28 @@ define i64 @test_trunc_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a4, 524288 +; RV32IFD-NEXT: lui a3, 524288 +; RV32IFD-NEXT: li a4, 1 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB9_2 +; RV32IFD-NEXT: bne s0, a4, .LBB9_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB9_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI9_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_1)(a1) -; RV32IFD-NEXT: flt.d a3, fa5, fs0 -; RV32IFD-NEXT: beqz a3, .LBB9_4 +; RV32IFD-NEXT: flt.d a4, fa5, fs0 +; RV32IFD-NEXT: beqz a4, .LBB9_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a4, -1 +; RV32IFD-NEXT: addi a2, a3, -1 ; RV32IFD-NEXT: .LBB9_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a4, a1 -; RV32IFD-NEXT: and a1, a4, a2 -; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a3, a1 +; RV32IFD-NEXT: and a1, a3, a2 +; RV32IFD-NEXT: neg a2, a4 +; RV32IFD-NEXT: neg a4, s0 ; RV32IFD-NEXT: and a0, a4, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -788,27 +791,28 @@ define i64 @test_round_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a4, 524288 +; RV32IFD-NEXT: lui a3, 524288 +; RV32IFD-NEXT: li a4, 1 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB13_2 +; RV32IFD-NEXT: bne s0, a4, .LBB13_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB13_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI13_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_1)(a1) -; RV32IFD-NEXT: flt.d a3, fa5, fs0 -; RV32IFD-NEXT: beqz a3, .LBB13_4 +; RV32IFD-NEXT: flt.d a4, fa5, fs0 +; RV32IFD-NEXT: beqz a4, .LBB13_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a4, -1 +; RV32IFD-NEXT: addi a2, a3, -1 ; RV32IFD-NEXT: .LBB13_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a4, a1 -; RV32IFD-NEXT: and a1, a4, a2 -; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a3, a1 +; RV32IFD-NEXT: and a1, a3, a2 +; RV32IFD-NEXT: neg a2, a4 +; RV32IFD-NEXT: neg a4, s0 ; RV32IFD-NEXT: and a0, a4, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -1033,27 +1037,28 @@ define i64 @test_roundeven_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a4, 524288 +; RV32IFD-NEXT: lui a3, 524288 +; RV32IFD-NEXT: li a4, 1 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB17_2 +; RV32IFD-NEXT: bne s0, a4, .LBB17_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB17_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI17_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_1)(a1) -; RV32IFD-NEXT: flt.d a3, fa5, fs0 -; RV32IFD-NEXT: beqz a3, .LBB17_4 +; RV32IFD-NEXT: flt.d a4, fa5, fs0 +; RV32IFD-NEXT: beqz a4, .LBB17_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a4, -1 +; RV32IFD-NEXT: addi a2, a3, -1 ; RV32IFD-NEXT: .LBB17_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a4, a1 -; RV32IFD-NEXT: and a1, a4, a2 -; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a3, a1 +; RV32IFD-NEXT: and a1, a3, a2 +; RV32IFD-NEXT: neg a2, a4 +; RV32IFD-NEXT: neg a4, s0 ; RV32IFD-NEXT: and a0, a4, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -1278,27 +1283,28 @@ define i64 @test_rint_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a4, 524288 +; RV32IFD-NEXT: lui a3, 524288 +; RV32IFD-NEXT: li a4, 1 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: beqz s0, .LBB21_2 +; RV32IFD-NEXT: bne s0, a4, .LBB21_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB21_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI21_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI21_1)(a1) -; RV32IFD-NEXT: flt.d a3, fa5, fs0 -; RV32IFD-NEXT: beqz a3, .LBB21_4 +; RV32IFD-NEXT: flt.d a4, fa5, fs0 +; RV32IFD-NEXT: beqz a4, .LBB21_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a4, -1 +; RV32IFD-NEXT: addi a2, a3, -1 ; RV32IFD-NEXT: .LBB21_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a4, a1 -; RV32IFD-NEXT: and a1, a4, a2 -; RV32IFD-NEXT: neg a2, a3 -; RV32IFD-NEXT: neg a3, s0 -; RV32IFD-NEXT: and a0, a3, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a3, a1 +; RV32IFD-NEXT: and a1, a3, a2 +; RV32IFD-NEXT: neg a2, a4 +; RV32IFD-NEXT: neg a4, s0 ; RV32IFD-NEXT: and a0, a4, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a3, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll index 7eabd3f5f227..653b64ec7304 100644 --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -275,24 +275,26 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg s1, a0 +; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: addi s1, a0, -1 +; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi -; RV32I-NEXT: and s1, s1, a0 -; RV32I-NEXT: lui a1, 325632 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: or a0, a0, s1 +; RV32I-NEXT: and a0, s2, a0 +; RV32I-NEXT: or a0, s1, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; @@ -616,36 +618,38 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fa0 +; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: call __fixsfdi +; RV32IF-NEXT: lui a2, %hi(.LCPI12_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a2) +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: feq.s a2, fs0, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 -; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB12_2 ; RV32IF-NEXT: # %bb.1: # %start -; RV32IF-NEXT: mv a2, a1 +; RV32IF-NEXT: mv a4, a1 ; RV32IF-NEXT: .LBB12_2: # %start -; RV32IF-NEXT: lui a1, %hi(.LCPI12_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a1) -; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: beqz a3, .LBB12_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: addi a2, a4, -1 +; RV32IF-NEXT: addi a4, a5, -1 ; RV32IF-NEXT: .LBB12_4: # %start -; RV32IF-NEXT: feq.s a1, fs0, fs0 -; RV32IF-NEXT: neg a4, a1 -; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a0, a4, a0 +; RV32IF-NEXT: and a1, a2, a4 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -863,23 +867,22 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fmv.s fs0, fa0 +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: lui a0, %hi(.LCPI14_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a0) +; RV32IF-NEXT: flt.s a0, fa5, fa0 +; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: fle.s a0, fa5, fa0 -; RV32IF-NEXT: neg s0, a0 +; RV32IF-NEXT: neg s1, a0 ; RV32IF-NEXT: call __fixunssfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI14_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2) -; RV32IF-NEXT: and a0, s0, a0 -; RV32IF-NEXT: flt.s a2, fa5, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a1, s0, a1 -; RV32IF-NEXT: or a1, a2, a1 +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: or a0, s0, a0 +; RV32IF-NEXT: and a1, s1, a1 +; RV32IF-NEXT: or a1, s0, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -898,19 +901,17 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: mv s0, a0 -; RV32IZFINX-NEXT: fle.s a0, zero, a0 -; RV32IZFINX-NEXT: neg s1, a0 -; RV32IZFINX-NEXT: mv a0, s0 +; RV32IZFINX-NEXT: lui a1, %hi(.LCPI14_0) +; RV32IZFINX-NEXT: lw a1, %lo(.LCPI14_0)(a1) +; RV32IZFINX-NEXT: flt.s a1, a1, a0 +; RV32IZFINX-NEXT: neg s0, a1 +; RV32IZFINX-NEXT: fle.s a1, zero, a0 +; RV32IZFINX-NEXT: neg s1, a1 ; RV32IZFINX-NEXT: call __fixunssfdi -; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0) -; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 -; RV32IZFINX-NEXT: flt.s a2, a2, s0 -; RV32IZFINX-NEXT: neg a2, a2 -; RV32IZFINX-NEXT: or a0, a2, a0 +; RV32IZFINX-NEXT: or a0, s0, a0 ; RV32IZFINX-NEXT: and a1, s1, a1 -; RV32IZFINX-NEXT: or a1, a2, a1 +; RV32IZFINX-NEXT: or a1, s0, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -928,36 +929,33 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; ; RV32I-LABEL: fcvt_lu_s_sat: ; RV32I: # %bb.0: # %start -; RV32I-NEXT: addi sp, sp, -32 -; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi sp, sp, -16 +; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 +; RV32I-NEXT: lui a1, 391168 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg s1, a0 +; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfdi -; RV32I-NEXT: mv s1, a1 -; RV32I-NEXT: and s3, s2, a0 -; RV32I-NEXT: lui a1, 391168 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg a1, a0 -; RV32I-NEXT: or a0, a1, s3 -; RV32I-NEXT: and a2, s2, s1 -; RV32I-NEXT: or a1, a1, a2 -; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 32 +; RV32I-NEXT: and a0, s2, a0 +; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: and a1, s2, a1 +; RV32I-NEXT: or a1, s1, a1 +; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fcvt_lu_s_sat: @@ -2091,24 +2089,26 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg s1, a0 +; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: addi s1, a0, -1 +; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi -; RV32I-NEXT: and s1, s1, a0 -; RV32I-NEXT: lui a1, 325632 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: mv a0, s0 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg a0, a0 -; RV32I-NEXT: or a0, a0, s1 +; RV32I-NEXT: and a0, s2, a0 +; RV32I-NEXT: or a0, s1, a0 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll index 5e99c7eb9056..4f747c278da0 100644 --- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll @@ -37,7 +37,8 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -52,32 +53,33 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi +; RV32IF-NEXT: lui a2, %hi(.LCPI1_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a2) +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: feq.s a2, fs0, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 -; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB1_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a2, a1 +; RV32IF-NEXT: mv a4, a1 ; RV32IF-NEXT: .LBB1_4: -; RV32IF-NEXT: lui a1, %hi(.LCPI1_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a1) -; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: beqz a3, .LBB1_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a2, a4, -1 +; RV32IF-NEXT: addi a4, a5, -1 ; RV32IF-NEXT: .LBB1_6: -; RV32IF-NEXT: feq.s a1, fs0, fs0 -; RV32IF-NEXT: neg a4, a1 -; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a0, a4, a0 +; RV32IF-NEXT: and a1, a2, a4 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -115,23 +117,23 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 -; RV32IZFINX-NEXT: neg a2, a4 +; RV32IZFINX-NEXT: flt.s a3, a2, s0 +; RV32IZFINX-NEXT: neg a2, a3 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a3, 524288 +; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB1_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a3, a1 +; RV32IZFINX-NEXT: mv a4, a1 ; RV32IZFINX-NEXT: .LBB1_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a4, .LBB1_6 +; RV32IZFINX-NEXT: beqz a3, .LBB1_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a3, a5, -1 +; RV32IZFINX-NEXT: addi a4, a5, -1 ; RV32IZFINX-NEXT: .LBB1_6: -; RV32IZFINX-NEXT: and a1, a2, a3 +; RV32IZFINX-NEXT: and a1, a2, a4 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -297,7 +299,8 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -312,32 +315,33 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi +; RV32IF-NEXT: lui a2, %hi(.LCPI5_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a2) +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: feq.s a2, fs0, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 -; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB5_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a2, a1 +; RV32IF-NEXT: mv a4, a1 ; RV32IF-NEXT: .LBB5_4: -; RV32IF-NEXT: lui a1, %hi(.LCPI5_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a1) -; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: beqz a3, .LBB5_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a2, a4, -1 +; RV32IF-NEXT: addi a4, a5, -1 ; RV32IF-NEXT: .LBB5_6: -; RV32IF-NEXT: feq.s a1, fs0, fs0 -; RV32IF-NEXT: neg a4, a1 -; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a0, a4, a0 +; RV32IF-NEXT: and a1, a2, a4 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -375,23 +379,23 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 -; RV32IZFINX-NEXT: neg a2, a4 +; RV32IZFINX-NEXT: flt.s a3, a2, s0 +; RV32IZFINX-NEXT: neg a2, a3 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a3, 524288 +; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB5_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a3, a1 +; RV32IZFINX-NEXT: mv a4, a1 ; RV32IZFINX-NEXT: .LBB5_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a4, .LBB5_6 +; RV32IZFINX-NEXT: beqz a3, .LBB5_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a3, a5, -1 +; RV32IZFINX-NEXT: addi a4, a5, -1 ; RV32IZFINX-NEXT: .LBB5_6: -; RV32IZFINX-NEXT: and a1, a2, a3 +; RV32IZFINX-NEXT: and a1, a2, a4 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -557,7 +561,8 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -572,32 +577,33 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi +; RV32IF-NEXT: lui a2, %hi(.LCPI9_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a2) +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: feq.s a2, fs0, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 -; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB9_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a2, a1 +; RV32IF-NEXT: mv a4, a1 ; RV32IF-NEXT: .LBB9_4: -; RV32IF-NEXT: lui a1, %hi(.LCPI9_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a1) -; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: beqz a3, .LBB9_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a2, a4, -1 +; RV32IF-NEXT: addi a4, a5, -1 ; RV32IF-NEXT: .LBB9_6: -; RV32IF-NEXT: feq.s a1, fs0, fs0 -; RV32IF-NEXT: neg a4, a1 -; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a0, a4, a0 +; RV32IF-NEXT: and a1, a2, a4 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -635,23 +641,23 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 -; RV32IZFINX-NEXT: neg a2, a4 +; RV32IZFINX-NEXT: flt.s a3, a2, s0 +; RV32IZFINX-NEXT: neg a2, a3 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a3, 524288 +; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB9_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a3, a1 +; RV32IZFINX-NEXT: mv a4, a1 ; RV32IZFINX-NEXT: .LBB9_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a4, .LBB9_6 +; RV32IZFINX-NEXT: beqz a3, .LBB9_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a3, a5, -1 +; RV32IZFINX-NEXT: addi a4, a5, -1 ; RV32IZFINX-NEXT: .LBB9_6: -; RV32IZFINX-NEXT: and a1, a2, a3 +; RV32IZFINX-NEXT: and a1, a2, a4 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -817,7 +823,8 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -832,32 +839,33 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi +; RV32IF-NEXT: lui a2, %hi(.LCPI13_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a2) +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: feq.s a2, fs0, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 -; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB13_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a2, a1 +; RV32IF-NEXT: mv a4, a1 ; RV32IF-NEXT: .LBB13_4: -; RV32IF-NEXT: lui a1, %hi(.LCPI13_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a1) -; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: beqz a3, .LBB13_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a2, a4, -1 +; RV32IF-NEXT: addi a4, a5, -1 ; RV32IF-NEXT: .LBB13_6: -; RV32IF-NEXT: feq.s a1, fs0, fs0 -; RV32IF-NEXT: neg a4, a1 -; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a0, a4, a0 +; RV32IF-NEXT: and a1, a2, a4 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -895,23 +903,23 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 -; RV32IZFINX-NEXT: neg a2, a4 +; RV32IZFINX-NEXT: flt.s a3, a2, s0 +; RV32IZFINX-NEXT: neg a2, a3 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a3, 524288 +; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB13_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a3, a1 +; RV32IZFINX-NEXT: mv a4, a1 ; RV32IZFINX-NEXT: .LBB13_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a4, .LBB13_6 +; RV32IZFINX-NEXT: beqz a3, .LBB13_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a3, a5, -1 +; RV32IZFINX-NEXT: addi a4, a5, -1 ; RV32IZFINX-NEXT: .LBB13_6: -; RV32IZFINX-NEXT: and a1, a2, a3 +; RV32IZFINX-NEXT: and a1, a2, a4 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1077,7 +1085,8 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -1092,32 +1101,33 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi +; RV32IF-NEXT: lui a2, %hi(.LCPI17_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a2) +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: feq.s a2, fs0, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 -; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB17_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a2, a1 +; RV32IF-NEXT: mv a4, a1 ; RV32IF-NEXT: .LBB17_4: -; RV32IF-NEXT: lui a1, %hi(.LCPI17_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a1) -; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: beqz a3, .LBB17_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a2, a4, -1 +; RV32IF-NEXT: addi a4, a5, -1 ; RV32IF-NEXT: .LBB17_6: -; RV32IF-NEXT: feq.s a1, fs0, fs0 -; RV32IF-NEXT: neg a4, a1 -; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a0, a4, a0 +; RV32IF-NEXT: and a1, a2, a4 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1155,23 +1165,23 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 -; RV32IZFINX-NEXT: neg a2, a4 +; RV32IZFINX-NEXT: flt.s a3, a2, s0 +; RV32IZFINX-NEXT: neg a2, a3 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a3, 524288 +; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB17_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a3, a1 +; RV32IZFINX-NEXT: mv a4, a1 ; RV32IZFINX-NEXT: .LBB17_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a4, .LBB17_6 +; RV32IZFINX-NEXT: beqz a3, .LBB17_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a3, a5, -1 +; RV32IZFINX-NEXT: addi a4, a5, -1 ; RV32IZFINX-NEXT: .LBB17_6: -; RV32IZFINX-NEXT: and a1, a2, a3 +; RV32IZFINX-NEXT: and a1, a2, a4 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1337,7 +1347,8 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -1352,32 +1363,33 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 +; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi +; RV32IF-NEXT: lui a2, %hi(.LCPI21_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI21_0)(a2) +; RV32IF-NEXT: and a0, s1, a0 +; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: feq.s a2, fs0, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 -; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB21_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a2, a1 +; RV32IF-NEXT: mv a4, a1 ; RV32IF-NEXT: .LBB21_4: -; RV32IF-NEXT: lui a1, %hi(.LCPI21_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI21_0)(a1) -; RV32IF-NEXT: flt.s a3, fa5, fs0 +; RV32IF-NEXT: and a0, a2, a0 ; RV32IF-NEXT: beqz a3, .LBB21_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a2, a4, -1 +; RV32IF-NEXT: addi a4, a5, -1 ; RV32IF-NEXT: .LBB21_6: -; RV32IF-NEXT: feq.s a1, fs0, fs0 -; RV32IF-NEXT: neg a4, a1 -; RV32IF-NEXT: and a1, a4, a2 -; RV32IF-NEXT: neg a2, s0 -; RV32IF-NEXT: and a0, a2, a0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: and a0, a4, a0 +; RV32IF-NEXT: and a1, a2, a4 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1415,23 +1427,23 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a4, a2, s0 -; RV32IZFINX-NEXT: neg a2, a4 +; RV32IZFINX-NEXT: flt.s a3, a2, s0 +; RV32IZFINX-NEXT: neg a2, a3 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a3, 524288 +; RV32IZFINX-NEXT: lui a4, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB21_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a3, a1 +; RV32IZFINX-NEXT: mv a4, a1 ; RV32IZFINX-NEXT: .LBB21_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a4, .LBB21_6 +; RV32IZFINX-NEXT: beqz a3, .LBB21_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a3, a5, -1 +; RV32IZFINX-NEXT: addi a4, a5, -1 ; RV32IZFINX-NEXT: .LBB21_6: -; RV32IZFINX-NEXT: and a1, a2, a3 +; RV32IZFINX-NEXT: and a1, a2, a4 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll index f6a53a9d76dd..c303690aadff 100644 --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -3567,8 +3567,8 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV32-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32-NEXT: neg a3, a0 ; RV32-NEXT: and a3, a3, a1 -; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a1, 4(sp) +; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: mv a1, sp ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 @@ -3659,8 +3659,8 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind { ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32-NEXT: neg a3, a0 ; RV32-NEXT: and a3, a3, a1 -; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: sw a1, 4(sp) +; RV32-NEXT: sw a4, 0(sp) ; RV32-NEXT: mv a1, sp ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll index deb5a6d4013d..06ab813faf02 100644 --- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll +++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll @@ -114,8 +114,8 @@ define i32 @utest_f64i32(double %x) { ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 ; RV32IF-NEXT: call __fixunsdfdi -; RV32IF-NEXT: sltiu a2, a0, -1 ; RV32IF-NEXT: seqz a1, a1 +; RV32IF-NEXT: sltiu a2, a0, -1 ; RV32IF-NEXT: and a1, a1, a2 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: or a0, a1, a0 @@ -429,8 +429,8 @@ define i32 @utesth_f16i32(half %x) { ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: call __fixunssfdi -; RV32-NEXT: sltiu a2, a0, -1 ; RV32-NEXT: seqz a1, a1 +; RV32-NEXT: sltiu a2, a0, -1 ; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: or a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index 31fb6e2ee9c8..277749c75bbb 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -2145,41 +2145,47 @@ define i64 @fcvt_l_h(half %a) nounwind { define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IZFH-LABEL: fcvt_l_h_sat: ; RV32IZFH: # %bb.0: # %start -; RV32IZFH-NEXT: addi sp, sp, -16 -; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: addi sp, sp, -32 +; RV32IZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_0) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 +; RV32IZFH-NEXT: flt.s s0, fa5, fs0 +; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: fle.s s2, fa5, fs0 +; RV32IZFH-NEXT: neg s3, s2 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi +; RV32IZFH-NEXT: and a0, s3, a0 +; RV32IZFH-NEXT: or a0, s1, a0 +; RV32IZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a2, 524288 -; RV32IZFH-NEXT: beqz s0, .LBB10_2 +; RV32IZFH-NEXT: lui a3, 524288 +; RV32IZFH-NEXT: beqz s2, .LBB10_2 ; RV32IZFH-NEXT: # %bb.1: # %start -; RV32IZFH-NEXT: mv a2, a1 +; RV32IZFH-NEXT: mv a3, a1 ; RV32IZFH-NEXT: .LBB10_2: # %start -; RV32IZFH-NEXT: lui a1, %hi(.LCPI10_0) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1) -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: beqz a3, .LBB10_4 +; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: beqz s0, .LBB10_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: addi a3, a4, -1 ; RV32IZFH-NEXT: .LBB10_4: # %start -; RV32IZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IZFH-NEXT: neg a4, a1 -; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: neg a3, s0 -; RV32IZFH-NEXT: and a0, a3, a0 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a0, a4, a0 -; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 16 +; RV32IZFH-NEXT: and a1, a2, a3 +; RV32IZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 32 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_l_h_sat: @@ -2193,41 +2199,47 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IDZFH-LABEL: fcvt_l_h_sat: ; RV32IDZFH: # %bb.0: # %start -; RV32IDZFH-NEXT: addi sp, sp, -16 -; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: addi sp, sp, -32 +; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill +; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_0) +; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 +; RV32IDZFH-NEXT: flt.s s0, fa5, fs0 +; RV32IDZFH-NEXT: neg s1, s0 ; RV32IDZFH-NEXT: lui a0, 913408 ; RV32IDZFH-NEXT: fmv.w.x fa5, a0 -; RV32IDZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IDZFH-NEXT: fle.s s2, fa5, fs0 +; RV32IDZFH-NEXT: neg s3, s2 ; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: call __fixsfdi +; RV32IDZFH-NEXT: and a0, s3, a0 +; RV32IDZFH-NEXT: or a0, s1, a0 +; RV32IDZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IDZFH-NEXT: neg a2, a2 ; RV32IDZFH-NEXT: lui a4, 524288 -; RV32IDZFH-NEXT: lui a2, 524288 -; RV32IDZFH-NEXT: beqz s0, .LBB10_2 +; RV32IDZFH-NEXT: lui a3, 524288 +; RV32IDZFH-NEXT: beqz s2, .LBB10_2 ; RV32IDZFH-NEXT: # %bb.1: # %start -; RV32IDZFH-NEXT: mv a2, a1 +; RV32IDZFH-NEXT: mv a3, a1 ; RV32IDZFH-NEXT: .LBB10_2: # %start -; RV32IDZFH-NEXT: lui a1, %hi(.LCPI10_0) -; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1) -; RV32IDZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IDZFH-NEXT: beqz a3, .LBB10_4 +; RV32IDZFH-NEXT: and a0, a2, a0 +; RV32IDZFH-NEXT: beqz s0, .LBB10_4 ; RV32IDZFH-NEXT: # %bb.3: -; RV32IDZFH-NEXT: addi a2, a4, -1 +; RV32IDZFH-NEXT: addi a3, a4, -1 ; RV32IDZFH-NEXT: .LBB10_4: # %start -; RV32IDZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IDZFH-NEXT: neg a4, a1 -; RV32IDZFH-NEXT: and a1, a4, a2 -; RV32IDZFH-NEXT: neg a2, a3 -; RV32IDZFH-NEXT: neg a3, s0 -; RV32IDZFH-NEXT: and a0, a3, a0 -; RV32IDZFH-NEXT: or a0, a2, a0 -; RV32IDZFH-NEXT: and a0, a4, a0 -; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: and a1, a2, a3 +; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 16 +; RV32IDZFH-NEXT: addi sp, sp, 32 ; RV32IDZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_l_h_sat: @@ -2503,41 +2515,47 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32ID-LABEL: fcvt_l_h_sat: ; RV32ID: # %bb.0: # %start -; RV32ID-NEXT: addi sp, sp, -16 -; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32ID-NEXT: addi sp, sp, -32 +; RV32ID-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32ID-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32ID-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32ID-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32ID-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32ID-NEXT: call __extendhfsf2 +; RV32ID-NEXT: lui a0, %hi(.LCPI10_0) +; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32ID-NEXT: fmv.s fs0, fa0 +; RV32ID-NEXT: flt.s s0, fa5, fa0 +; RV32ID-NEXT: neg s1, s0 ; RV32ID-NEXT: lui a0, 913408 ; RV32ID-NEXT: fmv.w.x fa5, a0 -; RV32ID-NEXT: fle.s s0, fa5, fa0 +; RV32ID-NEXT: fle.s s2, fa5, fa0 +; RV32ID-NEXT: neg s3, s2 ; RV32ID-NEXT: call __fixsfdi +; RV32ID-NEXT: and a0, s3, a0 +; RV32ID-NEXT: or a0, s1, a0 +; RV32ID-NEXT: feq.s a2, fs0, fs0 +; RV32ID-NEXT: neg a2, a2 ; RV32ID-NEXT: lui a4, 524288 -; RV32ID-NEXT: lui a2, 524288 -; RV32ID-NEXT: beqz s0, .LBB10_2 +; RV32ID-NEXT: lui a3, 524288 +; RV32ID-NEXT: beqz s2, .LBB10_2 ; RV32ID-NEXT: # %bb.1: # %start -; RV32ID-NEXT: mv a2, a1 +; RV32ID-NEXT: mv a3, a1 ; RV32ID-NEXT: .LBB10_2: # %start -; RV32ID-NEXT: lui a1, %hi(.LCPI10_0) -; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a1) -; RV32ID-NEXT: flt.s a3, fa5, fs0 -; RV32ID-NEXT: beqz a3, .LBB10_4 +; RV32ID-NEXT: and a0, a2, a0 +; RV32ID-NEXT: beqz s0, .LBB10_4 ; RV32ID-NEXT: # %bb.3: -; RV32ID-NEXT: addi a2, a4, -1 +; RV32ID-NEXT: addi a3, a4, -1 ; RV32ID-NEXT: .LBB10_4: # %start -; RV32ID-NEXT: feq.s a1, fs0, fs0 -; RV32ID-NEXT: neg a4, a1 -; RV32ID-NEXT: and a1, a4, a2 -; RV32ID-NEXT: neg a2, s0 -; RV32ID-NEXT: and a0, a2, a0 -; RV32ID-NEXT: neg a2, a3 -; RV32ID-NEXT: or a0, a2, a0 -; RV32ID-NEXT: and a0, a4, a0 -; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32ID-NEXT: and a1, a2, a3 +; RV32ID-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32ID-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32ID-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32ID-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32ID-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32ID-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32ID-NEXT: addi sp, sp, 16 +; RV32ID-NEXT: addi sp, sp, 32 ; RV32ID-NEXT: ret ; ; RV64ID-LABEL: fcvt_l_h_sat: @@ -2556,41 +2574,47 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IFZFHMIN-LABEL: fcvt_l_h_sat: ; RV32IFZFHMIN: # %bb.0: # %start -; RV32IFZFHMIN-NEXT: addi sp, sp, -16 -; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: addi sp, sp, -32 +; RV32IFZFHMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: lui a0, %hi(.LCPI10_0) +; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0 +; RV32IFZFHMIN-NEXT: flt.s s0, fa5, fs0 +; RV32IFZFHMIN-NEXT: neg s1, s0 ; RV32IFZFHMIN-NEXT: lui a0, 913408 ; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IFZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IFZFHMIN-NEXT: fle.s s2, fa5, fs0 +; RV32IFZFHMIN-NEXT: neg s3, s2 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IFZFHMIN-NEXT: call __fixsfdi +; RV32IFZFHMIN-NEXT: and a0, s3, a0 +; RV32IFZFHMIN-NEXT: or a0, s1, a0 +; RV32IFZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IFZFHMIN-NEXT: neg a2, a2 ; RV32IFZFHMIN-NEXT: lui a4, 524288 -; RV32IFZFHMIN-NEXT: lui a2, 524288 -; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_2 +; RV32IFZFHMIN-NEXT: lui a3, 524288 +; RV32IFZFHMIN-NEXT: beqz s2, .LBB10_2 ; RV32IFZFHMIN-NEXT: # %bb.1: # %start -; RV32IFZFHMIN-NEXT: mv a2, a1 +; RV32IFZFHMIN-NEXT: mv a3, a1 ; RV32IFZFHMIN-NEXT: .LBB10_2: # %start -; RV32IFZFHMIN-NEXT: lui a1, %hi(.LCPI10_0) -; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) -; RV32IFZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IFZFHMIN-NEXT: beqz a3, .LBB10_4 +; RV32IFZFHMIN-NEXT: and a0, a2, a0 +; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_4 ; RV32IFZFHMIN-NEXT: # %bb.3: -; RV32IFZFHMIN-NEXT: addi a2, a4, -1 +; RV32IFZFHMIN-NEXT: addi a3, a4, -1 ; RV32IFZFHMIN-NEXT: .LBB10_4: # %start -; RV32IFZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IFZFHMIN-NEXT: neg a4, a1 -; RV32IFZFHMIN-NEXT: and a1, a4, a2 -; RV32IFZFHMIN-NEXT: neg a2, a3 -; RV32IFZFHMIN-NEXT: neg a3, s0 -; RV32IFZFHMIN-NEXT: and a0, a3, a0 -; RV32IFZFHMIN-NEXT: or a0, a2, a0 -; RV32IFZFHMIN-NEXT: and a0, a4, a0 -; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: addi sp, sp, 16 +; RV32IFZFHMIN-NEXT: and a1, a2, a3 +; RV32IFZFHMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: addi sp, sp, 32 ; RV32IFZFHMIN-NEXT: ret ; ; CHECK64-IZFHMIN-LABEL: fcvt_l_h_sat: @@ -2605,41 +2629,47 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IDZFHMIN-LABEL: fcvt_l_h_sat: ; RV32IDZFHMIN: # %bb.0: # %start -; RV32IDZFHMIN-NEXT: addi sp, sp, -16 -; RV32IDZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: addi sp, sp, -32 +; RV32IDZFHMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32IDZFHMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill +; RV32IDZFHMIN-NEXT: lui a0, %hi(.LCPI10_0) +; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0 +; RV32IDZFHMIN-NEXT: flt.s s0, fa5, fs0 +; RV32IDZFHMIN-NEXT: neg s1, s0 ; RV32IDZFHMIN-NEXT: lui a0, 913408 ; RV32IDZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IDZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IDZFHMIN-NEXT: fle.s s2, fa5, fs0 +; RV32IDZFHMIN-NEXT: neg s3, s2 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IDZFHMIN-NEXT: call __fixsfdi +; RV32IDZFHMIN-NEXT: and a0, s3, a0 +; RV32IDZFHMIN-NEXT: or a0, s1, a0 +; RV32IDZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IDZFHMIN-NEXT: neg a2, a2 ; RV32IDZFHMIN-NEXT: lui a4, 524288 -; RV32IDZFHMIN-NEXT: lui a2, 524288 -; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_2 +; RV32IDZFHMIN-NEXT: lui a3, 524288 +; RV32IDZFHMIN-NEXT: beqz s2, .LBB10_2 ; RV32IDZFHMIN-NEXT: # %bb.1: # %start -; RV32IDZFHMIN-NEXT: mv a2, a1 +; RV32IDZFHMIN-NEXT: mv a3, a1 ; RV32IDZFHMIN-NEXT: .LBB10_2: # %start -; RV32IDZFHMIN-NEXT: lui a1, %hi(.LCPI10_0) -; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) -; RV32IDZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IDZFHMIN-NEXT: beqz a3, .LBB10_4 +; RV32IDZFHMIN-NEXT: and a0, a2, a0 +; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_4 ; RV32IDZFHMIN-NEXT: # %bb.3: -; RV32IDZFHMIN-NEXT: addi a2, a4, -1 +; RV32IDZFHMIN-NEXT: addi a3, a4, -1 ; RV32IDZFHMIN-NEXT: .LBB10_4: # %start -; RV32IDZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IDZFHMIN-NEXT: neg a4, a1 -; RV32IDZFHMIN-NEXT: and a1, a4, a2 -; RV32IDZFHMIN-NEXT: neg a2, a3 -; RV32IDZFHMIN-NEXT: neg a3, s0 -; RV32IDZFHMIN-NEXT: and a0, a3, a0 -; RV32IDZFHMIN-NEXT: or a0, a2, a0 -; RV32IDZFHMIN-NEXT: and a0, a4, a0 -; RV32IDZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: and a1, a2, a3 +; RV32IDZFHMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32IDZFHMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32IDZFHMIN-NEXT: addi sp, sp, 16 +; RV32IDZFHMIN-NEXT: addi sp, sp, 32 ; RV32IDZFHMIN-NEXT: ret ; ; CHECK32-IZHINXMIN-LABEL: fcvt_l_h_sat: diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll index 04a8a66f4459..9c95210bfa7c 100644 --- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll @@ -108,38 +108,40 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi +; RV32IZFH-NEXT: lui a2, %hi(.LCPI1_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a2) +; RV32IZFH-NEXT: and a0, s1, a0 +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IZFH-NEXT: neg a2, a2 +; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB1_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a2, a1 +; RV32IZFH-NEXT: mv a4, a1 ; RV32IZFH-NEXT: .LBB1_4: -; RV32IZFH-NEXT: lui a1, %hi(.LCPI1_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a1) -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: beqz a3, .LBB1_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a2, a4, -1 -; RV32IZFH-NEXT: .LBB1_6: -; RV32IZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IZFH-NEXT: neg a4, a1 -; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 +; RV32IZFH-NEXT: beqz a3, .LBB1_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a4, a5, -1 +; RV32IZFH-NEXT: .LBB1_6: +; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_floor_si64: @@ -177,16 +179,16 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 -; RV32IZHINX-NEXT: neg a2, a4 +; RV32IZHINX-NEXT: flt.s a3, a2, s0 +; RV32IZHINX-NEXT: neg a2, a3 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a3, 524288 +; RV32IZHINX-NEXT: lui a4, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB1_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a3, a1 +; RV32IZHINX-NEXT: mv a4, a1 ; RV32IZHINX-NEXT: .LBB1_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -194,11 +196,11 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a4, .LBB1_6 +; RV32IZHINX-NEXT: beqz a3, .LBB1_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a3, a5, -1 +; RV32IZHINX-NEXT: addi a4, a5, -1 ; RV32IZHINX-NEXT: .LBB1_6: -; RV32IZHINX-NEXT: and a1, a2, a3 +; RV32IZHINX-NEXT: and a1, a2, a4 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_floor_si64: @@ -236,39 +238,41 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi +; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI1_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a2) +; RV32IZFHMIN-NEXT: and a0, s1, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a2, a2 +; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 -; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a2, a1 +; RV32IZFHMIN-NEXT: mv a4, a1 ; RV32IZFHMIN-NEXT: .LBB1_4: -; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI1_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a1) -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a2, a4, -1 -; RV32IZFHMIN-NEXT: .LBB1_6: -; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a4, a1 -; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 +; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a4, a5, -1 +; RV32IZFHMIN-NEXT: .LBB1_6: +; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_floor_si64: @@ -320,16 +324,16 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a4 +; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a3 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a3, 524288 +; RV32IZHINXMIN-NEXT: lui a4, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB1_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: mv a4, a1 ; RV32IZHINXMIN-NEXT: .LBB1_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -337,11 +341,11 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB1_6 +; RV32IZHINXMIN-NEXT: beqz a3, .LBB1_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: addi a4, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB1_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: and a1, a2, a4 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_floor_si64: @@ -820,38 +824,40 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi +; RV32IZFH-NEXT: lui a2, %hi(.LCPI5_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a2) +; RV32IZFH-NEXT: and a0, s1, a0 +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IZFH-NEXT: neg a2, a2 +; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB5_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a2, a1 +; RV32IZFH-NEXT: mv a4, a1 ; RV32IZFH-NEXT: .LBB5_4: -; RV32IZFH-NEXT: lui a1, %hi(.LCPI5_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a1) -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: beqz a3, .LBB5_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a2, a4, -1 -; RV32IZFH-NEXT: .LBB5_6: -; RV32IZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IZFH-NEXT: neg a4, a1 -; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 +; RV32IZFH-NEXT: beqz a3, .LBB5_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a4, a5, -1 +; RV32IZFH-NEXT: .LBB5_6: +; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_ceil_si64: @@ -889,16 +895,16 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI5_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI5_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 -; RV32IZHINX-NEXT: neg a2, a4 +; RV32IZHINX-NEXT: flt.s a3, a2, s0 +; RV32IZHINX-NEXT: neg a2, a3 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a3, 524288 +; RV32IZHINX-NEXT: lui a4, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB5_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a3, a1 +; RV32IZHINX-NEXT: mv a4, a1 ; RV32IZHINX-NEXT: .LBB5_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -906,11 +912,11 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a4, .LBB5_6 +; RV32IZHINX-NEXT: beqz a3, .LBB5_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a3, a5, -1 +; RV32IZHINX-NEXT: addi a4, a5, -1 ; RV32IZHINX-NEXT: .LBB5_6: -; RV32IZHINX-NEXT: and a1, a2, a3 +; RV32IZHINX-NEXT: and a1, a2, a4 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_ceil_si64: @@ -948,39 +954,41 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi +; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI5_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a2) +; RV32IZFHMIN-NEXT: and a0, s1, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a2, a2 +; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 -; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a2, a1 +; RV32IZFHMIN-NEXT: mv a4, a1 ; RV32IZFHMIN-NEXT: .LBB5_4: -; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI5_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a1) -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a2, a4, -1 -; RV32IZFHMIN-NEXT: .LBB5_6: -; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a4, a1 -; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 +; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a4, a5, -1 +; RV32IZFHMIN-NEXT: .LBB5_6: +; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_ceil_si64: @@ -1032,16 +1040,16 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a4 +; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a3 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a3, 524288 +; RV32IZHINXMIN-NEXT: lui a4, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB5_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: mv a4, a1 ; RV32IZHINXMIN-NEXT: .LBB5_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1049,11 +1057,11 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB5_6 +; RV32IZHINXMIN-NEXT: beqz a3, .LBB5_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: addi a4, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB5_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: and a1, a2, a4 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_ceil_si64: @@ -1532,38 +1540,40 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi +; RV32IZFH-NEXT: lui a2, %hi(.LCPI9_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a2) +; RV32IZFH-NEXT: and a0, s1, a0 +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IZFH-NEXT: neg a2, a2 +; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB9_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a2, a1 +; RV32IZFH-NEXT: mv a4, a1 ; RV32IZFH-NEXT: .LBB9_4: -; RV32IZFH-NEXT: lui a1, %hi(.LCPI9_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a1) -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: beqz a3, .LBB9_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a2, a4, -1 -; RV32IZFH-NEXT: .LBB9_6: -; RV32IZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IZFH-NEXT: neg a4, a1 -; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 +; RV32IZFH-NEXT: beqz a3, .LBB9_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a4, a5, -1 +; RV32IZFH-NEXT: .LBB9_6: +; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_trunc_si64: @@ -1601,16 +1611,16 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI9_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI9_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 -; RV32IZHINX-NEXT: neg a2, a4 +; RV32IZHINX-NEXT: flt.s a3, a2, s0 +; RV32IZHINX-NEXT: neg a2, a3 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a3, 524288 +; RV32IZHINX-NEXT: lui a4, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB9_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a3, a1 +; RV32IZHINX-NEXT: mv a4, a1 ; RV32IZHINX-NEXT: .LBB9_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1618,11 +1628,11 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a4, .LBB9_6 +; RV32IZHINX-NEXT: beqz a3, .LBB9_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a3, a5, -1 +; RV32IZHINX-NEXT: addi a4, a5, -1 ; RV32IZHINX-NEXT: .LBB9_6: -; RV32IZHINX-NEXT: and a1, a2, a3 +; RV32IZHINX-NEXT: and a1, a2, a4 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_trunc_si64: @@ -1660,39 +1670,41 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi +; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI9_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a2) +; RV32IZFHMIN-NEXT: and a0, s1, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a2, a2 +; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 -; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a2, a1 +; RV32IZFHMIN-NEXT: mv a4, a1 ; RV32IZFHMIN-NEXT: .LBB9_4: -; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI9_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a1) -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a2, a4, -1 -; RV32IZFHMIN-NEXT: .LBB9_6: -; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a4, a1 -; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 +; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a4, a5, -1 +; RV32IZFHMIN-NEXT: .LBB9_6: +; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_trunc_si64: @@ -1744,16 +1756,16 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a4 +; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a3 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a3, 524288 +; RV32IZHINXMIN-NEXT: lui a4, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB9_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: mv a4, a1 ; RV32IZHINXMIN-NEXT: .LBB9_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1761,11 +1773,11 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB9_6 +; RV32IZHINXMIN-NEXT: beqz a3, .LBB9_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: addi a4, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB9_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: and a1, a2, a4 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_trunc_si64: @@ -2244,38 +2256,40 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi +; RV32IZFH-NEXT: lui a2, %hi(.LCPI13_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a2) +; RV32IZFH-NEXT: and a0, s1, a0 +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IZFH-NEXT: neg a2, a2 +; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB13_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a2, a1 +; RV32IZFH-NEXT: mv a4, a1 ; RV32IZFH-NEXT: .LBB13_4: -; RV32IZFH-NEXT: lui a1, %hi(.LCPI13_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a1) -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: beqz a3, .LBB13_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a2, a4, -1 -; RV32IZFH-NEXT: .LBB13_6: -; RV32IZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IZFH-NEXT: neg a4, a1 -; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 +; RV32IZFH-NEXT: beqz a3, .LBB13_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a4, a5, -1 +; RV32IZFH-NEXT: .LBB13_6: +; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_round_si64: @@ -2313,16 +2327,16 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI13_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI13_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 -; RV32IZHINX-NEXT: neg a2, a4 +; RV32IZHINX-NEXT: flt.s a3, a2, s0 +; RV32IZHINX-NEXT: neg a2, a3 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a3, 524288 +; RV32IZHINX-NEXT: lui a4, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB13_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a3, a1 +; RV32IZHINX-NEXT: mv a4, a1 ; RV32IZHINX-NEXT: .LBB13_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2330,11 +2344,11 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a4, .LBB13_6 +; RV32IZHINX-NEXT: beqz a3, .LBB13_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a3, a5, -1 +; RV32IZHINX-NEXT: addi a4, a5, -1 ; RV32IZHINX-NEXT: .LBB13_6: -; RV32IZHINX-NEXT: and a1, a2, a3 +; RV32IZHINX-NEXT: and a1, a2, a4 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_round_si64: @@ -2372,39 +2386,41 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi +; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI13_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a2) +; RV32IZFHMIN-NEXT: and a0, s1, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a2, a2 +; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 -; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a2, a1 +; RV32IZFHMIN-NEXT: mv a4, a1 ; RV32IZFHMIN-NEXT: .LBB13_4: -; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI13_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a1) -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a2, a4, -1 -; RV32IZFHMIN-NEXT: .LBB13_6: -; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a4, a1 -; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 +; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a4, a5, -1 +; RV32IZFHMIN-NEXT: .LBB13_6: +; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_round_si64: @@ -2456,16 +2472,16 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a4 +; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a3 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a3, 524288 +; RV32IZHINXMIN-NEXT: lui a4, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB13_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: mv a4, a1 ; RV32IZHINXMIN-NEXT: .LBB13_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2473,11 +2489,11 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB13_6 +; RV32IZHINXMIN-NEXT: beqz a3, .LBB13_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: addi a4, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB13_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: and a1, a2, a4 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_round_si64: @@ -2956,38 +2972,40 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi +; RV32IZFH-NEXT: lui a2, %hi(.LCPI17_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a2) +; RV32IZFH-NEXT: and a0, s1, a0 +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IZFH-NEXT: neg a2, a2 +; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB17_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a2, a1 +; RV32IZFH-NEXT: mv a4, a1 ; RV32IZFH-NEXT: .LBB17_4: -; RV32IZFH-NEXT: lui a1, %hi(.LCPI17_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a1) -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: beqz a3, .LBB17_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a2, a4, -1 -; RV32IZFH-NEXT: .LBB17_6: -; RV32IZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IZFH-NEXT: neg a4, a1 -; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 +; RV32IZFH-NEXT: beqz a3, .LBB17_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a4, a5, -1 +; RV32IZFH-NEXT: .LBB17_6: +; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_roundeven_si64: @@ -3025,16 +3043,16 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI17_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI17_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 -; RV32IZHINX-NEXT: neg a2, a4 +; RV32IZHINX-NEXT: flt.s a3, a2, s0 +; RV32IZHINX-NEXT: neg a2, a3 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a3, 524288 +; RV32IZHINX-NEXT: lui a4, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB17_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a3, a1 +; RV32IZHINX-NEXT: mv a4, a1 ; RV32IZHINX-NEXT: .LBB17_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3042,11 +3060,11 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a4, .LBB17_6 +; RV32IZHINX-NEXT: beqz a3, .LBB17_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a3, a5, -1 +; RV32IZHINX-NEXT: addi a4, a5, -1 ; RV32IZHINX-NEXT: .LBB17_6: -; RV32IZHINX-NEXT: and a1, a2, a3 +; RV32IZHINX-NEXT: and a1, a2, a4 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_roundeven_si64: @@ -3084,39 +3102,41 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi +; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI17_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a2) +; RV32IZFHMIN-NEXT: and a0, s1, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a2, a2 +; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 -; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a2, a1 +; RV32IZFHMIN-NEXT: mv a4, a1 ; RV32IZFHMIN-NEXT: .LBB17_4: -; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI17_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a1) -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a2, a4, -1 -; RV32IZFHMIN-NEXT: .LBB17_6: -; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a4, a1 -; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 +; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a4, a5, -1 +; RV32IZFHMIN-NEXT: .LBB17_6: +; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_roundeven_si64: @@ -3168,16 +3188,16 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a4 +; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a3 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a3, 524288 +; RV32IZHINXMIN-NEXT: lui a4, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB17_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: mv a4, a1 ; RV32IZHINXMIN-NEXT: .LBB17_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3185,11 +3205,11 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB17_6 +; RV32IZHINXMIN-NEXT: beqz a3, .LBB17_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: addi a4, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB17_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: and a1, a2, a4 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_roundeven_si64: @@ -3668,38 +3688,40 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 +; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi +; RV32IZFH-NEXT: lui a2, %hi(.LCPI21_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a2) +; RV32IZFH-NEXT: and a0, s1, a0 +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: feq.s a2, fs0, fs0 +; RV32IZFH-NEXT: neg a2, a2 +; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB21_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a2, a1 +; RV32IZFH-NEXT: mv a4, a1 ; RV32IZFH-NEXT: .LBB21_4: -; RV32IZFH-NEXT: lui a1, %hi(.LCPI21_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a1) -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: beqz a3, .LBB21_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a2, a4, -1 -; RV32IZFH-NEXT: .LBB21_6: -; RV32IZFH-NEXT: feq.s a1, fs0, fs0 -; RV32IZFH-NEXT: neg a4, a1 -; RV32IZFH-NEXT: and a1, a4, a2 -; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 +; RV32IZFH-NEXT: beqz a3, .LBB21_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a4, a5, -1 +; RV32IZFH-NEXT: .LBB21_6: +; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_rint_si64: @@ -3737,16 +3759,16 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI21_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI21_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a4, a2, s0 -; RV32IZHINX-NEXT: neg a2, a4 +; RV32IZHINX-NEXT: flt.s a3, a2, s0 +; RV32IZHINX-NEXT: neg a2, a3 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a3, 524288 +; RV32IZHINX-NEXT: lui a4, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB21_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a3, a1 +; RV32IZHINX-NEXT: mv a4, a1 ; RV32IZHINX-NEXT: .LBB21_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3754,11 +3776,11 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a4, .LBB21_6 +; RV32IZHINX-NEXT: beqz a3, .LBB21_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a3, a5, -1 +; RV32IZHINX-NEXT: addi a4, a5, -1 ; RV32IZHINX-NEXT: .LBB21_6: -; RV32IZHINX-NEXT: and a1, a2, a3 +; RV32IZHINX-NEXT: and a1, a2, a4 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_rint_si64: @@ -3796,39 +3818,41 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 +; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi +; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI21_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a2) +; RV32IZFHMIN-NEXT: and a0, s1, a0 +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a2, a2 +; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 -; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB21_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a2, a1 +; RV32IZFHMIN-NEXT: mv a4, a1 ; RV32IZFHMIN-NEXT: .LBB21_4: -; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI21_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a1) -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: beqz a3, .LBB21_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a2, a4, -1 -; RV32IZFHMIN-NEXT: .LBB21_6: -; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a4, a1 -; RV32IZFHMIN-NEXT: and a1, a4, a2 -; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 +; RV32IZFHMIN-NEXT: beqz a3, .LBB21_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a4, a5, -1 +; RV32IZFHMIN-NEXT: .LBB21_6: +; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_rint_si64: @@ -3880,16 +3904,16 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a4 +; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a3 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a3, 524288 +; RV32IZHINXMIN-NEXT: lui a4, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB21_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a3, a1 +; RV32IZHINXMIN-NEXT: mv a4, a1 ; RV32IZHINXMIN-NEXT: .LBB21_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3897,11 +3921,11 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a4, .LBB21_6 +; RV32IZHINXMIN-NEXT: beqz a3, .LBB21_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a3, a5, -1 +; RV32IZHINXMIN-NEXT: addi a4, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB21_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a3 +; RV32IZHINXMIN-NEXT: and a1, a2, a4 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_rint_si64: diff --git a/llvm/test/CodeGen/RISCV/iabs.ll b/llvm/test/CodeGen/RISCV/iabs.ll index a0c85ab4dca7..98c886333d69 100644 --- a/llvm/test/CodeGen/RISCV/iabs.ll +++ b/llvm/test/CodeGen/RISCV/iabs.ll @@ -630,8 +630,8 @@ define void @zext16_abs8(i8 %x, ptr %p) { ; RV32I-LABEL: zext16_abs8: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: srai a2, a0, 31 ; RV32I-NEXT: srai a0, a0, 24 +; RV32I-NEXT: srai a2, a0, 31 ; RV32I-NEXT: xor a0, a0, a2 ; RV32I-NEXT: sub a0, a0, a2 ; RV32I-NEXT: sh a0, 0(a1) @@ -648,8 +648,8 @@ define void @zext16_abs8(i8 %x, ptr %p) { ; RV64I-LABEL: zext16_abs8: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 56 -; RV64I-NEXT: srai a2, a0, 63 ; RV64I-NEXT: srai a0, a0, 56 +; RV64I-NEXT: srai a2, a0, 63 ; RV64I-NEXT: xor a0, a0, a2 ; RV64I-NEXT: subw a0, a0, a2 ; RV64I-NEXT: sh a0, 0(a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll index a6b2d3141f22..b3bda5973eb8 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll @@ -2190,66 +2190,65 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.d fs0, fa1 +; CHECK-NOV-NEXT: fmv.d fs0, fa0 +; CHECK-NOV-NEXT: fmv.d fa0, fa1 ; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixdfti -; CHECK-NOV-NEXT: mv a2, a0 -; CHECK-NOV-NEXT: li a0, -1 -; CHECK-NOV-NEXT: srli a3, a0, 1 -; CHECK-NOV-NEXT: beqz a1, .LBB18_3 +; CHECK-NOV-NEXT: li a2, -1 +; CHECK-NOV-NEXT: srli a3, a2, 1 +; CHECK-NOV-NEXT: beqz s1, .LBB18_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 -; CHECK-NOV-NEXT: bnez s1, .LBB18_4 +; CHECK-NOV-NEXT: slti a4, s1, 0 +; CHECK-NOV-NEXT: bnez a1, .LBB18_4 ; CHECK-NOV-NEXT: .LBB18_2: -; CHECK-NOV-NEXT: sltu a5, s0, a3 +; CHECK-NOV-NEXT: sltu a5, a0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB18_5 ; CHECK-NOV-NEXT: j .LBB18_6 ; CHECK-NOV-NEXT: .LBB18_3: -; CHECK-NOV-NEXT: sltu a4, a2, a3 -; CHECK-NOV-NEXT: beqz s1, .LBB18_2 +; CHECK-NOV-NEXT: sltu a4, s0, a3 +; CHECK-NOV-NEXT: beqz a1, .LBB18_2 ; CHECK-NOV-NEXT: .LBB18_4: # %entry -; CHECK-NOV-NEXT: slti a5, s1, 0 +; CHECK-NOV-NEXT: slti a5, a1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB18_6 ; CHECK-NOV-NEXT: .LBB18_5: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a0, a3 ; CHECK-NOV-NEXT: .LBB18_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, a1 +; CHECK-NOV-NEXT: and a5, a5, s1 ; CHECK-NOV-NEXT: bnez a4, .LBB18_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv a2, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB18_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, s1 -; CHECK-NOV-NEXT: slli a1, a0, 63 -; CHECK-NOV-NEXT: beq a5, a0, .LBB18_11 +; CHECK-NOV-NEXT: and a4, a6, a1 +; CHECK-NOV-NEXT: slli a1, a2, 63 +; CHECK-NOV-NEXT: beq a5, a2, .LBB18_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a0, .LBB18_12 +; CHECK-NOV-NEXT: bne a4, a2, .LBB18_12 ; CHECK-NOV-NEXT: .LBB18_10: -; CHECK-NOV-NEXT: sltu a0, a1, s0 -; CHECK-NOV-NEXT: beqz a0, .LBB18_13 +; CHECK-NOV-NEXT: sltu a2, a1, a0 +; CHECK-NOV-NEXT: beqz a2, .LBB18_13 ; CHECK-NOV-NEXT: j .LBB18_14 ; CHECK-NOV-NEXT: .LBB18_11: -; CHECK-NOV-NEXT: sltu a3, a1, a2 -; CHECK-NOV-NEXT: beq a4, a0, .LBB18_10 +; CHECK-NOV-NEXT: sltu a3, a1, s0 +; CHECK-NOV-NEXT: beq a4, a2, .LBB18_10 ; CHECK-NOV-NEXT: .LBB18_12: # %entry -; CHECK-NOV-NEXT: slti a0, a4, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 -; CHECK-NOV-NEXT: bnez a0, .LBB18_14 +; CHECK-NOV-NEXT: slti a2, a4, 0 +; CHECK-NOV-NEXT: xori a2, a2, 1 +; CHECK-NOV-NEXT: bnez a2, .LBB18_14 ; CHECK-NOV-NEXT: .LBB18_13: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a0, a1 ; CHECK-NOV-NEXT: .LBB18_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB18_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv a2, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB18_16: # %entry -; CHECK-NOV-NEXT: mv a0, s0 -; CHECK-NOV-NEXT: mv a1, a2 +; CHECK-NOV-NEXT: mv a1, s0 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2274,43 +2273,43 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 -; CHECK-V-NEXT: vfmv.f.s fa0, v9 +; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz a1, .LBB18_3 +; CHECK-V-NEXT: beqz s1, .LBB18_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 -; CHECK-V-NEXT: bnez s1, .LBB18_4 +; CHECK-V-NEXT: slti a4, s1, 0 +; CHECK-V-NEXT: bnez a1, .LBB18_4 ; CHECK-V-NEXT: .LBB18_2: -; CHECK-V-NEXT: sltu a5, s0, a3 +; CHECK-V-NEXT: sltu a5, a0, a3 ; CHECK-V-NEXT: beqz a5, .LBB18_5 ; CHECK-V-NEXT: j .LBB18_6 ; CHECK-V-NEXT: .LBB18_3: -; CHECK-V-NEXT: sltu a4, a0, a3 -; CHECK-V-NEXT: beqz s1, .LBB18_2 +; CHECK-V-NEXT: sltu a4, s0, a3 +; CHECK-V-NEXT: beqz a1, .LBB18_2 ; CHECK-V-NEXT: .LBB18_4: # %entry -; CHECK-V-NEXT: slti a5, s1, 0 +; CHECK-V-NEXT: slti a5, a1, 0 ; CHECK-V-NEXT: bnez a5, .LBB18_6 ; CHECK-V-NEXT: .LBB18_5: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB18_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, a1 +; CHECK-V-NEXT: and a5, a5, s1 ; CHECK-V-NEXT: bnez a4, .LBB18_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB18_8: # %entry -; CHECK-V-NEXT: and a4, a6, s1 +; CHECK-V-NEXT: and a4, a6, a1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB18_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -2318,26 +2317,26 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB18_12 ; CHECK-V-NEXT: .LBB18_10: -; CHECK-V-NEXT: sltu a2, a1, s0 +; CHECK-V-NEXT: sltu a2, a1, a0 ; CHECK-V-NEXT: beqz a2, .LBB18_13 ; CHECK-V-NEXT: j .LBB18_14 ; CHECK-V-NEXT: .LBB18_11: -; CHECK-V-NEXT: sltu a3, a1, a0 +; CHECK-V-NEXT: sltu a3, a1, s0 ; CHECK-V-NEXT: beq a4, a2, .LBB18_10 ; CHECK-V-NEXT: .LBB18_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB18_14 ; CHECK-V-NEXT: .LBB18_13: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB18_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB18_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB18_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a0 -; CHECK-V-NEXT: vmv.s.x v9, s0 +; CHECK-V-NEXT: vmv.s.x v8, s0 +; CHECK-V-NEXT: vmv.s.x v9, a0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2370,19 +2369,19 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.d fs0, fa1 +; CHECK-NOV-NEXT: fmv.d fs0, fa0 +; CHECK-NOV-NEXT: fmv.d fa0, fa1 ; CHECK-NOV-NEXT: call __fixunsdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixunsdfti -; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: snez a2, s1 -; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a2, a2, s0 +; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a1, a1, a0 -; CHECK-NOV-NEXT: mv a0, a2 +; CHECK-NOV-NEXT: and a0, a1, a0 +; CHECK-NOV-NEXT: addi a1, a2, -1 +; CHECK-NOV-NEXT: and a1, a1, s0 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2407,25 +2406,25 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 -; CHECK-V-NEXT: vfmv.f.s fa0, v9 +; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunsdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunsdfti -; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a2, s1 -; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a2, a2, s0 +; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: addi a2, a2, -1 +; CHECK-V-NEXT: and a2, a2, s0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a0 -; CHECK-V-NEXT: vmv.s.x v9, a2 +; CHECK-V-NEXT: vmv.s.x v8, a2 +; CHECK-V-NEXT: vmv.s.x v9, a0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2467,32 +2466,32 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB20_2: # %entry -; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: slti a4, s1, 1 +; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB20_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB20_4: # %entry -; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 +; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB20_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a4, a4, s0 +; CHECK-NOV-NEXT: and a0, a0, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB20_8 ; CHECK-NOV-NEXT: .LBB20_6: -; CHECK-NOV-NEXT: snez a0, a4 +; CHECK-NOV-NEXT: snez a2, a0 ; CHECK-NOV-NEXT: j .LBB20_9 ; CHECK-NOV-NEXT: .LBB20_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a4, a4, s0 +; CHECK-NOV-NEXT: and a0, a0, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB20_6 ; CHECK-NOV-NEXT: .LBB20_8: # %entry -; CHECK-NOV-NEXT: sgtz a0, a2 +; CHECK-NOV-NEXT: sgtz a2, a2 ; CHECK-NOV-NEXT: .LBB20_9: # %entry -; CHECK-NOV-NEXT: neg a0, a0 -; CHECK-NOV-NEXT: and a0, a0, a4 +; CHECK-NOV-NEXT: neg a2, a2 +; CHECK-NOV-NEXT: and a0, a2, a0 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -2534,15 +2533,15 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB20_2: # %entry -; CHECK-V-NEXT: slti a4, a1, 1 ; CHECK-V-NEXT: slti a3, s1, 1 +; CHECK-V-NEXT: slti a4, a1, 1 ; CHECK-V-NEXT: blez a1, .LBB20_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB20_4: # %entry -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB20_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -2597,66 +2596,65 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.s fs0, fa1 +; CHECK-NOV-NEXT: fmv.s fs0, fa0 +; CHECK-NOV-NEXT: fmv.s fa0, fa1 ; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, a0 -; CHECK-NOV-NEXT: li a0, -1 -; CHECK-NOV-NEXT: srli a3, a0, 1 -; CHECK-NOV-NEXT: beqz a1, .LBB21_3 +; CHECK-NOV-NEXT: li a2, -1 +; CHECK-NOV-NEXT: srli a3, a2, 1 +; CHECK-NOV-NEXT: beqz s1, .LBB21_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 -; CHECK-NOV-NEXT: bnez s1, .LBB21_4 +; CHECK-NOV-NEXT: slti a4, s1, 0 +; CHECK-NOV-NEXT: bnez a1, .LBB21_4 ; CHECK-NOV-NEXT: .LBB21_2: -; CHECK-NOV-NEXT: sltu a5, s0, a3 +; CHECK-NOV-NEXT: sltu a5, a0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB21_5 ; CHECK-NOV-NEXT: j .LBB21_6 ; CHECK-NOV-NEXT: .LBB21_3: -; CHECK-NOV-NEXT: sltu a4, a2, a3 -; CHECK-NOV-NEXT: beqz s1, .LBB21_2 +; CHECK-NOV-NEXT: sltu a4, s0, a3 +; CHECK-NOV-NEXT: beqz a1, .LBB21_2 ; CHECK-NOV-NEXT: .LBB21_4: # %entry -; CHECK-NOV-NEXT: slti a5, s1, 0 +; CHECK-NOV-NEXT: slti a5, a1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB21_6 ; CHECK-NOV-NEXT: .LBB21_5: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a0, a3 ; CHECK-NOV-NEXT: .LBB21_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, a1 +; CHECK-NOV-NEXT: and a5, a5, s1 ; CHECK-NOV-NEXT: bnez a4, .LBB21_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv a2, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB21_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, s1 -; CHECK-NOV-NEXT: slli a1, a0, 63 -; CHECK-NOV-NEXT: beq a5, a0, .LBB21_11 +; CHECK-NOV-NEXT: and a4, a6, a1 +; CHECK-NOV-NEXT: slli a1, a2, 63 +; CHECK-NOV-NEXT: beq a5, a2, .LBB21_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a0, .LBB21_12 +; CHECK-NOV-NEXT: bne a4, a2, .LBB21_12 ; CHECK-NOV-NEXT: .LBB21_10: -; CHECK-NOV-NEXT: sltu a0, a1, s0 -; CHECK-NOV-NEXT: beqz a0, .LBB21_13 +; CHECK-NOV-NEXT: sltu a2, a1, a0 +; CHECK-NOV-NEXT: beqz a2, .LBB21_13 ; CHECK-NOV-NEXT: j .LBB21_14 ; CHECK-NOV-NEXT: .LBB21_11: -; CHECK-NOV-NEXT: sltu a3, a1, a2 -; CHECK-NOV-NEXT: beq a4, a0, .LBB21_10 +; CHECK-NOV-NEXT: sltu a3, a1, s0 +; CHECK-NOV-NEXT: beq a4, a2, .LBB21_10 ; CHECK-NOV-NEXT: .LBB21_12: # %entry -; CHECK-NOV-NEXT: slti a0, a4, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 -; CHECK-NOV-NEXT: bnez a0, .LBB21_14 +; CHECK-NOV-NEXT: slti a2, a4, 0 +; CHECK-NOV-NEXT: xori a2, a2, 1 +; CHECK-NOV-NEXT: bnez a2, .LBB21_14 ; CHECK-NOV-NEXT: .LBB21_13: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a0, a1 ; CHECK-NOV-NEXT: .LBB21_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB21_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv a2, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB21_16: # %entry -; CHECK-NOV-NEXT: mv a0, s0 -; CHECK-NOV-NEXT: mv a1, a2 +; CHECK-NOV-NEXT: mv a1, s0 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2681,43 +2679,43 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 -; CHECK-V-NEXT: vfmv.f.s fa0, v9 +; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz a1, .LBB21_3 +; CHECK-V-NEXT: beqz s1, .LBB21_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 -; CHECK-V-NEXT: bnez s1, .LBB21_4 +; CHECK-V-NEXT: slti a4, s1, 0 +; CHECK-V-NEXT: bnez a1, .LBB21_4 ; CHECK-V-NEXT: .LBB21_2: -; CHECK-V-NEXT: sltu a5, s0, a3 +; CHECK-V-NEXT: sltu a5, a0, a3 ; CHECK-V-NEXT: beqz a5, .LBB21_5 ; CHECK-V-NEXT: j .LBB21_6 ; CHECK-V-NEXT: .LBB21_3: -; CHECK-V-NEXT: sltu a4, a0, a3 -; CHECK-V-NEXT: beqz s1, .LBB21_2 +; CHECK-V-NEXT: sltu a4, s0, a3 +; CHECK-V-NEXT: beqz a1, .LBB21_2 ; CHECK-V-NEXT: .LBB21_4: # %entry -; CHECK-V-NEXT: slti a5, s1, 0 +; CHECK-V-NEXT: slti a5, a1, 0 ; CHECK-V-NEXT: bnez a5, .LBB21_6 ; CHECK-V-NEXT: .LBB21_5: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB21_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, a1 +; CHECK-V-NEXT: and a5, a5, s1 ; CHECK-V-NEXT: bnez a4, .LBB21_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB21_8: # %entry -; CHECK-V-NEXT: and a4, a6, s1 +; CHECK-V-NEXT: and a4, a6, a1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB21_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -2725,26 +2723,26 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB21_12 ; CHECK-V-NEXT: .LBB21_10: -; CHECK-V-NEXT: sltu a2, a1, s0 +; CHECK-V-NEXT: sltu a2, a1, a0 ; CHECK-V-NEXT: beqz a2, .LBB21_13 ; CHECK-V-NEXT: j .LBB21_14 ; CHECK-V-NEXT: .LBB21_11: -; CHECK-V-NEXT: sltu a3, a1, a0 +; CHECK-V-NEXT: sltu a3, a1, s0 ; CHECK-V-NEXT: beq a4, a2, .LBB21_10 ; CHECK-V-NEXT: .LBB21_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB21_14 ; CHECK-V-NEXT: .LBB21_13: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB21_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB21_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB21_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a0 -; CHECK-V-NEXT: vmv.s.x v9, s0 +; CHECK-V-NEXT: vmv.s.x v8, s0 +; CHECK-V-NEXT: vmv.s.x v9, a0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2777,19 +2775,19 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.s fs0, fa1 +; CHECK-NOV-NEXT: fmv.s fs0, fa0 +; CHECK-NOV-NEXT: fmv.s fa0, fa1 ; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixunssfti -; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: snez a2, s1 -; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a2, a2, s0 +; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a1, a1, a0 -; CHECK-NOV-NEXT: mv a0, a2 +; CHECK-NOV-NEXT: and a0, a1, a0 +; CHECK-NOV-NEXT: addi a1, a2, -1 +; CHECK-NOV-NEXT: and a1, a1, s0 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2814,25 +2812,25 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 -; CHECK-V-NEXT: vfmv.f.s fa0, v9 +; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload +; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunssfti -; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a2, s1 -; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a2, a2, s0 +; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: addi a2, a2, -1 +; CHECK-V-NEXT: and a2, a2, s0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a0 -; CHECK-V-NEXT: vmv.s.x v9, a2 +; CHECK-V-NEXT: vmv.s.x v8, a2 +; CHECK-V-NEXT: vmv.s.x v9, a0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2874,32 +2872,32 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB23_2: # %entry -; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: slti a4, s1, 1 +; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB23_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB23_4: # %entry -; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 +; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB23_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a4, a4, s0 +; CHECK-NOV-NEXT: and a0, a0, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB23_8 ; CHECK-NOV-NEXT: .LBB23_6: -; CHECK-NOV-NEXT: snez a0, a4 +; CHECK-NOV-NEXT: snez a2, a0 ; CHECK-NOV-NEXT: j .LBB23_9 ; CHECK-NOV-NEXT: .LBB23_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a4, a4, s0 +; CHECK-NOV-NEXT: and a0, a0, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB23_6 ; CHECK-NOV-NEXT: .LBB23_8: # %entry -; CHECK-NOV-NEXT: sgtz a0, a2 +; CHECK-NOV-NEXT: sgtz a2, a2 ; CHECK-NOV-NEXT: .LBB23_9: # %entry -; CHECK-NOV-NEXT: neg a0, a0 -; CHECK-NOV-NEXT: and a0, a0, a4 +; CHECK-NOV-NEXT: neg a2, a2 +; CHECK-NOV-NEXT: and a0, a2, a0 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -2941,15 +2939,15 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB23_2: # %entry -; CHECK-V-NEXT: slti a4, a1, 1 ; CHECK-V-NEXT: slti a3, s1, 1 +; CHECK-V-NEXT: slti a4, a1, 1 ; CHECK-V-NEXT: blez a1, .LBB23_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB23_4: # %entry -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB23_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -3004,8 +3002,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset s2, -32 -; CHECK-NOV-NEXT: mv s2, a1 -; CHECK-NOV-NEXT: fmv.w.x fa0, a0 +; CHECK-NOV-NEXT: mv s2, a0 +; CHECK-NOV-NEXT: fmv.w.x fa0, a1 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 @@ -3013,60 +3011,58 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, a0 -; CHECK-NOV-NEXT: li a0, -1 -; CHECK-NOV-NEXT: srli a3, a0, 1 -; CHECK-NOV-NEXT: beqz a1, .LBB24_3 +; CHECK-NOV-NEXT: li a2, -1 +; CHECK-NOV-NEXT: srli a3, a2, 1 +; CHECK-NOV-NEXT: beqz s1, .LBB24_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, a1, 0 -; CHECK-NOV-NEXT: bnez s1, .LBB24_4 +; CHECK-NOV-NEXT: slti a4, s1, 0 +; CHECK-NOV-NEXT: bnez a1, .LBB24_4 ; CHECK-NOV-NEXT: .LBB24_2: -; CHECK-NOV-NEXT: sltu a5, s0, a3 +; CHECK-NOV-NEXT: sltu a5, a0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB24_5 ; CHECK-NOV-NEXT: j .LBB24_6 ; CHECK-NOV-NEXT: .LBB24_3: -; CHECK-NOV-NEXT: sltu a4, a2, a3 -; CHECK-NOV-NEXT: beqz s1, .LBB24_2 +; CHECK-NOV-NEXT: sltu a4, s0, a3 +; CHECK-NOV-NEXT: beqz a1, .LBB24_2 ; CHECK-NOV-NEXT: .LBB24_4: # %entry -; CHECK-NOV-NEXT: slti a5, s1, 0 +; CHECK-NOV-NEXT: slti a5, a1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB24_6 ; CHECK-NOV-NEXT: .LBB24_5: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a0, a3 ; CHECK-NOV-NEXT: .LBB24_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, a1 +; CHECK-NOV-NEXT: and a5, a5, s1 ; CHECK-NOV-NEXT: bnez a4, .LBB24_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv a2, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB24_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, s1 -; CHECK-NOV-NEXT: slli a1, a0, 63 -; CHECK-NOV-NEXT: beq a5, a0, .LBB24_11 +; CHECK-NOV-NEXT: and a4, a6, a1 +; CHECK-NOV-NEXT: slli a1, a2, 63 +; CHECK-NOV-NEXT: beq a5, a2, .LBB24_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a0, .LBB24_12 +; CHECK-NOV-NEXT: bne a4, a2, .LBB24_12 ; CHECK-NOV-NEXT: .LBB24_10: -; CHECK-NOV-NEXT: sltu a0, a1, s0 -; CHECK-NOV-NEXT: beqz a0, .LBB24_13 +; CHECK-NOV-NEXT: sltu a2, a1, a0 +; CHECK-NOV-NEXT: beqz a2, .LBB24_13 ; CHECK-NOV-NEXT: j .LBB24_14 ; CHECK-NOV-NEXT: .LBB24_11: -; CHECK-NOV-NEXT: sltu a3, a1, a2 -; CHECK-NOV-NEXT: beq a4, a0, .LBB24_10 +; CHECK-NOV-NEXT: sltu a3, a1, s0 +; CHECK-NOV-NEXT: beq a4, a2, .LBB24_10 ; CHECK-NOV-NEXT: .LBB24_12: # %entry -; CHECK-NOV-NEXT: slti a0, a4, 0 -; CHECK-NOV-NEXT: xori a0, a0, 1 -; CHECK-NOV-NEXT: bnez a0, .LBB24_14 +; CHECK-NOV-NEXT: slti a2, a4, 0 +; CHECK-NOV-NEXT: xori a2, a2, 1 +; CHECK-NOV-NEXT: bnez a2, .LBB24_14 ; CHECK-NOV-NEXT: .LBB24_13: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a0, a1 ; CHECK-NOV-NEXT: .LBB24_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB24_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv a2, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB24_16: # %entry -; CHECK-NOV-NEXT: mv a0, s0 -; CHECK-NOV-NEXT: mv a1, a2 +; CHECK-NOV-NEXT: mv a1, s0 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -3086,8 +3082,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s2, -32 -; CHECK-V-NEXT: mv s2, a1 -; CHECK-V-NEXT: fmv.w.x fa0, a0 +; CHECK-V-NEXT: mv s2, a0 +; CHECK-V-NEXT: fmv.w.x fa0, a1 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 @@ -3097,31 +3093,31 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz a1, .LBB24_3 +; CHECK-V-NEXT: beqz s1, .LBB24_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, a1, 0 -; CHECK-V-NEXT: bnez s1, .LBB24_4 +; CHECK-V-NEXT: slti a4, s1, 0 +; CHECK-V-NEXT: bnez a1, .LBB24_4 ; CHECK-V-NEXT: .LBB24_2: -; CHECK-V-NEXT: sltu a5, s0, a3 +; CHECK-V-NEXT: sltu a5, a0, a3 ; CHECK-V-NEXT: beqz a5, .LBB24_5 ; CHECK-V-NEXT: j .LBB24_6 ; CHECK-V-NEXT: .LBB24_3: -; CHECK-V-NEXT: sltu a4, a0, a3 -; CHECK-V-NEXT: beqz s1, .LBB24_2 +; CHECK-V-NEXT: sltu a4, s0, a3 +; CHECK-V-NEXT: beqz a1, .LBB24_2 ; CHECK-V-NEXT: .LBB24_4: # %entry -; CHECK-V-NEXT: slti a5, s1, 0 +; CHECK-V-NEXT: slti a5, a1, 0 ; CHECK-V-NEXT: bnez a5, .LBB24_6 ; CHECK-V-NEXT: .LBB24_5: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB24_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, a1 +; CHECK-V-NEXT: and a5, a5, s1 ; CHECK-V-NEXT: bnez a4, .LBB24_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB24_8: # %entry -; CHECK-V-NEXT: and a4, a6, s1 +; CHECK-V-NEXT: and a4, a6, a1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB24_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -3129,26 +3125,26 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB24_12 ; CHECK-V-NEXT: .LBB24_10: -; CHECK-V-NEXT: sltu a2, a1, s0 +; CHECK-V-NEXT: sltu a2, a1, a0 ; CHECK-V-NEXT: beqz a2, .LBB24_13 ; CHECK-V-NEXT: j .LBB24_14 ; CHECK-V-NEXT: .LBB24_11: -; CHECK-V-NEXT: sltu a3, a1, a0 +; CHECK-V-NEXT: sltu a3, a1, s0 ; CHECK-V-NEXT: beq a4, a2, .LBB24_10 ; CHECK-V-NEXT: .LBB24_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB24_14 ; CHECK-V-NEXT: .LBB24_13: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB24_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB24_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB24_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v9, a0 -; CHECK-V-NEXT: vmv.s.x v8, s0 +; CHECK-V-NEXT: vmv.s.x v9, s0 +; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -3179,8 +3175,8 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset s2, -32 -; CHECK-NOV-NEXT: mv s0, a1 -; CHECK-NOV-NEXT: fmv.w.x fa0, a0 +; CHECK-NOV-NEXT: mv s0, a0 +; CHECK-NOV-NEXT: fmv.w.x fa0, a1 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s1, a0 @@ -3188,13 +3184,12 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s0 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixunssfti -; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: snez a2, s2 -; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a2, a2, s1 +; CHECK-NOV-NEXT: snez a1, a1 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a1, a1, a0 -; CHECK-NOV-NEXT: mv a0, a2 +; CHECK-NOV-NEXT: and a0, a1, a0 +; CHECK-NOV-NEXT: addi a1, a2, -1 +; CHECK-NOV-NEXT: and a1, a1, s1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -3214,8 +3209,8 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s2, -32 -; CHECK-V-NEXT: mv s0, a1 -; CHECK-V-NEXT: fmv.w.x fa0, a0 +; CHECK-V-NEXT: mv s0, a0 +; CHECK-V-NEXT: fmv.w.x fa0, a1 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s1, a0 @@ -3223,15 +3218,15 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixunssfti -; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: snez a2, s2 -; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a2, a2, s1 +; CHECK-V-NEXT: snez a1, a1 ; CHECK-V-NEXT: addi a1, a1, -1 ; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: addi a2, a2, -1 +; CHECK-V-NEXT: and a2, a2, s1 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v9, a0 -; CHECK-V-NEXT: vmv.s.x v8, a2 +; CHECK-V-NEXT: vmv.s.x v9, a2 +; CHECK-V-NEXT: vmv.s.x v8, a0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -3274,32 +3269,32 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB26_2: # %entry -; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: slti a4, s1, 1 +; CHECK-NOV-NEXT: slti a3, a1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB26_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB26_4: # %entry -; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 +; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB26_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a4, a4, s0 +; CHECK-NOV-NEXT: and a0, a0, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB26_8 ; CHECK-NOV-NEXT: .LBB26_6: -; CHECK-NOV-NEXT: snez a0, a4 +; CHECK-NOV-NEXT: snez a2, a0 ; CHECK-NOV-NEXT: j .LBB26_9 ; CHECK-NOV-NEXT: .LBB26_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a4, a4, s0 +; CHECK-NOV-NEXT: and a0, a0, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB26_6 ; CHECK-NOV-NEXT: .LBB26_8: # %entry -; CHECK-NOV-NEXT: sgtz a0, a2 +; CHECK-NOV-NEXT: sgtz a2, a2 ; CHECK-NOV-NEXT: .LBB26_9: # %entry -; CHECK-NOV-NEXT: neg a0, a0 -; CHECK-NOV-NEXT: and a0, a0, a4 +; CHECK-NOV-NEXT: neg a2, a2 +; CHECK-NOV-NEXT: and a0, a2, a0 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -3335,15 +3330,15 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB26_2: # %entry -; CHECK-V-NEXT: slti a4, a1, 1 ; CHECK-V-NEXT: slti a3, s1, 1 +; CHECK-V-NEXT: slti a4, a1, 1 ; CHECK-V-NEXT: blez a1, .LBB26_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB26_4: # %entry -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB26_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -5816,15 +5811,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixdfti -; CHECK-NOV-NEXT: mv a2, a1 +; CHECK-NOV-NEXT: mv a2, s1 +; CHECK-NOV-NEXT: mv a3, a1 ; CHECK-NOV-NEXT: blez a1, .LBB47_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB47_2: # %entry -; CHECK-NOV-NEXT: mv a3, s1 -; CHECK-NOV-NEXT: blez s1, .LBB47_4 +; CHECK-NOV-NEXT: blez a2, .LBB47_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB47_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -5832,11 +5827,11 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 -; CHECK-NOV-NEXT: slti a3, a3, 0 -; CHECK-NOV-NEXT: addi a3, a3, -1 -; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: slti a2, a3, 0 +; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -5872,15 +5867,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixdfti -; CHECK-V-NEXT: mv a2, a1 +; CHECK-V-NEXT: mv a2, s1 +; CHECK-V-NEXT: mv a3, a1 ; CHECK-V-NEXT: blez a1, .LBB47_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB47_2: # %entry -; CHECK-V-NEXT: mv a3, s1 -; CHECK-V-NEXT: blez s1, .LBB47_4 +; CHECK-V-NEXT: blez a2, .LBB47_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB47_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -5888,11 +5883,11 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 -; CHECK-V-NEXT: slti a3, a3, 0 -; CHECK-V-NEXT: addi a3, a3, -1 -; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 +; CHECK-V-NEXT: and a1, a2, a1 +; CHECK-V-NEXT: slti a2, a3, 0 +; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -6202,15 +6197,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, a1 +; CHECK-NOV-NEXT: mv a2, s1 +; CHECK-NOV-NEXT: mv a3, a1 ; CHECK-NOV-NEXT: blez a1, .LBB50_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB50_2: # %entry -; CHECK-NOV-NEXT: mv a3, s1 -; CHECK-NOV-NEXT: blez s1, .LBB50_4 +; CHECK-NOV-NEXT: blez a2, .LBB50_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB50_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -6218,11 +6213,11 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 -; CHECK-NOV-NEXT: slti a3, a3, 0 -; CHECK-NOV-NEXT: addi a3, a3, -1 -; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: slti a2, a3, 0 +; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -6258,15 +6253,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixsfti -; CHECK-V-NEXT: mv a2, a1 +; CHECK-V-NEXT: mv a2, s1 +; CHECK-V-NEXT: mv a3, a1 ; CHECK-V-NEXT: blez a1, .LBB50_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB50_2: # %entry -; CHECK-V-NEXT: mv a3, s1 -; CHECK-V-NEXT: blez s1, .LBB50_4 +; CHECK-V-NEXT: blez a2, .LBB50_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB50_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -6274,11 +6269,11 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 -; CHECK-V-NEXT: slti a3, a3, 0 -; CHECK-V-NEXT: addi a3, a3, -1 -; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 +; CHECK-V-NEXT: and a1, a2, a1 +; CHECK-V-NEXT: slti a2, a3, 0 +; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -6580,15 +6575,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, a1 +; CHECK-NOV-NEXT: mv a2, s1 +; CHECK-NOV-NEXT: mv a3, a1 ; CHECK-NOV-NEXT: blez a1, .LBB53_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB53_2: # %entry -; CHECK-NOV-NEXT: mv a3, s1 -; CHECK-NOV-NEXT: blez s1, .LBB53_4 +; CHECK-NOV-NEXT: blez a2, .LBB53_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB53_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -6596,11 +6591,11 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 -; CHECK-NOV-NEXT: slti a3, a3, 0 -; CHECK-NOV-NEXT: addi a3, a3, -1 -; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: slti a2, a3, 0 +; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -6630,15 +6625,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixsfti -; CHECK-V-NEXT: mv a2, a1 +; CHECK-V-NEXT: mv a2, s1 +; CHECK-V-NEXT: mv a3, a1 ; CHECK-V-NEXT: blez a1, .LBB53_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB53_2: # %entry -; CHECK-V-NEXT: mv a3, s1 -; CHECK-V-NEXT: blez s1, .LBB53_4 +; CHECK-V-NEXT: blez a2, .LBB53_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB53_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -6646,11 +6641,11 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 -; CHECK-V-NEXT: slti a3, a3, 0 -; CHECK-V-NEXT: addi a3, a3, -1 -; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 +; CHECK-V-NEXT: and a1, a2, a1 +; CHECK-V-NEXT: slti a2, a3, 0 +; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v9, a0 diff --git a/llvm/test/CodeGen/X86/abdu-vector-128.ll b/llvm/test/CodeGen/X86/abdu-vector-128.ll index 0c33e8973c2d..dd180b67e492 100644 --- a/llvm/test/CodeGen/X86/abdu-vector-128.ll +++ b/llvm/test/CodeGen/X86/abdu-vector-128.ll @@ -715,41 +715,43 @@ define <2 x i64> @abd_cmp_v2i64_multiuse_cmp(<2 x i64> %a, <2 x i64> %b) nounwin ; ; SSE42-LABEL: abd_cmp_v2i64_multiuse_cmp: ; SSE42: # %bb.0: -; SSE42-NEXT: movdqa %xmm0, %xmm2 -; SSE42-NEXT: psubq %xmm1, %xmm2 +; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] ; SSE42-NEXT: movdqa %xmm1, %xmm3 -; SSE42-NEXT: psubq %xmm0, %xmm3 -; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] -; SSE42-NEXT: pxor %xmm4, %xmm1 -; SSE42-NEXT: pxor %xmm4, %xmm0 -; SSE42-NEXT: pcmpgtq %xmm1, %xmm0 -; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm3 -; SSE42-NEXT: paddq %xmm3, %xmm0 +; SSE42-NEXT: pxor %xmm2, %xmm3 +; SSE42-NEXT: pxor %xmm0, %xmm2 +; SSE42-NEXT: pcmpgtq %xmm3, %xmm2 +; SSE42-NEXT: movdqa %xmm0, %xmm3 +; SSE42-NEXT: psubq %xmm1, %xmm3 +; SSE42-NEXT: psubq %xmm0, %xmm1 +; SSE42-NEXT: movdqa %xmm2, %xmm0 +; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm1 +; SSE42-NEXT: paddq %xmm1, %xmm2 +; SSE42-NEXT: movdqa %xmm2, %xmm0 ; SSE42-NEXT: retq ; ; AVX1-LABEL: abd_cmp_v2i64_multiuse_cmp: ; AVX1: # %bb.0: -; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm2 -; AVX1-NEXT: vpsubq %xmm0, %xmm1, %xmm3 -; AVX1-NEXT: vmovddup {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] -; AVX1-NEXT: # xmm4 = mem[0,0] -; AVX1-NEXT: vpxor %xmm4, %xmm1, %xmm1 -; AVX1-NEXT: vpxor %xmm4, %xmm0, %xmm0 -; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 -; AVX1-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm1 -; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX1-NEXT: # xmm2 = mem[0,0] +; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 +; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2 +; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm3 +; AVX1-NEXT: vpsubq %xmm0, %xmm1, %xmm0 +; AVX1-NEXT: vblendvpd %xmm2, %xmm3, %xmm0, %xmm0 +; AVX1-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: abd_cmp_v2i64_multiuse_cmp: ; AVX2: # %bb.0: -; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm2 -; AVX2-NEXT: vpsubq %xmm0, %xmm1, %xmm3 -; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] -; AVX2-NEXT: vpxor %xmm4, %xmm1, %xmm1 -; AVX2-NEXT: vpxor %xmm4, %xmm0, %xmm0 -; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 -; AVX2-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm1 -; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 +; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2 +; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 +; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm3 +; AVX2-NEXT: vpsubq %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vblendvpd %xmm2, %xmm3, %xmm0, %xmm0 +; AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: abd_cmp_v2i64_multiuse_cmp: diff --git a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll index b2cb2c3e04b3..017024c173c3 100644 --- a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll +++ b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll @@ -52,7 +52,10 @@ alloca_21: define i32 @kmovrk_1(<4 x ptr> %arg) { ; AVX512-LABEL: kmovrk_1: ; AVX512: # %bb.0: # %bb -; AVX512-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] +; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 +; AVX512-NEXT: vptestmq %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc0] +; AVX512-NEXT: kmovw %k0, %eax # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x93,0xc0] +; AVX512-NEXT: testb $15, %al # encoding: [0xa8,0x0f] ; AVX512-NEXT: jne .LBB2_1 # encoding: [0x75,A] ; AVX512-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 ; AVX512-NEXT: # %bb.2: # %bb3 @@ -63,7 +66,10 @@ define i32 @kmovrk_1(<4 x ptr> %arg) { ; ; AVX512BW-LABEL: kmovrk_1: ; AVX512BW: # %bb.0: # %bb -; AVX512BW-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] +; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 +; AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc0] +; AVX512BW-NEXT: kmovd %k0, %eax # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x93,0xc0] +; AVX512BW-NEXT: testb $15, %al # encoding: [0xa8,0x0f] ; AVX512BW-NEXT: jne .LBB2_1 # encoding: [0x75,A] ; AVX512BW-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 ; AVX512BW-NEXT: # %bb.2: # %bb3 diff --git a/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll b/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll index 7e48b3719cf0..13d1265a249d 100644 --- a/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll +++ b/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll @@ -30,13 +30,13 @@ define <64 x i8> @add_v64i8_broadcasts(<64 x i8> %a0, i64 %a1, i8 %a2) { ; AVX512F-NEXT: vinserti128 $1, %xmm4, %ymm3, %ymm3 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-NEXT: vpternlogq $216, %zmm2, %zmm1, %zmm0 -; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3 -; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm3 +; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm3 +; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm0 ; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0 -; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm4 -; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm3 +; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm4 ; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0 -; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 +; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm1 +; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512F-NEXT: vpternlogq $226, %zmm4, %zmm2, %zmm0 ; AVX512F-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/combine-mul.ll b/llvm/test/CodeGen/X86/combine-mul.ll index 5d7bf4a2c978..8d2bb77a9e1a 100644 --- a/llvm/test/CodeGen/X86/combine-mul.ll +++ b/llvm/test/CodeGen/X86/combine-mul.ll @@ -80,13 +80,13 @@ define <4 x i32> @combine_vec_mul_pow2b(<4 x i32> %x) { define <4 x i64> @combine_vec_mul_pow2c(<4 x i64> %x) { ; SSE-LABEL: combine_vec_mul_pow2c: ; SSE: # %bb.0: -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: paddq %xmm0, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: psllq $4, %xmm2 ; SSE-NEXT: psllq $2, %xmm1 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: paddq %xmm0, %xmm2 +; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_mul_pow2c: @@ -399,12 +399,14 @@ define i64 @combine_mul_self_demandedbits(i64 %x) { ; SSE: # %bb.0: ; SSE-NEXT: movq %rdi, %rax ; SSE-NEXT: imulq %rdi, %rax +; SSE-NEXT: andq $-3, %rax ; SSE-NEXT: retq ; ; AVX-LABEL: combine_mul_self_demandedbits: ; AVX: # %bb.0: ; AVX-NEXT: movq %rdi, %rax ; AVX-NEXT: imulq %rdi, %rax +; AVX-NEXT: andq $-3, %rax ; AVX-NEXT: retq %1 = mul i64 %x, %x %2 = and i64 %1, -3 diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll index 33cc8e96f663..e12ca56023a7 100644 --- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll +++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll @@ -182,101 +182,101 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: sarl $31, %eax -; X86-NEXT: movl %edx, %ebx -; X86-NEXT: sarl $31, %ebx +; X86-NEXT: movl %edx, %edi +; X86-NEXT: sarl $31, %edi ; X86-NEXT: movl %eax, %esi ; X86-NEXT: xorl %ecx, %esi ; X86-NEXT: movl %esi, %ebp ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl %ecx, %edi +; X86-NEXT: movl %ecx, %ebx ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %eax, %esi ; X86-NEXT: xorl {{[0-9]+}}(%esp), %esi ; X86-NEXT: subl %eax, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %esi, (%esp) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %eax, %edi -; X86-NEXT: movl %edi, (%esp) # 4-byte Spill +; X86-NEXT: sbbl %eax, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ebp ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, %esi +; X86-NEXT: movl %edi, %esi ; X86-NEXT: xorl %edx, %esi -; X86-NEXT: movl %ebx, %edx +; X86-NEXT: movl %edi, %edx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %edx -; X86-NEXT: movl %ebx, %edi -; X86-NEXT: xorl {{[0-9]+}}(%esp), %edi -; X86-NEXT: movl %ebx, %ebp +; X86-NEXT: movl %edi, %ebx +; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebx +; X86-NEXT: movl %edi, %ebp ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: subl %ebx, %ebp -; X86-NEXT: sbbl %ebx, %edi -; X86-NEXT: sbbl %ebx, %edx -; X86-NEXT: sbbl %ebx, %esi -; X86-NEXT: xorl %eax, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, %eax +; X86-NEXT: subl %edi, %ebp +; X86-NEXT: sbbl %edi, %ebx +; X86-NEXT: sbbl %edi, %edx +; X86-NEXT: sbbl %edi, %esi +; X86-NEXT: xorl %eax, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, %eax ; X86-NEXT: orl %esi, %eax ; X86-NEXT: movl %ebp, %ecx ; X86-NEXT: orl %edx, %ecx -; X86-NEXT: movl %edx, %ebx +; X86-NEXT: movl %edx, %edi ; X86-NEXT: orl %eax, %ecx ; X86-NEXT: sete %cl ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: orl (%esp), %edx # 4-byte Folded Reload +; X86-NEXT: movl (%esp), %edx # 4-byte Reload +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: orl %eax, %edx ; X86-NEXT: sete %al ; X86-NEXT: orb %cl, %al ; X86-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; X86-NEXT: bsrl %esi, %edx ; X86-NEXT: xorl $31, %edx -; X86-NEXT: bsrl %ebx, %ecx +; X86-NEXT: bsrl %edi, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx ; X86-NEXT: testl %esi, %esi ; X86-NEXT: cmovnel %edx, %ecx -; X86-NEXT: bsrl %edi, %edx +; X86-NEXT: bsrl %ebx, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: bsrl %ebp, %ebp ; X86-NEXT: xorl $31, %ebp ; X86-NEXT: addl $32, %ebp -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: testl %edi, %edi +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: testl %ebx, %ebx ; X86-NEXT: cmovnel %edx, %ebp ; X86-NEXT: addl $64, %ebp -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %ebx +; X86-NEXT: orl %esi, %edi ; X86-NEXT: cmovnel %ecx, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: bsrl %ebx, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: bsrl %edi, %edx ; X86-NEXT: xorl $31, %edx -; X86-NEXT: movl (%esp), %eax # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: bsrl %eax, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx -; X86-NEXT: testl %ebx, %ebx +; X86-NEXT: testl %edi, %edi ; X86-NEXT: cmovnel %edx, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: bsrl %edi, %esi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: bsrl %ebx, %esi ; X86-NEXT: xorl $31, %esi -; X86-NEXT: bsrl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: bsrl (%esp), %edx # 4-byte Folded Reload ; X86-NEXT: xorl $31, %edx ; X86-NEXT: addl $32, %edx -; X86-NEXT: testl %edi, %edi +; X86-NEXT: testl %ebx, %ebx ; X86-NEXT: cmovnel %esi, %edx ; X86-NEXT: addl $64, %edx ; X86-NEXT: movl %eax, %esi -; X86-NEXT: orl %ebx, %esi +; X86-NEXT: orl %edi, %esi ; X86-NEXT: cmovnel %ecx, %edx ; X86-NEXT: xorl %esi, %esi ; X86-NEXT: subl %edx, %ebp -; X86-NEXT: movl $0, %edi -; X86-NEXT: sbbl %edi, %edi +; X86-NEXT: movl $0, %ebx +; X86-NEXT: sbbl %ebx, %ebx ; X86-NEXT: movl $0, %edx ; X86-NEXT: sbbl %edx, %edx ; X86-NEXT: movl $0, %eax @@ -284,39 +284,39 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl $127, %ecx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: cmpl %ebp, %ecx -; X86-NEXT: movl %edx, %ebp ; X86-NEXT: movl $0, %ecx -; X86-NEXT: sbbl %edi, %ecx +; X86-NEXT: sbbl %ebx, %ecx ; X86-NEXT: movl $0, %ecx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %edx, %ecx ; X86-NEXT: movl $0, %ecx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: setb %cl ; X86-NEXT: orb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Folded Reload -; X86-NEXT: movl %ebx, %edx +; X86-NEXT: cmovnel %esi, %edi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: cmovnel %esi, %edx -; X86-NEXT: movl (%esp), %ebx # 4-byte Reload -; X86-NEXT: cmovnel %esi, %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: cmovnel %esi, %eax -; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload +; X86-NEXT: cmovel (%esp), %esi # 4-byte Folded Reload +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-NEXT: jne .LBB4_8 ; X86-NEXT: # %bb.1: # %_udiv-special-cases -; X86-NEXT: movl %edi, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: xorl $127, %edi -; X86-NEXT: orl %ebp, %edi +; X86-NEXT: movl %ebx, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: xorl $127, %ebx +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: orl %edi, %ecx +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: je .LBB4_8 ; X86-NEXT: # %bb.2: # %udiv-bb1 -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) -; X86-NEXT: movl (%esp), %eax # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) @@ -332,44 +332,41 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: shrb $3, %al ; X86-NEXT: andb $15, %al ; X86-NEXT: negb %al -; X86-NEXT: movsbl %al, %edi -; X86-NEXT: movl 144(%esp,%edi), %edx -; X86-NEXT: movl 148(%esp,%edi), %esi +; X86-NEXT: movsbl %al, %ebx +; X86-NEXT: movl 144(%esp,%ebx), %edx +; X86-NEXT: movl 148(%esp,%ebx), %edi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %edx, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl %cl, %edx, %edi ; X86-NEXT: shll %cl, %edx ; X86-NEXT: notb %cl -; X86-NEXT: movl 140(%esp,%edi), %eax -; X86-NEXT: movl %eax, %ebx -; X86-NEXT: shrl %ebx -; X86-NEXT: shrl %cl, %ebx -; X86-NEXT: orl %edx, %ebx -; X86-NEXT: movl 136(%esp,%edi), %edx +; X86-NEXT: movl 140(%esp,%ebx), %eax +; X86-NEXT: movl %eax, %esi +; X86-NEXT: shrl %esi +; X86-NEXT: shrl %cl, %esi +; X86-NEXT: orl %edx, %esi +; X86-NEXT: movl %esi, %edx +; X86-NEXT: movl 136(%esp,%ebx), %esi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %edx, %eax -; X86-NEXT: shll %cl, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl %cl, %esi, %eax +; X86-NEXT: shll %cl, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: addl $1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: adcl $0, %ecx -; X86-NEXT: adcl $0, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: adcl $0, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: adcl $0, %ebx +; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: jae .LBB4_3 ; X86-NEXT: # %bb.6: -; X86-NEXT: xorl %edi, %edi -; X86-NEXT: xorl %ecx, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: xorl %ebx, %ebx +; X86-NEXT: xorl %esi, %esi ; X86-NEXT: jmp .LBB4_7 ; X86-NEXT: .LBB4_3: # %udiv-preheader -; X86-NEXT: movl %ecx, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: movl (%esp), %esi # 4-byte Reload ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) -; X86-NEXT: movl (%esp), %esi # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) @@ -377,188 +374,192 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movb %dl, %ch +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movb %bl, %ch ; X86-NEXT: andb $7, %ch -; X86-NEXT: movb %dl, %cl +; X86-NEXT: movb %bl, %cl ; X86-NEXT: shrb $3, %cl ; X86-NEXT: andb $15, %cl -; X86-NEXT: movzbl %cl, %edx -; X86-NEXT: movl 100(%esp,%edx), %esi -; X86-NEXT: movl %esi, (%esp) # 4-byte Spill -; X86-NEXT: movl 96(%esp,%edx), %edi -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, %ebp +; X86-NEXT: movzbl %cl, %ebp +; X86-NEXT: movl 100(%esp,%ebp), %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 96(%esp,%ebp), %ebx +; X86-NEXT: movl %ebp, %eax +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, %edx ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrdl %cl, %esi, %ebp -; X86-NEXT: movl 88(%esp,%edx), %ebx -; X86-NEXT: movl 92(%esp,%edx), %esi -; X86-NEXT: movl %esi, %edx -; X86-NEXT: shrl %cl, %edx +; X86-NEXT: shrdl %cl, %esi, %edx +; X86-NEXT: movl 88(%esp,%ebp), %ebp +; X86-NEXT: movl 92(%esp,%eax), %esi +; X86-NEXT: movl %esi, %eax +; X86-NEXT: shrl %cl, %eax ; X86-NEXT: notb %cl -; X86-NEXT: addl %edi, %edi -; X86-NEXT: shll %cl, %edi -; X86-NEXT: orl %edx, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrl %cl, (%esp) # 4-byte Folded Spill -; X86-NEXT: shrdl %cl, %esi, %ebx +; X86-NEXT: addl %ebx, %ebx +; X86-NEXT: shll %cl, %ebx +; X86-NEXT: orl %eax, %ebx ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movb %ch, %cl +; X86-NEXT: shrl %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: shrdl %cl, %esi, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: addl $-1, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: adcl $-1, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: adcl $-1, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: addl $-1, %ecx -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: adcl $-1, %ecx -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: adcl $-1, %ecx -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: adcl $-1, %ecx -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: adcl $-1, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: xorl %esi, %esi ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .LBB4_4: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebp, %esi -; X86-NEXT: shldl $1, %ebp, (%esp) # 4-byte Folded Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload -; X86-NEXT: shldl $1, %ebp, %esi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: shldl $1, %edx, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: shldl $1, %edi, %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: shldl $1, %ecx, %edi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: orl %ebx, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: shldl $1, %eax, %ecx -; X86-NEXT: orl %ebx, %ecx -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $1, %edx, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: shldl $1, %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: shldl $1, %ebp, %edx +; X86-NEXT: shldl $1, %edi, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: shldl $1, %eax, %edi +; X86-NEXT: orl %esi, %edi +; X86-NEXT: movl %edi, (%esp) # 4-byte Spill +; X86-NEXT: movl %ecx, %edi ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: shldl $1, %ecx, %eax -; X86-NEXT: orl %ebx, %eax +; X86-NEXT: orl %esi, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: addl %ecx, %ecx -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: shldl $1, %eax, %ecx +; X86-NEXT: orl %esi, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload +; X86-NEXT: addl %eax, %eax +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: cmpl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl %ebp, %ecx +; X86-NEXT: sbbl %edx, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl %esi, %ecx +; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl (%esp), %ecx # 4-byte Folded Reload +; X86-NEXT: sbbl %ebx, %ecx ; X86-NEXT: sarl $31, %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: andl $1, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ecx, %ebx -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: andl %edi, %esi ; X86-NEXT: movl %ecx, %edi ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: subl %ecx, %edx +; X86-NEXT: subl %ecx, %ebp +; X86-NEXT: sbbl %eax, %edx ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: sbbl %eax, %ebp -; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %edi, %esi -; X86-NEXT: movl %esi, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: sbbl %ebx, (%esp) # 4-byte Folded Spill +; X86-NEXT: sbbl %edi, %edx +; X86-NEXT: movl (%esp), %edi # 4-byte Reload +; X86-NEXT: sbbl %esi, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: addl $-1, %ecx -; X86-NEXT: adcl $-1, %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: adcl $-1, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: adcl $-1, %eax ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: adcl $-1, %esi -; X86-NEXT: movl %edx, %edi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %edi +; X86-NEXT: adcl $-1, %ebx +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %ebx, %eax ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %ebx, %ecx -; X86-NEXT: orl %edi, %ecx +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %esi, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: orl %eax, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: jne .LBB4_4 ; X86-NEXT: # %bb.5: -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: .LBB4_7: # %udiv-loop-exit -; X86-NEXT: shldl $1, %ebx, %edx -; X86-NEXT: orl %ecx, %edx -; X86-NEXT: shldl $1, %eax, %ebx -; X86-NEXT: orl %ecx, %ebx +; X86-NEXT: shldl $1, %edx, %edi +; X86-NEXT: orl %esi, %edi +; X86-NEXT: shldl $1, %eax, %edx +; X86-NEXT: orl %esi, %edx +; X86-NEXT: movl %esi, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: shldl $1, %esi, %eax ; X86-NEXT: orl %ecx, %eax ; X86-NEXT: addl %esi, %esi -; X86-NEXT: orl %edi, %esi +; X86-NEXT: orl %ebx, %esi ; X86-NEXT: .LBB4_8: # %udiv-end ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: xorl %ecx, %edi ; X86-NEXT: xorl %ecx, %edx -; X86-NEXT: xorl %ecx, %ebx ; X86-NEXT: xorl %ecx, %eax ; X86-NEXT: xorl %ecx, %esi ; X86-NEXT: subl %ecx, %esi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %ecx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %ecx, %ebx ; X86-NEXT: sbbl %ecx, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl %esi, (%ecx) -; X86-NEXT: movl %eax, 4(%ecx) -; X86-NEXT: movl %ebx, 8(%ecx) -; X86-NEXT: movl %edx, 12(%ecx) -; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: sbbl %ecx, %edi +; X86-NEXT: movl %edi, (%esp) # 4-byte Spill +; X86-NEXT: movl %esi, (%ebp) +; X86-NEXT: movl %eax, 4(%ebp) +; X86-NEXT: movl %edx, 8(%ebp) +; X86-NEXT: movl %edi, 12(%ebp) +; X86-NEXT: movl {{[0-9]+}}(%esp), %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: movl %ebx, %edi -; X86-NEXT: mull %ecx ; X86-NEXT: movl %edx, %ebx +; X86-NEXT: mull %edi +; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, %eax -; X86-NEXT: mull %ecx -; X86-NEXT: movl %eax, (%esp) # 4-byte Spill -; X86-NEXT: movl %edx, %ecx -; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: adcl $0, %ebx +; X86-NEXT: mull %edi +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edx, %edi +; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload +; X86-NEXT: adcl $0, %ecx ; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: mull %esi -; X86-NEXT: addl %ecx, %eax +; X86-NEXT: addl %edi, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: adcl %ebx, %edx -; X86-NEXT: movl %edx, %ebx +; X86-NEXT: adcl %ecx, %edx +; X86-NEXT: movl %edx, %edi ; X86-NEXT: setb %cl ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: addl %ebx, %eax +; X86-NEXT: addl %edi, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movzbl %cl, %eax ; X86-NEXT: adcl %eax, %edx ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movl (%esp), %ecx # 4-byte Reload ; X86-NEXT: imull %eax, %ecx -; X86-NEXT: mull %edi -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: imull {{[0-9]+}}(%esp), %edi -; X86-NEXT: addl %edx, %edi -; X86-NEXT: addl %ecx, %edi +; X86-NEXT: mull %ebx +; X86-NEXT: movl %eax, (%esp) # 4-byte Spill +; X86-NEXT: imull {{[0-9]+}}(%esp), %ebx +; X86-NEXT: addl %edx, %ebx +; X86-NEXT: addl %ecx, %ebx ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: imull %esi, %ecx @@ -567,12 +568,12 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: mull %edx ; X86-NEXT: addl %edx, %ebp ; X86-NEXT: addl %ecx, %ebp -; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: adcl %edi, %ebp +; X86-NEXT: addl (%esp), %eax # 4-byte Folded Reload +; X86-NEXT: adcl %ebx, %ebp ; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: subl (%esp), %edx # 4-byte Folded Reload +; X86-NEXT: subl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi diff --git a/llvm/test/CodeGen/X86/fold-masked-merge.ll b/llvm/test/CodeGen/X86/fold-masked-merge.ll index b2614c5fe049..135494ac25f8 100644 --- a/llvm/test/CodeGen/X86/fold-masked-merge.ll +++ b/llvm/test/CodeGen/X86/fold-masked-merge.ll @@ -56,7 +56,9 @@ define i8 @masked_merge2(i8 %a0, i8 %a1, i8 %a2) { ; NOBMI-LABEL: masked_merge2: ; NOBMI: # %bb.0: ; NOBMI-NEXT: movl %esi, %eax -; NOBMI-NEXT: # kill: def $al killed $al killed $eax +; NOBMI-NEXT: xorb %sil, %al +; NOBMI-NEXT: andb %dil, %al +; NOBMI-NEXT: xorb %sil, %al ; NOBMI-NEXT: retq ; ; BMI-LABEL: masked_merge2: diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll index c79da37988e4..b212e9438e1b 100644 --- a/llvm/test/CodeGen/X86/freeze-binary.ll +++ b/llvm/test/CodeGen/X86/freeze-binary.ll @@ -459,7 +459,8 @@ define i32 @freeze_ashr(i32 %a0) nounwind { ; X64-LABEL: freeze_ashr: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: sarl $6, %eax +; X64-NEXT: sarl $3, %eax +; X64-NEXT: sarl $3, %eax ; X64-NEXT: retq %x = ashr i32 %a0, 3 %y = freeze i32 %x @@ -530,12 +531,30 @@ define i32 @freeze_ashr_outofrange(i32 %a0) nounwind { define <8 x i16> @freeze_ashr_vec(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_ashr_vec: ; X86: # %bb.0: -; X86-NEXT: psraw $4, %xmm0 +; X86-NEXT: movdqa %xmm0, %xmm2 +; X86-NEXT: psraw $1, %xmm2 +; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] +; X86-NEXT: movdqa %xmm1, %xmm3 +; X86-NEXT: pandn %xmm2, %xmm3 +; X86-NEXT: psraw $3, %xmm0 +; X86-NEXT: pand %xmm1, %xmm0 +; X86-NEXT: por %xmm3, %xmm0 +; X86-NEXT: movdqa %xmm0, %xmm2 +; X86-NEXT: psraw $3, %xmm2 +; X86-NEXT: psraw $1, %xmm0 +; X86-NEXT: pand %xmm1, %xmm0 +; X86-NEXT: pandn %xmm2, %xmm1 +; X86-NEXT: por %xmm1, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_ashr_vec: ; X64: # %bb.0: -; X64-NEXT: vpsraw $4, %xmm0, %xmm0 +; X64-NEXT: vpsraw $1, %xmm0, %xmm1 +; X64-NEXT: vpsraw $3, %xmm0, %xmm0 +; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; X64-NEXT: vpsraw $3, %xmm0, %xmm1 +; X64-NEXT: vpsraw $1, %xmm0, %xmm0 +; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] ; X64-NEXT: retq %x = ashr <8 x i16> %a0, %y = freeze <8 x i16> %x @@ -573,7 +592,8 @@ define i32 @freeze_lshr(i32 %a0) nounwind { ; X64-LABEL: freeze_lshr: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: shrl $3, %eax +; X64-NEXT: shrl $2, %eax +; X64-NEXT: shrl %eax ; X64-NEXT: retq %x = lshr i32 %a0, 2 %y = freeze i32 %x @@ -644,12 +664,30 @@ define i32 @freeze_lshr_outofrange(i32 %a0) nounwind { define <8 x i16> @freeze_lshr_vec(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_lshr_vec: ; X86: # %bb.0: -; X86-NEXT: psrlw $3, %xmm0 +; X86-NEXT: movdqa %xmm0, %xmm2 +; X86-NEXT: psrlw $1, %xmm2 +; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] +; X86-NEXT: movdqa %xmm1, %xmm3 +; X86-NEXT: pandn %xmm2, %xmm3 +; X86-NEXT: psrlw $2, %xmm0 +; X86-NEXT: pand %xmm1, %xmm0 +; X86-NEXT: por %xmm3, %xmm0 +; X86-NEXT: movdqa %xmm0, %xmm2 +; X86-NEXT: psrlw $2, %xmm2 +; X86-NEXT: psrlw $1, %xmm0 +; X86-NEXT: pand %xmm1, %xmm0 +; X86-NEXT: pandn %xmm2, %xmm1 +; X86-NEXT: por %xmm1, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_lshr_vec: ; X64: # %bb.0: -; X64-NEXT: vpsrlw $3, %xmm0, %xmm0 +; X64-NEXT: vpsrlw $1, %xmm0, %xmm1 +; X64-NEXT: vpsrlw $2, %xmm0, %xmm0 +; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; X64-NEXT: vpsrlw $2, %xmm0, %xmm1 +; X64-NEXT: vpsrlw $1, %xmm0, %xmm0 +; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] ; X64-NEXT: retq %x = lshr <8 x i16> %a0, %y = freeze <8 x i16> %x diff --git a/llvm/test/CodeGen/X86/freeze-combine.ll b/llvm/test/CodeGen/X86/freeze-combine.ll index 1cfb8627a4dd..b037a6d9a1b9 100644 --- a/llvm/test/CodeGen/X86/freeze-combine.ll +++ b/llvm/test/CodeGen/X86/freeze-combine.ll @@ -3,9 +3,9 @@ define i32 @const() { ; CHECK-LABEL: name: const ; CHECK: bb.0 (%ir-block.0): - ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 - ; CHECK-NEXT: $eax = COPY [[MOV32ri]] - ; CHECK-NEXT: RET 0, $eax + ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 + ; CHECK: $eax = COPY [[MOV32ri]] + ; CHECK: RET 0, $eax %y = freeze i32 1 ret i32 %y } @@ -13,11 +13,11 @@ define i32 @const() { define i32 @fold(i32 %x) { ; CHECK-LABEL: name: fold ; CHECK: bb.0 (%ir-block.0): - ; CHECK-NEXT: liveins: $edi - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK-NEXT: $eax = COPY [[COPY]] - ; CHECK-NEXT: RET 0, $eax + ; CHECK: liveins: $edi + ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]] + ; CHECK: $eax = COPY [[COPY1]] + ; CHECK: RET 0, $eax %y = freeze i32 %x %z = freeze i32 %y ret i32 %z diff --git a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll index afe0ebb9dcb4..0c341dc63a9e 100644 --- a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll +++ b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll @@ -522,17 +522,17 @@ declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) define <16 x i8> @splatconstant_fshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind { ; GFNISSE-LABEL: splatconstant_fshr_v16i8: ; GFNISSE: # %bb.0: -; GFNISSE-NEXT: paddb %xmm0, %xmm0 ; GFNISSE-NEXT: psrlw $7, %xmm1 ; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; GFNISSE-NEXT: paddb %xmm0, %xmm0 ; GFNISSE-NEXT: por %xmm1, %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: splatconstant_fshr_v16i8: ; GFNIAVX1OR2: # %bb.0: -; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm1, %xmm1 ; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 +; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/gfni-rotates.ll b/llvm/test/CodeGen/X86/gfni-rotates.ll index 96aff5b2af31..7ab8300b269a 100644 --- a/llvm/test/CodeGen/X86/gfni-rotates.ll +++ b/llvm/test/CodeGen/X86/gfni-rotates.ll @@ -421,18 +421,18 @@ define <16 x i8> @splatconstant_rotr_v16i8(<16 x i8> %a) nounwind { ; GFNISSE-LABEL: splatconstant_rotr_v16i8: ; GFNISSE: # %bb.0: ; GFNISSE-NEXT: movdqa %xmm0, %xmm1 -; GFNISSE-NEXT: paddb %xmm0, %xmm1 -; GFNISSE-NEXT: psrlw $7, %xmm0 -; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; GFNISSE-NEXT: psrlw $7, %xmm1 +; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; GFNISSE-NEXT: paddb %xmm0, %xmm0 ; GFNISSE-NEXT: por %xmm1, %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: splatconstant_rotr_v16i8: ; GFNIAVX1OR2: # %bb.0: -; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm1 -; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpor %xmm0, %xmm1, %xmm0 +; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm1 +; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 +; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; ; GFNIAVX512-LABEL: splatconstant_rotr_v16i8: diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll index 2f780e3c6fe1..39d02f9112f4 100644 --- a/llvm/test/CodeGen/X86/known-never-zero.ll +++ b/llvm/test/CodeGen/X86/known-never-zero.ll @@ -676,13 +676,12 @@ define i32 @rotr_known_nonzero(i32 %xx, i32 %y) { ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx ; X64-NEXT: orl $256, %edi # imm = 0x100 -; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %eax +; X64-NEXT: rorl %cl, %edi ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB22_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %eax, %eax +; X64-NEXT: rep bsfl %edi, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB22_1: ; X64-NEXT: movl $32, %eax @@ -714,13 +713,12 @@ define i32 @rotr_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotr_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx -; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %eax +; X64-NEXT: rorl %cl, %edi ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB23_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %eax, %eax +; X64-NEXT: rep bsfl %edi, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB23_1: ; X64-NEXT: movl $32, %eax @@ -775,13 +773,12 @@ define i32 @rotr_with_fshr_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotr_with_fshr_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx -; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %eax +; X64-NEXT: rorl %cl, %edi ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB25_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %eax, %eax +; X64-NEXT: rep bsfl %edi, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB25_1: ; X64-NEXT: movl $32, %eax @@ -811,13 +808,12 @@ define i32 @rotl_known_nonzero(i32 %xx, i32 %y) { ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx ; X64-NEXT: orl $256, %edi # imm = 0x100 -; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %eax +; X64-NEXT: roll %cl, %edi ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB26_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %eax, %eax +; X64-NEXT: rep bsfl %edi, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB26_1: ; X64-NEXT: movl $32, %eax @@ -849,13 +845,12 @@ define i32 @rotl_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotl_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx -; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %eax +; X64-NEXT: roll %cl, %edi ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB27_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %eax, %eax +; X64-NEXT: rep bsfl %edi, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB27_1: ; X64-NEXT: movl $32, %eax @@ -910,13 +905,12 @@ define i32 @rotl_with_fshl_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotl_with_fshl_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx -; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %eax +; X64-NEXT: roll %cl, %edi ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB29_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %eax, %eax +; X64-NEXT: rep bsfl %edi, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB29_1: ; X64-NEXT: movl $32, %eax diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll index 5a6375e08bca..d3cced3233ea 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll @@ -893,26 +893,27 @@ define <2 x i64> @vec128_i64_signed_reg_reg(<2 x i64> %a1, <2 x i64> %a2) nounwi ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm5, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] -; SSE41-NEXT: por %xmm3, %xmm0 -; SSE41-NEXT: pmovsxbq {{.*#+}} xmm3 = [1,1] -; SSE41-NEXT: por %xmm0, %xmm3 -; SSE41-NEXT: movdqa %xmm2, %xmm4 -; SSE41-NEXT: psubq %xmm1, %xmm4 +; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3] +; SSE41-NEXT: por %xmm3, %xmm6 +; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 +; SSE41-NEXT: pand %xmm5, %xmm0 +; SSE41-NEXT: por %xmm4, %xmm0 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: psubq %xmm1, %xmm3 ; SSE41-NEXT: psubq %xmm2, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 +; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 ; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: psrlq $1, %xmm0 ; SSE41-NEXT: psrlq $33, %xmm1 -; SSE41-NEXT: pmuludq %xmm3, %xmm1 -; SSE41-NEXT: movdqa %xmm3, %xmm4 -; SSE41-NEXT: psrlq $32, %xmm4 -; SSE41-NEXT: pmuludq %xmm0, %xmm4 -; SSE41-NEXT: paddq %xmm1, %xmm4 -; SSE41-NEXT: psllq $32, %xmm4 -; SSE41-NEXT: pmuludq %xmm3, %xmm0 +; SSE41-NEXT: pmuludq %xmm6, %xmm1 +; SSE41-NEXT: movdqa %xmm6, %xmm3 +; SSE41-NEXT: psrlq $32, %xmm3 +; SSE41-NEXT: pmuludq %xmm0, %xmm3 +; SSE41-NEXT: paddq %xmm1, %xmm3 +; SSE41-NEXT: psllq $32, %xmm3 +; SSE41-NEXT: pmuludq %xmm6, %xmm0 ; SSE41-NEXT: paddq %xmm2, %xmm0 -; SSE41-NEXT: paddq %xmm4, %xmm0 +; SSE41-NEXT: paddq %xmm3, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: vec128_i64_signed_reg_reg: @@ -1076,26 +1077,27 @@ define <2 x i64> @vec128_i64_unsigned_reg_reg(<2 x i64> %a1, <2 x i64> %a2) noun ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm5, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] -; SSE41-NEXT: por %xmm3, %xmm0 -; SSE41-NEXT: pmovsxbq {{.*#+}} xmm3 = [1,1] -; SSE41-NEXT: por %xmm0, %xmm3 -; SSE41-NEXT: movdqa %xmm2, %xmm4 -; SSE41-NEXT: psubq %xmm1, %xmm4 +; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3] +; SSE41-NEXT: por %xmm3, %xmm6 +; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 +; SSE41-NEXT: pand %xmm5, %xmm0 +; SSE41-NEXT: por %xmm4, %xmm0 +; SSE41-NEXT: movdqa %xmm2, %xmm3 +; SSE41-NEXT: psubq %xmm1, %xmm3 ; SSE41-NEXT: psubq %xmm2, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 +; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 ; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: psrlq $1, %xmm0 ; SSE41-NEXT: psrlq $33, %xmm1 -; SSE41-NEXT: pmuludq %xmm3, %xmm1 -; SSE41-NEXT: movdqa %xmm3, %xmm4 -; SSE41-NEXT: psrlq $32, %xmm4 -; SSE41-NEXT: pmuludq %xmm0, %xmm4 -; SSE41-NEXT: paddq %xmm1, %xmm4 -; SSE41-NEXT: psllq $32, %xmm4 -; SSE41-NEXT: pmuludq %xmm3, %xmm0 +; SSE41-NEXT: pmuludq %xmm6, %xmm1 +; SSE41-NEXT: movdqa %xmm6, %xmm3 +; SSE41-NEXT: psrlq $32, %xmm3 +; SSE41-NEXT: pmuludq %xmm0, %xmm3 +; SSE41-NEXT: paddq %xmm1, %xmm3 +; SSE41-NEXT: psllq $32, %xmm3 +; SSE41-NEXT: pmuludq %xmm6, %xmm0 ; SSE41-NEXT: paddq %xmm2, %xmm0 -; SSE41-NEXT: paddq %xmm4, %xmm0 +; SSE41-NEXT: paddq %xmm3, %xmm0 ; SSE41-NEXT: retq ; ; AVX1-LABEL: vec128_i64_unsigned_reg_reg: @@ -1991,14 +1993,14 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun ; ; AVX512VL-FALLBACK-LABEL: vec128_i16_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpminuw %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %xmm1, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm1, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpsubw %xmm1, %xmm2, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpminuw %xmm1, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm2, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm2, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1 ; AVX512VL-FALLBACK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; AVX512VL-FALLBACK-NEXT: retq ; @@ -2784,14 +2786,14 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw ; ; AVX512VL-FALLBACK-LABEL: vec128_i8_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %xmm1, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %xmm1, %xmm2, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm2, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1 ; AVX512VL-FALLBACK-NEXT: vpaddb %xmm0, %xmm1, %xmm0 ; AVX512VL-FALLBACK-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll index e880a1acc9e8..cc08396ae8c7 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll @@ -1445,14 +1445,14 @@ define <16 x i16> @vec256_i16_unsigned_reg_reg(<16 x i16> %a1, <16 x i16> %a2) n ; ; AVX512VL-FALLBACK-LABEL: vec256_i16_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpxor %ymm1, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm2, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm2, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpxor %ymm2, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpaddw %ymm0, %ymm1, %ymm0 ; AVX512VL-FALLBACK-NEXT: retq ; @@ -2210,14 +2210,14 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw ; ; AVX512VL-FALLBACK-LABEL: vec256_i8_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm2, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm2, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512VL-FALLBACK-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll index 366dad1612b4..2fdf6ef224ca 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll @@ -684,21 +684,22 @@ define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwin ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4 ; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5 ; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4 -; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5 -; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 -; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5 ; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 ; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2 -; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 -; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2 +; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5 +; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 +; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1 +; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5 -; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6 -; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2 -; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1 +; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5 +; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 +; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7 +; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2 +; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1 +; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512F-NEXT: vpternlogq $226, %zmm5, %zmm4, %zmm1 ; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -714,21 +715,22 @@ define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwin ; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4 ; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm5 -; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpminsb %ymm2, %ymm3, %ymm5 ; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm5 +; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm5, %zmm5 +; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm7, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512VL-FALLBACK-NEXT: vpternlogq $226, %zmm5, %zmm4, %zmm1 ; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -770,19 +772,20 @@ define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounw ; AVX512F-NEXT: vpminub %ymm1, %ymm0, %ymm6 ; AVX512F-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7 ; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5 -; AVX512F-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 -; AVX512F-NEXT: vpsubb %ymm6, %ymm1, %ymm1 ; AVX512F-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 ; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2 -; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 -; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2 +; AVX512F-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 +; AVX512F-NEXT: vpsubb %ymm6, %ymm1, %ymm1 ; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1 +; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4 -; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6 -; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2 -; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1 +; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512F-NEXT: vpandq %zmm6, %zmm4, %zmm4 +; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 +; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7 +; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2 +; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1 +; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512F-NEXT: vpternlogq $184, %zmm4, %zmm5, %zmm1 ; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -800,19 +803,20 @@ define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounw ; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm6 ; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm6, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpsubb %ymm4, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm6, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm4, %zmm4 +; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm7, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512VL-FALLBACK-NEXT: vpternlogq $184, %zmm4, %zmm5, %zmm1 ; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 diff --git a/llvm/test/CodeGen/X86/pr38539.ll b/llvm/test/CodeGen/X86/pr38539.ll index ace78b38d53e..04aff9b7d2e5 100644 --- a/llvm/test/CodeGen/X86/pr38539.ll +++ b/llvm/test/CodeGen/X86/pr38539.ll @@ -22,7 +22,7 @@ define void @f() nounwind { ; X86-NEXT: pushl %edi ; X86-NEXT: pushl %esi ; X86-NEXT: andl $-16, %esp -; X86-NEXT: subl $160, %esp +; X86-NEXT: subl $176, %esp ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi @@ -47,54 +47,55 @@ define void @f() nounwind { ; X86-NEXT: testl %edi, %edi ; X86-NEXT: jne .LBB0_1 ; X86-NEXT: # %bb.2: # %BB_udiv-special-cases -; X86-NEXT: bsrl %esi, %eax -; X86-NEXT: xorl $31, %eax -; X86-NEXT: addl $32, %eax +; X86-NEXT: bsrl %esi, %ecx +; X86-NEXT: xorl $31, %ecx +; X86-NEXT: addl $32, %ecx ; X86-NEXT: jmp .LBB0_3 ; X86-NEXT: .LBB0_1: -; X86-NEXT: bsrl %edi, %eax -; X86-NEXT: xorl $31, %eax +; X86-NEXT: bsrl %edi, %ecx +; X86-NEXT: xorl $31, %ecx ; X86-NEXT: .LBB0_3: # %BB_udiv-special-cases -; X86-NEXT: xorl %ecx, %ecx +; X86-NEXT: xorl %eax, %eax ; X86-NEXT: testl %edx, %edx -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: jne .LBB0_4 ; X86-NEXT: # %bb.5: # %BB_udiv-special-cases -; X86-NEXT: addl $64, %eax +; X86-NEXT: addl $64, %ecx ; X86-NEXT: jmp .LBB0_6 ; X86-NEXT: .LBB0_4: -; X86-NEXT: bsrl %edx, %eax -; X86-NEXT: xorl $31, %eax -; X86-NEXT: addl $32, %eax +; X86-NEXT: bsrl %edx, %ecx +; X86-NEXT: xorl $31, %ecx +; X86-NEXT: addl $32, %ecx ; X86-NEXT: .LBB0_6: # %BB_udiv-special-cases -; X86-NEXT: subl $62, %eax +; X86-NEXT: subl $62, %ecx ; X86-NEXT: movl $0, %ebx ; X86-NEXT: sbbl %ebx, %ebx -; X86-NEXT: sbbl %ecx, %ecx -; X86-NEXT: addl $-66, %eax +; X86-NEXT: sbbl %eax, %eax +; X86-NEXT: addl $-66, %ecx ; X86-NEXT: adcl $-1, %ebx -; X86-NEXT: adcl $3, %ecx -; X86-NEXT: movl %ecx, %esi -; X86-NEXT: movb $1, %cl -; X86-NEXT: testb %cl, %cl +; X86-NEXT: adcl $3, %eax +; X86-NEXT: movl %eax, %edi +; X86-NEXT: movb $1, %al +; X86-NEXT: testb %al, %al ; X86-NEXT: jne .LBB0_11 ; X86-NEXT: # %bb.7: # %BB_udiv-special-cases -; X86-NEXT: andl $3, %esi -; X86-NEXT: movl %eax, %ecx -; X86-NEXT: xorl $65, %ecx -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %ecx -; X86-NEXT: orl %ebx, %ecx +; X86-NEXT: andl $3, %edi +; X86-NEXT: movl %ecx, %eax +; X86-NEXT: xorl $65, %eax +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %edi, %eax +; X86-NEXT: orl %ebx, %eax ; X86-NEXT: je .LBB0_11 ; X86-NEXT: # %bb.8: # %udiv-bb1 -; X86-NEXT: movl %eax, %ecx +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ecx, %eax ; X86-NEXT: addl $1, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: adcl $0, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: adcl $0, %ebx -; X86-NEXT: andl $3, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: adcl $0, %esi +; X86-NEXT: andl $3, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movb $65, %cl ; X86-NEXT: subb %al, %cl ; X86-NEXT: movb %cl, %ch @@ -111,31 +112,29 @@ define void @f() nounwind { ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl 120(%esp,%eax), %edi +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 136(%esp,%eax), %edx ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shll %cl, %edi +; X86-NEXT: shll %cl, %edx ; X86-NEXT: notb %cl -; X86-NEXT: movl 112(%esp,%eax), %esi -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl 116(%esp,%eax), %edx -; X86-NEXT: movl %edx, %eax +; X86-NEXT: movl 128(%esp,%eax), %edi +; X86-NEXT: movl 132(%esp,%eax), %esi +; X86-NEXT: movl %esi, %eax ; X86-NEXT: shrl %eax ; X86-NEXT: shrl %cl, %eax ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %esi, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: shll %cl, %esi +; X86-NEXT: shldl %cl, %edi, %esi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shll %cl, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: je .LBB0_11 ; X86-NEXT: # %bb.9: # %udiv-preheader -; X86-NEXT: orl %eax, %edi -; X86-NEXT: andl $3, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %eax, %edx +; X86-NEXT: andl $3, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -150,20 +149,20 @@ define void @f() nounwind { ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: shrb $3, %al ; X86-NEXT: andb $15, %al -; X86-NEXT: movzbl %al, %eax -; X86-NEXT: movl 64(%esp,%eax), %edi -; X86-NEXT: movl 68(%esp,%eax), %edx -; X86-NEXT: movl %edx, %esi +; X86-NEXT: movzbl %al, %esi +; X86-NEXT: movl 80(%esp,%esi), %edx +; X86-NEXT: movl 84(%esp,%esi), %eax +; X86-NEXT: movl %eax, %edi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrl %cl, %esi +; X86-NEXT: shrl %cl, %edi ; X86-NEXT: notb %cl -; X86-NEXT: movl 72(%esp,%eax), %ebx -; X86-NEXT: addl %ebx, %ebx -; X86-NEXT: shll %cl, %ebx -; X86-NEXT: orl %esi, %ebx +; X86-NEXT: movl 88(%esp,%esi), %esi +; X86-NEXT: addl %esi, %esi +; X86-NEXT: shll %cl, %esi +; X86-NEXT: orl %edi, %esi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrdl %cl, %edx, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shrdl %cl, %eax, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: addl $-1, %eax @@ -180,62 +179,63 @@ define void @f() nounwind { ; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .LBB0_10: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 -; X86-NEXT: movl %ebx, %edi -; X86-NEXT: shldl $1, %ebx, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: shldl $1, %ebx, %edi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: movl %esi, %edx -; X86-NEXT: andl $2, %edx -; X86-NEXT: shrl %edx -; X86-NEXT: leal (%edx,%ebx,2), %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $1, %esi, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: shldl $1, %edx, %esi -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl %ebx, %eax +; X86-NEXT: andl $2, %eax +; X86-NEXT: shrl %eax +; X86-NEXT: leal (%eax,%edx,2), %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: shldl $1, %edi, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: orl %esi, %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: shldl $1, %eax, %edx -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $1, %eax, %edi +; X86-NEXT: orl %esi, %edi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: addl %eax, %eax ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: andl $3, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: cmpl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: sbbl %edi, %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: sbbl %ecx, %esi -; X86-NEXT: shll $30, %esi -; X86-NEXT: movl %esi, %edx -; X86-NEXT: sarl $30, %edx -; X86-NEXT: sarl $31, %esi -; X86-NEXT: shrdl $1, %esi, %edx -; X86-NEXT: movl %edx, %eax -; X86-NEXT: andl $1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload -; X86-NEXT: movl %esi, %eax -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload -; X86-NEXT: subl %edx, %ebx +; X86-NEXT: andl $3, %ebx ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %esi, %edi -; X86-NEXT: movl %edi, %ebx -; X86-NEXT: sbbl %eax, %ecx +; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: sbbl %esi, %eax +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: sbbl %ecx, %ebx +; X86-NEXT: shll $30, %ebx +; X86-NEXT: movl %ebx, %eax +; X86-NEXT: sarl $30, %eax +; X86-NEXT: sarl $31, %ebx +; X86-NEXT: shrdl $1, %ebx, %eax +; X86-NEXT: movl %eax, %edi +; X86-NEXT: andl $1, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload +; X86-NEXT: subl %eax, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %ebx, %esi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: sbbl %edi, %ecx ; X86-NEXT: andl $3, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: addl $-1, %eax -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: adcl $-1, %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: adcl $3, %esi -; X86-NEXT: andl $3, %esi +; X86-NEXT: adcl $-1, %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: adcl $3, %edi +; X86-NEXT: andl $3, %edi ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %eax -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %edx, %eax +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %edi, %eax +; X86-NEXT: orl %ebx, %eax ; X86-NEXT: jne .LBB0_10 ; X86-NEXT: .LBB0_11: # %udiv-end ; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload diff --git a/llvm/test/CodeGen/X86/pr62286.ll b/llvm/test/CodeGen/X86/pr62286.ll index 1b13cee628df..782c84408f25 100644 --- a/llvm/test/CodeGen/X86/pr62286.ll +++ b/llvm/test/CodeGen/X86/pr62286.ll @@ -8,20 +8,21 @@ define i64 @PR62286(i32 %a) { ; SSE-LABEL: PR62286: ; SSE: # %bb.0: ; SSE-NEXT: movd %edi, %xmm0 -; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,1,0] -; SSE-NEXT: paddd %xmm0, %xmm0 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,0] +; SSE-NEXT: paddd %xmm1, %xmm1 ; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] -; SSE-NEXT: pxor %xmm3, %xmm3 -; SSE-NEXT: pcmpgtd %xmm0, %xmm3 -; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] -; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; SSE-NEXT: pcmpgtd %xmm1, %xmm2 ; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; SSE-NEXT: paddq %xmm0, %xmm1 -; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] +; SSE-NEXT: pxor %xmm3, %xmm3 +; SSE-NEXT: pcmpgtd %xmm1, %xmm3 +; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,0] +; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 +; SSE-NEXT: pcmpgtd %xmm0, %xmm2 +; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; SSE-NEXT: paddq %xmm1, %xmm0 -; SSE-NEXT: movq %xmm0, %rax +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; SSE-NEXT: paddq %xmm0, %xmm1 +; SSE-NEXT: movq %xmm1, %rax ; SSE-NEXT: retq ; ; AVX1-LABEL: PR62286: @@ -46,10 +47,10 @@ define i64 @PR62286(i32 %a) { ; AVX2-LABEL: PR62286: ; AVX2: # %bb.0: ; AVX2-NEXT: vmovd %edi, %xmm0 -; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm1 -; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 -; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] +; AVX2-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] +; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0 +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 +; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0 ; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 diff --git a/llvm/test/CodeGen/X86/scheduler-backtracking.ll b/llvm/test/CodeGen/X86/scheduler-backtracking.ll index 785b97d8c240..a9f3e8b22fb6 100644 --- a/llvm/test/CodeGen/X86/scheduler-backtracking.ll +++ b/llvm/test/CodeGen/X86/scheduler-backtracking.ll @@ -14,6 +14,7 @@ define i256 @test1(i256 %a) nounwind { ; ILP: # %bb.0: ; ILP-NEXT: movq %rdi, %rax ; ILP-NEXT: leal (%rsi,%rsi), %ecx +; ILP-NEXT: addb $3, %cl ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) @@ -22,7 +23,6 @@ define i256 @test1(i256 %a) nounwind { ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) -; ILP-NEXT: addb $3, %cl ; ILP-NEXT: movl %ecx, %edx ; ILP-NEXT: shrb $3, %dl ; ILP-NEXT: andb $7, %cl diff --git a/llvm/test/CodeGen/X86/sdiv_fix_sat.ll b/llvm/test/CodeGen/X86/sdiv_fix_sat.ll index a1cabb433d87..31297a06f809 100644 --- a/llvm/test/CodeGen/X86/sdiv_fix_sat.ll +++ b/llvm/test/CodeGen/X86/sdiv_fix_sat.ll @@ -563,20 +563,18 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: subq $120, %rsp ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: pxor %xmm3, %xmm3 -; X64-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm0[2],xmm3[3],xmm0[3] +; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] +; X64-NEXT: psllq $32, %xmm3 ; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; X64-NEXT: psrad $31, %xmm2 ; X64-NEXT: psrlq $31, %xmm3 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: movq %xmm0, %rbp -; X64-NEXT: movq %rbp, %r14 -; X64-NEXT: sarq $63, %r14 -; X64-NEXT: shldq $31, %rbp, %r14 -; X64-NEXT: movq %rbp, %r15 -; X64-NEXT: shlq $31, %r15 +; X64-NEXT: movq %xmm0, %rbx +; X64-NEXT: movq %rbx, %r13 +; X64-NEXT: sarq $63, %r13 +; X64-NEXT: shldq $31, %rbx, %r13 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; X64-NEXT: pxor %xmm0, %xmm0 ; X64-NEXT: pcmpgtd %xmm1, %xmm0 @@ -584,113 +582,113 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movq %xmm1, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: sarq $63, %rbx -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %rdx, %r15 +; X64-NEXT: sarq $63, %r15 +; X64-NEXT: movq %rbx, %r12 +; X64-NEXT: shlq $31, %r12 +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %r13 +; X64-NEXT: movq %rax, %rbp ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r12 +; X64-NEXT: movq %rdx, %r14 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %r13 -; X64-NEXT: sbbq $0, %r12 -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi +; X64-NEXT: subq $1, %rbp +; X64-NEXT: sbbq $0, %r14 +; X64-NEXT: shrq $63, %rbx +; X64-NEXT: xorl %r15d, %ebx +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al -; X64-NEXT: shrq $63, %rbp -; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload ; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: movl $4294967295, %edx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rdx, %r13 -; X64-NEXT: movq %r12, %rax +; X64-NEXT: cmpq %rdx, %rbp +; X64-NEXT: movq %r14, %rax ; X64-NEXT: sbbq $0, %rax -; X64-NEXT: cmovgeq %rdx, %r13 -; X64-NEXT: cmovgeq %rcx, %r12 +; X64-NEXT: cmovgeq %rcx, %r14 +; X64-NEXT: cmovgeq %rdx, %rbp ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %r13, %rcx +; X64-NEXT: cmpq %rbp, %rcx ; X64-NEXT: movq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r12, %rax -; X64-NEXT: cmovgeq %rcx, %r13 -; X64-NEXT: movq %r13, %xmm0 +; X64-NEXT: sbbq %r14, %rax +; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: movq %rbp, %xmm0 ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] -; X64-NEXT: movq %xmm0, %rbp -; X64-NEXT: movq %rbp, %r14 -; X64-NEXT: sarq $63, %r14 -; X64-NEXT: shldq $31, %rbp, %r14 -; X64-NEXT: movq %rbp, %r15 -; X64-NEXT: shlq $31, %r15 +; X64-NEXT: movq %xmm0, %rbx +; X64-NEXT: movq %rbx, %r13 +; X64-NEXT: sarq $63, %r13 +; X64-NEXT: shldq $31, %rbx, %r13 ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: sarq $63, %rbx -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %rdx, %r15 +; X64-NEXT: sarq $63, %r15 +; X64-NEXT: movq %rbx, %r12 +; X64-NEXT: shlq $31, %r12 +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %r13 +; X64-NEXT: movq %rax, %rbp ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r12 +; X64-NEXT: movq %rdx, %r14 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %r13 -; X64-NEXT: sbbq $0, %r12 -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi +; X64-NEXT: subq $1, %rbp +; X64-NEXT: sbbq $0, %r14 +; X64-NEXT: shrq $63, %rbx +; X64-NEXT: xorl %r15d, %ebx +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al -; X64-NEXT: shrq $63, %rbp -; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %r13 -; X64-NEXT: movq %r12, %rax +; X64-NEXT: cmpq %rcx, %rbp +; X64-NEXT: movq %r14, %rax ; X64-NEXT: sbbq $0, %rax -; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r12 +; X64-NEXT: cmovgeq %rax, %r14 +; X64-NEXT: cmovgeq %rcx, %rbp ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %r13, %rcx +; X64-NEXT: cmpq %rbp, %rcx ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r12, %rax -; X64-NEXT: cmovgeq %rcx, %r13 -; X64-NEXT: movq %r13, %xmm0 +; X64-NEXT: sbbq %r14, %rax +; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: movq %rbp, %xmm0 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; X64-NEXT: psrlq $1, %xmm1 ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: pxor %xmm0, %xmm0 -; X64-NEXT: punpckldq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload -; X64-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] +; X64-NEXT: pshufd $212, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload +; X64-NEXT: # xmm0 = mem[0,1,1,3] +; X64-NEXT: psllq $32, %xmm0 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3] ; X64-NEXT: psrad $31, %xmm1 ; X64-NEXT: psrlq $31, %xmm0 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: movq %xmm0, %rbp -; X64-NEXT: movq %rbp, %r14 -; X64-NEXT: sarq $63, %r14 -; X64-NEXT: shldq $31, %rbp, %r14 -; X64-NEXT: movq %rbp, %r15 -; X64-NEXT: shlq $31, %r15 +; X64-NEXT: movq %xmm0, %rbx +; X64-NEXT: movq %rbx, %r13 +; X64-NEXT: sarq $63, %r13 +; X64-NEXT: shldq $31, %rbx, %r13 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; X64-NEXT: pxor %xmm1, %xmm1 ; X64-NEXT: pcmpgtd %xmm0, %xmm1 @@ -698,92 +696,94 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: sarq $63, %rbx -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %rdx, %r15 +; X64-NEXT: sarq $63, %r15 +; X64-NEXT: movq %rbx, %r12 +; X64-NEXT: shlq $31, %r12 +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %r13 +; X64-NEXT: movq %rax, %rbp ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r12 +; X64-NEXT: movq %rdx, %r14 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %r13 -; X64-NEXT: sbbq $0, %r12 -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi +; X64-NEXT: subq $1, %rbp +; X64-NEXT: sbbq $0, %r14 +; X64-NEXT: shrq $63, %rbx +; X64-NEXT: xorl %r15d, %ebx +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al -; X64-NEXT: shrq $63, %rbp -; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %r13 -; X64-NEXT: movq %r12, %rax +; X64-NEXT: cmpq %rcx, %rbp +; X64-NEXT: movq %r14, %rax ; X64-NEXT: sbbq $0, %rax -; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r12 +; X64-NEXT: cmovgeq %rax, %r14 +; X64-NEXT: cmovgeq %rcx, %rbp ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %r13, %rcx +; X64-NEXT: cmpq %rbp, %rcx ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r12, %rax -; X64-NEXT: cmovgeq %rcx, %r13 -; X64-NEXT: movq %r13, %xmm0 +; X64-NEXT: sbbq %r14, %rax +; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: movq %rbp, %xmm0 ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] -; X64-NEXT: movq %xmm0, %rbp -; X64-NEXT: movq %rbp, %r14 -; X64-NEXT: sarq $63, %r14 -; X64-NEXT: shldq $31, %rbp, %r14 -; X64-NEXT: movq %rbp, %r15 -; X64-NEXT: shlq $31, %r15 +; X64-NEXT: movq %xmm0, %rbx +; X64-NEXT: movq %rbx, %r13 +; X64-NEXT: sarq $63, %r13 +; X64-NEXT: shldq $31, %rbx, %r13 ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %rbx -; X64-NEXT: sarq $63, %rbx -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %rdx, %r15 +; X64-NEXT: sarq $63, %r15 +; X64-NEXT: movq %rbx, %r12 +; X64-NEXT: shlq $31, %r12 +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %r13 +; X64-NEXT: movq %rax, %rbp ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r12 +; X64-NEXT: movq %rdx, %r14 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %r13 -; X64-NEXT: sbbq $0, %r12 -; X64-NEXT: movq %r15, %rdi -; X64-NEXT: movq %r14, %rsi +; X64-NEXT: subq $1, %rbp +; X64-NEXT: sbbq $0, %r14 +; X64-NEXT: shrq $63, %rbx +; X64-NEXT: xorl %r15d, %ebx +; X64-NEXT: movq %r12, %rdi +; X64-NEXT: movq %r13, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %rbx, %rcx +; X64-NEXT: movq %r15, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al -; X64-NEXT: shrq $63, %rbp -; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %r13 -; X64-NEXT: movq %r12, %rax +; X64-NEXT: cmpq %rcx, %rbp +; X64-NEXT: movq %r14, %rax ; X64-NEXT: sbbq $0, %rax -; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r12 +; X64-NEXT: cmovgeq %rax, %r14 +; X64-NEXT: cmovgeq %rcx, %rbp ; X64-NEXT: movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %r13, %rax -; X64-NEXT: sbbq %r12, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill -; X64-NEXT: cmovgeq %rax, %r13 -; X64-NEXT: movq %r13, %xmm1 +; X64-NEXT: cmpq %rbp, %rax +; X64-NEXT: sbbq %r14, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill +; X64-NEXT: cmovgeq %rax, %rbp +; X64-NEXT: movq %rbp, %xmm1 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X64-NEXT: psrlq $1, %xmm0 diff --git a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll index a80d8d8cd01b..97c3c2040b29 100644 --- a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll +++ b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll @@ -46,6 +46,7 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: movq 24(%rsi), %rcx ; CHECK-NEXT: movq 32(%rsi), %rdx ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0] +; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [1,1] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2,2] ; CHECK-NEXT: .p2align 4, 0x90 @@ -53,45 +54,39 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-NEXT: xorpd %xmm3, %xmm3 -; CHECK-NEXT: movq $-1024, %rsi # imm = 0xFC00 +; CHECK-NEXT: movq $-1024, %rdi # imm = 0xFC00 ; CHECK-NEXT: movdqa %xmm0, %xmm4 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_2: # %vector.body ; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-NEXT: movdqu 1024(%rdx,%rsi), %xmm5 -; CHECK-NEXT: movdqu 1040(%rdx,%rsi), %xmm6 -; CHECK-NEXT: movq %xmm5, %rdi -; CHECK-NEXT: movq %xmm6, %r8 -; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3] -; CHECK-NEXT: movq %xmm5, %r9 -; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[2,3,2,3] -; CHECK-NEXT: movq %xmm5, %r10 -; CHECK-NEXT: negq %r8 +; CHECK-NEXT: cmpq 1024(%rdx,%rdi), %rsi ; CHECK-NEXT: movq %rcx, %r8 -; CHECK-NEXT: sbbq %r10, %r8 +; CHECK-NEXT: sbbq 1032(%rdx,%rdi), %r8 ; CHECK-NEXT: setge %r8b ; CHECK-NEXT: movzbl %r8b, %r8d +; CHECK-NEXT: andl $1, %r8d ; CHECK-NEXT: negq %r8 ; CHECK-NEXT: movq %r8, %xmm5 -; CHECK-NEXT: negq %rdi -; CHECK-NEXT: movq %rcx, %rdi -; CHECK-NEXT: sbbq %r9, %rdi -; CHECK-NEXT: setge %dil -; CHECK-NEXT: movzbl %dil, %edi -; CHECK-NEXT: negq %rdi -; CHECK-NEXT: movq %rdi, %xmm6 -; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm5[0] -; CHECK-NEXT: movdqa %xmm1, %xmm5 -; CHECK-NEXT: psllq %xmm4, %xmm5 +; CHECK-NEXT: cmpq 1040(%rdx,%rdi), %rsi +; CHECK-NEXT: movq %rcx, %r8 +; CHECK-NEXT: sbbq 1048(%rdx,%rdi), %r8 +; CHECK-NEXT: setge %r8b +; CHECK-NEXT: movzbl %r8b, %r8d +; CHECK-NEXT: andl $1, %r8d +; CHECK-NEXT: negq %r8 +; CHECK-NEXT: movq %r8, %xmm6 +; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0] +; CHECK-NEXT: movdqa %xmm1, %xmm6 +; CHECK-NEXT: psllq %xmm4, %xmm6 ; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[2,3,2,3] ; CHECK-NEXT: movdqa %xmm1, %xmm8 ; CHECK-NEXT: psllq %xmm7, %xmm8 -; CHECK-NEXT: movsd {{.*#+}} xmm8 = xmm5[0],xmm8[1] -; CHECK-NEXT: andpd %xmm6, %xmm8 +; CHECK-NEXT: movsd {{.*#+}} xmm8 = xmm6[0],xmm8[1] +; CHECK-NEXT: andpd %xmm5, %xmm8 ; CHECK-NEXT: orpd %xmm8, %xmm3 ; CHECK-NEXT: paddq %xmm2, %xmm4 -; CHECK-NEXT: addq $32, %rsi +; CHECK-NEXT: addq $32, %rdi ; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: # %bb.3: # %middle.block ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 @@ -106,6 +101,7 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-AVX2-NEXT: movq 24(%rsi), %rcx ; CHECK-AVX2-NEXT: movq 32(%rsi), %rdx ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,1] +; CHECK-AVX2-NEXT: xorl %esi, %esi ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm1 = [1,1] ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm2 = [2,2] ; CHECK-AVX2-NEXT: .p2align 4, 0x90 @@ -113,40 +109,34 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-AVX2-NEXT: # =>This Loop Header: Depth=1 ; CHECK-AVX2-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; CHECK-AVX2-NEXT: movq $-1024, %rsi # imm = 0xFC00 +; CHECK-AVX2-NEXT: movq $-1024, %rdi # imm = 0xFC00 ; CHECK-AVX2-NEXT: vmovdqa %xmm0, %xmm4 ; CHECK-AVX2-NEXT: .p2align 4, 0x90 ; CHECK-AVX2-NEXT: .LBB0_2: # %vector.body ; CHECK-AVX2-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-AVX2-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-AVX2-NEXT: vmovdqu 1024(%rdx,%rsi), %xmm5 -; CHECK-AVX2-NEXT: vmovdqu 1040(%rdx,%rsi), %xmm6 -; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm5[0],xmm6[0] -; CHECK-AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm5 = xmm5[1],xmm6[1] -; CHECK-AVX2-NEXT: vmovq %xmm5, %rdi -; CHECK-AVX2-NEXT: vpextrq $1, %xmm5, %r8 -; CHECK-AVX2-NEXT: vmovq %xmm7, %r9 -; CHECK-AVX2-NEXT: vpextrq $1, %xmm7, %r10 -; CHECK-AVX2-NEXT: negq %r10 -; CHECK-AVX2-NEXT: movq %rcx, %r10 -; CHECK-AVX2-NEXT: sbbq %r8, %r10 +; CHECK-AVX2-NEXT: cmpq 1024(%rdx,%rdi), %rsi +; CHECK-AVX2-NEXT: movq %rcx, %r8 +; CHECK-AVX2-NEXT: sbbq 1032(%rdx,%rdi), %r8 ; CHECK-AVX2-NEXT: setge %r8b ; CHECK-AVX2-NEXT: movzbl %r8b, %r8d +; CHECK-AVX2-NEXT: andl $1, %r8d ; CHECK-AVX2-NEXT: negq %r8 ; CHECK-AVX2-NEXT: vmovq %r8, %xmm5 -; CHECK-AVX2-NEXT: negq %r9 +; CHECK-AVX2-NEXT: cmpq 1040(%rdx,%rdi), %rsi ; CHECK-AVX2-NEXT: movq %rcx, %r8 -; CHECK-AVX2-NEXT: sbbq %rdi, %r8 -; CHECK-AVX2-NEXT: setge %dil -; CHECK-AVX2-NEXT: movzbl %dil, %edi -; CHECK-AVX2-NEXT: negq %rdi -; CHECK-AVX2-NEXT: vmovq %rdi, %xmm6 -; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0] +; CHECK-AVX2-NEXT: sbbq 1048(%rdx,%rdi), %r8 +; CHECK-AVX2-NEXT: setge %r8b +; CHECK-AVX2-NEXT: movzbl %r8b, %r8d +; CHECK-AVX2-NEXT: andl $1, %r8d +; CHECK-AVX2-NEXT: negq %r8 +; CHECK-AVX2-NEXT: vmovq %r8, %xmm6 +; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0] ; CHECK-AVX2-NEXT: vpsllvq %xmm4, %xmm1, %xmm6 ; CHECK-AVX2-NEXT: vpand %xmm6, %xmm5, %xmm5 ; CHECK-AVX2-NEXT: vpor %xmm3, %xmm5, %xmm3 ; CHECK-AVX2-NEXT: vpaddq %xmm2, %xmm4, %xmm4 -; CHECK-AVX2-NEXT: addq $32, %rsi +; CHECK-AVX2-NEXT: addq $32, %rdi ; CHECK-AVX2-NEXT: jne .LBB0_2 ; CHECK-AVX2-NEXT: # %bb.3: # %middle.block ; CHECK-AVX2-NEXT: # in Loop: Header=BB0_1 Depth=1 diff --git a/llvm/test/CodeGen/X86/vec_saddo.ll b/llvm/test/CodeGen/X86/vec_saddo.ll index 460c5fe11f82..cee30f5fe5da 100644 --- a/llvm/test/CodeGen/X86/vec_saddo.ll +++ b/llvm/test/CodeGen/X86/vec_saddo.ll @@ -1045,12 +1045,16 @@ define <4 x i32> @saddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: saddo_v4i1: ; AVX512: # %bb.0: -; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 -; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 -; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 +; AVX512-NEXT: vpslld $31, %xmm1, %xmm0 +; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 +; AVX512-NEXT: kxorw %k1, %k0, %k2 +; AVX512-NEXT: kandw %k1, %k0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} +; AVX512-NEXT: kshiftlw $12, %k2, %k0 +; AVX512-NEXT: kshiftrw $12, %k0, %k0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_ssubo.ll b/llvm/test/CodeGen/X86/vec_ssubo.ll index d06993da6365..64ed08104885 100644 --- a/llvm/test/CodeGen/X86/vec_ssubo.ll +++ b/llvm/test/CodeGen/X86/vec_ssubo.ll @@ -1062,12 +1062,16 @@ define <4 x i32> @ssubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: ssubo_v4i1: ; AVX512: # %bb.0: -; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 -; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 -; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 -; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 +; AVX512-NEXT: vpslld $31, %xmm1, %xmm1 +; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k1 +; AVX512-NEXT: kxorw %k1, %k0, %k0 +; AVX512-NEXT: vptestnmd %xmm0, %xmm0, %k1 {%k1} +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} +; AVX512-NEXT: kshiftlw $12, %k0, %k0 +; AVX512-NEXT: kshiftrw $12, %k0, %k0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_uaddo.ll b/llvm/test/CodeGen/X86/vec_uaddo.ll index bac118095331..950e943bd902 100644 --- a/llvm/test/CodeGen/X86/vec_uaddo.ll +++ b/llvm/test/CodeGen/X86/vec_uaddo.ll @@ -1098,12 +1098,16 @@ define <4 x i32> @uaddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: uaddo_v4i1: ; AVX512: # %bb.0: -; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 -; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 -; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 -; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 +; AVX512-NEXT: vpslld $31, %xmm1, %xmm0 +; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 +; AVX512-NEXT: kxorw %k1, %k0, %k2 +; AVX512-NEXT: kandw %k1, %k0, %k1 +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} +; AVX512-NEXT: kshiftlw $12, %k2, %k0 +; AVX512-NEXT: kshiftrw $12, %k0, %k0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_usubo.ll b/llvm/test/CodeGen/X86/vec_usubo.ll index ab75ada72f25..7de972770d8d 100644 --- a/llvm/test/CodeGen/X86/vec_usubo.ll +++ b/llvm/test/CodeGen/X86/vec_usubo.ll @@ -1145,12 +1145,16 @@ define <4 x i32> @usubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: usubo_v4i1: ; AVX512: # %bb.0: -; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 -; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 -; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 -; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 +; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 +; AVX512-NEXT: vpslld $31, %xmm1, %xmm1 +; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k1 +; AVX512-NEXT: kxorw %k1, %k0, %k0 +; AVX512-NEXT: vptestnmd %xmm0, %xmm0, %k1 {%k1} +; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 +; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} +; AVX512-NEXT: kshiftlw $12, %k0, %k0 +; AVX512-NEXT: kshiftrw $12, %k0, %k0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll index 27aaad6353ed..78797b9acc2e 100644 --- a/llvm/test/CodeGen/X86/vector-bo-select.ll +++ b/llvm/test/CodeGen/X86/vector-bo-select.ll @@ -3137,11 +3137,11 @@ define <8 x i64> @mul_v8i64_cast_cond(i8 noundef zeroext %pb, <8 x i64> noundef ; AVX512-LABEL: mul_v8i64_cast_cond: ; AVX512: # %bb.0: ; AVX512-NEXT: kmovw %edi, %k1 -; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm2 -; AVX512-NEXT: vpmuludq %zmm1, %zmm2, %zmm2 -; AVX512-NEXT: vpsrlq $32, %zmm1, %zmm3 -; AVX512-NEXT: vpmuludq %zmm3, %zmm0, %zmm3 -; AVX512-NEXT: vpaddq %zmm2, %zmm3, %zmm2 +; AVX512-NEXT: vpsrlq $32, %zmm1, %zmm2 +; AVX512-NEXT: vpmuludq %zmm2, %zmm0, %zmm2 +; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm3 +; AVX512-NEXT: vpmuludq %zmm1, %zmm3, %zmm3 +; AVX512-NEXT: vpaddq %zmm3, %zmm2, %zmm2 ; AVX512-NEXT: vpsllq $32, %zmm2, %zmm2 ; AVX512-NEXT: vpmuludq %zmm1, %zmm0, %zmm1 ; AVX512-NEXT: vpaddq %zmm2, %zmm1, %zmm0 {%k1} diff --git a/llvm/test/CodeGen/X86/vector-fshr-128.ll b/llvm/test/CodeGen/X86/vector-fshr-128.ll index 3aaa9268a8d8..b839452725a9 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-128.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-128.ll @@ -58,12 +58,12 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; SSE41-NEXT: psrlq %xmm4, %xmm1 ; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pandn %xmm3, %xmm2 +; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3] ; SSE41-NEXT: paddq %xmm0, %xmm0 -; SSE41-NEXT: movdqa %xmm0, %xmm1 -; SSE41-NEXT: psllq %xmm2, %xmm1 -; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] +; SSE41-NEXT: movdqa %xmm0, %xmm3 +; SSE41-NEXT: psllq %xmm1, %xmm3 ; SSE41-NEXT: psllq %xmm2, %xmm0 -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7] ; SSE41-NEXT: por %xmm5, %xmm0 ; SSE41-NEXT: retq ; @@ -76,11 +76,11 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; AVX1-NEXT: vpsrlq %xmm4, %xmm1, %xmm1 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0,1,2,3],xmm1[4,5,6,7] ; AVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,3,2,3] ; AVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 -; AVX1-NEXT: vpsllq %xmm2, %xmm0, %xmm3 -; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] +; AVX1-NEXT: vpsllq %xmm3, %xmm0, %xmm3 ; AVX1-NEXT: vpsllq %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7] ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: retq ; @@ -158,13 +158,13 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; XOPAVX1-LABEL: var_funnnel_v2i64: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpmovsxbq {{.*#+}} xmm3 = [63,63] -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 +; XOPAVX1-NEXT: vpsubq %xmm4, %xmm5, %xmm4 +; XOPAVX1-NEXT: vpshlq %xmm4, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlq %xmm4, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 -; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; XOPAVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2 -; XOPAVX1-NEXT: vpshlq %xmm2, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpshlq %xmm2, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; @@ -366,13 +366,13 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %amt) ; XOPAVX1-LABEL: var_funnnel_v4i32: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [31,31,31,31] -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 +; XOPAVX1-NEXT: vpsubd %xmm4, %xmm5, %xmm4 +; XOPAVX1-NEXT: vpshld %xmm4, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshld %xmm4, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 -; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; XOPAVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2 -; XOPAVX1-NEXT: vpshld %xmm2, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpshld %xmm2, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; @@ -646,26 +646,26 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt) ; XOPAVX1-LABEL: var_funnnel_v8i16: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15] -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 +; XOPAVX1-NEXT: vpsubw %xmm4, %xmm5, %xmm4 +; XOPAVX1-NEXT: vpshlw %xmm4, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpaddw %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlw %xmm4, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 -; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; XOPAVX1-NEXT: vpsubw %xmm2, %xmm3, %xmm2 -; XOPAVX1-NEXT: vpshlw %xmm2, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpshlw %xmm2, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_funnnel_v8i16: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastw {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15] -; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm4 +; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm4 +; XOPAVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5 +; XOPAVX2-NEXT: vpsubw %xmm4, %xmm5, %xmm4 +; XOPAVX2-NEXT: vpshlw %xmm4, %xmm1, %xmm1 +; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm2 ; XOPAVX2-NEXT: vpaddw %xmm0, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpshlw %xmm4, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm2 -; XOPAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; XOPAVX2-NEXT: vpsubw %xmm2, %xmm3, %xmm2 -; XOPAVX2-NEXT: vpshlw %xmm2, %xmm1, %xmm1 +; XOPAVX2-NEXT: vpshlw %xmm2, %xmm0, %xmm0 ; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: retq ; @@ -995,26 +995,26 @@ define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) ; XOPAVX1-LABEL: var_funnnel_v16i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 +; XOPAVX1-NEXT: vpsubb %xmm4, %xmm5, %xmm4 +; XOPAVX1-NEXT: vpshlb %xmm4, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlb %xmm4, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 -; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; XOPAVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2 -; XOPAVX1-NEXT: vpshlb %xmm2, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpshlb %xmm2, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_funnnel_v16i8: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastb {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] -; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm4 +; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm4 +; XOPAVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5 +; XOPAVX2-NEXT: vpsubb %xmm4, %xmm5, %xmm4 +; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1 +; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm2 ; XOPAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpshlb %xmm4, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm2 -; XOPAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; XOPAVX2-NEXT: vpsubb %xmm2, %xmm3, %xmm2 -; XOPAVX2-NEXT: vpshlb %xmm2, %xmm1, %xmm1 +; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0 ; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll index fc65f759f5fb..7b6b0ea83c7e 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-256.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll @@ -486,22 +486,22 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> % ; XOPAVX2-LABEL: var_funnnel_v16i16: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastw {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; XOPAVX2-NEXT: vpandn %ymm3, %ymm2, %ymm4 +; XOPAVX2-NEXT: vpand %ymm3, %ymm2, %ymm4 ; XOPAVX2-NEXT: vextracti128 $1, %ymm4, %xmm5 -; XOPAVX2-NEXT: vpaddw %ymm0, %ymm0, %ymm0 -; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm6 -; XOPAVX2-NEXT: vpshlw %xmm5, %xmm6, %xmm5 -; XOPAVX2-NEXT: vpshlw %xmm4, %xmm0, %xmm0 -; XOPAVX2-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm0 -; XOPAVX2-NEXT: vpand %ymm3, %ymm2, %ymm2 +; XOPAVX2-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; XOPAVX2-NEXT: vpsubw %xmm5, %xmm6, %xmm5 +; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm7 +; XOPAVX2-NEXT: vpshlw %xmm5, %xmm7, %xmm5 +; XOPAVX2-NEXT: vpsubw %xmm4, %xmm6, %xmm4 +; XOPAVX2-NEXT: vpshlw %xmm4, %xmm1, %xmm1 +; XOPAVX2-NEXT: vinserti128 $1, %xmm5, %ymm1, %ymm1 +; XOPAVX2-NEXT: vpandn %ymm3, %ymm2, %ymm2 ; XOPAVX2-NEXT: vextracti128 $1, %ymm2, %xmm3 -; XOPAVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4 -; XOPAVX2-NEXT: vpsubw %xmm3, %xmm4, %xmm3 -; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm5 -; XOPAVX2-NEXT: vpshlw %xmm3, %xmm5, %xmm3 -; XOPAVX2-NEXT: vpsubw %xmm2, %xmm4, %xmm2 -; XOPAVX2-NEXT: vpshlw %xmm2, %xmm1, %xmm1 -; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1 +; XOPAVX2-NEXT: vpaddw %ymm0, %ymm0, %ymm0 +; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm4 +; XOPAVX2-NEXT: vpshlw %xmm3, %xmm4, %xmm3 +; XOPAVX2-NEXT: vpshlw %xmm2, %xmm0, %xmm0 +; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0 ; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq %res = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %amt) diff --git a/llvm/test/CodeGen/X86/vector-fshr-sub128.ll b/llvm/test/CodeGen/X86/vector-fshr-sub128.ll index a6067a960fc0..0426c48aecfc 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-sub128.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-sub128.ll @@ -185,13 +185,13 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %amt) ; XOPAVX1-LABEL: var_funnnel_v2i32: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [31,31,31,31] -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 +; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 +; XOPAVX1-NEXT: vpsubd %xmm4, %xmm5, %xmm4 +; XOPAVX1-NEXT: vpshld %xmm4, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 ; XOPAVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshld %xmm4, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 -; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; XOPAVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2 -; XOPAVX1-NEXT: vpshld %xmm2, %xmm1, %xmm1 +; XOPAVX1-NEXT: vpshld %xmm2, %xmm0, %xmm0 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll index 75baba5f35f7..c54da38ef10c 100644 --- a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll +++ b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll @@ -927,9 +927,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; SSE2-LABEL: constant_shift_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: paddq %xmm0, %xmm1 -; SSE2-NEXT: psllq $7, %xmm0 -; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; SSE2-NEXT: psllq $7, %xmm1 +; SSE2-NEXT: paddq %xmm0, %xmm0 +; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; SSE2-NEXT: retq ; ; SSE41-LABEL: constant_shift_v2i64: @@ -975,9 +975,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; X86-SSE-LABEL: constant_shift_v2i64: ; X86-SSE: # %bb.0: ; X86-SSE-NEXT: movdqa %xmm0, %xmm1 -; X86-SSE-NEXT: paddq %xmm0, %xmm1 -; X86-SSE-NEXT: psllq $7, %xmm0 -; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] +; X86-SSE-NEXT: psllq $7, %xmm1 +; X86-SSE-NEXT: paddq %xmm0, %xmm0 +; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] ; X86-SSE-NEXT: retl %shift = shl <2 x i64> %a, ret <2 x i64> %shift -- GitLab From bfc0317153dca75137fba00b5c28758d6f720963 Mon Sep 17 00:00:00 2001 From: Maciej Gabka Date: Mon, 29 Apr 2024 10:16:45 +0100 Subject: [PATCH 196/301] Move several vector intrinsics out of experimental namespace (#88748) This patch is moving out following intrinsics: * vector.interleave2/deinterleave2 * vector.reverse * vector.splice from the experimental namespace. All these intrinsics exist in LLVM for more than a year now, and are widely used, so should not be considered as experimental. --- clang/lib/CodeGen/CGExprScalar.cpp | 2 +- llvm/docs/LangRef.rst | 53 +- llvm/docs/ReleaseNotes.rst | 6 +- llvm/include/llvm/CodeGen/BasicTTIImpl.h | 4 +- .../llvm/CodeGen/GlobalISel/IRTranslator.h | 4 +- llvm/include/llvm/CodeGen/TargetLowering.h | 4 +- llvm/include/llvm/IR/Intrinsics.td | 32 +- llvm/include/llvm/IR/PatternMatch.h | 2 +- llvm/lib/Analysis/InstructionSimplify.cpp | 6 +- .../lib/CodeGen/ComplexDeinterleavingPass.cpp | 30 +- llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp | 10 +- llvm/lib/CodeGen/InterleavedAccessPass.cpp | 4 +- .../SelectionDAG/SelectionDAGBuilder.cpp | 8 +- llvm/lib/IR/AutoUpgrade.cpp | 19 +- llvm/lib/IR/IRBuilder.cpp | 6 +- llvm/lib/IR/Instructions.cpp | 2 +- llvm/lib/IR/Verifier.cpp | 2 +- .../Target/AArch64/AArch64ISelLowering.cpp | 4 +- .../AArch64/GISel/AArch64LegalizerInfo.cpp | 2 +- llvm/lib/Target/RISCV/RISCVISelLowering.cpp | 4 +- .../InstCombine/InstCombineCalls.cpp | 2 +- .../InstCombine/InstCombineCompares.cpp | 4 +- .../InstCombine/InstCombineSelect.cpp | 4 +- .../InstCombine/InstructionCombining.cpp | 4 +- .../Transforms/Vectorize/LoopVectorize.cpp | 13 +- .../getIntrinsicInstrCost-vector-reverse.ll | 96 +-- .../test/Analysis/CostModel/AArch64/splice.ll | 172 ++--- .../CostModel/AArch64/sve-intrinsics.ll | 656 +++++++++--------- .../Analysis/CostModel/RISCV/rvv-shuffle.ll | 250 +++---- llvm/test/Analysis/CostModel/RISCV/splice.ll | 392 +++++------ ...or-interleave2-deinterleave2-intrinsics.ll | 46 ++ .../upgrade-vector-reverse-intrinsic.ll | 24 + .../upgrade-vector-splice-intrinsic.ll | 24 + .../irtranslator-vector-deinterleave2.ll | 4 +- .../irtranslator-vector-interleave2.ll | 4 +- ...interleaving-add-mull-scalable-contract.ll | 52 +- ...x-deinterleaving-add-mull-scalable-fast.ll | 52 +- ...complex-deinterleaving-f16-add-scalable.ll | 40 +- .../AArch64/complex-deinterleaving-f16-add.ll | 30 +- ...complex-deinterleaving-f16-mul-scalable.ll | 40 +- ...complex-deinterleaving-f32-add-scalable.ll | 30 +- ...complex-deinterleaving-f32-mul-scalable.ll | 30 +- ...complex-deinterleaving-f64-add-scalable.ll | 30 +- ...complex-deinterleaving-f64-mul-scalable.ll | 30 +- ...complex-deinterleaving-i16-add-scalable.ll | 40 +- ...complex-deinterleaving-i16-mul-scalable.ll | 40 +- ...complex-deinterleaving-i32-add-scalable.ll | 30 +- ...complex-deinterleaving-i32-mul-scalable.ll | 30 +- ...complex-deinterleaving-i64-add-scalable.ll | 30 +- ...complex-deinterleaving-i64-mul-scalable.ll | 36 +- .../complex-deinterleaving-i8-add-scalable.ll | 30 +- ...rleaving-reductions-predicated-scalable.ll | 26 +- ...plex-deinterleaving-reductions-scalable.ll | 20 +- .../complex-deinterleaving-splat-scalable.ll | 16 +- .../AArch64/fixed-vector-deinterleave.ll | 40 +- .../AArch64/fixed-vector-interleave.ll | 40 +- .../named-vector-shuffle-reverse-neon.ll | 52 +- .../named-vector-shuffle-reverse-sve.ll | 84 +-- .../AArch64/named-vector-shuffles-neon.ll | 30 +- .../AArch64/named-vector-shuffles-sve.ll | 164 ++--- .../AArch64/sve-vector-deinterleave.ll | 76 +- .../CodeGen/AArch64/sve-vector-interleave.ll | 76 +- .../AArch64/sve2-intrinsics-while-reversed.ll | 128 ++-- .../rvv/fixed-vectors-deinterleave-load.ll | 46 +- .../rvv/fixed-vectors-interleave-store.ll | 42 +- ...fixed-vectors-shuffle-reverse-bitrotate.ll | 4 +- .../rvv/fixed-vectors-shuffle-reverse.ll | 188 ++--- .../RISCV/rvv/named-vector-shuffle-reverse.ll | 184 ++--- .../RISCV/rvv/vector-deinterleave-fixed.ll | 44 +- .../RISCV/rvv/vector-deinterleave-load.ll | 54 +- .../CodeGen/RISCV/rvv/vector-deinterleave.ll | 76 +- .../RISCV/rvv/vector-interleave-fixed.ll | 40 +- .../RISCV/rvv/vector-interleave-store.ll | 50 +- .../CodeGen/RISCV/rvv/vector-interleave.ll | 80 +-- llvm/test/CodeGen/RISCV/rvv/vector-splice.ll | 412 +++++------ .../X86/named-vector-shuffle-reverse.ll | 38 +- .../Transforms/InstCombine/vector-reverse.ll | 292 ++++---- .../named-vector-shuffle-reverse.ll | 8 +- llvm/test/Transforms/InstSimplify/select.ll | 6 +- .../AArch64/fixed-deinterleave-intrinsics.ll | 96 +-- .../scalable-deinterleave-intrinsics.ll | 68 +- .../AArch64/sve-interleaved-accesses.ll | 2 +- .../AArch64/first-order-recurrence.ll | 6 +- .../AArch64/reduction-recurrence-costs-sve.ll | 12 +- .../AArch64/scalable-strict-fadd.ll | 8 +- .../AArch64/sve-interleaved-accesses.ll | 48 +- .../sve-interleaved-masked-accesses.ll | 16 +- .../AArch64/sve-tail-folding-option.ll | 24 +- .../AArch64/sve-vector-reverse-mask4.ll | 10 +- .../AArch64/sve-vector-reverse.ll | 2 +- .../LoopVectorize/AArch64/sve-widen-phi.ll | 4 +- .../RISCV/riscv-vector-reverse.ll | 2 +- ...-force-tail-with-evl-reverse-load-store.ll | 8 +- .../scalable-first-order-recurrence.ll | 12 +- llvm/test/Verifier/invalid-splice.ll | 14 +- .../mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td | 4 +- .../VectorToLLVM/ConvertVectorToLLVM.cpp | 2 +- .../ArmSME/Transforms/OuterProductFusion.cpp | 3 +- .../VectorToLLVM/vector-to-llvm.mlir | 4 +- .../Dialect/ArmSME/outer-product-fusion.mlir | 32 +- mlir/test/Dialect/LLVMIR/invalid.mlir | 16 +- mlir/test/Dialect/LLVMIR/roundtrip.mlir | 8 +- 102 files changed, 2642 insertions(+), 2544 deletions(-) create mode 100644 llvm/test/Bitcode/upgrade-vector-interleave2-deinterleave2-intrinsics.ll create mode 100644 llvm/test/Bitcode/upgrade-vector-reverse-intrinsic.ll create mode 100644 llvm/test/Bitcode/upgrade-vector-splice-intrinsic.ll diff --git a/clang/lib/CodeGen/CGExprScalar.cpp b/clang/lib/CodeGen/CGExprScalar.cpp index 40a5cd20c3d7..af48e8d2b839 100644 --- a/clang/lib/CodeGen/CGExprScalar.cpp +++ b/clang/lib/CodeGen/CGExprScalar.cpp @@ -2330,7 +2330,7 @@ Value *ScalarExprEmitter::VisitCastExpr(CastExpr *CE) { } // Perform VLAT <-> VLST bitcast through memory. - // TODO: since the llvm.experimental.vector.{insert,extract} intrinsics + // TODO: since the llvm.vector.{insert,extract} intrinsics // require the element types of the vectors to be the same, we // need to keep this around for bitcasts between VLAT <-> VLST where // the element types of the vectors are not the same, until we figure diff --git a/llvm/docs/LangRef.rst b/llvm/docs/LangRef.rst index f169ab941c45..37662f79145d 100644 --- a/llvm/docs/LangRef.rst +++ b/llvm/docs/LangRef.rst @@ -18805,7 +18805,7 @@ runtime, then the result vector is a :ref:`poison value `. The ``idx`` parameter must be a vector index constant type (for most targets this will be an integer pointer type). -'``llvm.experimental.vector.reverse``' Intrinsic +'``llvm.vector.reverse``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: @@ -18814,25 +18814,26 @@ This is an overloaded intrinsic. :: - declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a) - declare @llvm.experimental.vector.reverse.nxv4i32( %a) + declare <2 x i8> @llvm.vector.reverse.v2i8(<2 x i8> %a) + declare @llvm.vector.reverse.nxv4i32( %a) Overview: """"""""" -The '``llvm.experimental.vector.reverse.*``' intrinsics reverse a vector. +The '``llvm.vector.reverse.*``' intrinsics reverse a vector. The intrinsic takes a single vector and returns a vector of matching type but with the original lane order reversed. These intrinsics work for both fixed -and scalable vectors. While this intrinsic is marked as experimental the -recommended way to express reverse operations for fixed-width vectors is still -to use a shufflevector, as that may allow for more optimization opportunities. +and scalable vectors. While this intrinsic supports all vector types +the recommended way to express this operation for fixed-width vectors is +still to use a shufflevector, as that may allow for more optimization +opportunities. Arguments: """""""""" The argument to this intrinsic must be a vector. -'``llvm.experimental.vector.deinterleave2``' Intrinsic +'``llvm.vector.deinterleave2``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: @@ -18841,13 +18842,13 @@ This is an overloaded intrinsic. :: - declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec1) - declare {, } @llvm.experimental.vector.deinterleave2.nxv8i32( %vec1) + declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec1) + declare {, } @llvm.vector.deinterleave2.nxv8i32( %vec1) Overview: """"""""" -The '``llvm.experimental.vector.deinterleave2``' intrinsic constructs two +The '``llvm.vector.deinterleave2``' intrinsic constructs two vectors by deinterleaving the even and odd lanes of the input vector. This intrinsic works for both fixed and scalable vectors. While this intrinsic @@ -18859,7 +18860,7 @@ For example: .. code-block:: text - {<2 x i64>, <2 x i64>} llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> ); ==> {<2 x i64> , <2 x i64> } + {<2 x i64>, <2 x i64>} llvm.vector.deinterleave2.v4i64(<4 x i64> ); ==> {<2 x i64> , <2 x i64> } Arguments: """""""""" @@ -18867,7 +18868,7 @@ Arguments: The argument is a vector whose type corresponds to the logical concatenation of the two result types. -'``llvm.experimental.vector.interleave2``' Intrinsic +'``llvm.vector.interleave2``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: @@ -18876,13 +18877,13 @@ This is an overloaded intrinsic. :: - declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %vec1, <2 x double> %vec2) - declare @llvm.experimental.vector.interleave2.nxv8i32( %vec1, %vec2) + declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %vec1, <2 x double> %vec2) + declare @llvm.vector.interleave2.nxv8i32( %vec1, %vec2) Overview: """"""""" -The '``llvm.experimental.vector.interleave2``' intrinsic constructs a vector +The '``llvm.vector.interleave2``' intrinsic constructs a vector by interleaving two input vectors. This intrinsic works for both fixed and scalable vectors. While this intrinsic @@ -18894,7 +18895,7 @@ For example: .. code-block:: text - <4 x i64> llvm.experimental.vector.interleave2.v4i64(<2 x i64> , <2 x i64> ); ==> <4 x i64> + <4 x i64> llvm.vector.interleave2.v4i64(<2 x i64> , <2 x i64> ); ==> <4 x i64> Arguments: """""""""" @@ -18940,7 +18941,7 @@ The '``llvm.experimental.cttz.elts``' intrinsic counts the trailing (least significant) zero elements in a vector. If ``src == 0`` the result is the number of elements in the input vector. -'``llvm.experimental.vector.splice``' Intrinsic +'``llvm.vector.splice``' Intrinsic ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ Syntax: @@ -18949,13 +18950,13 @@ This is an overloaded intrinsic. :: - declare <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %vec1, <2 x double> %vec2, i32 %imm) - declare @llvm.experimental.vector.splice.nxv4i32( %vec1, %vec2, i32 %imm) + declare <2 x double> @llvm.vector.splice.v2f64(<2 x double> %vec1, <2 x double> %vec2, i32 %imm) + declare @llvm.vector.splice.nxv4i32( %vec1, %vec2, i32 %imm) Overview: """"""""" -The '``llvm.experimental.vector.splice.*``' intrinsics construct a vector by +The '``llvm.vector.splice.*``' intrinsics construct a vector by concatenating elements from the first input vector with elements of the second input vector, returning a vector of the same type as the input vectors. The signed immediate, modulo the number of elements in the vector, is the index @@ -18966,7 +18967,7 @@ immediate, it extracts ``-imm`` trailing elements from the first vector, and the remaining elements from ``%vec2``. These intrinsics work for both fixed and scalable vectors. While this intrinsic -is marked as experimental, the recommended way to express this operation for +supports all vector types the recommended way to express this operation for fixed-width vectors is still to use a shufflevector, as that may allow for more optimization opportunities. @@ -18974,8 +18975,8 @@ For example: .. code-block:: text - llvm.experimental.vector.splice(, , 1); ==> index - llvm.experimental.vector.splice(, , -3); ==> trailing elements + llvm.vector.splice(, , 1); ==> index + llvm.vector.splice(, , -3); ==> trailing elements Arguments: @@ -22198,7 +22199,7 @@ Overview: """"""""" The '``llvm.experimental.vp.splice.*``' intrinsic is the vector length -predicated version of the '``llvm.experimental.vector.splice.*``' intrinsic. +predicated version of the '``llvm.vector.splice.*``' intrinsic. Arguments: """""""""" @@ -22257,7 +22258,7 @@ Overview: """"""""" The '``llvm.experimental.vp.reverse.*``' intrinsic is the vector length -predicated version of the '``llvm.experimental.vector.reverse.*``' intrinsic. +predicated version of the '``llvm.vector.reverse.*``' intrinsic. Arguments: """""""""" diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index 64a698325212..46d79d6c5822 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -50,7 +50,11 @@ Update on required toolchains to build LLVM Changes to the LLVM IR ---------------------- -- Added Memory Model Relaxation Annotations (MMRAs). +* Added Memory Model Relaxation Annotations (MMRAs). +* Renamed ``llvm.experimental.vector.reverse`` intrinsic to ``llvm.vector.reverse``. +* Renamed ``llvm.experimental.vector.splice`` intrinsic to ``llvm.vector.splice``. +* Renamed ``llvm.experimental.vector.interleave2`` intrinsic to ``llvm.vector.interleave2``. +* Renamed ``llvm.experimental.vector.deinterleave2`` intrinsic to ``llvm.vector.deinterleave2``. Changes to LLVM infrastructure ------------------------------ diff --git a/llvm/include/llvm/CodeGen/BasicTTIImpl.h b/llvm/include/llvm/CodeGen/BasicTTIImpl.h index 4a3a03dc5ad4..92b51438b4cb 100644 --- a/llvm/include/llvm/CodeGen/BasicTTIImpl.h +++ b/llvm/include/llvm/CodeGen/BasicTTIImpl.h @@ -1662,12 +1662,12 @@ public: TTI::SK_InsertSubvector, cast(Args[0]->getType()), std::nullopt, CostKind, Index, cast(Args[1]->getType())); } - case Intrinsic::experimental_vector_reverse: { + case Intrinsic::vector_reverse: { return thisT()->getShuffleCost( TTI::SK_Reverse, cast(Args[0]->getType()), std::nullopt, CostKind, 0, cast(RetTy)); } - case Intrinsic::experimental_vector_splice: { + case Intrinsic::vector_splice: { unsigned Index = cast(Args[2])->getZExtValue(); return thisT()->getShuffleCost( TTI::SK_Splice, cast(Args[0]->getType()), std::nullopt, diff --git a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h index 5f28908e998a..deae2c55d26e 100644 --- a/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h +++ b/llvm/include/llvm/CodeGen/GlobalISel/IRTranslator.h @@ -247,8 +247,8 @@ private: bool translateTrap(const CallInst &U, MachineIRBuilder &MIRBuilder, unsigned Opcode); - // Translate @llvm.experimental.vector.interleave2 and - // @llvm.experimental.vector.deinterleave2 intrinsics for fixed-width vector + // Translate @llvm.vector.interleave2 and + // @llvm.vector.deinterleave2 intrinsics for fixed-width vector // types into vector shuffles. bool translateVectorInterleave2Intrinsic(const CallInst &CI, MachineIRBuilder &MIRBuilder); diff --git a/llvm/include/llvm/CodeGen/TargetLowering.h b/llvm/include/llvm/CodeGen/TargetLowering.h index 6b8090b09b04..661b2841c6ac 100644 --- a/llvm/include/llvm/CodeGen/TargetLowering.h +++ b/llvm/include/llvm/CodeGen/TargetLowering.h @@ -3146,7 +3146,7 @@ public: /// Lower a deinterleave intrinsic to a target specific load intrinsic. /// Return true on success. Currently only supports - /// llvm.experimental.vector.deinterleave2 + /// llvm.vector.deinterleave2 /// /// \p DI is the deinterleave intrinsic. /// \p LI is the accompanying load instruction @@ -3157,7 +3157,7 @@ public: /// Lower an interleave intrinsic to a target specific store intrinsic. /// Return true on success. Currently only supports - /// llvm.experimental.vector.interleave2 + /// llvm.vector.interleave2 /// /// \p II is the interleave intrinsic. /// \p SI is the accompanying store instruction diff --git a/llvm/include/llvm/IR/Intrinsics.td b/llvm/include/llvm/IR/Intrinsics.td index a14e9dedef8c..a2678d69ce40 100644 --- a/llvm/include/llvm/IR/Intrinsics.td +++ b/llvm/include/llvm/IR/Intrinsics.td @@ -2577,15 +2577,15 @@ def int_preserve_static_offset : DefaultAttrsIntrinsic<[llvm_ptr_ty], //===------------ Intrinsics to perform common vector shuffles ------------===// -def int_experimental_vector_reverse : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>], - [IntrNoMem]>; +def int_vector_reverse : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>], + [IntrNoMem]>; -def int_experimental_vector_splice : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMMatchType<0>, - LLVMMatchType<0>, - llvm_i32_ty], - [IntrNoMem, ImmArg>]>; +def int_vector_splice : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMMatchType<0>, + LLVMMatchType<0>, + llvm_i32_ty], + [IntrNoMem, ImmArg>]>; //===---------- Intrinsics to query properties of scalable vectors --------===// def int_vscale : DefaultAttrsIntrinsic<[llvm_anyint_ty], [], [IntrNoMem]>; @@ -2600,15 +2600,15 @@ def int_vector_extract : DefaultAttrsIntrinsic<[llvm_anyvector_ty], [IntrNoMem, IntrSpeculatable, ImmArg>]>; -def int_experimental_vector_interleave2 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], - [LLVMHalfElementsVectorType<0>, - LLVMHalfElementsVectorType<0>], - [IntrNoMem]>; +def int_vector_interleave2 : DefaultAttrsIntrinsic<[llvm_anyvector_ty], + [LLVMHalfElementsVectorType<0>, + LLVMHalfElementsVectorType<0>], + [IntrNoMem]>; -def int_experimental_vector_deinterleave2 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>, - LLVMHalfElementsVectorType<0>], - [llvm_anyvector_ty], - [IntrNoMem]>; +def int_vector_deinterleave2 : DefaultAttrsIntrinsic<[LLVMHalfElementsVectorType<0>, + LLVMHalfElementsVectorType<0>], + [llvm_anyvector_ty], + [IntrNoMem]>; //===----------------- Pointer Authentication Intrinsics ------------------===// // diff --git a/llvm/include/llvm/IR/PatternMatch.h b/llvm/include/llvm/IR/PatternMatch.h index 0b13b4aad9c3..739208e74dcb 100644 --- a/llvm/include/llvm/IR/PatternMatch.h +++ b/llvm/include/llvm/IR/PatternMatch.h @@ -2513,7 +2513,7 @@ inline typename m_Intrinsic_Ty::Ty m_CopySign(const Opnd0 &Op0, template inline typename m_Intrinsic_Ty::Ty m_VecReverse(const Opnd0 &Op0) { - return m_Intrinsic(Op0); + return m_Intrinsic(Op0); } //===----------------------------------------------------------------------===// diff --git a/llvm/lib/Analysis/InstructionSimplify.cpp b/llvm/lib/Analysis/InstructionSimplify.cpp index c06984c0d494..4061dae83c10 100644 --- a/llvm/lib/Analysis/InstructionSimplify.cpp +++ b/llvm/lib/Analysis/InstructionSimplify.cpp @@ -6281,11 +6281,11 @@ static Value *simplifyUnaryIntrinsic(Function *F, Value *Op0, m_Intrinsic(m_SpecificFP(10.0), m_Value(X))))) return X; break; - case Intrinsic::experimental_vector_reverse: - // experimental.vector.reverse(experimental.vector.reverse(x)) -> x + case Intrinsic::vector_reverse: + // vector.reverse(vector.reverse(x)) -> x if (match(Op0, m_VecReverse(m_Value(X)))) return X; - // experimental.vector.reverse(splat(X)) -> splat(X) + // vector.reverse(splat(X)) -> splat(X) if (isSplatValue(Op0)) return Op0; break; diff --git a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp index 031a271de5bd..8573b016d1e5 100644 --- a/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp +++ b/llvm/lib/CodeGen/ComplexDeinterleavingPass.cpp @@ -1639,8 +1639,7 @@ bool ComplexDeinterleavingGraph::checkNodes() { ComplexDeinterleavingGraph::NodePtr ComplexDeinterleavingGraph::identifyRoot(Instruction *RootI) { if (auto *Intrinsic = dyn_cast(RootI)) { - if (Intrinsic->getIntrinsicID() != - Intrinsic::experimental_vector_interleave2) + if (Intrinsic->getIntrinsicID() != Intrinsic::vector_interleave2) return nullptr; auto *Real = dyn_cast(Intrinsic->getOperand(0)); @@ -1675,7 +1674,7 @@ ComplexDeinterleavingGraph::identifyDeinterleave(Instruction *Real, Value *FinalValue = nullptr; if (match(Real, m_ExtractValue<0>(m_Instruction(I))) && match(Imag, m_ExtractValue<1>(m_Specific(I))) && - match(I, m_Intrinsic( + match(I, m_Intrinsic( m_Value(FinalValue)))) { NodePtr PlaceholderNode = prepareCompositeNode( llvm::ComplexDeinterleavingOperation::Deinterleave, Real, Imag); @@ -1960,13 +1959,11 @@ Value *ComplexDeinterleavingGraph::replaceNode(IRBuilderBase &Builder, // Splats that are not constant are interleaved where they are located Instruction *InsertPoint = (I->comesBefore(R) ? R : I)->getNextNode(); IRBuilder<> IRB(InsertPoint); - ReplacementNode = - IRB.CreateIntrinsic(Intrinsic::experimental_vector_interleave2, NewTy, - {Node->Real, Node->Imag}); + ReplacementNode = IRB.CreateIntrinsic(Intrinsic::vector_interleave2, + NewTy, {Node->Real, Node->Imag}); } else { - ReplacementNode = - Builder.CreateIntrinsic(Intrinsic::experimental_vector_interleave2, - NewTy, {Node->Real, Node->Imag}); + ReplacementNode = Builder.CreateIntrinsic( + Intrinsic::vector_interleave2, NewTy, {Node->Real, Node->Imag}); } break; } @@ -1991,9 +1988,8 @@ Value *ComplexDeinterleavingGraph::replaceNode(IRBuilderBase &Builder, auto *B = replaceNode(Builder, Node->Operands[1]); auto *NewMaskTy = VectorType::getDoubleElementsVectorType( cast(MaskReal->getType())); - auto *NewMask = - Builder.CreateIntrinsic(Intrinsic::experimental_vector_interleave2, - NewMaskTy, {MaskReal, MaskImag}); + auto *NewMask = Builder.CreateIntrinsic(Intrinsic::vector_interleave2, + NewMaskTy, {MaskReal, MaskImag}); ReplacementNode = Builder.CreateSelect(NewMask, A, B); break; } @@ -2021,8 +2017,8 @@ void ComplexDeinterleavingGraph::processReductionOperation( Value *InitImag = OldPHIImag->getIncomingValueForBlock(Incoming); IRBuilder<> Builder(Incoming->getTerminator()); - auto *NewInit = Builder.CreateIntrinsic( - Intrinsic::experimental_vector_interleave2, NewVTy, {InitReal, InitImag}); + auto *NewInit = Builder.CreateIntrinsic(Intrinsic::vector_interleave2, NewVTy, + {InitReal, InitImag}); NewPHI->addIncoming(NewInit, Incoming); NewPHI->addIncoming(OperationReplacement, BackEdge); @@ -2034,9 +2030,9 @@ void ComplexDeinterleavingGraph::processReductionOperation( Builder.SetInsertPoint( &*FinalReductionReal->getParent()->getFirstInsertionPt()); - auto *Deinterleave = Builder.CreateIntrinsic( - Intrinsic::experimental_vector_deinterleave2, - OperationReplacement->getType(), OperationReplacement); + auto *Deinterleave = Builder.CreateIntrinsic(Intrinsic::vector_deinterleave2, + OperationReplacement->getType(), + OperationReplacement); auto *NewReal = Builder.CreateExtractValue(Deinterleave, (uint64_t)0); FinalReductionReal->replaceUsesOfWith(Real, NewReal); diff --git a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp index d7b0c9aa1667..e26c6ca3d616 100644 --- a/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp +++ b/llvm/lib/CodeGen/GlobalISel/IRTranslator.cpp @@ -1804,7 +1804,7 @@ bool IRTranslator::translateTrap(const CallInst &CI, bool IRTranslator::translateVectorInterleave2Intrinsic( const CallInst &CI, MachineIRBuilder &MIRBuilder) { - assert(CI.getIntrinsicID() == Intrinsic::experimental_vector_interleave2 && + assert(CI.getIntrinsicID() == Intrinsic::vector_interleave2 && "This function can only be called on the interleave2 intrinsic!"); // Canonicalize interleave2 to G_SHUFFLE_VECTOR (similar to SelectionDAG). Register Op0 = getOrCreateVReg(*CI.getOperand(0)); @@ -1820,7 +1820,7 @@ bool IRTranslator::translateVectorInterleave2Intrinsic( bool IRTranslator::translateVectorDeinterleave2Intrinsic( const CallInst &CI, MachineIRBuilder &MIRBuilder) { - assert(CI.getIntrinsicID() == Intrinsic::experimental_vector_deinterleave2 && + assert(CI.getIntrinsicID() == Intrinsic::vector_deinterleave2 && "This function can only be called on the deinterleave2 intrinsic!"); // Canonicalize deinterleave2 to shuffles that extract sub-vectors (similar to // SelectionDAG). @@ -2572,15 +2572,15 @@ bool IRTranslator::translateKnownIntrinsic(const CallInst &CI, Intrinsic::ID ID, return true; } - case Intrinsic::experimental_vector_interleave2: - case Intrinsic::experimental_vector_deinterleave2: { + case Intrinsic::vector_interleave2: + case Intrinsic::vector_deinterleave2: { // Both intrinsics have at least one operand. Value *Op0 = CI.getOperand(0); LLT ResTy = getLLTForType(*Op0->getType(), MIRBuilder.getDataLayout()); if (!ResTy.isFixedVector()) return false; - if (CI.getIntrinsicID() == Intrinsic::experimental_vector_interleave2) + if (CI.getIntrinsicID() == Intrinsic::vector_interleave2) return translateVectorInterleave2Intrinsic(CI, MIRBuilder); return translateVectorDeinterleave2Intrinsic(CI, MIRBuilder); diff --git a/llvm/lib/CodeGen/InterleavedAccessPass.cpp b/llvm/lib/CodeGen/InterleavedAccessPass.cpp index 8989eabbe6df..8c9065aec7fa 100644 --- a/llvm/lib/CodeGen/InterleavedAccessPass.cpp +++ b/llvm/lib/CodeGen/InterleavedAccessPass.cpp @@ -535,9 +535,9 @@ bool InterleavedAccessImpl::runOnFunction(Function &F) { if (auto *II = dyn_cast(&I)) { // At present, we only have intrinsics to represent (de)interleaving // with a factor of 2. - if (II->getIntrinsicID() == Intrinsic::experimental_vector_deinterleave2) + if (II->getIntrinsicID() == Intrinsic::vector_deinterleave2) Changed |= lowerDeinterleaveIntrinsic(II, DeadInsts); - if (II->getIntrinsicID() == Intrinsic::experimental_vector_interleave2) + if (II->getIntrinsicID() == Intrinsic::vector_interleave2) Changed |= lowerInterleaveIntrinsic(II, DeadInsts); } } diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp index 0db484a5e06b..5caf868c83a2 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp @@ -7930,19 +7930,19 @@ void SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, DAG.getNode(ISD::EXTRACT_SUBVECTOR, sdl, ResultVT, Vec, Index)); return; } - case Intrinsic::experimental_vector_reverse: + case Intrinsic::vector_reverse: visitVectorReverse(I); return; - case Intrinsic::experimental_vector_splice: + case Intrinsic::vector_splice: visitVectorSplice(I); return; case Intrinsic::callbr_landingpad: visitCallBrLandingPad(I); return; - case Intrinsic::experimental_vector_interleave2: + case Intrinsic::vector_interleave2: visitVectorInterleave(I); return; - case Intrinsic::experimental_vector_deinterleave2: + case Intrinsic::vector_deinterleave2: visitVectorDeinterleave(I); return; case Intrinsic::experimental_convergence_anchor: diff --git a/llvm/lib/IR/AutoUpgrade.cpp b/llvm/lib/IR/AutoUpgrade.cpp index 6dc5b9aae769..5b02b0e94dda 100644 --- a/llvm/lib/IR/AutoUpgrade.cpp +++ b/llvm/lib/IR/AutoUpgrade.cpp @@ -1092,17 +1092,24 @@ static bool upgradeIntrinsicFunction1(Function *F, Function *&NewFn, break; case 'e': if (Name.consume_front("experimental.vector.")) { - Intrinsic::ID ID = StringSwitch(Name) - .StartsWith("extract.", Intrinsic::vector_extract) - .StartsWith("insert.", Intrinsic::vector_insert) - .Default(Intrinsic::not_intrinsic); + Intrinsic::ID ID = + StringSwitch(Name) + .StartsWith("extract.", Intrinsic::vector_extract) + .StartsWith("insert.", Intrinsic::vector_insert) + .StartsWith("splice.", Intrinsic::vector_splice) + .StartsWith("reverse.", Intrinsic::vector_reverse) + .StartsWith("interleave2.", Intrinsic::vector_interleave2) + .StartsWith("deinterleave2.", Intrinsic::vector_deinterleave2) + .Default(Intrinsic::not_intrinsic); if (ID != Intrinsic::not_intrinsic) { const auto *FT = F->getFunctionType(); SmallVector Tys; - if (ID == Intrinsic::vector_extract) + if (ID == Intrinsic::vector_extract || + ID == Intrinsic::vector_interleave2) // Extracting overloads the return type. Tys.push_back(FT->getReturnType()); - Tys.push_back(FT->getParamType(0)); + if (ID != Intrinsic::vector_interleave2) + Tys.push_back(FT->getParamType(0)); if (ID == Intrinsic::vector_insert) // Inserting overloads the inserted type. Tys.push_back(FT->getParamType(1)); diff --git a/llvm/lib/IR/IRBuilder.cpp b/llvm/lib/IR/IRBuilder.cpp index d6746d1d4382..9ec5a7deeec6 100644 --- a/llvm/lib/IR/IRBuilder.cpp +++ b/llvm/lib/IR/IRBuilder.cpp @@ -1171,8 +1171,7 @@ Value *IRBuilderBase::CreateVectorReverse(Value *V, const Twine &Name) { auto *Ty = cast(V->getType()); if (isa(Ty)) { Module *M = BB->getParent()->getParent(); - Function *F = Intrinsic::getDeclaration( - M, Intrinsic::experimental_vector_reverse, Ty); + Function *F = Intrinsic::getDeclaration(M, Intrinsic::vector_reverse, Ty); return Insert(CallInst::Create(F, V), Name); } // Keep the original behaviour for fixed vector @@ -1191,8 +1190,7 @@ Value *IRBuilderBase::CreateVectorSplice(Value *V1, Value *V2, int64_t Imm, if (auto *VTy = dyn_cast(V1->getType())) { Module *M = BB->getParent()->getParent(); - Function *F = Intrinsic::getDeclaration( - M, Intrinsic::experimental_vector_splice, VTy); + Function *F = Intrinsic::getDeclaration(M, Intrinsic::vector_splice, VTy); Value *Ops[] = {V1, V2, getInt32(Imm)}; return Insert(CallInst::Create(F, Ops), Name); diff --git a/llvm/lib/IR/Instructions.cpp b/llvm/lib/IR/Instructions.cpp index d2babc748731..7ad1ad4cddb7 100644 --- a/llvm/lib/IR/Instructions.cpp +++ b/llvm/lib/IR/Instructions.cpp @@ -2889,7 +2889,7 @@ bool ShuffleVectorInst::isOneUseSingleSourceMask(int VF) const { bool ShuffleVectorInst::isInterleave(unsigned Factor) { FixedVectorType *OpTy = dyn_cast(getOperand(0)->getType()); // shuffle_vector can only interleave fixed length vectors - for scalable - // vectors, see the @llvm.experimental.vector.interleave2 intrinsic + // vectors, see the @llvm.vector.interleave2 intrinsic if (!OpTy) return false; unsigned OpNumElts = OpTy->getNumElements(); diff --git a/llvm/lib/IR/Verifier.cpp b/llvm/lib/IR/Verifier.cpp index e42cc7e260ef..430e2ce89f6a 100644 --- a/llvm/lib/IR/Verifier.cpp +++ b/llvm/lib/IR/Verifier.cpp @@ -6019,7 +6019,7 @@ void Verifier::visitIntrinsicCall(Intrinsic::ID ID, CallBase &Call) { break; } - case Intrinsic::experimental_vector_splice: { + case Intrinsic::vector_splice: { VectorType *VecTy = cast(Call.getType()); int64_t Idx = cast(Call.getArgOperand(2))->getSExtValue(); int64_t KnownMinNumElements = VecTy->getElementCount().getKnownMinValue(); diff --git a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp index 409ba13b8c6a..cb7930f0cdee 100644 --- a/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp +++ b/llvm/lib/Target/AArch64/AArch64ISelLowering.cpp @@ -16398,7 +16398,7 @@ bool AArch64TargetLowering::lowerInterleavedStore(StoreInst *SI, bool AArch64TargetLowering::lowerDeinterleaveIntrinsicToLoad( IntrinsicInst *DI, LoadInst *LI) const { // Only deinterleave2 supported at present. - if (DI->getIntrinsicID() != Intrinsic::experimental_vector_deinterleave2) + if (DI->getIntrinsicID() != Intrinsic::vector_deinterleave2) return false; // Only a factor of 2 supported at present. @@ -16473,7 +16473,7 @@ bool AArch64TargetLowering::lowerDeinterleaveIntrinsicToLoad( bool AArch64TargetLowering::lowerInterleaveIntrinsicToStore( IntrinsicInst *II, StoreInst *SI) const { // Only interleave2 supported at present. - if (II->getIntrinsicID() != Intrinsic::experimental_vector_interleave2) + if (II->getIntrinsicID() != Intrinsic::vector_interleave2) return false; // Only a factor of 2 supported at present. diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp index f654065c735d..243891249668 100644 --- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp +++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp @@ -1570,7 +1570,7 @@ bool AArch64LegalizerInfo::legalizeIntrinsic(LegalizerHelper &Helper, MI.eraseFromParent(); return true; } - case Intrinsic::experimental_vector_reverse: + case Intrinsic::vector_reverse: // TODO: Add support for vector_reverse return false; } diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp index ebc2d04e9371..662ff86df600 100644 --- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp +++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp @@ -21015,7 +21015,7 @@ bool RISCVTargetLowering::lowerDeinterleaveIntrinsicToLoad(IntrinsicInst *DI, IRBuilder<> Builder(LI); // Only deinterleave2 supported at present. - if (DI->getIntrinsicID() != Intrinsic::experimental_vector_deinterleave2) + if (DI->getIntrinsicID() != Intrinsic::vector_deinterleave2) return false; unsigned Factor = 2; @@ -21065,7 +21065,7 @@ bool RISCVTargetLowering::lowerInterleaveIntrinsicToStore(IntrinsicInst *II, IRBuilder<> Builder(SI); // Only interleave2 supported at present. - if (II->getIntrinsicID() != Intrinsic::experimental_vector_interleave2) + if (II->getIntrinsicID() != Intrinsic::vector_interleave2) return false; unsigned Factor = 2; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp index e5652458f150..1913ef92c16c 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCalls.cpp @@ -3168,7 +3168,7 @@ Instruction *InstCombinerImpl::visitCallInst(CallInst &CI) { } break; } - case Intrinsic::experimental_vector_reverse: { + case Intrinsic::vector_reverse: { Value *BO0, *BO1, *X, *Y; Value *Vec = II->getArgOperand(0); if (match(Vec, m_OneUse(m_BinOp(m_Value(BO0), m_Value(BO1))))) { diff --git a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp index 1064340cb536..f66883de8dd5 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineCompares.cpp @@ -6889,8 +6889,8 @@ static Instruction *foldVectorCmp(CmpInst &Cmp, if (auto *I = dyn_cast(V)) I->copyIRFlags(&Cmp); Module *M = Cmp.getModule(); - Function *F = Intrinsic::getDeclaration( - M, Intrinsic::experimental_vector_reverse, V->getType()); + Function *F = + Intrinsic::getDeclaration(M, Intrinsic::vector_reverse, V->getType()); return CallInst::Create(F, V); }; diff --git a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp index 117eb7a1dcc9..8818369e7945 100644 --- a/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp +++ b/llvm/lib/Transforms/InstCombine/InstCombineSelect.cpp @@ -2537,8 +2537,8 @@ Instruction *InstCombinerImpl::foldVectorSelect(SelectInst &Sel) { if (auto *I = dyn_cast(V)) I->copyIRFlags(&Sel); Module *M = Sel.getModule(); - Function *F = Intrinsic::getDeclaration( - M, Intrinsic::experimental_vector_reverse, V->getType()); + Function *F = + Intrinsic::getDeclaration(M, Intrinsic::vector_reverse, V->getType()); return CallInst::Create(F, V); }; diff --git a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp index 0858116cd911..7356941be645 100644 --- a/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp +++ b/llvm/lib/Transforms/InstCombine/InstructionCombining.cpp @@ -2043,8 +2043,8 @@ Instruction *InstCombinerImpl::foldVectorBinop(BinaryOperator &Inst) { if (auto *BO = dyn_cast(V)) BO->copyIRFlags(&Inst); Module *M = Inst.getModule(); - Function *F = Intrinsic::getDeclaration( - M, Intrinsic::experimental_vector_reverse, V->getType()); + Function *F = + Intrinsic::getDeclaration(M, Intrinsic::vector_reverse, V->getType()); return CallInst::Create(F, V); }; diff --git a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp index e2dd62619b01..f6dcdbee590e 100644 --- a/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp +++ b/llvm/lib/Transforms/Vectorize/LoopVectorize.cpp @@ -460,9 +460,9 @@ static Value *interleaveVectors(IRBuilderBase &Builder, ArrayRef Vals, // must use intrinsics to interleave. if (VecTy->isScalableTy()) { VectorType *WideVecTy = VectorType::getDoubleElementsVectorType(VecTy); - return Builder.CreateIntrinsic( - WideVecTy, Intrinsic::experimental_vector_interleave2, Vals, - /*FMFSource=*/nullptr, Name); + return Builder.CreateIntrinsic(WideVecTy, Intrinsic::vector_interleave2, + Vals, + /*FMFSource=*/nullptr, Name); } // Fixed length. Start by concatenating all vectors into a wide vector. @@ -2517,9 +2517,8 @@ void InnerLoopVectorizer::vectorizeInterleaveGroup( SmallVector Ops = {BlockInMaskPart, BlockInMaskPart}; auto *MaskTy = VectorType::get(Builder.getInt1Ty(), VF.getKnownMinValue() * 2, true); - return Builder.CreateIntrinsic( - MaskTy, Intrinsic::experimental_vector_interleave2, Ops, - /*FMFSource=*/nullptr, "interleaved.mask"); + return Builder.CreateIntrinsic(MaskTy, Intrinsic::vector_interleave2, Ops, + /*FMFSource=*/nullptr, "interleaved.mask"); } if (!BlockInMask) @@ -2571,7 +2570,7 @@ void InnerLoopVectorizer::vectorizeInterleaveGroup( // Scalable vectors cannot use arbitrary shufflevectors (only splats), // so must use intrinsics to deinterleave. Value *DI = Builder.CreateIntrinsic( - Intrinsic::experimental_vector_deinterleave2, VecTy, NewLoads[Part], + Intrinsic::vector_deinterleave2, VecTy, NewLoads[Part], /*FMFSource=*/nullptr, "strided.vec"); unsigned J = 0; for (unsigned I = 0; I < InterleaveFactor; ++I) { diff --git a/llvm/test/Analysis/CostModel/AArch64/getIntrinsicInstrCost-vector-reverse.ll b/llvm/test/Analysis/CostModel/AArch64/getIntrinsicInstrCost-vector-reverse.ll index 836a028ad6aa..f491b086107a 100644 --- a/llvm/test/Analysis/CostModel/AArch64/getIntrinsicInstrCost-vector-reverse.ll +++ b/llvm/test/Analysis/CostModel/AArch64/getIntrinsicInstrCost-vector-reverse.ll @@ -7,58 +7,58 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" define void @vector_reverse() #0{ ; CHECK-LABEL: 'vector_reverse' -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <32 x i8> @llvm.experimental.vector.reverse.v32i8(<32 x i8> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = call <16 x i16> @llvm.experimental.vector.reverse.v16i16(<16 x i16> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %6 = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %8 = call <4 x i64> @llvm.experimental.vector.reverse.v4i64(<4 x i64> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %9 = call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %10 = call <16 x half> @llvm.experimental.vector.reverse.v16f16(<16 x half> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %11 = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %12 = call <8 x float> @llvm.experimental.vector.reverse.v8f32(<8 x float> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %14 = call <4 x double> @llvm.experimental.vector.reverse.v4f64(<4 x double> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %15 = call <8 x bfloat> @llvm.experimental.vector.reverse.v8bf16(<8 x bfloat> undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %16 = call <16 x bfloat> @llvm.experimental.vector.reverse.v16bf16(<16 x bfloat> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %1 = call <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %2 = call <32 x i8> @llvm.vector.reverse.v32i8(<32 x i8> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %3 = call <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %4 = call <16 x i16> @llvm.vector.reverse.v16i16(<16 x i16> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %5 = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %6 = call <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %7 = call <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %8 = call <4 x i64> @llvm.vector.reverse.v4i64(<4 x i64> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %9 = call <8 x half> @llvm.vector.reverse.v8f16(<8 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %10 = call <16 x half> @llvm.vector.reverse.v16f16(<16 x half> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %11 = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %12 = call <8 x float> @llvm.vector.reverse.v8f32(<8 x float> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %13 = call <2 x double> @llvm.vector.reverse.v2f64(<2 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %14 = call <4 x double> @llvm.vector.reverse.v4f64(<4 x double> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 28 for instruction: %15 = call <8 x bfloat> @llvm.vector.reverse.v8bf16(<8 x bfloat> undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 56 for instruction: %16 = call <16 x bfloat> @llvm.vector.reverse.v16bf16(<16 x bfloat> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; - call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> undef) - call <32 x i8> @llvm.experimental.vector.reverse.v32i8(<32 x i8> undef) - call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> undef) - call <16 x i16> @llvm.experimental.vector.reverse.v16i16(<16 x i16> undef) - call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> undef) - call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> undef) - call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> undef) - call <4 x i64> @llvm.experimental.vector.reverse.v4i64(<4 x i64> undef) - call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> undef) - call <16 x half> @llvm.experimental.vector.reverse.v16f16(<16 x half> undef) - call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> undef) - call <8 x float> @llvm.experimental.vector.reverse.v8f32(<8 x float> undef) - call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> undef) - call <4 x double> @llvm.experimental.vector.reverse.v4f64(<4 x double> undef) - call <8 x bfloat> @llvm.experimental.vector.reverse.v8bf16(<8 x bfloat> undef) - call <16 x bfloat> @llvm.experimental.vector.reverse.v16bf16(<16 x bfloat> undef) + call <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8> undef) + call <32 x i8> @llvm.vector.reverse.v32i8(<32 x i8> undef) + call <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16> undef) + call <16 x i16> @llvm.vector.reverse.v16i16(<16 x i16> undef) + call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> undef) + call <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32> undef) + call <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64> undef) + call <4 x i64> @llvm.vector.reverse.v4i64(<4 x i64> undef) + call <8 x half> @llvm.vector.reverse.v8f16(<8 x half> undef) + call <16 x half> @llvm.vector.reverse.v16f16(<16 x half> undef) + call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> undef) + call <8 x float> @llvm.vector.reverse.v8f32(<8 x float> undef) + call <2 x double> @llvm.vector.reverse.v2f64(<2 x double> undef) + call <4 x double> @llvm.vector.reverse.v4f64(<4 x double> undef) + call <8 x bfloat> @llvm.vector.reverse.v8bf16(<8 x bfloat> undef) + call <16 x bfloat> @llvm.vector.reverse.v16bf16(<16 x bfloat> undef) ret void } attributes #0 = { "target-features"="+sve,+bf16" } -declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>) -declare <32 x i8> @llvm.experimental.vector.reverse.v32i8(<32 x i8>) -declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>) -declare <16 x i16> @llvm.experimental.vector.reverse.v16i16(<16 x i16>) -declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>) -declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>) -declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>) -declare <4 x i64> @llvm.experimental.vector.reverse.v4i64(<4 x i64>) -declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>) -declare <16 x half> @llvm.experimental.vector.reverse.v16f16(<16 x half>) -declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>) -declare <8 x float> @llvm.experimental.vector.reverse.v8f32(<8 x float>) -declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>) -declare <4 x double> @llvm.experimental.vector.reverse.v4f64(<4 x double>) -declare <8 x bfloat> @llvm.experimental.vector.reverse.v8bf16(<8 x bfloat>) -declare <16 x bfloat> @llvm.experimental.vector.reverse.v16bf16(<16 x bfloat>) +declare <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8>) +declare <32 x i8> @llvm.vector.reverse.v32i8(<32 x i8>) +declare <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16>) +declare <16 x i16> @llvm.vector.reverse.v16i16(<16 x i16>) +declare <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32>) +declare <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32>) +declare <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64>) +declare <4 x i64> @llvm.vector.reverse.v4i64(<4 x i64>) +declare <8 x half> @llvm.vector.reverse.v8f16(<8 x half>) +declare <16 x half> @llvm.vector.reverse.v16f16(<16 x half>) +declare <4 x float> @llvm.vector.reverse.v4f32(<4 x float>) +declare <8 x float> @llvm.vector.reverse.v8f32(<8 x float>) +declare <2 x double> @llvm.vector.reverse.v2f64(<2 x double>) +declare <4 x double> @llvm.vector.reverse.v4f64(<4 x double>) +declare <8 x bfloat> @llvm.vector.reverse.v8bf16(<8 x bfloat>) +declare <16 x bfloat> @llvm.vector.reverse.v16bf16(<16 x bfloat>) diff --git a/llvm/test/Analysis/CostModel/AArch64/splice.ll b/llvm/test/Analysis/CostModel/AArch64/splice.ll index f5afdff41b1d..1d76a4838cee 100644 --- a/llvm/test/Analysis/CostModel/AArch64/splice.ll +++ b/llvm/test/Analysis/CostModel/AArch64/splice.ll @@ -5,96 +5,96 @@ target datalayout = "e-m:e-i8:8:32-i16:16:32-i64:64-i128:128-n32:64-S128" define void @vector_splice() #0 { ; CHECK-LABEL: 'vector_splice' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v16i8 = call <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8> zeroinitializer, <16 x i8> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v32i8 = call <32 x i8> @llvm.experimental.vector.splice.v32i8(<32 x i8> zeroinitializer, <32 x i8> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2i16 = call <2 x i16> @llvm.experimental.vector.splice.v2i16(<2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4i16 = call <4 x i16> @llvm.experimental.vector.splice.v4i16(<4 x i16> zeroinitializer, <4 x i16> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8i16 = call <8 x i16> @llvm.experimental.vector.splice.v8i16(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v16i16 = call <16 x i16> @llvm.experimental.vector.splice.v16i16(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4i32 = call <4 x i32> @llvm.experimental.vector.splice.v4i32(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v8i32 = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2i64 = call <2 x i64> @llvm.experimental.vector.splice.v2i64(<2 x i64> zeroinitializer, <2 x i64> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v4i64 = call <4 x i64> @llvm.experimental.vector.splice.v4i64(<4 x i64> zeroinitializer, <4 x i64> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2f16 = call <2 x half> @llvm.experimental.vector.splice.v2f16(<2 x half> zeroinitializer, <2 x half> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4f16 = call <4 x half> @llvm.experimental.vector.splice.v4f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8f16 = call <8 x half> @llvm.experimental.vector.splice.v8f16(<8 x half> zeroinitializer, <8 x half> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v16f16 = call <16 x half> @llvm.experimental.vector.splice.v16f16(<16 x half> zeroinitializer, <16 x half> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2f32 = call <2 x float> @llvm.experimental.vector.splice.v2f32(<2 x float> zeroinitializer, <2 x float> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4f32 = call <4 x float> @llvm.experimental.vector.splice.v4f32(<4 x float> zeroinitializer, <4 x float> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v8f32 = call <8 x float> @llvm.experimental.vector.splice.v8f32(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2f64 = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v4f64 = call <4 x double> @llvm.experimental.vector.splice.v4f64(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2bf16 = call <2 x bfloat> @llvm.experimental.vector.splice.v2bf16(<2 x bfloat> zeroinitializer, <2 x bfloat> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4bf16 = call <4 x bfloat> @llvm.experimental.vector.splice.v4bf16(<4 x bfloat> zeroinitializer, <4 x bfloat> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8bf16 = call <8 x bfloat> @llvm.experimental.vector.splice.v8bf16(<8 x bfloat> zeroinitializer, <8 x bfloat> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v16bf16 = call <16 x bfloat> @llvm.experimental.vector.splice.v16bf16(<16 x bfloat> zeroinitializer, <16 x bfloat> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v16i1 = call <16 x i1> @llvm.experimental.vector.splice.v16i1(<16 x i1> zeroinitializer, <16 x i1> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8i1 = call <8 x i1> @llvm.experimental.vector.splice.v8i1(<8 x i1> zeroinitializer, <8 x i1> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4i1 = call <4 x i1> @llvm.experimental.vector.splice.v4i1(<4 x i1> zeroinitializer, <4 x i1> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2i1 = call <2 x i1> @llvm.experimental.vector.splice.v2i1(<2 x i1> zeroinitializer, <2 x i1> zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %splice.v2i128 = call <2 x i128> @llvm.experimental.vector.splice.v2i128(<2 x i128> zeroinitializer, <2 x i128> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v16i8 = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> zeroinitializer, <16 x i8> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v32i8 = call <32 x i8> @llvm.vector.splice.v32i8(<32 x i8> zeroinitializer, <32 x i8> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2i16 = call <2 x i16> @llvm.vector.splice.v2i16(<2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4i16 = call <4 x i16> @llvm.vector.splice.v4i16(<4 x i16> zeroinitializer, <4 x i16> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8i16 = call <8 x i16> @llvm.vector.splice.v8i16(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v16i16 = call <16 x i16> @llvm.vector.splice.v16i16(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4i32 = call <4 x i32> @llvm.vector.splice.v4i32(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v8i32 = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2i64 = call <2 x i64> @llvm.vector.splice.v2i64(<2 x i64> zeroinitializer, <2 x i64> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v4i64 = call <4 x i64> @llvm.vector.splice.v4i64(<4 x i64> zeroinitializer, <4 x i64> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2f16 = call <2 x half> @llvm.vector.splice.v2f16(<2 x half> zeroinitializer, <2 x half> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4f16 = call <4 x half> @llvm.vector.splice.v4f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8f16 = call <8 x half> @llvm.vector.splice.v8f16(<8 x half> zeroinitializer, <8 x half> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v16f16 = call <16 x half> @llvm.vector.splice.v16f16(<16 x half> zeroinitializer, <16 x half> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2f32 = call <2 x float> @llvm.vector.splice.v2f32(<2 x float> zeroinitializer, <2 x float> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4f32 = call <4 x float> @llvm.vector.splice.v4f32(<4 x float> zeroinitializer, <4 x float> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v8f32 = call <8 x float> @llvm.vector.splice.v8f32(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2f64 = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v4f64 = call <4 x double> @llvm.vector.splice.v4f64(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2bf16 = call <2 x bfloat> @llvm.vector.splice.v2bf16(<2 x bfloat> zeroinitializer, <2 x bfloat> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4bf16 = call <4 x bfloat> @llvm.vector.splice.v4bf16(<4 x bfloat> zeroinitializer, <4 x bfloat> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8bf16 = call <8 x bfloat> @llvm.vector.splice.v8bf16(<8 x bfloat> zeroinitializer, <8 x bfloat> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.v16bf16 = call <16 x bfloat> @llvm.vector.splice.v16bf16(<16 x bfloat> zeroinitializer, <16 x bfloat> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v16i1 = call <16 x i1> @llvm.vector.splice.v16i1(<16 x i1> zeroinitializer, <16 x i1> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v8i1 = call <8 x i1> @llvm.vector.splice.v8i1(<8 x i1> zeroinitializer, <8 x i1> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v4i1 = call <4 x i1> @llvm.vector.splice.v4i1(<4 x i1> zeroinitializer, <4 x i1> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice.v2i1 = call <2 x i1> @llvm.vector.splice.v2i1(<2 x i1> zeroinitializer, <2 x i1> zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: %splice.v2i128 = call <2 x i128> @llvm.vector.splice.v2i128(<2 x i128> zeroinitializer, <2 x i128> zeroinitializer, i32 1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; - %splice.v16i8 = call <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8> zeroinitializer, <16 x i8> zeroinitializer, i32 1) - %splice.v32i8 = call <32 x i8> @llvm.experimental.vector.splice.v32i8(<32 x i8> zeroinitializer, <32 x i8> zeroinitializer, i32 1) - %splice.v2i16 = call <2 x i16> @llvm.experimental.vector.splice.v2i16(<2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i32 1) - %splice.v4i16 = call <4 x i16> @llvm.experimental.vector.splice.v4i16(<4 x i16> zeroinitializer, <4 x i16> zeroinitializer, i32 1) - %splice.v8i16 = call <8 x i16> @llvm.experimental.vector.splice.v8i16(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer, i32 1) - %splice.v16i16 = call <16 x i16> @llvm.experimental.vector.splice.v16i16(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer, i32 1) - %splice.v4i32 = call <4 x i32> @llvm.experimental.vector.splice.v4i32(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer, i32 1) - %splice.v8i32 = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 1) - %splice.v2i64 = call <2 x i64> @llvm.experimental.vector.splice.v2i64(<2 x i64> zeroinitializer, <2 x i64> zeroinitializer, i32 1) - %splice.v4i64 = call <4 x i64> @llvm.experimental.vector.splice.v4i64(<4 x i64> zeroinitializer, <4 x i64> zeroinitializer, i32 1) - %splice.v2f16 = call <2 x half> @llvm.experimental.vector.splice.v2f16(<2 x half> zeroinitializer, <2 x half> zeroinitializer, i32 1) - %splice.v4f16 = call <4 x half> @llvm.experimental.vector.splice.v4f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, i32 1) - %splice.v8f16 = call <8 x half> @llvm.experimental.vector.splice.v8f16(<8 x half> zeroinitializer, <8 x half> zeroinitializer, i32 1) - %splice.v16f16 = call <16 x half> @llvm.experimental.vector.splice.v16f16(<16 x half> zeroinitializer, <16 x half> zeroinitializer, i32 1) - %splice.v2f32 = call <2 x float> @llvm.experimental.vector.splice.v2f32(<2 x float> zeroinitializer, <2 x float> zeroinitializer, i32 1) - %splice.v4f32 = call <4 x float> @llvm.experimental.vector.splice.v4f32(<4 x float> zeroinitializer, <4 x float> zeroinitializer, i32 1) - %splice.v8f32 = call <8 x float> @llvm.experimental.vector.splice.v8f32(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i32 1) - %splice.v2f64 = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, i32 1) - %splice.v4f64 = call <4 x double> @llvm.experimental.vector.splice.v4f64(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i32 1) - %splice.v2bf16 = call <2 x bfloat> @llvm.experimental.vector.splice.v2bf16(<2 x bfloat> zeroinitializer, <2 x bfloat> zeroinitializer, i32 1) - %splice.v4bf16 = call <4 x bfloat> @llvm.experimental.vector.splice.v4bf16(<4 x bfloat> zeroinitializer, <4 x bfloat> zeroinitializer, i32 1) - %splice.v8bf16 = call <8 x bfloat> @llvm.experimental.vector.splice.v8bf16(<8 x bfloat> zeroinitializer, <8 x bfloat> zeroinitializer, i32 1) - %splice.v16bf16 = call <16 x bfloat> @llvm.experimental.vector.splice.v16bf16(<16 x bfloat> zeroinitializer, <16 x bfloat> zeroinitializer, i32 1) - %splice.v16i1 = call <16 x i1> @llvm.experimental.vector.splice.v16i1(<16 x i1> zeroinitializer, <16 x i1> zeroinitializer, i32 1) - %splice.v8i1 = call <8 x i1> @llvm.experimental.vector.splice.v8i1(<8 x i1> zeroinitializer, <8 x i1> zeroinitializer, i32 1) - %splice.v4i1 = call <4 x i1> @llvm.experimental.vector.splice.v4i1(<4 x i1> zeroinitializer, <4 x i1> zeroinitializer, i32 1) - %splice.v2i1 = call <2 x i1> @llvm.experimental.vector.splice.v2i1(<2 x i1> zeroinitializer, <2 x i1> zeroinitializer, i32 1) - %splice.v2i128 = call <2 x i128> @llvm.experimental.vector.splice.v2i128(<2 x i128> zeroinitializer, <2 x i128> zeroinitializer, i32 1) + %splice.v16i8 = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> zeroinitializer, <16 x i8> zeroinitializer, i32 1) + %splice.v32i8 = call <32 x i8> @llvm.vector.splice.v32i8(<32 x i8> zeroinitializer, <32 x i8> zeroinitializer, i32 1) + %splice.v2i16 = call <2 x i16> @llvm.vector.splice.v2i16(<2 x i16> zeroinitializer, <2 x i16> zeroinitializer, i32 1) + %splice.v4i16 = call <4 x i16> @llvm.vector.splice.v4i16(<4 x i16> zeroinitializer, <4 x i16> zeroinitializer, i32 1) + %splice.v8i16 = call <8 x i16> @llvm.vector.splice.v8i16(<8 x i16> zeroinitializer, <8 x i16> zeroinitializer, i32 1) + %splice.v16i16 = call <16 x i16> @llvm.vector.splice.v16i16(<16 x i16> zeroinitializer, <16 x i16> zeroinitializer, i32 1) + %splice.v4i32 = call <4 x i32> @llvm.vector.splice.v4i32(<4 x i32> zeroinitializer, <4 x i32> zeroinitializer, i32 1) + %splice.v8i32 = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> zeroinitializer, <8 x i32> zeroinitializer, i32 1) + %splice.v2i64 = call <2 x i64> @llvm.vector.splice.v2i64(<2 x i64> zeroinitializer, <2 x i64> zeroinitializer, i32 1) + %splice.v4i64 = call <4 x i64> @llvm.vector.splice.v4i64(<4 x i64> zeroinitializer, <4 x i64> zeroinitializer, i32 1) + %splice.v2f16 = call <2 x half> @llvm.vector.splice.v2f16(<2 x half> zeroinitializer, <2 x half> zeroinitializer, i32 1) + %splice.v4f16 = call <4 x half> @llvm.vector.splice.v4f16(<4 x half> zeroinitializer, <4 x half> zeroinitializer, i32 1) + %splice.v8f16 = call <8 x half> @llvm.vector.splice.v8f16(<8 x half> zeroinitializer, <8 x half> zeroinitializer, i32 1) + %splice.v16f16 = call <16 x half> @llvm.vector.splice.v16f16(<16 x half> zeroinitializer, <16 x half> zeroinitializer, i32 1) + %splice.v2f32 = call <2 x float> @llvm.vector.splice.v2f32(<2 x float> zeroinitializer, <2 x float> zeroinitializer, i32 1) + %splice.v4f32 = call <4 x float> @llvm.vector.splice.v4f32(<4 x float> zeroinitializer, <4 x float> zeroinitializer, i32 1) + %splice.v8f32 = call <8 x float> @llvm.vector.splice.v8f32(<8 x float> zeroinitializer, <8 x float> zeroinitializer, i32 1) + %splice.v2f64 = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> zeroinitializer, <2 x double> zeroinitializer, i32 1) + %splice.v4f64 = call <4 x double> @llvm.vector.splice.v4f64(<4 x double> zeroinitializer, <4 x double> zeroinitializer, i32 1) + %splice.v2bf16 = call <2 x bfloat> @llvm.vector.splice.v2bf16(<2 x bfloat> zeroinitializer, <2 x bfloat> zeroinitializer, i32 1) + %splice.v4bf16 = call <4 x bfloat> @llvm.vector.splice.v4bf16(<4 x bfloat> zeroinitializer, <4 x bfloat> zeroinitializer, i32 1) + %splice.v8bf16 = call <8 x bfloat> @llvm.vector.splice.v8bf16(<8 x bfloat> zeroinitializer, <8 x bfloat> zeroinitializer, i32 1) + %splice.v16bf16 = call <16 x bfloat> @llvm.vector.splice.v16bf16(<16 x bfloat> zeroinitializer, <16 x bfloat> zeroinitializer, i32 1) + %splice.v16i1 = call <16 x i1> @llvm.vector.splice.v16i1(<16 x i1> zeroinitializer, <16 x i1> zeroinitializer, i32 1) + %splice.v8i1 = call <8 x i1> @llvm.vector.splice.v8i1(<8 x i1> zeroinitializer, <8 x i1> zeroinitializer, i32 1) + %splice.v4i1 = call <4 x i1> @llvm.vector.splice.v4i1(<4 x i1> zeroinitializer, <4 x i1> zeroinitializer, i32 1) + %splice.v2i1 = call <2 x i1> @llvm.vector.splice.v2i1(<2 x i1> zeroinitializer, <2 x i1> zeroinitializer, i32 1) + %splice.v2i128 = call <2 x i128> @llvm.vector.splice.v2i128(<2 x i128> zeroinitializer, <2 x i128> zeroinitializer, i32 1) ret void } -declare <2 x i1> @llvm.experimental.vector.splice.v2i1(<2 x i1>, <2 x i1>, i32) -declare <4 x i1> @llvm.experimental.vector.splice.v4i1(<4 x i1>, <4 x i1>, i32) -declare <8 x i1> @llvm.experimental.vector.splice.v8i1(<8 x i1>, <8 x i1>, i32) -declare <16 x i1> @llvm.experimental.vector.splice.v16i1(<16 x i1>, <16 x i1>, i32) -declare <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32) -declare <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32) -declare <32 x i8> @llvm.experimental.vector.splice.v32i8(<32 x i8>, <32 x i8>, i32) -declare <2 x i16> @llvm.experimental.vector.splice.v2i16(<2 x i16>, <2 x i16>, i32) -declare <4 x i16> @llvm.experimental.vector.splice.v4i16(<4 x i16>, <4 x i16>, i32) -declare <8 x i16> @llvm.experimental.vector.splice.v8i16(<8 x i16>, <8 x i16>, i32) -declare <16 x i16> @llvm.experimental.vector.splice.v16i16(<16 x i16>, <16 x i16>, i32) -declare <4 x i32> @llvm.experimental.vector.splice.v4i32(<4 x i32>, <4 x i32>, i32) -declare <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32) -declare <2 x i64> @llvm.experimental.vector.splice.v2i64(<2 x i64>, <2 x i64>, i32) -declare <4 x i64> @llvm.experimental.vector.splice.v4i64(<4 x i64>, <4 x i64>, i32) -declare <2 x half> @llvm.experimental.vector.splice.v2f16(<2 x half>, <2 x half>, i32) -declare <4 x half> @llvm.experimental.vector.splice.v4f16(<4 x half>, <4 x half>, i32) -declare <8 x half> @llvm.experimental.vector.splice.v8f16(<8 x half>, <8 x half>, i32) -declare <16 x half> @llvm.experimental.vector.splice.v16f16(<16 x half>, <16 x half>, i32) -declare <2 x bfloat> @llvm.experimental.vector.splice.v2bf16(<2 x bfloat>, <2 x bfloat>, i32) -declare <4 x bfloat> @llvm.experimental.vector.splice.v4bf16(<4 x bfloat>, <4 x bfloat>, i32) -declare <8 x bfloat> @llvm.experimental.vector.splice.v8bf16(<8 x bfloat>, <8 x bfloat>, i32) -declare <16 x bfloat> @llvm.experimental.vector.splice.v16bf16(<16 x bfloat>, <16 x bfloat>, i32) -declare <2 x float> @llvm.experimental.vector.splice.v2f32(<2 x float>, <2 x float>, i32) -declare <4 x float> @llvm.experimental.vector.splice.v4f32(<4 x float>, <4 x float>, i32) -declare <8 x float> @llvm.experimental.vector.splice.v8f32(<8 x float>, <8 x float>, i32) -declare <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float>, <16 x float>, i32) -declare <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double>, <2 x double>, i32) -declare <4 x double> @llvm.experimental.vector.splice.v4f64(<4 x double>, <4 x double>, i32) -declare <2 x i128> @llvm.experimental.vector.splice.v2i128(<2 x i128>, <2 x i128>, i32) +declare <2 x i1> @llvm.vector.splice.v2i1(<2 x i1>, <2 x i1>, i32) +declare <4 x i1> @llvm.vector.splice.v4i1(<4 x i1>, <4 x i1>, i32) +declare <8 x i1> @llvm.vector.splice.v8i1(<8 x i1>, <8 x i1>, i32) +declare <16 x i1> @llvm.vector.splice.v16i1(<16 x i1>, <16 x i1>, i32) +declare <2 x i8> @llvm.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32) +declare <16 x i8> @llvm.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32) +declare <32 x i8> @llvm.vector.splice.v32i8(<32 x i8>, <32 x i8>, i32) +declare <2 x i16> @llvm.vector.splice.v2i16(<2 x i16>, <2 x i16>, i32) +declare <4 x i16> @llvm.vector.splice.v4i16(<4 x i16>, <4 x i16>, i32) +declare <8 x i16> @llvm.vector.splice.v8i16(<8 x i16>, <8 x i16>, i32) +declare <16 x i16> @llvm.vector.splice.v16i16(<16 x i16>, <16 x i16>, i32) +declare <4 x i32> @llvm.vector.splice.v4i32(<4 x i32>, <4 x i32>, i32) +declare <8 x i32> @llvm.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32) +declare <2 x i64> @llvm.vector.splice.v2i64(<2 x i64>, <2 x i64>, i32) +declare <4 x i64> @llvm.vector.splice.v4i64(<4 x i64>, <4 x i64>, i32) +declare <2 x half> @llvm.vector.splice.v2f16(<2 x half>, <2 x half>, i32) +declare <4 x half> @llvm.vector.splice.v4f16(<4 x half>, <4 x half>, i32) +declare <8 x half> @llvm.vector.splice.v8f16(<8 x half>, <8 x half>, i32) +declare <16 x half> @llvm.vector.splice.v16f16(<16 x half>, <16 x half>, i32) +declare <2 x bfloat> @llvm.vector.splice.v2bf16(<2 x bfloat>, <2 x bfloat>, i32) +declare <4 x bfloat> @llvm.vector.splice.v4bf16(<4 x bfloat>, <4 x bfloat>, i32) +declare <8 x bfloat> @llvm.vector.splice.v8bf16(<8 x bfloat>, <8 x bfloat>, i32) +declare <16 x bfloat> @llvm.vector.splice.v16bf16(<16 x bfloat>, <16 x bfloat>, i32) +declare <2 x float> @llvm.vector.splice.v2f32(<2 x float>, <2 x float>, i32) +declare <4 x float> @llvm.vector.splice.v4f32(<4 x float>, <4 x float>, i32) +declare <8 x float> @llvm.vector.splice.v8f32(<8 x float>, <8 x float>, i32) +declare <16 x float> @llvm.vector.splice.v16f32(<16 x float>, <16 x float>, i32) +declare <2 x double> @llvm.vector.splice.v2f64(<2 x double>, <2 x double>, i32) +declare <4 x double> @llvm.vector.splice.v4f64(<4 x double>, <4 x double>, i32) +declare <2 x i128> @llvm.vector.splice.v2i128(<2 x i128>, <2 x i128>, i32) attributes #0 = { "target-features"="+bf16" } diff --git a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll index 7ce3021b0093..15c278b060c9 100644 --- a/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll +++ b/llvm/test/Analysis/CostModel/AArch64/sve-intrinsics.ll @@ -270,122 +270,122 @@ declare @llvm.cttz.nxv4i32(, i1) define void @vector_reverse() #0 { ; CHECK-LABEL: 'vector_reverse' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv16i8 = call @llvm.experimental.vector.reverse.nxv16i8( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv32i8 = call @llvm.experimental.vector.reverse.nxv32i8( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2i16 = call @llvm.experimental.vector.reverse.nxv2i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4i16 = call @llvm.experimental.vector.reverse.nxv4i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8i16 = call @llvm.experimental.vector.reverse.nxv8i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv16i16 = call @llvm.experimental.vector.reverse.nxv16i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4i32 = call @llvm.experimental.vector.reverse.nxv4i32( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv8i32 = call @llvm.experimental.vector.reverse.nxv8i32( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2i64 = call @llvm.experimental.vector.reverse.nxv2i64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv4i64 = call @llvm.experimental.vector.reverse.nxv4i64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2f16 = call @llvm.experimental.vector.reverse.nxv2f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4f16 = call @llvm.experimental.vector.reverse.nxv4f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8f16 = call @llvm.experimental.vector.reverse.nxv8f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv16f16 = call @llvm.experimental.vector.reverse.nxv16f16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2f32 = call @llvm.experimental.vector.reverse.nxv2f32( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4f32 = call @llvm.experimental.vector.reverse.nxv4f32( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv8f32 = call @llvm.experimental.vector.reverse.nxv8f32( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2f64 = call @llvm.experimental.vector.reverse.nxv2f64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv4f64 = call @llvm.experimental.vector.reverse.nxv4f64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2bf16 = call @llvm.experimental.vector.reverse.nxv2bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4bf16 = call @llvm.experimental.vector.reverse.nxv4bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8bf16 = call @llvm.experimental.vector.reverse.nxv8bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv16bf16 = call @llvm.experimental.vector.reverse.nxv16bf16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv16i1 = call @llvm.experimental.vector.reverse.nxv16i1( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8i1 = call @llvm.experimental.vector.reverse.nxv8i1( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4i1 = call @llvm.experimental.vector.reverse.nxv4i1( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2i1 = call @llvm.experimental.vector.reverse.nxv2i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv16i8 = call @llvm.vector.reverse.nxv16i8( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv32i8 = call @llvm.vector.reverse.nxv32i8( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2i16 = call @llvm.vector.reverse.nxv2i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4i16 = call @llvm.vector.reverse.nxv4i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8i16 = call @llvm.vector.reverse.nxv8i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv16i16 = call @llvm.vector.reverse.nxv16i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4i32 = call @llvm.vector.reverse.nxv4i32( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv8i32 = call @llvm.vector.reverse.nxv8i32( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2i64 = call @llvm.vector.reverse.nxv2i64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv4i64 = call @llvm.vector.reverse.nxv4i64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2f16 = call @llvm.vector.reverse.nxv2f16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4f16 = call @llvm.vector.reverse.nxv4f16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8f16 = call @llvm.vector.reverse.nxv8f16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv16f16 = call @llvm.vector.reverse.nxv16f16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2f32 = call @llvm.vector.reverse.nxv2f32( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4f32 = call @llvm.vector.reverse.nxv4f32( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv8f32 = call @llvm.vector.reverse.nxv8f32( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2f64 = call @llvm.vector.reverse.nxv2f64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv4f64 = call @llvm.vector.reverse.nxv4f64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2bf16 = call @llvm.vector.reverse.nxv2bf16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4bf16 = call @llvm.vector.reverse.nxv4bf16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8bf16 = call @llvm.vector.reverse.nxv8bf16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %reverse_nxv16bf16 = call @llvm.vector.reverse.nxv16bf16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv16i1 = call @llvm.vector.reverse.nxv16i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv8i1 = call @llvm.vector.reverse.nxv8i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv4i1 = call @llvm.vector.reverse.nxv4i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %reverse_nxv2i1 = call @llvm.vector.reverse.nxv2i1( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; TYPE_BASED_ONLY-LABEL: 'vector_reverse' -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16i8 = call @llvm.experimental.vector.reverse.nxv16i8( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv32i8 = call @llvm.experimental.vector.reverse.nxv32i8( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2i16 = call @llvm.experimental.vector.reverse.nxv2i16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i16 = call @llvm.experimental.vector.reverse.nxv4i16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8i16 = call @llvm.experimental.vector.reverse.nxv8i16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16i16 = call @llvm.experimental.vector.reverse.nxv16i16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i32 = call @llvm.experimental.vector.reverse.nxv4i32( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8i32 = call @llvm.experimental.vector.reverse.nxv8i32( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2i64 = call @llvm.experimental.vector.reverse.nxv2i64( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i64 = call @llvm.experimental.vector.reverse.nxv4i64( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2f16 = call @llvm.experimental.vector.reverse.nxv2f16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4f16 = call @llvm.experimental.vector.reverse.nxv4f16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8f16 = call @llvm.experimental.vector.reverse.nxv8f16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16f16 = call @llvm.experimental.vector.reverse.nxv16f16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2f32 = call @llvm.experimental.vector.reverse.nxv2f32( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4f32 = call @llvm.experimental.vector.reverse.nxv4f32( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8f32 = call @llvm.experimental.vector.reverse.nxv8f32( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2f64 = call @llvm.experimental.vector.reverse.nxv2f64( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4f64 = call @llvm.experimental.vector.reverse.nxv4f64( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2bf16 = call @llvm.experimental.vector.reverse.nxv2bf16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4bf16 = call @llvm.experimental.vector.reverse.nxv4bf16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8bf16 = call @llvm.experimental.vector.reverse.nxv8bf16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16bf16 = call @llvm.experimental.vector.reverse.nxv16bf16( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16i1 = call @llvm.experimental.vector.reverse.nxv16i1( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8i1 = call @llvm.experimental.vector.reverse.nxv8i1( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i1 = call @llvm.experimental.vector.reverse.nxv4i1( undef) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2i1 = call @llvm.experimental.vector.reverse.nxv2i1( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16i8 = call @llvm.vector.reverse.nxv16i8( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv32i8 = call @llvm.vector.reverse.nxv32i8( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2i16 = call @llvm.vector.reverse.nxv2i16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i16 = call @llvm.vector.reverse.nxv4i16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8i16 = call @llvm.vector.reverse.nxv8i16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16i16 = call @llvm.vector.reverse.nxv16i16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i32 = call @llvm.vector.reverse.nxv4i32( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8i32 = call @llvm.vector.reverse.nxv8i32( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2i64 = call @llvm.vector.reverse.nxv2i64( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i64 = call @llvm.vector.reverse.nxv4i64( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2f16 = call @llvm.vector.reverse.nxv2f16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4f16 = call @llvm.vector.reverse.nxv4f16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8f16 = call @llvm.vector.reverse.nxv8f16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16f16 = call @llvm.vector.reverse.nxv16f16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2f32 = call @llvm.vector.reverse.nxv2f32( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4f32 = call @llvm.vector.reverse.nxv4f32( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8f32 = call @llvm.vector.reverse.nxv8f32( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2f64 = call @llvm.vector.reverse.nxv2f64( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4f64 = call @llvm.vector.reverse.nxv4f64( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2bf16 = call @llvm.vector.reverse.nxv2bf16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4bf16 = call @llvm.vector.reverse.nxv4bf16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8bf16 = call @llvm.vector.reverse.nxv8bf16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16bf16 = call @llvm.vector.reverse.nxv16bf16( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv16i1 = call @llvm.vector.reverse.nxv16i1( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv8i1 = call @llvm.vector.reverse.nxv8i1( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv4i1 = call @llvm.vector.reverse.nxv4i1( undef) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %reverse_nxv2i1 = call @llvm.vector.reverse.nxv2i1( undef) ; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; - %reverse_nxv16i8 = call @llvm.experimental.vector.reverse.nxv16i8( undef) - %reverse_nxv32i8 = call @llvm.experimental.vector.reverse.nxv32i8( undef) - %reverse_nxv2i16 = call @llvm.experimental.vector.reverse.nxv2i16( undef) - %reverse_nxv4i16 = call @llvm.experimental.vector.reverse.nxv4i16( undef) - %reverse_nxv8i16 = call @llvm.experimental.vector.reverse.nxv8i16( undef) - %reverse_nxv16i16 = call @llvm.experimental.vector.reverse.nxv16i16( undef) - %reverse_nxv4i32 = call @llvm.experimental.vector.reverse.nxv4i32( undef) - %reverse_nxv8i32 = call @llvm.experimental.vector.reverse.nxv8i32( undef) - %reverse_nxv2i64 = call @llvm.experimental.vector.reverse.nxv2i64( undef) - %reverse_nxv4i64 = call @llvm.experimental.vector.reverse.nxv4i64( undef) - %reverse_nxv2f16 = call @llvm.experimental.vector.reverse.nxv2f16( undef) - %reverse_nxv4f16 = call @llvm.experimental.vector.reverse.nxv4f16( undef) - %reverse_nxv8f16 = call @llvm.experimental.vector.reverse.nxv8f16( undef) - %reverse_nxv16f16 = call @llvm.experimental.vector.reverse.nxv16f16( undef) - %reverse_nxv2f32 = call @llvm.experimental.vector.reverse.nxv2f32( undef) - %reverse_nxv4f32 = call @llvm.experimental.vector.reverse.nxv4f32( undef) - %reverse_nxv8f32 = call @llvm.experimental.vector.reverse.nxv8f32( undef) - %reverse_nxv2f64 = call @llvm.experimental.vector.reverse.nxv2f64( undef) - %reverse_nxv4f64 = call @llvm.experimental.vector.reverse.nxv4f64( undef) - %reverse_nxv2bf16 = call @llvm.experimental.vector.reverse.nxv2bf16( undef) - %reverse_nxv4bf16 = call @llvm.experimental.vector.reverse.nxv4bf16( undef) - %reverse_nxv8bf16 = call @llvm.experimental.vector.reverse.nxv8bf16( undef) - %reverse_nxv16bf16 = call @llvm.experimental.vector.reverse.nxv16bf16( undef) - %reverse_nxv16i1 = call @llvm.experimental.vector.reverse.nxv16i1( undef) - %reverse_nxv8i1 = call @llvm.experimental.vector.reverse.nxv8i1( undef) - %reverse_nxv4i1 = call @llvm.experimental.vector.reverse.nxv4i1( undef) - %reverse_nxv2i1 = call @llvm.experimental.vector.reverse.nxv2i1( undef) + %reverse_nxv16i8 = call @llvm.vector.reverse.nxv16i8( undef) + %reverse_nxv32i8 = call @llvm.vector.reverse.nxv32i8( undef) + %reverse_nxv2i16 = call @llvm.vector.reverse.nxv2i16( undef) + %reverse_nxv4i16 = call @llvm.vector.reverse.nxv4i16( undef) + %reverse_nxv8i16 = call @llvm.vector.reverse.nxv8i16( undef) + %reverse_nxv16i16 = call @llvm.vector.reverse.nxv16i16( undef) + %reverse_nxv4i32 = call @llvm.vector.reverse.nxv4i32( undef) + %reverse_nxv8i32 = call @llvm.vector.reverse.nxv8i32( undef) + %reverse_nxv2i64 = call @llvm.vector.reverse.nxv2i64( undef) + %reverse_nxv4i64 = call @llvm.vector.reverse.nxv4i64( undef) + %reverse_nxv2f16 = call @llvm.vector.reverse.nxv2f16( undef) + %reverse_nxv4f16 = call @llvm.vector.reverse.nxv4f16( undef) + %reverse_nxv8f16 = call @llvm.vector.reverse.nxv8f16( undef) + %reverse_nxv16f16 = call @llvm.vector.reverse.nxv16f16( undef) + %reverse_nxv2f32 = call @llvm.vector.reverse.nxv2f32( undef) + %reverse_nxv4f32 = call @llvm.vector.reverse.nxv4f32( undef) + %reverse_nxv8f32 = call @llvm.vector.reverse.nxv8f32( undef) + %reverse_nxv2f64 = call @llvm.vector.reverse.nxv2f64( undef) + %reverse_nxv4f64 = call @llvm.vector.reverse.nxv4f64( undef) + %reverse_nxv2bf16 = call @llvm.vector.reverse.nxv2bf16( undef) + %reverse_nxv4bf16 = call @llvm.vector.reverse.nxv4bf16( undef) + %reverse_nxv8bf16 = call @llvm.vector.reverse.nxv8bf16( undef) + %reverse_nxv16bf16 = call @llvm.vector.reverse.nxv16bf16( undef) + %reverse_nxv16i1 = call @llvm.vector.reverse.nxv16i1( undef) + %reverse_nxv8i1 = call @llvm.vector.reverse.nxv8i1( undef) + %reverse_nxv4i1 = call @llvm.vector.reverse.nxv4i1( undef) + %reverse_nxv2i1 = call @llvm.vector.reverse.nxv2i1( undef) ret void } -declare @llvm.experimental.vector.reverse.nxv16i8() -declare @llvm.experimental.vector.reverse.nxv32i8() -declare @llvm.experimental.vector.reverse.nxv2i16() -declare @llvm.experimental.vector.reverse.nxv4i16() -declare @llvm.experimental.vector.reverse.nxv8i16() -declare @llvm.experimental.vector.reverse.nxv16i16() -declare @llvm.experimental.vector.reverse.nxv4i32() -declare @llvm.experimental.vector.reverse.nxv8i32() -declare @llvm.experimental.vector.reverse.nxv2i64() -declare @llvm.experimental.vector.reverse.nxv4i64() -declare @llvm.experimental.vector.reverse.nxv2f16() -declare @llvm.experimental.vector.reverse.nxv4f16() -declare @llvm.experimental.vector.reverse.nxv8f16() -declare @llvm.experimental.vector.reverse.nxv16f16() -declare @llvm.experimental.vector.reverse.nxv2f32() -declare @llvm.experimental.vector.reverse.nxv4f32() -declare @llvm.experimental.vector.reverse.nxv8f32() -declare @llvm.experimental.vector.reverse.nxv2f64() -declare @llvm.experimental.vector.reverse.nxv4f64() -declare @llvm.experimental.vector.reverse.nxv2bf16() -declare @llvm.experimental.vector.reverse.nxv4bf16() -declare @llvm.experimental.vector.reverse.nxv8bf16() -declare @llvm.experimental.vector.reverse.nxv16bf16() -declare @llvm.experimental.vector.reverse.nxv16i1() -declare @llvm.experimental.vector.reverse.nxv8i1() -declare @llvm.experimental.vector.reverse.nxv4i1() -declare @llvm.experimental.vector.reverse.nxv2i1() +declare @llvm.vector.reverse.nxv16i8() +declare @llvm.vector.reverse.nxv32i8() +declare @llvm.vector.reverse.nxv2i16() +declare @llvm.vector.reverse.nxv4i16() +declare @llvm.vector.reverse.nxv8i16() +declare @llvm.vector.reverse.nxv16i16() +declare @llvm.vector.reverse.nxv4i32() +declare @llvm.vector.reverse.nxv8i32() +declare @llvm.vector.reverse.nxv2i64() +declare @llvm.vector.reverse.nxv4i64() +declare @llvm.vector.reverse.nxv2f16() +declare @llvm.vector.reverse.nxv4f16() +declare @llvm.vector.reverse.nxv8f16() +declare @llvm.vector.reverse.nxv16f16() +declare @llvm.vector.reverse.nxv2f32() +declare @llvm.vector.reverse.nxv4f32() +declare @llvm.vector.reverse.nxv8f32() +declare @llvm.vector.reverse.nxv2f64() +declare @llvm.vector.reverse.nxv4f64() +declare @llvm.vector.reverse.nxv2bf16() +declare @llvm.vector.reverse.nxv4bf16() +declare @llvm.vector.reverse.nxv8bf16() +declare @llvm.vector.reverse.nxv16bf16() +declare @llvm.vector.reverse.nxv16i1() +declare @llvm.vector.reverse.nxv8i1() +declare @llvm.vector.reverse.nxv4i1() +declare @llvm.vector.reverse.nxv2i1() define void @unsupported_fp_ops( %vec, i32 %extraarg) { ; CHECK-LABEL: 'unsupported_fp_ops' @@ -450,236 +450,236 @@ declare @llvm.log10.nxv4f32() define void @vector_splice() #0 { ; CHECK-LABEL: 'vector_splice' -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2f16 = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4f16 = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv8f16 = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16f16 = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2f32 = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4f32 = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8f32 = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2f64 = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4f64 = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2bf16 = call @llvm.experimental.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4bf16 = call @llvm.experimental.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv8bf16 = call @llvm.experimental.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16bf16 = call @llvm.experimental.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv16i1 = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8i1 = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4i1 = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2i1 = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv16i8_neg = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv32i8_neg = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i16_neg = call @llvm.experimental.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2i16_neg = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4i16_neg = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8i16_neg = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv16i16_neg = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4i32_neg = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv8i32_neg = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i64_neg = call @llvm.experimental.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2i64_neg = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv4i64_neg = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f16_neg = call @llvm.experimental.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2f16_neg = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4f16_neg = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8f16_neg = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv16f16_neg = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f32_neg = call @llvm.experimental.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2f32_neg = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4f32_neg = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv8f32_neg = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f64_neg = call @llvm.experimental.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2f64_neg = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv4f64_neg = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1bf16_neg = call @llvm.experimental.vector.splice.nxv1bf16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2bf16_neg = call @llvm.experimental.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4bf16_neg = call @llvm.experimental.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8bf16_neg = call @llvm.experimental.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv16bf16_neg = call @llvm.experimental.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv16i1_neg = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv8i1_neg = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv4i1_neg = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv2i1_neg = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i1_neg = call @llvm.experimental.vector.splice.nxv1i1( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2f16 = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4f16 = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv8f16 = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16f16 = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2f32 = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4f32 = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8f32 = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2f64 = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4f64 = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv2bf16 = call @llvm.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv4bf16 = call @llvm.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: %splice_nxv8bf16 = call @llvm.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16bf16 = call @llvm.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv16i1 = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8i1 = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4i1 = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2i1 = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv16i8_neg = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv32i8_neg = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i16_neg = call @llvm.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2i16_neg = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4i16_neg = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8i16_neg = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv16i16_neg = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4i32_neg = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv8i32_neg = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i64_neg = call @llvm.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2i64_neg = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv4i64_neg = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f16_neg = call @llvm.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2f16_neg = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4f16_neg = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8f16_neg = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv16f16_neg = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f32_neg = call @llvm.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2f32_neg = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4f32_neg = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv8f32_neg = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f64_neg = call @llvm.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2f64_neg = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv4f64_neg = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1bf16_neg = call @llvm.vector.splice.nxv1bf16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv2bf16_neg = call @llvm.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv4bf16_neg = call @llvm.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 3 for instruction: %splice_nxv8bf16_neg = call @llvm.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %splice_nxv16bf16_neg = call @llvm.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv16i1_neg = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv8i1_neg = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv4i1_neg = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 5 for instruction: %splice_nxv2i1_neg = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i1_neg = call @llvm.vector.splice.nxv1i1( zeroinitializer, zeroinitializer, i32 -1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; TYPE_BASED_ONLY-LABEL: 'vector_splice' -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f16 = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f16 = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f16 = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16f16 = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f32 = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f32 = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f32 = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f64 = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f64 = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2bf16 = call @llvm.experimental.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4bf16 = call @llvm.experimental.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8bf16 = call @llvm.experimental.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16bf16 = call @llvm.experimental.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i1 = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i1 = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i1 = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i1 = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i8_neg = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv32i8_neg = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i16_neg = call @llvm.experimental.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i16_neg = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i16_neg = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i16_neg = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i16_neg = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i32_neg = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i32_neg = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i64_neg = call @llvm.experimental.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i64_neg = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i64_neg = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f16_neg = call @llvm.experimental.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f16_neg = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f16_neg = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f16_neg = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16f16_neg = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f32_neg = call @llvm.experimental.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f32_neg = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f32_neg = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f32_neg = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f64_neg = call @llvm.experimental.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f64_neg = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f64_neg = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1bf16_neg = call @llvm.experimental.vector.splice.nxv1bf16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2bf16_neg = call @llvm.experimental.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4bf16_neg = call @llvm.experimental.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8bf16_neg = call @llvm.experimental.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16bf16_neg = call @llvm.experimental.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i1_neg = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i1_neg = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i1_neg = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i1_neg = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 -1) -; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i1_neg = call @llvm.experimental.vector.splice.nxv1i1( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f16 = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f16 = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f16 = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16f16 = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f32 = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f32 = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f32 = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f64 = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f64 = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2bf16 = call @llvm.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4bf16 = call @llvm.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8bf16 = call @llvm.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16bf16 = call @llvm.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i1 = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i1 = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i1 = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i1 = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i8_neg = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv32i8_neg = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i16_neg = call @llvm.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i16_neg = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i16_neg = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i16_neg = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i16_neg = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i32_neg = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i32_neg = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i64_neg = call @llvm.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i64_neg = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i64_neg = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f16_neg = call @llvm.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f16_neg = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f16_neg = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f16_neg = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16f16_neg = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f32_neg = call @llvm.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f32_neg = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f32_neg = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8f32_neg = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1f64_neg = call @llvm.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2f64_neg = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4f64_neg = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1bf16_neg = call @llvm.vector.splice.nxv1bf16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2bf16_neg = call @llvm.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4bf16_neg = call @llvm.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8bf16_neg = call @llvm.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16bf16_neg = call @llvm.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv16i1_neg = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv8i1_neg = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv4i1_neg = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv2i1_neg = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 -1) +; TYPE_BASED_ONLY-NEXT: Cost Model: Invalid cost for instruction: %splice_nxv1i1_neg = call @llvm.vector.splice.nxv1i1( zeroinitializer, zeroinitializer, i32 -1) ; TYPE_BASED_ONLY-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; - %splice_nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2f16 = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4f16 = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8f16 = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv16f16 = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2f32 = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4f32 = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8f32 = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2f64 = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4f64 = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2bf16 = call @llvm.experimental.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4bf16 = call @llvm.experimental.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8bf16 = call @llvm.experimental.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv16bf16 = call @llvm.experimental.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv16i1 = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8i1 = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i1 = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2i1 = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2f16 = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4f16 = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8f16 = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16f16 = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2f32 = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4f32 = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8f32 = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2f64 = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4f64 = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2bf16 = call @llvm.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4bf16 = call @llvm.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8bf16 = call @llvm.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16bf16 = call @llvm.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16i1 = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8i1 = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i1 = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2i1 = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) ;; negative Index - %splice_nxv16i8_neg = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv32i8_neg = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv1i16_neg = call @llvm.experimental.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv2i16_neg = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4i16_neg = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv8i16_neg = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv16i16_neg = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4i32_neg = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv8i32_neg = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv1i64_neg= call @llvm.experimental.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv2i64_neg= call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4i64_neg = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv1f16_neg = call @llvm.experimental.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv2f16_neg = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4f16_neg = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv8f16_neg = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv16f16_neg = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv1f32_neg = call @llvm.experimental.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv2f32_neg = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4f32_neg = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv8f32_neg = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv1f64_neg = call @llvm.experimental.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv2f64_neg = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4f64_neg = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv1bf16_neg = call @llvm.experimental.vector.splice.nxv1bf16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv2bf16_neg = call @llvm.experimental.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4bf16_neg = call @llvm.experimental.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv8bf16_neg = call @llvm.experimental.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv16bf16_neg = call @llvm.experimental.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv16i1_neg = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv8i1_neg = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv4i1_neg = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv2i1_neg = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 -1) - %splice_nxv1i1_neg = call @llvm.experimental.vector.splice.nxv1i1( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv16i8_neg = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv32i8_neg = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv1i16_neg = call @llvm.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv2i16_neg = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4i16_neg = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv8i16_neg = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv16i16_neg = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4i32_neg = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv8i32_neg = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv1i64_neg= call @llvm.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv2i64_neg= call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4i64_neg = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv1f16_neg = call @llvm.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv2f16_neg = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4f16_neg = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv8f16_neg = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv16f16_neg = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv1f32_neg = call @llvm.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv2f32_neg = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4f32_neg = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv8f32_neg = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv1f64_neg = call @llvm.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv2f64_neg = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4f64_neg = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv1bf16_neg = call @llvm.vector.splice.nxv1bf16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv2bf16_neg = call @llvm.vector.splice.nxv2bf16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4bf16_neg = call @llvm.vector.splice.nxv4bf16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv8bf16_neg = call @llvm.vector.splice.nxv8bf16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv16bf16_neg = call @llvm.vector.splice.nxv16bf16( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv16i1_neg = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv8i1_neg = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv4i1_neg = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv2i1_neg = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 -1) + %splice_nxv1i1_neg = call @llvm.vector.splice.nxv1i1( zeroinitializer, zeroinitializer, i32 -1) ret void } -declare @llvm.experimental.vector.splice.nxv1i1(, , i32) -declare @llvm.experimental.vector.splice.nxv2i1(, , i32) -declare @llvm.experimental.vector.splice.nxv4i1(, , i32) -declare @llvm.experimental.vector.splice.nxv8i1(, , i32) -declare @llvm.experimental.vector.splice.nxv16i1(, , i32) -declare @llvm.experimental.vector.splice.nxv1i8(, , i32) -declare @llvm.experimental.vector.splice.nxv2i8(, , i32) -declare @llvm.experimental.vector.splice.nxv16i8(, , i32) -declare @llvm.experimental.vector.splice.nxv32i8(, , i32) -declare @llvm.experimental.vector.splice.nxv1i16(, , i32) -declare @llvm.experimental.vector.splice.nxv2i16(, , i32) -declare @llvm.experimental.vector.splice.nxv4i16(, , i32) -declare @llvm.experimental.vector.splice.nxv8i16(, , i32) -declare @llvm.experimental.vector.splice.nxv16i16(, , i32) -declare @llvm.experimental.vector.splice.nxv4i32(, , i32) -declare @llvm.experimental.vector.splice.nxv8i32(, , i32) -declare @llvm.experimental.vector.splice.nxv1i64(, , i32) -declare @llvm.experimental.vector.splice.nxv2i64(, , i32) -declare @llvm.experimental.vector.splice.nxv4i64(, , i32) -declare @llvm.experimental.vector.splice.nxv1f16(, , i32) -declare @llvm.experimental.vector.splice.nxv2f16(, , i32) -declare @llvm.experimental.vector.splice.nxv4f16(, , i32) -declare @llvm.experimental.vector.splice.nxv8f16(, , i32) -declare @llvm.experimental.vector.splice.nxv16f16(, , i32) -declare @llvm.experimental.vector.splice.nxv1bf16(, , i32) -declare @llvm.experimental.vector.splice.nxv2bf16(, , i32) -declare @llvm.experimental.vector.splice.nxv4bf16(, , i32) -declare @llvm.experimental.vector.splice.nxv8bf16(, , i32) -declare @llvm.experimental.vector.splice.nxv16bf16(, , i32) -declare @llvm.experimental.vector.splice.nxv1f32(, , i32) -declare @llvm.experimental.vector.splice.nxv2f32(, , i32) -declare @llvm.experimental.vector.splice.nxv4f32(, , i32) -declare @llvm.experimental.vector.splice.nxv8f32(, , i32) -declare @llvm.experimental.vector.splice.nxv16f32(, , i32) -declare @llvm.experimental.vector.splice.nxv1f64(, , i32) -declare @llvm.experimental.vector.splice.nxv2f64(, , i32) -declare @llvm.experimental.vector.splice.nxv4f64(, , i32) +declare @llvm.vector.splice.nxv1i1(, , i32) +declare @llvm.vector.splice.nxv2i1(, , i32) +declare @llvm.vector.splice.nxv4i1(, , i32) +declare @llvm.vector.splice.nxv8i1(, , i32) +declare @llvm.vector.splice.nxv16i1(, , i32) +declare @llvm.vector.splice.nxv1i8(, , i32) +declare @llvm.vector.splice.nxv2i8(, , i32) +declare @llvm.vector.splice.nxv16i8(, , i32) +declare @llvm.vector.splice.nxv32i8(, , i32) +declare @llvm.vector.splice.nxv1i16(, , i32) +declare @llvm.vector.splice.nxv2i16(, , i32) +declare @llvm.vector.splice.nxv4i16(, , i32) +declare @llvm.vector.splice.nxv8i16(, , i32) +declare @llvm.vector.splice.nxv16i16(, , i32) +declare @llvm.vector.splice.nxv4i32(, , i32) +declare @llvm.vector.splice.nxv8i32(, , i32) +declare @llvm.vector.splice.nxv1i64(, , i32) +declare @llvm.vector.splice.nxv2i64(, , i32) +declare @llvm.vector.splice.nxv4i64(, , i32) +declare @llvm.vector.splice.nxv1f16(, , i32) +declare @llvm.vector.splice.nxv2f16(, , i32) +declare @llvm.vector.splice.nxv4f16(, , i32) +declare @llvm.vector.splice.nxv8f16(, , i32) +declare @llvm.vector.splice.nxv16f16(, , i32) +declare @llvm.vector.splice.nxv1bf16(, , i32) +declare @llvm.vector.splice.nxv2bf16(, , i32) +declare @llvm.vector.splice.nxv4bf16(, , i32) +declare @llvm.vector.splice.nxv8bf16(, , i32) +declare @llvm.vector.splice.nxv16bf16(, , i32) +declare @llvm.vector.splice.nxv1f32(, , i32) +declare @llvm.vector.splice.nxv2f32(, , i32) +declare @llvm.vector.splice.nxv4f32(, , i32) +declare @llvm.vector.splice.nxv8f32(, , i32) +declare @llvm.vector.splice.nxv16f32(, , i32) +declare @llvm.vector.splice.nxv1f64(, , i32) +declare @llvm.vector.splice.nxv2f64(, , i32) +declare @llvm.vector.splice.nxv4f64(, , i32) define void @get_lane_mask() #0 { ; CHECK-LABEL: 'get_lane_mask' diff --git a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll index 7cc7cff0e6e8..e068ab638d3a 100644 --- a/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll +++ b/llvm/test/Analysis/CostModel/RISCV/rvv-shuffle.ll @@ -78,148 +78,148 @@ declare @llvm.vector.insert.nxv16i32.nxv4i32( @llvm.experimental.vector.reverse.nxv16i8( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv32i8 = call @llvm.experimental.vector.reverse.nxv32i8( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i16 = call @llvm.experimental.vector.reverse.nxv2i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i16 = call @llvm.experimental.vector.reverse.nxv4i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %reverse_nxv8i16 = call @llvm.experimental.vector.reverse.nxv8i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv16i16 = call @llvm.experimental.vector.reverse.nxv16i16( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %reverse_nxv4i32 = call @llvm.experimental.vector.reverse.nxv4i32( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv8i32 = call @llvm.experimental.vector.reverse.nxv8i32( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %reverse_nxv2i64 = call @llvm.experimental.vector.reverse.nxv2i64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv4i64 = call @llvm.experimental.vector.reverse.nxv4i64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %reverse_nxv8i64 = call @llvm.experimental.vector.reverse.nxv8i64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 166 for instruction: %reverse_nxv16i64 = call @llvm.experimental.vector.reverse.nxv16i64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 332 for instruction: %reverse_nxv32i64 = call @llvm.experimental.vector.reverse.nxv32i64( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %reverse_nxv16i1 = call @llvm.experimental.vector.reverse.nxv16i1( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv8i1 = call @llvm.experimental.vector.reverse.nxv8i1( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv4i1 = call @llvm.experimental.vector.reverse.nxv4i1( undef) -; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv2i1 = call @llvm.experimental.vector.reverse.nxv2i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %reverse_nxv16i8 = call @llvm.vector.reverse.nxv16i8( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv32i8 = call @llvm.vector.reverse.nxv32i8( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i16 = call @llvm.vector.reverse.nxv2i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i16 = call @llvm.vector.reverse.nxv4i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %reverse_nxv8i16 = call @llvm.vector.reverse.nxv8i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv16i16 = call @llvm.vector.reverse.nxv16i16( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %reverse_nxv4i32 = call @llvm.vector.reverse.nxv4i32( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv8i32 = call @llvm.vector.reverse.nxv8i32( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 11 for instruction: %reverse_nxv2i64 = call @llvm.vector.reverse.nxv2i64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 27 for instruction: %reverse_nxv4i64 = call @llvm.vector.reverse.nxv4i64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 83 for instruction: %reverse_nxv8i64 = call @llvm.vector.reverse.nxv8i64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 166 for instruction: %reverse_nxv16i64 = call @llvm.vector.reverse.nxv16i64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 332 for instruction: %reverse_nxv32i64 = call @llvm.vector.reverse.nxv32i64( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 14 for instruction: %reverse_nxv16i1 = call @llvm.vector.reverse.nxv16i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv8i1 = call @llvm.vector.reverse.nxv8i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv4i1 = call @llvm.vector.reverse.nxv4i1( undef) +; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv2i1 = call @llvm.vector.reverse.nxv2i1( undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'vector_reverse' -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv16i8 = call @llvm.experimental.vector.reverse.nxv16i8( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv32i8 = call @llvm.experimental.vector.reverse.nxv32i8( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i16 = call @llvm.experimental.vector.reverse.nxv2i16( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i16 = call @llvm.experimental.vector.reverse.nxv4i16( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i16 = call @llvm.experimental.vector.reverse.nxv8i16( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv16i16 = call @llvm.experimental.vector.reverse.nxv16i16( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i32 = call @llvm.experimental.vector.reverse.nxv4i32( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i32 = call @llvm.experimental.vector.reverse.nxv8i32( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i64 = call @llvm.experimental.vector.reverse.nxv2i64( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i64 = call @llvm.experimental.vector.reverse.nxv4i64( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i64 = call @llvm.experimental.vector.reverse.nxv8i64( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %reverse_nxv16i64 = call @llvm.experimental.vector.reverse.nxv16i64( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %reverse_nxv32i64 = call @llvm.experimental.vector.reverse.nxv32i64( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv16i1 = call @llvm.experimental.vector.reverse.nxv16i1( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv8i1 = call @llvm.experimental.vector.reverse.nxv8i1( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv4i1 = call @llvm.experimental.vector.reverse.nxv4i1( undef) -; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv2i1 = call @llvm.experimental.vector.reverse.nxv2i1( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv16i8 = call @llvm.vector.reverse.nxv16i8( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv32i8 = call @llvm.vector.reverse.nxv32i8( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i16 = call @llvm.vector.reverse.nxv2i16( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i16 = call @llvm.vector.reverse.nxv4i16( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i16 = call @llvm.vector.reverse.nxv8i16( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv16i16 = call @llvm.vector.reverse.nxv16i16( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i32 = call @llvm.vector.reverse.nxv4i32( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i32 = call @llvm.vector.reverse.nxv8i32( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv2i64 = call @llvm.vector.reverse.nxv2i64( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv4i64 = call @llvm.vector.reverse.nxv4i64( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 6 for instruction: %reverse_nxv8i64 = call @llvm.vector.reverse.nxv8i64( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 12 for instruction: %reverse_nxv16i64 = call @llvm.vector.reverse.nxv16i64( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 24 for instruction: %reverse_nxv32i64 = call @llvm.vector.reverse.nxv32i64( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv16i1 = call @llvm.vector.reverse.nxv16i1( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv8i1 = call @llvm.vector.reverse.nxv8i1( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv4i1 = call @llvm.vector.reverse.nxv4i1( undef) +; SIZE-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %reverse_nxv2i1 = call @llvm.vector.reverse.nxv2i1( undef) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; - %reverse_nxv16i8 = call @llvm.experimental.vector.reverse.nxv16i8( undef) - %reverse_nxv32i8 = call @llvm.experimental.vector.reverse.nxv32i8( undef) - %reverse_nxv2i16 = call @llvm.experimental.vector.reverse.nxv2i16( undef) - %reverse_nxv4i16 = call @llvm.experimental.vector.reverse.nxv4i16( undef) - %reverse_nxv8i16 = call @llvm.experimental.vector.reverse.nxv8i16( undef) - %reverse_nxv16i16 = call @llvm.experimental.vector.reverse.nxv16i16( undef) - %reverse_nxv4i32 = call @llvm.experimental.vector.reverse.nxv4i32( undef) - %reverse_nxv8i32 = call @llvm.experimental.vector.reverse.nxv8i32( undef) - %reverse_nxv2i64 = call @llvm.experimental.vector.reverse.nxv2i64( undef) - %reverse_nxv4i64 = call @llvm.experimental.vector.reverse.nxv4i64( undef) - %reverse_nxv8i64 = call @llvm.experimental.vector.reverse.nxv8i64( undef) - %reverse_nxv16i64 = call @llvm.experimental.vector.reverse.nxv16i64( undef) - %reverse_nxv32i64 = call @llvm.experimental.vector.reverse.nxv32i64( undef) - %reverse_nxv16i1 = call @llvm.experimental.vector.reverse.nxv16i1( undef) - %reverse_nxv8i1 = call @llvm.experimental.vector.reverse.nxv8i1( undef) - %reverse_nxv4i1 = call @llvm.experimental.vector.reverse.nxv4i1( undef) - %reverse_nxv2i1 = call @llvm.experimental.vector.reverse.nxv2i1( undef) + %reverse_nxv16i8 = call @llvm.vector.reverse.nxv16i8( undef) + %reverse_nxv32i8 = call @llvm.vector.reverse.nxv32i8( undef) + %reverse_nxv2i16 = call @llvm.vector.reverse.nxv2i16( undef) + %reverse_nxv4i16 = call @llvm.vector.reverse.nxv4i16( undef) + %reverse_nxv8i16 = call @llvm.vector.reverse.nxv8i16( undef) + %reverse_nxv16i16 = call @llvm.vector.reverse.nxv16i16( undef) + %reverse_nxv4i32 = call @llvm.vector.reverse.nxv4i32( undef) + %reverse_nxv8i32 = call @llvm.vector.reverse.nxv8i32( undef) + %reverse_nxv2i64 = call @llvm.vector.reverse.nxv2i64( undef) + %reverse_nxv4i64 = call @llvm.vector.reverse.nxv4i64( undef) + %reverse_nxv8i64 = call @llvm.vector.reverse.nxv8i64( undef) + %reverse_nxv16i64 = call @llvm.vector.reverse.nxv16i64( undef) + %reverse_nxv32i64 = call @llvm.vector.reverse.nxv32i64( undef) + %reverse_nxv16i1 = call @llvm.vector.reverse.nxv16i1( undef) + %reverse_nxv8i1 = call @llvm.vector.reverse.nxv8i1( undef) + %reverse_nxv4i1 = call @llvm.vector.reverse.nxv4i1( undef) + %reverse_nxv2i1 = call @llvm.vector.reverse.nxv2i1( undef) ret void } -declare @llvm.experimental.vector.reverse.nxv16i8() -declare @llvm.experimental.vector.reverse.nxv32i8() -declare @llvm.experimental.vector.reverse.nxv2i16() -declare @llvm.experimental.vector.reverse.nxv4i16() -declare @llvm.experimental.vector.reverse.nxv8i16() -declare @llvm.experimental.vector.reverse.nxv16i16() -declare @llvm.experimental.vector.reverse.nxv4i32() -declare @llvm.experimental.vector.reverse.nxv8i32() -declare @llvm.experimental.vector.reverse.nxv2i64() -declare @llvm.experimental.vector.reverse.nxv4i64() -declare @llvm.experimental.vector.reverse.nxv8i64() -declare @llvm.experimental.vector.reverse.nxv16i64() -declare @llvm.experimental.vector.reverse.nxv32i64() -declare @llvm.experimental.vector.reverse.nxv16i1() -declare @llvm.experimental.vector.reverse.nxv8i1() -declare @llvm.experimental.vector.reverse.nxv4i1() -declare @llvm.experimental.vector.reverse.nxv2i1() +declare @llvm.vector.reverse.nxv16i8() +declare @llvm.vector.reverse.nxv32i8() +declare @llvm.vector.reverse.nxv2i16() +declare @llvm.vector.reverse.nxv4i16() +declare @llvm.vector.reverse.nxv8i16() +declare @llvm.vector.reverse.nxv16i16() +declare @llvm.vector.reverse.nxv4i32() +declare @llvm.vector.reverse.nxv8i32() +declare @llvm.vector.reverse.nxv2i64() +declare @llvm.vector.reverse.nxv4i64() +declare @llvm.vector.reverse.nxv8i64() +declare @llvm.vector.reverse.nxv16i64() +declare @llvm.vector.reverse.nxv32i64() +declare @llvm.vector.reverse.nxv16i1() +declare @llvm.vector.reverse.nxv8i1() +declare @llvm.vector.reverse.nxv4i1() +declare @llvm.vector.reverse.nxv2i1() define void @vector_splice() { ; CHECK-LABEL: 'vector_splice' -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv16i1 = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i1 = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i1 = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i1 = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice_nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice_nxv16i1 = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i1 = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i1 = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i1 = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'vector_splice' -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i1 = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i1 = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i1 = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i1 = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv16i1 = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv8i1 = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv4i1 = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice_nxv2i1 = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; - %splice_nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv16i1 = call @llvm.experimental.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv8i1 = call @llvm.experimental.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv4i1 = call @llvm.experimental.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) - %splice_nxv2i1 = call @llvm.experimental.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv16i1 = call @llvm.vector.splice.nxv16i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv8i1 = call @llvm.vector.splice.nxv8i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv4i1 = call @llvm.vector.splice.nxv4i1( zeroinitializer, zeroinitializer, i32 1) + %splice_nxv2i1 = call @llvm.vector.splice.nxv2i1( zeroinitializer, zeroinitializer, i32 1) ret void } -declare @llvm.experimental.vector.splice.nxv2i1(, , i32) -declare @llvm.experimental.vector.splice.nxv4i1(, , i32) -declare @llvm.experimental.vector.splice.nxv8i1(, , i32) -declare @llvm.experimental.vector.splice.nxv16i1(, , i32) -declare @llvm.experimental.vector.splice.nxv2i8(, , i32) -declare @llvm.experimental.vector.splice.nxv16i8(, , i32) -declare @llvm.experimental.vector.splice.nxv32i8(, , i32) -declare @llvm.experimental.vector.splice.nxv2i16(, , i32) -declare @llvm.experimental.vector.splice.nxv4i16(, , i32) -declare @llvm.experimental.vector.splice.nxv8i16(, , i32) -declare @llvm.experimental.vector.splice.nxv16i16(, , i32) -declare @llvm.experimental.vector.splice.nxv4i32(, , i32) -declare @llvm.experimental.vector.splice.nxv8i32(, , i32) -declare @llvm.experimental.vector.splice.nxv2i64(, , i32) -declare @llvm.experimental.vector.splice.nxv4i64(, , i32) +declare @llvm.vector.splice.nxv2i1(, , i32) +declare @llvm.vector.splice.nxv4i1(, , i32) +declare @llvm.vector.splice.nxv8i1(, , i32) +declare @llvm.vector.splice.nxv16i1(, , i32) +declare @llvm.vector.splice.nxv2i8(, , i32) +declare @llvm.vector.splice.nxv16i8(, , i32) +declare @llvm.vector.splice.nxv32i8(, , i32) +declare @llvm.vector.splice.nxv2i16(, , i32) +declare @llvm.vector.splice.nxv4i16(, , i32) +declare @llvm.vector.splice.nxv8i16(, , i32) +declare @llvm.vector.splice.nxv16i16(, , i32) +declare @llvm.vector.splice.nxv4i32(, , i32) +declare @llvm.vector.splice.nxv8i32(, , i32) +declare @llvm.vector.splice.nxv2i64(, , i32) +declare @llvm.vector.splice.nxv4i64(, , i32) diff --git a/llvm/test/Analysis/CostModel/RISCV/splice.ll b/llvm/test/Analysis/CostModel/RISCV/splice.ll index c70c879dba5a..9acccef9c4f6 100644 --- a/llvm/test/Analysis/CostModel/RISCV/splice.ll +++ b/llvm/test/Analysis/CostModel/RISCV/splice.ll @@ -4,220 +4,220 @@ define void @vector_splice() { ; CHECK-LABEL: 'vector_splice' -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.experimental.vector.splice.nxv1i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.experimental.vector.splice.nxv2i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.experimental.vector.splice.nxv4i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.experimental.vector.splice.nxv8i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i8 = call @llvm.experimental.vector.splice.nxv64i8( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.experimental.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32i16 = call @llvm.experimental.vector.splice.nxv32i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64i16 = call @llvm.experimental.vector.splice.nxv64i16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.experimental.vector.splice.nxv1i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.experimental.vector.splice.nxv2i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16i32 = call @llvm.experimental.vector.splice.nxv16i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32i32 = call @llvm.experimental.vector.splice.nxv32i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64i32 = call @llvm.experimental.vector.splice.nxv64i32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.experimental.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8i64 = call @llvm.experimental.vector.splice.nxv8i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16i64 = call @llvm.experimental.vector.splice.nxv16i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32i64 = call @llvm.experimental.vector.splice.nxv32i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64i64 = call @llvm.experimental.vector.splice.nxv64i64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.experimental.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8f16 = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16f16 = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32f16 = call @llvm.experimental.vector.splice.nxv32f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64f16 = call @llvm.experimental.vector.splice.nxv64f16( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.experimental.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4f32 = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8f32 = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16f32 = call @llvm.experimental.vector.splice.nxv16f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32f32 = call @llvm.experimental.vector.splice.nxv32f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64f32 = call @llvm.experimental.vector.splice.nxv64f32( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.experimental.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2f64 = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4f64 = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8f64 = call @llvm.experimental.vector.splice.nxv8f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16f64 = call @llvm.experimental.vector.splice.nxv16f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32f64 = call @llvm.experimental.vector.splice.nxv32f64( zeroinitializer, zeroinitializer, i32 -1) -; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64f64 = call @llvm.experimental.vector.splice.nxv64f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.vector.splice.nxv1i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.vector.splice.nxv2i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.vector.splice.nxv4i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.vector.splice.nxv8i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i8 = call @llvm.vector.splice.nxv64i8( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32i16 = call @llvm.vector.splice.nxv32i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64i16 = call @llvm.vector.splice.nxv64i16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.vector.splice.nxv1i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.vector.splice.nxv2i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16i32 = call @llvm.vector.splice.nxv16i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32i32 = call @llvm.vector.splice.nxv32i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64i32 = call @llvm.vector.splice.nxv64i32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8i64 = call @llvm.vector.splice.nxv8i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16i64 = call @llvm.vector.splice.nxv16i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32i64 = call @llvm.vector.splice.nxv32i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64i64 = call @llvm.vector.splice.nxv64i64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv8f16 = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv16f16 = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv32f16 = call @llvm.vector.splice.nxv32f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv64f16 = call @llvm.vector.splice.nxv64f16( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv4f32 = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv8f32 = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv16f32 = call @llvm.vector.splice.nxv16f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv32f32 = call @llvm.vector.splice.nxv32f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv64f32 = call @llvm.vector.splice.nxv64f32( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv2f64 = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv4f64 = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv8f64 = call @llvm.vector.splice.nxv8f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 32 for instruction: %splice.nxv16f64 = call @llvm.vector.splice.nxv16f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 64 for instruction: %splice.nxv32f64 = call @llvm.vector.splice.nxv32f64( zeroinitializer, zeroinitializer, i32 -1) +; CHECK-NEXT: Cost Model: Found an estimated cost of 128 for instruction: %splice.nxv64f64 = call @llvm.vector.splice.nxv64f64( zeroinitializer, zeroinitializer, i32 -1) ; CHECK-NEXT: Cost Model: Found an estimated cost of 0 for instruction: ret void ; ; SIZE-LABEL: 'vector_splice' -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.experimental.vector.splice.nxv1i8( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.experimental.vector.splice.nxv2i8( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.experimental.vector.splice.nxv4i8( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.experimental.vector.splice.nxv8i8( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv64i8 = call @llvm.experimental.vector.splice.nxv64i8( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.experimental.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i16 = call @llvm.experimental.vector.splice.nxv32i16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64i16 = call @llvm.experimental.vector.splice.nxv64i16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.experimental.vector.splice.nxv1i32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.experimental.vector.splice.nxv2i32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i32 = call @llvm.experimental.vector.splice.nxv16i32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32i32 = call @llvm.experimental.vector.splice.nxv32i32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64i32 = call @llvm.experimental.vector.splice.nxv64i32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.experimental.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i64 = call @llvm.experimental.vector.splice.nxv8i64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i64 = call @llvm.experimental.vector.splice.nxv16i64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i64 = call @llvm.experimental.vector.splice.nxv32i64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i64 = call @llvm.experimental.vector.splice.nxv64i64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.experimental.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f16 = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f16 = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32f16 = call @llvm.experimental.vector.splice.nxv32f16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64f16 = call @llvm.experimental.vector.splice.nxv64f16( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.experimental.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f32 = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f32 = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f32 = call @llvm.experimental.vector.splice.nxv16f32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32f32 = call @llvm.experimental.vector.splice.nxv32f32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64f32 = call @llvm.experimental.vector.splice.nxv64f32( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.experimental.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f64 = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f64 = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f64 = call @llvm.experimental.vector.splice.nxv8f64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16f64 = call @llvm.experimental.vector.splice.nxv16f64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32f64 = call @llvm.experimental.vector.splice.nxv32f64( zeroinitializer, zeroinitializer, i32 -1) -; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64f64 = call @llvm.experimental.vector.splice.nxv64f64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i8 = call @llvm.vector.splice.nxv1i8( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i8 = call @llvm.vector.splice.nxv2i8( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i8 = call @llvm.vector.splice.nxv4i8( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i8 = call @llvm.vector.splice.nxv8i8( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv64i8 = call @llvm.vector.splice.nxv64i8( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i16 = call @llvm.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32i16 = call @llvm.vector.splice.nxv32i16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64i16 = call @llvm.vector.splice.nxv64i16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i32 = call @llvm.vector.splice.nxv1i32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i32 = call @llvm.vector.splice.nxv2i32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16i32 = call @llvm.vector.splice.nxv16i32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32i32 = call @llvm.vector.splice.nxv32i32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64i32 = call @llvm.vector.splice.nxv64i32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1i64 = call @llvm.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8i64 = call @llvm.vector.splice.nxv8i64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16i64 = call @llvm.vector.splice.nxv16i64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32i64 = call @llvm.vector.splice.nxv32i64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64i64 = call @llvm.vector.splice.nxv64i64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f16 = call @llvm.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f16 = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f16 = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f16 = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f16 = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv32f16 = call @llvm.vector.splice.nxv32f16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv64f16 = call @llvm.vector.splice.nxv64f16( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f32 = call @llvm.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f32 = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f32 = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f32 = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv16f32 = call @llvm.vector.splice.nxv16f32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv32f32 = call @llvm.vector.splice.nxv32f32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv64f32 = call @llvm.vector.splice.nxv64f32( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv1f64 = call @llvm.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv2f64 = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv4f64 = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 2 for instruction: %splice.nxv8f64 = call @llvm.vector.splice.nxv8f64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 4 for instruction: %splice.nxv16f64 = call @llvm.vector.splice.nxv16f64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 8 for instruction: %splice.nxv32f64 = call @llvm.vector.splice.nxv32f64( zeroinitializer, zeroinitializer, i32 -1) +; SIZE-NEXT: Cost Model: Found an estimated cost of 16 for instruction: %splice.nxv64f64 = call @llvm.vector.splice.nxv64f64( zeroinitializer, zeroinitializer, i32 -1) ; SIZE-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; - %splice.nxv1i8 = call @llvm.experimental.vector.splice.nxv1i8( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv2i8 = call @llvm.experimental.vector.splice.nxv2i8( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv4i8 = call @llvm.experimental.vector.splice.nxv4i8( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv8i8 = call @llvm.experimental.vector.splice.nxv8i8( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv16i8 = call @llvm.experimental.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv32i8 = call @llvm.experimental.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv64i8 = call @llvm.experimental.vector.splice.nxv64i8( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv1i8 = call @llvm.vector.splice.nxv1i8( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv2i8 = call @llvm.vector.splice.nxv2i8( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv4i8 = call @llvm.vector.splice.nxv4i8( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv8i8 = call @llvm.vector.splice.nxv8i8( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv16i8 = call @llvm.vector.splice.nxv16i8( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv32i8 = call @llvm.vector.splice.nxv32i8( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv64i8 = call @llvm.vector.splice.nxv64i8( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv1i16 = call @llvm.experimental.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv2i16 = call @llvm.experimental.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv4i16 = call @llvm.experimental.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv8i16 = call @llvm.experimental.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv16i16 = call @llvm.experimental.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv32i16 = call @llvm.experimental.vector.splice.nxv32i16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv64i16 = call @llvm.experimental.vector.splice.nxv64i16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv1i16 = call @llvm.vector.splice.nxv1i16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv2i16 = call @llvm.vector.splice.nxv2i16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv4i16 = call @llvm.vector.splice.nxv4i16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv8i16 = call @llvm.vector.splice.nxv8i16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv16i16 = call @llvm.vector.splice.nxv16i16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv32i16 = call @llvm.vector.splice.nxv32i16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv64i16 = call @llvm.vector.splice.nxv64i16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv1i32 = call @llvm.experimental.vector.splice.nxv1i32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv2i32 = call @llvm.experimental.vector.splice.nxv2i32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv4i32 = call @llvm.experimental.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv8i32 = call @llvm.experimental.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv16i32 = call @llvm.experimental.vector.splice.nxv16i32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv32i32 = call @llvm.experimental.vector.splice.nxv32i32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv64i32 = call @llvm.experimental.vector.splice.nxv64i32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv1i32 = call @llvm.vector.splice.nxv1i32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv2i32 = call @llvm.vector.splice.nxv2i32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv4i32 = call @llvm.vector.splice.nxv4i32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv8i32 = call @llvm.vector.splice.nxv8i32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv16i32 = call @llvm.vector.splice.nxv16i32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv32i32 = call @llvm.vector.splice.nxv32i32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv64i32 = call @llvm.vector.splice.nxv64i32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv1i64 = call @llvm.experimental.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv2i64 = call @llvm.experimental.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv4i64 = call @llvm.experimental.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv8i64 = call @llvm.experimental.vector.splice.nxv8i64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv16i64 = call @llvm.experimental.vector.splice.nxv16i64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv32i64 = call @llvm.experimental.vector.splice.nxv32i64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv64i64 = call @llvm.experimental.vector.splice.nxv64i64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv1i64 = call @llvm.vector.splice.nxv1i64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv2i64 = call @llvm.vector.splice.nxv2i64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv4i64 = call @llvm.vector.splice.nxv4i64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv8i64 = call @llvm.vector.splice.nxv8i64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv16i64 = call @llvm.vector.splice.nxv16i64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv32i64 = call @llvm.vector.splice.nxv32i64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv64i64 = call @llvm.vector.splice.nxv64i64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv1f16 = call @llvm.experimental.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv2f16 = call @llvm.experimental.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv4f16 = call @llvm.experimental.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv8f16 = call @llvm.experimental.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv16f16 = call @llvm.experimental.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv32f16 = call @llvm.experimental.vector.splice.nxv32f16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv64f16 = call @llvm.experimental.vector.splice.nxv64f16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv1f16 = call @llvm.vector.splice.nxv1f16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv2f16 = call @llvm.vector.splice.nxv2f16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv4f16 = call @llvm.vector.splice.nxv4f16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv8f16 = call @llvm.vector.splice.nxv8f16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv16f16 = call @llvm.vector.splice.nxv16f16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv32f16 = call @llvm.vector.splice.nxv32f16( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv64f16 = call @llvm.vector.splice.nxv64f16( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv1f32 = call @llvm.experimental.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv2f32 = call @llvm.experimental.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv4f32 = call @llvm.experimental.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv8f32 = call @llvm.experimental.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv16f32 = call @llvm.experimental.vector.splice.nxv16f32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv32f32 = call @llvm.experimental.vector.splice.nxv32f32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv64f32 = call @llvm.experimental.vector.splice.nxv64f32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv1f32 = call @llvm.vector.splice.nxv1f32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv2f32 = call @llvm.vector.splice.nxv2f32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv4f32 = call @llvm.vector.splice.nxv4f32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv8f32 = call @llvm.vector.splice.nxv8f32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv16f32 = call @llvm.vector.splice.nxv16f32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv32f32 = call @llvm.vector.splice.nxv32f32( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv64f32 = call @llvm.vector.splice.nxv64f32( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv1f64 = call @llvm.experimental.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv2f64 = call @llvm.experimental.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv4f64 = call @llvm.experimental.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv8f64 = call @llvm.experimental.vector.splice.nxv8f64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv16f64 = call @llvm.experimental.vector.splice.nxv16f64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv32f64 = call @llvm.experimental.vector.splice.nxv32f64( zeroinitializer, zeroinitializer, i32 -1) - %splice.nxv64f64 = call @llvm.experimental.vector.splice.nxv64f64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv1f64 = call @llvm.vector.splice.nxv1f64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv2f64 = call @llvm.vector.splice.nxv2f64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv4f64 = call @llvm.vector.splice.nxv4f64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv8f64 = call @llvm.vector.splice.nxv8f64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv16f64 = call @llvm.vector.splice.nxv16f64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv32f64 = call @llvm.vector.splice.nxv32f64( zeroinitializer, zeroinitializer, i32 -1) + %splice.nxv64f64 = call @llvm.vector.splice.nxv64f64( zeroinitializer, zeroinitializer, i32 -1) ret void } -declare @llvm.experimental.vector.splice.nxv1i8(, , i32) -declare @llvm.experimental.vector.splice.nxv2i8(, , i32) -declare @llvm.experimental.vector.splice.nxv4i8(, , i32) -declare @llvm.experimental.vector.splice.nxv8i8(, , i32) -declare @llvm.experimental.vector.splice.nxv16i8(, , i32) -declare @llvm.experimental.vector.splice.nxv32i8(, , i32) -declare @llvm.experimental.vector.splice.nxv64i8(, , i32) +declare @llvm.vector.splice.nxv1i8(, , i32) +declare @llvm.vector.splice.nxv2i8(, , i32) +declare @llvm.vector.splice.nxv4i8(, , i32) +declare @llvm.vector.splice.nxv8i8(, , i32) +declare @llvm.vector.splice.nxv16i8(, , i32) +declare @llvm.vector.splice.nxv32i8(, , i32) +declare @llvm.vector.splice.nxv64i8(, , i32) -declare @llvm.experimental.vector.splice.nxv1i16(, , i32) -declare @llvm.experimental.vector.splice.nxv2i16(, , i32) -declare @llvm.experimental.vector.splice.nxv4i16(, , i32) -declare @llvm.experimental.vector.splice.nxv8i16(, , i32) -declare @llvm.experimental.vector.splice.nxv16i16(, , i32) -declare @llvm.experimental.vector.splice.nxv32i16(, , i32) -declare @llvm.experimental.vector.splice.nxv64i16(, , i32) +declare @llvm.vector.splice.nxv1i16(, , i32) +declare @llvm.vector.splice.nxv2i16(, , i32) +declare @llvm.vector.splice.nxv4i16(, , i32) +declare @llvm.vector.splice.nxv8i16(, , i32) +declare @llvm.vector.splice.nxv16i16(, , i32) +declare @llvm.vector.splice.nxv32i16(, , i32) +declare @llvm.vector.splice.nxv64i16(, , i32) -declare @llvm.experimental.vector.splice.nxv1i32(, , i32) -declare @llvm.experimental.vector.splice.nxv2i32(, , i32) -declare @llvm.experimental.vector.splice.nxv4i32(, , i32) -declare @llvm.experimental.vector.splice.nxv8i32(, , i32) -declare @llvm.experimental.vector.splice.nxv16i32(, , i32) -declare @llvm.experimental.vector.splice.nxv32i32(, , i32) -declare @llvm.experimental.vector.splice.nxv64i32(, , i32) +declare @llvm.vector.splice.nxv1i32(, , i32) +declare @llvm.vector.splice.nxv2i32(, , i32) +declare @llvm.vector.splice.nxv4i32(, , i32) +declare @llvm.vector.splice.nxv8i32(, , i32) +declare @llvm.vector.splice.nxv16i32(, , i32) +declare @llvm.vector.splice.nxv32i32(, , i32) +declare @llvm.vector.splice.nxv64i32(, , i32) -declare @llvm.experimental.vector.splice.nxv1i64(, , i32) -declare @llvm.experimental.vector.splice.nxv2i64(, , i32) -declare @llvm.experimental.vector.splice.nxv4i64(, , i32) -declare @llvm.experimental.vector.splice.nxv8i64(, , i32) -declare @llvm.experimental.vector.splice.nxv16i64(, , i32) -declare @llvm.experimental.vector.splice.nxv32i64(, , i32) -declare @llvm.experimental.vector.splice.nxv64i64(, , i32) +declare @llvm.vector.splice.nxv1i64(, , i32) +declare @llvm.vector.splice.nxv2i64(, , i32) +declare @llvm.vector.splice.nxv4i64(, , i32) +declare @llvm.vector.splice.nxv8i64(, , i32) +declare @llvm.vector.splice.nxv16i64(, , i32) +declare @llvm.vector.splice.nxv32i64(, , i32) +declare @llvm.vector.splice.nxv64i64(, , i32) -declare @llvm.experimental.vector.splice.nxv1f16(, , i32) -declare @llvm.experimental.vector.splice.nxv2f16(, , i32) -declare @llvm.experimental.vector.splice.nxv4f16(, , i32) -declare @llvm.experimental.vector.splice.nxv8f16(, , i32) -declare @llvm.experimental.vector.splice.nxv16f16(, , i32) -declare @llvm.experimental.vector.splice.nxv32f16(, , i32) -declare @llvm.experimental.vector.splice.nxv64f16(, , i32) +declare @llvm.vector.splice.nxv1f16(, , i32) +declare @llvm.vector.splice.nxv2f16(, , i32) +declare @llvm.vector.splice.nxv4f16(, , i32) +declare @llvm.vector.splice.nxv8f16(, , i32) +declare @llvm.vector.splice.nxv16f16(, , i32) +declare @llvm.vector.splice.nxv32f16(, , i32) +declare @llvm.vector.splice.nxv64f16(, , i32) -declare @llvm.experimental.vector.splice.nxv1f32(, , i32) -declare @llvm.experimental.vector.splice.nxv2f32(, , i32) -declare @llvm.experimental.vector.splice.nxv4f32(, , i32) -declare @llvm.experimental.vector.splice.nxv8f32(, , i32) -declare @llvm.experimental.vector.splice.nxv16f32(, , i32) -declare @llvm.experimental.vector.splice.nxv32f32(, , i32) -declare @llvm.experimental.vector.splice.nxv64f32(, , i32) +declare @llvm.vector.splice.nxv1f32(, , i32) +declare @llvm.vector.splice.nxv2f32(, , i32) +declare @llvm.vector.splice.nxv4f32(, , i32) +declare @llvm.vector.splice.nxv8f32(, , i32) +declare @llvm.vector.splice.nxv16f32(, , i32) +declare @llvm.vector.splice.nxv32f32(, , i32) +declare @llvm.vector.splice.nxv64f32(, , i32) -declare @llvm.experimental.vector.splice.nxv1f64(, , i32) -declare @llvm.experimental.vector.splice.nxv2f64(, , i32) -declare @llvm.experimental.vector.splice.nxv4f64(, , i32) -declare @llvm.experimental.vector.splice.nxv8f64(, , i32) -declare @llvm.experimental.vector.splice.nxv16f64(, , i32) -declare @llvm.experimental.vector.splice.nxv32f64(, , i32) -declare @llvm.experimental.vector.splice.nxv64f64(, , i32) +declare @llvm.vector.splice.nxv1f64(, , i32) +declare @llvm.vector.splice.nxv2f64(, , i32) +declare @llvm.vector.splice.nxv4f64(, , i32) +declare @llvm.vector.splice.nxv8f64(, , i32) +declare @llvm.vector.splice.nxv16f64(, , i32) +declare @llvm.vector.splice.nxv32f64(, , i32) +declare @llvm.vector.splice.nxv64f64(, , i32) diff --git a/llvm/test/Bitcode/upgrade-vector-interleave2-deinterleave2-intrinsics.ll b/llvm/test/Bitcode/upgrade-vector-interleave2-deinterleave2-intrinsics.ll new file mode 100644 index 000000000000..f06395945297 --- /dev/null +++ b/llvm/test/Bitcode/upgrade-vector-interleave2-deinterleave2-intrinsics.ll @@ -0,0 +1,46 @@ +; RUN: opt -S < %s | FileCheck %s +; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s + +define <8 x i32> @interleave_fixed(<4 x i32> %a, <4 x i32> %b) { +; CHECK-LABEL: @interleave_fixed +; CHECK: %res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b) + + %res = call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b) + ret <8 x i32> %res +} + +define { <4 x i32>, <4 x i32> } @deinterleave_fixed(<8 x i32> %a) { +; CHECK-LABEL: @deinterleave_fixed +; CHECK: %res = call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %a) + + %res = call { <4 x i32>, <4 x i32> } @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %a) + ret { <4 x i32>, <4 x i32> } %res +} + +define @interleave_scalable( %a, %b) { +; CHECK-LABEL: @interleave_scalable +; CHECK: %res = call @llvm.vector.interleave2.nxv8i32( %a, %b) + + %res = call @llvm.experimental.vector.interleave2.nxv8i32( %a, %b) + ret %res +} + +define { , } @deinterleave_scalable( %a) { +; CHECK-LABEL: @deinterleave_scalable +; CHECK: %res = call { , } @llvm.vector.deinterleave2.nxv8i32( %a) + + %res = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( %a) + ret { , } %res +} + +declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) +; CHECK: <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) + +declare { <4 x i32>, <4 x i32> } @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>) +; CHECK: declare { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32>) + +declare @llvm.experimental.vector.interleave2.nxv8i32(, ) +; CHECK: @llvm.vector.interleave2.nxv8i32(, ) + +declare { , } @llvm.experimental.vector.deinterleave2.nxv8i32() +; CHECK: declare { , } @llvm.vector.deinterleave2.nxv8i32() diff --git a/llvm/test/Bitcode/upgrade-vector-reverse-intrinsic.ll b/llvm/test/Bitcode/upgrade-vector-reverse-intrinsic.ll new file mode 100644 index 000000000000..6b853eaf4175 --- /dev/null +++ b/llvm/test/Bitcode/upgrade-vector-reverse-intrinsic.ll @@ -0,0 +1,24 @@ +; RUN: opt -S < %s | FileCheck %s +; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s + +define <16 x i8> @reverse_fixed(<16 x i8> %a) { +; CHECK-LABEL: @reverse_fixed +; CHECK: %res = call <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8> %a) + + %res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a) + ret <16 x i8> %res +} + +define @reverse_scalable( %a) { +; CHECK-LABEL: @reverse_scalable +; CHECK: %res = call @llvm.vector.reverse.nxv16i8( %a) + + %res = call @llvm.experimental.vector.reverse.nxv16i8( %a) + ret %res +} + +declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>) +; CHECK: declare <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8>) + +declare @llvm.experimental.vector.reverse.nxv16i8() +; CHECK: declare @llvm.vector.reverse.nxv16i8() diff --git a/llvm/test/Bitcode/upgrade-vector-splice-intrinsic.ll b/llvm/test/Bitcode/upgrade-vector-splice-intrinsic.ll new file mode 100644 index 000000000000..1b55da21ecd2 --- /dev/null +++ b/llvm/test/Bitcode/upgrade-vector-splice-intrinsic.ll @@ -0,0 +1,24 @@ +; RUN: opt -S < %s | FileCheck %s +; RUN: llvm-as %s -o - | llvm-dis | FileCheck %s + +define <8 x half> @splice_fixed(<8 x half> %a, <8 x half> %b) { +; CHECK-LABEL: @splice_fixed +; CHECK: %res = call <8 x half> @llvm.vector.splice.v8f16(<8 x half> %a, <8 x half> %b, i32 2) + + %res = call <8 x half> @llvm.experimental.vector.splice.v8f16(<8 x half> %a, <8 x half> %b, i32 2) + ret <8 x half> %res +} + +define @splice_scalable( %a, %b) { +; CHECK-LABEL: @splice_scalable +; CHECK: %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 2) + + %res = call @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 2) + ret %res +} + +declare <8 x half> @llvm.experimental.vector.splice.v8f16(<8 x half>, <8 x half>, i32 immarg) +; CHECK: declare <8 x half> @llvm.vector.splice.v8f16(<8 x half>, <8 x half>, i32 immarg) + +declare @llvm.experimental.vector.splice.nxv8f16(, , i32 immarg) +; CHECK: declare @llvm.vector.splice.nxv8f16(, , i32 immarg) diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll index 10882a06af1b..0b7fae47a65a 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-deinterleave2.ll @@ -11,7 +11,7 @@ define void @vector_deinterleave2_v4i32(<4 x i32> %a) { ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[DEF]], shufflemask(0, 2) ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<2 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<4 x s32>), [[DEF]], shufflemask(1, 3) ; CHECK-NEXT: RET_ReallyLR - %res = call {<2 x i32>, <2 x i32>} @llvm.experimental.vector.deinterleave2.v4i32(<4 x i32> %a) + %res = call {<2 x i32>, <2 x i32>} @llvm.vector.deinterleave2.v4i32(<4 x i32> %a) ret void } @@ -29,6 +29,6 @@ define void @vector_deinterleave2_v8f32(<8 x float> %a) { ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x s32>), [[DEF]], shufflemask(0, 2, 4, 6) ; CHECK-NEXT: [[SHUF1:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[CONCAT_VECTORS]](<8 x s32>), [[DEF]], shufflemask(1, 3, 5, 7) ; CHECK-NEXT: RET_ReallyLR - %res = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %a) + %res = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %a) ret void } diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll index f51e47a428d1..0d8ac82c1051 100644 --- a/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll +++ b/llvm/test/CodeGen/AArch64/GlobalISel/irtranslator-vector-interleave2.ll @@ -10,7 +10,7 @@ define void @vector_interleave2_v4i32(<2 x i32> %a, <2 x i32> %b) { ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(<2 x s32>) = COPY $d1 ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<4 x s32>) = G_SHUFFLE_VECTOR [[COPY]](<2 x s32>), [[COPY1]], shufflemask(0, 2, 1, 3) ; CHECK-NEXT: RET_ReallyLR - %res = call <4 x i32> @llvm.experimental.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b) + %res = call <4 x i32> @llvm.vector.interleave2.v4i32(<2 x i32> %a, <2 x i32> %b) ret void } @@ -25,6 +25,6 @@ define void @vector_interleave2_v8f32(<4 x float> %a, <4 x float> %b) { ; CHECK-NEXT: [[BITCAST1:%[0-9]+]]:_(<4 x s32>) = G_BITCAST [[COPY1]](<2 x s64>) ; CHECK-NEXT: [[SHUF:%[0-9]+]]:_(<8 x s32>) = G_SHUFFLE_VECTOR [[BITCAST]](<4 x s32>), [[BITCAST1]], shufflemask(0, 4, 1, 5, 2, 6, 3, 7) ; CHECK-NEXT: RET_ReallyLR - %res = call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b) + %res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b) ret void } diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll index 86b1d5d195ff..0485d530fd06 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-contract.ll @@ -25,10 +25,10 @@ define @mull_add( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec29 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec29 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec29, 0 %3 = extractvalue { , } %strided.vec29, 1 %4 = fmul contract %0, %3 @@ -37,12 +37,12 @@ entry: %7 = fmul contract %0, %2 %8 = fmul contract %1, %3 %9 = fsub contract %7, %8 - %strided.vec31 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec31 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %10 = extractvalue { , } %strided.vec31, 0 %11 = extractvalue { , } %strided.vec31, 1 %12 = fadd contract %10, %9 %13 = fadd contract %6, %11 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %12, %13) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %12, %13) ret %interleaved.vec } @@ -67,10 +67,10 @@ define @mul_add_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec52 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec52 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec52, 0 %3 = extractvalue { , } %strided.vec52, 1 %4 = fmul contract %0, %3 @@ -79,10 +79,10 @@ entry: %7 = fmul contract %0, %2 %8 = fmul contract %1, %3 %9 = fsub contract %7, %8 - %strided.vec54 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec54 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %10 = extractvalue { , } %strided.vec54, 0 %11 = extractvalue { , } %strided.vec54, 1 - %strided.vec56 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec56 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %12 = extractvalue { , } %strided.vec56, 0 %13 = extractvalue { , } %strided.vec56, 1 %14 = fmul contract %10, %13 @@ -93,7 +93,7 @@ entry: %19 = fsub contract %17, %18 %20 = fadd contract %9, %19 %21 = fadd contract %6, %16 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %20, %21) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %20, %21) ret %interleaved.vec } @@ -118,10 +118,10 @@ define @mul_sub_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec52 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec52 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec52, 0 %3 = extractvalue { , } %strided.vec52, 1 %4 = fmul contract %0, %3 @@ -130,10 +130,10 @@ entry: %7 = fmul contract %0, %2 %8 = fmul contract %1, %3 %9 = fsub contract %7, %8 - %strided.vec54 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec54 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %10 = extractvalue { , } %strided.vec54, 0 %11 = extractvalue { , } %strided.vec54, 1 - %strided.vec56 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec56 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %12 = extractvalue { , } %strided.vec56, 0 %13 = extractvalue { , } %strided.vec56, 1 %14 = fmul contract %10, %13 @@ -144,7 +144,7 @@ entry: %19 = fsub contract %17, %18 %20 = fsub contract %9, %19 %21 = fsub contract %6, %16 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %20, %21) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %20, %21) ret %interleaved.vec } @@ -169,10 +169,10 @@ define @mul_conj_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec60 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec60 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec60, 0 %3 = extractvalue { , } %strided.vec60, 1 %4 = fmul contract %0, %3 @@ -181,10 +181,10 @@ entry: %7 = fmul contract %0, %2 %8 = fmul contract %1, %3 %9 = fsub contract %7, %8 - %strided.vec62 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec62 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %10 = extractvalue { , } %strided.vec62, 0 %11 = extractvalue { , } %strided.vec62, 1 - %strided.vec64 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec64 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %12 = extractvalue { , } %strided.vec64, 0 %13 = extractvalue { , } %strided.vec64, 1 %14 = fmul contract %10, %13 @@ -195,7 +195,7 @@ entry: %19 = fadd contract %17, %18 %20 = fadd contract %9, %19 %21 = fadd contract %6, %16 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %20, %21) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %20, %21) ret %interleaved.vec } @@ -238,10 +238,10 @@ define @mul_add_rot_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec78 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec78 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec78, 0 %3 = extractvalue { , } %strided.vec78, 1 %4 = fmul contract %0, %3 @@ -250,14 +250,14 @@ entry: %7 = fmul contract %0, %2 %8 = fmul contract %1, %3 %9 = fsub contract %7, %8 - %strided.vec80 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec80 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %10 = extractvalue { , } %strided.vec80, 0 %11 = extractvalue { , } %strided.vec80, 1 %12 = tail call contract @llvm.copysign.nxv2f64( zeroinitializer, %11) %13 = fadd contract %10, %12 %14 = tail call contract @llvm.copysign.nxv2f64( zeroinitializer, %10) %15 = fsub contract %14, %11 - %strided.vec82 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec82 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %16 = extractvalue { , } %strided.vec82, 0 %17 = extractvalue { , } %strided.vec82, 1 %18 = fmul contract %15, %17 @@ -268,10 +268,10 @@ entry: %23 = fsub contract %21, %22 %24 = fadd contract %9, %23 %25 = fadd contract %6, %20 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %24, %25) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %24, %25) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f64() +declare @llvm.vector.interleave2.nxv4f64(, ) declare @llvm.copysign.nxv2f64(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll index edf580e334e8..c643ae9265c0 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-add-mull-scalable-fast.ll @@ -16,24 +16,24 @@ define @mull_add( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec29 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec29 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec29, 0 %3 = extractvalue { , } %strided.vec29, 1 %4 = fmul fast %3, %0 %5 = fmul fast %2, %1 %6 = fadd fast %4, %5 %7 = fmul fast %2, %0 - %strided.vec31 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec31 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %8 = extractvalue { , } %strided.vec31, 0 %9 = extractvalue { , } %strided.vec31, 1 %10 = fadd fast %8, %7 %11 = fmul fast %3, %1 %12 = fsub fast %10, %11 %13 = fadd fast %6, %9 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %12, %13) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %12, %13) ret %interleaved.vec } @@ -56,20 +56,20 @@ define @mul_add_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec52 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec52 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec52, 0 %3 = extractvalue { , } %strided.vec52, 1 %4 = fmul fast %3, %0 %5 = fmul fast %2, %1 %6 = fmul fast %2, %0 %7 = fmul fast %3, %1 - %strided.vec54 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec54 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %8 = extractvalue { , } %strided.vec54, 0 %9 = extractvalue { , } %strided.vec54, 1 - %strided.vec56 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec56 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %10 = extractvalue { , } %strided.vec56, 0 %11 = extractvalue { , } %strided.vec56, 1 %12 = fmul fast %11, %8 @@ -82,7 +82,7 @@ entry: %19 = fadd fast %4, %5 %20 = fadd fast %19, %13 %21 = fadd fast %20, %12 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %18, %21) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %18, %21) ret %interleaved.vec } @@ -105,20 +105,20 @@ define @mul_sub_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec54 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec54 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec54, 0 %3 = extractvalue { , } %strided.vec54, 1 %4 = fmul fast %3, %0 %5 = fmul fast %2, %1 %6 = fmul fast %2, %0 %7 = fmul fast %3, %1 - %strided.vec56 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec56 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %8 = extractvalue { , } %strided.vec56, 0 %9 = extractvalue { , } %strided.vec56, 1 - %strided.vec58 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec58 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %10 = extractvalue { , } %strided.vec58, 0 %11 = extractvalue { , } %strided.vec58, 1 %12 = fmul fast %11, %9 @@ -131,7 +131,7 @@ entry: %19 = fadd fast %18, %17 %20 = fadd fast %4, %5 %21 = fsub fast %20, %19 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %16, %21) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %16, %21) ret %interleaved.vec } @@ -154,19 +154,19 @@ define @mul_conj_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec60 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec60 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec60, 0 %3 = extractvalue { , } %strided.vec60, 1 %4 = fmul fast %3, %0 %5 = fmul fast %2, %1 %6 = fmul fast %2, %0 - %strided.vec62 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec62 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %7 = extractvalue { , } %strided.vec62, 0 %8 = extractvalue { , } %strided.vec62, 1 - %strided.vec64 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec64 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %9 = extractvalue { , } %strided.vec64, 0 %10 = extractvalue { , } %strided.vec64, 1 %11 = fmul fast %10, %7 @@ -180,7 +180,7 @@ entry: %19 = fmul fast %9, %8 %20 = fsub fast %18, %19 %21 = fadd fast %20, %11 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %17, %21) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %17, %21) ret %interleaved.vec } @@ -211,20 +211,20 @@ define @mul_add_rot_mull( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec80 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec80 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec80, 0 %3 = extractvalue { , } %strided.vec80, 1 %4 = fmul fast %3, %0 %5 = fmul fast %2, %1 %6 = fmul fast %2, %0 %7 = fmul fast %3, %1 - %strided.vec82 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %c) + %strided.vec82 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %c) %8 = extractvalue { , } %strided.vec82, 0 %9 = extractvalue { , } %strided.vec82, 1 - %strided.vec84 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %d) + %strided.vec84 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %d) %10 = extractvalue { , } %strided.vec84, 0 %11 = extractvalue { , } %strided.vec84, 1 %12 = fmul fast %10, %8 @@ -237,9 +237,9 @@ entry: %19 = fadd fast %18, %12 %20 = fmul fast %11, %9 %21 = fsub fast %19, %20 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %17, %21) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %17, %21) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f64() +declare @llvm.vector.interleave2.nxv4f64(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll index 48b5756b01fb..dae8d9f89e99 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add-scalable.ll @@ -24,15 +24,15 @@ define @complex_add_v4f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f16( %0, %1) ret %interleaved.vec } @@ -45,15 +45,15 @@ define @complex_add_v8f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv8f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8f16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8f16( %0, %1) ret %interleaved.vec } @@ -68,15 +68,15 @@ define @complex_add_v16f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv16f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16f16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16f16( %0, %1) ret %interleaved.vec } @@ -95,26 +95,26 @@ define @complex_add_v32f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv32f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv32f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv32f16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv32f16( %0, %1) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f16() -declare @llvm.experimental.vector.interleave2.nxv4f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f16() +declare @llvm.vector.interleave2.nxv4f16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f16() -declare @llvm.experimental.vector.interleave2.nxv8f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv8f16() +declare @llvm.vector.interleave2.nxv8f16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16f16() -declare @llvm.experimental.vector.interleave2.nxv16f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv16f16() +declare @llvm.vector.interleave2.nxv16f16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv32f16() -declare @llvm.experimental.vector.interleave2.nxv32f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv32f16() +declare @llvm.vector.interleave2.nxv32f16(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll index 7cdb10e7159f..a5c64c0982d0 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-add.ll @@ -127,15 +127,15 @@ define <4 x half> @complex_add_v4f16_with_intrinsic(<4 x half> %a, <4 x half> %b ; CHECK-NEXT: fcadd v0.4h, v1.4h, v0.4h, #90 ; CHECK-NEXT: ret entry: - %a.deinterleaved = tail call { <2 x half>, <2 x half> } @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %a) + %a.deinterleaved = tail call { <2 x half>, <2 x half> } @llvm.vector.deinterleave2.v4f16(<4 x half> %a) %a.real = extractvalue { <2 x half>, <2 x half> } %a.deinterleaved, 0 %a.imag = extractvalue { <2 x half>, <2 x half> } %a.deinterleaved, 1 - %b.deinterleaved = tail call { <2 x half>, <2 x half> } @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %b) + %b.deinterleaved = tail call { <2 x half>, <2 x half> } @llvm.vector.deinterleave2.v4f16(<4 x half> %b) %b.real = extractvalue { <2 x half>, <2 x half> } %b.deinterleaved, 0 %b.imag = extractvalue { <2 x half>, <2 x half> } %b.deinterleaved, 1 %0 = fsub fast <2 x half> %b.real, %a.imag %1 = fadd fast <2 x half> %b.imag, %a.real - %interleaved.vec = tail call <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half> %0, <2 x half> %1) + %interleaved.vec = tail call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %0, <2 x half> %1) ret <4 x half> %interleaved.vec } @@ -146,15 +146,15 @@ define <8 x half> @complex_add_v8f16_with_intrinsic(<8 x half> %a, <8 x half> %b ; CHECK-NEXT: fcadd v0.8h, v1.8h, v0.8h, #90 ; CHECK-NEXT: ret entry: - %a.deinterleaved = tail call { <4 x half>, <4 x half> } @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %a) + %a.deinterleaved = tail call { <4 x half>, <4 x half> } @llvm.vector.deinterleave2.v8f16(<8 x half> %a) %a.real = extractvalue { <4 x half>, <4 x half> } %a.deinterleaved, 0 %a.imag = extractvalue { <4 x half>, <4 x half> } %a.deinterleaved, 1 - %b.deinterleaved = tail call { <4 x half>, <4 x half> } @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %b) + %b.deinterleaved = tail call { <4 x half>, <4 x half> } @llvm.vector.deinterleave2.v8f16(<8 x half> %b) %b.real = extractvalue { <4 x half>, <4 x half> } %b.deinterleaved, 0 %b.imag = extractvalue { <4 x half>, <4 x half> } %b.deinterleaved, 1 %0 = fsub fast <4 x half> %b.real, %a.imag %1 = fadd fast <4 x half> %b.imag, %a.real - %interleaved.vec = tail call <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half> %0, <4 x half> %1) + %interleaved.vec = tail call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %0, <4 x half> %1) ret <8 x half> %interleaved.vec } @@ -166,15 +166,15 @@ define <16 x half> @complex_add_v16f16_with_intrinsic(<16 x half> %a, <16 x half ; CHECK-NEXT: fcadd v0.8h, v2.8h, v0.8h, #90 ; CHECK-NEXT: ret entry: - %a.deinterleaved = tail call { <8 x half>, <8 x half> } @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %a) + %a.deinterleaved = tail call { <8 x half>, <8 x half> } @llvm.vector.deinterleave2.v16f16(<16 x half> %a) %a.real = extractvalue { <8 x half>, <8 x half> } %a.deinterleaved, 0 %a.imag = extractvalue { <8 x half>, <8 x half> } %a.deinterleaved, 1 - %b.deinterleaved = tail call { <8 x half>, <8 x half> } @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %b) + %b.deinterleaved = tail call { <8 x half>, <8 x half> } @llvm.vector.deinterleave2.v16f16(<16 x half> %b) %b.real = extractvalue { <8 x half>, <8 x half> } %b.deinterleaved, 0 %b.imag = extractvalue { <8 x half>, <8 x half> } %b.deinterleaved, 1 %0 = fsub fast <8 x half> %b.real, %a.imag %1 = fadd fast <8 x half> %b.imag, %a.real - %interleaved.vec = tail call <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half> %0, <8 x half> %1) + %interleaved.vec = tail call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %0, <8 x half> %1) ret <16 x half> %interleaved.vec } @@ -216,11 +216,11 @@ entry: } -declare { <2 x half>, <2 x half> } @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>) -declare <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half>, <2 x half>) +declare { <2 x half>, <2 x half> } @llvm.vector.deinterleave2.v4f16(<4 x half>) +declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>) -declare { <4 x half>, <4 x half> } @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>) -declare <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half>, <4 x half>) +declare { <4 x half>, <4 x half> } @llvm.vector.deinterleave2.v8f16(<8 x half>) +declare <8 x half> @llvm.vector.interleave2.v8f16(<4 x half>, <4 x half>) -declare { <8 x half>, <8 x half> } @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>) -declare <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half>, <8 x half>) +declare { <8 x half>, <8 x half> } @llvm.vector.deinterleave2.v16f16(<16 x half>) +declare <16 x half> @llvm.vector.interleave2.v16f16(<8 x half>, <8 x half>) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll index cb285c05b2e8..c09ec616b015 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f16-mul-scalable.ll @@ -27,10 +27,10 @@ define @complex_mul_v4f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -39,7 +39,7 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f16( %5, %2) ret %interleaved.vec } @@ -54,10 +54,10 @@ define @complex_mul_v8f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv8f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -66,7 +66,7 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8f16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8f16( %5, %2) ret %interleaved.vec } ; Expected to transform @@ -84,10 +84,10 @@ define @complex_mul_v16f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv16f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -96,7 +96,7 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16f16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16f16( %5, %2) ret %interleaved.vec } @@ -123,10 +123,10 @@ define @complex_mul_v32f16( %a, , } @llvm.experimental.vector.deinterleave2.nxv32f16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32f16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv32f16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32f16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -135,20 +135,20 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv32f16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv32f16( %5, %2) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f16() -declare @llvm.experimental.vector.interleave2.nxv4f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f16() +declare @llvm.vector.interleave2.nxv4f16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f16() -declare @llvm.experimental.vector.interleave2.nxv8f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv8f16() +declare @llvm.vector.interleave2.nxv8f16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16f16() -declare @llvm.experimental.vector.interleave2.nxv16f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv16f16() +declare @llvm.vector.interleave2.nxv16f16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv32f16() -declare @llvm.experimental.vector.interleave2.nxv32f16(, ) +declare { , } @llvm.vector.deinterleave2.nxv32f16() +declare @llvm.vector.interleave2.nxv32f16(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll index ab764a58a770..47ad9ea2451a 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-add-scalable.ll @@ -12,15 +12,15 @@ define @complex_add_v4f32( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f32( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f32( %0, %1) ret %interleaved.vec } @@ -35,15 +35,15 @@ define @complex_add_v8f32( %a, , } @llvm.experimental.vector.deinterleave2.nxv8f32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8f32( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8f32( %0, %1) ret %interleaved.vec } ; Expected to transform @@ -61,23 +61,23 @@ define @complex_add_v16f32( %a, , } @llvm.experimental.vector.deinterleave2.nxv16f32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16f32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16f32( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16f32( %0, %1) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f32() -declare @llvm.experimental.vector.interleave2.nxv4f32(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f32() +declare @llvm.vector.interleave2.nxv4f32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f32() -declare @llvm.experimental.vector.interleave2.nxv8f32(, ) +declare { , } @llvm.vector.deinterleave2.nxv8f32() +declare @llvm.vector.interleave2.nxv8f32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16f32() -declare @llvm.experimental.vector.interleave2.nxv16f32(, ) +declare { , } @llvm.vector.deinterleave2.nxv16f32() +declare @llvm.vector.interleave2.nxv16f32(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll index 1e2afb78de1b..bcd46aa182b5 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f32-mul-scalable.ll @@ -14,10 +14,10 @@ define @complex_mul_v4f32( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -26,7 +26,7 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f32( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f32( %5, %2) ret %interleaved.vec } @@ -45,10 +45,10 @@ define @complex_mul_v8f32( %a, , } @llvm.experimental.vector.deinterleave2.nxv8f32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -57,7 +57,7 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8f32( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8f32( %5, %2) ret %interleaved.vec } @@ -84,10 +84,10 @@ define @complex_mul_v16f32( %a, , } @llvm.experimental.vector.deinterleave2.nxv16f32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16f32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16f32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -96,16 +96,16 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16f32( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16f32( %5, %2) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f32() -declare @llvm.experimental.vector.interleave2.nxv4f32(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f32() +declare @llvm.vector.interleave2.nxv4f32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f32() -declare @llvm.experimental.vector.interleave2.nxv8f32(, ) +declare { , } @llvm.vector.deinterleave2.nxv8f32() +declare @llvm.vector.interleave2.nxv8f32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16f32() -declare @llvm.experimental.vector.interleave2.nxv16f32(, ) +declare { , } @llvm.vector.deinterleave2.nxv16f32() +declare @llvm.vector.interleave2.nxv16f32(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll index 46a15f489d2b..c992d63ca283 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-add-scalable.ll @@ -12,15 +12,15 @@ define @complex_add_v2f64( %a, , } @llvm.experimental.vector.deinterleave2.nxv2f64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv2f64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv2f64( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv2f64( %0, %1) ret %interleaved.vec } @@ -35,15 +35,15 @@ define @complex_add_v4f64( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %0, %1) ret %interleaved.vec } @@ -62,23 +62,23 @@ define @complex_add_v8f64( %a, , } @llvm.experimental.vector.deinterleave2.nxv8f64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fsub fast %b.real, %a.imag %1 = fadd fast %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8f64( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8f64( %0, %1) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv2f64() -declare @llvm.experimental.vector.interleave2.nxv2f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv2f64() +declare @llvm.vector.interleave2.nxv2f64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f64() +declare @llvm.vector.interleave2.nxv4f64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f64() -declare @llvm.experimental.vector.interleave2.nxv8f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv8f64() +declare @llvm.vector.interleave2.nxv8f64(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll index 17a239a09a03..db28fa3997cb 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-f64-mul-scalable.ll @@ -14,10 +14,10 @@ define @complex_mul_v2f64( %a, , } @llvm.experimental.vector.deinterleave2.nxv2f64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv2f64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -26,7 +26,7 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv2f64( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv2f64( %5, %2) ret %interleaved.vec } @@ -45,10 +45,10 @@ define @complex_mul_v4f64( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -57,7 +57,7 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %5, %2) ret %interleaved.vec } @@ -84,10 +84,10 @@ define @complex_mul_v8f64( %a, , } @llvm.experimental.vector.deinterleave2.nxv8f64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8f64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = fmul fast %b.imag, %a.real @@ -96,15 +96,15 @@ entry: %3 = fmul fast %b.real, %a.real %4 = fmul fast %a.imag, %b.imag %5 = fsub fast %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8f64( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8f64( %5, %2) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv2f64() -declare @llvm.experimental.vector.interleave2.nxv2f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv2f64() +declare @llvm.vector.interleave2.nxv2f64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f64() +declare @llvm.vector.interleave2.nxv4f64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f64() -declare @llvm.experimental.vector.interleave2.nxv8f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv8f64() +declare @llvm.vector.interleave2.nxv8f64(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll index 001046f8f397..f0569674c651 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-add-scalable.ll @@ -22,15 +22,15 @@ define @complex_add_v4i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv4i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4i16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4i16( %0, %1) ret %interleaved.vec } @@ -42,15 +42,15 @@ define @complex_add_v8i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i16( %0, %1) ret %interleaved.vec } @@ -64,15 +64,15 @@ define @complex_add_v16i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv16i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16i16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16i16( %0, %1) ret %interleaved.vec } @@ -90,26 +90,26 @@ define @complex_add_v32i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv32i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv32i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv32i16( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv32i16( %0, %1) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4i16() -declare @llvm.experimental.vector.interleave2.nxv4i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv4i16() +declare @llvm.vector.interleave2.nxv4i16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i16() -declare @llvm.experimental.vector.interleave2.nxv8i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv8i16() +declare @llvm.vector.interleave2.nxv8i16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16i16() -declare @llvm.experimental.vector.interleave2.nxv16i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv16i16() +declare @llvm.vector.interleave2.nxv16i16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv32i16() -declare @llvm.experimental.vector.interleave2.nxv32i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv32i16() +declare @llvm.vector.interleave2.nxv32i16(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll index 07488b623b98..b4cb548f6308 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i16-mul-scalable.ll @@ -26,10 +26,10 @@ define @complex_mul_v4i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv4i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -38,7 +38,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4i16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4i16( %5, %2) ret %interleaved.vec } @@ -52,10 +52,10 @@ define @complex_mul_v8i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -64,7 +64,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i16( %5, %2) ret %interleaved.vec } ; Expected to transform @@ -81,10 +81,10 @@ define @complex_mul_v16i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv16i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -93,7 +93,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16i16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16i16( %5, %2) ret %interleaved.vec } @@ -119,10 +119,10 @@ define @complex_mul_v32i16( %a, , } @llvm.experimental.vector.deinterleave2.nxv32i16( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32i16( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv32i16( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32i16( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -131,20 +131,20 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv32i16( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv32i16( %5, %2) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4i16() -declare @llvm.experimental.vector.interleave2.nxv4i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv4i16() +declare @llvm.vector.interleave2.nxv4i16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i16() -declare @llvm.experimental.vector.interleave2.nxv8i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv8i16() +declare @llvm.vector.interleave2.nxv8i16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16i16() -declare @llvm.experimental.vector.interleave2.nxv16i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv16i16() +declare @llvm.vector.interleave2.nxv16i16(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv32i16() -declare @llvm.experimental.vector.interleave2.nxv32i16(, ) +declare { , } @llvm.vector.deinterleave2.nxv32i16() +declare @llvm.vector.interleave2.nxv32i16(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll index 1ce480bbf3d8..458cd62269f8 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-add-scalable.ll @@ -11,15 +11,15 @@ define @complex_add_v4i32( %a, , } @llvm.experimental.vector.deinterleave2.nxv4i32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4i32( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4i32( %0, %1) ret %interleaved.vec } @@ -33,15 +33,15 @@ define @complex_add_v8i32( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i32( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i32( %0, %1) ret %interleaved.vec } @@ -59,23 +59,23 @@ define @complex_add_v16i32( %a, , } @llvm.experimental.vector.deinterleave2.nxv16i32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16i32( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16i32( %0, %1) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4i32() -declare @llvm.experimental.vector.interleave2.nxv4i32(, ) +declare { , } @llvm.vector.deinterleave2.nxv4i32() +declare @llvm.vector.interleave2.nxv4i32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i32() -declare @llvm.experimental.vector.interleave2.nxv8i32(, ) +declare { , } @llvm.vector.deinterleave2.nxv8i32() +declare @llvm.vector.interleave2.nxv8i32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16i32() -declare @llvm.experimental.vector.interleave2.nxv16i32(, ) +declare { , } @llvm.vector.deinterleave2.nxv16i32() +declare @llvm.vector.interleave2.nxv16i32(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll index d88eef9800d7..4cfe4707b9a9 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i32-mul-scalable.ll @@ -13,10 +13,10 @@ define @complex_mul_v4i32( %a, , } @llvm.experimental.vector.deinterleave2.nxv4i32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -25,7 +25,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4i32( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4i32( %5, %2) ret %interleaved.vec } @@ -43,10 +43,10 @@ define @complex_mul_v8i32( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -55,7 +55,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i32( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i32( %5, %2) ret %interleaved.vec } @@ -81,10 +81,10 @@ define @complex_mul_v16i32( %a, , } @llvm.experimental.vector.deinterleave2.nxv16i32( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i32( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i32( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i32( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -93,16 +93,16 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16i32( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16i32( %5, %2) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4i32() -declare @llvm.experimental.vector.interleave2.nxv4i32(, ) +declare { , } @llvm.vector.deinterleave2.nxv4i32() +declare @llvm.vector.interleave2.nxv4i32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i32() -declare @llvm.experimental.vector.interleave2.nxv8i32(, ) +declare { , } @llvm.vector.deinterleave2.nxv8i32() +declare @llvm.vector.interleave2.nxv8i32(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16i32() -declare @llvm.experimental.vector.interleave2.nxv16i32(, ) +declare { , } @llvm.vector.deinterleave2.nxv16i32() +declare @llvm.vector.interleave2.nxv16i32(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-add-scalable.ll index 0b59be9414fa..f06b55c68b7e 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-add-scalable.ll @@ -11,15 +11,15 @@ define @complex_add_v2i64( %a, , } @llvm.experimental.vector.deinterleave2.nxv2i64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2i64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv2i64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2i64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv2i64( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv2i64( %0, %1) ret %interleaved.vec } @@ -33,15 +33,15 @@ define @complex_add_v4i64( %a, , } @llvm.experimental.vector.deinterleave2.nxv4i64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4i64( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4i64( %0, %1) ret %interleaved.vec } @@ -59,23 +59,23 @@ define @complex_add_v8i64( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i64( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i64( %0, %1) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv2i64() -declare @llvm.experimental.vector.interleave2.nxv2i64(, ) +declare { , } @llvm.vector.deinterleave2.nxv2i64() +declare @llvm.vector.interleave2.nxv2i64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv4i64() -declare @llvm.experimental.vector.interleave2.nxv4i64(, ) +declare { , } @llvm.vector.deinterleave2.nxv4i64() +declare @llvm.vector.interleave2.nxv4i64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i64() -declare @llvm.experimental.vector.interleave2.nxv8i64(, ) +declare { , } @llvm.vector.deinterleave2.nxv8i64() +declare @llvm.vector.interleave2.nxv8i64(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll index 16e1f3e63dce..5975f3b491d4 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i64-mul-scalable.ll @@ -13,10 +13,10 @@ define @complex_mul_v2i64( %a, , } @llvm.experimental.vector.deinterleave2.nxv2i64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2i64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv2i64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv2i64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -25,7 +25,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv2i64( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv2i64( %5, %2) ret %interleaved.vec } @@ -43,10 +43,10 @@ define @complex_mul_v4i64( %a, , } @llvm.experimental.vector.deinterleave2.nxv4i64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv4i64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -55,7 +55,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4i64( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4i64( %5, %2) ret %interleaved.vec } @@ -81,10 +81,10 @@ define @complex_mul_v8i64( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = mul %b.imag, %a.real @@ -93,7 +93,7 @@ entry: %3 = mul %b.real, %a.real %4 = mul %a.imag, %b.imag %5 = sub %3, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i64( %5, %2) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i64( %5, %2) ret %interleaved.vec } @@ -119,11 +119,11 @@ define @complex_minus_mul_v8i64( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i64( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i64( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 %0 = sub zeroinitializer, %a.real - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i64( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i64( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %1 = mul %b.real, %0 @@ -132,15 +132,15 @@ entry: %4 = mul %b.real, %a.imag %5 = mul %b.imag, %0 %6 = sub %5, %4 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i64( %3, %6) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i64( %3, %6) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv2i64() -declare @llvm.experimental.vector.interleave2.nxv2i64(, ) +declare { , } @llvm.vector.deinterleave2.nxv2i64() +declare @llvm.vector.interleave2.nxv2i64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv4i64() -declare @llvm.experimental.vector.interleave2.nxv4i64(, ) +declare { , } @llvm.vector.deinterleave2.nxv4i64() +declare @llvm.vector.interleave2.nxv4i64(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i64() -declare @llvm.experimental.vector.interleave2.nxv8i64(, ) +declare { , } @llvm.vector.deinterleave2.nxv8i64() +declare @llvm.vector.interleave2.nxv8i64(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll index b631486137e6..81872c1723f2 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-i8-add-scalable.ll @@ -22,15 +22,15 @@ define @complex_add_v8i8( %a, , } @llvm.experimental.vector.deinterleave2.nxv8i8( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i8( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i8( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv8i8( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv8i8( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv8i8( %0, %1) ret %interleaved.vec } @@ -42,15 +42,15 @@ define @complex_add_v16i8( %a, , } @llvm.experimental.vector.deinterleave2.nxv16i8( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i8( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i8( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv16i8( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv16i8( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv16i8( %0, %1) ret %interleaved.vec } @@ -64,23 +64,23 @@ define @complex_add_v32i8( %a, , } @llvm.experimental.vector.deinterleave2.nxv32i8( %a) + %a.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32i8( %a) %a.real = extractvalue { , } %a.deinterleaved, 0 %a.imag = extractvalue { , } %a.deinterleaved, 1 - %b.deinterleaved = tail call { , } @llvm.experimental.vector.deinterleave2.nxv32i8( %b) + %b.deinterleaved = tail call { , } @llvm.vector.deinterleave2.nxv32i8( %b) %b.real = extractvalue { , } %b.deinterleaved, 0 %b.imag = extractvalue { , } %b.deinterleaved, 1 %0 = sub %b.real, %a.imag %1 = add %b.imag, %a.real - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv32i8( %0, %1) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv32i8( %0, %1) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i8() -declare @llvm.experimental.vector.interleave2.nxv8i8(, ) +declare { , } @llvm.vector.deinterleave2.nxv8i8() +declare @llvm.vector.interleave2.nxv8i8(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv16i8() -declare @llvm.experimental.vector.interleave2.nxv16i8(, ) +declare { , } @llvm.vector.deinterleave2.nxv16i8() +declare @llvm.vector.interleave2.nxv16i8(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv32i8() -declare @llvm.experimental.vector.interleave2.nxv32i8(, ) +declare { , } @llvm.vector.deinterleave2.nxv32i8() +declare @llvm.vector.interleave2.nxv32i8(, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll index 19318fdeeca7..ac2b21af29ab 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-predicated-scalable.ll @@ -69,14 +69,14 @@ vector.body: ; preds = %vector.body, %entry %vec.phi27 = phi [ zeroinitializer, %entry ], [ %16, %vector.body ] %scevgep = getelementptr i8, ptr %a, i64 %lsr.iv %scevgep34 = getelementptr i8, ptr %b, i64 %lsr.iv - %interleaved.mask = tail call @llvm.experimental.vector.interleave2.nxv4i1( %active.lane.mask, %active.lane.mask) + %interleaved.mask = tail call @llvm.vector.interleave2.nxv4i1( %active.lane.mask, %active.lane.mask) %wide.masked.vec = tail call @llvm.masked.load.nxv4f64.p0(ptr %scevgep, i32 8, %interleaved.mask, poison) - %strided.vec = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.masked.vec) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.masked.vec) %3 = extractvalue { , } %strided.vec, 0 %4 = extractvalue { , } %strided.vec, 1 - %interleaved.mask28 = tail call @llvm.experimental.vector.interleave2.nxv4i1( %active.lane.mask, %active.lane.mask) + %interleaved.mask28 = tail call @llvm.vector.interleave2.nxv4i1( %active.lane.mask, %active.lane.mask) %wide.masked.vec29 = tail call @llvm.masked.load.nxv4f64.p0(ptr %scevgep34, i32 8, %interleaved.mask28, poison) - %strided.vec30 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.masked.vec29) + %strided.vec30 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.masked.vec29) %5 = extractvalue { , } %strided.vec30, 0 %6 = extractvalue { , } %strided.vec30, 1 %7 = fmul fast %6, %3 @@ -175,13 +175,13 @@ vector.body: ; preds = %vector.body, %entry %4 = icmp ne %wide.load, zeroinitializer %scevgep49 = getelementptr i8, ptr %a, i64 %lsr.iv48 %scevgep50 = getelementptr i8, ptr %b, i64 %lsr.iv48 - %interleaved.mask = tail call @llvm.experimental.vector.interleave2.nxv4i1( %4, %4) + %interleaved.mask = tail call @llvm.vector.interleave2.nxv4i1( %4, %4) %wide.masked.vec = tail call @llvm.masked.load.nxv4f64.p0(ptr %scevgep49, i32 8, %interleaved.mask, poison) - %strided.vec = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.masked.vec) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.masked.vec) %5 = extractvalue { , } %strided.vec, 0 %6 = extractvalue { , } %strided.vec, 1 %wide.masked.vec32 = tail call @llvm.masked.load.nxv4f64.p0(ptr %scevgep50, i32 8, %interleaved.mask, poison) - %strided.vec33 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.masked.vec32) + %strided.vec33 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.masked.vec32) %7 = extractvalue { , } %strided.vec33, 0 %8 = extractvalue { , } %strided.vec33, 1 %9 = fmul fast %8, %5 @@ -279,14 +279,14 @@ vector.body: ; preds = %vector.body, %entry %scevgep38 = getelementptr i8, ptr %a, i64 %lsr.iv %scevgep39 = getelementptr i8, ptr %b, i64 %lsr.iv %5 = select %active.lane.mask, %4, zeroinitializer - %interleaved.mask = tail call @llvm.experimental.vector.interleave2.nxv4i1( %5, %5) + %interleaved.mask = tail call @llvm.vector.interleave2.nxv4i1( %5, %5) %wide.masked.vec = tail call @llvm.masked.load.nxv4f64.p0(ptr %scevgep38, i32 8, %interleaved.mask, poison) - %strided.vec = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.masked.vec) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.masked.vec) %6 = extractvalue { , } %strided.vec, 0 %7 = extractvalue { , } %strided.vec, 1 - %interleaved.mask31 = tail call @llvm.experimental.vector.interleave2.nxv4i1( %5, %5) + %interleaved.mask31 = tail call @llvm.vector.interleave2.nxv4i1( %5, %5) %wide.masked.vec32 = tail call @llvm.masked.load.nxv4f64.p0(ptr %scevgep39, i32 8, %interleaved.mask31, poison) - %strided.vec33 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.masked.vec32) + %strided.vec33 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.masked.vec32) %8 = extractvalue { , } %strided.vec33, 0 %9 = extractvalue { , } %strided.vec33, 1 %10 = fmul fast %9, %6 @@ -320,6 +320,6 @@ declare i64 @llvm.vscale.i64() declare @llvm.get.active.lane.mask.nxv2i1.i64(i64, i64) declare @llvm.masked.load.nxv2i32.p0(ptr nocapture, i32 immarg, , ) declare @llvm.masked.load.nxv4f64.p0(ptr nocapture, i32 immarg, , ) -declare @llvm.experimental.vector.interleave2.nxv4i1(, ) -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() +declare @llvm.vector.interleave2.nxv4i1(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f64() declare double @llvm.vector.reduce.fadd.nxv2f64(double, ) diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll index 5bef95910d90..af07519ad53d 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-reductions-scalable.ll @@ -64,11 +64,11 @@ vector.body: ; preds = %vector.body, %entry %scevgep46 = getelementptr i8, ptr %a, i64 %lsr.iv27 %scevgep47 = getelementptr i8, ptr %b, i64 %lsr.iv27 %wide.vec = load , ptr %scevgep46, align 8 - %3 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec) + %3 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec) %4 = extractvalue { , } %3, 0 %5 = extractvalue { , } %3, 1 %wide.vec30 = load , ptr %scevgep47, align 8 - %6 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec30) + %6 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec30) %7 = extractvalue { , } %6, 0 %8 = extractvalue { , } %6, 1 %9 = fmul fast %8, %4 @@ -156,11 +156,11 @@ vector.body: ; preds = %vector.body, %entry %scevgep46 = getelementptr i8, ptr %a, i64 %lsr.iv27 %scevgep47 = getelementptr i8, ptr %b, i64 %lsr.iv27 %wide.vec = load , ptr %scevgep46, align 8 - %3 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec) + %3 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec) %4 = extractvalue { , } %3, 0 %5 = extractvalue { , } %3, 1 %wide.vec30 = load , ptr %scevgep47, align 8 - %6 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec30) + %6 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec30) %7 = extractvalue { , } %6, 0 %8 = extractvalue { , } %6, 1 %9 = fmul fast %8, %4 @@ -266,16 +266,16 @@ vector.body: ; preds = %vector.body, %entry %scevgep62 = getelementptr i8, ptr %scevgep61, i64 %lsr.iv34 %wide.vec = load , ptr %scevgep57, align 8 %wide.vec32 = load , ptr %scevgep64, align 8 - %4 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec) - %5 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec32) + %4 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec) + %5 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec32) %6 = extractvalue { , } %4, 0 %7 = extractvalue { , } %5, 0 %8 = extractvalue { , } %4, 1 %9 = extractvalue { , } %5, 1 %wide.vec34 = load , ptr %scevgep58, align 8 %wide.vec35 = load , ptr %scevgep62, align 8 - %10 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec34) - %11 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec35) + %10 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec34) + %11 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec35) %12 = extractvalue { , } %10, 0 %13 = extractvalue { , } %11, 0 %14 = extractvalue { , } %10, 1 @@ -375,7 +375,7 @@ vector.body: ; preds = %vector.body, %entry %5 = add %wide.load, %vec.phi %6 = getelementptr inbounds %"class.std::complex", ptr %a, i64 %index %wide.vec = load , ptr %6, align 8 - %strided.vec = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %wide.vec) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %wide.vec) %7 = extractvalue { , } %strided.vec, 0 %8 = extractvalue { , } %strided.vec, 1 %9 = fadd fast %7, %vec.phi13 @@ -396,6 +396,6 @@ middle.block: ; preds = %vector.body declare i64 @llvm.vscale.i64() -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() +declare { , } @llvm.vector.deinterleave2.nxv4f64() declare double @llvm.vector.reduce.fadd.nxv2f64(double, ) declare i32 @llvm.vector.reduce.add.nxv2i32() diff --git a/llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll b/llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll index 17bf5ba6eb48..b4425c0c01e1 100644 --- a/llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll +++ b/llvm/test/CodeGen/AArch64/complex-deinterleaving-splat-scalable.ll @@ -28,10 +28,10 @@ define @complex_mul_const( %a, , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec48 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec48 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec48, 0 %3 = extractvalue { , } %strided.vec48, 1 %4 = fmul fast %3, %0 @@ -46,7 +46,7 @@ entry: %13 = fmul fast %9, splat (double 1.100000e+01) %14 = fmul fast %6, splat (double 3.000000e+00) %15 = fsub fast %13, %14 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %15, %12) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %15, %12) ret %interleaved.vec } @@ -83,10 +83,10 @@ entry: %broadcast.splat = shufflevector %broadcast.splatinsert, poison, zeroinitializer %broadcast.splatinsert49 = insertelement poison, double %c.coerce.fca.0.extract, i64 0 %broadcast.splat50 = shufflevector %broadcast.splatinsert49, poison, zeroinitializer - %strided.vec = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %a) + %strided.vec = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %a) %0 = extractvalue { , } %strided.vec, 0 %1 = extractvalue { , } %strided.vec, 1 - %strided.vec48 = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %b) + %strided.vec48 = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %b) %2 = extractvalue { , } %strided.vec48, 0 %3 = extractvalue { , } %strided.vec48, 1 %4 = fmul fast %3, %0 @@ -101,9 +101,9 @@ entry: %13 = fmul fast %9, %broadcast.splat50 %14 = fmul fast %6, %broadcast.splat %15 = fsub fast %13, %14 - %interleaved.vec = tail call @llvm.experimental.vector.interleave2.nxv4f64( %15, %12) + %interleaved.vec = tail call @llvm.vector.interleave2.nxv4f64( %15, %12) ret %interleaved.vec } -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare { , } @llvm.vector.deinterleave2.nxv4f64() +declare @llvm.vector.interleave2.nxv4f64(, ) diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll index 2ad5623b6551..c58db8290c87 100644 --- a/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll +++ b/llvm/test/CodeGen/AArch64/fixed-vector-deinterleave.ll @@ -25,7 +25,7 @@ define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q1 ; CHECK-GI-NEXT: fmov d0, d2 ; CHECK-GI-NEXT: ret - %retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec) + %retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec) ret {<2 x half>, <2 x half>} %retval } @@ -45,7 +45,7 @@ define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q1 ; CHECK-GI-NEXT: fmov d0, d2 ; CHECK-GI-NEXT: ret - %retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec) + %retval = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec) ret {<4 x half>, <4 x half>} %retval } @@ -56,7 +56,7 @@ define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %v ; CHECK-NEXT: uzp2 v1.8h, v0.8h, v1.8h ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec) + %retval = call {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half> %vec) ret {<8 x half>, <8 x half>} %retval } @@ -76,7 +76,7 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> % ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 killed $q1 ; CHECK-GI-NEXT: fmov d0, d2 ; CHECK-GI-NEXT: ret - %retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec) + %retval = call {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float> %vec) ret {<2 x float>, <2 x float>} %retval } @@ -87,7 +87,7 @@ define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> % ; CHECK-NEXT: uzp2 v1.4s, v0.4s, v1.4s ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec) + %retval = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %vec) ret {<4 x float>, <4 x float>} %retval } @@ -98,7 +98,7 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double ; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec) + %retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec) ret {<2 x double>, <2 x double>} %retval } @@ -111,7 +111,7 @@ define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) { ; CHECK-NEXT: uzp2 v1.16b, v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec) + %retval = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec) ret {<16 x i8>, <16 x i8>} %retval } @@ -122,7 +122,7 @@ define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) ; CHECK-NEXT: uzp2 v1.8h, v0.8h, v1.8h ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec) + %retval = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec) ret {<8 x i16>, <8 x i16>} %retval } @@ -133,7 +133,7 @@ define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_v8i32(<8 x i32> %vec) { ; CHECK-NEXT: uzp2 v1.4s, v0.4s, v1.4s ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec) + %retval = call {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32> %vec) ret {<4 x i32>, <4 x i32>} %retval } @@ -144,22 +144,22 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) { ; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec) + %retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec) ret {<2 x i64>, <2 x i64>} %retval } ; Floating declarations -declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>) -declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>) -declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>) -declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>) -declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>) -declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>) +declare {<2 x half>,<2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half>) +declare {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half>) +declare {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float>) +declare {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half>) +declare {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float>) +declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double>) ; Integer declarations -declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>) -declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>) -declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>) -declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>) +declare {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8>) +declare {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16>) +declare {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32>) +declare {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64>) diff --git a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll index eb81aff33e49..2e992964f598 100644 --- a/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll +++ b/llvm/test/CodeGen/AArch64/fixed-vector-interleave.ll @@ -7,7 +7,7 @@ define <4 x half> @interleave2_v4f16(<2 x half> %vec0, <2 x half> %vec1) { ; CHECK: // %bb.0: ; CHECK-NEXT: zip1 v0.4h, v0.4h, v1.4h ; CHECK-NEXT: ret - %retval = call <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half> %vec0, <2 x half> %vec1) + %retval = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %vec0, <2 x half> %vec1) ret <4 x half> %retval } @@ -28,7 +28,7 @@ define <8 x half> @interleave2_v8f16(<4 x half> %vec0, <4 x half> %vec1) { ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-GI-NEXT: zip1 v0.8h, v0.8h, v1.8h ; CHECK-GI-NEXT: ret - %retval = call <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1) + %retval = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %vec0, <4 x half> %vec1) ret <8 x half> %retval } @@ -39,7 +39,7 @@ define <16 x half> @interleave2_v16f16(<8 x half> %vec0, <8 x half> %vec1) { ; CHECK-NEXT: zip2 v1.8h, v0.8h, v1.8h ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half> %vec0, <8 x half> %vec1) + %retval = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %vec0, <8 x half> %vec1) ret <16 x half> %retval } @@ -59,7 +59,7 @@ define <4 x float> @interleave2_v4f32(<2 x float> %vec0, <2 x float> %vec1) { ; CHECK-GI-NEXT: // kill: def $d1 killed $d1 def $q1 ; CHECK-GI-NEXT: zip1 v0.4s, v0.4s, v1.4s ; CHECK-GI-NEXT: ret - %retval = call <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1) + %retval = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %vec0, <2 x float> %vec1) ret <4 x float> %retval } @@ -70,7 +70,7 @@ define <8 x float> @interleave2_v8f32(<4 x float> %vec0, <4 x float> %vec1) { ; CHECK-NEXT: zip2 v1.4s, v0.4s, v1.4s ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %vec0, <4 x float> %vec1) + %retval = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %vec0, <4 x float> %vec1) ret <8 x float> %retval } @@ -81,7 +81,7 @@ define <4 x double> @interleave2_v4f64(<2 x double> %vec0, <2 x double> %vec1) { ; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call <4 x double>@llvm.experimental.vector.interleave2.v4f64(<2 x double> %vec0, <2 x double> %vec1) + %retval = call <4 x double>@llvm.vector.interleave2.v4f64(<2 x double> %vec0, <2 x double> %vec1) ret <4 x double> %retval } @@ -94,7 +94,7 @@ define <32 x i8> @interleave2_v32i8(<16 x i8> %vec0, <16 x i8> %vec1) { ; CHECK-NEXT: zip2 v1.16b, v0.16b, v1.16b ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call <32 x i8> @llvm.experimental.vector.interleave2.v32i8(<16 x i8> %vec0, <16 x i8> %vec1) + %retval = call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %vec0, <16 x i8> %vec1) ret <32 x i8> %retval } @@ -105,7 +105,7 @@ define <16 x i16> @interleave2_v16i16(<8 x i16> %vec0, <8 x i16> %vec1) { ; CHECK-NEXT: zip2 v1.8h, v0.8h, v1.8h ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %vec0, <8 x i16> %vec1) + %retval = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %vec0, <8 x i16> %vec1) ret <16 x i16> %retval } @@ -116,7 +116,7 @@ define <8 x i32> @interleave2_v8i32(<4 x i32> %vec0, <4 x i32> %vec1) { ; CHECK-NEXT: zip2 v1.4s, v0.4s, v1.4s ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %vec0, <4 x i32> %vec1) + %retval = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %vec0, <4 x i32> %vec1) ret <8 x i32> %retval } @@ -127,22 +127,22 @@ define <4 x i64> @interleave2_v4i64(<2 x i64> %vec0, <2 x i64> %vec1) { ; CHECK-NEXT: zip2 v1.2d, v0.2d, v1.2d ; CHECK-NEXT: mov v0.16b, v2.16b ; CHECK-NEXT: ret - %retval = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %vec0, <2 x i64> %vec1) + %retval = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %vec0, <2 x i64> %vec1) ret <4 x i64> %retval } ; Float declarations -declare <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half>, <2 x half>) -declare <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half>, <4 x half>) -declare <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half>, <8 x half>) -declare <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float>, <2 x float>) -declare <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float>, <4 x float>) -declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double>, <2 x double>) +declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>) +declare <8 x half> @llvm.vector.interleave2.v8f16(<4 x half>, <4 x half>) +declare <16 x half> @llvm.vector.interleave2.v16f16(<8 x half>, <8 x half>) +declare <4 x float> @llvm.vector.interleave2.v4f32(<2 x float>, <2 x float>) +declare <8 x float> @llvm.vector.interleave2.v8f32(<4 x float>, <4 x float>) +declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double>, <2 x double>) ; Integer declarations -declare <32 x i8> @llvm.experimental.vector.interleave2.v32i8(<16 x i8>, <16 x i8>) -declare <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) -declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) -declare <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) +declare <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8>, <16 x i8>) +declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) +declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll index 0eee19ad2adb..cff7759c72c9 100644 --- a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll +++ b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-neon.ll @@ -15,7 +15,7 @@ define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 { ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ret - %res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a) + %res = call <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8> %a) ret <16 x i8> %res } @@ -26,7 +26,7 @@ define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 { ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ret - %res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a) + %res = call <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16> %a) ret <8 x i16> %res } @@ -35,7 +35,7 @@ define <2 x i16> @reverse_v2i16(<2 x i16> %a) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: rev64 v0.2s, v0.2s ; CHECK-NEXT: ret - %res = call <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16> %a) + %res = call <2 x i16> @llvm.vector.reverse.v2i16(<2 x i16> %a) ret <2 x i16> %res } @@ -44,7 +44,7 @@ define <2 x i32> @reverse_v2i32(<2 x i32> %a) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: rev64 v0.2s, v0.2s ; CHECK-NEXT: ret - %res = call <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32> %a) + %res = call <2 x i32> @llvm.vector.reverse.v2i32(<2 x i32> %a) ret <2 x i32> %res } @@ -55,7 +55,7 @@ define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 { ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ret - %res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a) + %res = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> %a) ret <4 x i32> %res } @@ -65,7 +65,7 @@ define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 { ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ret - %res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a) + %res = call <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64> %a) ret <2 x i64> %res } @@ -76,7 +76,7 @@ define <8 x half> @reverse_v8f16(<8 x half> %a) #0 { ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ret - %res = call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> %a) + %res = call <8 x half> @llvm.vector.reverse.v8f16(<8 x half> %a) ret <8 x half> %res } @@ -85,7 +85,7 @@ define <2 x float> @reverse_v2f32(<2 x float> %a) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: rev64 v0.2s, v0.2s ; CHECK-NEXT: ret - %res = call <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float> %a) + %res = call <2 x float> @llvm.vector.reverse.v2f32(<2 x float> %a) ret <2 x float> %res } @@ -96,7 +96,7 @@ define <4 x float> @reverse_v4f32(<4 x float> %a) #0 { ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ret - %res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a) + %res = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %a) ret <4 x float> %res } @@ -106,7 +106,7 @@ define <2 x double> @reverse_v2f64(<2 x double> %a) #0 { ; CHECK-NEXT: ext v0.16b, v0.16b, v0.16b, #8 ; CHECK-NEXT: ret - %res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a) + %res = call <2 x double> @llvm.vector.reverse.v2f64(<2 x double> %a) ret <2 x double> %res } @@ -117,7 +117,7 @@ define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 { ; CHECK-NEXT: rev64 v0.2s, v0.2s ; CHECK-NEXT: ret - %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a) + %res = call <2 x i8> @llvm.vector.reverse.v2i8(<2 x i8> %a) ret <2 x i8> %res } @@ -144,7 +144,7 @@ define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 { ; CHECK-FASTISEL-NEXT: add sp, sp, #16 ; CHECK-FASTISEL-NEXT: ret - %res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a) + %res = call <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32> %a) ret <8 x i32> %res } @@ -182,23 +182,23 @@ define <16 x float> @reverse_v16f32(<16 x float> %a) #0 { ; CHECK-FASTISEL-NEXT: add sp, sp, #32 ; CHECK-FASTISEL-NEXT: ret - %res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a) + %res = call <16 x float> @llvm.vector.reverse.v16f32(<16 x float> %a) ret <16 x float> %res } -declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>) -declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>) -declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>) -declare <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16>) -declare <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32>) -declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>) -declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>) -declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>) -declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>) -declare <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float>) -declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>) -declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>) -declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>) +declare <2 x i8> @llvm.vector.reverse.v2i8(<2 x i8>) +declare <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8>) +declare <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16>) +declare <2 x i16> @llvm.vector.reverse.v2i16(<2 x i16>) +declare <2 x i32> @llvm.vector.reverse.v2i32(<2 x i32>) +declare <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32>) +declare <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32>) +declare <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64>) +declare <8 x half> @llvm.vector.reverse.v8f16(<8 x half>) +declare <2 x float> @llvm.vector.reverse.v2f32(<2 x float>) +declare <4 x float> @llvm.vector.reverse.v4f32(<4 x float>) +declare <16 x float> @llvm.vector.reverse.v16f32(<16 x float>) +declare <2 x double> @llvm.vector.reverse.v2f64(<2 x double>) attributes #0 = { nounwind "target-features"="+neon" } diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll index 4d5045feca08..a84e6e7bcae8 100644 --- a/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll +++ b/llvm/test/CodeGen/AArch64/named-vector-shuffle-reverse-sve.ll @@ -14,7 +14,7 @@ define @reverse_nxv2i1( %a) #0 { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i1( %a) + %res = call @llvm.vector.reverse.nxv2i1( %a) ret %res } @@ -24,7 +24,7 @@ define @reverse_nxv4i1( %a) #0 { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4i1( %a) + %res = call @llvm.vector.reverse.nxv4i1( %a) ret %res } @@ -34,7 +34,7 @@ define @reverse_nxv8i1( %a) #0 { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i1( %a) + %res = call @llvm.vector.reverse.nxv8i1( %a) ret %res } @@ -44,7 +44,7 @@ define @reverse_nxv16i1( %a) #0 { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16i1( %a) + %res = call @llvm.vector.reverse.nxv16i1( %a) ret %res } @@ -70,7 +70,7 @@ define @reverse_nxv32i1( %a) #0 { ; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-FASTISEL-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv32i1( %a) + %res = call @llvm.vector.reverse.nxv32i1( %a) ret %res } @@ -84,7 +84,7 @@ define @reverse_nxv16i8( %a) #0 { ; CHECK-NEXT: rev z0.b, z0.b ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16i8( %a) + %res = call @llvm.vector.reverse.nxv16i8( %a) ret %res } @@ -94,7 +94,7 @@ define @reverse_nxv8i16( %a) #0 { ; CHECK-NEXT: rev z0.h, z0.h ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i16( %a) + %res = call @llvm.vector.reverse.nxv8i16( %a) ret %res } @@ -104,7 +104,7 @@ define @reverse_nxv4i32( %a) #0 { ; CHECK-NEXT: rev z0.s, z0.s ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4i32( %a) + %res = call @llvm.vector.reverse.nxv4i32( %a) ret %res } @@ -114,7 +114,7 @@ define @reverse_nxv2i64( %a) #0 { ; CHECK-NEXT: rev z0.d, z0.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i64( %a) + %res = call @llvm.vector.reverse.nxv2i64( %a) ret %res } @@ -124,7 +124,7 @@ define @reverse_nxv2f16( %a) #0 { ; CHECK-NEXT: rev z0.d, z0.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2f16( %a) + %res = call @llvm.vector.reverse.nxv2f16( %a) ret %res } @@ -134,7 +134,7 @@ define @reverse_nxv4f16( %a) #0 { ; CHECK-NEXT: rev z0.s, z0.s ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4f16( %a) + %res = call @llvm.vector.reverse.nxv4f16( %a) ret %res } @@ -144,7 +144,7 @@ define @reverse_nxv8f16( %a) #0 { ; CHECK-NEXT: rev z0.h, z0.h ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8f16( %a) + %res = call @llvm.vector.reverse.nxv8f16( %a) ret %res } @@ -154,7 +154,7 @@ define @reverse_nxv2bf16( %a) #1 { ; CHECK-NEXT: rev z0.d, z0.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2bf16( %a) + %res = call @llvm.vector.reverse.nxv2bf16( %a) ret %res } @@ -164,7 +164,7 @@ define @reverse_nxv4bf16( %a) #1 { ; CHECK-NEXT: rev z0.s, z0.s ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4bf16( %a) + %res = call @llvm.vector.reverse.nxv4bf16( %a) ret %res } @@ -174,7 +174,7 @@ define @reverse_nxv8bf16( %a) #1 { ; CHECK-NEXT: rev z0.h, z0.h ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8bf16( %a) + %res = call @llvm.vector.reverse.nxv8bf16( %a) ret %res } @@ -184,7 +184,7 @@ define @reverse_nxv2f32( %a) #0 { ; CHECK-NEXT: rev z0.d, z0.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2f32( %a) ret %res + %res = call @llvm.vector.reverse.nxv2f32( %a) ret %res } define @reverse_nxv4f32( %a) #0 { @@ -193,7 +193,7 @@ define @reverse_nxv4f32( %a) #0 { ; CHECK-NEXT: rev z0.s, z0.s ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4f32( %a) ret %res + %res = call @llvm.vector.reverse.nxv4f32( %a) ret %res } define @reverse_nxv2f64( %a) #0 { @@ -202,7 +202,7 @@ define @reverse_nxv2f64( %a) #0 { ; CHECK-NEXT: rev z0.d, z0.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2f64( %a) + %res = call @llvm.vector.reverse.nxv2f64( %a) ret %res } @@ -213,7 +213,7 @@ define @reverse_nxv2i8( %a) #0 { ; CHECK-NEXT: rev z0.d, z0.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i8( %a) + %res = call @llvm.vector.reverse.nxv2i8( %a) ret %res } @@ -239,7 +239,7 @@ define @reverse_nxv8i32( %a) #0 { ; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-FASTISEL-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i32( %a) + %res = call @llvm.vector.reverse.nxv8i32( %a) ret %res } @@ -273,32 +273,32 @@ define @reverse_nxv16f32( %a) #0 { ; CHECK-FASTISEL-NEXT: ldr x29, [sp], #16 // 8-byte Folded Reload ; CHECK-FASTISEL-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16f32( %a) + %res = call @llvm.vector.reverse.nxv16f32( %a) ret %res } -declare @llvm.experimental.vector.reverse.nxv2i1() -declare @llvm.experimental.vector.reverse.nxv4i1() -declare @llvm.experimental.vector.reverse.nxv8i1() -declare @llvm.experimental.vector.reverse.nxv16i1() -declare @llvm.experimental.vector.reverse.nxv32i1() -declare @llvm.experimental.vector.reverse.nxv2i8() -declare @llvm.experimental.vector.reverse.nxv16i8() -declare @llvm.experimental.vector.reverse.nxv8i16() -declare @llvm.experimental.vector.reverse.nxv4i32() -declare @llvm.experimental.vector.reverse.nxv8i32() -declare @llvm.experimental.vector.reverse.nxv2i64() -declare @llvm.experimental.vector.reverse.nxv2f16() -declare @llvm.experimental.vector.reverse.nxv4f16() -declare @llvm.experimental.vector.reverse.nxv8f16() -declare @llvm.experimental.vector.reverse.nxv2bf16() -declare @llvm.experimental.vector.reverse.nxv4bf16() -declare @llvm.experimental.vector.reverse.nxv8bf16() -declare @llvm.experimental.vector.reverse.nxv2f32() -declare @llvm.experimental.vector.reverse.nxv4f32() -declare @llvm.experimental.vector.reverse.nxv16f32() -declare @llvm.experimental.vector.reverse.nxv2f64() +declare @llvm.vector.reverse.nxv2i1() +declare @llvm.vector.reverse.nxv4i1() +declare @llvm.vector.reverse.nxv8i1() +declare @llvm.vector.reverse.nxv16i1() +declare @llvm.vector.reverse.nxv32i1() +declare @llvm.vector.reverse.nxv2i8() +declare @llvm.vector.reverse.nxv16i8() +declare @llvm.vector.reverse.nxv8i16() +declare @llvm.vector.reverse.nxv4i32() +declare @llvm.vector.reverse.nxv8i32() +declare @llvm.vector.reverse.nxv2i64() +declare @llvm.vector.reverse.nxv2f16() +declare @llvm.vector.reverse.nxv4f16() +declare @llvm.vector.reverse.nxv8f16() +declare @llvm.vector.reverse.nxv2bf16() +declare @llvm.vector.reverse.nxv4bf16() +declare @llvm.vector.reverse.nxv8bf16() +declare @llvm.vector.reverse.nxv2f32() +declare @llvm.vector.reverse.nxv4f32() +declare @llvm.vector.reverse.nxv16f32() +declare @llvm.vector.reverse.nxv2f64() attributes #0 = { nounwind "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll index 9210a5ec1c8b..f2e62bc4f3c8 100644 --- a/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll +++ b/llvm/test/CodeGen/AArch64/named-vector-shuffles-neon.ll @@ -12,7 +12,7 @@ define <16 x i8> @splice_v16i8_idx(<16 x i8> %a, <16 x i8> %b) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1 ; CHECK-NEXT: ret - %res = call <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1) + %res = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 1) ret <16 x i8> %res } @@ -21,7 +21,7 @@ define <2 x double> @splice_v2f64_idx(<2 x double> %a, <2 x double> %b) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8 ; CHECK-NEXT: ret - %res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 1) + %res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 1) ret <2 x double> %res } @@ -31,7 +31,7 @@ define <2 x i8> @splice_v2i8_idx(<2 x i8> %a, <2 x i8> %b) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4 ; CHECK-NEXT: ret - %res = call <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 1) + %res = call <2 x i8> @llvm.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 1) ret <2 x i8> %res } @@ -42,7 +42,7 @@ define <8 x i32> @splice_v8i32_idx(<8 x i32> %a, <8 x i32> %b) #0 { ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4 ; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4 ; CHECK-NEXT: ret - %res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 5) + %res = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 5) ret <8 x i32> %res } @@ -56,7 +56,7 @@ define <16 x float> @splice_v16f32_idx(<16 x float> %a, <16 x float> %b) #0 { ; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12 ; CHECK-NEXT: mov v2.16b, v6.16b ; CHECK-NEXT: ret - %res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7) + %res = call <16 x float> @llvm.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 7) ret <16 x float> %res } @@ -69,7 +69,7 @@ define <16 x i8> @splice_v16i8(<16 x i8> %a, <16 x i8> %b) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #1 ; CHECK-NEXT: ret - %res = call <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 -15) + %res = call <16 x i8> @llvm.vector.splice.v16i8(<16 x i8> %a, <16 x i8> %b, i32 -15) ret <16 x i8> %res } @@ -78,7 +78,7 @@ define <2 x double> @splice_v2f64(<2 x double> %a, <2 x double> %b) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: ext v0.16b, v0.16b, v1.16b, #8 ; CHECK-NEXT: ret - %res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -1) + %res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -1) ret <2 x double> %res } @@ -88,7 +88,7 @@ define <2 x i8> @splice_v2i8(<2 x i8> %a, <2 x i8> %b) #0 { ; CHECK: // %bb.0: ; CHECK-NEXT: ext v0.8b, v0.8b, v1.8b, #4 ; CHECK-NEXT: ret - %res = call <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 -1) + %res = call <2 x i8> @llvm.vector.splice.v2i8(<2 x i8> %a, <2 x i8> %b, i32 -1) ret <2 x i8> %res } @@ -99,7 +99,7 @@ define <8 x i32> @splice_v8i32(<8 x i32> %a, <8 x i32> %b) #0 { ; CHECK-NEXT: ext v0.16b, v1.16b, v2.16b, #4 ; CHECK-NEXT: ext v1.16b, v2.16b, v3.16b, #4 ; CHECK-NEXT: ret - %res = call <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 -3) + %res = call <8 x i32> @llvm.vector.splice.v8i32(<8 x i32> %a, <8 x i32> %b, i32 -3) ret <8 x i32> %res } @@ -113,14 +113,14 @@ define <16 x float> @splice_v16f32(<16 x float> %a, <16 x float> %b) #0 { ; CHECK-NEXT: ext v3.16b, v4.16b, v5.16b, #12 ; CHECK-NEXT: mov v2.16b, v6.16b ; CHECK-NEXT: ret - %res = call <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9) + %res = call <16 x float> @llvm.vector.splice.v16f32(<16 x float> %a, <16 x float> %b, i32 -9) ret <16 x float> %res } -declare <2 x i8> @llvm.experimental.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32) -declare <16 x i8> @llvm.experimental.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32) -declare <8 x i32> @llvm.experimental.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32) -declare <16 x float> @llvm.experimental.vector.splice.v16f32(<16 x float>, <16 x float>, i32) -declare <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double>, <2 x double>, i32) +declare <2 x i8> @llvm.vector.splice.v2i8(<2 x i8>, <2 x i8>, i32) +declare <16 x i8> @llvm.vector.splice.v16i8(<16 x i8>, <16 x i8>, i32) +declare <8 x i32> @llvm.vector.splice.v8i32(<8 x i32>, <8 x i32>, i32) +declare <16 x float> @llvm.vector.splice.v16f32(<16 x float>, <16 x float>, i32) +declare <2 x double> @llvm.vector.splice.v2f64(<2 x double>, <2 x double>, i32) attributes #0 = { nounwind "target-features"="+neon" } diff --git a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll index fac96e07de54..f5763cd61033 100644 --- a/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll +++ b/llvm/test/CodeGen/AArch64/named-vector-shuffles-sve.ll @@ -11,7 +11,7 @@ define @splice_nxv16i8_zero_idx( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 0) ret %res } @@ -20,7 +20,7 @@ define @splice_nxv16i8_first_idx( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 1) ret %res } @@ -29,7 +29,7 @@ define @splice_nxv16i8_last_idx( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 255) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 255) ret %res } @@ -38,7 +38,7 @@ define @splice_nxv8i16_first_idx( %a, @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 1) ret %res } @@ -47,7 +47,7 @@ define @splice_nxv4i32_first_idx( %a, @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 1) ret %res } @@ -56,7 +56,7 @@ define @splice_nxv4i32_last_idx( %a, @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 63) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 63) ret %res } @@ -65,7 +65,7 @@ define @splice_nxv2i64_first_idx( %a, @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 1) ret %res } @@ -74,7 +74,7 @@ define @splice_nxv2i64_last_idx( %a, @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 31) ret %res } @@ -85,7 +85,7 @@ define @splice_nxv2f16_neg_idx( %a, @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 -1) ret %res } @@ -96,7 +96,7 @@ define @splice_nxv2f16_neg2_idx( %a, @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 -2) ret %res } @@ -105,7 +105,7 @@ define @splice_nxv2f16_first_idx( %a, @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 1) ret %res } @@ -114,7 +114,7 @@ define @splice_nxv2f16_last_idx( %a, @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 31) ret %res } @@ -125,7 +125,7 @@ define @splice_nxv4f16_neg_idx( %a, @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 -1) ret %res } @@ -136,7 +136,7 @@ define @splice_nxv4f16_neg3_idx( %a, @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 -3) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 -3) ret %res } @@ -145,7 +145,7 @@ define @splice_nxv4f16_first_idx( %a, @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 1) ret %res } @@ -154,7 +154,7 @@ define @splice_nxv4f16_last_idx( %a, @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 63) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 63) ret %res } @@ -163,7 +163,7 @@ define @splice_nxv8f16_first_idx( %a, @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 1) ret %res } @@ -172,7 +172,7 @@ define @splice_nxv8f16_last_idx( %a, @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 127) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 127) ret %res } @@ -183,7 +183,7 @@ define @splice_nxv2f32_neg_idx( %a, @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 -1) ret %res } @@ -194,7 +194,7 @@ define @splice_nxv2f32_neg2_idx( %a, @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 -2) ret %res } @@ -203,7 +203,7 @@ define @splice_nxv2f32_first_idx( %a, < ; CHECK: // %bb.0: ; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 1) ret %res } @@ -212,7 +212,7 @@ define @splice_nxv2f32_last_idx( %a, @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 31) ret %res } @@ -221,7 +221,7 @@ define @splice_nxv4f32_first_idx( %a, < ; CHECK: // %bb.0: ; CHECK-NEXT: ext z0.b, z0.b, z1.b, #4 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 1) ret %res } @@ -230,7 +230,7 @@ define @splice_nxv4f32_last_idx( %a, @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 63) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 63) ret %res } @@ -239,7 +239,7 @@ define @splice_nxv2f64_first_idx( %a, ; CHECK: // %bb.0: ; CHECK-NEXT: ext z0.b, z0.b, z1.b, #8 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 1) ret %res } @@ -248,7 +248,7 @@ define @splice_nxv2f64_last_idx( %a, ; CHECK: // %bb.0: ; CHECK-NEXT: ext z0.b, z0.b, z1.b, #248 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 31) ret %res } @@ -263,7 +263,7 @@ define @splice_nxv2i1_idx( %a, @llvm.experimental.vector.splice.nxv2i1( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv2i1( %a, %b, i32 1) ret %res } @@ -278,7 +278,7 @@ define @splice_nxv4i1_idx( %a, @llvm.experimental.vector.splice.nxv4i1( %a, %b, i32 2) + %res = call @llvm.vector.splice.nxv4i1( %a, %b, i32 2) ret %res } @@ -293,7 +293,7 @@ define @splice_nxv8i1_idx( %a, @llvm.experimental.vector.splice.nxv8i1( %a, %b, i32 4) + %res = call @llvm.vector.splice.nxv8i1( %a, %b, i32 4) ret %res } @@ -308,7 +308,7 @@ define @splice_nxv16i1_idx( %a, @llvm.experimental.vector.splice.nxv16i1( %a, %b, i32 8) + %res = call @llvm.vector.splice.nxv16i1( %a, %b, i32 8) ret %res } @@ -318,7 +318,7 @@ define @splice_nxv2i8_idx( %a, @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv2i8( %a, %b, i32 1) ret %res } @@ -340,7 +340,7 @@ define @splice_nxv8i32_idx( %a, @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 2) + %res = call @llvm.vector.splice.nxv8i32( %a, %b, i32 2) ret %res } @@ -373,7 +373,7 @@ define @splice_nxv16f32_16( %a, @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 16) + %res = call @llvm.vector.splice.nxv16f32( %a, %b, i32 16) ret %res } @@ -388,7 +388,7 @@ define @splice_nxv16i8( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -16) ret %res } @@ -399,7 +399,7 @@ define @splice_nxv16i8_neg32( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -32) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -32) ret %res } @@ -410,7 +410,7 @@ define @splice_nxv16i8_neg64( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -64) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -64) ret %res } @@ -421,7 +421,7 @@ define @splice_nxv16i8_neg128( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -128) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -128) ret %res } @@ -432,7 +432,7 @@ define @splice_nxv16i8_neg256( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -256) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -256) ret %res } @@ -443,7 +443,7 @@ define @splice_nxv16i8_1( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -1) ret %res } @@ -466,7 +466,7 @@ define @splice_nxv16i8_neg17( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -17) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -17) ret %res } @@ -477,7 +477,7 @@ define @splice_nxv8i16( %a, @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 -8) ret %res } @@ -488,7 +488,7 @@ define @splice_nxv8i16_1( %a, @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 -1) ret %res } @@ -511,7 +511,7 @@ define @splice_nxv8i16_neg9( %a, @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 -9) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 -9) ret %res } @@ -522,7 +522,7 @@ define @splice_nxv4i32( %a, @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 -4) ret %res } @@ -533,7 +533,7 @@ define @splice_nxv4i32_1( %a, @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 -1) ret %res } @@ -544,7 +544,7 @@ define @splice_nxv4i32_neg5( %a, @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 -5) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 -5) ret %res } @@ -555,7 +555,7 @@ define @splice_nxv2i64( %a, @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 -2) ret %res } @@ -566,7 +566,7 @@ define @splice_nxv2i64_1( %a, @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 -1) ret %res } @@ -577,7 +577,7 @@ define @splice_nxv2i64_neg3( %a, @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 -3) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 -3) ret %res } @@ -588,7 +588,7 @@ define @splice_nxv8f16( %a, @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 -8) ret %res } @@ -599,7 +599,7 @@ define @splice_nxv8f16_1( %a, @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 -1) ret %res } @@ -622,7 +622,7 @@ define @splice_nxv8f16_neg9( %a, @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 -9) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 -9) ret %res } @@ -633,7 +633,7 @@ define @splice_nxv4f32( %a, @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 -4) ret %res } @@ -644,7 +644,7 @@ define @splice_nxv4f32_1( %a, @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 -1) ret %res } @@ -655,7 +655,7 @@ define @splice_nxv4f32_neg5( %a, @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 -5) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 -5) ret %res } @@ -666,7 +666,7 @@ define @splice_nxv2f64( %a, @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 -2) ret %res } @@ -677,7 +677,7 @@ define @splice_nxv2f64_1( %a, @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 -1) ret %res } @@ -688,7 +688,7 @@ define @splice_nxv2f64_neg3( %a, @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -3) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 -3) ret %res } @@ -705,7 +705,7 @@ define @splice_nxv2i1( %a, ; CHECK-NEXT: and z1.d, z1.d, #0x1 ; CHECK-NEXT: cmpne p0.d, p0/z, z1.d, #0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2i1( %a, %b, i32 -1) ret %res } @@ -722,7 +722,7 @@ define @splice_nxv4i1( %a, ; CHECK-NEXT: and z1.s, z1.s, #0x1 ; CHECK-NEXT: cmpne p0.s, p0/z, z1.s, #0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4i1( %a, %b, i32 -1) ret %res } @@ -739,7 +739,7 @@ define @splice_nxv8i1( %a, ; CHECK-NEXT: and z1.h, z1.h, #0x1 ; CHECK-NEXT: cmpne p0.h, p0/z, z1.h, #0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8i1( %a, %b, i32 -1) ret %res } @@ -756,7 +756,7 @@ define @splice_nxv16i1( %a, @llvm.experimental.vector.splice.nxv16i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16i1( %a, %b, i32 -1) ret %res } @@ -768,7 +768,7 @@ define @splice_nxv2i8( %a, ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: splice z0.d, p0, z0.d, z1.d ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv2i8( %a, %b, i32 -2) ret %res } @@ -793,7 +793,7 @@ define @splice_nxv8i32( %a, @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv8i32( %a, %b, i32 -8) ret %res } @@ -826,26 +826,26 @@ define @splice_nxv16f32_neg17( %a, @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 -17) + %res = call @llvm.vector.splice.nxv16f32( %a, %b, i32 -17) ret %res } -declare @llvm.experimental.vector.splice.nxv2i1(, , i32) -declare @llvm.experimental.vector.splice.nxv4i1(, , i32) -declare @llvm.experimental.vector.splice.nxv8i1(, , i32) -declare @llvm.experimental.vector.splice.nxv16i1(, , i32) -declare @llvm.experimental.vector.splice.nxv2i8(, , i32) -declare @llvm.experimental.vector.splice.nxv16i8(, , i32) -declare @llvm.experimental.vector.splice.nxv8i16(, , i32) -declare @llvm.experimental.vector.splice.nxv4i32(, , i32) -declare @llvm.experimental.vector.splice.nxv8i32(, , i32) -declare @llvm.experimental.vector.splice.nxv2i64(, , i32) -declare @llvm.experimental.vector.splice.nxv2f16(, , i32) -declare @llvm.experimental.vector.splice.nxv4f16(, , i32) -declare @llvm.experimental.vector.splice.nxv8f16(, , i32) -declare @llvm.experimental.vector.splice.nxv2f32(, , i32) -declare @llvm.experimental.vector.splice.nxv4f32(, , i32) -declare @llvm.experimental.vector.splice.nxv16f32(, , i32) -declare @llvm.experimental.vector.splice.nxv2f64(, , i32) +declare @llvm.vector.splice.nxv2i1(, , i32) +declare @llvm.vector.splice.nxv4i1(, , i32) +declare @llvm.vector.splice.nxv8i1(, , i32) +declare @llvm.vector.splice.nxv16i1(, , i32) +declare @llvm.vector.splice.nxv2i8(, , i32) +declare @llvm.vector.splice.nxv16i8(, , i32) +declare @llvm.vector.splice.nxv8i16(, , i32) +declare @llvm.vector.splice.nxv4i32(, , i32) +declare @llvm.vector.splice.nxv8i32(, , i32) +declare @llvm.vector.splice.nxv2i64(, , i32) +declare @llvm.vector.splice.nxv2f16(, , i32) +declare @llvm.vector.splice.nxv4f16(, , i32) +declare @llvm.vector.splice.nxv8f16(, , i32) +declare @llvm.vector.splice.nxv2f32(, , i32) +declare @llvm.vector.splice.nxv4f32(, , i32) +declare @llvm.vector.splice.nxv16f32(, , i32) +declare @llvm.vector.splice.nxv2f64(, , i32) attributes #0 = { nounwind "target-features"="+sve" } diff --git a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll index 9920bc6048e8..478f4a689d3c 100644 --- a/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll +++ b/llvm/test/CodeGen/AArch64/sve-vector-deinterleave.ll @@ -9,7 +9,7 @@ define {, } @vector_deinterleave_nxv2f16_n ; CHECK-NEXT: uzp1 z0.d, z2.d, z1.d ; CHECK-NEXT: uzp2 z1.d, z2.d, z1.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4f16( %vec) ret {, } %retval } @@ -21,7 +21,7 @@ define {, } @vector_deinterleave_nxv4f16_n ; CHECK-NEXT: uzp1 z0.s, z2.s, z1.s ; CHECK-NEXT: uzp2 z1.s, z2.s, z1.s ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8f16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8f16( %vec) ret {, } %retval } @@ -32,7 +32,7 @@ define {, } @vector_deinterleave_nxv8f16_n ; CHECK-NEXT: uzp2 z1.h, z0.h, z1.h ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16f16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv16f16( %vec) ret {, } %retval } @@ -44,7 +44,7 @@ define {, } @vector_deinterleave_nxv2f32 ; CHECK-NEXT: uzp1 z0.d, z2.d, z1.d ; CHECK-NEXT: uzp2 z1.d, z2.d, z1.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f32( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4f32( %vec) ret {, } %retval } @@ -55,7 +55,7 @@ define {, } @vector_deinterleave_nxv4f32 ; CHECK-NEXT: uzp2 z1.s, z0.s, z1.s ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8f32( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8f32( %vec) ret {, } %retval } @@ -66,7 +66,7 @@ define {, } @vector_deinterleave_nxv2f ; CHECK-NEXT: uzp2 z1.d, z0.d, z1.d ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f64( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4f64( %vec) ret {, } %retval } @@ -79,7 +79,7 @@ define {, } @vector_deinterleave_nxv16i8_nxv ; CHECK-NEXT: uzp2 z1.b, z0.b, z1.b ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32i8( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv32i8( %vec) ret {, } %retval } @@ -90,7 +90,7 @@ define {, } @vector_deinterleave_nxv8i16_nxv ; CHECK-NEXT: uzp2 z1.h, z0.h, z1.h ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv16i16( %vec) ret {, } %retval } @@ -101,7 +101,7 @@ define {, } @vector_deinterleave_nxv4i32_nxv ; CHECK-NEXT: uzp2 z1.s, z0.s, z1.s ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8i32( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8i32( %vec) ret {, } %retval } @@ -112,7 +112,7 @@ define {, } @vector_deinterleave_nxv2i64_nxv ; CHECK-NEXT: uzp2 z1.d, z0.d, z1.d ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4i64( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4i64( %vec) ret {, } %retval } @@ -124,7 +124,7 @@ define {, } @vector_deinterleave_nxv16i1_nxv ; CHECK-NEXT: uzp2 p1.b, p0.b, p1.b ; CHECK-NEXT: mov p0.b, p2.b ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32i1( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv32i1( %vec) ret {, } %retval } @@ -136,7 +136,7 @@ define {, } @vector_deinterleave_nxv8i1_nxv16i ; CHECK-NEXT: uzp1 p0.h, p2.h, p1.h ; CHECK-NEXT: uzp2 p1.h, p2.h, p1.h ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i1( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv16i1( %vec) ret {, } %retval } @@ -148,7 +148,7 @@ define {, } @vector_deinterleave_nxv4i1_nxv8i1 ; CHECK-NEXT: uzp1 p0.s, p2.s, p1.s ; CHECK-NEXT: uzp2 p1.s, p2.s, p1.s ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8i1( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8i1( %vec) ret {, } %retval } @@ -160,7 +160,7 @@ define {, } @vector_deinterleave_nxv2i1_nxv4i1 ; CHECK-NEXT: uzp1 p0.d, p2.d, p1.d ; CHECK-NEXT: uzp2 p1.d, p2.d, p1.d ; CHECK-NEXT: ret - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4i1( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4i1( %vec) ret {, } %retval } @@ -178,7 +178,7 @@ define {, } @vector_deinterleave_nxv4i64_nxv ; CHECK-NEXT: mov z1.d, z4.d ; CHECK-NEXT: mov z2.d, z6.d ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8i64( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv8i64( %vec) ret {, } %retval } @@ -201,7 +201,7 @@ define {, } @vector_deinterleave_nxv8i64_nx ; CHECK-NEXT: mov z5.d, z29.d ; CHECK-NEXT: mov z6.d, z30.d ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i64( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv16i64( %vec) ret {, } %retval } @@ -216,7 +216,7 @@ define {, } @vector_deinterleave_nxv8i8_nxv16i ; CHECK-NEXT: uzp1 z0.h, z2.h, z1.h ; CHECK-NEXT: uzp2 z1.h, z2.h, z1.h ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i8( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv16i8( %vec) ret {, } %retval } @@ -228,7 +228,7 @@ define {, } @vector_deinterleave_nxv4i16_nxv ; CHECK-NEXT: uzp1 z0.s, z2.s, z1.s ; CHECK-NEXT: uzp2 z1.s, z2.s, z1.s ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8i16( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv8i16( %vec) ret {, } %retval } @@ -240,35 +240,35 @@ define {, } @vector_deinterleave_nxv2i32_nxv ; CHECK-NEXT: uzp1 z0.d, z2.d, z1.d ; CHECK-NEXT: uzp2 z1.d, z2.d, z1.d ; CHECK-NEXT: ret -%retval = call {,} @llvm.experimental.vector.deinterleave2.nxv4i32( %vec) +%retval = call {,} @llvm.vector.deinterleave2.nxv4i32( %vec) ret {, } %retval } ; Floating declarations -declare {,} @llvm.experimental.vector.deinterleave2.nxv4f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4f32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8f32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4f64() +declare {,} @llvm.vector.deinterleave2.nxv4f16() +declare {, } @llvm.vector.deinterleave2.nxv8f16() +declare {, } @llvm.vector.deinterleave2.nxv4f32() +declare {, } @llvm.vector.deinterleave2.nxv16f16() +declare {, } @llvm.vector.deinterleave2.nxv8f32() +declare {, } @llvm.vector.deinterleave2.nxv4f64() ; Integer declarations -declare {, } @llvm.experimental.vector.deinterleave2.nxv32i8() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8i32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4i64() +declare {, } @llvm.vector.deinterleave2.nxv32i8() +declare {, } @llvm.vector.deinterleave2.nxv16i16() +declare {, } @llvm.vector.deinterleave2.nxv8i32() +declare {, } @llvm.vector.deinterleave2.nxv4i64() ; Predicated declarations -declare {, } @llvm.experimental.vector.deinterleave2.nxv32i1() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i1() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8i1() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4i1() +declare {, } @llvm.vector.deinterleave2.nxv32i1() +declare {, } @llvm.vector.deinterleave2.nxv16i1() +declare {, } @llvm.vector.deinterleave2.nxv8i1() +declare {, } @llvm.vector.deinterleave2.nxv4i1() ; Illegal size type -declare {, } @llvm.experimental.vector.deinterleave2.nxv8i64() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i64() +declare {, } @llvm.vector.deinterleave2.nxv8i64() +declare {, } @llvm.vector.deinterleave2.nxv16i64() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i8() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8i16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4i32() +declare {, } @llvm.vector.deinterleave2.nxv16i8() +declare {, } @llvm.vector.deinterleave2.nxv8i16() +declare {, } @llvm.vector.deinterleave2.nxv4i32() diff --git a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll index 23bf5065286e..e2c3b0abe21a 100644 --- a/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll +++ b/llvm/test/CodeGen/AArch64/sve-vector-interleave.ll @@ -8,7 +8,7 @@ define @interleave2_nxv4f16( %vec0, @llvm.experimental.vector.interleave2.nxv4f16( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv4f16( %vec0, %vec1) ret %retval } @@ -19,7 +19,7 @@ define @interleave2_nxv8f16( %vec0, @llvm.experimental.vector.interleave2.nxv8f16( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv8f16( %vec0, %vec1) ret %retval } @@ -30,7 +30,7 @@ define @interleave2_nxv16f16( %vec0, @llvm.experimental.vector.interleave2.nxv16f16( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv16f16( %vec0, %vec1) ret %retval } @@ -41,7 +41,7 @@ define @interleave2_nxv4f32( %vec0, @llvm.experimental.vector.interleave2.nxv4f32( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv4f32( %vec0, %vec1) ret %retval } @@ -52,7 +52,7 @@ define @interleave2_nxv8f32( %vec0, @llvm.experimental.vector.interleave2.nxv8f32( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv8f32( %vec0, %vec1) ret %retval } @@ -63,7 +63,7 @@ define @interleave2_nxv4f64( %vec0, < ; CHECK-NEXT: zip2 z1.d, z0.d, z1.d ; CHECK-NEXT: mov z0.d, z2.d ; CHECK-NEXT: ret - %retval = call @llvm.experimental.vector.interleave2.nxv4f64( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv4f64( %vec0, %vec1) ret %retval } @@ -76,7 +76,7 @@ define @interleave2_nxv32i8( %vec0, @llvm.experimental.vector.interleave2.nxv32i8( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv32i8( %vec0, %vec1) ret %retval } @@ -87,7 +87,7 @@ define @interleave2_nxv16i16( %vec0, @llvm.experimental.vector.interleave2.nxv16i16( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv16i16( %vec0, %vec1) ret %retval } @@ -98,7 +98,7 @@ define @interleave2_nxv8i32( %vec0, @llvm.experimental.vector.interleave2.nxv8i32( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv8i32( %vec0, %vec1) ret %retval } @@ -109,7 +109,7 @@ define @interleave2_nxv4i64( %vec0, @llvm.experimental.vector.interleave2.nxv4i64( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv4i64( %vec0, %vec1) ret %retval } @@ -122,7 +122,7 @@ define @interleave2_nxv32i1( %vec0, @llvm.experimental.vector.interleave2.nxv32i1( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv32i1( %vec0, %vec1) ret %retval } @@ -133,7 +133,7 @@ define @interleave2_nxv16i1( %vec0, @llvm.experimental.vector.interleave2.nxv16i1( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv16i1( %vec0, %vec1) ret %retval } @@ -144,7 +144,7 @@ define @interleave2_nxv8i1( %vec0, @llvm.experimental.vector.interleave2.nxv8i1( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv8i1( %vec0, %vec1) ret %retval } @@ -155,7 +155,7 @@ define @interleave2_nxv4i1( %vec0, @llvm.experimental.vector.interleave2.nxv4i1( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv4i1( %vec0, %vec1) ret %retval } @@ -172,7 +172,7 @@ define @interleave2_nxv16i32( %vec0, @llvm.experimental.vector.interleave2.nxv16i32( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv16i32( %vec0, %vec1) ret %retval } @@ -187,7 +187,7 @@ define @interleave2_nxv8i64( %vec0, @llvm.experimental.vector.interleave2.nxv8i64( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv8i64( %vec0, %vec1) ret %retval } @@ -200,7 +200,7 @@ define @interleave2_nxv8i8( %vec0, @llvm.experimental.vector.interleave2.nxv16i8( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv16i8( %vec0, %vec1) ret %retval } @@ -211,7 +211,7 @@ define @interleave2_nxv4i16( %vec0, @llvm.experimental.vector.interleave2.nxv8i16( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv8i16( %vec0, %vec1) ret %retval } @@ -222,34 +222,34 @@ define @interleave2_nxv2i32( %vec0, @llvm.experimental.vector.interleave2.nxv4i32( %vec0, %vec1) + %retval = call @llvm.vector.interleave2.nxv4i32( %vec0, %vec1) ret %retval } ; Float declarations -declare @llvm.experimental.vector.interleave2.nxv4f16(, ) -declare @llvm.experimental.vector.interleave2.nxv8f16(, ) -declare @llvm.experimental.vector.interleave2.nxv16f16(, ) -declare @llvm.experimental.vector.interleave2.nxv4f32(, ) -declare @llvm.experimental.vector.interleave2.nxv8f32(, ) -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare @llvm.vector.interleave2.nxv4f16(, ) +declare @llvm.vector.interleave2.nxv8f16(, ) +declare @llvm.vector.interleave2.nxv16f16(, ) +declare @llvm.vector.interleave2.nxv4f32(, ) +declare @llvm.vector.interleave2.nxv8f32(, ) +declare @llvm.vector.interleave2.nxv4f64(, ) ; Integer declarations -declare @llvm.experimental.vector.interleave2.nxv32i8(, ) -declare @llvm.experimental.vector.interleave2.nxv16i16(, ) -declare @llvm.experimental.vector.interleave2.nxv8i32(, ) -declare @llvm.experimental.vector.interleave2.nxv4i64(, ) +declare @llvm.vector.interleave2.nxv32i8(, ) +declare @llvm.vector.interleave2.nxv16i16(, ) +declare @llvm.vector.interleave2.nxv8i32(, ) +declare @llvm.vector.interleave2.nxv4i64(, ) ; Predicated -declare @llvm.experimental.vector.interleave2.nxv32i1(, ) -declare @llvm.experimental.vector.interleave2.nxv16i1(, ) -declare @llvm.experimental.vector.interleave2.nxv8i1(, ) -declare @llvm.experimental.vector.interleave2.nxv4i1(, ) +declare @llvm.vector.interleave2.nxv32i1(, ) +declare @llvm.vector.interleave2.nxv16i1(, ) +declare @llvm.vector.interleave2.nxv8i1(, ) +declare @llvm.vector.interleave2.nxv4i1(, ) ; Illegal type size -declare @llvm.experimental.vector.interleave2.nxv16i32(, ) -declare @llvm.experimental.vector.interleave2.nxv8i64(, ) +declare @llvm.vector.interleave2.nxv16i32(, ) +declare @llvm.vector.interleave2.nxv8i64(, ) -declare @llvm.experimental.vector.interleave2.nxv16i8(, ) -declare @llvm.experimental.vector.interleave2.nxv8i16(, ) -declare @llvm.experimental.vector.interleave2.nxv4i32(, ) +declare @llvm.vector.interleave2.nxv16i8(, ) +declare @llvm.vector.interleave2.nxv8i16(, ) +declare @llvm.vector.interleave2.nxv4i32(, ) diff --git a/llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll b/llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll index cb74cd8032ab..5f7476397891 100644 --- a/llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll +++ b/llvm/test/CodeGen/AArch64/sve2-intrinsics-while-reversed.ll @@ -16,7 +16,7 @@ define @whilege_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -28,7 +28,7 @@ define @whilege_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -40,7 +40,7 @@ define @whilege_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -52,7 +52,7 @@ define @whilege_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -64,7 +64,7 @@ define @whilege_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -76,7 +76,7 @@ define @whilege_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -88,7 +88,7 @@ define @whilege_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -100,7 +100,7 @@ define @whilege_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilele.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -116,7 +116,7 @@ define @whilehs_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -128,7 +128,7 @@ define @whilehs_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -140,7 +140,7 @@ define @whilehs_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -152,7 +152,7 @@ define @whilehs_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -164,7 +164,7 @@ define @whilehs_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -176,7 +176,7 @@ define @whilehs_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -188,7 +188,7 @@ define @whilehs_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -200,7 +200,7 @@ define @whilehs_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilels.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -214,7 +214,7 @@ define @whilegt_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilegt p0.b, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -224,7 +224,7 @@ define @whilegt_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilegt p0.b, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -234,7 +234,7 @@ define @whilegt_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilegt p0.h, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -244,7 +244,7 @@ define @whilegt_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilegt p0.h, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -254,7 +254,7 @@ define @whilegt_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilegt p0.s, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -264,7 +264,7 @@ define @whilegt_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilegt p0.s, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -274,7 +274,7 @@ define @whilegt_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilegt p0.d, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -284,7 +284,7 @@ define @whilegt_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilegt p0.d, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelt.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -298,7 +298,7 @@ define @whilehi_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilehi p0.b, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -308,7 +308,7 @@ define @whilehi_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilehi p0.b, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -318,7 +318,7 @@ define @whilehi_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilehi p0.h, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -328,7 +328,7 @@ define @whilehi_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilehi p0.h, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -338,7 +338,7 @@ define @whilehi_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilehi p0.s, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -348,7 +348,7 @@ define @whilehi_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilehi p0.s, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -358,7 +358,7 @@ define @whilehi_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilehi p0.d, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -368,7 +368,7 @@ define @whilehi_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilehi p0.d, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilelo.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -384,7 +384,7 @@ define @whilele_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -396,7 +396,7 @@ define @whilele_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -408,7 +408,7 @@ define @whilele_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -420,7 +420,7 @@ define @whilele_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -432,7 +432,7 @@ define @whilele_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -444,7 +444,7 @@ define @whilele_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -456,7 +456,7 @@ define @whilele_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -468,7 +468,7 @@ define @whilele_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilege.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -482,7 +482,7 @@ define @whilelo_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelo p0.b, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -492,7 +492,7 @@ define @whilelo_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelo p0.b, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -502,7 +502,7 @@ define @whilelo_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelo p0.h, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -512,7 +512,7 @@ define @whilelo_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelo p0.h, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -522,7 +522,7 @@ define @whilelo_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelo p0.s, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -532,7 +532,7 @@ define @whilelo_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelo p0.s, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -542,7 +542,7 @@ define @whilelo_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelo p0.d, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -552,7 +552,7 @@ define @whilelo_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelo p0.d, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehi.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -568,7 +568,7 @@ define @whilels_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -580,7 +580,7 @@ define @whilels_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.b, p0.b ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -592,7 +592,7 @@ define @whilels_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -604,7 +604,7 @@ define @whilels_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.h, p0.h ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -616,7 +616,7 @@ define @whilels_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -628,7 +628,7 @@ define @whilels_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.s, p0.s ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -640,7 +640,7 @@ define @whilels_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -652,7 +652,7 @@ define @whilels_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: rev p0.d, p0.d ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilehs.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -666,7 +666,7 @@ define @whilelt_b_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelt p0.b, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv16i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -676,7 +676,7 @@ define @whilelt_b_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelt p0.b, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv16i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv16i1( %while) + %while.rev = call @llvm.vector.reverse.nxv16i1( %while) ret %while.rev } @@ -686,7 +686,7 @@ define @whilelt_h_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelt p0.h, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv8i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -696,7 +696,7 @@ define @whilelt_h_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelt p0.h, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv8i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv8i1( %while) + %while.rev = call @llvm.vector.reverse.nxv8i1( %while) ret %while.rev } @@ -706,7 +706,7 @@ define @whilelt_s_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelt p0.s, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv4i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -716,7 +716,7 @@ define @whilelt_s_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelt p0.s, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv4i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv4i1( %while) + %while.rev = call @llvm.vector.reverse.nxv4i1( %while) ret %while.rev } @@ -726,7 +726,7 @@ define @whilelt_d_ww(i32 %a, i32 %b) { ; CHECK-NEXT: whilelt p0.d, w0, w1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv2i1.i32(i32 %b, i32 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } @@ -736,6 +736,6 @@ define @whilelt_d_xx(i64 %a, i64 %b) { ; CHECK-NEXT: whilelt p0.d, x0, x1 ; CHECK-NEXT: ret %while = call @llvm.aarch64.sve.whilegt.nxv2i1.i64(i64 %b, i64 %a) - %while.rev = call @llvm.experimental.vector.reverse.nxv2i1( %while) + %while.rev = call @llvm.vector.reverse.nxv2i1( %while) ret %while.rev } diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll index 83edd49bc963..1587f770f87c 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-deinterleave-load.ll @@ -35,7 +35,7 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_load_v16i1_v32i1(ptr %p) { ; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: ret %vec = load <32 x i1>, ptr %p - %retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec) + %retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec) ret {<16 x i1>, <16 x i1>} %retval } @@ -46,7 +46,7 @@ define {<16 x i8>, <16 x i8>} @vector_deinterleave_load_v16i8_v32i8(ptr %p) { ; CHECK-NEXT: vlseg2e8.v v8, (a0) ; CHECK-NEXT: ret %vec = load <32 x i8>, ptr %p - %retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec) + %retval = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec) ret {<16 x i8>, <16 x i8>} %retval } @@ -62,7 +62,7 @@ define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16_align1(ptr ; CHECK-NEXT: vnsrl.wi v9, v10, 16 ; CHECK-NEXT: ret %vec = load <16 x i16>, ptr %p, align 1 - %retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec) + %retval = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec) ret {<8 x i16>, <8 x i16>} %retval } @@ -73,7 +73,7 @@ define {<8 x i16>, <8 x i16>} @vector_deinterleave_load_v8i16_v16i16(ptr %p) { ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load <16 x i16>, ptr %p - %retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec) + %retval = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec) ret {<8 x i16>, <8 x i16>} %retval } @@ -84,7 +84,7 @@ define {<4 x i32>, <4 x i32>} @vector_deinterleave_load_v4i32_vv8i32(ptr %p) { ; CHECK-NEXT: vlseg2e32.v v8, (a0) ; CHECK-NEXT: ret %vec = load <8 x i32>, ptr %p - %retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec) + %retval = call {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32> %vec) ret {<4 x i32>, <4 x i32>} %retval } @@ -95,15 +95,15 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_load_v2i64_v4i64(ptr %p) { ; CHECK-NEXT: vlseg2e64.v v8, (a0) ; CHECK-NEXT: ret %vec = load <4 x i64>, ptr %p - %retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec) + %retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec) ret {<2 x i64>, <2 x i64>} %retval } -declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>) -declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>) -declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>) -declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>) -declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>) +declare {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1>) +declare {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8>) +declare {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16>) +declare {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32>) +declare {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64>) ; Floats @@ -114,7 +114,7 @@ define {<2 x half>, <2 x half>} @vector_deinterleave_load_v2f16_v4f16(ptr %p) { ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load <4 x half>, ptr %p - %retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec) + %retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec) ret {<2 x half>, <2 x half>} %retval } @@ -125,7 +125,7 @@ define {<4 x half>, <4 x half>} @vector_deinterleave_load_v4f16_v8f16(ptr %p) { ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load <8 x half>, ptr %p - %retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec) + %retval = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec) ret {<4 x half>, <4 x half>} %retval } @@ -136,7 +136,7 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_load_v2f32_v4f32(ptr %p) ; CHECK-NEXT: vlseg2e32.v v8, (a0) ; CHECK-NEXT: ret %vec = load <4 x float>, ptr %p - %retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec) + %retval = call {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float> %vec) ret {<2 x float>, <2 x float>} %retval } @@ -147,7 +147,7 @@ define {<8 x half>, <8 x half>} @vector_deinterleave_load_v8f16_v16f16(ptr %p) { ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load <16 x half>, ptr %p - %retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec) + %retval = call {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half> %vec) ret {<8 x half>, <8 x half>} %retval } @@ -158,7 +158,7 @@ define {<4 x float>, <4 x float>} @vector_deinterleave_load_v4f32_v8f32(ptr %p) ; CHECK-NEXT: vlseg2e32.v v8, (a0) ; CHECK-NEXT: ret %vec = load <8 x float>, ptr %p - %retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec) + %retval = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %vec) ret {<4 x float>, <4 x float>} %retval } @@ -169,13 +169,13 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_load_v2f64_v4f64(ptr %p ; CHECK-NEXT: vlseg2e64.v v8, (a0) ; CHECK-NEXT: ret %vec = load <4 x double>, ptr %p - %retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec) + %retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec) ret {<2 x double>, <2 x double>} %retval } -declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>) -declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>) -declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>) -declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>) -declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>) -declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>) +declare {<2 x half>,<2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half>) +declare {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half>) +declare {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float>) +declare {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half>) +declare {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float>) +declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll index 9161cedd58e3..8de9cc25ae09 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-interleave-store.ll @@ -23,7 +23,7 @@ define void @vector_interleave_store_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b, ptr ; CHECK-NEXT: vmsne.vi v8, v12, 0 ; CHECK-NEXT: vsm.v v8, (a0) ; CHECK-NEXT: ret - %res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b) + %res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b) store <32 x i1> %res, ptr %p ret void } @@ -40,7 +40,7 @@ define void @vector_interleave_store_v16i16_v8i16_align1(<8 x i16> %a, <8 x i16> ; CHECK-NEXT: vsetvli zero, a1, e8, m2, ta, ma ; CHECK-NEXT: vse8.v v10, (a0) ; CHECK-NEXT: ret - %res = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b) + %res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b) store <16 x i16> %res, ptr %p, align 1 ret void } @@ -51,7 +51,7 @@ define void @vector_interleave_store_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b, pt ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret - %res = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b) + %res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b) store <16 x i16> %res, ptr %p ret void } @@ -62,7 +62,7 @@ define void @vector_interleave_store_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b, ptr ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret - %res = call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b) + %res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b) store <8 x i32> %res, ptr %p ret void } @@ -73,15 +73,15 @@ define void @vector_interleave_store_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b, ptr ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret - %res = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b) + %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b) store <4 x i64> %res, ptr %p ret void } -declare <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1>, <16 x i1>) -declare <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) -declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) -declare <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) +declare <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1>, <16 x i1>) +declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) +declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) ; Floats @@ -91,7 +91,7 @@ define void @vector_interleave_store_v4f16_v2f16(<2 x half> %a, <2 x half> %b, p ; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma ; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret - %res = call <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b) + %res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b) store <4 x half> %res, ptr %p ret void } @@ -102,7 +102,7 @@ define void @vector_interleave_store_v8f16_v4f16(<4 x half> %a, <4 x half> %b, p ; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma ; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret - %res = call <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b) + %res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b) store <8 x half> %res, ptr %p ret void } @@ -113,7 +113,7 @@ define void @vector_interleave_store_v4f32_v2f32(<2 x float> %a, <2 x float> %b, ; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma ; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret - %res = call <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b) + %res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b) store <4 x float> %res, ptr %p ret void } @@ -124,7 +124,7 @@ define void @vector_interleave_store_v16f16_v8f16(<8 x half> %a, <8 x half> %b, ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma ; CHECK-NEXT: vsseg2e16.v v8, (a0) ; CHECK-NEXT: ret - %res = call <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b) + %res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b) store <16 x half> %res, ptr %p ret void } @@ -135,7 +135,7 @@ define void @vector_interleave_store_v8f32_v4f32(<4 x float> %a, <4 x float> %b, ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma ; CHECK-NEXT: vsseg2e32.v v8, (a0) ; CHECK-NEXT: ret - %res = call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b) + %res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b) store <8 x float> %res, ptr %p ret void } @@ -146,15 +146,15 @@ define void @vector_interleave_store_v4f64_v2f64(<2 x double> %a, <2 x double> % ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret - %res = call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b) + %res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b) store <4 x double> %res, ptr %p ret void } -declare <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half>, <2 x half>) -declare <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half>, <4 x half>) -declare <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float>, <2 x float>) -declare <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half>, <8 x half>) -declare <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float>, <4 x float>) -declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double>, <2 x double>) +declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>) +declare <8 x half> @llvm.vector.interleave2.v8f16(<4 x half>, <4 x half>) +declare <4 x float> @llvm.vector.interleave2.v4f32(<2 x float>, <2 x float>) +declare <16 x half> @llvm.vector.interleave2.v16f16(<8 x half>, <8 x half>) +declare <8 x float> @llvm.vector.interleave2.v8f32(<4 x float>, <4 x float>) +declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double>, <2 x double>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll index d4c0477408fd..a81f740f1739 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse-bitrotate.ll @@ -16,8 +16,8 @@ define <256 x i1> @reverse_v256i1(<256 x i1> %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v10 ; CHECK-NEXT: vmsne.vi v0, v12, 0 ; CHECK-NEXT: ret - %res = call <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1> %a) + %res = call <256 x i1> @llvm.vector.reverse.v256i1(<256 x i1> %a) ret <256 x i1> %res } -declare <256 x i1> @llvm.experimental.vector.reverse.v256i1(<256 x i1>) +declare <256 x i1> @llvm.vector.reverse.v256i1(<256 x i1>) diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll index 8f9f1c2729fc..47d7baade8b4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-shuffle-reverse.ll @@ -29,7 +29,7 @@ define <2 x i1> @reverse_v2i1(<2 x i1> %a) { ; ZVBB-NEXT: vbrev.v v8, v0 ; ZVBB-NEXT: vsrl.vi v0, v8, 6 ; ZVBB-NEXT: ret - %res = call <2 x i1> @llvm.experimental.vector.reverse.v2i1(<2 x i1> %a) + %res = call <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1> %a) ret <2 x i1> %res } @@ -51,7 +51,7 @@ define <4 x i1> @reverse_v4i1(<4 x i1> %a) { ; ZVBB-NEXT: vbrev.v v8, v0 ; ZVBB-NEXT: vsrl.vi v0, v8, 4 ; ZVBB-NEXT: ret - %res = call <4 x i1> @llvm.experimental.vector.reverse.v4i1(<4 x i1> %a) + %res = call <4 x i1> @llvm.vector.reverse.v4i1(<4 x i1> %a) ret <4 x i1> %res } @@ -72,7 +72,7 @@ define <8 x i1> @reverse_v8i1(<8 x i1> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e8, mf8, ta, ma ; ZVBB-NEXT: vbrev.v v0, v0 ; ZVBB-NEXT: ret - %res = call <8 x i1> @llvm.experimental.vector.reverse.v8i1(<8 x i1> %a) + %res = call <8 x i1> @llvm.vector.reverse.v8i1(<8 x i1> %a) ret <8 x i1> %res } @@ -93,7 +93,7 @@ define <16 x i1> @reverse_v16i1(<16 x i1> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; ZVBB-NEXT: vbrev.v v0, v0 ; ZVBB-NEXT: ret - %res = call <16 x i1> @llvm.experimental.vector.reverse.v16i1(<16 x i1> %a) + %res = call <16 x i1> @llvm.vector.reverse.v16i1(<16 x i1> %a) ret <16 x i1> %res } @@ -116,7 +116,7 @@ define <32 x i1> @reverse_v32i1(<32 x i1> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; ZVBB-NEXT: vbrev.v v0, v0 ; ZVBB-NEXT: ret - %res = call <32 x i1> @llvm.experimental.vector.reverse.v32i1(<32 x i1> %a) + %res = call <32 x i1> @llvm.vector.reverse.v32i1(<32 x i1> %a) ret <32 x i1> %res } @@ -139,7 +139,7 @@ define <64 x i1> @reverse_v64i1(<64 x i1> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; ZVBB-NEXT: vbrev.v v0, v0 ; ZVBB-NEXT: ret - %res = call <64 x i1> @llvm.experimental.vector.reverse.v64i1(<64 x i1> %a) + %res = call <64 x i1> @llvm.vector.reverse.v64i1(<64 x i1> %a) ret <64 x i1> %res } @@ -156,7 +156,7 @@ define <128 x i1> @reverse_v128i1(<128 x i1> %a) { ; CHECK-NEXT: vrgather.vv v24, v16, v8 ; CHECK-NEXT: vmsne.vi v0, v24, 0 ; CHECK-NEXT: ret - %res = call <128 x i1> @llvm.experimental.vector.reverse.v128i1(<128 x i1> %a) + %res = call <128 x i1> @llvm.vector.reverse.v128i1(<128 x i1> %a) ret <128 x i1> %res } @@ -164,7 +164,7 @@ define <1 x i8> @reverse_v1i8(<1 x i8> %a) { ; CHECK-LABEL: reverse_v1i8: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call <1 x i8> @llvm.experimental.vector.reverse.v1i8(<1 x i8> %a) + %res = call <1 x i8> @llvm.vector.reverse.v1i8(<1 x i8> %a) ret <1 x i8> %res } @@ -182,7 +182,7 @@ define <2 x i8> @reverse_v2i8(<2 x i8> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e16, mf4, ta, ma ; ZVBB-NEXT: vrev8.v v8, v8 ; ZVBB-NEXT: ret - %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a) + %res = call <2 x i8> @llvm.vector.reverse.v2i8(<2 x i8> %a) ret <2 x i8> %res } @@ -195,7 +195,7 @@ define <4 x i8> @reverse_v4i8(<4 x i8> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call <4 x i8> @llvm.experimental.vector.reverse.v4i8(<4 x i8> %a) + %res = call <4 x i8> @llvm.vector.reverse.v4i8(<4 x i8> %a) ret <4 x i8> %res } @@ -208,7 +208,7 @@ define <8 x i8> @reverse_v8i8(<8 x i8> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call <8 x i8> @llvm.experimental.vector.reverse.v8i8(<8 x i8> %a) + %res = call <8 x i8> @llvm.vector.reverse.v8i8(<8 x i8> %a) ret <8 x i8> %res } @@ -221,7 +221,7 @@ define <16 x i8> @reverse_v16i8(<16 x i8> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a) + %res = call <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8> %a) ret <16 x i8> %res } @@ -236,7 +236,7 @@ define <32 x i8> @reverse_v32i8(<32 x i8> %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call <32 x i8> @llvm.experimental.vector.reverse.v32i8(<32 x i8> %a) + %res = call <32 x i8> @llvm.vector.reverse.v32i8(<32 x i8> %a) ret <32 x i8> %res } @@ -251,7 +251,7 @@ define <64 x i8> @reverse_v64i8(<64 x i8> %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call <64 x i8> @llvm.experimental.vector.reverse.v64i8(<64 x i8> %a) + %res = call <64 x i8> @llvm.vector.reverse.v64i8(<64 x i8> %a) ret <64 x i8> %res } @@ -259,7 +259,7 @@ define <1 x i16> @reverse_v1i16(<1 x i16> %a) { ; CHECK-LABEL: reverse_v1i16: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call <1 x i16> @llvm.experimental.vector.reverse.v1i16(<1 x i16> %a) + %res = call <1 x i16> @llvm.vector.reverse.v1i16(<1 x i16> %a) ret <1 x i16> %res } @@ -277,7 +277,7 @@ define <2 x i16> @reverse_v2i16(<2 x i16> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; ZVBB-NEXT: vror.vi v8, v8, 16 ; ZVBB-NEXT: ret - %res = call <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16> %a) + %res = call <2 x i16> @llvm.vector.reverse.v2i16(<2 x i16> %a) ret <2 x i16> %res } @@ -290,7 +290,7 @@ define <4 x i16> @reverse_v4i16(<4 x i16> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call <4 x i16> @llvm.experimental.vector.reverse.v4i16(<4 x i16> %a) + %res = call <4 x i16> @llvm.vector.reverse.v4i16(<4 x i16> %a) ret <4 x i16> %res } @@ -303,7 +303,7 @@ define <8 x i16> @reverse_v8i16(<8 x i16> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a) + %res = call <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16> %a) ret <8 x i16> %res } @@ -316,7 +316,7 @@ define <16 x i16> @reverse_v16i16(<16 x i16> %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call <16 x i16> @llvm.experimental.vector.reverse.v16i16(<16 x i16> %a) + %res = call <16 x i16> @llvm.vector.reverse.v16i16(<16 x i16> %a) ret <16 x i16> %res } @@ -332,7 +332,7 @@ define <32 x i16> @reverse_v32i16(<32 x i16> %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call <32 x i16> @llvm.experimental.vector.reverse.v32i16(<32 x i16> %a) + %res = call <32 x i16> @llvm.vector.reverse.v32i16(<32 x i16> %a) ret <32 x i16> %res } @@ -340,7 +340,7 @@ define <1 x i32> @reverse_v1i32(<1 x i32> %a) { ; CHECK-LABEL: reverse_v1i32: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call <1 x i32> @llvm.experimental.vector.reverse.v1i32(<1 x i32> %a) + %res = call <1 x i32> @llvm.vector.reverse.v1i32(<1 x i32> %a) ret <1 x i32> %res } @@ -358,7 +358,7 @@ define <2 x i32> @reverse_v2i32(<2 x i32> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; ZVBB-NEXT: vror.vi v8, v8, 32 ; ZVBB-NEXT: ret - %res = call <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32> %a) + %res = call <2 x i32> @llvm.vector.reverse.v2i32(<2 x i32> %a) ret <2 x i32> %res } @@ -371,7 +371,7 @@ define <4 x i32> @reverse_v4i32(<4 x i32> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a) + %res = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> %a) ret <4 x i32> %res } @@ -385,7 +385,7 @@ define <8 x i32> @reverse_v8i32(<8 x i32> %a) { ; CHECK-NEXT: vrgatherei16.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a) + %res = call <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32> %a) ret <8 x i32> %res } @@ -399,7 +399,7 @@ define <16 x i32> @reverse_v16i32(<16 x i32> %a) { ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call <16 x i32> @llvm.experimental.vector.reverse.v16i32(<16 x i32> %a) + %res = call <16 x i32> @llvm.vector.reverse.v16i32(<16 x i32> %a) ret <16 x i32> %res } @@ -407,7 +407,7 @@ define <1 x i64> @reverse_v1i64(<1 x i64> %a) { ; CHECK-LABEL: reverse_v1i64: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call <1 x i64> @llvm.experimental.vector.reverse.v1i64(<1 x i64> %a) + %res = call <1 x i64> @llvm.vector.reverse.v1i64(<1 x i64> %a) ret <1 x i64> %res } @@ -419,7 +419,7 @@ define <2 x i64> @reverse_v2i64(<2 x i64> %a) { ; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a) + %res = call <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64> %a) ret <2 x i64> %res } @@ -433,7 +433,7 @@ define <4 x i64> @reverse_v4i64(<4 x i64> %a) { ; CHECK-NEXT: vrgatherei16.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call <4 x i64> @llvm.experimental.vector.reverse.v4i64(<4 x i64> %a) + %res = call <4 x i64> @llvm.vector.reverse.v4i64(<4 x i64> %a) ret <4 x i64> %res } @@ -447,7 +447,7 @@ define <8 x i64> @reverse_v8i64(<8 x i64> %a) { ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call <8 x i64> @llvm.experimental.vector.reverse.v8i64(<8 x i64> %a) + %res = call <8 x i64> @llvm.vector.reverse.v8i64(<8 x i64> %a) ret <8 x i64> %res } @@ -456,7 +456,7 @@ define <1 x half> @reverse_v1f16(<1 x half> %a) { ; CHECK-LABEL: reverse_v1f16: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call <1 x half> @llvm.experimental.vector.reverse.v1f16(<1 x half> %a) + %res = call <1 x half> @llvm.vector.reverse.v1f16(<1 x half> %a) ret <1 x half> %res } @@ -474,7 +474,7 @@ define <2 x half> @reverse_v2f16(<2 x half> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; ZVBB-NEXT: vror.vi v8, v8, 16 ; ZVBB-NEXT: ret - %res = call <2 x half> @llvm.experimental.vector.reverse.v2f16(<2 x half> %a) + %res = call <2 x half> @llvm.vector.reverse.v2f16(<2 x half> %a) ret <2 x half> %res } @@ -487,7 +487,7 @@ define <4 x half> @reverse_v4f16(<4 x half> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call <4 x half> @llvm.experimental.vector.reverse.v4f16(<4 x half> %a) + %res = call <4 x half> @llvm.vector.reverse.v4f16(<4 x half> %a) ret <4 x half> %res } @@ -500,7 +500,7 @@ define <8 x half> @reverse_v8f16(<8 x half> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half> %a) + %res = call <8 x half> @llvm.vector.reverse.v8f16(<8 x half> %a) ret <8 x half> %res } @@ -513,7 +513,7 @@ define <16 x half> @reverse_v16f16(<16 x half> %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call <16 x half> @llvm.experimental.vector.reverse.v16f16(<16 x half> %a) + %res = call <16 x half> @llvm.vector.reverse.v16f16(<16 x half> %a) ret <16 x half> %res } @@ -529,7 +529,7 @@ define <32 x half> @reverse_v32f16(<32 x half> %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call <32 x half> @llvm.experimental.vector.reverse.v32f16(<32 x half> %a) + %res = call <32 x half> @llvm.vector.reverse.v32f16(<32 x half> %a) ret <32 x half> %res } @@ -537,7 +537,7 @@ define <1 x float> @reverse_v1f32(<1 x float> %a) { ; CHECK-LABEL: reverse_v1f32: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call <1 x float> @llvm.experimental.vector.reverse.v1f32(<1 x float> %a) + %res = call <1 x float> @llvm.vector.reverse.v1f32(<1 x float> %a) ret <1 x float> %res } @@ -555,7 +555,7 @@ define <2 x float> @reverse_v2f32(<2 x float> %a) { ; ZVBB-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; ZVBB-NEXT: vror.vi v8, v8, 32 ; ZVBB-NEXT: ret - %res = call <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float> %a) + %res = call <2 x float> @llvm.vector.reverse.v2f32(<2 x float> %a) ret <2 x float> %res } @@ -568,7 +568,7 @@ define <4 x float> @reverse_v4f32(<4 x float> %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a) + %res = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %a) ret <4 x float> %res } @@ -582,7 +582,7 @@ define <8 x float> @reverse_v8f32(<8 x float> %a) { ; CHECK-NEXT: vrgatherei16.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call <8 x float> @llvm.experimental.vector.reverse.v8f32(<8 x float> %a) + %res = call <8 x float> @llvm.vector.reverse.v8f32(<8 x float> %a) ret <8 x float> %res } @@ -596,7 +596,7 @@ define <16 x float> @reverse_v16f32(<16 x float> %a) { ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a) + %res = call <16 x float> @llvm.vector.reverse.v16f32(<16 x float> %a) ret <16 x float> %res } @@ -604,7 +604,7 @@ define <1 x double> @reverse_v1f64(<1 x double> %a) { ; CHECK-LABEL: reverse_v1f64: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call <1 x double> @llvm.experimental.vector.reverse.v1f64(<1 x double> %a) + %res = call <1 x double> @llvm.vector.reverse.v1f64(<1 x double> %a) ret <1 x double> %res } @@ -616,7 +616,7 @@ define <2 x double> @reverse_v2f64(<2 x double> %a) { ; CHECK-NEXT: vslideup.vi v9, v8, 1 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a) + %res = call <2 x double> @llvm.vector.reverse.v2f64(<2 x double> %a) ret <2 x double> %res } @@ -630,7 +630,7 @@ define <4 x double> @reverse_v4f64(<4 x double> %a) { ; CHECK-NEXT: vrgatherei16.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call <4 x double> @llvm.experimental.vector.reverse.v4f64(<4 x double> %a) + %res = call <4 x double> @llvm.vector.reverse.v4f64(<4 x double> %a) ret <4 x double> %res } @@ -644,7 +644,7 @@ define <8 x double> @reverse_v8f64(<8 x double> %a) { ; CHECK-NEXT: vrgatherei16.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call <8 x double> @llvm.experimental.vector.reverse.v8f64(<8 x double> %a) + %res = call <8 x double> @llvm.vector.reverse.v8f64(<8 x double> %a) ret <8 x double> %res } @@ -729,7 +729,7 @@ define <3 x i64> @reverse_v3i64(<3 x i64> %a) { ; RV64-ZVBB-NEXT: vrgatherei16.vv v10, v8, v12 ; RV64-ZVBB-NEXT: vmv.v.v v8, v10 ; RV64-ZVBB-NEXT: ret - %res = call <3 x i64> @llvm.experimental.vector.reverse.v3i64(<3 x i64> %a) + %res = call <3 x i64> @llvm.vector.reverse.v3i64(<3 x i64> %a) ret <3 x i64> %res } @@ -813,7 +813,7 @@ define <6 x i64> @reverse_v6i64(<6 x i64> %a) { ; RV64-ZVBB-NEXT: vrgatherei16.vv v12, v8, v16 ; RV64-ZVBB-NEXT: vmv.v.v v8, v12 ; RV64-ZVBB-NEXT: ret - %res = call <6 x i64> @llvm.experimental.vector.reverse.v6i64(<6 x i64> %a) + %res = call <6 x i64> @llvm.vector.reverse.v6i64(<6 x i64> %a) ret <6 x i64> %res } @@ -901,54 +901,54 @@ define <12 x i64> @reverse_v12i64(<12 x i64> %a) { ; RV64-ZVBB-NEXT: vrgatherei16.vv v16, v8, v24 ; RV64-ZVBB-NEXT: vmv.v.v v8, v16 ; RV64-ZVBB-NEXT: ret - %res = call <12 x i64> @llvm.experimental.vector.reverse.v12i64(<12 x i64> %a) + %res = call <12 x i64> @llvm.vector.reverse.v12i64(<12 x i64> %a) ret <12 x i64> %res } -declare <2 x i1> @llvm.experimental.vector.reverse.v2i1(<2 x i1>) -declare <4 x i1> @llvm.experimental.vector.reverse.v4i1(<4 x i1>) -declare <8 x i1> @llvm.experimental.vector.reverse.v8i1(<8 x i1>) -declare <16 x i1> @llvm.experimental.vector.reverse.v16i1(<16 x i1>) -declare <32 x i1> @llvm.experimental.vector.reverse.v32i1(<32 x i1>) -declare <64 x i1> @llvm.experimental.vector.reverse.v64i1(<64 x i1>) -declare <128 x i1> @llvm.experimental.vector.reverse.v128i1(<128 x i1>) -declare <1 x i8> @llvm.experimental.vector.reverse.v1i8(<1 x i8>) -declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>) -declare <4 x i8> @llvm.experimental.vector.reverse.v4i8(<4 x i8>) -declare <8 x i8> @llvm.experimental.vector.reverse.v8i8(<8 x i8>) -declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>) -declare <32 x i8> @llvm.experimental.vector.reverse.v32i8(<32 x i8>) -declare <64 x i8> @llvm.experimental.vector.reverse.v64i8(<64 x i8>) -declare <1 x i16> @llvm.experimental.vector.reverse.v1i16(<1 x i16>) -declare <2 x i16> @llvm.experimental.vector.reverse.v2i16(<2 x i16>) -declare <4 x i16> @llvm.experimental.vector.reverse.v4i16(<4 x i16>) -declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>) -declare <16 x i16> @llvm.experimental.vector.reverse.v16i16(<16 x i16>) -declare <32 x i16> @llvm.experimental.vector.reverse.v32i16(<32 x i16>) -declare <1 x i32> @llvm.experimental.vector.reverse.v1i32(<1 x i32>) -declare <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32>) -declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>) -declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>) -declare <16 x i32> @llvm.experimental.vector.reverse.v16i32(<16 x i32>) -declare <1 x i64> @llvm.experimental.vector.reverse.v1i64(<1 x i64>) -declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>) -declare <4 x i64> @llvm.experimental.vector.reverse.v4i64(<4 x i64>) -declare <8 x i64> @llvm.experimental.vector.reverse.v8i64(<8 x i64>) -declare <1 x half> @llvm.experimental.vector.reverse.v1f16(<1 x half>) -declare <2 x half> @llvm.experimental.vector.reverse.v2f16(<2 x half>) -declare <4 x half> @llvm.experimental.vector.reverse.v4f16(<4 x half>) -declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>) -declare <16 x half> @llvm.experimental.vector.reverse.v16f16(<16 x half>) -declare <32 x half> @llvm.experimental.vector.reverse.v32f16(<32 x half>) -declare <1 x float> @llvm.experimental.vector.reverse.v1f32(<1 x float>) -declare <2 x float> @llvm.experimental.vector.reverse.v2f32(<2 x float>) -declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>) -declare <8 x float> @llvm.experimental.vector.reverse.v8f32(<8 x float>) -declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>) -declare <1 x double> @llvm.experimental.vector.reverse.v1f64(<1 x double>) -declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>) -declare <4 x double> @llvm.experimental.vector.reverse.v4f64(<4 x double>) -declare <8 x double> @llvm.experimental.vector.reverse.v8f64(<8 x double>) -declare <3 x i64> @llvm.experimental.vector.reverse.v3i64(<3 x i64>) -declare <6 x i64> @llvm.experimental.vector.reverse.v6i64(<6 x i64>) -declare <12 x i64> @llvm.experimental.vector.reverse.v12i64(<12 x i64>) +declare <2 x i1> @llvm.vector.reverse.v2i1(<2 x i1>) +declare <4 x i1> @llvm.vector.reverse.v4i1(<4 x i1>) +declare <8 x i1> @llvm.vector.reverse.v8i1(<8 x i1>) +declare <16 x i1> @llvm.vector.reverse.v16i1(<16 x i1>) +declare <32 x i1> @llvm.vector.reverse.v32i1(<32 x i1>) +declare <64 x i1> @llvm.vector.reverse.v64i1(<64 x i1>) +declare <128 x i1> @llvm.vector.reverse.v128i1(<128 x i1>) +declare <1 x i8> @llvm.vector.reverse.v1i8(<1 x i8>) +declare <2 x i8> @llvm.vector.reverse.v2i8(<2 x i8>) +declare <4 x i8> @llvm.vector.reverse.v4i8(<4 x i8>) +declare <8 x i8> @llvm.vector.reverse.v8i8(<8 x i8>) +declare <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8>) +declare <32 x i8> @llvm.vector.reverse.v32i8(<32 x i8>) +declare <64 x i8> @llvm.vector.reverse.v64i8(<64 x i8>) +declare <1 x i16> @llvm.vector.reverse.v1i16(<1 x i16>) +declare <2 x i16> @llvm.vector.reverse.v2i16(<2 x i16>) +declare <4 x i16> @llvm.vector.reverse.v4i16(<4 x i16>) +declare <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16>) +declare <16 x i16> @llvm.vector.reverse.v16i16(<16 x i16>) +declare <32 x i16> @llvm.vector.reverse.v32i16(<32 x i16>) +declare <1 x i32> @llvm.vector.reverse.v1i32(<1 x i32>) +declare <2 x i32> @llvm.vector.reverse.v2i32(<2 x i32>) +declare <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32>) +declare <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32>) +declare <16 x i32> @llvm.vector.reverse.v16i32(<16 x i32>) +declare <1 x i64> @llvm.vector.reverse.v1i64(<1 x i64>) +declare <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64>) +declare <4 x i64> @llvm.vector.reverse.v4i64(<4 x i64>) +declare <8 x i64> @llvm.vector.reverse.v8i64(<8 x i64>) +declare <1 x half> @llvm.vector.reverse.v1f16(<1 x half>) +declare <2 x half> @llvm.vector.reverse.v2f16(<2 x half>) +declare <4 x half> @llvm.vector.reverse.v4f16(<4 x half>) +declare <8 x half> @llvm.vector.reverse.v8f16(<8 x half>) +declare <16 x half> @llvm.vector.reverse.v16f16(<16 x half>) +declare <32 x half> @llvm.vector.reverse.v32f16(<32 x half>) +declare <1 x float> @llvm.vector.reverse.v1f32(<1 x float>) +declare <2 x float> @llvm.vector.reverse.v2f32(<2 x float>) +declare <4 x float> @llvm.vector.reverse.v4f32(<4 x float>) +declare <8 x float> @llvm.vector.reverse.v8f32(<8 x float>) +declare <16 x float> @llvm.vector.reverse.v16f32(<16 x float>) +declare <1 x double> @llvm.vector.reverse.v1f64(<1 x double>) +declare <2 x double> @llvm.vector.reverse.v2f64(<2 x double>) +declare <4 x double> @llvm.vector.reverse.v4f64(<4 x double>) +declare <8 x double> @llvm.vector.reverse.v8f64(<8 x double>) +declare <3 x i64> @llvm.vector.reverse.v3i64(<3 x i64>) +declare <6 x i64> @llvm.vector.reverse.v6i64(<6 x i64>) +declare <12 x i64> @llvm.vector.reverse.v12i64(<12 x i64>) diff --git a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll index 4e08f401ca4e..96094eea631b 100644 --- a/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll +++ b/llvm/test/CodeGen/RISCV/rvv/named-vector-shuffle-reverse.ll @@ -104,7 +104,7 @@ define @reverse_nxv2i1( %a) { ; RV64-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i1( %a) + %res = call @llvm.vector.reverse.nxv2i1( %a) ret %res } @@ -202,7 +202,7 @@ define @reverse_nxv4i1( %a) { ; RV64-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4i1( %a) + %res = call @llvm.vector.reverse.nxv4i1( %a) ret %res } @@ -294,7 +294,7 @@ define @reverse_nxv8i1( %a) { ; RV64-BITS-512-NEXT: vand.vi v8, v10, 1 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i1( %a) + %res = call @llvm.vector.reverse.nxv8i1( %a) ret %res } @@ -392,7 +392,7 @@ define @reverse_nxv16i1( %a) { ; RV64-BITS-512-NEXT: vand.vi v8, v12, 1 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16i1( %a) + %res = call @llvm.vector.reverse.nxv16i1( %a) ret %res } @@ -490,7 +490,7 @@ define @reverse_nxv32i1( %a) { ; RV64-BITS-512-NEXT: vand.vi v8, v16, 1 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv32i1( %a) + %res = call @llvm.vector.reverse.nxv32i1( %a) ret %res } @@ -600,7 +600,7 @@ define @reverse_nxv64i1( %a) { ; RV64-BITS-512-NEXT: vand.vi v8, v24, 1 ; RV64-BITS-512-NEXT: vmsne.vi v0, v8, 0 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv64i1( %a) + %res = call @llvm.vector.reverse.nxv64i1( %a) ret %res } @@ -682,7 +682,7 @@ define @reverse_nxv1i8( %a) { ; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv1i8( %a) + %res = call @llvm.vector.reverse.nxv1i8( %a) ret %res } @@ -760,7 +760,7 @@ define @reverse_nxv2i8( %a) { ; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i8( %a) + %res = call @llvm.vector.reverse.nxv2i8( %a) ret %res } @@ -838,7 +838,7 @@ define @reverse_nxv4i8( %a) { ; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-512-NEXT: vmv1r.v v8, v9 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4i8( %a) + %res = call @llvm.vector.reverse.nxv4i8( %a) ret %res } @@ -910,7 +910,7 @@ define @reverse_nxv8i8( %a) { ; RV64-BITS-512-NEXT: vrgather.vv v9, v8, v10 ; RV64-BITS-512-NEXT: vmv.v.v v8, v9 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i8( %a) + %res = call @llvm.vector.reverse.nxv8i8( %a) ret %res } @@ -988,7 +988,7 @@ define @reverse_nxv16i8( %a) { ; RV64-BITS-512-NEXT: vrgather.vv v10, v8, v12 ; RV64-BITS-512-NEXT: vmv.v.v v8, v10 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16i8( %a) + %res = call @llvm.vector.reverse.nxv16i8( %a) ret %res } @@ -1066,7 +1066,7 @@ define @reverse_nxv32i8( %a) { ; RV64-BITS-512-NEXT: vrgather.vv v12, v8, v16 ; RV64-BITS-512-NEXT: vmv.v.v v8, v12 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv32i8( %a) + %res = call @llvm.vector.reverse.nxv32i8( %a) ret %res } @@ -1148,7 +1148,7 @@ define @reverse_nxv64i8( %a) { ; RV64-BITS-512-NEXT: vrgather.vv v16, v12, v24 ; RV64-BITS-512-NEXT: vmv8r.v v8, v16 ; RV64-BITS-512-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv64i8( %a) + %res = call @llvm.vector.reverse.nxv64i8( %a) ret %res } @@ -1164,7 +1164,7 @@ define @reverse_nxv1i16( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv1i16( %a) + %res = call @llvm.vector.reverse.nxv1i16( %a) ret %res } @@ -1180,7 +1180,7 @@ define @reverse_nxv2i16( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i16( %a) + %res = call @llvm.vector.reverse.nxv2i16( %a) ret %res } @@ -1196,7 +1196,7 @@ define @reverse_nxv4i16( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4i16( %a) + %res = call @llvm.vector.reverse.nxv4i16( %a) ret %res } @@ -1211,7 +1211,7 @@ define @reverse_nxv8i16( %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i16( %a) + %res = call @llvm.vector.reverse.nxv8i16( %a) ret %res } @@ -1227,7 +1227,7 @@ define @reverse_nxv16i16( %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16i16( %a) + %res = call @llvm.vector.reverse.nxv16i16( %a) ret %res } @@ -1243,7 +1243,7 @@ define @reverse_nxv32i16( %a) { ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv32i16( %a) + %res = call @llvm.vector.reverse.nxv32i16( %a) ret %res } @@ -1259,7 +1259,7 @@ define @reverse_nxv1i32( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv1i32( %a) + %res = call @llvm.vector.reverse.nxv1i32( %a) ret %res } @@ -1275,7 +1275,7 @@ define @reverse_nxv2i32( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i32( %a) + %res = call @llvm.vector.reverse.nxv2i32( %a) ret %res } @@ -1291,7 +1291,7 @@ define @reverse_nxv4i32( %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4i32( %a) + %res = call @llvm.vector.reverse.nxv4i32( %a) ret %res } @@ -1306,7 +1306,7 @@ define @reverse_nxv8i32( %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i32( %a) + %res = call @llvm.vector.reverse.nxv8i32( %a) ret %res } @@ -1322,7 +1322,7 @@ define @reverse_nxv16i32( %a) { ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16i32( %a) + %res = call @llvm.vector.reverse.nxv16i32( %a) ret %res } @@ -1338,7 +1338,7 @@ define @reverse_nxv1i64( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv1i64( %a) + %res = call @llvm.vector.reverse.nxv1i64( %a) ret %res } @@ -1354,7 +1354,7 @@ define @reverse_nxv2i64( %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2i64( %a) + %res = call @llvm.vector.reverse.nxv2i64( %a) ret %res } @@ -1370,7 +1370,7 @@ define @reverse_nxv4i64( %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4i64( %a) + %res = call @llvm.vector.reverse.nxv4i64( %a) ret %res } @@ -1385,7 +1385,7 @@ define @reverse_nxv8i64( %a) { ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8i64( %a) + %res = call @llvm.vector.reverse.nxv8i64( %a) ret %res } @@ -1405,7 +1405,7 @@ define @reverse_nxv1f16( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv1f16( %a) + %res = call @llvm.vector.reverse.nxv1f16( %a) ret %res } @@ -1421,7 +1421,7 @@ define @reverse_nxv2f16( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2f16( %a) + %res = call @llvm.vector.reverse.nxv2f16( %a) ret %res } @@ -1437,7 +1437,7 @@ define @reverse_nxv4f16( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4f16( %a) + %res = call @llvm.vector.reverse.nxv4f16( %a) ret %res } @@ -1452,7 +1452,7 @@ define @reverse_nxv8f16( %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8f16( %a) + %res = call @llvm.vector.reverse.nxv8f16( %a) ret %res } @@ -1468,7 +1468,7 @@ define @reverse_nxv16f16( %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16f16( %a) + %res = call @llvm.vector.reverse.nxv16f16( %a) ret %res } @@ -1484,7 +1484,7 @@ define @reverse_nxv32f16( %a) { ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv32f16( %a) + %res = call @llvm.vector.reverse.nxv32f16( %a) ret %res } @@ -1500,7 +1500,7 @@ define @reverse_nxv1f32( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv1r.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv1f32( %a) + %res = call @llvm.vector.reverse.nxv1f32( %a) ret %res } @@ -1516,7 +1516,7 @@ define @reverse_nxv2f32( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2f32( %a) + %res = call @llvm.vector.reverse.nxv2f32( %a) ret %res } @@ -1532,7 +1532,7 @@ define @reverse_nxv4f32( %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4f32( %a) + %res = call @llvm.vector.reverse.nxv4f32( %a) ret %res } @@ -1547,7 +1547,7 @@ define @reverse_nxv8f32( %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8f32( %a) + %res = call @llvm.vector.reverse.nxv8f32( %a) ret %res } @@ -1563,7 +1563,7 @@ define @reverse_nxv16f32( %a) { ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv16f32( %a) + %res = call @llvm.vector.reverse.nxv16f32( %a) ret %res } @@ -1579,7 +1579,7 @@ define @reverse_nxv1f64( %a) { ; CHECK-NEXT: vrgather.vv v9, v8, v10 ; CHECK-NEXT: vmv.v.v v8, v9 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv1f64( %a) + %res = call @llvm.vector.reverse.nxv1f64( %a) ret %res } @@ -1595,7 +1595,7 @@ define @reverse_nxv2f64( %a) { ; CHECK-NEXT: vrgather.vv v10, v8, v12 ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv2f64( %a) + %res = call @llvm.vector.reverse.nxv2f64( %a) ret %res } @@ -1611,7 +1611,7 @@ define @reverse_nxv4f64( %a) { ; CHECK-NEXT: vrgather.vv v12, v8, v16 ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv4f64( %a) + %res = call @llvm.vector.reverse.nxv4f64( %a) ret %res } @@ -1626,7 +1626,7 @@ define @reverse_nxv8f64( %a) { ; CHECK-NEXT: vrgather.vv v16, v8, v24 ; CHECK-NEXT: vmv.v.v v8, v16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv8f64( %a) + %res = call @llvm.vector.reverse.nxv8f64( %a) ret %res } @@ -1646,7 +1646,7 @@ define @reverse_nxv3i64( %a) { ; CHECK-NEXT: vmv1r.v v9, v18 ; CHECK-NEXT: vmv1r.v v10, v19 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv3i64( %a) + %res = call @llvm.vector.reverse.nxv3i64( %a) ret %res } @@ -1663,7 +1663,7 @@ define @reverse_nxv6i64( %a) { ; CHECK-NEXT: vmv2r.v v10, v28 ; CHECK-NEXT: vmv2r.v v12, v30 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv6i64( %a) + %res = call @llvm.vector.reverse.nxv6i64( %a) ret %res } @@ -1739,53 +1739,53 @@ define @reverse_nxv12i64( %a) { ; RV64-NEXT: ld s0, 64(sp) # 8-byte Folded Reload ; RV64-NEXT: addi sp, sp, 80 ; RV64-NEXT: ret - %res = call @llvm.experimental.vector.reverse.nxv12i64( %a) + %res = call @llvm.vector.reverse.nxv12i64( %a) ret %res } -declare @llvm.experimental.vector.reverse.nxv2i1() -declare @llvm.experimental.vector.reverse.nxv4i1() -declare @llvm.experimental.vector.reverse.nxv8i1() -declare @llvm.experimental.vector.reverse.nxv16i1() -declare @llvm.experimental.vector.reverse.nxv32i1() -declare @llvm.experimental.vector.reverse.nxv64i1() -declare @llvm.experimental.vector.reverse.nxv1i8() -declare @llvm.experimental.vector.reverse.nxv2i8() -declare @llvm.experimental.vector.reverse.nxv4i8() -declare @llvm.experimental.vector.reverse.nxv8i8() -declare @llvm.experimental.vector.reverse.nxv16i8() -declare @llvm.experimental.vector.reverse.nxv32i8() -declare @llvm.experimental.vector.reverse.nxv64i8() -declare @llvm.experimental.vector.reverse.nxv1i16() -declare @llvm.experimental.vector.reverse.nxv2i16() -declare @llvm.experimental.vector.reverse.nxv4i16() -declare @llvm.experimental.vector.reverse.nxv8i16() -declare @llvm.experimental.vector.reverse.nxv16i16() -declare @llvm.experimental.vector.reverse.nxv32i16() -declare @llvm.experimental.vector.reverse.nxv1i32() -declare @llvm.experimental.vector.reverse.nxv2i32() -declare @llvm.experimental.vector.reverse.nxv4i32() -declare @llvm.experimental.vector.reverse.nxv8i32() -declare @llvm.experimental.vector.reverse.nxv16i32() -declare @llvm.experimental.vector.reverse.nxv1i64() -declare @llvm.experimental.vector.reverse.nxv2i64() -declare @llvm.experimental.vector.reverse.nxv4i64() -declare @llvm.experimental.vector.reverse.nxv8i64() -declare @llvm.experimental.vector.reverse.nxv1f16() -declare @llvm.experimental.vector.reverse.nxv2f16() -declare @llvm.experimental.vector.reverse.nxv4f16() -declare @llvm.experimental.vector.reverse.nxv8f16() -declare @llvm.experimental.vector.reverse.nxv16f16() -declare @llvm.experimental.vector.reverse.nxv32f16() -declare @llvm.experimental.vector.reverse.nxv1f32() -declare @llvm.experimental.vector.reverse.nxv2f32() -declare @llvm.experimental.vector.reverse.nxv4f32() -declare @llvm.experimental.vector.reverse.nxv8f32() -declare @llvm.experimental.vector.reverse.nxv16f32() -declare @llvm.experimental.vector.reverse.nxv1f64() -declare @llvm.experimental.vector.reverse.nxv2f64() -declare @llvm.experimental.vector.reverse.nxv4f64() -declare @llvm.experimental.vector.reverse.nxv8f64() -declare @llvm.experimental.vector.reverse.nxv3i64() -declare @llvm.experimental.vector.reverse.nxv6i64() -declare @llvm.experimental.vector.reverse.nxv12i64() +declare @llvm.vector.reverse.nxv2i1() +declare @llvm.vector.reverse.nxv4i1() +declare @llvm.vector.reverse.nxv8i1() +declare @llvm.vector.reverse.nxv16i1() +declare @llvm.vector.reverse.nxv32i1() +declare @llvm.vector.reverse.nxv64i1() +declare @llvm.vector.reverse.nxv1i8() +declare @llvm.vector.reverse.nxv2i8() +declare @llvm.vector.reverse.nxv4i8() +declare @llvm.vector.reverse.nxv8i8() +declare @llvm.vector.reverse.nxv16i8() +declare @llvm.vector.reverse.nxv32i8() +declare @llvm.vector.reverse.nxv64i8() +declare @llvm.vector.reverse.nxv1i16() +declare @llvm.vector.reverse.nxv2i16() +declare @llvm.vector.reverse.nxv4i16() +declare @llvm.vector.reverse.nxv8i16() +declare @llvm.vector.reverse.nxv16i16() +declare @llvm.vector.reverse.nxv32i16() +declare @llvm.vector.reverse.nxv1i32() +declare @llvm.vector.reverse.nxv2i32() +declare @llvm.vector.reverse.nxv4i32() +declare @llvm.vector.reverse.nxv8i32() +declare @llvm.vector.reverse.nxv16i32() +declare @llvm.vector.reverse.nxv1i64() +declare @llvm.vector.reverse.nxv2i64() +declare @llvm.vector.reverse.nxv4i64() +declare @llvm.vector.reverse.nxv8i64() +declare @llvm.vector.reverse.nxv1f16() +declare @llvm.vector.reverse.nxv2f16() +declare @llvm.vector.reverse.nxv4f16() +declare @llvm.vector.reverse.nxv8f16() +declare @llvm.vector.reverse.nxv16f16() +declare @llvm.vector.reverse.nxv32f16() +declare @llvm.vector.reverse.nxv1f32() +declare @llvm.vector.reverse.nxv2f32() +declare @llvm.vector.reverse.nxv4f32() +declare @llvm.vector.reverse.nxv8f32() +declare @llvm.vector.reverse.nxv16f32() +declare @llvm.vector.reverse.nxv1f64() +declare @llvm.vector.reverse.nxv2f64() +declare @llvm.vector.reverse.nxv4f64() +declare @llvm.vector.reverse.nxv8f64() +declare @llvm.vector.reverse.nxv3i64() +declare @llvm.vector.reverse.nxv6i64() +declare @llvm.vector.reverse.nxv12i64() diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll index f3c70ed78c74..d02fe5b205f7 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-fixed.ll @@ -31,7 +31,7 @@ define {<16 x i1>, <16 x i1>} @vector_deinterleave_v16i1_v32i1(<32 x i1> %vec) { ; CHECK-NEXT: vmsne.vi v8, v13, 0 ; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: ret -%retval = call {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1> %vec) +%retval = call {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1> %vec) ret {<16 x i1>, <16 x i1>} %retval } @@ -44,7 +44,7 @@ define {<16 x i8>, <16 x i8>} @vector_deinterleave_v16i8_v32i8(<32 x i8> %vec) { ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v9, v11 ; CHECK-NEXT: ret -%retval = call {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %vec) +%retval = call {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8> %vec) ret {<16 x i8>, <16 x i8>} %retval } @@ -57,7 +57,7 @@ define {<8 x i16>, <8 x i16>} @vector_deinterleave_v8i16_v16i16(<16 x i16> %vec) ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v9, v11 ; CHECK-NEXT: ret -%retval = call {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %vec) +%retval = call {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16> %vec) ret {<8 x i16>, <8 x i16>} %retval } @@ -71,7 +71,7 @@ define {<4 x i32>, <4 x i32>} @vector_deinterleave_v4i32_vv8i32(<8 x i32> %vec) ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: vmv.v.v v9, v10 ; CHECK-NEXT: ret -%retval = call {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %vec) +%retval = call {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32> %vec) ret {<4 x i32>, <4 x i32>} %retval } @@ -87,15 +87,15 @@ define {<2 x i64>, <2 x i64>} @vector_deinterleave_v2i64_v4i64(<4 x i64> %vec) { ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret -%retval = call {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %vec) +%retval = call {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64> %vec) ret {<2 x i64>, <2 x i64>} %retval } -declare {<16 x i1>, <16 x i1>} @llvm.experimental.vector.deinterleave2.v32i1(<32 x i1>) -declare {<16 x i8>, <16 x i8>} @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>) -declare {<8 x i16>, <8 x i16>} @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>) -declare {<4 x i32>, <4 x i32>} @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>) -declare {<2 x i64>, <2 x i64>} @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>) +declare {<16 x i1>, <16 x i1>} @llvm.vector.deinterleave2.v32i1(<32 x i1>) +declare {<16 x i8>, <16 x i8>} @llvm.vector.deinterleave2.v32i8(<32 x i8>) +declare {<8 x i16>, <8 x i16>} @llvm.vector.deinterleave2.v16i16(<16 x i16>) +declare {<4 x i32>, <4 x i32>} @llvm.vector.deinterleave2.v8i32(<8 x i32>) +declare {<2 x i64>, <2 x i64>} @llvm.vector.deinterleave2.v4i64(<4 x i64>) ; Floats @@ -107,7 +107,7 @@ define {<2 x half>, <2 x half>} @vector_deinterleave_v2f16_v4f16(<4 x half> %vec ; CHECK-NEXT: vnsrl.wi v9, v8, 16 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret -%retval = call {<2 x half>, <2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half> %vec) +%retval = call {<2 x half>, <2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half> %vec) ret {<2 x half>, <2 x half>} %retval } @@ -119,7 +119,7 @@ define {<4 x half>, <4 x half>} @vector_deinterleave_v4f16_v8f16(<8 x half> %vec ; CHECK-NEXT: vnsrl.wi v9, v8, 16 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret -%retval = call {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half> %vec) +%retval = call {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half> %vec) ret {<4 x half>, <4 x half>} %retval } @@ -131,7 +131,7 @@ define {<2 x float>, <2 x float>} @vector_deinterleave_v2f32_v4f32(<4 x float> % ; CHECK-NEXT: vnsrl.wx v9, v8, a0 ; CHECK-NEXT: vnsrl.wi v8, v8, 0 ; CHECK-NEXT: ret -%retval = call {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float> %vec) +%retval = call {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float> %vec) ret {<2 x float>, <2 x float>} %retval } @@ -144,7 +144,7 @@ define {<8 x half>, <8 x half>} @vector_deinterleave_v8f16_v16f16(<16 x half> %v ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v9, v11 ; CHECK-NEXT: ret -%retval = call {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half> %vec) +%retval = call {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half> %vec) ret {<8 x half>, <8 x half>} %retval } @@ -158,7 +158,7 @@ define {<4 x float>, <4 x float>} @vector_deinterleave_v4f32_v8f32(<8 x float> % ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: vmv.v.v v9, v10 ; CHECK-NEXT: ret -%retval = call {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %vec) +%retval = call {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float> %vec) ret {<4 x float>, <4 x float>} %retval } @@ -174,13 +174,13 @@ define {<2 x double>, <2 x double>} @vector_deinterleave_v2f64_v4f64(<4 x double ; CHECK-NEXT: vmerge.vvm v9, v9, v10, v0 ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret -%retval = call {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %vec) +%retval = call {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double> %vec) ret {<2 x double>, <2 x double>} %retval } -declare {<2 x half>,<2 x half>} @llvm.experimental.vector.deinterleave2.v4f16(<4 x half>) -declare {<4 x half>, <4 x half>} @llvm.experimental.vector.deinterleave2.v8f16(<8 x half>) -declare {<2 x float>, <2 x float>} @llvm.experimental.vector.deinterleave2.v4f32(<4 x float>) -declare {<8 x half>, <8 x half>} @llvm.experimental.vector.deinterleave2.v16f16(<16 x half>) -declare {<4 x float>, <4 x float>} @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>) -declare {<2 x double>, <2 x double>} @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>) +declare {<2 x half>,<2 x half>} @llvm.vector.deinterleave2.v4f16(<4 x half>) +declare {<4 x half>, <4 x half>} @llvm.vector.deinterleave2.v8f16(<8 x half>) +declare {<2 x float>, <2 x float>} @llvm.vector.deinterleave2.v4f32(<4 x float>) +declare {<8 x half>, <8 x half>} @llvm.vector.deinterleave2.v16f16(<16 x half>) +declare {<4 x float>, <4 x float>} @llvm.vector.deinterleave2.v8f32(<8 x float>) +declare {<2 x double>, <2 x double>} @llvm.vector.deinterleave2.v4f64(<4 x double>) diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll index 6a712080fda7..8f4ff37fffb0 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave-load.ll @@ -24,7 +24,7 @@ define {, } @vector_deinterleave_load_nxv16i ; CHECK-NEXT: vmsne.vi v9, v10, 0 ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32i1( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv32i1( %vec) ret {, } %retval } @@ -35,7 +35,7 @@ define {, } @vector_deinterleave_load_nxv16i ; CHECK-NEXT: vlseg2e8.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32i8( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv32i8( %vec) ret {, } %retval } @@ -49,7 +49,7 @@ define {, } @vector_deinterleave_load_nxv8i1 ; CHECK-NEXT: vnsrl.wi v10, v12, 16 ; CHECK-NEXT: ret %vec = load , ptr %p, align 1 - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv16i16( %vec) ret {, } %retval } @@ -60,7 +60,7 @@ define {, } @vector_deinterleave_load_nxv8i1 ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv16i16( %vec) ret {, } %retval } @@ -71,7 +71,7 @@ define {, } @vector_deinterleave_load_nxv4i3 ; CHECK-NEXT: vlseg2e32.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8i32( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8i32( %vec) ret {, } %retval } @@ -82,7 +82,7 @@ define {, } @vector_deinterleave_load_nxv2i6 ; CHECK-NEXT: vlseg2e64.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4i64( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4i64( %vec) ret {, } %retval } @@ -93,7 +93,7 @@ define {, } @vector_deinterleave_load_nxv4i6 ; CHECK-NEXT: vlseg2e64.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8i64( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8i64( %vec) ret {, } %retval } @@ -171,17 +171,17 @@ define {, } @vector_deinterleave_load_nxv8i6 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i64( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv16i64( %vec) ret {, } %retval } -declare {, } @llvm.experimental.vector.deinterleave2.nxv32i1() -declare {, } @llvm.experimental.vector.deinterleave2.nxv32i8() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8i32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4i64() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8i64() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i64() +declare {, } @llvm.vector.deinterleave2.nxv32i1() +declare {, } @llvm.vector.deinterleave2.nxv32i8() +declare {, } @llvm.vector.deinterleave2.nxv16i16() +declare {, } @llvm.vector.deinterleave2.nxv8i32() +declare {, } @llvm.vector.deinterleave2.nxv4i64() +declare {, } @llvm.vector.deinterleave2.nxv8i64() +declare {, } @llvm.vector.deinterleave2.nxv16i64() ; Floats @@ -192,7 +192,7 @@ define {, } @vector_deinterleave_load_nxv2 ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4f16( %vec) ret {, } %retval } @@ -203,7 +203,7 @@ define {, } @vector_deinterleave_load_nxv4 ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8f16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8f16( %vec) ret {, } %retval } @@ -214,7 +214,7 @@ define {, } @vector_deinterleave_load_nx ; CHECK-NEXT: vlseg2e32.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f32( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4f32( %vec) ret {, } %retval } @@ -225,7 +225,7 @@ define {, } @vector_deinterleave_load_nxv8 ; CHECK-NEXT: vlseg2e16.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16f16( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv16f16( %vec) ret {, } %retval } @@ -236,7 +236,7 @@ define {, } @vector_deinterleave_load_nx ; CHECK-NEXT: vlseg2e32.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8f32( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv8f32( %vec) ret {, } %retval } @@ -247,13 +247,13 @@ define {, } @vector_deinterleave_load_ ; CHECK-NEXT: vlseg2e64.v v8, (a0) ; CHECK-NEXT: ret %vec = load , ptr %p - %retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f64( %vec) + %retval = call {, } @llvm.vector.deinterleave2.nxv4f64( %vec) ret {, } %retval } -declare {,} @llvm.experimental.vector.deinterleave2.nxv4f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4f32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8f32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4f64() +declare {,} @llvm.vector.deinterleave2.nxv4f16() +declare {, } @llvm.vector.deinterleave2.nxv8f16() +declare {, } @llvm.vector.deinterleave2.nxv4f32() +declare {, } @llvm.vector.deinterleave2.nxv16f16() +declare {, } @llvm.vector.deinterleave2.nxv8f32() +declare {, } @llvm.vector.deinterleave2.nxv4f64() diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll index d98597fabcd9..7797577362c9 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-deinterleave.ll @@ -21,7 +21,7 @@ define {, } @vector_deinterleave_nxv16i1_nxv ; CHECK-NEXT: vnsrl.wi v10, v12, 8 ; CHECK-NEXT: vmsne.vi v9, v10, 0 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32i1( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv32i1( %vec) ret {, } %retval } @@ -34,7 +34,7 @@ define {, } @vector_deinterleave_nxv16i8_nxv ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v10, v14 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32i8( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv32i8( %vec) ret {, } %retval } @@ -47,7 +47,7 @@ define {, } @vector_deinterleave_nxv8i16_nxv ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v10, v14 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i16( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv16i16( %vec) ret {, } %retval } @@ -61,7 +61,7 @@ define {, } @vector_deinterleave_nxv4i32_nxv ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: vmv.v.v v10, v12 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8i32( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv8i32( %vec) ret {, } %retval } @@ -77,15 +77,15 @@ define {, } @vector_deinterleave_nxv2i64_nxv ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: vmv2r.v v10, v20 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4i64( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv4i64( %vec) ret {, } %retval } -declare {, } @llvm.experimental.vector.deinterleave2.nxv32i1() -declare {, } @llvm.experimental.vector.deinterleave2.nxv32i8() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8i32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4i64() +declare {, } @llvm.vector.deinterleave2.nxv32i1() +declare {, } @llvm.vector.deinterleave2.nxv32i8() +declare {, } @llvm.vector.deinterleave2.nxv16i16() +declare {, } @llvm.vector.deinterleave2.nxv8i32() +declare {, } @llvm.vector.deinterleave2.nxv4i64() define {, } @vector_deinterleave_nxv64i1_nxv128i1( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv64i1_nxv128i1: @@ -110,7 +110,7 @@ define {, } @vector_deinterleave_nxv64i1_nxv ; CHECK-NEXT: vmsne.vi v9, v24, 0 ; CHECK-NEXT: vmv1r.v v8, v7 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv128i1( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv128i1( %vec) ret {, } %retval } @@ -125,7 +125,7 @@ define {, } @vector_deinterleave_nxv64i8_nxv ; CHECK-NEXT: vnsrl.wi v4, v16, 8 ; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv128i8( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv128i8( %vec) ret {, } %retval } @@ -140,7 +140,7 @@ define {, } @vector_deinterleave_nxv32i16_ ; CHECK-NEXT: vnsrl.wi v4, v16, 16 ; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv64i16( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv64i16( %vec) ret {, } %retval } @@ -156,7 +156,7 @@ define {, } @vector_deinterleave_nxv16i32_ ; CHECK-NEXT: vnsrl.wi v4, v24, 0 ; CHECK-NEXT: vmv8r.v v8, v0 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32i32( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv32i32( %vec) ret {, } %retval } @@ -229,15 +229,15 @@ define {, } @vector_deinterleave_nxv8i64_nxv ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16i64( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv16i64( %vec) ret {, } %retval } -declare {, } @llvm.experimental.vector.deinterleave2.nxv128i1() -declare {, } @llvm.experimental.vector.deinterleave2.nxv128i8() -declare {, } @llvm.experimental.vector.deinterleave2.nxv64i16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv32i32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16i64() +declare {, } @llvm.vector.deinterleave2.nxv128i1() +declare {, } @llvm.vector.deinterleave2.nxv128i8() +declare {, } @llvm.vector.deinterleave2.nxv64i16() +declare {, } @llvm.vector.deinterleave2.nxv32i32() +declare {, } @llvm.vector.deinterleave2.nxv16i64() ; Floats @@ -249,7 +249,7 @@ define {, } @vector_deinterleave_nxv2f16_n ; CHECK-NEXT: vnsrl.wi v9, v8, 16 ; CHECK-NEXT: vmv1r.v v8, v10 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f16( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv4f16( %vec) ret {, } %retval } @@ -262,7 +262,7 @@ define {, } @vector_deinterleave_nxv4f16_n ; CHECK-NEXT: vmv.v.v v8, v10 ; CHECK-NEXT: vmv.v.v v9, v11 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8f16( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv8f16( %vec) ret {, } %retval } @@ -276,7 +276,7 @@ define {, } @vector_deinterleave_nxv2f32 ; CHECK-NEXT: vmv.v.v v8, v11 ; CHECK-NEXT: vmv.v.v v9, v10 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f32( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv4f32( %vec) ret {, } %retval } @@ -289,7 +289,7 @@ define {, } @vector_deinterleave_nxv8f16_n ; CHECK-NEXT: vmv.v.v v8, v12 ; CHECK-NEXT: vmv.v.v v10, v14 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16f16( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv16f16( %vec) ret {, } %retval } @@ -303,7 +303,7 @@ define {, } @vector_deinterleave_nxv4f32 ; CHECK-NEXT: vmv.v.v v8, v14 ; CHECK-NEXT: vmv.v.v v10, v12 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv8f32( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv8f32( %vec) ret {, } %retval } @@ -319,16 +319,16 @@ define {, } @vector_deinterleave_nxv2f ; CHECK-NEXT: vmv2r.v v8, v12 ; CHECK-NEXT: vmv2r.v v10, v20 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv4f64( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv4f64( %vec) ret {, } %retval } -declare {,} @llvm.experimental.vector.deinterleave2.nxv4f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4f32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv8f32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv4f64() +declare {,} @llvm.vector.deinterleave2.nxv4f16() +declare {, } @llvm.vector.deinterleave2.nxv8f16() +declare {, } @llvm.vector.deinterleave2.nxv4f32() +declare {, } @llvm.vector.deinterleave2.nxv16f16() +declare {, } @llvm.vector.deinterleave2.nxv8f32() +declare {, } @llvm.vector.deinterleave2.nxv4f64() define {, } @vector_deinterleave_nxv32f16_nxv64f16( %vec) { ; CHECK-LABEL: vector_deinterleave_nxv32f16_nxv64f16: @@ -341,7 +341,7 @@ define {, } @vector_deinterleave_nxv32f1 ; CHECK-NEXT: vnsrl.wi v4, v16, 16 ; CHECK-NEXT: vmv8r.v v16, v0 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv64f16( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv64f16( %vec) ret {, } %retval } @@ -357,7 +357,7 @@ define {, } @vector_deinterleave_nxv16 ; CHECK-NEXT: vnsrl.wi v4, v24, 0 ; CHECK-NEXT: vmv8r.v v8, v0 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv32f32( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv32f32( %vec) ret {, } %retval } @@ -430,10 +430,10 @@ define {, } @vector_deinterleave_nxv8f ; CHECK-NEXT: add sp, sp, a0 ; CHECK-NEXT: addi sp, sp, 16 ; CHECK-NEXT: ret -%retval = call {, } @llvm.experimental.vector.deinterleave2.nxv16f64( %vec) +%retval = call {, } @llvm.vector.deinterleave2.nxv16f64( %vec) ret {, } %retval } -declare {, } @llvm.experimental.vector.deinterleave2.nxv64f16() -declare {, } @llvm.experimental.vector.deinterleave2.nxv32f32() -declare {, } @llvm.experimental.vector.deinterleave2.nxv16f64() +declare {, } @llvm.vector.deinterleave2.nxv64f16() +declare {, } @llvm.vector.deinterleave2.nxv32f32() +declare {, } @llvm.vector.deinterleave2.nxv16f64() diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll index 6ebe8e095469..99872c199a1e 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-fixed.ll @@ -41,7 +41,7 @@ define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) { ; ZVBB-NEXT: vsetvli zero, a0, e8, m2, ta, ma ; ZVBB-NEXT: vmsne.vi v0, v12, 0 ; ZVBB-NEXT: ret - %res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b) + %res = call <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b) ret <32 x i1> %res } @@ -62,7 +62,7 @@ define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) { ; ZVBB-NEXT: vwaddu.wv v10, v10, v8 ; ZVBB-NEXT: vmv2r.v v8, v10 ; ZVBB-NEXT: ret - %res = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b) + %res = call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b) ret <16 x i16> %res } @@ -84,7 +84,7 @@ define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) { ; ZVBB-NEXT: vwaddu.wv v10, v10, v8 ; ZVBB-NEXT: vmv2r.v v8, v10 ; ZVBB-NEXT: ret - %res = call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b) + %res = call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b) ret <8 x i32> %res } @@ -118,14 +118,14 @@ define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) { ; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12 ; ZVBB-NEXT: vmv.v.v v8, v10 ; ZVBB-NEXT: ret - %res = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b) + %res = call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b) ret <4 x i64> %res } -declare <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1>, <16 x i1>) -declare <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) -declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) -declare <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) +declare <32 x i1> @llvm.vector.interleave2.v32i1(<16 x i1>, <16 x i1>) +declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) +declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) ; Floats @@ -146,7 +146,7 @@ define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) { ; ZVBB-NEXT: vwaddu.wv v10, v10, v8 ; ZVBB-NEXT: vmv1r.v v8, v10 ; ZVBB-NEXT: ret - %res = call <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b) + %res = call <4 x half> @llvm.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b) ret <4 x half> %res } @@ -167,7 +167,7 @@ define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) { ; ZVBB-NEXT: vwaddu.wv v10, v10, v8 ; ZVBB-NEXT: vmv1r.v v8, v10 ; ZVBB-NEXT: ret - %res = call <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b) + %res = call <8 x half> @llvm.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b) ret <8 x half> %res } @@ -189,7 +189,7 @@ define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b ; ZVBB-NEXT: vwaddu.wv v10, v10, v8 ; ZVBB-NEXT: vmv1r.v v8, v10 ; ZVBB-NEXT: ret - %res = call <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b) + %res = call <4 x float> @llvm.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b) ret <4 x float> %res } @@ -210,7 +210,7 @@ define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) ; ZVBB-NEXT: vwaddu.wv v10, v10, v8 ; ZVBB-NEXT: vmv2r.v v8, v10 ; ZVBB-NEXT: ret - %res = call <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b) + %res = call <16 x half> @llvm.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b) ret <16 x half> %res } @@ -232,7 +232,7 @@ define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b ; ZVBB-NEXT: vwaddu.wv v10, v10, v8 ; ZVBB-NEXT: vmv2r.v v8, v10 ; ZVBB-NEXT: ret - %res = call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b) + %res = call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b) ret <8 x float> %res } @@ -266,17 +266,17 @@ define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> ; ZVBB-NEXT: vrgatherei16.vv v10, v8, v12 ; ZVBB-NEXT: vmv.v.v v8, v10 ; ZVBB-NEXT: ret - %res = call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b) + %res = call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b) ret <4 x double> %res } -declare <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half>, <2 x half>) -declare <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half>, <4 x half>) -declare <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float>, <2 x float>) -declare <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half>, <8 x half>) -declare <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float>, <4 x float>) -declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double>, <2 x double>) +declare <4 x half> @llvm.vector.interleave2.v4f16(<2 x half>, <2 x half>) +declare <8 x half> @llvm.vector.interleave2.v8f16(<4 x half>, <4 x half>) +declare <4 x float> @llvm.vector.interleave2.v4f32(<2 x float>, <2 x float>) +declare <16 x half> @llvm.vector.interleave2.v16f16(<8 x half>, <8 x half>) +declare <8 x float> @llvm.vector.interleave2.v8f32(<4 x float>, <4 x float>) +declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double>, <2 x double>) ;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line: ; RV32: {{.*}} ; RV64: {{.*}} diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll index 922692ed88c9..7ade47e60bc6 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave-store.ll @@ -27,7 +27,7 @@ define void @vector_interleave_store_nxv32i1_nxv16i1( %a, @llvm.experimental.vector.interleave2.nxv32i1( %a, %b) + %res = call @llvm.vector.interleave2.nxv32i1( %a, %b) store %res, ptr %p ret void } @@ -42,7 +42,7 @@ define void @vector_interleave_store_nxv16i16_nxv8i16_align1( ; CHECK-NEXT: vwmaccu.vx v12, a1, v10 ; CHECK-NEXT: vs4r.v v12, (a0) ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.interleave2.nxv16i16( %a, %b) + %res = call @llvm.vector.interleave2.nxv16i16( %a, %b) store %res, ptr %p, align 1 ret void } @@ -53,7 +53,7 @@ define void @vector_interleave_store_nxv16i16_nxv8i16( %a, @llvm.experimental.vector.interleave2.nxv16i16( %a, %b) + %res = call @llvm.vector.interleave2.nxv16i16( %a, %b) store %res, ptr %p ret void } @@ -64,7 +64,7 @@ define void @vector_interleave_store_nxv8i32_nxv4i32( %a, @llvm.experimental.vector.interleave2.nxv8i32( %a, %b) + %res = call @llvm.vector.interleave2.nxv8i32( %a, %b) store %res, ptr %p ret void } @@ -75,7 +75,7 @@ define void @vector_interleave_store_nxv4i64_nxv2i64( %a, @llvm.experimental.vector.interleave2.nxv4i64( %a, %b) + %res = call @llvm.vector.interleave2.nxv4i64( %a, %b) store %res, ptr %p ret void } @@ -86,7 +86,7 @@ define void @vector_interleave_store_nxv8i64_nxv4i64( %a, @llvm.experimental.vector.interleave2.nxv8i64( %a, %b) + %res = call @llvm.vector.interleave2.nxv8i64( %a, %b) store %res, ptr %p ret void } @@ -138,17 +138,17 @@ define void @vector_interleave_store_nxv16i64_nxv8i64( %a, @llvm.experimental.vector.interleave2.nxv16i64( %a, %b) + %res = call @llvm.vector.interleave2.nxv16i64( %a, %b) store %res, ptr %p ret void } -declare @llvm.experimental.vector.interleave2.nxv32i1(, ) -declare @llvm.experimental.vector.interleave2.nxv16i16(, ) -declare @llvm.experimental.vector.interleave2.nxv8i32(, ) -declare @llvm.experimental.vector.interleave2.nxv4i64(, ) -declare @llvm.experimental.vector.interleave2.nxv8i64(, ) -declare @llvm.experimental.vector.interleave2.nxv16i64(, ) +declare @llvm.vector.interleave2.nxv32i1(, ) +declare @llvm.vector.interleave2.nxv16i16(, ) +declare @llvm.vector.interleave2.nxv8i32(, ) +declare @llvm.vector.interleave2.nxv4i64(, ) +declare @llvm.vector.interleave2.nxv8i64(, ) +declare @llvm.vector.interleave2.nxv16i64(, ) ; Floats @@ -158,7 +158,7 @@ define void @vector_interleave_store_nxv4f16_nxv2f16( %a, @llvm.experimental.vector.interleave2.nxv4f16( %a, %b) + %res = call @llvm.vector.interleave2.nxv4f16( %a, %b) store %res, ptr %p ret void } @@ -169,7 +169,7 @@ define void @vector_interleave_store_nxv8f16_nxv4f16( %a, @llvm.experimental.vector.interleave2.nxv8f16( %a, %b) + %res = call @llvm.vector.interleave2.nxv8f16( %a, %b) store %res, ptr %p ret void } @@ -180,7 +180,7 @@ define void @vector_interleave_store_nxv4f32_nxv2f32( %a, @llvm.experimental.vector.interleave2.nxv4f32( %a, %b) + %res = call @llvm.vector.interleave2.nxv4f32( %a, %b) store %res, ptr %p ret void } @@ -191,7 +191,7 @@ define void @vector_interleave_store_nxv16f16_nxv8f16( %a, @llvm.experimental.vector.interleave2.nxv16f16( %a, %b) + %res = call @llvm.vector.interleave2.nxv16f16( %a, %b) store %res, ptr %p ret void } @@ -202,7 +202,7 @@ define void @vector_interleave_store_nxv8f32_nxv4f32( %a, @llvm.experimental.vector.interleave2.nxv8f32( %a, %b) + %res = call @llvm.vector.interleave2.nxv8f32( %a, %b) store %res, ptr %p ret void } @@ -213,15 +213,15 @@ define void @vector_interleave_store_nxv4f64_nxv2f64( %a, < ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vsseg2e64.v v8, (a0) ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.interleave2.nxv4f64( %a, %b) + %res = call @llvm.vector.interleave2.nxv4f64( %a, %b) store %res, ptr %p ret void } -declare @llvm.experimental.vector.interleave2.nxv4f16(, ) -declare @llvm.experimental.vector.interleave2.nxv8f16(, ) -declare @llvm.experimental.vector.interleave2.nxv4f32(, ) -declare @llvm.experimental.vector.interleave2.nxv16f16(, ) -declare @llvm.experimental.vector.interleave2.nxv8f32(, ) -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare @llvm.vector.interleave2.nxv4f16(, ) +declare @llvm.vector.interleave2.nxv8f16(, ) +declare @llvm.vector.interleave2.nxv4f32(, ) +declare @llvm.vector.interleave2.nxv16f16(, ) +declare @llvm.vector.interleave2.nxv8f32(, ) +declare @llvm.vector.interleave2.nxv4f64(, ) diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll index 327e18e91381..a7e0ad6ee5f4 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-interleave.ll @@ -47,7 +47,7 @@ define @vector_interleave_nxv32i1_nxv16i1( ; ZVBB-NEXT: vsetvli zero, a1, e8, mf2, ta, ma ; ZVBB-NEXT: vslideup.vx v0, v8, a0 ; ZVBB-NEXT: ret - %res = call @llvm.experimental.vector.interleave2.nxv32i1( %a, %b) + %res = call @llvm.vector.interleave2.nxv32i1( %a, %b) ret %res } @@ -68,7 +68,7 @@ define @vector_interleave_nxv32i8_nxv16i8( ; ZVBB-NEXT: vwaddu.wv v12, v12, v8 ; ZVBB-NEXT: vmv4r.v v8, v12 ; ZVBB-NEXT: ret - %res = call @llvm.experimental.vector.interleave2.nxv32i8( %a, %b) + %res = call @llvm.vector.interleave2.nxv32i8( %a, %b) ret %res } @@ -89,7 +89,7 @@ define @vector_interleave_nxv16i16_nxv8i16( @llvm.experimental.vector.interleave2.nxv16i16( %a, %b) + %res = call @llvm.vector.interleave2.nxv16i16( %a, %b) ret %res } @@ -111,7 +111,7 @@ define @vector_interleave_nxv8i32_nxv4i32( ; ZVBB-NEXT: vwaddu.wv v12, v12, v8 ; ZVBB-NEXT: vmv4r.v v8, v12 ; ZVBB-NEXT: ret - %res = call @llvm.experimental.vector.interleave2.nxv8i32( %a, %b) + %res = call @llvm.vector.interleave2.nxv8i32( %a, %b) ret %res } @@ -145,15 +145,15 @@ define @vector_interleave_nxv4i64_nxv2i64( ; ZVBB-NEXT: vrgatherei16.vv v12, v8, v16 ; ZVBB-NEXT: vmv.v.v v8, v12 ; ZVBB-NEXT: ret - %res = call @llvm.experimental.vector.interleave2.nxv4i64( %a, %b) + %res = call @llvm.vector.interleave2.nxv4i64( %a, %b) ret %res } -declare @llvm.experimental.vector.interleave2.nxv32i1(, ) -declare @llvm.experimental.vector.interleave2.nxv32i8(, ) -declare @llvm.experimental.vector.interleave2.nxv16i16(, ) -declare @llvm.experimental.vector.interleave2.nxv8i32(, ) -declare @llvm.experimental.vector.interleave2.nxv4i64(, ) +declare @llvm.vector.interleave2.nxv32i1(, ) +declare @llvm.vector.interleave2.nxv32i8(, ) +declare @llvm.vector.interleave2.nxv16i16(, ) +declare @llvm.vector.interleave2.nxv8i32(, ) +declare @llvm.vector.interleave2.nxv4i64(, ) define @vector_interleave_nxv128i1_nxv64i1( %a, %b) { ; CHECK-LABEL: vector_interleave_nxv128i1_nxv64i1: @@ -196,7 +196,7 @@ define @vector_interleave_nxv128i1_nxv64i1( @llvm.experimental.vector.interleave2.nxv128i1( %a, %b) + %res = call @llvm.vector.interleave2.nxv128i1( %a, %b) ret %res } @@ -223,7 +223,7 @@ define @vector_interleave_nxv128i8_nxv64i8( @llvm.experimental.vector.interleave2.nxv128i8( %a, %b) + %res = call @llvm.vector.interleave2.nxv128i8( %a, %b) ret %res } @@ -250,7 +250,7 @@ define @vector_interleave_nxv64i16_nxv32i16( @llvm.experimental.vector.interleave2.nxv64i16( %a, %b) + %res = call @llvm.vector.interleave2.nxv64i16( %a, %b) ret %res } @@ -278,7 +278,7 @@ define @vector_interleave_nxv32i32_nxv16i32( @llvm.experimental.vector.interleave2.nxv32i32( %a, %b) + %res = call @llvm.vector.interleave2.nxv32i32( %a, %b) ret %res } @@ -376,15 +376,15 @@ define @vector_interleave_nxv16i64_nxv8i64( @llvm.experimental.vector.interleave2.nxv16i64( %a, %b) + %res = call @llvm.vector.interleave2.nxv16i64( %a, %b) ret %res } -declare @llvm.experimental.vector.interleave2.nxv128i1(, ) -declare @llvm.experimental.vector.interleave2.nxv128i8(, ) -declare @llvm.experimental.vector.interleave2.nxv64i16(, ) -declare @llvm.experimental.vector.interleave2.nxv32i32(, ) -declare @llvm.experimental.vector.interleave2.nxv16i64(, ) +declare @llvm.vector.interleave2.nxv128i1(, ) +declare @llvm.vector.interleave2.nxv128i8(, ) +declare @llvm.vector.interleave2.nxv64i16(, ) +declare @llvm.vector.interleave2.nxv32i32(, ) +declare @llvm.vector.interleave2.nxv16i64(, ) ; Floats @@ -419,7 +419,7 @@ define @vector_interleave_nxv4f16_nxv2f16( @llvm.experimental.vector.interleave2.nxv4f16( %a, %b) + %res = call @llvm.vector.interleave2.nxv4f16( %a, %b) ret %res } @@ -440,7 +440,7 @@ define @vector_interleave_nxv8f16_nxv4f16( @llvm.experimental.vector.interleave2.nxv8f16( %a, %b) + %res = call @llvm.vector.interleave2.nxv8f16( %a, %b) ret %res } @@ -462,7 +462,7 @@ define @vector_interleave_nxv4f32_nxv2f32( @llvm.experimental.vector.interleave2.nxv4f32( %a, %b) + %res = call @llvm.vector.interleave2.nxv4f32( %a, %b) ret %res } @@ -483,7 +483,7 @@ define @vector_interleave_nxv16f16_nxv8f16( @llvm.experimental.vector.interleave2.nxv16f16( %a, %b) + %res = call @llvm.vector.interleave2.nxv16f16( %a, %b) ret %res } @@ -505,7 +505,7 @@ define @vector_interleave_nxv8f32_nxv4f32( @llvm.experimental.vector.interleave2.nxv8f32( %a, %b) + %res = call @llvm.vector.interleave2.nxv8f32( %a, %b) ret %res } @@ -539,17 +539,17 @@ define @vector_interleave_nxv4f64_nxv2f64( @llvm.experimental.vector.interleave2.nxv4f64( %a, %b) + %res = call @llvm.vector.interleave2.nxv4f64( %a, %b) ret %res } -declare @llvm.experimental.vector.interleave2.nxv4f16(, ) -declare @llvm.experimental.vector.interleave2.nxv8f16(, ) -declare @llvm.experimental.vector.interleave2.nxv4f32(, ) -declare @llvm.experimental.vector.interleave2.nxv16f16(, ) -declare @llvm.experimental.vector.interleave2.nxv8f32(, ) -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) +declare @llvm.vector.interleave2.nxv4f16(, ) +declare @llvm.vector.interleave2.nxv8f16(, ) +declare @llvm.vector.interleave2.nxv4f32(, ) +declare @llvm.vector.interleave2.nxv16f16(, ) +declare @llvm.vector.interleave2.nxv8f32(, ) +declare @llvm.vector.interleave2.nxv4f64(, ) define @vector_interleave_nxv64f16_nxv32f16( %a, %b) { ; CHECK-LABEL: vector_interleave_nxv64f16_nxv32f16: @@ -574,7 +574,7 @@ define @vector_interleave_nxv64f16_nxv32f16( @llvm.experimental.vector.interleave2.nxv64f16( %a, %b) + %res = call @llvm.vector.interleave2.nxv64f16( %a, %b) ret %res } @@ -602,7 +602,7 @@ define @vector_interleave_nxv32f32_nxv16f32( @llvm.experimental.vector.interleave2.nxv32f32( %a, %b) + %res = call @llvm.vector.interleave2.nxv32f32( %a, %b) ret %res } @@ -700,7 +700,7 @@ define @vector_interleave_nxv16f64_nxv8f64( @llvm.experimental.vector.interleave2.nxv16f64( %a, %b) + %res = call @llvm.vector.interleave2.nxv16f64( %a, %b) ret %res } @@ -718,7 +718,7 @@ define @vector_interleave_nxv8i32_nxv4i32_poison( @llvm.experimental.vector.interleave2.nxv8i32( %a, poison) + %res = call @llvm.vector.interleave2.nxv8i32( %a, poison) ret %res } @@ -738,10 +738,10 @@ define @vector_interleave_nxv8i32_nxv4i32_poison2( @llvm.experimental.vector.interleave2.nxv8i32( poison, %a) + %res = call @llvm.vector.interleave2.nxv8i32( poison, %a) ret %res } -declare @llvm.experimental.vector.interleave2.nxv64f16(, ) -declare @llvm.experimental.vector.interleave2.nxv32f32(, ) -declare @llvm.experimental.vector.interleave2.nxv16f64(, ) +declare @llvm.vector.interleave2.nxv64f16(, ) +declare @llvm.vector.interleave2.nxv32f32(, ) +declare @llvm.vector.interleave2.nxv16f64(, ) diff --git a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll index c98242437f62..be56db52e349 100644 --- a/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll +++ b/llvm/test/CodeGen/RISCV/rvv/vector-splice.ll @@ -4,7 +4,7 @@ ; Tests assume VLEN=128 or vscale_range_min=2. -declare @llvm.experimental.vector.splice.nxv1i1(, , i32) +declare @llvm.vector.splice.nxv1i1(, , i32) define @splice_nxv1i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i1_offset_negone: @@ -24,7 +24,7 @@ define @splice_nxv1i1_offset_negone( %a, @llvm.experimental.vector.splice.nxv1i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1i1( %a, %b, i32 -1) ret %res } @@ -48,11 +48,11 @@ define @splice_nxv1i1_offset_max( %a, @llvm.experimental.vector.splice.nxv1i1( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1i1( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2i1(, , i32) +declare @llvm.vector.splice.nxv2i1(, , i32) define @splice_nxv2i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i1_offset_negone: @@ -72,7 +72,7 @@ define @splice_nxv2i1_offset_negone( %a, @llvm.experimental.vector.splice.nxv2i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2i1( %a, %b, i32 -1) ret %res } @@ -96,11 +96,11 @@ define @splice_nxv2i1_offset_max( %a, @llvm.experimental.vector.splice.nxv2i1( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2i1( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4i1(, , i32) +declare @llvm.vector.splice.nxv4i1(, , i32) define @splice_nxv4i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i1_offset_negone: @@ -120,7 +120,7 @@ define @splice_nxv4i1_offset_negone( %a, @llvm.experimental.vector.splice.nxv4i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4i1( %a, %b, i32 -1) ret %res } @@ -144,11 +144,11 @@ define @splice_nxv4i1_offset_max( %a, @llvm.experimental.vector.splice.nxv4i1( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4i1( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8i1(, , i32) +declare @llvm.vector.splice.nxv8i1(, , i32) define @splice_nxv8i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i1_offset_negone: @@ -167,7 +167,7 @@ define @splice_nxv8i1_offset_negone( %a, @llvm.experimental.vector.splice.nxv8i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8i1( %a, %b, i32 -1) ret %res } @@ -190,11 +190,11 @@ define @splice_nxv8i1_offset_max( %a, @llvm.experimental.vector.splice.nxv8i1( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8i1( %a, %b, i32 15) ret %res } -declare @llvm.experimental.vector.splice.nxv16i1(, , i32) +declare @llvm.vector.splice.nxv16i1(, , i32) define @splice_nxv16i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i1_offset_negone: @@ -216,7 +216,7 @@ define @splice_nxv16i1_offset_negone( %a, < ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16i1( %a, %b, i32 -1) ret %res } @@ -240,11 +240,11 @@ define @splice_nxv16i1_offset_max( %a, @llvm.experimental.vector.splice.nxv16i1( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv16i1( %a, %b, i32 31) ret %res } -declare @llvm.experimental.vector.splice.nxv32i1(, , i32) +declare @llvm.vector.splice.nxv32i1(, , i32) define @splice_nxv32i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i1_offset_negone: @@ -266,7 +266,7 @@ define @splice_nxv32i1_offset_negone( %a, < ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv32i1( %a, %b, i32 -1) ret %res } @@ -289,11 +289,11 @@ define @splice_nxv32i1_offset_max( %a, @llvm.experimental.vector.splice.nxv32i1( %a, %b, i32 63) + %res = call @llvm.vector.splice.nxv32i1( %a, %b, i32 63) ret %res } -declare @llvm.experimental.vector.splice.nxv64i1(, , i32) +declare @llvm.vector.splice.nxv64i1(, , i32) define @splice_nxv64i1_offset_negone( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i1_offset_negone: @@ -315,7 +315,7 @@ define @splice_nxv64i1_offset_negone( %a, < ; CHECK-NEXT: vand.vi v8, v8, 1 ; CHECK-NEXT: vmsne.vi v0, v8, 0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv64i1( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv64i1( %a, %b, i32 -1) ret %res } @@ -338,17 +338,17 @@ define @splice_nxv64i1_offset_max( %a, @llvm.experimental.vector.splice.nxv64i1( %a, %b, i32 127) + %res = call @llvm.vector.splice.nxv64i1( %a, %b, i32 127) ret %res } -declare @llvm.experimental.vector.splice.nxv1i8(, , i32) +declare @llvm.vector.splice.nxv1i8(, , i32) define @splice_nxv1i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv1i8( %a, %b, i32 0) ret %res } @@ -363,7 +363,7 @@ define @splice_nxv1i8_offset_negone( %a, @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1i8( %a, %b, i32 -1) ret %res } @@ -378,7 +378,7 @@ define @splice_nxv1i8_offset_min( %a, @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv1i8( %a, %b, i32 -2) ret %res } @@ -393,17 +393,17 @@ define @splice_nxv1i8_offset_max( %a, @llvm.experimental.vector.splice.nxv1i8( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1i8( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2i8(, , i32) +declare @llvm.vector.splice.nxv2i8(, , i32) define @splice_nxv2i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv2i8( %a, %b, i32 0) ret %res } @@ -418,7 +418,7 @@ define @splice_nxv2i8_offset_negone( %a, @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2i8( %a, %b, i32 -1) ret %res } @@ -433,7 +433,7 @@ define @splice_nxv2i8_offset_min( %a, @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv2i8( %a, %b, i32 -4) ret %res } @@ -448,17 +448,17 @@ define @splice_nxv2i8_offset_max( %a, @llvm.experimental.vector.splice.nxv2i8( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2i8( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4i8(, , i32) +declare @llvm.vector.splice.nxv4i8(, , i32) define @splice_nxv4i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv4i8( %a, %b, i32 0) ret %res } @@ -473,7 +473,7 @@ define @splice_nxv4i8_offset_negone( %a, @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4i8( %a, %b, i32 -1) ret %res } @@ -488,7 +488,7 @@ define @splice_nxv4i8_offset_min( %a, @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv4i8( %a, %b, i32 -8) ret %res } @@ -503,17 +503,17 @@ define @splice_nxv4i8_offset_max( %a, @llvm.experimental.vector.splice.nxv4i8( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4i8( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8i8(, , i32) +declare @llvm.vector.splice.nxv8i8(, , i32) define @splice_nxv8i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv8i8( %a, %b, i32 0) ret %res } @@ -527,7 +527,7 @@ define @splice_nxv8i8_offset_negone( %a, @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8i8( %a, %b, i32 -1) ret %res } @@ -541,7 +541,7 @@ define @splice_nxv8i8_offset_min( %a, @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv8i8( %a, %b, i32 -16) ret %res } @@ -555,17 +555,17 @@ define @splice_nxv8i8_offset_max( %a, @llvm.experimental.vector.splice.nxv8i8( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8i8( %a, %b, i32 15) ret %res } -declare @llvm.experimental.vector.splice.nxv16i8(, , i32) +declare @llvm.vector.splice.nxv16i8(, , i32) define @splice_nxv16i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 0) ret %res } @@ -580,7 +580,7 @@ define @splice_nxv16i8_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e8, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -1) ret %res } @@ -596,7 +596,7 @@ define @splice_nxv16i8_offset_min( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 -32) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 -32) ret %res } @@ -611,17 +611,17 @@ define @splice_nxv16i8_offset_max( %a, @llvm.experimental.vector.splice.nxv16i8( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv16i8( %a, %b, i32 31) ret %res } -declare @llvm.experimental.vector.splice.nxv32i8(, , i32) +declare @llvm.vector.splice.nxv32i8(, , i32) define @splice_nxv32i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv32i8( %a, %b, i32 0) ret %res } @@ -636,7 +636,7 @@ define @splice_nxv32i8_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e8, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv32i8( %a, %b, i32 -1) ret %res } @@ -652,7 +652,7 @@ define @splice_nxv32i8_offset_min( %a, @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 -64) + %res = call @llvm.vector.splice.nxv32i8( %a, %b, i32 -64) ret %res } @@ -668,17 +668,17 @@ define @splice_nxv32i8_offset_max( %a, @llvm.experimental.vector.splice.nxv32i8( %a, %b, i32 63) + %res = call @llvm.vector.splice.nxv32i8( %a, %b, i32 63) ret %res } -declare @llvm.experimental.vector.splice.nxv64i8(, , i32) +declare @llvm.vector.splice.nxv64i8(, , i32) define @splice_nxv64i8_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv64i8_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv64i8( %a, %b, i32 0) ret %res } @@ -693,7 +693,7 @@ define @splice_nxv64i8_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e8, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv64i8( %a, %b, i32 -1) ret %res } @@ -709,7 +709,7 @@ define @splice_nxv64i8_offset_min( %a, @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 -128) + %res = call @llvm.vector.splice.nxv64i8( %a, %b, i32 -128) ret %res } @@ -725,17 +725,17 @@ define @splice_nxv64i8_offset_max( %a, @llvm.experimental.vector.splice.nxv64i8( %a, %b, i32 127) + %res = call @llvm.vector.splice.nxv64i8( %a, %b, i32 127) ret %res } -declare @llvm.experimental.vector.splice.nxv1i16(, , i32) +declare @llvm.vector.splice.nxv1i16(, , i32) define @splice_nxv1i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv1i16( %a, %b, i32 0) ret %res } @@ -750,7 +750,7 @@ define @splice_nxv1i16_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1i16( %a, %b, i32 -1) ret %res } @@ -765,7 +765,7 @@ define @splice_nxv1i16_offset_min( %a, @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv1i16( %a, %b, i32 -2) ret %res } @@ -780,17 +780,17 @@ define @splice_nxv1i16_offset_max( %a, @llvm.experimental.vector.splice.nxv1i16( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1i16( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2i16(, , i32) +declare @llvm.vector.splice.nxv2i16(, , i32) define @splice_nxv2i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv2i16( %a, %b, i32 0) ret %res } @@ -805,7 +805,7 @@ define @splice_nxv2i16_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2i16( %a, %b, i32 -1) ret %res } @@ -820,7 +820,7 @@ define @splice_nxv2i16_offset_min( %a, @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv2i16( %a, %b, i32 -4) ret %res } @@ -835,17 +835,17 @@ define @splice_nxv2i16_offset_max( %a, @llvm.experimental.vector.splice.nxv2i16( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2i16( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4i16(, , i32) +declare @llvm.vector.splice.nxv4i16(, , i32) define @splice_nxv4i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv4i16( %a, %b, i32 0) ret %res } @@ -860,7 +860,7 @@ define @splice_nxv4i16_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4i16( %a, %b, i32 -1) ret %res } @@ -875,7 +875,7 @@ define @splice_nxv4i16_offset_min( %a, @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv4i16( %a, %b, i32 -8) ret %res } @@ -890,17 +890,17 @@ define @splice_nxv4i16_offset_max( %a, @llvm.experimental.vector.splice.nxv4i16( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4i16( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8i16(, , i32) +declare @llvm.vector.splice.nxv8i16(, , i32) define @splice_nxv8i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 0) ret %res } @@ -914,7 +914,7 @@ define @splice_nxv8i16_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 -1) ret %res } @@ -928,7 +928,7 @@ define @splice_nxv8i16_offset_min( %a, @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 -16) ret %res } @@ -942,17 +942,17 @@ define @splice_nxv8i16_offset_max( %a, @llvm.experimental.vector.splice.nxv8i16( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8i16( %a, %b, i32 15) ret %res } -declare @llvm.experimental.vector.splice.nxv16i16(, , i32) +declare @llvm.vector.splice.nxv16i16(, , i32) define @splice_nxv16i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv16i16( %a, %b, i32 0) ret %res } @@ -967,7 +967,7 @@ define @splice_nxv16i16_offset_negone( %a ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16i16( %a, %b, i32 -1) ret %res } @@ -983,7 +983,7 @@ define @splice_nxv16i16_offset_min( %a, < ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 -32) + %res = call @llvm.vector.splice.nxv16i16( %a, %b, i32 -32) ret %res } @@ -998,17 +998,17 @@ define @splice_nxv16i16_offset_max( %a, < ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i16( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv16i16( %a, %b, i32 31) ret %res } -declare @llvm.experimental.vector.splice.nxv32i16(, , i32) +declare @llvm.vector.splice.nxv32i16(, , i32) define @splice_nxv32i16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32i16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv32i16( %a, %b, i32 0) ret %res } @@ -1023,7 +1023,7 @@ define @splice_nxv32i16_offset_negone( %a ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv32i16( %a, %b, i32 -1) ret %res } @@ -1039,7 +1039,7 @@ define @splice_nxv32i16_offset_min( %a, < ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 -64) + %res = call @llvm.vector.splice.nxv32i16( %a, %b, i32 -64) ret %res } @@ -1055,17 +1055,17 @@ define @splice_nxv32i16_offset_max( %a, < ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32i16( %a, %b, i32 63) + %res = call @llvm.vector.splice.nxv32i16( %a, %b, i32 63) ret %res } -declare @llvm.experimental.vector.splice.nxv1i32(, , i32) +declare @llvm.vector.splice.nxv1i32(, , i32) define @splice_nxv1i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv1i32( %a, %b, i32 0) ret %res } @@ -1080,7 +1080,7 @@ define @splice_nxv1i32_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1i32( %a, %b, i32 -1) ret %res } @@ -1095,7 +1095,7 @@ define @splice_nxv1i32_offset_min( %a, @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv1i32( %a, %b, i32 -2) ret %res } @@ -1110,17 +1110,17 @@ define @splice_nxv1i32_offset_max( %a, @llvm.experimental.vector.splice.nxv1i32( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1i32( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2i32(, , i32) +declare @llvm.vector.splice.nxv2i32(, , i32) define @splice_nxv2i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv2i32( %a, %b, i32 0) ret %res } @@ -1135,7 +1135,7 @@ define @splice_nxv2i32_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2i32( %a, %b, i32 -1) ret %res } @@ -1150,7 +1150,7 @@ define @splice_nxv2i32_offset_min( %a, @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv2i32( %a, %b, i32 -4) ret %res } @@ -1165,17 +1165,17 @@ define @splice_nxv2i32_offset_max( %a, @llvm.experimental.vector.splice.nxv2i32( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2i32( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4i32(, , i32) +declare @llvm.vector.splice.nxv4i32(, , i32) define @splice_nxv4i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 0) ret %res } @@ -1190,7 +1190,7 @@ define @splice_nxv4i32_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 -1) ret %res } @@ -1205,7 +1205,7 @@ define @splice_nxv4i32_offset_min( %a, @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 -8) ret %res } @@ -1220,17 +1220,17 @@ define @splice_nxv4i32_offset_max( %a, @llvm.experimental.vector.splice.nxv4i32( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4i32( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8i32(, , i32) +declare @llvm.vector.splice.nxv8i32(, , i32) define @splice_nxv8i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv8i32( %a, %b, i32 0) ret %res } @@ -1244,7 +1244,7 @@ define @splice_nxv8i32_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8i32( %a, %b, i32 -1) ret %res } @@ -1258,7 +1258,7 @@ define @splice_nxv8i32_offset_min( %a, @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv8i32( %a, %b, i32 -16) ret %res } @@ -1272,17 +1272,17 @@ define @splice_nxv8i32_offset_max( %a, @llvm.experimental.vector.splice.nxv8i32( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8i32( %a, %b, i32 15) ret %res } -declare @llvm.experimental.vector.splice.nxv16i32(, , i32) +declare @llvm.vector.splice.nxv16i32(, , i32) define @splice_nxv16i32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16i32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv16i32( %a, %b, i32 0) ret %res } @@ -1297,7 +1297,7 @@ define @splice_nxv16i32_offset_negone( %a ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16i32( %a, %b, i32 -1) ret %res } @@ -1313,7 +1313,7 @@ define @splice_nxv16i32_offset_min( %a, < ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 -32) + %res = call @llvm.vector.splice.nxv16i32( %a, %b, i32 -32) ret %res } @@ -1328,17 +1328,17 @@ define @splice_nxv16i32_offset_max( %a, < ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16i32( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv16i32( %a, %b, i32 31) ret %res } -declare @llvm.experimental.vector.splice.nxv1i64(, , i32) +declare @llvm.vector.splice.nxv1i64(, , i32) define @splice_nxv1i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv1i64( %a, %b, i32 0) ret %res } @@ -1353,7 +1353,7 @@ define @splice_nxv1i64_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1i64( %a, %b, i32 -1) ret %res } @@ -1368,7 +1368,7 @@ define @splice_nxv1i64_offset_min( %a, @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv1i64( %a, %b, i32 -2) ret %res } @@ -1383,17 +1383,17 @@ define @splice_nxv1i64_offset_max( %a, @llvm.experimental.vector.splice.nxv1i64( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1i64( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2i64(, , i32) +declare @llvm.vector.splice.nxv2i64(, , i32) define @splice_nxv2i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 0) ret %res } @@ -1408,7 +1408,7 @@ define @splice_nxv2i64_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 -1) ret %res } @@ -1423,7 +1423,7 @@ define @splice_nxv2i64_offset_min( %a, @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 -4) ret %res } @@ -1438,17 +1438,17 @@ define @splice_nxv2i64_offset_max( %a, @llvm.experimental.vector.splice.nxv2i64( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2i64( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4i64(, , i32) +declare @llvm.vector.splice.nxv4i64(, , i32) define @splice_nxv4i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv4i64( %a, %b, i32 0) ret %res } @@ -1463,7 +1463,7 @@ define @splice_nxv4i64_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4i64( %a, %b, i32 -1) ret %res } @@ -1478,7 +1478,7 @@ define @splice_nxv4i64_offset_min( %a, @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv4i64( %a, %b, i32 -8) ret %res } @@ -1493,17 +1493,17 @@ define @splice_nxv4i64_offset_max( %a, @llvm.experimental.vector.splice.nxv4i64( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4i64( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8i64(, , i32) +declare @llvm.vector.splice.nxv8i64(, , i32) define @splice_nxv8i64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8i64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv8i64( %a, %b, i32 0) ret %res } @@ -1517,7 +1517,7 @@ define @splice_nxv8i64_offset_negone( %a, < ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8i64( %a, %b, i32 -1) ret %res } @@ -1531,7 +1531,7 @@ define @splice_nxv8i64_offset_min( %a, @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv8i64( %a, %b, i32 -16) ret %res } @@ -1545,17 +1545,17 @@ define @splice_nxv8i64_offset_max( %a, @llvm.experimental.vector.splice.nxv8i64( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8i64( %a, %b, i32 15) ret %res } -declare @llvm.experimental.vector.splice.nxv1f16(, , i32) +declare @llvm.vector.splice.nxv1f16(, , i32) define @splice_nxv1f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv1f16( %a, %b, i32 0) ret %res } @@ -1570,7 +1570,7 @@ define @splice_nxv1f16_offset_negone( %a, ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1f16( %a, %b, i32 -1) ret %res } @@ -1585,7 +1585,7 @@ define @splice_nxv1f16_offset_min( %a, @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv1f16( %a, %b, i32 -2) ret %res } @@ -1600,17 +1600,17 @@ define @splice_nxv1f16_offset_max( %a, @llvm.experimental.vector.splice.nxv1f16( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1f16( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2f16(, , i32) +declare @llvm.vector.splice.nxv2f16(, , i32) define @splice_nxv2f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 0) ret %res } @@ -1625,7 +1625,7 @@ define @splice_nxv2f16_offset_negone( %a, ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 -1) ret %res } @@ -1640,7 +1640,7 @@ define @splice_nxv2f16_offset_min( %a, @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 -4) ret %res } @@ -1655,17 +1655,17 @@ define @splice_nxv2f16_offset_max( %a, @llvm.experimental.vector.splice.nxv2f16( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2f16( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4f16(, , i32) +declare @llvm.vector.splice.nxv4f16(, , i32) define @splice_nxv4f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 0) ret %res } @@ -1680,7 +1680,7 @@ define @splice_nxv4f16_offset_negone( %a, ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 -1) ret %res } @@ -1695,7 +1695,7 @@ define @splice_nxv4f16_offset_min( %a, @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 -8) ret %res } @@ -1710,17 +1710,17 @@ define @splice_nxv4f16_offset_max( %a, @llvm.experimental.vector.splice.nxv4f16( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4f16( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8f16(, , i32) +declare @llvm.vector.splice.nxv8f16(, , i32) define @splice_nxv8f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 0) ret %res } @@ -1734,7 +1734,7 @@ define @splice_nxv8f16_offset_negone( %a, ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 -1) ret %res } @@ -1748,7 +1748,7 @@ define @splice_nxv8f16_offset_min( %a, @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 -16) ret %res } @@ -1762,17 +1762,17 @@ define @splice_nxv8f16_offset_max( %a, @llvm.experimental.vector.splice.nxv8f16( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8f16( %a, %b, i32 15) ret %res } -declare @llvm.experimental.vector.splice.nxv16f16(, , i32) +declare @llvm.vector.splice.nxv16f16(, , i32) define @splice_nxv16f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv16f16( %a, %b, i32 0) ret %res } @@ -1787,7 +1787,7 @@ define @splice_nxv16f16_offset_negone( ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16f16( %a, %b, i32 -1) ret %res } @@ -1803,7 +1803,7 @@ define @splice_nxv16f16_offset_min( %a, ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 -32) + %res = call @llvm.vector.splice.nxv16f16( %a, %b, i32 -32) ret %res } @@ -1818,17 +1818,17 @@ define @splice_nxv16f16_offset_max( %a, ; CHECK-NEXT: vsetvli a1, zero, e16, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16f16( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv16f16( %a, %b, i32 31) ret %res } -declare @llvm.experimental.vector.splice.nxv32f16(, , i32) +declare @llvm.vector.splice.nxv32f16(, , i32) define @splice_nxv32f16_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv32f16_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv32f16( %a, %b, i32 0) ret %res } @@ -1843,7 +1843,7 @@ define @splice_nxv32f16_offset_negone( ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv32f16( %a, %b, i32 -1) ret %res } @@ -1859,7 +1859,7 @@ define @splice_nxv32f16_offset_min( %a, ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 -64) + %res = call @llvm.vector.splice.nxv32f16( %a, %b, i32 -64) ret %res } @@ -1875,17 +1875,17 @@ define @splice_nxv32f16_offset_max( %a, ; CHECK-NEXT: vsetvli a1, zero, e16, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv32f16( %a, %b, i32 63) + %res = call @llvm.vector.splice.nxv32f16( %a, %b, i32 63) ret %res } -declare @llvm.experimental.vector.splice.nxv1f32(, , i32) +declare @llvm.vector.splice.nxv1f32(, , i32) define @splice_nxv1f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv1f32( %a, %b, i32 0) ret %res } @@ -1900,7 +1900,7 @@ define @splice_nxv1f32_offset_negone( % ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1f32( %a, %b, i32 -1) ret %res } @@ -1915,7 +1915,7 @@ define @splice_nxv1f32_offset_min( %a, ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv1f32( %a, %b, i32 -2) ret %res } @@ -1930,17 +1930,17 @@ define @splice_nxv1f32_offset_max( %a, ; CHECK-NEXT: vsetvli a1, zero, e32, mf2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f32( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1f32( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2f32(, , i32) +declare @llvm.vector.splice.nxv2f32(, , i32) define @splice_nxv2f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 0) ret %res } @@ -1955,7 +1955,7 @@ define @splice_nxv2f32_offset_negone( % ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 -1) ret %res } @@ -1970,7 +1970,7 @@ define @splice_nxv2f32_offset_min( %a, ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 4 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 -4) ret %res } @@ -1985,17 +1985,17 @@ define @splice_nxv2f32_offset_max( %a, ; CHECK-NEXT: vsetvli a1, zero, e32, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f32( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2f32( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4f32(, , i32) +declare @llvm.vector.splice.nxv4f32(, , i32) define @splice_nxv4f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 0) ret %res } @@ -2010,7 +2010,7 @@ define @splice_nxv4f32_offset_negone( % ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 -1) ret %res } @@ -2025,7 +2025,7 @@ define @splice_nxv4f32_offset_min( %a, ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 8 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 -8) ret %res } @@ -2040,17 +2040,17 @@ define @splice_nxv4f32_offset_max( %a, ; CHECK-NEXT: vsetvli a1, zero, e32, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f32( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4f32( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8f32(, , i32) +declare @llvm.vector.splice.nxv8f32(, , i32) define @splice_nxv8f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv8f32( %a, %b, i32 0) ret %res } @@ -2064,7 +2064,7 @@ define @splice_nxv8f32_offset_negone( % ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8f32( %a, %b, i32 -1) ret %res } @@ -2078,7 +2078,7 @@ define @splice_nxv8f32_offset_min( %a, ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv8f32( %a, %b, i32 -16) ret %res } @@ -2092,17 +2092,17 @@ define @splice_nxv8f32_offset_max( %a, ; CHECK-NEXT: vsetvli a1, zero, e32, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f32( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8f32( %a, %b, i32 15) ret %res } -declare @llvm.experimental.vector.splice.nxv16f32(, , i32) +declare @llvm.vector.splice.nxv16f32(, , i32) define @splice_nxv16f32_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv16f32_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv16f32( %a, %b, i32 0) ret %res } @@ -2117,7 +2117,7 @@ define @splice_nxv16f32_offset_negone( @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv16f32( %a, %b, i32 -1) ret %res } @@ -2133,7 +2133,7 @@ define @splice_nxv16f32_offset_min( % ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 -32) + %res = call @llvm.vector.splice.nxv16f32( %a, %b, i32 -32) ret %res } @@ -2148,17 +2148,17 @@ define @splice_nxv16f32_offset_max( % ; CHECK-NEXT: vsetvli a1, zero, e32, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv16f32( %a, %b, i32 31) + %res = call @llvm.vector.splice.nxv16f32( %a, %b, i32 31) ret %res } -declare @llvm.experimental.vector.splice.nxv1f64(, , i32) +declare @llvm.vector.splice.nxv1f64(, , i32) define @splice_nxv1f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv1f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv1f64( %a, %b, i32 0) ret %res } @@ -2173,7 +2173,7 @@ define @splice_nxv1f64_offset_negone( ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv1f64( %a, %b, i32 -1) ret %res } @@ -2188,7 +2188,7 @@ define @splice_nxv1f64_offset_min( %a ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vi v8, v9, 2 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 -2) + %res = call @llvm.vector.splice.nxv1f64( %a, %b, i32 -2) ret %res } @@ -2203,17 +2203,17 @@ define @splice_nxv1f64_offset_max( %a ; CHECK-NEXT: vsetvli a1, zero, e64, m1, ta, ma ; CHECK-NEXT: vslideup.vx v8, v9, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv1f64( %a, %b, i32 1) + %res = call @llvm.vector.splice.nxv1f64( %a, %b, i32 1) ret %res } -declare @llvm.experimental.vector.splice.nxv2f64(, , i32) +declare @llvm.vector.splice.nxv2f64(, , i32) define @splice_nxv2f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv2f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 0) ret %res } @@ -2228,7 +2228,7 @@ define @splice_nxv2f64_offset_negone( ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 -1) ret %res } @@ -2243,7 +2243,7 @@ define @splice_nxv2f64_offset_min( %a ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vi v8, v10, 4 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -4) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 -4) ret %res } @@ -2258,17 +2258,17 @@ define @splice_nxv2f64_offset_max( %a ; CHECK-NEXT: vsetvli a1, zero, e64, m2, ta, ma ; CHECK-NEXT: vslideup.vx v8, v10, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 3) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 3) ret %res } -declare @llvm.experimental.vector.splice.nxv4f64(, , i32) +declare @llvm.vector.splice.nxv4f64(, , i32) define @splice_nxv4f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv4f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv4f64( %a, %b, i32 0) ret %res } @@ -2283,7 +2283,7 @@ define @splice_nxv4f64_offset_negone( ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv4f64( %a, %b, i32 -1) ret %res } @@ -2298,7 +2298,7 @@ define @splice_nxv4f64_offset_min( %a ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vi v8, v12, 8 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 -8) + %res = call @llvm.vector.splice.nxv4f64( %a, %b, i32 -8) ret %res } @@ -2313,17 +2313,17 @@ define @splice_nxv4f64_offset_max( %a ; CHECK-NEXT: vsetvli a1, zero, e64, m4, ta, ma ; CHECK-NEXT: vslideup.vx v8, v12, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv4f64( %a, %b, i32 7) + %res = call @llvm.vector.splice.nxv4f64( %a, %b, i32 7) ret %res } -declare @llvm.experimental.vector.splice.nxv8f64(, , i32) +declare @llvm.vector.splice.nxv8f64(, , i32) define @splice_nxv8f64_offset_zero( %a, %b) #0 { ; CHECK-LABEL: splice_nxv8f64_offset_zero: ; CHECK: # %bb.0: ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 0) + %res = call @llvm.vector.splice.nxv8f64( %a, %b, i32 0) ret %res } @@ -2337,7 +2337,7 @@ define @splice_nxv8f64_offset_negone( ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 1 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 -1) + %res = call @llvm.vector.splice.nxv8f64( %a, %b, i32 -1) ret %res } @@ -2351,7 +2351,7 @@ define @splice_nxv8f64_offset_min( %a ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vi v8, v16, 16 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 -16) + %res = call @llvm.vector.splice.nxv8f64( %a, %b, i32 -16) ret %res } @@ -2365,7 +2365,7 @@ define @splice_nxv8f64_offset_max( %a ; CHECK-NEXT: vsetvli a1, zero, e64, m8, ta, ma ; CHECK-NEXT: vslideup.vx v8, v16, a0 ; CHECK-NEXT: ret - %res = call @llvm.experimental.vector.splice.nxv8f64( %a, %b, i32 15) + %res = call @llvm.vector.splice.nxv8f64( %a, %b, i32 15) ret %res } diff --git a/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll b/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll index f0917be88744..2a5e834f0ac7 100644 --- a/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll +++ b/llvm/test/CodeGen/X86/named-vector-shuffle-reverse.ll @@ -23,7 +23,7 @@ define <16 x i8> @reverse_v16i8(<16 x i8> %a) #0 { ; CHECK-NEXT: packuswb %xmm2, %xmm0 ; CHECK-NEXT: retq - %res = call <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8> %a) + %res = call <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8> %a) ret <16 x i8> %res } @@ -34,7 +34,7 @@ define <8 x i16> @reverse_v8i16(<8 x i16> %a) #0 { ; CHECK-NEXT: pshuflw {{.*#+}} xmm0 = xmm0[3,2,1,0,4,5,6,7] ; CHECK-NEXT: pshufhw {{.*#+}} xmm0 = xmm0[0,1,2,3,7,6,5,4] ; CHECK-NEXT: retq - %res = call <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16> %a) + %res = call <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16> %a) ret <8 x i16> %res } @@ -43,7 +43,7 @@ define <4 x i32> @reverse_v4i32(<4 x i32> %a) #0 { ; CHECK: # %bb.0: ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[3,2,1,0] ; CHECK-NEXT: retq - %res = call <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32> %a) + %res = call <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32> %a) ret <4 x i32> %res } @@ -52,7 +52,7 @@ define <2 x i64> @reverse_v2i64(<2 x i64> %a) #0 { ; CHECK: # %bb.0: ; CHECK-NEXT: pshufd {{.*#+}} xmm0 = xmm0[2,3,0,1] ; CHECK-NEXT: retq - %res = call <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64> %a) + %res = call <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64> %a) ret <2 x i64> %res } @@ -61,7 +61,7 @@ define <4 x float> @reverse_v4f32(<4 x float> %a) #0 { ; CHECK: # %bb.0: ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[3,2,1,0] ; CHECK-NEXT: retq - %res = call <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float> %a) + %res = call <4 x float> @llvm.vector.reverse.v4f32(<4 x float> %a) ret <4 x float> %res } @@ -70,7 +70,7 @@ define <2 x double> @reverse_v2f64(<2 x double> %a) #0 { ; CHECK: # %bb.0: ; CHECK-NEXT: shufps {{.*#+}} xmm0 = xmm0[2,3,0,1] ; CHECK-NEXT: retq - %res = call <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double> %a) + %res = call <2 x double> @llvm.vector.reverse.v2f64(<2 x double> %a) ret <2 x double> %res } @@ -83,7 +83,7 @@ define <2 x i8> @reverse_v2i8(<2 x i8> %a) #0 { ; CHECK-NEXT: psllw $8, %xmm0 ; CHECK-NEXT: por %xmm1, %xmm0 ; CHECK-NEXT: retq - %res = call <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8> %a) + %res = call <2 x i8> @llvm.vector.reverse.v2i8(<2 x i8> %a) ret <2 x i8> %res } @@ -95,7 +95,7 @@ define <8 x i32> @reverse_v8i32(<8 x i32> %a) #0 { ; CHECK-NEXT: pshufd {{.*#+}} xmm1 = xmm0[3,2,1,0] ; CHECK-NEXT: movdqa %xmm2, %xmm0 ; CHECK-NEXT: retq - %res = call <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32> %a) + %res = call <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32> %a) ret <8 x i32> %res } @@ -115,20 +115,20 @@ define <16 x float> @reverse_v16f32(<16 x float> %a) #0 { ; CHECK-NEXT: movaps %xmm5, %xmm3 ; CHECK-NEXT: retq - %res = call <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float> %a) + %res = call <16 x float> @llvm.vector.reverse.v16f32(<16 x float> %a) ret <16 x float> %res } -declare <2 x i8> @llvm.experimental.vector.reverse.v2i8(<2 x i8>) -declare <16 x i8> @llvm.experimental.vector.reverse.v16i8(<16 x i8>) -declare <8 x i16> @llvm.experimental.vector.reverse.v8i16(<8 x i16>) -declare <4 x i32> @llvm.experimental.vector.reverse.v4i32(<4 x i32>) -declare <8 x i32> @llvm.experimental.vector.reverse.v8i32(<8 x i32>) -declare <2 x i64> @llvm.experimental.vector.reverse.v2i64(<2 x i64>) -declare <8 x half> @llvm.experimental.vector.reverse.v8f16(<8 x half>) -declare <4 x float> @llvm.experimental.vector.reverse.v4f32(<4 x float>) -declare <16 x float> @llvm.experimental.vector.reverse.v16f32(<16 x float>) -declare <2 x double> @llvm.experimental.vector.reverse.v2f64(<2 x double>) +declare <2 x i8> @llvm.vector.reverse.v2i8(<2 x i8>) +declare <16 x i8> @llvm.vector.reverse.v16i8(<16 x i8>) +declare <8 x i16> @llvm.vector.reverse.v8i16(<8 x i16>) +declare <4 x i32> @llvm.vector.reverse.v4i32(<4 x i32>) +declare <8 x i32> @llvm.vector.reverse.v8i32(<8 x i32>) +declare <2 x i64> @llvm.vector.reverse.v2i64(<2 x i64>) +declare <8 x half> @llvm.vector.reverse.v8f16(<8 x half>) +declare <4 x float> @llvm.vector.reverse.v4f32(<4 x float>) +declare <16 x float> @llvm.vector.reverse.v16f32(<16 x float>) +declare <2 x double> @llvm.vector.reverse.v2f64(<2 x double>) attributes #0 = { nounwind } diff --git a/llvm/test/Transforms/InstCombine/vector-reverse.ll b/llvm/test/Transforms/InstCombine/vector-reverse.ll index 5e6672658f9a..a1a6ee949a13 100644 --- a/llvm/test/Transforms/InstCombine/vector-reverse.ll +++ b/llvm/test/Transforms/InstCombine/vector-reverse.ll @@ -8,11 +8,11 @@ define @binop_reverse( %a, %b) { ; CHECK-LABEL: @binop_reverse( ; CHECK-NEXT: [[ADD1:%.*]] = add nsw [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[ADD:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[ADD1]]) +; CHECK-NEXT: [[ADD:%.*]] = call @llvm.vector.reverse.nxv4i32( [[ADD1]]) ; CHECK-NEXT: ret [[ADD]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %add = add nsw %a.rev, %b.rev ret %add } @@ -20,14 +20,14 @@ define @binop_reverse( %a, @binop_reverse_1( %a, %b) { ; CHECK-LABEL: @binop_reverse_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: [[ADD1:%.*]] = add [[A]], [[B:%.*]] -; CHECK-NEXT: [[ADD:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[ADD1]]) +; CHECK-NEXT: [[ADD:%.*]] = call @llvm.vector.reverse.nxv4i32( [[ADD1]]) ; CHECK-NEXT: ret [[ADD]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) call void @use_nxv4i32( %a.rev) %add = add %a.rev, %b.rev ret %add @@ -36,14 +36,14 @@ define @binop_reverse_1( %a, @binop_reverse_2( %a, %b) { ; CHECK-LABEL: @binop_reverse_2( -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[ADD1:%.*]] = add [[A:%.*]], [[B]] -; CHECK-NEXT: [[ADD:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[ADD1]]) +; CHECK-NEXT: [[ADD:%.*]] = call @llvm.vector.reverse.nxv4i32( [[ADD1]]) ; CHECK-NEXT: ret [[ADD]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) call void @use_nxv4i32( %b.rev) %add = add %a.rev, %b.rev ret %add @@ -52,15 +52,15 @@ define @binop_reverse_2( %a, @binop_reverse_3( %a, %b) { ; CHECK-LABEL: @binop_reverse_3( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[ADD:%.*]] = add [[A_REV]], [[B_REV]] ; CHECK-NEXT: ret [[ADD]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) call void @use_nxv4i32( %a.rev) call void @use_nxv4i32( %b.rev) %add = add %a.rev, %b.rev @@ -71,10 +71,10 @@ define @binop_reverse_3( %a, @binop_reverse_4( %a) { ; CHECK-LABEL: @binop_reverse_4( ; CHECK-NEXT: [[MUL1:%.*]] = mul [[A:%.*]], [[A]] -; CHECK-NEXT: [[MUL:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[MUL1]]) +; CHECK-NEXT: [[MUL:%.*]] = call @llvm.vector.reverse.nxv4i32( [[MUL1]]) ; CHECK-NEXT: ret [[MUL]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %mul = mul %a.rev, %a.rev ret %mul } @@ -82,12 +82,12 @@ define @binop_reverse_4( %a) { ; %a.rev used as both operands along with a third use define @binop_reverse_5( %a) { ; CHECK-LABEL: @binop_reverse_5( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: [[MUL:%.*]] = mul [[A_REV]], [[A_REV]] ; CHECK-NEXT: ret [[MUL]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) call void @use_nxv4i32( %a.rev) %mul = mul %a.rev, %a.rev ret %mul @@ -98,10 +98,10 @@ define @binop_reverse_splat_RHS( %a, i32 %b ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: [[DIV1:%.*]] = udiv [[A:%.*]], [[B_SPLAT]] -; CHECK-NEXT: [[DIV:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[DIV1]]) +; CHECK-NEXT: [[DIV:%.*]] = call @llvm.vector.reverse.nxv4i32( [[DIV1]]) ; CHECK-NEXT: ret [[DIV]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer %div = udiv %a.rev, %b.splat @@ -111,14 +111,14 @@ define @binop_reverse_splat_RHS( %a, i32 %b ; %a.rev has multiple uses define @binop_reverse_splat_RHS_1( %a, i32 %b) { ; CHECK-LABEL: @binop_reverse_splat_RHS_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: [[DIV:%.*]] = udiv [[A_REV]], [[B_SPLAT]] ; CHECK-NEXT: ret [[DIV]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer call void @use_nxv4i32( %a.rev) @@ -131,10 +131,10 @@ define @binop_reverse_splat_LHS( %a, i32 %b ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: [[DIV1:%.*]] = udiv [[B_SPLAT]], [[A:%.*]] -; CHECK-NEXT: [[DIV:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[DIV1]]) +; CHECK-NEXT: [[DIV:%.*]] = call @llvm.vector.reverse.nxv4i32( [[DIV1]]) ; CHECK-NEXT: ret [[DIV]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer %div = udiv %b.splat, %a.rev @@ -144,14 +144,14 @@ define @binop_reverse_splat_LHS( %a, i32 %b ; %a.rev has multiple uses define @binop_reverse_splat_LHS_1( %a, i32 %b) { ; CHECK-LABEL: @binop_reverse_splat_LHS_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: [[DIV:%.*]] = udiv [[B_SPLAT]], [[A_REV]] ; CHECK-NEXT: ret [[DIV]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer call void @use_nxv4i32( %a.rev) @@ -161,11 +161,11 @@ define @binop_reverse_splat_LHS_1( %a, i32 define @unop_reverse( %a) { ; CHECK-LABEL: @unop_reverse( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4f32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4f32( [[A:%.*]]) ; CHECK-NEXT: [[NEG:%.*]] = fneg fast [[A_REV]] ; CHECK-NEXT: ret [[NEG]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4f32( %a) %neg = fneg fast %a.rev ret %neg } @@ -173,12 +173,12 @@ define @unop_reverse( %a) { ; %a.rev has multiple uses define @unop_reverse_1( %a) { ; CHECK-LABEL: @unop_reverse_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4f32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4f32( [[A:%.*]]) ; CHECK-NEXT: call void @use_nxv4f32( [[A_REV]]) ; CHECK-NEXT: [[NEG:%.*]] = fneg fast [[A_REV]] ; CHECK-NEXT: ret [[NEG]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4f32( %a) call void @use_nxv4f32( %a.rev) %neg = fneg fast %a.rev ret %neg @@ -187,11 +187,11 @@ define @unop_reverse_1( %a) { define @icmp_reverse( %a, %b) { ; CHECK-LABEL: @icmp_reverse( ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq [[A:%.*]], [[B:%.*]] -; CHECK-NEXT: [[CMP:%.*]] = call @llvm.experimental.vector.reverse.nxv4i1( [[CMP1]]) +; CHECK-NEXT: [[CMP:%.*]] = call @llvm.vector.reverse.nxv4i1( [[CMP1]]) ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %cmp = icmp eq %a.rev, %b.rev ret %cmp } @@ -199,14 +199,14 @@ define @icmp_reverse( %a, ; %a.rev has multiple uses define @icmp_reverse_1( %a, %b) { ; CHECK-LABEL: @icmp_reverse_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq [[A]], [[B:%.*]] -; CHECK-NEXT: [[CMP:%.*]] = call @llvm.experimental.vector.reverse.nxv4i1( [[CMP1]]) +; CHECK-NEXT: [[CMP:%.*]] = call @llvm.vector.reverse.nxv4i1( [[CMP1]]) ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) call void @use_nxv4i32( %a.rev) %cmp = icmp eq %a.rev, %b.rev ret %cmp @@ -215,14 +215,14 @@ define @icmp_reverse_1( %a, @icmp_reverse_2( %a, %b) { ; CHECK-LABEL: @icmp_reverse_2( -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[CMP1:%.*]] = icmp eq [[A:%.*]], [[B]] -; CHECK-NEXT: [[CMP:%.*]] = call @llvm.experimental.vector.reverse.nxv4i1( [[CMP1]]) +; CHECK-NEXT: [[CMP:%.*]] = call @llvm.vector.reverse.nxv4i1( [[CMP1]]) ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) call void @use_nxv4i32( %b.rev) %cmp = icmp eq %a.rev, %b.rev ret %cmp @@ -231,15 +231,15 @@ define @icmp_reverse_2( %a, @icmp_reverse_3( %a, %b) { ; CHECK-LABEL: @icmp_reverse_3( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp eq [[A_REV]], [[B_REV]] ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) call void @use_nxv4i32( %a.rev) call void @use_nxv4i32( %b.rev) %cmp = icmp eq %a.rev, %b.rev @@ -251,10 +251,10 @@ define @icmp_reverse_splat_RHS( %a, i32 %b) ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: [[CMP1:%.*]] = icmp slt [[B_SPLAT]], [[A:%.*]] -; CHECK-NEXT: [[CMP:%.*]] = call @llvm.experimental.vector.reverse.nxv4i1( [[CMP1]]) +; CHECK-NEXT: [[CMP:%.*]] = call @llvm.vector.reverse.nxv4i1( [[CMP1]]) ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer %cmp = icmp sgt %a.rev, %b.splat @@ -264,14 +264,14 @@ define @icmp_reverse_splat_RHS( %a, i32 %b) ; %a.rev has multiple uses define @icmp_reverse_splat_RHS_1( %a, i32 %b) { ; CHECK-LABEL: @icmp_reverse_splat_RHS_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp sgt [[A_REV]], [[B_SPLAT]] ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer call void @use_nxv4i32( %a.rev) @@ -284,10 +284,10 @@ define @icmp_reverse_splat_LHS( %a, i32 %b) ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: [[CMP1:%.*]] = icmp ult [[B_SPLAT]], [[A:%.*]] -; CHECK-NEXT: [[CMP:%.*]] = call @llvm.experimental.vector.reverse.nxv4i1( [[CMP1]]) +; CHECK-NEXT: [[CMP:%.*]] = call @llvm.vector.reverse.nxv4i1( [[CMP1]]) ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer %cmp = icmp ult %b.splat, %a.rev @@ -297,14 +297,14 @@ define @icmp_reverse_splat_LHS( %a, i32 %b) ; %a.rev has multiple uses define @icmp_reverse_splat_LHS_1( %a, i32 %b) { ; CHECK-LABEL: @icmp_reverse_splat_LHS_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[A:%.*]]) ; CHECK-NEXT: [[B_INSERT:%.*]] = insertelement poison, i32 [[B:%.*]], i64 0 ; CHECK-NEXT: [[B_SPLAT:%.*]] = shufflevector [[B_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i32( [[A_REV]]) ; CHECK-NEXT: [[CMP:%.*]] = icmp ult [[B_SPLAT]], [[A_REV]] ; CHECK-NEXT: ret [[CMP]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4i32( %a) %b.insert = insertelement poison, i32 %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer call void @use_nxv4i32( %a.rev) @@ -315,12 +315,12 @@ define @icmp_reverse_splat_LHS_1( %a, i32 %b define @select_reverse( %a, %b, %c) { ; CHECK-LABEL: @select_reverse( ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[B:%.*]], [[C:%.*]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) %select = select %a.rev, %b.rev, %c.rev ret %select } @@ -328,15 +328,15 @@ define @select_reverse( %a, @select_reverse_1( %a, %b, %c) { ; CHECK-LABEL: @select_reverse_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A]], [[B:%.*]], [[C:%.*]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) call void @use_nxv4i1( %a.rev) %select = select %a.rev, %b.rev, %c.rev ret %select @@ -345,15 +345,15 @@ define @select_reverse_1( %a, @select_reverse_2( %a, %b, %c) { ; CHECK-LABEL: @select_reverse_2( -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[B]], [[C:%.*]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) call void @use_nxv4i32( %b.rev) %select = select %a.rev, %b.rev, %c.rev ret %select @@ -362,15 +362,15 @@ define @select_reverse_2( %a, @select_reverse_3( %a, %b, %c) { ; CHECK-LABEL: @select_reverse_3( -; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[C:%.*]]) +; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[C:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[C_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[B:%.*]], [[C]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) call void @use_nxv4i32( %c.rev) %select = select %a.rev, %b.rev, %c.rev ret %select @@ -379,17 +379,17 @@ define @select_reverse_3( %a, @select_reverse_4( %a, %b, %c) { ; CHECK-LABEL: @select_reverse_4( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A]], [[B]], [[C:%.*]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) call void @use_nxv4i1( %a.rev) call void @use_nxv4i32( %b.rev) %select = select %a.rev, %b.rev, %c.rev @@ -399,17 +399,17 @@ define @select_reverse_4( %a, @select_reverse_5( %a, %b, %c) { ; CHECK-LABEL: @select_reverse_5( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) -; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[C:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[C:%.*]]) ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) ; CHECK-NEXT: call void @use_nxv4i32( [[C_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A]], [[B:%.*]], [[C]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) call void @use_nxv4i1( %a.rev) call void @use_nxv4i32( %c.rev) %select = select %a.rev, %b.rev, %c.rev @@ -419,17 +419,17 @@ define @select_reverse_5( %a, @select_reverse_6( %a, %b, %c) { ; CHECK-LABEL: @select_reverse_6( -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) -; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[C:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[C:%.*]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: call void @use_nxv4i32( [[C_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[B]], [[C]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) call void @use_nxv4i32( %b.rev) call void @use_nxv4i32( %c.rev) %select = select %a.rev, %b.rev, %c.rev @@ -439,18 +439,18 @@ define @select_reverse_6( %a, @select_reverse_7( %a, %b, %c) { ; CHECK-LABEL: @select_reverse_7( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) -; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[C:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[C_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[C:%.*]]) ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: call void @use_nxv4i32( [[C_REV]]) ; CHECK-NEXT: [[SELECT:%.*]] = select [[A_REV]], [[B_REV]], [[C_REV]] ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4i32( %c) call void @use_nxv4i1( %a.rev) call void @use_nxv4i32( %b.rev) call void @use_nxv4i32( %c.rev) @@ -463,11 +463,11 @@ define @select_reverse_splat_false( %a, poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[B:%.*]], [[C_SPLAT]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer %select = select %a.rev, %b.rev, %c.splat @@ -477,16 +477,16 @@ define @select_reverse_splat_false( %a, @select_reverse_splat_false_1( %a, %b, i32 %c) { ; CHECK-LABEL: @select_reverse_splat_false_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) ; CHECK-NEXT: [[C_INSERT:%.*]] = insertelement poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A]], [[B:%.*]], [[C_SPLAT]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer call void @use_nxv4i1( %a.rev) @@ -497,16 +497,16 @@ define @select_reverse_splat_false_1( %a, @select_reverse_splat_false_2( %a, %b, i32 %c) { ; CHECK-LABEL: @select_reverse_splat_false_2( -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: [[C_INSERT:%.*]] = insertelement poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[B]], [[C_SPLAT]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer call void @use_nxv4i32( %b.rev) @@ -517,8 +517,8 @@ define @select_reverse_splat_false_2( %a, @select_reverse_splat_false_3( %a, %b, i32 %c) { ; CHECK-LABEL: @select_reverse_splat_false_3( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: [[C_INSERT:%.*]] = insertelement poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) @@ -526,8 +526,8 @@ define @select_reverse_splat_false_3( %a, [[A_REV]], [[B_REV]], [[C_SPLAT]] ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer call void @use_nxv4i1( %a.rev) @@ -541,11 +541,11 @@ define @select_reverse_splat_true( %a, poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[C_SPLAT]], [[B:%.*]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer %select = select %a.rev, %c.splat, %b.rev @@ -555,16 +555,16 @@ define @select_reverse_splat_true( %a, @select_reverse_splat_true_1( %a, %b, i32 %c) { ; CHECK-LABEL: @select_reverse_splat_true_1( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) ; CHECK-NEXT: [[C_INSERT:%.*]] = insertelement poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A]], [[C_SPLAT]], [[B:%.*]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer call void @use_nxv4i1( %a.rev) @@ -575,16 +575,16 @@ define @select_reverse_splat_true_1( %a, @select_reverse_splat_true_2( %a, %b, i32 %c) { ; CHECK-LABEL: @select_reverse_splat_true_2( -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: [[C_INSERT:%.*]] = insertelement poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i32( [[B_REV]]) ; CHECK-NEXT: [[SELECT1:%.*]] = select [[A:%.*]], [[C_SPLAT]], [[B]] -; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[SELECT1]]) +; CHECK-NEXT: [[SELECT:%.*]] = call @llvm.vector.reverse.nxv4i32( [[SELECT1]]) ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer call void @use_nxv4i32( %b.rev) @@ -595,8 +595,8 @@ define @select_reverse_splat_true_2( %a, @select_reverse_splat_true_3( %a, %b, i32 %c) { ; CHECK-LABEL: @select_reverse_splat_true_3( -; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i1( [[A:%.*]]) -; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.experimental.vector.reverse.nxv4i32( [[B:%.*]]) +; CHECK-NEXT: [[A_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i1( [[A:%.*]]) +; CHECK-NEXT: [[B_REV:%.*]] = tail call @llvm.vector.reverse.nxv4i32( [[B:%.*]]) ; CHECK-NEXT: [[C_INSERT:%.*]] = insertelement poison, i32 [[C:%.*]], i64 0 ; CHECK-NEXT: [[C_SPLAT:%.*]] = shufflevector [[C_INSERT]], poison, zeroinitializer ; CHECK-NEXT: call void @use_nxv4i1( [[A_REV]]) @@ -604,8 +604,8 @@ define @select_reverse_splat_true_3( %a, [[A_REV]], [[C_SPLAT]], [[B_REV]] ; CHECK-NEXT: ret [[SELECT]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4i32( %b) %c.insert = insertelement poison, i32 %c, i32 0 %c.splat = shufflevector %c.insert, poison, zeroinitializer call void @use_nxv4i1( %a.rev) @@ -622,10 +622,10 @@ define @reverse_binop_reverse( %a, [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: ret [[ADD1]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4f32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4f32( %b) %add = fadd %a.rev, %b.rev - %add.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %add) + %add.rev = tail call @llvm.vector.reverse.nxv4f32( %add) ret %add.rev } @@ -636,11 +636,11 @@ define @reverse_binop_reverse_splat_RHS( [[A:%.*]], [[B_SPLAT]] ; CHECK-NEXT: ret [[DIV1]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4f32( %a) %b.insert = insertelement poison, float %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer %div = fdiv %a.rev, %b.splat - %div.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %div) + %div.rev = tail call @llvm.vector.reverse.nxv4f32( %div) ret %div.rev } @@ -651,11 +651,11 @@ define @reverse_binop_reverse_splat_LHS( [[B_SPLAT]], [[A:%.*]] ; CHECK-NEXT: ret [[DIV1]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4f32( %a) %b.insert = insertelement poison, float %b, i32 0 %b.splat = shufflevector %b.insert, poison, zeroinitializer %div = fdiv %b.splat, %a.rev - %div.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %div) + %div.rev = tail call @llvm.vector.reverse.nxv4f32( %div) ret %div.rev } @@ -664,10 +664,10 @@ define @reverse_fcmp_reverse( %a, [[A:%.*]], [[B:%.*]] ; CHECK-NEXT: ret [[CMP1]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %b) + %a.rev = tail call @llvm.vector.reverse.nxv4f32( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4f32( %b) %cmp = fcmp fast olt %a.rev, %b.rev - %cmp.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %cmp) + %cmp.rev = tail call @llvm.vector.reverse.nxv4i1( %cmp) ret %cmp.rev } @@ -676,11 +676,11 @@ define @reverse_select_reverse( %a, [[A:%.*]], [[B:%.*]], [[C:%.*]] ; CHECK-NEXT: ret [[SELECT1]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4i1( %a) - %b.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %b) - %c.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %c) + %a.rev = tail call @llvm.vector.reverse.nxv4i1( %a) + %b.rev = tail call @llvm.vector.reverse.nxv4f32( %b) + %c.rev = tail call @llvm.vector.reverse.nxv4f32( %c) %select = select fast %a.rev, %b.rev, %c.rev - %select.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %select) + %select.rev = tail call @llvm.vector.reverse.nxv4f32( %select) ret %select.rev } @@ -689,9 +689,9 @@ define @reverse_unop_reverse( %a) { ; CHECK-NEXT: [[NEG1:%.*]] = fneg [[A:%.*]] ; CHECK-NEXT: ret [[NEG1]] ; - %a.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %a) + %a.rev = tail call @llvm.vector.reverse.nxv4f32( %a) %neg = fneg %a.rev - %neg.rev = tail call @llvm.experimental.vector.reverse.nxv4f32( %neg) + %neg.rev = tail call @llvm.vector.reverse.nxv4f32( %neg) ret %neg.rev } @@ -700,6 +700,6 @@ declare void @use_nxv4i1() declare void @use_nxv4i32() declare void @use_nxv4f32() -declare @llvm.experimental.vector.reverse.nxv4i1() -declare @llvm.experimental.vector.reverse.nxv4i32() -declare @llvm.experimental.vector.reverse.nxv4f32() +declare @llvm.vector.reverse.nxv4i1() +declare @llvm.vector.reverse.nxv4i32() +declare @llvm.vector.reverse.nxv4f32() diff --git a/llvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll b/llvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll index a26f0a9d87f8..25e99ff0e715 100644 --- a/llvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll +++ b/llvm/test/Transforms/InstSimplify/named-vector-shuffle-reverse.ll @@ -6,8 +6,8 @@ define @shuffle_b2b_reverse( %a) { ; CHECK-LABEL: @shuffle_b2b_reverse( ; CHECK-NEXT: ret [[A:%.*]] ; - %rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %a) - %rev.rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %rev) + %rev = tail call @llvm.vector.reverse.nxv4i32( %a) + %rev.rev = tail call @llvm.vector.reverse.nxv4i32( %rev) ret %rev.rev } @@ -20,8 +20,8 @@ define @splat_reverse(i32 %a) { ; %splat_insert = insertelement poison, i32 %a, i32 0 %splat = shufflevector %splat_insert, poison, zeroinitializer - %rev = tail call @llvm.experimental.vector.reverse.nxv4i32( %splat) + %rev = tail call @llvm.vector.reverse.nxv4i32( %splat) ret %rev } -declare @llvm.experimental.vector.reverse.nxv4i32() +declare @llvm.vector.reverse.nxv4i32() diff --git a/llvm/test/Transforms/InstSimplify/select.ll b/llvm/test/Transforms/InstSimplify/select.ll index 40c1460e3ebc..4eb6491eec5a 100644 --- a/llvm/test/Transforms/InstSimplify/select.ll +++ b/llvm/test/Transforms/InstSimplify/select.ll @@ -1105,19 +1105,19 @@ define <2 x i32> @select_ctpop_zero_vec(<2 x i32> %x) { define <2 x i32> @select_vector_reverse(<2 x i32> %x) { ; CHECK-LABEL: @select_vector_reverse( ; CHECK-NEXT: [[CMP:%.*]] = icmp eq <2 x i32> [[X:%.*]], zeroinitializer -; CHECK-NEXT: [[REV:%.*]] = call <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32> [[X]]) +; CHECK-NEXT: [[REV:%.*]] = call <2 x i32> @llvm.vector.reverse.v2i32(<2 x i32> [[X]]) ; CHECK-NEXT: [[SEL:%.*]] = select <2 x i1> [[CMP]], <2 x i32> zeroinitializer, <2 x i32> [[REV]] ; CHECK-NEXT: ret <2 x i32> [[SEL]] ; %cmp = icmp eq <2 x i32> %x, zeroinitializer - %rev = call <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32> %x) + %rev = call <2 x i32> @llvm.vector.reverse.v2i32(<2 x i32> %x) %sel = select <2 x i1> %cmp, <2 x i32> zeroinitializer, <2 x i32> %rev ret <2 x i32> %sel } declare i32 @llvm.ctpop.i32(i32) declare <2 x i32> @llvm.ctpop.v2i32(<2 x i32>) -declare <2 x i32> @llvm.experimental.vector.reverse.v2i32(<2 x i32>) +declare <2 x i32> @llvm.vector.reverse.v2i32(<2 x i32>) define <2 x i32> @vec_select_no_equivalence(<2 x i32> %x, <2 x i32> %y) { ; CHECK-LABEL: @vec_select_no_equivalence( diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll index 224a0693bf21..54348d1e2a48 100644 --- a/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll +++ b/llvm/test/Transforms/InterleavedAccess/AArch64/fixed-deinterleave-intrinsics.ll @@ -15,11 +15,11 @@ define { <16 x i8>, <16 x i8> } @deinterleave_i8_factor2(ptr %ptr) { ; SVE-FIXED-LABEL: define { <16 x i8>, <16 x i8> } @deinterleave_i8_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0:[0-9]+]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <32 x i8>, ptr [[PTR]], align 1 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <16 x i8>, <16 x i8> } [[DEINTERLEAVE]] ; %load = load <32 x i8>, ptr %ptr, align 1 - %deinterleave = tail call { <16 x i8>, <16 x i8> } @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8> %load) + %deinterleave = tail call { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8> %load) ret { <16 x i8>, <16 x i8> } %deinterleave } @@ -32,11 +32,11 @@ define { <8 x i16>, <8 x i16> } @deinterleave_i16_factor2(ptr %ptr) { ; SVE-FIXED-LABEL: define { <8 x i16>, <8 x i16> } @deinterleave_i16_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <16 x i16>, ptr [[PTR]], align 2 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <8 x i16>, <8 x i16> } @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <8 x i16>, <8 x i16> } [[DEINTERLEAVE]] ; %load = load <16 x i16>, ptr %ptr, align 2 - %deinterleave = tail call { <8 x i16>, <8 x i16> } @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16> %load) + %deinterleave = tail call { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16> %load) ret { <8 x i16>, <8 x i16> } %deinterleave } @@ -49,11 +49,11 @@ define { <4 x i32>, <4 x i32> } @deinterleave_8xi32_factor2(ptr %ptr) { ; SVE-FIXED-LABEL: define { <4 x i32>, <4 x i32> } @deinterleave_8xi32_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <8 x i32>, ptr [[PTR]], align 4 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <4 x i32>, <4 x i32> } @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <4 x i32>, <4 x i32> } [[DEINTERLEAVE]] ; %load = load <8 x i32>, ptr %ptr, align 4 - %deinterleave = tail call { <4 x i32>, <4 x i32> } @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32> %load) + %deinterleave = tail call { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32> %load) ret { <4 x i32>, <4 x i32> } %deinterleave } @@ -66,11 +66,11 @@ define { <2 x i64>, <2 x i64> } @deinterleave_i64_factor2(ptr %ptr) { ; SVE-FIXED-LABEL: define { <2 x i64>, <2 x i64> } @deinterleave_i64_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <4 x i64>, ptr [[PTR]], align 8 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <2 x i64>, <2 x i64> } @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <2 x i64>, <2 x i64> } [[DEINTERLEAVE]] ; %load = load <4 x i64>, ptr %ptr, align 8 - %deinterleave = tail call { <2 x i64>, <2 x i64> } @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64> %load) + %deinterleave = tail call { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64> %load) ret { <2 x i64>, <2 x i64> } %deinterleave } @@ -83,11 +83,11 @@ define { <4 x float>, <4 x float> } @deinterleave_float_factor2(ptr %ptr) { ; SVE-FIXED-LABEL: define { <4 x float>, <4 x float> } @deinterleave_float_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <8 x float>, ptr [[PTR]], align 4 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <4 x float>, <4 x float> } @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <4 x float>, <4 x float> } [[DEINTERLEAVE]] ; %load = load <8 x float>, ptr %ptr, align 4 - %deinterleave = tail call { <4 x float>, <4 x float> } @llvm.experimental.vector.deinterleave2.v8f32(<8 x float> %load) + %deinterleave = tail call { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float> %load) ret { <4 x float>, <4 x float> } %deinterleave } @@ -100,11 +100,11 @@ define { <2 x double>, <2 x double> } @deinterleave_double_factor2(ptr %ptr) { ; SVE-FIXED-LABEL: define { <2 x double>, <2 x double> } @deinterleave_double_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <4 x double>, ptr [[PTR]], align 8 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <2 x double>, <2 x double> } @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <2 x double>, <2 x double> } [[DEINTERLEAVE]] ; %load = load <4 x double>, ptr %ptr, align 8 - %deinterleave = tail call { <2 x double>, <2 x double> } @llvm.experimental.vector.deinterleave2.v4f64(<4 x double> %load) + %deinterleave = tail call { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double> %load) ret { <2 x double>, <2 x double> } %deinterleave } @@ -117,11 +117,11 @@ define { <2 x ptr>, <2 x ptr> } @deinterleave_ptr_factor2(ptr %ptr) { ; SVE-FIXED-LABEL: define { <2 x ptr>, <2 x ptr> } @deinterleave_ptr_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <4 x ptr>, ptr [[PTR]], align 8 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <2 x ptr>, <2 x ptr> } @llvm.experimental.vector.deinterleave2.v4p0(<4 x ptr> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <2 x ptr>, <2 x ptr> } @llvm.vector.deinterleave2.v4p0(<4 x ptr> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <2 x ptr>, <2 x ptr> } [[DEINTERLEAVE]] ; %load = load <4 x ptr>, ptr %ptr, align 8 - %deinterleave = tail call { <2 x ptr>, <2 x ptr> } @llvm.experimental.vector.deinterleave2.v4p0(<4 x ptr> %load) + %deinterleave = tail call { <2 x ptr>, <2 x ptr> } @llvm.vector.deinterleave2.v4p0(<4 x ptr> %load) ret { <2 x ptr>, <2 x ptr> } %deinterleave } @@ -133,11 +133,11 @@ define void @interleave_i8_factor2(ptr %ptr, <16 x i8> %l, <16 x i8> %r) { ; ; SVE-FIXED-LABEL: define void @interleave_i8_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <16 x i8> [[L:%.*]], <16 x i8> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <32 x i8> @llvm.experimental.vector.interleave2.v32i8(<16 x i8> [[L]], <16 x i8> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> [[L]], <16 x i8> [[R]]) ; SVE-FIXED-NEXT: store <32 x i8> [[INTERLEAVE]], ptr [[PTR]], align 1 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <32 x i8> @llvm.experimental.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r) + %interleave = tail call <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8> %l, <16 x i8> %r) store <32 x i8> %interleave, ptr %ptr, align 1 ret void } @@ -150,11 +150,11 @@ define void @interleave_i16_factor2(ptr %ptr, <8 x i16> %l, <8 x i16> %r) { ; ; SVE-FIXED-LABEL: define void @interleave_i16_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <8 x i16> [[L:%.*]], <8 x i16> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> [[L]], <8 x i16> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> [[L]], <8 x i16> [[R]]) ; SVE-FIXED-NEXT: store <16 x i16> [[INTERLEAVE]], ptr [[PTR]], align 2 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r) + %interleave = tail call <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16> %l, <8 x i16> %r) store <16 x i16> %interleave, ptr %ptr, align 2 ret void } @@ -167,11 +167,11 @@ define void @interleave_i32_factor2(ptr %ptr, <4 x i32> %l, <4 x i32> %r) { ; ; SVE-FIXED-LABEL: define void @interleave_i32_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <4 x i32> [[L:%.*]], <4 x i32> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> [[L]], <4 x i32> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> [[L]], <4 x i32> [[R]]) ; SVE-FIXED-NEXT: store <8 x i32> [[INTERLEAVE]], ptr [[PTR]], align 4 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r) + %interleave = tail call <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32> %l, <4 x i32> %r) store <8 x i32> %interleave, ptr %ptr, align 4 ret void } @@ -184,11 +184,11 @@ define void @interleave_i64_factor2(ptr %ptr, <2 x i64> %l, <2 x i64> %r) { ; ; SVE-FIXED-LABEL: define void @interleave_i64_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <2 x i64> [[L:%.*]], <2 x i64> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> [[L]], <2 x i64> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> [[L]], <2 x i64> [[R]]) ; SVE-FIXED-NEXT: store <4 x i64> [[INTERLEAVE]], ptr [[PTR]], align 8 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r) + %interleave = tail call <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64> %l, <2 x i64> %r) store <4 x i64> %interleave, ptr %ptr, align 8 ret void } @@ -201,11 +201,11 @@ define void @interleave_float_factor2(ptr %ptr, <4 x float> %l, <4 x float> %r) ; ; SVE-FIXED-LABEL: define void @interleave_float_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <4 x float> [[L:%.*]], <4 x float> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> [[L]], <4 x float> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> [[L]], <4 x float> [[R]]) ; SVE-FIXED-NEXT: store <8 x float> [[INTERLEAVE]], ptr [[PTR]], align 4 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r) + %interleave = tail call <8 x float> @llvm.vector.interleave2.v8f32(<4 x float> %l, <4 x float> %r) store <8 x float> %interleave, ptr %ptr, align 4 ret void } @@ -218,11 +218,11 @@ define void @interleave_double_factor2(ptr %ptr, <2 x double> %l, <2 x double> % ; ; SVE-FIXED-LABEL: define void @interleave_double_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <2 x double> [[L:%.*]], <2 x double> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> [[L]], <2 x double> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> [[L]], <2 x double> [[R]]) ; SVE-FIXED-NEXT: store <4 x double> [[INTERLEAVE]], ptr [[PTR]], align 4 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r) + %interleave = tail call <4 x double> @llvm.vector.interleave2.v4f64(<2 x double> %l, <2 x double> %r) store <4 x double> %interleave, ptr %ptr, align 4 ret void } @@ -235,11 +235,11 @@ define void @interleave_ptr_factor2(ptr %ptr, <2 x ptr> %l, <2 x ptr> %r) { ; ; SVE-FIXED-LABEL: define void @interleave_ptr_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <2 x ptr> [[L:%.*]], <2 x ptr> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <4 x ptr> @llvm.experimental.vector.interleave2.v4p0(<2 x ptr> [[L]], <2 x ptr> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> [[L]], <2 x ptr> [[R]]) ; SVE-FIXED-NEXT: store <4 x ptr> [[INTERLEAVE]], ptr [[PTR]], align 4 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <4 x ptr> @llvm.experimental.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r) + %interleave = tail call <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr> %l, <2 x ptr> %r) store <4 x ptr> %interleave, ptr %ptr, align 4 ret void } @@ -266,11 +266,11 @@ define { <16 x i16>, <16 x i16> } @deinterleave_wide_i16_factor2(ptr %ptr) #0 { ; SVE-FIXED-LABEL: define { <16 x i16>, <16 x i16> } @deinterleave_wide_i16_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]]) #[[ATTR0]] { ; SVE-FIXED-NEXT: [[LOAD:%.*]] = load <32 x i16>, ptr [[PTR]], align 2 -; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <16 x i16>, <16 x i16> } @llvm.experimental.vector.deinterleave2.v32i16(<32 x i16> [[LOAD]]) +; SVE-FIXED-NEXT: [[DEINTERLEAVE:%.*]] = tail call { <16 x i16>, <16 x i16> } @llvm.vector.deinterleave2.v32i16(<32 x i16> [[LOAD]]) ; SVE-FIXED-NEXT: ret { <16 x i16>, <16 x i16> } [[DEINTERLEAVE]] ; %load = load <32 x i16>, ptr %ptr, align 2 - %deinterleave = tail call { <16 x i16>, <16 x i16> } @llvm.experimental.vector.deinterleave2.v32i16(<32 x i16> %load) + %deinterleave = tail call { <16 x i16>, <16 x i16> } @llvm.vector.deinterleave2.v32i16(<32 x i16> %load) ret { <16 x i16>, <16 x i16> } %deinterleave } @@ -297,29 +297,29 @@ define void @interleave_wide_ptr_factor2(ptr %ptr, <8 x ptr> %l, <8 x ptr> %r) { ; ; SVE-FIXED-LABEL: define void @interleave_wide_ptr_factor2 ; SVE-FIXED-SAME: (ptr [[PTR:%.*]], <8 x ptr> [[L:%.*]], <8 x ptr> [[R:%.*]]) #[[ATTR0]] { -; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <16 x ptr> @llvm.experimental.vector.interleave2.v16p0(<8 x ptr> [[L]], <8 x ptr> [[R]]) +; SVE-FIXED-NEXT: [[INTERLEAVE:%.*]] = tail call <16 x ptr> @llvm.vector.interleave2.v16p0(<8 x ptr> [[L]], <8 x ptr> [[R]]) ; SVE-FIXED-NEXT: store <16 x ptr> [[INTERLEAVE]], ptr [[PTR]], align 4 ; SVE-FIXED-NEXT: ret void ; - %interleave = tail call <16 x ptr> @llvm.experimental.vector.interleave2.v16p0(<8 x ptr> %l, <8 x ptr> %r) + %interleave = tail call <16 x ptr> @llvm.vector.interleave2.v16p0(<8 x ptr> %l, <8 x ptr> %r) store <16 x ptr> %interleave, ptr %ptr, align 4 ret void } -declare { <16 x i8>, <16 x i8> } @llvm.experimental.vector.deinterleave2.v32i8(<32 x i8>) -declare { <8 x i16>, <8 x i16> } @llvm.experimental.vector.deinterleave2.v16i16(<16 x i16>) -declare { <4 x i32>, <4 x i32> } @llvm.experimental.vector.deinterleave2.v8i32(<8 x i32>) -declare { <2 x i64>, <2 x i64> } @llvm.experimental.vector.deinterleave2.v4i64(<4 x i64>) -declare { <4 x float>, <4 x float> } @llvm.experimental.vector.deinterleave2.v8f32(<8 x float>) -declare { <2 x double>, <2 x double> } @llvm.experimental.vector.deinterleave2.v4f64(<4 x double>) -declare { <2 x ptr>, <2 x ptr> } @llvm.experimental.vector.deinterleave2.v4p0(<4 x ptr>) -declare { <16 x i16>, <16 x i16> } @llvm.experimental.vector.deinterleave2.v32i16(<32 x i16>) +declare { <16 x i8>, <16 x i8> } @llvm.vector.deinterleave2.v32i8(<32 x i8>) +declare { <8 x i16>, <8 x i16> } @llvm.vector.deinterleave2.v16i16(<16 x i16>) +declare { <4 x i32>, <4 x i32> } @llvm.vector.deinterleave2.v8i32(<8 x i32>) +declare { <2 x i64>, <2 x i64> } @llvm.vector.deinterleave2.v4i64(<4 x i64>) +declare { <4 x float>, <4 x float> } @llvm.vector.deinterleave2.v8f32(<8 x float>) +declare { <2 x double>, <2 x double> } @llvm.vector.deinterleave2.v4f64(<4 x double>) +declare { <2 x ptr>, <2 x ptr> } @llvm.vector.deinterleave2.v4p0(<4 x ptr>) +declare { <16 x i16>, <16 x i16> } @llvm.vector.deinterleave2.v32i16(<32 x i16>) -declare <32 x i8> @llvm.experimental.vector.interleave2.v32i8(<16 x i8>, <16 x i8>) -declare <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) -declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) -declare <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) -declare <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float>, <4 x float>) -declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double>, <2 x double>) -declare <4 x ptr> @llvm.experimental.vector.interleave2.v4p0(<2 x ptr>, <2 x ptr>) -declare <16 x ptr> @llvm.experimental.vector.interleave2.v16p0(<8 x ptr>, <8 x ptr>) +declare <32 x i8> @llvm.vector.interleave2.v32i8(<16 x i8>, <16 x i8>) +declare <16 x i16> @llvm.vector.interleave2.v16i16(<8 x i16>, <8 x i16>) +declare <8 x i32> @llvm.vector.interleave2.v8i32(<4 x i32>, <4 x i32>) +declare <4 x i64> @llvm.vector.interleave2.v4i64(<2 x i64>, <2 x i64>) +declare <8 x float> @llvm.vector.interleave2.v8f32(<4 x float>, <4 x float>) +declare <4 x double> @llvm.vector.interleave2.v4f64(<2 x double>, <2 x double>) +declare <4 x ptr> @llvm.vector.interleave2.v4p0(<2 x ptr>, <2 x ptr>) +declare <16 x ptr> @llvm.vector.interleave2.v16p0(<8 x ptr>, <8 x ptr>) diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll index 6353bf10d57c..2a05718cc416 100644 --- a/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll +++ b/llvm/test/Transforms/InterleavedAccess/AArch64/scalable-deinterleave-intrinsics.ll @@ -11,7 +11,7 @@ define { , } @deinterleave_nxi8_factor2(ptr ; CHECK-NEXT: ret { , } [[LDN]] ; %load = load , ptr %ptr, align 1 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv32i8( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv32i8( %load) ret { , } %deinterleave } @@ -22,7 +22,7 @@ define { , } @deinterleave_nxi16_factor2(pt ; CHECK-NEXT: ret { , } [[LDN]] ; %load = load , ptr %ptr, align 2 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv16i16( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv16i16( %load) ret { , } %deinterleave } @@ -33,7 +33,7 @@ define { , } @deinterleave_nx8xi32_factor2( ; CHECK-NEXT: ret { , } [[LDN]] ; %load = load , ptr %ptr, align 4 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv8i32( %load) ret { , } %deinterleave } @@ -44,7 +44,7 @@ define { , } @deinterleave_nxi64_factor2(pt ; CHECK-NEXT: ret { , } [[LDN]] ; %load = load , ptr %ptr, align 8 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4i64( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv4i64( %load) ret { , } %deinterleave } @@ -55,7 +55,7 @@ define { , } @deinterleave_nxfloat_fact ; CHECK-NEXT: ret { , } [[LDN]] ; %load = load , ptr %ptr, align 4 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f32( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv8f32( %load) ret { , } %deinterleave } @@ -66,7 +66,7 @@ define { , } @deinterleave_nxdouble_f ; CHECK-NEXT: ret { , } [[LDN]] ; %load = load , ptr %ptr, align 8 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4f64( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv4f64( %load) ret { , } %deinterleave } @@ -77,7 +77,7 @@ define { , } @deinterleave_nxptr_factor2(pt ; CHECK-NEXT: ret { , } [[LDN]] ; %load = load , ptr %ptr, align 8 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv4p0( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv4p0( %load) ret { , } %deinterleave } @@ -87,7 +87,7 @@ define void @interleave_nxi8_factor2(ptr %ptr, %l, [[L]], [[R]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[PTR]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv32i8( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv32i8( %l, %r) store %interleave, ptr %ptr, align 1 ret void } @@ -98,7 +98,7 @@ define void @interleave_nxi16_factor2(ptr %ptr, %l, [[L]], [[R]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[PTR]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv16i16( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv16i16( %l, %r) store %interleave, ptr %ptr, align 2 ret void } @@ -109,7 +109,7 @@ define void @interleave_nxi32_factor2(ptr %ptr, %l, [[L]], [[R]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[PTR]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv8i32( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv8i32( %l, %r) store %interleave, ptr %ptr, align 4 ret void } @@ -120,7 +120,7 @@ define void @interleave_nxi64_factor2(ptr %ptr, %l, [[L]], [[R]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[PTR]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv4i64( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv4i64( %l, %r) store %interleave, ptr %ptr, align 8 ret void } @@ -131,7 +131,7 @@ define void @interleave_nxfloat_factor2(ptr %ptr, %l, [[L]], [[R]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[PTR]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv8f32( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv8f32( %l, %r) store %interleave, ptr %ptr, align 4 ret void } @@ -142,7 +142,7 @@ define void @interleave_nxdouble_factor2(ptr %ptr, %l, [[L]], [[R]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[PTR]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv4f64( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv4f64( %l, %r) store %interleave, ptr %ptr, align 4 ret void } @@ -153,7 +153,7 @@ define void @interleave_nxptr_factor2(ptr %ptr, %l, [[L]], [[R]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[PTR]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv4p0( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv4p0( %l, %r) store %interleave, ptr %ptr, align 4 ret void } @@ -192,7 +192,7 @@ define { , } @deinterleave_wide_nxi32_fac ; CHECK-NEXT: ret { , } [[TMP22]] ; %load = load , ptr %ptr, align 4 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv32i32( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv32i32( %load) ret { , } %deinterleave } @@ -216,7 +216,7 @@ define { , } @deinterleave_wide_nxdou ; CHECK-NEXT: ret { , } [[TMP12]] ; %load = load , ptr %ptr, align 8 - %deinterleave = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f64( %load) + %deinterleave = tail call { , } @llvm.vector.deinterleave2.nxv8f64( %load) ret { , } %deinterleave } @@ -233,32 +233,32 @@ define void @interleave_wide_nxdouble_factor2(ptr %ptr, %l ; CHECK-NEXT: call void @llvm.aarch64.sve.st2.nxv2f64( [[TMP5]], [[TMP6]], shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), ptr [[TMP4]]) ; CHECK-NEXT: ret void ; - %interleave = tail call @llvm.experimental.vector.interleave2.nxv8f64( %l, %r) + %interleave = tail call @llvm.vector.interleave2.nxv8f64( %l, %r) store %interleave, ptr %ptr, align 4 ret void } -declare { , } @llvm.experimental.vector.deinterleave2.nxv32i8() -declare { , } @llvm.experimental.vector.deinterleave2.nxv16i16() -declare { , } @llvm.experimental.vector.deinterleave2.nxv8i32() -declare { , } @llvm.experimental.vector.deinterleave2.nxv4i64() -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f32() -declare { , } @llvm.experimental.vector.deinterleave2.nxv4f64() -declare { , } @llvm.experimental.vector.deinterleave2.nxv4p0() +declare { , } @llvm.vector.deinterleave2.nxv32i8() +declare { , } @llvm.vector.deinterleave2.nxv16i16() +declare { , } @llvm.vector.deinterleave2.nxv8i32() +declare { , } @llvm.vector.deinterleave2.nxv4i64() +declare { , } @llvm.vector.deinterleave2.nxv8f32() +declare { , } @llvm.vector.deinterleave2.nxv4f64() +declare { , } @llvm.vector.deinterleave2.nxv4p0() ; Larger deinterleaves to test 'legalization' -declare { , } @llvm.experimental.vector.deinterleave2.nxv32i32() -declare { , } @llvm.experimental.vector.deinterleave2.nxv8f64() +declare { , } @llvm.vector.deinterleave2.nxv32i32() +declare { , } @llvm.vector.deinterleave2.nxv8f64() -declare @llvm.experimental.vector.interleave2.nxv32i8(, ) -declare @llvm.experimental.vector.interleave2.nxv16i16(, ) -declare @llvm.experimental.vector.interleave2.nxv8i32(, ) -declare @llvm.experimental.vector.interleave2.nxv4i64(, ) -declare @llvm.experimental.vector.interleave2.nxv8f32(, ) -declare @llvm.experimental.vector.interleave2.nxv4f64(, ) -declare @llvm.experimental.vector.interleave2.nxv4p0(, ) +declare @llvm.vector.interleave2.nxv32i8(, ) +declare @llvm.vector.interleave2.nxv16i16(, ) +declare @llvm.vector.interleave2.nxv8i32(, ) +declare @llvm.vector.interleave2.nxv4i64(, ) +declare @llvm.vector.interleave2.nxv8f32(, ) +declare @llvm.vector.interleave2.nxv4f64(, ) +declare @llvm.vector.interleave2.nxv4p0(, ) ; Larger interleaves to test 'legalization' -declare @llvm.experimental.vector.interleave2.nxv8f64(, ) +declare @llvm.vector.interleave2.nxv8f64(, ) attributes #0 = { vscale_range(1,16) "target-features"="+sve" } diff --git a/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll b/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll index 45e2c36836ff..73f26814f3a4 100644 --- a/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll +++ b/llvm/test/Transforms/InterleavedAccess/AArch64/sve-interleaved-accesses.ll @@ -511,7 +511,7 @@ define { , } @deinterleave_nxptr_fact ; CHECK-NEXT: ret { , } [[TMP12]] ; %wide.vec = load , ptr %ptr, align 8 - %ldN = tail call { , } @llvm.experimental.vector.deinterleave2.nxv8f64( %wide.vec) + %ldN = tail call { , } @llvm.vector.deinterleave2.nxv8f64( %wide.vec) ret { , } %ldN } diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll index 2be525a2abc0..2cc0aa2ffca5 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/first-order-recurrence.ll @@ -22,8 +22,8 @@ define i32 @PR33613(ptr %b, double %j, i32 %d) #0 { ; CHECK-VF4UF2-LABEL: @PR33613 ; CHECK-VF4UF2: vector.body ; CHECK-VF4UF2: %[[VEC_RECUR:.*]] = phi [ {{.*}}, %vector.ph ], [ {{.*}}, %vector.body ] -; CHECK-VF4UF2: %[[SPLICE1:.*]] = call @llvm.experimental.vector.splice.nxv4f64( %[[VEC_RECUR]], {{.*}}, i32 -1) -; CHECK-VF4UF2-NEXT: %[[SPLICE2:.*]] = call @llvm.experimental.vector.splice.nxv4f64( %{{.*}}, %{{.*}}, i32 -1) +; CHECK-VF4UF2: %[[SPLICE1:.*]] = call @llvm.vector.splice.nxv4f64( %[[VEC_RECUR]], {{.*}}, i32 -1) +; CHECK-VF4UF2-NEXT: %[[SPLICE2:.*]] = call @llvm.vector.splice.nxv4f64( %{{.*}}, %{{.*}}, i32 -1) ; CHECK-VF4UF2-NOT: insertelement ; CHECK-VF4UF2: middle.block entry: @@ -71,7 +71,7 @@ define void @PR34711(ptr %a, ptr %b, ptr %c, i64 %n) #0 { ; CHECK-VF4UF1: vector.body ; CHECK-VF4UF1: %[[VEC_RECUR:.*]] = phi [ %vector.recur.init, %vector.ph ], [ %[[MGATHER:.*]], %vector.body ] ; CHECK-VF4UF1: %[[MGATHER]] = call @llvm.masked.gather.nxv4i16.nxv4p0( {{.*}}, i32 2, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison) -; CHECK-VF4UF1-NEXT: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i16( %[[VEC_RECUR]], %[[MGATHER]], i32 -1) +; CHECK-VF4UF1-NEXT: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i16( %[[VEC_RECUR]], %[[MGATHER]], i32 -1) ; CHECK-VF4UF1-NEXT: %[[SXT1:.*]] = sext %[[SPLICE]] to ; CHECK-VF4UF1-NEXT: %[[SXT2:.*]] = sext %[[MGATHER]] to ; CHECK-VF4UF1-NEXT: mul nsw %[[SXT2]], %[[SXT1]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll index 75250df79d17..c24c1a38177d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/reduction-recurrence-costs-sve.ll @@ -50,10 +50,10 @@ define i32 @chained_recurrences(i32 %x, i64 %y, ptr %src.1, i32 %z, ptr %src.2) ; DEFAULT-NEXT: [[TMP18:%.*]] = load i32, ptr [[TMP16]], align 4 ; DEFAULT-NEXT: [[BROADCAST_SPLATINSERT4:%.*]] = insertelement poison, i32 [[TMP18]], i64 0 ; DEFAULT-NEXT: [[BROADCAST_SPLAT5]] = shufflevector [[BROADCAST_SPLATINSERT4]], poison, zeroinitializer -; DEFAULT-NEXT: [[TMP19:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR]], [[BROADCAST_SPLAT]], i32 -1) -; DEFAULT-NEXT: [[TMP20]] = call @llvm.experimental.vector.splice.nxv4i32( [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT5]], i32 -1) -; DEFAULT-NEXT: [[TMP21:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR2]], [[TMP19]], i32 -1) -; DEFAULT-NEXT: [[TMP22:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[TMP19]], [[TMP20]], i32 -1) +; DEFAULT-NEXT: [[TMP19:%.*]] = call @llvm.vector.splice.nxv4i32( [[VECTOR_RECUR]], [[BROADCAST_SPLAT]], i32 -1) +; DEFAULT-NEXT: [[TMP20]] = call @llvm.vector.splice.nxv4i32( [[BROADCAST_SPLAT]], [[BROADCAST_SPLAT5]], i32 -1) +; DEFAULT-NEXT: [[TMP21:%.*]] = call @llvm.vector.splice.nxv4i32( [[VECTOR_RECUR2]], [[TMP19]], i32 -1) +; DEFAULT-NEXT: [[TMP22:%.*]] = call @llvm.vector.splice.nxv4i32( [[TMP19]], [[TMP20]], i32 -1) ; DEFAULT-NEXT: [[TMP23:%.*]] = or [[TMP21]], [[BROADCAST_SPLAT7]] ; DEFAULT-NEXT: [[TMP24:%.*]] = or [[TMP22]], [[BROADCAST_SPLAT7]] ; DEFAULT-NEXT: [[TMP25:%.*]] = lshr [[BROADCAST_SPLAT7]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) @@ -197,8 +197,8 @@ define i32 @chained_recurrences(i32 %x, i64 %y, ptr %src.1, i32 %z, ptr %src.2) ; PRED-NEXT: [[TMP21:%.*]] = load i32, ptr [[TMP20]], align 4 ; PRED-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement poison, i32 [[TMP21]], i64 0 ; PRED-NEXT: [[BROADCAST_SPLAT]] = shufflevector [[BROADCAST_SPLATINSERT]], poison, zeroinitializer -; PRED-NEXT: [[TMP22]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR]], [[BROADCAST_SPLAT]], i32 -1) -; PRED-NEXT: [[TMP23:%.*]] = call @llvm.experimental.vector.splice.nxv4i32( [[VECTOR_RECUR2]], [[TMP22]], i32 -1) +; PRED-NEXT: [[TMP22]] = call @llvm.vector.splice.nxv4i32( [[VECTOR_RECUR]], [[BROADCAST_SPLAT]], i32 -1) +; PRED-NEXT: [[TMP23:%.*]] = call @llvm.vector.splice.nxv4i32( [[VECTOR_RECUR2]], [[TMP22]], i32 -1) ; PRED-NEXT: [[TMP24:%.*]] = or [[TMP23]], [[BROADCAST_SPLAT4]] ; PRED-NEXT: [[TMP25:%.*]] = lshr [[BROADCAST_SPLAT4]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ; PRED-NEXT: [[TMP26:%.*]] = shl [[TMP24]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll index ad6e8534f318..ddc004657ed5 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/scalable-strict-fadd.ll @@ -588,7 +588,7 @@ define void @fadd_strict_interleave(ptr noalias nocapture readonly %a, ptr noali ; CHECK-UNORDERED-NEXT: [[TMP10:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP9]] ; CHECK-UNORDERED-NEXT: [[TMP11:%.*]] = getelementptr inbounds float, ptr [[TMP10]], i32 0 ; CHECK-UNORDERED-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP11]], align 4 -; CHECK-UNORDERED-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8f32( [[WIDE_VEC]]) +; CHECK-UNORDERED-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8f32( [[WIDE_VEC]]) ; CHECK-UNORDERED-NEXT: [[TMP12:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-UNORDERED-NEXT: [[TMP13:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; CHECK-UNORDERED-NEXT: [[TMP14]] = fadd [[TMP12]], [[VEC_PHI1]] @@ -658,7 +658,7 @@ define void @fadd_strict_interleave(ptr noalias nocapture readonly %a, ptr noali ; CHECK-ORDERED-NEXT: [[TMP8:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP7]] ; CHECK-ORDERED-NEXT: [[TMP9:%.*]] = getelementptr inbounds float, ptr [[TMP8]], i32 0 ; CHECK-ORDERED-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP9]], align 4 -; CHECK-ORDERED-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8f32( [[WIDE_VEC]]) +; CHECK-ORDERED-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8f32( [[WIDE_VEC]]) ; CHECK-ORDERED-NEXT: [[TMP10:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-ORDERED-NEXT: [[TMP11:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; CHECK-ORDERED-NEXT: [[TMP12]] = call float @llvm.vector.reduce.fadd.nxv4f32(float [[VEC_PHI]], [[TMP11]]) @@ -733,9 +733,9 @@ define void @fadd_strict_interleave(ptr noalias nocapture readonly %a, ptr noali ; CHECK-ORDERED-TF-NEXT: [[TMP13:%.*]] = add i64 [[OFFSET_IDX]], 0 ; CHECK-ORDERED-TF-NEXT: [[TMP14:%.*]] = getelementptr inbounds float, ptr [[B]], i64 [[TMP13]] ; CHECK-ORDERED-TF-NEXT: [[TMP15:%.*]] = getelementptr inbounds float, ptr [[TMP14]], i32 0 -; CHECK-ORDERED-TF-NEXT: [[INTERLEAVED_MASK:%.*]] = call @llvm.experimental.vector.interleave2.nxv8i1( [[ACTIVE_LANE_MASK]], [[ACTIVE_LANE_MASK]]) +; CHECK-ORDERED-TF-NEXT: [[INTERLEAVED_MASK:%.*]] = call @llvm.vector.interleave2.nxv8i1( [[ACTIVE_LANE_MASK]], [[ACTIVE_LANE_MASK]]) ; CHECK-ORDERED-TF-NEXT: [[WIDE_MASKED_VEC:%.*]] = call @llvm.masked.load.nxv8f32.p0(ptr [[TMP15]], i32 4, [[INTERLEAVED_MASK]], poison) -; CHECK-ORDERED-TF-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8f32( [[WIDE_MASKED_VEC]]) +; CHECK-ORDERED-TF-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8f32( [[WIDE_MASKED_VEC]]) ; CHECK-ORDERED-TF-NEXT: [[TMP16:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-ORDERED-TF-NEXT: [[TMP17:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; CHECK-ORDERED-TF-NEXT: [[TMP18:%.*]] = select [[ACTIVE_LANE_MASK]], [[TMP17]], shufflevector ( insertelement ( poison, float -0.000000e+00, i64 0), poison, zeroinitializer) diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll index c07b3c8d4922..1853e551806b 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-accesses.ll @@ -38,7 +38,7 @@ define void @test_array_load2_store2(i32 %C, i32 %D) #1 { ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [1024 x i32], ptr @AB, i64 0, i64 [[OFFSET_IDX]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP2]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = or disjoint i64 [[OFFSET_IDX]], 1 @@ -46,7 +46,7 @@ define void @test_array_load2_store2(i32 %C, i32 %D) #1 { ; CHECK-NEXT: [[TMP7:%.*]] = mul nsw [[TMP4]], [[BROADCAST_SPLAT2]] ; CHECK-NEXT: [[TMP8:%.*]] = getelementptr inbounds [1024 x i32], ptr @CD, i64 0, i64 [[TMP5]] ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i8, ptr [[TMP8]], i64 -4 -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.experimental.vector.interleave2.nxv8i32( [[TMP6]], [[TMP7]]) +; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv8i32( [[TMP6]], [[TMP7]]) ; CHECK-NEXT: store [[INTERLEAVED_VEC]], ptr [[TMP9]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] ; CHECK-NEXT: [[TMP10:%.*]] = icmp eq i64 [[INDEX_NEXT]], 512 @@ -134,7 +134,7 @@ define void @test_array_load2_i16_store2(i32 %C, i32 %D) #1 { ; CHECK-NEXT: [[TMP13:%.*]] = extractelement [[TMP7]], i64 0 ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [1024 x i32], ptr @CD, i64 0, i64 [[TMP13]] ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[TMP14]], i64 -4 -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.experimental.vector.interleave2.nxv8i32( [[TMP10]], [[TMP12]]) +; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv8i32( [[TMP10]], [[TMP12]]) ; CHECK-NEXT: store [[INTERLEAVED_VEC]], ptr [[TMP15]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] ; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[DOTSPLAT]] @@ -216,7 +216,7 @@ define void @test_array_load2_store2_i16(i32 noundef %C, i32 noundef %D) #1 { ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = getelementptr inbounds [1024 x i32], ptr @AB, i64 0, i64 [[OFFSET_IDX]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP6]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP8:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; CHECK-NEXT: [[TMP9:%.*]] = or disjoint [[VEC_IND]], shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer) @@ -401,11 +401,11 @@ define void @test_reversed_load2_store2(ptr noalias nocapture readonly %A, ptr n ; CHECK-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64 ; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i32, ptr [[TMP4]], i64 [[TMP8]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP9]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP10:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 -; CHECK-NEXT: [[REVERSE:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[TMP10]]) +; CHECK-NEXT: [[REVERSE:%.*]] = call @llvm.vector.reverse.nxv4i32( [[TMP10]]) ; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 -; CHECK-NEXT: [[REVERSE1:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[TMP11]]) +; CHECK-NEXT: [[REVERSE1:%.*]] = call @llvm.vector.reverse.nxv4i32( [[TMP11]]) ; CHECK-NEXT: [[TMP12:%.*]] = add nsw [[REVERSE]], [[VEC_IND]] ; CHECK-NEXT: [[TMP13:%.*]] = sub nsw [[REVERSE1]], [[VEC_IND]] ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[STRUCT_ST2]], ptr [[B:%.*]], i64 [[OFFSET_IDX]], i32 1 @@ -414,9 +414,9 @@ define void @test_reversed_load2_store2(ptr noalias nocapture readonly %A, ptr n ; CHECK-NEXT: [[TMP17:%.*]] = sub nsw i32 1, [[TMP16]] ; CHECK-NEXT: [[TMP18:%.*]] = sext i32 [[TMP17]] to i64 ; CHECK-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[TMP14]], i64 [[TMP18]] -; CHECK-NEXT: [[REVERSE2:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[TMP12]]) -; CHECK-NEXT: [[REVERSE3:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[TMP13]]) -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.experimental.vector.interleave2.nxv8i32( [[REVERSE2]], [[REVERSE3]]) +; CHECK-NEXT: [[REVERSE2:%.*]] = call @llvm.vector.reverse.nxv4i32( [[TMP12]]) +; CHECK-NEXT: [[REVERSE3:%.*]] = call @llvm.vector.reverse.nxv4i32( [[TMP13]]) +; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv8i32( [[REVERSE2]], [[REVERSE3]]) ; CHECK-NEXT: store [[INTERLEAVED_VEC]], ptr [[TMP19]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] ; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[DOTSPLAT]] @@ -483,7 +483,7 @@ define void @even_load_static_tc(ptr noalias nocapture readonly %A, ptr noalias ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP4:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[OFFSET_IDX]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP4]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP5:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP6:%.*]] = shl nsw [[TMP5]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP7:%.*]] = and i64 [[INDEX]], 9223372036854775804 @@ -569,7 +569,7 @@ define void @even_load_dynamic_tc(ptr noalias nocapture readonly %A, ptr noalias ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[OFFSET_IDX]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP12]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = shl nsw [[TMP13]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) ; CHECK-NEXT: [[TMP15:%.*]] = and i64 [[INDEX]], 9223372036854775804 @@ -717,18 +717,18 @@ define void @mixed_load2_store2(ptr noalias nocapture readonly %A, ptr noalias n ; CHECK-NEXT: [[OFFSET_IDX:%.*]] = shl i64 [[INDEX]], 1 ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds i32, ptr [[A:%.*]], i64 [[OFFSET_IDX]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP2]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = or disjoint i64 [[OFFSET_IDX]], 1 ; CHECK-NEXT: [[TMP6:%.*]] = mul nsw [[TMP4]], [[TMP3]] -; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP7:%.*]] = extractvalue { , } [[STRIDED_VEC2]], 0 ; CHECK-NEXT: [[TMP8:%.*]] = extractvalue { , } [[STRIDED_VEC2]], 1 ; CHECK-NEXT: [[TMP9:%.*]] = add nsw [[TMP8]], [[TMP7]] ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i32, ptr [[B:%.*]], i64 [[TMP5]] ; CHECK-NEXT: [[TMP11:%.*]] = getelementptr inbounds i8, ptr [[TMP10]], i64 -4 -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.experimental.vector.interleave2.nxv8i32( [[TMP6]], [[TMP9]]) +; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv8i32( [[TMP6]], [[TMP9]]) ; CHECK-NEXT: store [[INTERLEAVED_VEC]], ptr [[TMP11]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP1]] ; CHECK-NEXT: [[TMP12:%.*]] = icmp eq i64 [[INDEX_NEXT]], 512 @@ -811,7 +811,7 @@ define void @int_float_struct(ptr nocapture readonly %p) #0 { ; CHECK-NEXT: [[VEC_PHI1:%.*]] = phi [ insertelement ( zeroinitializer, i32 undef, i32 0), [[VECTOR_PH]] ], [ [[TMP6:%.*]], [[VECTOR_BODY]] ] ; CHECK-NEXT: [[TMP2:%.*]] = getelementptr inbounds [[STRUCT_INTFLOAT:%.*]], ptr [[P:%.*]], i64 [[INDEX]], i32 0 ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP2]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP3:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP4:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; CHECK-NEXT: [[TMP5:%.*]] = bitcast [[TMP4]] to @@ -910,7 +910,7 @@ define void @PR27626_0(ptr %p, i32 %z, i64 %n) #1 { ; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[BROADCAST_SPLAT]], [[TMP12]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) ; CHECK-NEXT: [[TMP14:%.*]] = extractelement [[TMP12]], i64 0 ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP14]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP15:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[TMP15]], [[TMP13]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP8]] @@ -994,12 +994,12 @@ define i32 @PR27626_1(ptr %p, i64 %n) #1 { ; CHECK-NEXT: [[TMP12:%.*]] = getelementptr inbounds [[PAIR_I32:%.*]], ptr [[P:%.*]], i64 [[INDEX]], i32 0 ; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], [[VEC_IND]], i32 1 ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP12]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[TMP14]], [[TMP13]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) ; CHECK-NEXT: [[TMP15:%.*]] = extractelement [[TMP13]], i64 0 ; CHECK-NEXT: [[WIDE_VEC1:%.*]] = load , ptr [[TMP15]], align 4 -; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC1]]) +; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC1]]) ; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { , } [[STRIDED_VEC2]], 0 ; CHECK-NEXT: [[TMP17]] = add [[TMP16]], [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP8]] @@ -1092,7 +1092,7 @@ define void @PR27626_2(ptr %p, i64 %n, i32 %z) #1 { ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], [[VEC_IND]], i32 1 ; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[BROADCAST_SPLAT]], [[TMP12]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP13]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP15:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[TMP15]], [[TMP14]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP8]] @@ -1181,11 +1181,11 @@ define i32 @PR27626_3(ptr %p, i64 %n, i32 %z) #1 { ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], i64 [[INDEX]], i32 1 ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds [[PAIR_I32]], ptr [[P]], [[TMP12]], i32 1 ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP13]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP16:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[TMP16]], [[TMP15]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) ; CHECK-NEXT: [[WIDE_VEC1:%.*]] = load , ptr [[TMP14]], align 4 -; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC1]]) +; CHECK-NEXT: [[STRIDED_VEC2:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC1]]) ; CHECK-NEXT: [[TMP17:%.*]] = extractvalue { , } [[STRIDED_VEC2]], 0 ; CHECK-NEXT: [[TMP18]] = add [[TMP17]], [[VEC_PHI]] ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP8]] @@ -1291,7 +1291,7 @@ define void @PR27626_4(ptr %a, i32 %x, i32 %y, i32 %z, i64 %n) #1 { ; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, ptr [[A]], i64 [[TMP12]] ; CHECK-NEXT: call void @llvm.masked.scatter.nxv4i32.nxv4p0( [[BROADCAST_SPLAT]], [[TMP13]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer)) ; CHECK-NEXT: [[TMP15:%.*]] = getelementptr inbounds i8, ptr [[TMP14]], i64 -4 -; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.experimental.vector.interleave2.nxv8i32( [[BROADCAST_SPLAT2]], [[BROADCAST_SPLAT4]]) +; CHECK-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv8i32( [[BROADCAST_SPLAT2]], [[BROADCAST_SPLAT4]]) ; CHECK-NEXT: store [[INTERLEAVED_VEC]], ptr [[TMP15]], align 4 ; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], [[TMP7]] ; CHECK-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[DOTSPLAT]] @@ -1497,7 +1497,7 @@ define void @PR34743(ptr %a, ptr %b, i64 %n) #1 { ; CHECK-NEXT: [[TMP21:%.*]] = sext [[WIDE_MASKED_GATHER]] to ; CHECK-NEXT: [[TMP22:%.*]] = getelementptr inbounds i16, ptr [[A]], [[TMP19]] ; CHECK-NEXT: [[WIDE_MASKED_GATHER4]] = call @llvm.masked.gather.nxv4i16.nxv4p0( [[TMP22]], i32 4, shufflevector ( insertelement ( poison, i1 true, i64 0), poison, zeroinitializer), poison), !alias.scope [[META34]] -; CHECK-NEXT: [[TMP23:%.*]] = call @llvm.experimental.vector.splice.nxv4i16( [[VECTOR_RECUR]], [[WIDE_MASKED_GATHER4]], i32 -1) +; CHECK-NEXT: [[TMP23:%.*]] = call @llvm.vector.splice.nxv4i16( [[VECTOR_RECUR]], [[WIDE_MASKED_GATHER4]], i32 -1) ; CHECK-NEXT: [[TMP24:%.*]] = sext [[TMP23]] to ; CHECK-NEXT: [[TMP25:%.*]] = sext [[WIDE_MASKED_GATHER4]] to ; CHECK-NEXT: [[TMP26:%.*]] = mul nsw [[TMP24]], [[TMP21]] diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll index 3ba91360850e..726d98f4d37d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-interleaved-masked-accesses.ll @@ -52,9 +52,9 @@ define dso_local void @masked_strided1(ptr noalias nocapture readonly %p, ptr no ; SCALAR_TAIL_FOLDING-NEXT: [[TMP8:%.*]] = shl i32 [[INDEX]], 1 ; SCALAR_TAIL_FOLDING-NEXT: [[TMP9:%.*]] = sext i32 [[TMP8]] to i64 ; SCALAR_TAIL_FOLDING-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP9]] -; SCALAR_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK:%.*]] = call @llvm.experimental.vector.interleave2.nxv32i1( [[TMP7]], [[TMP7]]) +; SCALAR_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK:%.*]] = call @llvm.vector.interleave2.nxv32i1( [[TMP7]], [[TMP7]]) ; SCALAR_TAIL_FOLDING-NEXT: [[WIDE_MASKED_VEC:%.*]] = call @llvm.masked.load.nxv32i8.p0(ptr [[TMP10]], i32 1, [[INTERLEAVED_MASK]], poison) -; SCALAR_TAIL_FOLDING-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv32i8( [[WIDE_MASKED_VEC]]) +; SCALAR_TAIL_FOLDING-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv32i8( [[WIDE_MASKED_VEC]]) ; SCALAR_TAIL_FOLDING-NEXT: [[TMP11:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; SCALAR_TAIL_FOLDING-NEXT: [[TMP12:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; SCALAR_TAIL_FOLDING-NEXT: [[TMP13:%.*]] = or disjoint i32 [[TMP8]], 1 @@ -63,8 +63,8 @@ define dso_local void @masked_strided1(ptr noalias nocapture readonly %p, ptr no ; SCALAR_TAIL_FOLDING-NEXT: [[TMP16:%.*]] = sext i32 [[TMP13]] to i64 ; SCALAR_TAIL_FOLDING-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP16]] ; SCALAR_TAIL_FOLDING-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[TMP17]], i64 -1 -; SCALAR_TAIL_FOLDING-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.experimental.vector.interleave2.nxv32i8( [[TMP14]], [[TMP15]]) -; SCALAR_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK1:%.*]] = call @llvm.experimental.vector.interleave2.nxv32i1( [[TMP7]], [[TMP7]]) +; SCALAR_TAIL_FOLDING-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv32i8( [[TMP14]], [[TMP15]]) +; SCALAR_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK1:%.*]] = call @llvm.vector.interleave2.nxv32i1( [[TMP7]], [[TMP7]]) ; SCALAR_TAIL_FOLDING-NEXT: call void @llvm.masked.store.nxv32i8.p0( [[INTERLEAVED_VEC]], ptr [[TMP18]], i32 1, [[INTERLEAVED_MASK1]]) ; SCALAR_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], [[TMP20]] ; SCALAR_TAIL_FOLDING-NEXT: [[VEC_IND_NEXT]] = add [[VEC_IND]], [[DOTSPLAT]] @@ -134,9 +134,9 @@ define dso_local void @masked_strided1(ptr noalias nocapture readonly %p, ptr no ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP7:%.*]] = shl i32 [[INDEX]], 1 ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP8:%.*]] = sext i32 [[TMP7]] to i64 ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP9:%.*]] = getelementptr i8, ptr [[P]], i64 [[TMP8]] -; PREDICATED_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK:%.*]] = call @llvm.experimental.vector.interleave2.nxv32i1( [[TMP10]], [[TMP10]]) +; PREDICATED_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK:%.*]] = call @llvm.vector.interleave2.nxv32i1( [[TMP10]], [[TMP10]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[WIDE_MASKED_VEC:%.*]] = call @llvm.masked.load.nxv32i8.p0(ptr [[TMP9]], i32 1, [[INTERLEAVED_MASK]], poison) -; PREDICATED_TAIL_FOLDING-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv32i8( [[WIDE_MASKED_VEC]]) +; PREDICATED_TAIL_FOLDING-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv32i8( [[WIDE_MASKED_VEC]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP11:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP12:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP13:%.*]] = or disjoint i32 [[TMP7]], 1 @@ -145,8 +145,8 @@ define dso_local void @masked_strided1(ptr noalias nocapture readonly %p, ptr no ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP16:%.*]] = sext i32 [[TMP13]] to i64 ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP17:%.*]] = getelementptr i8, ptr [[Q]], i64 [[TMP16]] ; PREDICATED_TAIL_FOLDING-NEXT: [[TMP18:%.*]] = getelementptr i8, ptr [[TMP17]], i64 -1 -; PREDICATED_TAIL_FOLDING-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.experimental.vector.interleave2.nxv32i8( [[TMP14]], [[TMP15]]) -; PREDICATED_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK1:%.*]] = call @llvm.experimental.vector.interleave2.nxv32i1( [[TMP10]], [[TMP10]]) +; PREDICATED_TAIL_FOLDING-NEXT: [[INTERLEAVED_VEC:%.*]] = call @llvm.vector.interleave2.nxv32i8( [[TMP14]], [[TMP15]]) +; PREDICATED_TAIL_FOLDING-NEXT: [[INTERLEAVED_MASK1:%.*]] = call @llvm.vector.interleave2.nxv32i1( [[TMP10]], [[TMP10]]) ; PREDICATED_TAIL_FOLDING-NEXT: call void @llvm.masked.store.nxv32i8.p0( [[INTERLEAVED_VEC]], ptr [[TMP18]], i32 1, [[INTERLEAVED_MASK1]]) ; PREDICATED_TAIL_FOLDING-NEXT: [[INDEX_NEXT]] = add i32 [[INDEX]], [[TMP20]] ; PREDICATED_TAIL_FOLDING-NEXT: [[ACTIVE_LANE_MASK_NEXT]] = call @llvm.get.active.lane.mask.nxv16i1.i32(i32 [[INDEX]], i32 [[TMP2]]) diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll index 1dfa7f8fe18b..cf4d65318b7e 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-tail-folding-option.ll @@ -178,7 +178,7 @@ define void @add_recur(ptr noalias %dst, ptr noalias %src, i64 %n) #0 { ; CHECK-NOTF-NOT: %{{.*}} = phi ; CHECK-NOTF: %[[VECTOR_RECUR:.*]] = phi [ %[[RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-NOTF: %[[LOAD]] = load -; CHECK-NOTF: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) +; CHECK-NOTF: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) ; CHECK-NOTF: %[[ADD:.*]] = add nsw %[[LOAD]], %[[SPLICE]] ; CHECK-NOTF: store %[[ADD]] @@ -191,7 +191,7 @@ define void @add_recur(ptr noalias %dst, ptr noalias %src, i64 %n) #0 { ; CHECK-TF-NORED: %[[ACTIVE_LANE_MASK:.*]] = phi ; CHECK-TF-NORED: %[[VECTOR_RECUR:.*]] = phi [ %[[RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-TF-NORED: %[[LOAD]] = call @llvm.masked.load.nxv4i32.p0({{.*}} %[[ACTIVE_LANE_MASK]] -; CHECK-TF-NORED: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) +; CHECK-TF-NORED: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) ; CHECK-TF-NORED: %[[ADD:.*]] = add nsw %[[LOAD]], %[[SPLICE]] ; CHECK-TF-NORED: call void @llvm.masked.store.nxv4i32.p0( %[[ADD]], {{.*}} %[[ACTIVE_LANE_MASK]]) @@ -204,7 +204,7 @@ define void @add_recur(ptr noalias %dst, ptr noalias %src, i64 %n) #0 { ; CHECK-TF-NOREC-NOT: %{{.*}} = phi ; CHECK-TF-NOREC: %[[VECTOR_RECUR:.*]] = phi [ %[[RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-TF-NOREC: %[[LOAD]] = load -; CHECK-TF-NOREC: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) +; CHECK-TF-NOREC: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) ; CHECK-TF-NOREC: %[[ADD:.*]] = add nsw %[[LOAD]], %[[SPLICE]] ; CHECK-TF-NOREC: store %[[ADD]] @@ -217,7 +217,7 @@ define void @add_recur(ptr noalias %dst, ptr noalias %src, i64 %n) #0 { ; CHECK-TF-NOREV: %[[ACTIVE_LANE_MASK:.*]] = phi ; CHECK-TF-NOREV: %[[VECTOR_RECUR:.*]] = phi [ %[[RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-TF-NOREV: %[[LOAD]] = call @llvm.masked.load.nxv4i32.p0({{.*}} %[[ACTIVE_LANE_MASK]] -; CHECK-TF-NOREV: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) +; CHECK-TF-NOREV: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) ; CHECK-TF-NOREV: %[[ADD:.*]] = add nsw %[[LOAD]], %[[SPLICE]] ; CHECK-TF-NOREV: call void @llvm.masked.store.nxv4i32.p0( %[[ADD]], {{.*}} %[[ACTIVE_LANE_MASK]]) @@ -230,7 +230,7 @@ define void @add_recur(ptr noalias %dst, ptr noalias %src, i64 %n) #0 { ; CHECK-TF: %[[ACTIVE_LANE_MASK:.*]] = phi ; CHECK-TF: %[[VECTOR_RECUR:.*]] = phi [ %[[RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-TF: %[[LOAD]] = call @llvm.masked.load.nxv4i32.p0({{.*}} %[[ACTIVE_LANE_MASK]] -; CHECK-TF: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) +; CHECK-TF: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) ; CHECK-TF: %[[ADD:.*]] = add nsw %[[LOAD]], %[[SPLICE]] ; CHECK-TF: call void @llvm.masked.store.nxv4i32.p0( %[[ADD]], {{.*}} %[[ACTIVE_LANE_MASK]]) @@ -243,7 +243,7 @@ define void @add_recur(ptr noalias %dst, ptr noalias %src, i64 %n) #0 { ; CHECK-TF-ONLYRED-NOT: %{{.*}} = phi ; CHECK-TF-ONLYRED: %[[VECTOR_RECUR:.*]] = phi [ %[[RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-TF-ONLYRED: %[[LOAD]] = load -; CHECK-TF-ONLYRED: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) +; CHECK-TF-ONLYRED: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) ; CHECK-TF-ONLYRED: %[[ADD:.*]] = add nsw %[[LOAD]], %[[SPLICE]] ; CHECK-TF-ONLYRED: store %[[ADD]] @@ -256,7 +256,7 @@ define void @add_recur(ptr noalias %dst, ptr noalias %src, i64 %n) #0 { ; CHECK-NEOVERSE-V1-NOT: %{{.*}} = phi ; CHECK-NEOVERSE-V1: %[[VECTOR_RECUR:.*]] = phi [ %[[RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-NEOVERSE-V1: %[[LOAD]] = load -; CHECK-NEOVERSE-V1: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) +; CHECK-NEOVERSE-V1: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VECTOR_RECUR]], %[[LOAD]], i32 -1) ; CHECK-NEOVERSE-V1: %[[ADD:.*]] = add nsw %[[LOAD]], %[[SPLICE]] ; CHECK-NEOVERSE-V1: store %[[ADD]] @@ -350,30 +350,30 @@ define void @reverse(ptr noalias %dst, ptr noalias %src) #0 { ; CHECK-NOTF: vector.body: ; CHECK-NOTF-NOT: %{{.*}} = phi ; CHECK-NOTF: %[[LOAD:.*]] = load , ptr -; CHECK-NOTF: %{{.*}} = call @llvm.experimental.vector.reverse.nxv2f64( %[[LOAD]]) +; CHECK-NOTF: %{{.*}} = call @llvm.vector.reverse.nxv2f64( %[[LOAD]]) ; CHECK-TF-NOREV-LABEL: @reverse( ; CHECK-TF-NOREV: vector.body: ; CHECK-TF-NOREV-NOT: %{{.*}} = phi ; CHECK-TF-NOREV: %[[LOAD:.*]] = load , ptr -; CHECK-TF-NOREV: %{{.*}} = call @llvm.experimental.vector.reverse.nxv2f64( %[[LOAD]]) +; CHECK-TF-NOREV: %{{.*}} = call @llvm.vector.reverse.nxv2f64( %[[LOAD]]) ; CHECK-TF-LABEL: @reverse( ; CHECK-TF: vector.body: ; CHECK-TF: %[[ACTIVE_LANE_MASK:.*]] = phi -; CHECK-TF: %[[REVERSE_MASK:.*]] = call @llvm.experimental.vector.reverse.nxv2i1( %[[ACTIVE_LANE_MASK]]) +; CHECK-TF: %[[REVERSE_MASK:.*]] = call @llvm.vector.reverse.nxv2i1( %[[ACTIVE_LANE_MASK]]) ; CHECK-TF: %[[MASKED_LOAD:.*]] = call @llvm.masked.load.nxv2f64.p0({{.*}} %reverse ; CHECK-TF-NORED-LABEL: @reverse( ; CHECK-TF-NORED: vector.body: ; CHECK-TF-NORED: %[[ACTIVE_LANE_MASK:.*]] = phi -; CHECK-TF-NORED: %[[REVERSE_MASK:.*]] = call @llvm.experimental.vector.reverse.nxv2i1( %[[ACTIVE_LANE_MASK]]) +; CHECK-TF-NORED: %[[REVERSE_MASK:.*]] = call @llvm.vector.reverse.nxv2i1( %[[ACTIVE_LANE_MASK]]) ; CHECK-TF-NORED: %[[MASKED_LOAD:.*]] = call @llvm.masked.load.nxv2f64.p0({{.*}} %reverse ; CHECK-TF-NOREC-LABEL: @reverse( ; CHECK-TF-NOREC: vector.body: ; CHECK-TF-NOREC: %[[ACTIVE_LANE_MASK:.*]] = phi -; CHECK-TF-NOREC: %[[REVERSE_MASK:.*]] = call @llvm.experimental.vector.reverse.nxv2i1( %[[ACTIVE_LANE_MASK]]) +; CHECK-TF-NOREC: %[[REVERSE_MASK:.*]] = call @llvm.vector.reverse.nxv2i1( %[[ACTIVE_LANE_MASK]]) ; CHECK-TF-NOREC: %[[MASKED_LOAD:.*]] = call @llvm.masked.load.nxv2f64.p0({{.*}} %reverse entry: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll index 70833e44b075..9485d827ced4 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse-mask4.ll @@ -1,5 +1,5 @@ ; This is the loop in c++ being vectorize in this file with -; experimental.vector.reverse +; vector.reverse ;#pragma clang loop vectorize_width(4, scalable) ; for (long int i = N - 1; i >= 0; i--) @@ -18,12 +18,12 @@ target triple = "aarch64-unknown-linux-gnu" define void @vector_reverse_mask_nxv4i1(ptr %a, ptr %cond, i64 %N) #0 { ; CHECK-LABEL: vector.body: -; CHECK: %[[REVERSE6:.*]] = call @llvm.experimental.vector.reverse.nxv4i1( %{{.*}}) +; CHECK: %[[REVERSE6:.*]] = call @llvm.vector.reverse.nxv4i1( %{{.*}}) ; CHECK: %[[WIDEMSKLOAD:.*]] = call @llvm.masked.load.nxv4f64.p0(ptr %{{.*}}, i32 8, %[[REVERSE6]], poison) -; CHECK: %[[REVERSE7:.*]] = call @llvm.experimental.vector.reverse.nxv4f64( %[[WIDEMSKLOAD]]) +; CHECK: %[[REVERSE7:.*]] = call @llvm.vector.reverse.nxv4f64( %[[WIDEMSKLOAD]]) ; CHECK: %[[FADD:.*]] = fadd %[[REVERSE7]] -; CHECK: %[[REVERSE9:.*]] = call @llvm.experimental.vector.reverse.nxv4i1( %{{.*}}) -; CHECK: %[[REVERSE8:.*]] = call @llvm.experimental.vector.reverse.nxv4f64( %[[FADD]]) +; CHECK: %[[REVERSE9:.*]] = call @llvm.vector.reverse.nxv4i1( %{{.*}}) +; CHECK: %[[REVERSE8:.*]] = call @llvm.vector.reverse.nxv4f64( %[[FADD]]) ; CHECK: call void @llvm.masked.store.nxv4f64.p0( %[[REVERSE8]], ptr %{{.*}}, i32 8, %[[REVERSE9]] entry: diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll index e35a4db36905..e3bba1338e1d 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-vector-reverse.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py ; This is the loop in c++ being vectorize in this file with -;experimental.vector.reverse +;vector.reverse ; #pragma clang loop vectorize_width(8, scalable) interleave_count(2) ; for (int i = N-1; i >= 0; --i) ; a[i] = b[i] + 1.0; diff --git a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll index 126ceac7325a..61105e51cb94 100644 --- a/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll +++ b/llvm/test/Transforms/LoopVectorize/AArch64/sve-widen-phi.ll @@ -40,10 +40,10 @@ define void @widen_ptr_phi_unrolled(ptr noalias nocapture %a, ptr noalias nocapt ; CHECK-NEXT: [[TMP10:%.*]] = getelementptr i8, ptr [[TMP9]], i64 [[TMP7]] ; CHECK-NEXT: [[WIDE_VEC:%.*]] = load , ptr [[TMP8]], align 4 ; CHECK-NEXT: [[WIDE_VEC2:%.*]] = load , ptr [[TMP10]], align 4 -; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) +; CHECK-NEXT: [[STRIDED_VEC:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC]]) ; CHECK-NEXT: [[TMP11:%.*]] = extractvalue { , } [[STRIDED_VEC]], 0 ; CHECK-NEXT: [[TMP12:%.*]] = extractvalue { , } [[STRIDED_VEC]], 1 -; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = call { , } @llvm.experimental.vector.deinterleave2.nxv8i32( [[WIDE_VEC2]]) +; CHECK-NEXT: [[STRIDED_VEC3:%.*]] = call { , } @llvm.vector.deinterleave2.nxv8i32( [[WIDE_VEC2]]) ; CHECK-NEXT: [[TMP13:%.*]] = extractvalue { , } [[STRIDED_VEC3]], 0 ; CHECK-NEXT: [[TMP14:%.*]] = extractvalue { , } [[STRIDED_VEC3]], 1 ; CHECK-NEXT: [[TMP15:%.*]] = add nsw [[TMP11]], shufflevector ( insertelement ( poison, i32 1, i64 0), poison, zeroinitializer) diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll index 72d9691b2bb8..c3374fceb1fb 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; This is the loop in c++ being vectorize in this file with -;experimental.vector.reverse +;vector.reverse ; #pragma clang loop vectorize_width(4, scalable) ; for (int i = N-1; i >= 0; --i) ; a[i] = b[i] + 1.0; diff --git a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll index f2222e0a1f93..0dee4a9b8585 100644 --- a/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll +++ b/llvm/test/Transforms/LoopVectorize/RISCV/vectorize-force-tail-with-evl-reverse-load-store.ll @@ -46,9 +46,9 @@ define void @reverse_load_store(i64 %startval, ptr noalias %ptr, ptr noalias %pt ; IF-EVL-NEXT: [[TMP16:%.*]] = sub i64 1, [[TMP14]] ; IF-EVL-NEXT: [[TMP17:%.*]] = getelementptr inbounds i32, ptr [[TMP12]], i64 [[TMP15]] ; IF-EVL-NEXT: [[TMP18:%.*]] = getelementptr inbounds i32, ptr [[TMP17]], i64 [[TMP16]] -; IF-EVL-NEXT: [[REVERSE:%.*]] = call @llvm.experimental.vector.reverse.nxv4i1( [[TMP10]]) +; IF-EVL-NEXT: [[REVERSE:%.*]] = call @llvm.vector.reverse.nxv4i1( [[TMP10]]) ; IF-EVL-NEXT: [[WIDE_MASKED_LOAD:%.*]] = call @llvm.masked.load.nxv4i32.p0(ptr [[TMP18]], i32 4, [[REVERSE]], poison) -; IF-EVL-NEXT: [[REVERSE3:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[WIDE_MASKED_LOAD]]) +; IF-EVL-NEXT: [[REVERSE3:%.*]] = call @llvm.vector.reverse.nxv4i32( [[WIDE_MASKED_LOAD]]) ; IF-EVL-NEXT: [[TMP19:%.*]] = getelementptr inbounds i32, ptr [[PTR2:%.*]], i64 [[TMP11]] ; IF-EVL-NEXT: [[TMP20:%.*]] = call i64 @llvm.vscale.i64() ; IF-EVL-NEXT: [[TMP21:%.*]] = mul i64 [[TMP20]], 4 @@ -56,8 +56,8 @@ define void @reverse_load_store(i64 %startval, ptr noalias %ptr, ptr noalias %pt ; IF-EVL-NEXT: [[TMP23:%.*]] = sub i64 1, [[TMP21]] ; IF-EVL-NEXT: [[TMP24:%.*]] = getelementptr inbounds i32, ptr [[TMP19]], i64 [[TMP22]] ; IF-EVL-NEXT: [[TMP25:%.*]] = getelementptr inbounds i32, ptr [[TMP24]], i64 [[TMP23]] -; IF-EVL-NEXT: [[REVERSE4:%.*]] = call @llvm.experimental.vector.reverse.nxv4i1( [[TMP10]]) -; IF-EVL-NEXT: [[REVERSE5:%.*]] = call @llvm.experimental.vector.reverse.nxv4i32( [[REVERSE3]]) +; IF-EVL-NEXT: [[REVERSE4:%.*]] = call @llvm.vector.reverse.nxv4i1( [[TMP10]]) +; IF-EVL-NEXT: [[REVERSE5:%.*]] = call @llvm.vector.reverse.nxv4i32( [[REVERSE3]]) ; IF-EVL-NEXT: call void @llvm.masked.store.nxv4i32.p0( [[REVERSE5]], ptr [[TMP25]], i32 4, [[REVERSE4]]) ; IF-EVL-NEXT: [[INDEX_NEXT]] = add i64 [[INDEX]], [[TMP6]] ; IF-EVL-NEXT: [[TMP26:%.*]] = icmp eq i64 [[INDEX_NEXT]], [[N_VEC]] diff --git a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll index 3be31c011eaa..d64755999635 100644 --- a/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll +++ b/llvm/test/Transforms/LoopVectorize/scalable-first-order-recurrence.ll @@ -21,7 +21,7 @@ define i32 @recurrence_1(ptr nocapture readonly %a, ptr nocapture %b, i32 %n) { ; CHECK-VF4UF1: %[[INDEX:.*]] = phi i64 [ 0, %vector.ph ], [ %[[NEXT_IDX:.*]], %vector.body ] ; CHECK-VF4UF1: %[[VEC_RECUR:.*]] = phi [ %[[VEC_RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-VF4UF1: %[[LOAD]] = load , ptr -; CHECK-VF4UF1: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VEC_RECUR]], %[[LOAD]], i32 -1) +; CHECK-VF4UF1: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VEC_RECUR]], %[[LOAD]], i32 -1) ; CHECK-VF4UF1: middle.block: ; CHECK-VF4UF1: %[[VSCALE2:.*]] = call i32 @llvm.vscale.i32() ; CHECK-VF4UF1: %[[MUL2:.*]] = mul i32 %[[VSCALE2]], 4 @@ -70,7 +70,7 @@ define i32 @recurrence_2(ptr nocapture readonly %a, i32 %n) { ; CHECK-VF4UF1: vector.body: ; CHECK-VF4UF1: %[[VEC_RECUR:.*]] = phi [ %[[VEC_RECUR_INIT]], %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-VF4UF1: %[[LOAD]] = load , ptr -; CHECK-VF4UF1: %[[REVERSE:.*]] = call @llvm.experimental.vector.splice.nxv4i32( %[[VEC_RECUR]], %[[LOAD]], i32 -1) +; CHECK-VF4UF1: %[[REVERSE:.*]] = call @llvm.vector.splice.nxv4i32( %[[VEC_RECUR]], %[[LOAD]], i32 -1) ; CHECK-VF4UF1: middle.block: ; CHECK-VF4UF1: %[[VSCALE2:.*]] = call i32 @llvm.vscale.i32() ; CHECK-VF4UF1: %[[MUL2:.*]] = mul i32 %[[VSCALE2]], 4 @@ -119,7 +119,7 @@ define void @recurrence_3(ptr nocapture readonly %a, ptr nocapture %b, i32 %n, f ; CHECK-VF4UF1: vector.body: ; CHECK-VF4UF1: %vector.recur = phi [ %vector.recur.init, %vector.ph ], [ %[[L1:.*]], %vector.body ] ; CHECK-VF4UF1: %[[L1]] = load , ptr -; CHECK-VF4UF1: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i16( %vector.recur, %[[L1]], i32 -1) +; CHECK-VF4UF1: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i16( %vector.recur, %[[L1]], i32 -1) ; Check also that the casts were not moved needlessly. ; CHECK-VF4UF1: sitofp %[[L1]] to ; CHECK-VF4UF1: sitofp %[[SPLICE]] to @@ -169,8 +169,8 @@ define i64 @constant_folded_previous_value() { ; CHECK-VF4UF2-LABEL: @constant_folded_previous_value ; CHECK-VF4UF2: vector.body ; CHECK-VF4UF2: %[[VECTOR_RECUR:.*]] = phi [ %vector.recur.init, %vector.ph ], [ shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer), %vector.body ] -; CHECK-VF4UF2: %[[SPLICE1:.*]] = call @llvm.experimental.vector.splice.nxv4i64( %vector.recur, shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer), i32 -1) -; CHECK-VF4UF2: %[[SPLICE2:.*]] = call @llvm.experimental.vector.splice.nxv4i64( shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer), shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer), i32 -1) +; CHECK-VF4UF2: %[[SPLICE1:.*]] = call @llvm.vector.splice.nxv4i64( %vector.recur, shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer), i32 -1) +; CHECK-VF4UF2: %[[SPLICE2:.*]] = call @llvm.vector.splice.nxv4i64( shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer), shufflevector ( insertelement ( poison, i64 1, i64 0), poison, zeroinitializer), i32 -1) ; CHECK-VF4UF2: br i1 {{.*}}, label %middle.block, label %vector.body entry: br label %scalar.body @@ -242,7 +242,7 @@ define void @sink_after(ptr %a, ptr %b, i64 %n) { ; CHECK-VF4UF1: vector.body ; CHECK-VF4UF1: %[[VEC_RECUR:.*]] = phi [ %vector.recur.init, %vector.ph ], [ %[[LOAD:.*]], %vector.body ] ; CHECK-VF4UF1: %[[LOAD]] = load , ptr -; CHECK-VF4UF1-NEXT: %[[SPLICE:.*]] = call @llvm.experimental.vector.splice.nxv4i16( %[[VEC_RECUR]], %[[LOAD]], i32 -1) +; CHECK-VF4UF1-NEXT: %[[SPLICE:.*]] = call @llvm.vector.splice.nxv4i16( %[[VEC_RECUR]], %[[LOAD]], i32 -1) ; CHECK-VF4UF1-NEXT: sext %[[SPLICE]] to ; CHECK-VF4UF1-NEXT: sext %[[LOAD]] to entry: diff --git a/llvm/test/Verifier/invalid-splice.ll b/llvm/test/Verifier/invalid-splice.ll index d5096bdf17ca..2239386df562 100644 --- a/llvm/test/Verifier/invalid-splice.ll +++ b/llvm/test/Verifier/invalid-splice.ll @@ -2,36 +2,36 @@ ; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector define <2 x double> @splice_v2f64_idx_neg3(<2 x double> %a, <2 x double> %b) #0 { - %res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -3) + %res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 -3) ret <2 x double> %res } ; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector define @splice_nxv2f64_idx_neg3_vscale_min1( %a, %b) #0 { - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -3) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 -3) ret %res } ; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector define @splice_nxv2f64_idx_neg5_vscale_min2( %a, %b) #1 { - %res = call @llvm.experimental.vector.splice.nxv2f64( %a, %b, i32 -5) + %res = call @llvm.vector.splice.nxv2f64( %a, %b, i32 -5) ret %res } ; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector define <2 x double> @splice_v2f64_idx2(<2 x double> %a, <2 x double> %b) #0 { - %res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 2) + %res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 2) ret <2 x double> %res } ; CHECK: The splice index exceeds the range [-VL, VL-1] where VL is the known minimum number of elements in the vector define <2 x double> @splice_v2f64_idx3(<2 x double> %a, <2 x double> %b) #1 { - %res = call <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 4) + %res = call <2 x double> @llvm.vector.splice.v2f64(<2 x double> %a, <2 x double> %b, i32 4) ret <2 x double> %res } attributes #0 = { vscale_range(1,16) } attributes #1 = { vscale_range(2,16) } -declare <2 x double> @llvm.experimental.vector.splice.v2f64(<2 x double>, <2 x double>, i32) -declare @llvm.experimental.vector.splice.nxv2f64(, , i32) +declare <2 x double> @llvm.vector.splice.v2f64(<2 x double>, <2 x double>, i32) +declare @llvm.vector.splice.nxv2f64(, , i32) diff --git a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td index a52cca3c95de..759cbe6c1564 100644 --- a/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td +++ b/mlir/include/mlir/Dialect/LLVMIR/LLVMIntrinsicOps.td @@ -1060,8 +1060,8 @@ def LLVM_vector_extract }]; } -def LLVM_experimental_vector_interleave2 - : LLVM_OneResultIntrOp<"experimental.vector.interleave2", +def LLVM_vector_interleave2 + : LLVM_OneResultIntrOp<"vector.interleave2", /*overloadedResults=*/[0], /*overloadedOperands=*/[], /*traits=*/[ Pure, AllTypesMatch<["vec1", "vec2"]>, diff --git a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp index 1b9975237c69..fe6bcc1c8b66 100644 --- a/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp +++ b/mlir/lib/Conversion/VectorToLLVM/ConvertVectorToLLVM.cpp @@ -1738,7 +1738,7 @@ struct VectorInterleaveOpLowering "InterleaveOp not rank 1"); // If the result is rank 1, then this directly maps to LLVM. if (resultType.isScalable()) { - rewriter.replaceOpWithNewOp( + rewriter.replaceOpWithNewOp( interleaveOp, typeConverter->convertType(resultType), adaptor.getLhs(), adaptor.getRhs()); return success(); diff --git a/mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp b/mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp index d3751d4ba7e7..39292c4533d6 100644 --- a/mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp +++ b/mlir/lib/Dialect/ArmSME/Transforms/OuterProductFusion.cpp @@ -86,8 +86,7 @@ static Value createInterleave2Intrinsic(RewriterBase &rewriter, Location loc, auto inputType = cast(lhs.getType()); VectorType inputTypeX2 = VectorType::Builder(inputType).setDim(0, inputType.getShape()[0] * 2); - return rewriter.create( - loc, inputTypeX2, lhs, rhs); + return rewriter.create(loc, inputTypeX2, lhs, rhs); } // Fuse two 'arm_sme.outerproduct' operations that are chained via the diff --git a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir index 1712d3d745b7..439f1e920e39 100644 --- a/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir +++ b/mlir/test/Conversion/VectorToLLVM/vector-to-llvm.mlir @@ -2517,7 +2517,7 @@ func.func @vector_interleave_1d(%a: vector<8xf32>, %b: vector<8xf32>) -> vector< // CHECK-SAME: %[[LHS:.*]]: vector<[4]xi32>, %[[RHS:.*]]: vector<[4]xi32>) func.func @vector_interleave_1d_scalable(%a: vector<[4]xi32>, %b: vector<[4]xi32>) -> vector<[8]xi32> { - // CHECK: %[[ZIP:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[LHS]], %[[RHS]]) : (vector<[4]xi32>, vector<[4]xi32>) -> vector<[8]xi32> + // CHECK: %[[ZIP:.*]] = "llvm.intr.vector.interleave2"(%[[LHS]], %[[RHS]]) : (vector<[4]xi32>, vector<[4]xi32>) -> vector<[8]xi32> // CHECK: return %[[ZIP]] %0 = vector.interleave %a, %b : vector<[4]xi32> return %0 : vector<[8]xi32> @@ -2541,7 +2541,7 @@ func.func @vector_interleave_2d(%a: vector<2x3xi8>, %b: vector<2x3xi8>) -> vecto // CHECK-SAME: %[[LHS:.*]]: vector<2x[8]xi16>, %[[RHS:.*]]: vector<2x[8]xi16>) func.func @vector_interleave_2d_scalable(%a: vector<2x[8]xi16>, %b: vector<2x[8]xi16>) -> vector<2x[16]xi16> { - // CHECK: llvm.intr.experimental.vector.interleave2 + // CHECK: llvm.intr.vector.interleave2 // CHECK-NOT: vector.interleave {{.*}} : vector<2x[8]xi16> %0 = vector.interleave %a, %b : vector<2x[8]xi16> return %0 : vector<2x[16]xi16> diff --git a/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir b/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir index de9de86003e6..01f54a4cf186 100644 --- a/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir +++ b/mlir/test/Dialect/ArmSME/outer-product-fusion.mlir @@ -4,10 +4,10 @@ // CHECK-SAME: %[[A0:.*]]: vector<[4]xf16>, %[[B0:.*]]: vector<[4]xf16>, %[[A1:.*]]: vector<[4]xf16>, %[[B1:.*]]: vector<[4]xf16>, // CHECK-SAME: %[[A0_MASK:.*]]: vector<[4]xi1>, %[[B0_MASK:.*]]: vector<[4]xi1>, %[[A1_MASK:.*]]: vector<[4]xi1>, %[[B1_MASK:.*]]: vector<[4]xi1> // CHECK-DAG: %[[ACC:.*]] = arith.constant dense<0.000000e+00> : vector<[4]x[4]xf32> -// CHECK-DAG: %[[LHS:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[A0]], %[[A1]]) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> -// CHECK-DAG: %[[RHS:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[B0]], %[[B1]]) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> -// CHECK-DAG: %[[LHS_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[A0_MASK]], %[[A1_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> -// CHECK-DAG: %[[RHS_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[B0_MASK]], %[[B1_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> +// CHECK-DAG: %[[LHS:.*]] = "llvm.intr.vector.interleave2"(%[[A0]], %[[A1]]) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> +// CHECK-DAG: %[[RHS:.*]] = "llvm.intr.vector.interleave2"(%[[B0]], %[[B1]]) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> +// CHECK-DAG: %[[LHS_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[A0_MASK]], %[[A1_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> +// CHECK-DAG: %[[RHS_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[B0_MASK]], %[[B1_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> // CHECK-DAG: arm_sme.fmopa_2way %[[LHS]], %[[RHS]] acc(%[[ACC]]) masks(%[[LHS_MASK]], %[[RHS_MASK]]) : vector<[8]xf16>, vector<[8]xf16> into vector<[4]x[4]xf32> func.func @outerproduct_add_widening_2way_f16f16f32( %a0 : vector<[4]xf16>, %b0 : vector<[4]xf16>, @@ -225,18 +225,18 @@ func.func @outerproduct_sub_widening_2way_unsigned_i16i16i32( // CHECK-SAME: %[[A2_MASK:[a-z0-9]+]]: vector<[4]xi1>, %[[B2_MASK:[a-z0-9]+]]: vector<[4]xi1>, // CHECK-SAME: %[[A3_MASK:[a-z0-9]+]]: vector<[4]xi1>, %[[B3_MASK:[a-z0-9]+]]: vector<[4]xi1> // CHECK-DAG: %[[ACC:.*]] = arith.constant dense<0> : vector<[4]x[4]xi32> -// CHECK-DAG: %[[LHS0:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[A0]], %[[A2]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> -// CHECK-DAG: %[[LHS1:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[A1]], %[[A3]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> -// CHECK-DAG: %[[RHS0:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[B0]], %[[B2]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> -// CHECK-DAG: %[[RHS1:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[B1]], %[[B3]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> -// CHECK-DAG: %[[LHS:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[LHS0]], %[[LHS1]]) : (vector<[8]xi8>, vector<[8]xi8>) -> vector<[16]xi8> -// CHECK-DAG: %[[RHS:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[RHS0]], %[[RHS1]]) : (vector<[8]xi8>, vector<[8]xi8>) -> vector<[16]xi8> -// CHECK-DAG: %[[LHS0_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[A0_MASK]], %[[A2_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> -// CHECK-DAG: %[[LHS1_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[A1_MASK]], %[[A3_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> -// CHECK-DAG: %[[RHS0_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[B0_MASK]], %[[B2_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> -// CHECK-DAG: %[[RHS1_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[B1_MASK]], %[[B3_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> -// CHECK-DAG: %[[LHS_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[LHS0_MASK]], %[[LHS1_MASK]]) : (vector<[8]xi1>, vector<[8]xi1>) -> vector<[16]xi1> -// CHECK-DAG: %[[RHS_MASK:.*]] = "llvm.intr.experimental.vector.interleave2"(%[[RHS0_MASK]], %[[RHS1_MASK]]) : (vector<[8]xi1>, vector<[8]xi1>) -> vector<[16]xi1> +// CHECK-DAG: %[[LHS0:.*]] = "llvm.intr.vector.interleave2"(%[[A0]], %[[A2]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> +// CHECK-DAG: %[[LHS1:.*]] = "llvm.intr.vector.interleave2"(%[[A1]], %[[A3]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> +// CHECK-DAG: %[[RHS0:.*]] = "llvm.intr.vector.interleave2"(%[[B0]], %[[B2]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> +// CHECK-DAG: %[[RHS1:.*]] = "llvm.intr.vector.interleave2"(%[[B1]], %[[B3]]) : (vector<[4]xi8>, vector<[4]xi8>) -> vector<[8]xi8> +// CHECK-DAG: %[[LHS:.*]] = "llvm.intr.vector.interleave2"(%[[LHS0]], %[[LHS1]]) : (vector<[8]xi8>, vector<[8]xi8>) -> vector<[16]xi8> +// CHECK-DAG: %[[RHS:.*]] = "llvm.intr.vector.interleave2"(%[[RHS0]], %[[RHS1]]) : (vector<[8]xi8>, vector<[8]xi8>) -> vector<[16]xi8> +// CHECK-DAG: %[[LHS0_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[A0_MASK]], %[[A2_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> +// CHECK-DAG: %[[LHS1_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[A1_MASK]], %[[A3_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> +// CHECK-DAG: %[[RHS0_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[B0_MASK]], %[[B2_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> +// CHECK-DAG: %[[RHS1_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[B1_MASK]], %[[B3_MASK]]) : (vector<[4]xi1>, vector<[4]xi1>) -> vector<[8]xi1> +// CHECK-DAG: %[[LHS_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[LHS0_MASK]], %[[LHS1_MASK]]) : (vector<[8]xi1>, vector<[8]xi1>) -> vector<[16]xi1> +// CHECK-DAG: %[[RHS_MASK:.*]] = "llvm.intr.vector.interleave2"(%[[RHS0_MASK]], %[[RHS1_MASK]]) : (vector<[8]xi1>, vector<[8]xi1>) -> vector<[16]xi1> // CHECK-DAG: arm_sme.smopa_4way %[[LHS]], %[[RHS]] acc(%[[ACC]]) masks(%[[LHS_MASK]], %[[RHS_MASK]]) : vector<[16]xi8>, vector<[16]xi8> into vector<[4]x[4]xi32> func.func @outerproduct_add_widening_4way_signed_i8i8i32( %a0 : vector<[4]xi8>, %b0 : vector<[4]xi8>, diff --git a/mlir/test/Dialect/LLVMIR/invalid.mlir b/mlir/test/Dialect/LLVMIR/invalid.mlir index de1ab9db8e8d..0914f0023210 100644 --- a/mlir/test/Dialect/LLVMIR/invalid.mlir +++ b/mlir/test/Dialect/LLVMIR/invalid.mlir @@ -1221,17 +1221,17 @@ func.func @extract_scalable_from_fixed_length_vector(%arg0 : vector<16xf32>) { // ----- -func.func @experimental_vector_interleave2_bad_type0(%vec1: vector<[2]xf16>, %vec2 : vector<[4]xf16>) { +func.func @vector_interleave2_bad_type0(%vec1: vector<[2]xf16>, %vec2 : vector<[4]xf16>) { // expected-error@+1 {{op failed to verify that all of {vec1, vec2} have same type}} - %0 = "llvm.intr.experimental.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[4]xf16>) -> vector<[8]xf16> + %0 = "llvm.intr.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[4]xf16>) -> vector<[8]xf16> return } // ----- -func.func @experimental_vector_interleave2_bad_type1(%vec1: vector<[2]xf16>, %vec2 : vector<[2]xf16>) { +func.func @vector_interleave2_bad_type1(%vec1: vector<[2]xf16>, %vec2 : vector<[2]xf16>) { // expected-error@+1 {{op failed to verify that result has twice as many elements as 'vec1'}} - %0 = "llvm.intr.experimental.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[2]xf16>) -> vector<[8]xf16> + %0 = "llvm.intr.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[2]xf16>) -> vector<[8]xf16> return } @@ -1239,9 +1239,9 @@ func.func @experimental_vector_interleave2_bad_type1(%vec1: vector<[2]xf16>, %ve /// result vector type is not scalable. -func.func @experimental_vector_interleave2_bad_type2(%vec1: vector<[2]xf16>, %vec2 : vector<[2]xf16>) { +func.func @vector_interleave2_bad_type2(%vec1: vector<[2]xf16>, %vec2 : vector<[2]xf16>) { // expected-error@+1 {{op failed to verify that result has twice as many elements as 'vec1'}} - %0 = "llvm.intr.experimental.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[2]xf16>) -> vector<4xf16> + %0 = "llvm.intr.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[2]xf16>) -> vector<4xf16> return } @@ -1250,9 +1250,9 @@ func.func @experimental_vector_interleave2_bad_type2(%vec1: vector<[2]xf16>, %ve /// element type doesn't match. -func.func @experimental_vector_interleave2_bad_type3(%vec1: vector<[2]xf16>, %vec2 : vector<[2]xf16>) { +func.func @vector_interleave2_bad_type3(%vec1: vector<[2]xf16>, %vec2 : vector<[2]xf16>) { // expected-error@+1 {{op failed to verify that result has twice as many elements as 'vec1'}} - %0 = "llvm.intr.experimental.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[2]xf16>) -> vector<[4]xf32> + %0 = "llvm.intr.vector.interleave2"(%vec1, %vec2) : (vector<[2]xf16>, vector<[2]xf16>) -> vector<[4]xf32> return } diff --git a/mlir/test/Dialect/LLVMIR/roundtrip.mlir b/mlir/test/Dialect/LLVMIR/roundtrip.mlir index 31acf2b95e46..3b94db389f54 100644 --- a/mlir/test/Dialect/LLVMIR/roundtrip.mlir +++ b/mlir/test/Dialect/LLVMIR/roundtrip.mlir @@ -342,10 +342,10 @@ func.func @mixed_vect(%arg0: vector<8xf32>, %arg1: vector<4xf32>, %arg2: vector< return } -// CHECK-LABEL: @experimental_vector_interleave2 -func.func @experimental_vector_interleave2(%vec1: vector<[4]xf16>, %vec2 : vector<[4]xf16>) { - // CHECK: = "llvm.intr.experimental.vector.interleave2"({{.*}}) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> - %0 = "llvm.intr.experimental.vector.interleave2"(%vec1, %vec2) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> +// CHECK-LABEL: @vector_interleave2 +func.func @vector_interleave2(%vec1: vector<[4]xf16>, %vec2 : vector<[4]xf16>) { + // CHECK: = "llvm.intr.vector.interleave2"({{.*}}) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> + %0 = "llvm.intr.vector.interleave2"(%vec1, %vec2) : (vector<[4]xf16>, vector<[4]xf16>) -> vector<[8]xf16> return } -- GitLab From d30f6bc5cd9579204864c944f127011be70b2c74 Mon Sep 17 00:00:00 2001 From: Nikolas Klauser Date: Mon, 29 Apr 2024 11:21:28 +0200 Subject: [PATCH 197/301] [libc++][NFC] Refactor __libcpp_datasizeof to be a variable template (#87769) This decreases memory consumption and compiles times slightly and removes a bit of boilderplate. --- .../include/__string/constexpr_c_functions.h | 2 +- libcxx/include/__type_traits/datasizeof.h | 47 +++++++++---------- .../type_traits/datasizeof.compile.pass.cpp | 14 +++--- .../no_unique_address.compile.pass.cpp | 22 ++++----- .../no_unique_address.compile.pass.cpp | 18 +++---- .../array/size_and_alignment.compile.pass.cpp | 2 +- 6 files changed, 52 insertions(+), 53 deletions(-) diff --git a/libcxx/include/__string/constexpr_c_functions.h b/libcxx/include/__string/constexpr_c_functions.h index 72c6ce69b60b..4da8542e3807 100644 --- a/libcxx/include/__string/constexpr_c_functions.h +++ b/libcxx/include/__string/constexpr_c_functions.h @@ -224,7 +224,7 @@ __constexpr_memmove(_Tp* __dest, _Up* __src, __element_count __n) { std::__assign_trivially_copyable(__dest[__i], __src[__i]); } } else if (__count > 0) { - ::__builtin_memmove(__dest, __src, (__count - 1) * sizeof(_Tp) + __libcpp_datasizeof<_Tp>::value); + ::__builtin_memmove(__dest, __src, (__count - 1) * sizeof(_Tp) + __datasizeof_v<_Tp>); } return __dest; } diff --git a/libcxx/include/__type_traits/datasizeof.h b/libcxx/include/__type_traits/datasizeof.h index 3a8b15160107..54fde242ebcd 100644 --- a/libcxx/include/__type_traits/datasizeof.h +++ b/libcxx/include/__type_traits/datasizeof.h @@ -26,39 +26,38 @@ _LIBCPP_BEGIN_NAMESPACE_STD -template -struct __libcpp_datasizeof { #if __has_extension(datasizeof) - static const size_t value = __datasizeof(_Tp); +template +inline const size_t __datasizeof_v = __datasizeof(_Tp); #else // NOLINTNEXTLINE(readability-redundant-preprocessor) This is https://llvm.org/PR64825 # if __has_cpp_attribute(__no_unique_address__) - template - struct _FirstPaddingByte { - [[__no_unique_address__]] _Tp __v_; - char __first_padding_byte_; - }; +template +struct _FirstPaddingByte { + [[__no_unique_address__]] _Tp __v_; + char __first_padding_byte_; +}; # else - template ::value || !is_class<_Tp>::value> - struct _FirstPaddingByte : _Tp { - char __first_padding_byte_; - }; +template ::value || !is_class<_Tp>::value> +struct _FirstPaddingByte : _Tp { + char __first_padding_byte_; +}; - template <> - struct _FirstPaddingByte { - _Tp __v_; - char __first_padding_byte_; - }; +template +struct _FirstPaddingByte<_Tp, true> { + _Tp __v_; + char __first_padding_byte_; +}; # endif // __has_cpp_attribute(__no_unique_address__) - // _FirstPaddingByte<> is sometimes non-standard layout. Using `offsetof` is UB in that case, but GCC and Clang allow - // the use as an extension. - _LIBCPP_DIAGNOSTIC_PUSH - _LIBCPP_CLANG_DIAGNOSTIC_IGNORED("-Winvalid-offsetof") - static const size_t value = offsetof(_FirstPaddingByte<>, __first_padding_byte_); - _LIBCPP_DIAGNOSTIC_POP +// _FirstPaddingByte<> is sometimes non-standard layout. Using `offsetof` is UB in that case, but GCC and Clang allow +// the use as an extension. +_LIBCPP_DIAGNOSTIC_PUSH +_LIBCPP_CLANG_DIAGNOSTIC_IGNORED("-Winvalid-offsetof") +template +inline const size_t __datasizeof_v = offsetof(_FirstPaddingByte<_Tp>, __first_padding_byte_); +_LIBCPP_DIAGNOSTIC_POP #endif // __has_extension(datasizeof) -}; _LIBCPP_END_NAMESPACE_STD diff --git a/libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp b/libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp index 881b0bd85190..03dd0f6eac53 100644 --- a/libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp +++ b/libcxx/test/libcxx/type_traits/datasizeof.compile.pass.cpp @@ -9,10 +9,10 @@ #include <__type_traits/datasizeof.h> #include -static_assert(std::__libcpp_datasizeof::value == 1, ""); -static_assert(std::__libcpp_datasizeof::value == 2, ""); -static_assert(std::__libcpp_datasizeof::value == 4, ""); -static_assert(std::__libcpp_datasizeof::value == 8, ""); +static_assert(std::__datasizeof_v == 1, ""); +static_assert(std::__datasizeof_v == 2, ""); +static_assert(std::__datasizeof_v == 4, ""); +static_assert(std::__datasizeof_v == 8, ""); struct OneBytePadding { OneBytePadding() {} @@ -22,9 +22,9 @@ struct OneBytePadding { }; #if defined(_WIN32) && !defined(__MINGW32__) -static_assert(std::__libcpp_datasizeof::value == 4, ""); +static_assert(std::__datasizeof_v == 4, ""); #else -static_assert(std::__libcpp_datasizeof::value == 3, ""); +static_assert(std::__datasizeof_v == 3, ""); #endif struct InBetweenPadding { @@ -35,4 +35,4 @@ struct InBetweenPadding { std::int16_t c; }; -static_assert(std::__libcpp_datasizeof::value == 8, ""); +static_assert(std::__datasizeof_v == 8, ""); diff --git a/libcxx/test/libcxx/utilities/expected/expected.expected/no_unique_address.compile.pass.cpp b/libcxx/test/libcxx/utilities/expected/expected.expected/no_unique_address.compile.pass.cpp index cf1909b92873..580c0f4ae10c 100644 --- a/libcxx/test/libcxx/utilities/expected/expected.expected/no_unique_address.compile.pass.cpp +++ b/libcxx/test/libcxx/utilities/expected/expected.expected/no_unique_address.compile.pass.cpp @@ -47,28 +47,28 @@ static_assert(sizeof(std::expected) == sizeof(B)); // Check that `expected`'s datasize is large enough for the parameter type(s). static_assert(sizeof(std::expected) == - std::__libcpp_datasizeof>::value); + std::__datasizeof_v>); static_assert(sizeof(std::expected) == - std::__libcpp_datasizeof>::value); + std::__datasizeof_v>); // In this case, there should be tail padding in the `expected` because `A` // itself does _not_ have tail padding. -static_assert(sizeof(std::expected) > std::__libcpp_datasizeof>::value); +static_assert(sizeof(std::expected) > std::__datasizeof_v>); // Test with some real types. static_assert(sizeof(std::expected, int>) == 8); -static_assert(std::__libcpp_datasizeof, int>>::value == 8); +static_assert(std::__datasizeof_v, int>> == 8); static_assert(sizeof(std::expected>) == 8); -static_assert(std::__libcpp_datasizeof>>::value == 8); +static_assert(std::__datasizeof_v>> == 8); static_assert(sizeof(std::expected) == 8); -static_assert(std::__libcpp_datasizeof>::value == 5); +static_assert(std::__datasizeof_v> == 5); // clang-format off -static_assert(std::__libcpp_datasizeof::value == 4); -static_assert(std::__libcpp_datasizeof>::value == 5); -static_assert(std::__libcpp_datasizeof, int>>::value == 8); -static_assert(std::__libcpp_datasizeof, int>, int>>::value == 9); -static_assert(std::__libcpp_datasizeof, int>, int>, int>>::value == 12); +static_assert(std::__datasizeof_v == 4); +static_assert(std::__datasizeof_v> == 5); +static_assert(std::__datasizeof_v, int>> == 8); +static_assert(std::__datasizeof_v, int>, int>> == 9); +static_assert(std::__datasizeof_v, int>, int>, int>> == 12); // clang-format on diff --git a/libcxx/test/libcxx/utilities/expected/expected.void/no_unique_address.compile.pass.cpp b/libcxx/test/libcxx/utilities/expected/expected.void/no_unique_address.compile.pass.cpp index fdee8b71e5d9..27da03c54ac4 100644 --- a/libcxx/test/libcxx/utilities/expected/expected.void/no_unique_address.compile.pass.cpp +++ b/libcxx/test/libcxx/utilities/expected/expected.void/no_unique_address.compile.pass.cpp @@ -45,23 +45,23 @@ static_assert(sizeof(std::expected) == sizeof(B)); // Check that `expected`'s datasize is large enough for the parameter type(s). static_assert(sizeof(std::expected) == - std::__libcpp_datasizeof>::value); + std::__datasizeof_v>); // In this case, there should be tail padding in the `expected` because `A` // itself does _not_ have tail padding. -static_assert(sizeof(std::expected) > std::__libcpp_datasizeof>::value); +static_assert(sizeof(std::expected) > std::__datasizeof_v>); // Test with some real types. static_assert(sizeof(std::expected>) == 8); -static_assert(std::__libcpp_datasizeof>>::value == 8); +static_assert(std::__datasizeof_v>> == 8); static_assert(sizeof(std::expected) == 8); -static_assert(std::__libcpp_datasizeof>::value == 5); +static_assert(std::__datasizeof_v> == 5); // clang-format off -static_assert(std::__libcpp_datasizeof::value == 4); -static_assert(std::__libcpp_datasizeof>::value == 5); -static_assert(std::__libcpp_datasizeof>>::value == 8); -static_assert(std::__libcpp_datasizeof>>>::value == 9); -static_assert(std::__libcpp_datasizeof>>>>::value == 12); +static_assert(std::__datasizeof_v == 4); +static_assert(std::__datasizeof_v> == 5); +static_assert(std::__datasizeof_v>> == 8); +static_assert(std::__datasizeof_v>>> == 9); +static_assert(std::__datasizeof_v>>>> == 12); // clang-format on diff --git a/libcxx/test/std/containers/sequences/array/size_and_alignment.compile.pass.cpp b/libcxx/test/std/containers/sequences/array/size_and_alignment.compile.pass.cpp index 209e24964807..7ba56577d1bb 100644 --- a/libcxx/test/std/containers/sequences/array/size_and_alignment.compile.pass.cpp +++ b/libcxx/test/std/containers/sequences/array/size_and_alignment.compile.pass.cpp @@ -46,7 +46,7 @@ void test_type() { static_assert(!std::is_empty::value, ""); // Make sure empty arrays don't have padding bytes - LIBCPP_STATIC_ASSERT(std::__libcpp_datasizeof::value == sizeof(Array), ""); + LIBCPP_STATIC_ASSERT(std::__datasizeof_v == sizeof(Array), ""); } { -- GitLab From 75d52f5797c367488c5623fefb02b32dea25fbb1 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 29 Apr 2024 10:36:11 +0100 Subject: [PATCH 198/301] [X86] matchTruncateWithPACK - merge equivalent calls to getSizeInBits/getScalarSizeInBits. NFC. --- llvm/lib/Target/X86/X86ISelLowering.cpp | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/llvm/lib/Target/X86/X86ISelLowering.cpp b/llvm/lib/Target/X86/X86ISelLowering.cpp index 82d3859225fd..3dca306a7642 100644 --- a/llvm/lib/Target/X86/X86ISelLowering.cpp +++ b/llvm/lib/Target/X86/X86ISelLowering.cpp @@ -20394,14 +20394,16 @@ static SDValue matchTruncateWithPACK(unsigned &PackOpcode, EVT DstVT, EVT SrcVT = In.getValueType(); EVT DstSVT = DstVT.getVectorElementType(); EVT SrcSVT = SrcVT.getVectorElementType(); + unsigned NumDstEltBits = DstSVT.getSizeInBits(); + unsigned NumSrcEltBits = SrcSVT.getSizeInBits(); // Check we have a truncation suited for PACKSS/PACKUS. if (!((SrcSVT == MVT::i16 || SrcSVT == MVT::i32 || SrcSVT == MVT::i64) && (DstSVT == MVT::i8 || DstSVT == MVT::i16 || DstSVT == MVT::i32))) return SDValue(); - assert(SrcSVT.getSizeInBits() > DstSVT.getSizeInBits() && "Bad truncation"); - unsigned NumStages = Log2_32(SrcSVT.getSizeInBits() / DstSVT.getSizeInBits()); + assert(NumSrcEltBits > NumDstEltBits && "Bad truncation"); + unsigned NumStages = Log2_32(NumSrcEltBits / NumDstEltBits); // Truncation from 128-bit to vXi32 can be better handled with PSHUFD. // Truncation to sub-64-bit vXi16 can be better handled with PSHUFD/PSHUFLW. @@ -20422,8 +20424,7 @@ static SDValue matchTruncateWithPACK(unsigned &PackOpcode, EVT DstVT, if (Subtarget.hasAVX512() && NumStages > 1) return SDValue(); - unsigned NumSrcEltBits = SrcVT.getScalarSizeInBits(); - unsigned NumPackedSignBits = std::min(DstSVT.getSizeInBits(), 16); + unsigned NumPackedSignBits = std::min(NumDstEltBits, 16); unsigned NumPackedZeroBits = Subtarget.hasSSE41() ? NumPackedSignBits : 8; // Truncate with PACKUS if we are truncating a vector with leading zero @@ -20445,7 +20446,7 @@ static SDValue matchTruncateWithPACK(unsigned &PackOpcode, EVT DstVT, // a sign splat (or AVX512 VPSRAQ support). ComputeNumSignBits struggles to // see through BITCASTs later on and combines/simplifications can't then use // it. - if (DstSVT == MVT::i32 && NumSignBits != SrcSVT.getSizeInBits() && + if (DstSVT == MVT::i32 && NumSignBits != NumSrcEltBits && !Subtarget.hasAVX512()) return SDValue(); -- GitLab From bf57d2e57c3e708a32c1f8a273b0e3465078d7b5 Mon Sep 17 00:00:00 2001 From: chuongg3 Date: Mon, 29 Apr 2024 10:53:30 +0100 Subject: [PATCH 199/301] [AArch64][GlobalISel] Enable computeNumSignBits for G_XOR, G_AND, G_OR (#89896) --- .../lib/CodeGen/GlobalISel/GISelKnownBits.cpp | 14 +++ .../CodeGen/GlobalISel/KnownBitsTest.cpp | 114 ++++++++++++++++++ 2 files changed, 128 insertions(+) diff --git a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp index 51ab7b6262c6..529e50c8ebe0 100644 --- a/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp +++ b/llvm/lib/CodeGen/GlobalISel/GISelKnownBits.cpp @@ -694,6 +694,20 @@ unsigned GISelKnownBits::computeNumSignBits(Register R, const MachineMemOperand *MMO = *MI.memoperands_begin(); return TyBits - MMO->getSizeInBits().getValue(); } + case TargetOpcode::G_AND: + case TargetOpcode::G_OR: + case TargetOpcode::G_XOR: { + Register Src1 = MI.getOperand(1).getReg(); + unsigned Src1NumSignBits = + computeNumSignBits(Src1, DemandedElts, Depth + 1); + if (Src1NumSignBits != 1) { + Register Src2 = MI.getOperand(2).getReg(); + unsigned Src2NumSignBits = + computeNumSignBits(Src2, DemandedElts, Depth + 1); + FirstAnswer = std::min(Src1NumSignBits, Src2NumSignBits); + } + break; + } case TargetOpcode::G_TRUNC: { Register Src = MI.getOperand(1).getReg(); LLT SrcTy = MRI.getType(Src); diff --git a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp index ef80eed8d180..34a36ba68d7c 100644 --- a/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp +++ b/llvm/unittests/CodeGen/GlobalISel/KnownBitsTest.cpp @@ -745,6 +745,120 @@ TEST_F(AArch64GISelMITest, TestNumSignBitsConstant) { EXPECT_EQ(3u, Info.computeNumSignBits(CopyRegNeg32)); } +TEST_F(AArch64GISelMITest, TestNumSignBitsXOR) { + StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n" + " %cn1:_(s8) = G_CONSTANT i8 -1\n" + " %c127:_(s8) = G_CONSTANT i8 127\n" + " %c32:_(s8) = G_CONSTANT i8 32\n" + " %cn32:_(s8) = G_CONSTANT i8 -32\n" + + " %xor1:_(s8) = G_XOR %c1, %cn1\n" + " %Copy1:_(s8) = COPY %xor1\n" + + " %xor2:_(s8) = G_XOR %c1, %c32\n" + " %Copy2:_(s8) = COPY %xor2\n" + + " %xor3:_(s8) = G_XOR %c32, %c127\n" + " %Copy3:_(s8) = COPY %xor3\n" + + " %xor4:_(s8) = G_XOR %cn32, %c127\n" + " %Copy4:_(s8) = COPY %xor4\n" + + " %xor5:_(s8) = G_XOR %c127, %cn32\n" + " %Copy5:_(s8) = COPY %xor5\n"; + setUp(MIRString); + if (!TM) + GTEST_SKIP(); + Register Copy1 = Copies[Copies.size() - 5]; + Register Copy2 = Copies[Copies.size() - 4]; + Register Copy3 = Copies[Copies.size() - 3]; + Register Copy4 = Copies[Copies.size() - 2]; + Register Copy5 = Copies[Copies.size() - 1]; + + GISelKnownBits Info(*MF); + EXPECT_EQ(7u, Info.computeNumSignBits(Copy1)); + EXPECT_EQ(2u, Info.computeNumSignBits(Copy2)); + EXPECT_EQ(1u, Info.computeNumSignBits(Copy3)); + EXPECT_EQ(1u, Info.computeNumSignBits(Copy4)); + EXPECT_EQ(1u, Info.computeNumSignBits(Copy5)); +} + +TEST_F(AArch64GISelMITest, TestNumSignBitsOR) { + StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n" + " %cn1:_(s8) = G_CONSTANT i8 -1\n" + " %c127:_(s8) = G_CONSTANT i8 127\n" + " %c32:_(s8) = G_CONSTANT i8 32\n" + " %cn32:_(s8) = G_CONSTANT i8 -32\n" + + " %or1:_(s8) = G_OR %c1, %cn1\n" + " %Copy1:_(s8) = COPY %or1\n" + + " %or2:_(s8) = G_OR %c1, %c32\n" + " %Copy2:_(s8) = COPY %or2\n" + + " %or3:_(s8) = G_OR %c32, %c127\n" + " %Copy3:_(s8) = COPY %or3\n" + + " %or4:_(s8) = G_OR %cn32, %c127\n" + " %Copy4:_(s8) = COPY %or4\n" + + " %or5:_(s8) = G_OR %c127, %cn32\n" + " %Copy5:_(s8) = COPY %or5\n"; + setUp(MIRString); + if (!TM) + GTEST_SKIP(); + Register Copy1 = Copies[Copies.size() - 5]; + Register Copy2 = Copies[Copies.size() - 4]; + Register Copy3 = Copies[Copies.size() - 3]; + Register Copy4 = Copies[Copies.size() - 2]; + Register Copy5 = Copies[Copies.size() - 1]; + + GISelKnownBits Info(*MF); + EXPECT_EQ(8u, Info.computeNumSignBits(Copy1)); + EXPECT_EQ(2u, Info.computeNumSignBits(Copy2)); + EXPECT_EQ(1u, Info.computeNumSignBits(Copy3)); + EXPECT_EQ(8u, Info.computeNumSignBits(Copy4)); + EXPECT_EQ(8u, Info.computeNumSignBits(Copy5)); +} + +TEST_F(AArch64GISelMITest, TestNumSignBitsAND) { + StringRef MIRString = " %c1:_(s8) = G_CONSTANT i8 1\n" + " %cn1:_(s8) = G_CONSTANT i8 -1\n" + " %c127:_(s8) = G_CONSTANT i8 127\n" + " %c32:_(s8) = G_CONSTANT i8 32\n" + " %cn32:_(s8) = G_CONSTANT i8 -32\n" + + " %and1:_(s8) = G_AND %c1, %cn1\n" + " %Copy1:_(s8) = COPY %and1\n" + + " %and2:_(s8) = G_AND %c1, %c32\n" + " %Copy2:_(s8) = COPY %and2\n" + + " %and3:_(s8) = G_AND %c32, %c127\n" + " %Copy3:_(s8) = COPY %and3\n" + + " %and4:_(s8) = G_AND %cn32, %c127\n" + " %Copy4:_(s8) = COPY %and4\n" + + " %and5:_(s8) = G_AND %c127, %cn32\n" + " %Copy5:_(s8) = COPY %and5\n"; + setUp(MIRString); + if (!TM) + GTEST_SKIP(); + Register Copy1 = Copies[Copies.size() - 5]; + Register Copy2 = Copies[Copies.size() - 4]; + Register Copy3 = Copies[Copies.size() - 3]; + Register Copy4 = Copies[Copies.size() - 2]; + Register Copy5 = Copies[Copies.size() - 1]; + + GISelKnownBits Info(*MF); + EXPECT_EQ(7u, Info.computeNumSignBits(Copy1)); + EXPECT_EQ(8u, Info.computeNumSignBits(Copy2)); + EXPECT_EQ(2u, Info.computeNumSignBits(Copy3)); + EXPECT_EQ(1u, Info.computeNumSignBits(Copy4)); + EXPECT_EQ(1u, Info.computeNumSignBits(Copy5)); +} + TEST_F(AArch64GISelMITest, TestNumSignBitsSext) { StringRef MIRString = " %3:_(p0) = G_IMPLICIT_DEF\n" " %4:_(s8) = G_LOAD %3 :: (load (s8))\n" -- GitLab From 0edb5c3be56a07ddaad26ffbb270b4aa2308d03a Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 29 Apr 2024 11:02:16 +0100 Subject: [PATCH 200/301] Revert "[flang] Improve debug info for functions." (#90444) Reverts llvm/llvm-project#90083 due to a test suite failure: https://lab.llvm.org/buildbot/#/builders/184/builds/11961 ``` flang-new: ../llvm/mlir/lib/IR/Types.cpp:126: unsigned int mlir::Type::getIntOrFloatBitWidth() const: Assertion `isIntOrFloat() && "only integers and floats have a bitwidth"' failed. ``` --- .../lib/Optimizer/Transforms/AddDebugInfo.cpp | 36 +++-------- flang/lib/Optimizer/Transforms/CMakeLists.txt | 1 - .../Transforms/DebugTypeGenerator.cpp | 63 ------------------- .../Optimizer/Transforms/DebugTypeGenerator.h | 40 ------------ flang/test/Transforms/debug-fn-info.f90 | 43 ------------- .../Transforms/debug-line-table-inc-file.fir | 2 +- 6 files changed, 11 insertions(+), 174 deletions(-) delete mode 100644 flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp delete mode 100644 flang/lib/Optimizer/Transforms/DebugTypeGenerator.h delete mode 100644 flang/test/Transforms/debug-fn-info.f90 diff --git a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp index 5108469cb6c8..18d98a11ef3c 100644 --- a/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp +++ b/flang/lib/Optimizer/Transforms/AddDebugInfo.cpp @@ -11,7 +11,6 @@ /// This pass populates some debug information for the module and functions. //===----------------------------------------------------------------------===// -#include "DebugTypeGenerator.h" #include "flang/Common/Version.h" #include "flang/Optimizer/Builder/FIRBuilder.h" #include "flang/Optimizer/Builder/Todo.h" @@ -107,27 +106,14 @@ void AddDebugInfoPass::runOnOperation() { filePath = llvm::sys::path::parent_path(funcLoc.getFilename().getValue()); } - mlir::StringAttr fullName = - mlir::StringAttr::get(context, funcOp.getName()); - auto result = fir::NameUniquer::deconstruct(funcOp.getName()); mlir::StringAttr funcName = - mlir::StringAttr::get(context, result.second.name); - - llvm::SmallVector types; - fir::DebugTypeGenerator typeGen(module); - for (auto resTy : funcOp.getResultTypes()) { - auto tyAttr = - typeGen.convertType(resTy, fileAttr, cuAttr, funcOp.getLoc()); - types.push_back(tyAttr); - } - for (auto inTy : funcOp.getArgumentTypes()) { - auto tyAttr = typeGen.convertType(fir::unwrapRefType(inTy), fileAttr, - cuAttr, funcOp.getLoc()); - types.push_back(tyAttr); - } - + mlir::StringAttr::get(context, funcOp.getName()); + mlir::LLVM::DIBasicTypeAttr bT = mlir::LLVM::DIBasicTypeAttr::get( + context, llvm::dwarf::DW_TAG_base_type, "void", /*sizeInBits=*/0, + /*encoding=*/1); + // FIXME: Provide proper type for subroutine mlir::LLVM::DISubroutineTypeAttr subTypeAttr = - mlir::LLVM::DISubroutineTypeAttr::get(context, CC, types); + mlir::LLVM::DISubroutineTypeAttr::get(context, CC, {bT, bT}); mlir::LLVM::DIFileAttr funcFileAttr = mlir::LLVM::DIFileAttr::get(context, fileName, filePath); @@ -144,13 +130,11 @@ void AddDebugInfoPass::runOnOperation() { subprogramFlags = subprogramFlags | mlir::LLVM::DISubprogramFlags::Definition; } - unsigned line = 1; - if (auto funcLoc = l.dyn_cast()) - line = funcLoc.getLine(); - + // FIXME: Provide proper line and scopeline. auto spAttr = mlir::LLVM::DISubprogramAttr::get( - context, id, compilationUnit, fileAttr, funcName, fullName, - funcFileAttr, line, line, subprogramFlags, subTypeAttr); + context, id, compilationUnit, fileAttr, funcName, funcName, + funcFileAttr, /*line=*/1, /*scopeline=*/1, subprogramFlags, + subTypeAttr); funcOp->setLoc(builder.getFusedLoc({funcOp->getLoc()}, spAttr)); }); } diff --git a/flang/lib/Optimizer/Transforms/CMakeLists.txt b/flang/lib/Optimizer/Transforms/CMakeLists.txt index 5a542f237f8f..fc08d67540ce 100644 --- a/flang/lib/Optimizer/Transforms/CMakeLists.txt +++ b/flang/lib/Optimizer/Transforms/CMakeLists.txt @@ -22,7 +22,6 @@ add_flang_library(FIRTransforms OMPMarkDeclareTarget.cpp VScaleAttr.cpp FunctionAttr.cpp - DebugTypeGenerator.cpp DEPENDS FIRDialect diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp deleted file mode 100644 index 0057e08f8a76..000000000000 --- a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.cpp +++ /dev/null @@ -1,63 +0,0 @@ -//===-- DebugTypeGenerator.cpp -- type conversion ---------------*- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/ -// -//===----------------------------------------------------------------------===// - -#define DEBUG_TYPE "flang-debug-type-generator" - -#include "DebugTypeGenerator.h" -#include "llvm/ADT/ScopeExit.h" -#include "llvm/BinaryFormat/Dwarf.h" -#include "llvm/Support/Debug.h" - -namespace fir { - -DebugTypeGenerator::DebugTypeGenerator(mlir::ModuleOp m) - : module(m), kindMapping(getKindMapping(m)) { - LLVM_DEBUG(llvm::dbgs() << "DITypeAttr generator\n"); -} - -static mlir::LLVM::DITypeAttr genPlaceholderType(mlir::MLIRContext *context) { - return mlir::LLVM::DIBasicTypeAttr::get( - context, llvm::dwarf::DW_TAG_base_type, "void", 32, 1); -} - -static mlir::LLVM::DITypeAttr genBasicType(mlir::MLIRContext *context, - mlir::StringAttr name, - unsigned bitSize, - unsigned decoding) { - return mlir::LLVM::DIBasicTypeAttr::get( - context, llvm::dwarf::DW_TAG_base_type, name, bitSize, decoding); -} - -mlir::LLVM::DITypeAttr -DebugTypeGenerator::convertType(mlir::Type Ty, mlir::LLVM::DIFileAttr fileAttr, - mlir::LLVM::DIScopeAttr scope, - mlir::Location loc) { - mlir::MLIRContext *context = module.getContext(); - if (Ty.isIntOrIndex()) { - return genBasicType(context, mlir::StringAttr::get(context, "integer"), - Ty.getIntOrFloatBitWidth(), llvm::dwarf::DW_ATE_signed); - } else if (Ty.isa() || Ty.isa()) { - return genBasicType(context, mlir::StringAttr::get(context, "real"), - Ty.getIntOrFloatBitWidth(), llvm::dwarf::DW_ATE_float); - } else if (auto logTy = Ty.dyn_cast_or_null()) { - return genBasicType(context, - mlir::StringAttr::get(context, logTy.getMnemonic()), - kindMapping.getLogicalBitsize(logTy.getFKind()), - llvm::dwarf::DW_ATE_boolean); - } else { - // FIXME: These types are currently unhandled. We are generating a - // placeholder type to allow us to test supported bits. - return genPlaceholderType(context); - } -} - -} // namespace fir diff --git a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h b/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h deleted file mode 100644 index 5a2bb201db47..000000000000 --- a/flang/lib/Optimizer/Transforms/DebugTypeGenerator.h +++ /dev/null @@ -1,40 +0,0 @@ -//===-- DebugTypeGenerator.h -- type conversion ------------------- C++ -*-===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// -// -// Coding style: https://mlir.llvm.org/getting_started/DeveloperGuide/ -// -//===----------------------------------------------------------------------===// - -#ifndef FORTRAN_OPTIMIZER_TRANSFORMS_DEBUGTYPEGENERATOR_H -#define FORTRAN_OPTIMIZER_TRANSFORMS_DEBUGTYPEGENERATOR_H - -#include "flang/Optimizer/Dialect/FIRType.h" -#include "flang/Optimizer/Dialect/Support/FIRContext.h" -#include "flang/Optimizer/Dialect/Support/KindMapping.h" -#include "llvm/Support/Debug.h" - -namespace fir { - -/// This converts FIR/mlir type to DITypeAttr. -class DebugTypeGenerator { -public: - DebugTypeGenerator(mlir::ModuleOp module); - - mlir::LLVM::DITypeAttr convertType(mlir::Type Ty, - mlir::LLVM::DIFileAttr fileAttr, - mlir::LLVM::DIScopeAttr scope, - mlir::Location loc); - -private: - mlir::ModuleOp module; - KindMapping kindMapping; -}; - -} // namespace fir - -#endif // FORTRAN_OPTIMIZER_TRANSFORMS_DEBUGTYPEGENERATOR_H diff --git a/flang/test/Transforms/debug-fn-info.f90 b/flang/test/Transforms/debug-fn-info.f90 deleted file mode 100644 index c1a817312c95..000000000000 --- a/flang/test/Transforms/debug-fn-info.f90 +++ /dev/null @@ -1,43 +0,0 @@ -! RUN: %flang_fc1 -emit-fir -debug-info-kind=standalone -mmlir --mlir-print-debuginfo %s -o - | fir-opt --add-debug-info --mlir-print-debuginfo | FileCheck %s - - -! CHECK-DAG: #[[INT8:.*]] = #llvm.di_basic_type -! CHECK-DAG: #[[INT4:.*]] = #llvm.di_basic_type -! CHECK-DAG: #[[REAL8:.*]] = #llvm.di_basic_type -! CHECK-DAG: #[[LOG1:.*]] = #llvm.di_basic_type -! CHECK-DAG: #[[REAL4:.*]] = #llvm.di_basic_type -! CHECK-DAG: #[[LOG4:.*]] = #llvm.di_basic_type -! CHECK: #[[TY1:.*]] = #llvm.di_subroutine_type -! CHECK: #[[TY2:.*]] = #llvm.di_subroutine_type - -program mn - integer(kind=4) :: i4 - integer(kind=8) :: i8 - real(kind=4) :: r4 - real(kind=8) :: r8 - logical(kind=1) :: l1 - logical(kind=4) :: l4 - i8 = fn1(i4, r8, l1) - i4 = fn2(i8, r4, l4) -contains - ! CHECK: #di_subprogram1 = #llvm.di_subprogram - function fn1(a, b, c) result (res) - implicit none - integer(kind=4), intent(in) :: a - real(kind=8), intent(in) :: b - logical(kind=1), intent(in) :: c - integer(kind=8) :: res - res = a + b - end function - -! CHECK: #di_subprogram2 = #llvm.di_subprogram - function fn2(a, b, c) result (res) - implicit none - integer(kind=8), intent(in) :: a - real(kind=4), intent(in) :: b - logical(kind=4), intent(in) :: c - integer(kind=4) :: res - res = a + b - end function -end program - diff --git a/flang/test/Transforms/debug-line-table-inc-file.fir b/flang/test/Transforms/debug-line-table-inc-file.fir index d7f60a1a86db..dc75482d4f8a 100644 --- a/flang/test/Transforms/debug-line-table-inc-file.fir +++ b/flang/test/Transforms/debug-line-table-inc-file.fir @@ -31,7 +31,7 @@ module attributes {} { // CHECK: #[[LOC_INC_FILE:.*]] = loc("{{.*}}inc.f90":1:1) // CHECK: #[[LOC_FILE:.*]] = loc("{{.*}}simple.f90":3:1) // CHECK: #[[DI_CU:.*]] = #llvm.di_compile_unit, sourceLanguage = DW_LANG_Fortran95, file = #[[DI_FILE]], producer = "flang{{.*}}", isOptimized = false, emissionKind = LineTablesOnly> -// CHECK: #[[DI_SP_INC:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "sinc", linkageName = "_QPsinc", file = #[[DI_INC_FILE]], {{.*}}> +// CHECK: #[[DI_SP_INC:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "_QPsinc", linkageName = "_QPsinc", file = #[[DI_INC_FILE]], {{.*}}> // CHECK: #[[DI_SP:.*]] = #llvm.di_subprogram, compileUnit = #[[DI_CU]], scope = #[[DI_FILE]], name = "_QQmain", linkageName = "_QQmain", file = #[[DI_FILE]], {{.*}}> // CHECK: #[[FUSED_LOC_INC_FILE]] = loc(fused<#[[DI_SP_INC]]>[#[[LOC_INC_FILE]]]) // CHECK: #[[FUSED_LOC_FILE]] = loc(fused<#[[DI_SP]]>[#[[LOC_FILE]]]) -- GitLab From 93e69abfc77b0bd90f3669e36e510dd4f45aab14 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 29 Apr 2024 10:52:48 +0100 Subject: [PATCH 201/301] [X86] avg*.ll - add nounwind to silence cfi noise --- llvm/test/CodeGen/X86/avgceils.ll | 238 +++-------------------------- llvm/test/CodeGen/X86/avgceilu.ll | 138 +++-------------- llvm/test/CodeGen/X86/avgfloors.ll | 238 +++-------------------------- llvm/test/CodeGen/X86/avgflooru.ll | 138 +++-------------- 4 files changed, 96 insertions(+), 656 deletions(-) diff --git a/llvm/test/CodeGen/X86/avgceils.ll b/llvm/test/CodeGen/X86/avgceils.ll index 4529ea275df9..f44f98c2a41a 100644 --- a/llvm/test/CodeGen/X86/avgceils.ll +++ b/llvm/test/CodeGen/X86/avgceils.ll @@ -9,7 +9,7 @@ ; 128-bit vectors ; -define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -65,7 +65,7 @@ define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i8: ; SSE2: # %bb.0: ; SSE2-NEXT: punpckhbw {{.*#+}} xmm2 = xmm2[8],xmm0[8],xmm2[9],xmm0[9],xmm2[10],xmm0[10],xmm2[11],xmm0[11],xmm2[12],xmm0[12],xmm2[13],xmm0[13],xmm2[14],xmm0[14],xmm2[15],xmm0[15] @@ -165,7 +165,7 @@ define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -190,7 +190,7 @@ define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i16: ; SSE2: # %bb.0: ; SSE2-NEXT: punpcklwd {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3] @@ -289,7 +289,7 @@ define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v4i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -314,7 +314,7 @@ define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3] @@ -410,7 +410,7 @@ define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE2-LABEL: test_fixed_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm0, %xmm2 @@ -472,7 +472,7 @@ define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ret <2 x i64> %res } -define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movq %xmm0, %rax @@ -574,7 +574,7 @@ define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ; 256-bit vectors ; -define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -649,7 +649,7 @@ define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v32i8: ; SSE2: # %bb.0: ; SSE2-NEXT: punpckhbw {{.*#+}} xmm5 = xmm5[8],xmm0[8],xmm5[9],xmm0[9],xmm5[10],xmm0[10],xmm5[11],xmm0[11],xmm5[12],xmm0[12],xmm5[13],xmm0[13],xmm5[14],xmm0[14],xmm5[15],xmm0[15] @@ -806,7 +806,7 @@ define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -858,7 +858,7 @@ define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i16: ; SSE2: # %bb.0: ; SSE2-NEXT: punpcklwd {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3] @@ -1014,7 +1014,7 @@ define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -1066,7 +1066,7 @@ define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm6 = xmm0[2,3,2,3] @@ -1218,7 +1218,7 @@ define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE2-LABEL: test_fixed_v4i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm1, %xmm4 @@ -1306,27 +1306,15 @@ define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ret <4 x i64> %res } -define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pushq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: pushq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: pushq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: pushq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: pushq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: pushq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 56 -; SSE2-NEXT: .cfi_offset %rbx, -56 -; SSE2-NEXT: .cfi_offset %r12, -48 -; SSE2-NEXT: .cfi_offset %r13, -40 -; SSE2-NEXT: .cfi_offset %r14, -32 -; SSE2-NEXT: .cfi_offset %r15, -24 -; SSE2-NEXT: .cfi_offset %rbp, -16 ; SSE2-NEXT: movq %xmm0, %r11 ; SSE2-NEXT: movq %r11, %r12 ; SSE2-NEXT: sarq $63, %r12 @@ -1382,39 +1370,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE2-NEXT: popq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: popq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: popq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: popq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: popq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: popq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 8 ; SSE2-NEXT: retq ; ; SSE4-LABEL: test_ext_v4i64: ; SSE4: # %bb.0: ; SSE4-NEXT: pushq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: pushq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: pushq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: pushq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: pushq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: pushq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 56 -; SSE4-NEXT: .cfi_offset %rbx, -56 -; SSE4-NEXT: .cfi_offset %r12, -48 -; SSE4-NEXT: .cfi_offset %r13, -40 -; SSE4-NEXT: .cfi_offset %r14, -32 -; SSE4-NEXT: .cfi_offset %r15, -24 -; SSE4-NEXT: .cfi_offset %rbp, -16 ; SSE4-NEXT: pextrq $1, %xmm0, %r11 ; SSE4-NEXT: movq %r11, %r12 ; SSE4-NEXT: sarq $63, %r12 @@ -1466,39 +1436,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE4-NEXT: popq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: popq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: popq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: popq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: popq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: popq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 8 ; SSE4-NEXT: retq ; ; AVX1-LABEL: test_ext_v4i64: ; AVX1: # %bb.0: ; AVX1-NEXT: pushq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: pushq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: pushq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: pushq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: pushq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: pushq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 56 -; AVX1-NEXT: .cfi_offset %rbx, -56 -; AVX1-NEXT: .cfi_offset %r12, -48 -; AVX1-NEXT: .cfi_offset %r13, -40 -; AVX1-NEXT: .cfi_offset %r14, -32 -; AVX1-NEXT: .cfi_offset %r15, -24 -; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm2 ; AVX1-NEXT: vpextrq $1, %xmm2, %r11 ; AVX1-NEXT: movq %r11, %r12 @@ -1553,39 +1505,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: popq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: popq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: popq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: popq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: popq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: popq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: retq ; ; AVX2-LABEL: test_ext_v4i64: ; AVX2: # %bb.0: ; AVX2-NEXT: pushq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: pushq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: pushq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: pushq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: pushq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: pushq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 56 -; AVX2-NEXT: .cfi_offset %rbx, -56 -; AVX2-NEXT: .cfi_offset %r12, -48 -; AVX2-NEXT: .cfi_offset %r13, -40 -; AVX2-NEXT: .cfi_offset %r14, -32 -; AVX2-NEXT: .cfi_offset %r15, -24 -; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm2 ; AVX2-NEXT: vpextrq $1, %xmm2, %r11 ; AVX2-NEXT: movq %r11, %r12 @@ -1640,39 +1574,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0] ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: popq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: popq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: popq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: popq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: popq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: popq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 8 ; AVX2-NEXT: retq ; ; AVX512-LABEL: test_ext_v4i64: ; AVX512: # %bb.0: ; AVX512-NEXT: pushq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: pushq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: pushq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: pushq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: pushq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: pushq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 56 -; AVX512-NEXT: .cfi_offset %rbx, -56 -; AVX512-NEXT: .cfi_offset %r12, -48 -; AVX512-NEXT: .cfi_offset %r13, -40 -; AVX512-NEXT: .cfi_offset %r14, -32 -; AVX512-NEXT: .cfi_offset %r15, -24 -; AVX512-NEXT: .cfi_offset %rbp, -16 ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm2 ; AVX512-NEXT: vpextrq $1, %xmm2, %r11 ; AVX512-NEXT: movq %r11, %r12 @@ -1727,17 +1643,11 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0] ; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX512-NEXT: popq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: popq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: popq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: popq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: popq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: popq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 8 ; AVX512-NEXT: retq %x0 = sext <4 x i64> %a0 to <4 x i128> %x1 = sext <4 x i64> %a1 to <4 x i128> @@ -1752,7 +1662,7 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; 512-bit vectors ; -define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v64i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm11 @@ -1864,7 +1774,7 @@ define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v64i8: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm3, %xmm8 @@ -2144,7 +2054,7 @@ define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -2220,7 +2130,7 @@ define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v32i16: ; SSE2: # %bb.0: ; SSE2-NEXT: punpcklwd {{.*#+}} xmm13 = xmm13[0],xmm3[0],xmm13[1],xmm3[1],xmm13[2],xmm3[2],xmm13[3],xmm3[3] @@ -2498,7 +2408,7 @@ define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -2574,7 +2484,7 @@ define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm13 = xmm0[2,3,2,3] @@ -2848,7 +2758,7 @@ define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE2-LABEL: test_fixed_v8i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm3, %xmm8 @@ -2985,29 +2895,16 @@ define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ret <8 x i64> %res } -define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pushq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: pushq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: pushq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: pushq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: pushq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: pushq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 56 ; SSE2-NEXT: pushq %rax -; SSE2-NEXT: .cfi_def_cfa_offset 64 -; SSE2-NEXT: .cfi_offset %rbx, -56 -; SSE2-NEXT: .cfi_offset %r12, -48 -; SSE2-NEXT: .cfi_offset %r13, -40 -; SSE2-NEXT: .cfi_offset %r14, -32 -; SSE2-NEXT: .cfi_offset %r15, -24 -; SSE2-NEXT: .cfi_offset %rbp, -16 ; SSE2-NEXT: movq %xmm0, %rax ; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE2-NEXT: sarq $63, %rax @@ -3137,43 +3034,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE2-NEXT: addq $8, %rsp -; SSE2-NEXT: .cfi_def_cfa_offset 56 ; SSE2-NEXT: popq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: popq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: popq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: popq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: popq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: popq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 8 ; SSE2-NEXT: retq ; ; SSE4-LABEL: test_ext_v8i64: ; SSE4: # %bb.0: ; SSE4-NEXT: pushq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: pushq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: pushq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: pushq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: pushq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: pushq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 56 ; SSE4-NEXT: subq $16, %rsp -; SSE4-NEXT: .cfi_def_cfa_offset 72 -; SSE4-NEXT: .cfi_offset %rbx, -56 -; SSE4-NEXT: .cfi_offset %r12, -48 -; SSE4-NEXT: .cfi_offset %r13, -40 -; SSE4-NEXT: .cfi_offset %r14, -32 -; SSE4-NEXT: .cfi_offset %r15, -24 -; SSE4-NEXT: .cfi_offset %rbp, -16 ; SSE4-NEXT: pextrq $1, %xmm0, %rax ; SSE4-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE4-NEXT: sarq $63, %rax @@ -3301,43 +3178,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE4-NEXT: addq $16, %rsp -; SSE4-NEXT: .cfi_def_cfa_offset 56 ; SSE4-NEXT: popq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: popq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: popq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: popq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: popq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: popq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 8 ; SSE4-NEXT: retq ; ; AVX1-LABEL: test_ext_v8i64: ; AVX1: # %bb.0: ; AVX1-NEXT: pushq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: pushq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: pushq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: pushq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: pushq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: pushq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 56 ; AVX1-NEXT: pushq %rax -; AVX1-NEXT: .cfi_def_cfa_offset 64 -; AVX1-NEXT: .cfi_offset %rbx, -56 -; AVX1-NEXT: .cfi_offset %r12, -48 -; AVX1-NEXT: .cfi_offset %r13, -40 -; AVX1-NEXT: .cfi_offset %r14, -32 -; AVX1-NEXT: .cfi_offset %r15, -24 -; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: vextractf128 $1, %ymm0, %xmm4 ; AVX1-NEXT: vpextrq $1, %xmm4, %rax ; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -3465,43 +3322,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: addq $8, %rsp -; AVX1-NEXT: .cfi_def_cfa_offset 56 ; AVX1-NEXT: popq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: popq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: popq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: popq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: popq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: popq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: retq ; ; AVX2-LABEL: test_ext_v8i64: ; AVX2: # %bb.0: ; AVX2-NEXT: pushq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: pushq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: pushq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: pushq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: pushq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: pushq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 56 ; AVX2-NEXT: pushq %rax -; AVX2-NEXT: .cfi_def_cfa_offset 64 -; AVX2-NEXT: .cfi_offset %rbx, -56 -; AVX2-NEXT: .cfi_offset %r12, -48 -; AVX2-NEXT: .cfi_offset %r13, -40 -; AVX2-NEXT: .cfi_offset %r14, -32 -; AVX2-NEXT: .cfi_offset %r15, -24 -; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm4 ; AVX2-NEXT: vpextrq $1, %xmm4, %rax ; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -3629,43 +3466,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: addq $8, %rsp -; AVX2-NEXT: .cfi_def_cfa_offset 56 ; AVX2-NEXT: popq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: popq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: popq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: popq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: popq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: popq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 8 ; AVX2-NEXT: retq ; ; AVX512-LABEL: test_ext_v8i64: ; AVX512: # %bb.0: ; AVX512-NEXT: pushq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: pushq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: pushq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: pushq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: pushq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: pushq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 56 ; AVX512-NEXT: pushq %rax -; AVX512-NEXT: .cfi_def_cfa_offset 64 -; AVX512-NEXT: .cfi_offset %rbx, -56 -; AVX512-NEXT: .cfi_offset %r12, -48 -; AVX512-NEXT: .cfi_offset %r13, -40 -; AVX512-NEXT: .cfi_offset %r14, -32 -; AVX512-NEXT: .cfi_offset %r15, -24 -; AVX512-NEXT: .cfi_offset %rbp, -16 ; AVX512-NEXT: vextracti64x4 $1, %zmm0, %ymm2 ; AVX512-NEXT: vextracti128 $1, %ymm2, %xmm3 ; AVX512-NEXT: vpextrq $1, %xmm3, %rax @@ -3796,19 +3613,12 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512-NEXT: addq $8, %rsp -; AVX512-NEXT: .cfi_def_cfa_offset 56 ; AVX512-NEXT: popq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: popq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: popq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: popq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: popq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: popq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 8 ; AVX512-NEXT: retq %x0 = sext <8 x i64> %a0 to <8 x i128> %x1 = sext <8 x i64> %a1 to <8 x i128> diff --git a/llvm/test/CodeGen/X86/avgceilu.ll b/llvm/test/CodeGen/X86/avgceilu.ll index dee1a5a720f9..d34894cc0fbb 100644 --- a/llvm/test/CodeGen/X86/avgceilu.ll +++ b/llvm/test/CodeGen/X86/avgceilu.ll @@ -9,7 +9,7 @@ ; 128-bit vectors ; -define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i8: ; SSE: # %bb.0: ; SSE-NEXT: pavgb %xmm1, %xmm0 @@ -26,7 +26,7 @@ define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE-LABEL: test_ext_v16i8: ; SSE: # %bb.0: ; SSE-NEXT: pavgb %xmm1, %xmm0 @@ -45,7 +45,7 @@ define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i16: ; SSE: # %bb.0: ; SSE-NEXT: pavgw %xmm1, %xmm0 @@ -62,7 +62,7 @@ define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE-LABEL: test_ext_v8i16: ; SSE: # %bb.0: ; SSE-NEXT: pavgw %xmm1, %xmm0 @@ -81,7 +81,7 @@ define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v4i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -106,7 +106,7 @@ define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm3, %xmm3 @@ -195,7 +195,7 @@ define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE-LABEL: test_fixed_v2i64: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -220,7 +220,7 @@ define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ret <2 x i64> %res } -define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3] @@ -310,7 +310,7 @@ define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ; 256-bit vectors ; -define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i8: ; SSE: # %bb.0: ; SSE-NEXT: pavgb %xmm2, %xmm0 @@ -342,7 +342,7 @@ define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE-LABEL: test_ext_v32i8: ; SSE: # %bb.0: ; SSE-NEXT: pavgb %xmm2, %xmm0 @@ -376,7 +376,7 @@ define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i16: ; SSE: # %bb.0: ; SSE-NEXT: pavgw %xmm2, %xmm0 @@ -408,7 +408,7 @@ define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: test_ext_v16i16: ; SSE: # %bb.0: ; SSE-NEXT: pavgw %xmm2, %xmm0 @@ -442,7 +442,7 @@ define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -494,7 +494,7 @@ define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i32: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm0, %xmm4 @@ -629,7 +629,7 @@ define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: test_fixed_v4i64: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -681,7 +681,7 @@ define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ret <4 x i64> %res } -define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3] @@ -937,7 +937,7 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; 512-bit vectors ; -define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v64i8: ; SSE: # %bb.0: ; SSE-NEXT: pavgb %xmm4, %xmm0 @@ -977,7 +977,7 @@ define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE-LABEL: test_ext_v64i8: ; SSE: # %bb.0: ; SSE-NEXT: pavgb %xmm4, %xmm0 @@ -1019,7 +1019,7 @@ define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i16: ; SSE: # %bb.0: ; SSE-NEXT: pavgw %xmm4, %xmm0 @@ -1059,7 +1059,7 @@ define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE-LABEL: test_ext_v32i16: ; SSE: # %bb.0: ; SSE-NEXT: pavgw %xmm4, %xmm0 @@ -1101,7 +1101,7 @@ define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -1177,7 +1177,7 @@ define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i32: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm2, %xmm8 @@ -1413,7 +1413,7 @@ define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i64: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -1489,27 +1489,15 @@ define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ret <8 x i64> %res } -define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pushq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: pushq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: pushq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: pushq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: pushq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: pushq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 56 -; SSE2-NEXT: .cfi_offset %rbx, -56 -; SSE2-NEXT: .cfi_offset %r12, -48 -; SSE2-NEXT: .cfi_offset %r13, -40 -; SSE2-NEXT: .cfi_offset %r14, -32 -; SSE2-NEXT: .cfi_offset %r15, -24 -; SSE2-NEXT: .cfi_offset %rbp, -16 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm3[2,3,2,3] ; SSE2-NEXT: movq %xmm8, %rcx ; SSE2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -1617,39 +1605,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE2-NEXT: popq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: popq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: popq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: popq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: popq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: popq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 8 ; SSE2-NEXT: retq ; ; SSE4-LABEL: test_ext_v8i64: ; SSE4: # %bb.0: ; SSE4-NEXT: pushq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: pushq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: pushq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: pushq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: pushq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: pushq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 56 -; SSE4-NEXT: .cfi_offset %rbx, -56 -; SSE4-NEXT: .cfi_offset %r12, -48 -; SSE4-NEXT: .cfi_offset %r13, -40 -; SSE4-NEXT: .cfi_offset %r14, -32 -; SSE4-NEXT: .cfi_offset %r15, -24 -; SSE4-NEXT: .cfi_offset %rbp, -16 ; SSE4-NEXT: movq %xmm3, %rcx ; SSE4-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE4-NEXT: movq %xmm7, %rdx @@ -1747,39 +1717,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE4-NEXT: popq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: popq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: popq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: popq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: popq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: popq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 8 ; SSE4-NEXT: retq ; ; AVX1-LABEL: test_ext_v8i64: ; AVX1: # %bb.0: ; AVX1-NEXT: pushq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: pushq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: pushq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: pushq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: pushq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: pushq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 56 -; AVX1-NEXT: .cfi_offset %rbx, -56 -; AVX1-NEXT: .cfi_offset %r12, -48 -; AVX1-NEXT: .cfi_offset %r13, -40 -; AVX1-NEXT: .cfi_offset %r14, -32 -; AVX1-NEXT: .cfi_offset %r15, -24 -; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: vmovq %xmm1, %rcx ; AVX1-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX1-NEXT: vmovq %xmm3, %rdx @@ -1885,39 +1837,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: popq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: popq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: popq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: popq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: popq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: popq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: retq ; ; AVX2-LABEL: test_ext_v8i64: ; AVX2: # %bb.0: ; AVX2-NEXT: pushq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: pushq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: pushq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: pushq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: pushq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: pushq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 56 -; AVX2-NEXT: .cfi_offset %rbx, -56 -; AVX2-NEXT: .cfi_offset %r12, -48 -; AVX2-NEXT: .cfi_offset %r13, -40 -; AVX2-NEXT: .cfi_offset %r14, -32 -; AVX2-NEXT: .cfi_offset %r15, -24 -; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: vmovq %xmm1, %rcx ; AVX2-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX2-NEXT: vmovq %xmm3, %rdx @@ -2023,39 +1957,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: popq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: popq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: popq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: popq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: popq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: popq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 8 ; AVX2-NEXT: retq ; ; AVX512-LABEL: test_ext_v8i64: ; AVX512: # %bb.0: ; AVX512-NEXT: pushq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: pushq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: pushq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: pushq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: pushq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: pushq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 56 -; AVX512-NEXT: .cfi_offset %rbx, -56 -; AVX512-NEXT: .cfi_offset %r12, -48 -; AVX512-NEXT: .cfi_offset %r13, -40 -; AVX512-NEXT: .cfi_offset %r14, -32 -; AVX512-NEXT: .cfi_offset %r15, -24 -; AVX512-NEXT: .cfi_offset %rbp, -16 ; AVX512-NEXT: vmovq %xmm0, %rcx ; AVX512-NEXT: movq %rcx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX512-NEXT: vmovq %xmm1, %rdx @@ -2164,17 +2080,11 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512-NEXT: popq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: popq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: popq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: popq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: popq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: popq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 8 ; AVX512-NEXT: retq %x0 = zext <8 x i64> %a0 to <8 x i128> %x1 = zext <8 x i64> %a1 to <8 x i128> diff --git a/llvm/test/CodeGen/X86/avgfloors.ll b/llvm/test/CodeGen/X86/avgfloors.ll index a3864ab4bb44..efee831a15c7 100644 --- a/llvm/test/CodeGen/X86/avgfloors.ll +++ b/llvm/test/CodeGen/X86/avgfloors.ll @@ -9,7 +9,7 @@ ; 128-bit vectors ; -define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -64,7 +64,7 @@ define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i8: ; SSE2: # %bb.0: ; SSE2-NEXT: punpcklbw {{.*#+}} xmm2 = xmm2[0],xmm0[0],xmm2[1],xmm0[1],xmm2[2],xmm0[2],xmm2[3],xmm0[3],xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] @@ -150,7 +150,7 @@ define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -174,7 +174,7 @@ define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i16: ; SSE2: # %bb.0: ; SSE2-NEXT: punpckhwd {{.*#+}} xmm2 = xmm2[4],xmm0[4],xmm2[5],xmm0[5],xmm2[6],xmm0[6],xmm2[7],xmm0[7] @@ -259,7 +259,7 @@ define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v4i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -283,7 +283,7 @@ define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm2, %xmm2 @@ -365,7 +365,7 @@ define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE2-LABEL: test_fixed_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm0, %xmm2 @@ -425,7 +425,7 @@ define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ret <2 x i64> %res } -define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3] @@ -514,7 +514,7 @@ define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ; 256-bit vectors ; -define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -587,7 +587,7 @@ define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v32i8: ; SSE2: # %bb.0: ; SSE2-NEXT: punpcklbw {{.*#+}} xmm4 = xmm4[0],xmm1[0],xmm4[1],xmm1[1],xmm4[2],xmm1[2],xmm4[3],xmm1[3],xmm4[4],xmm1[4],xmm4[5],xmm1[5],xmm4[6],xmm1[6],xmm4[7],xmm1[7] @@ -723,7 +723,7 @@ define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -773,7 +773,7 @@ define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i16: ; SSE2: # %bb.0: ; SSE2-NEXT: punpckhwd {{.*#+}} xmm4 = xmm4[4],xmm0[4],xmm4[5],xmm0[5],xmm4[6],xmm0[6],xmm4[7],xmm0[7] @@ -908,7 +908,7 @@ define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -958,7 +958,7 @@ define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm4, %xmm4 @@ -1089,7 +1089,7 @@ define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE2-LABEL: test_fixed_v4i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm1, %xmm4 @@ -1173,27 +1173,15 @@ define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ret <4 x i64> %res } -define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pushq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: pushq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: pushq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: pushq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: pushq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: pushq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 56 -; SSE2-NEXT: .cfi_offset %rbx, -56 -; SSE2-NEXT: .cfi_offset %r12, -48 -; SSE2-NEXT: .cfi_offset %r13, -40 -; SSE2-NEXT: .cfi_offset %r14, -32 -; SSE2-NEXT: .cfi_offset %r15, -24 -; SSE2-NEXT: .cfi_offset %rbp, -16 ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3] ; SSE2-NEXT: movq %xmm4, %rdx ; SSE2-NEXT: movq %rdx, %r14 @@ -1241,39 +1229,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE2-NEXT: popq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: popq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: popq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: popq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: popq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: popq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 8 ; SSE2-NEXT: retq ; ; SSE4-LABEL: test_ext_v4i64: ; SSE4: # %bb.0: ; SSE4-NEXT: pushq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: pushq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: pushq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: pushq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: pushq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: pushq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 56 -; SSE4-NEXT: .cfi_offset %rbx, -56 -; SSE4-NEXT: .cfi_offset %r12, -48 -; SSE4-NEXT: .cfi_offset %r13, -40 -; SSE4-NEXT: .cfi_offset %r14, -32 -; SSE4-NEXT: .cfi_offset %r15, -24 -; SSE4-NEXT: .cfi_offset %rbp, -16 ; SSE4-NEXT: movq %xmm1, %rdi ; SSE4-NEXT: movq %rdi, %r14 ; SSE4-NEXT: sarq $63, %r14 @@ -1317,39 +1287,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm2[0] ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm3[0] ; SSE4-NEXT: popq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: popq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: popq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: popq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: popq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: popq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 8 ; SSE4-NEXT: retq ; ; AVX1-LABEL: test_ext_v4i64: ; AVX1: # %bb.0: ; AVX1-NEXT: pushq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: pushq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: pushq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: pushq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: pushq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: pushq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 56 -; AVX1-NEXT: .cfi_offset %rbx, -56 -; AVX1-NEXT: .cfi_offset %r12, -48 -; AVX1-NEXT: .cfi_offset %r13, -40 -; AVX1-NEXT: .cfi_offset %r14, -32 -; AVX1-NEXT: .cfi_offset %r15, -24 -; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: vmovq %xmm0, %rdx ; AVX1-NEXT: movq %rdx, %r14 ; AVX1-NEXT: sarq $63, %r14 @@ -1396,39 +1348,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0] ; AVX1-NEXT: vinsertf128 $1, %xmm0, %ymm1, %ymm0 ; AVX1-NEXT: popq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: popq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: popq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: popq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: popq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: popq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: retq ; ; AVX2-LABEL: test_ext_v4i64: ; AVX2: # %bb.0: ; AVX2-NEXT: pushq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: pushq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: pushq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: pushq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: pushq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: pushq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 56 -; AVX2-NEXT: .cfi_offset %rbx, -56 -; AVX2-NEXT: .cfi_offset %r12, -48 -; AVX2-NEXT: .cfi_offset %r13, -40 -; AVX2-NEXT: .cfi_offset %r14, -32 -; AVX2-NEXT: .cfi_offset %r15, -24 -; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: vmovq %xmm0, %rdx ; AVX2-NEXT: movq %rdx, %r14 ; AVX2-NEXT: sarq $63, %r14 @@ -1475,39 +1409,21 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0] ; AVX2-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX2-NEXT: popq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: popq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: popq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: popq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: popq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: popq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 8 ; AVX2-NEXT: retq ; ; AVX512-LABEL: test_ext_v4i64: ; AVX512: # %bb.0: ; AVX512-NEXT: pushq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: pushq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: pushq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: pushq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: pushq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: pushq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 56 -; AVX512-NEXT: .cfi_offset %rbx, -56 -; AVX512-NEXT: .cfi_offset %r12, -48 -; AVX512-NEXT: .cfi_offset %r13, -40 -; AVX512-NEXT: .cfi_offset %r14, -32 -; AVX512-NEXT: .cfi_offset %r15, -24 -; AVX512-NEXT: .cfi_offset %rbp, -16 ; AVX512-NEXT: vmovq %xmm0, %rdx ; AVX512-NEXT: movq %rdx, %r14 ; AVX512-NEXT: sarq $63, %r14 @@ -1554,17 +1470,11 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; AVX512-NEXT: vpunpcklqdq {{.*#+}} xmm1 = xmm3[0],xmm2[0] ; AVX512-NEXT: vinserti128 $1, %xmm0, %ymm1, %ymm0 ; AVX512-NEXT: popq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: popq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: popq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: popq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: popq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: popq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 8 ; AVX512-NEXT: retq %x0 = sext <4 x i64> %a0 to <4 x i128> %x1 = sext <4 x i64> %a1 to <4 x i128> @@ -1578,7 +1488,7 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; 512-bit vectors ; -define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v64i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm10 @@ -1690,7 +1600,7 @@ define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v64i8: ; SSE2: # %bb.0: ; SSE2-NEXT: punpcklbw {{.*#+}} xmm13 = xmm13[0],xmm3[0],xmm13[1],xmm3[1],xmm13[2],xmm3[2],xmm13[3],xmm3[3],xmm13[4],xmm3[4],xmm13[5],xmm3[5],xmm13[6],xmm3[6],xmm13[7],xmm3[7] @@ -1934,7 +1844,7 @@ define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -2007,7 +1917,7 @@ define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v32i16: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm3, %xmm9 @@ -2251,7 +2161,7 @@ define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -2324,7 +2234,7 @@ define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm8, %xmm8 @@ -2561,7 +2471,7 @@ define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE2-LABEL: test_fixed_v8i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm3, %xmm11 @@ -2698,29 +2608,16 @@ define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ret <8 x i64> %res } -define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pushq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: pushq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: pushq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: pushq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: pushq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: pushq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 56 ; SSE2-NEXT: pushq %rax -; SSE2-NEXT: .cfi_def_cfa_offset 64 -; SSE2-NEXT: .cfi_offset %rbx, -56 -; SSE2-NEXT: .cfi_offset %r12, -48 -; SSE2-NEXT: .cfi_offset %r13, -40 -; SSE2-NEXT: .cfi_offset %r14, -32 -; SSE2-NEXT: .cfi_offset %r15, -24 -; SSE2-NEXT: .cfi_offset %rbp, -16 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm3[2,3,2,3] ; SSE2-NEXT: movq %xmm8, %rax ; SSE2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill @@ -2832,43 +2729,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE2-NEXT: addq $8, %rsp -; SSE2-NEXT: .cfi_def_cfa_offset 56 ; SSE2-NEXT: popq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: popq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: popq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: popq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: popq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: popq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 8 ; SSE2-NEXT: retq ; ; SSE4-LABEL: test_ext_v8i64: ; SSE4: # %bb.0: ; SSE4-NEXT: pushq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: pushq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: pushq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: pushq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: pushq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: pushq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 56 ; SSE4-NEXT: pushq %rax -; SSE4-NEXT: .cfi_def_cfa_offset 64 -; SSE4-NEXT: .cfi_offset %rbx, -56 -; SSE4-NEXT: .cfi_offset %r12, -48 -; SSE4-NEXT: .cfi_offset %r13, -40 -; SSE4-NEXT: .cfi_offset %r14, -32 -; SSE4-NEXT: .cfi_offset %r15, -24 -; SSE4-NEXT: .cfi_offset %rbp, -16 ; SSE4-NEXT: movq %xmm3, %rax ; SSE4-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; SSE4-NEXT: movq %rax, %rcx @@ -2972,43 +2849,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE4-NEXT: addq $8, %rsp -; SSE4-NEXT: .cfi_def_cfa_offset 56 ; SSE4-NEXT: popq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: popq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: popq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: popq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: popq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: popq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 8 ; SSE4-NEXT: retq ; ; AVX1-LABEL: test_ext_v8i64: ; AVX1: # %bb.0: ; AVX1-NEXT: pushq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: pushq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: pushq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: pushq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: pushq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: pushq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 56 ; AVX1-NEXT: pushq %rax -; AVX1-NEXT: .cfi_def_cfa_offset 64 -; AVX1-NEXT: .cfi_offset %rbx, -56 -; AVX1-NEXT: .cfi_offset %r12, -48 -; AVX1-NEXT: .cfi_offset %r13, -40 -; AVX1-NEXT: .cfi_offset %r14, -32 -; AVX1-NEXT: .cfi_offset %r15, -24 -; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: vmovq %xmm1, %rax ; AVX1-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX1-NEXT: movq %rax, %rcx @@ -3118,43 +2975,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: addq $8, %rsp -; AVX1-NEXT: .cfi_def_cfa_offset 56 ; AVX1-NEXT: popq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: popq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: popq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: popq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: popq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: popq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: retq ; ; AVX2-LABEL: test_ext_v8i64: ; AVX2: # %bb.0: ; AVX2-NEXT: pushq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: pushq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: pushq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: pushq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: pushq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: pushq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 56 ; AVX2-NEXT: pushq %rax -; AVX2-NEXT: .cfi_def_cfa_offset 64 -; AVX2-NEXT: .cfi_offset %rbx, -56 -; AVX2-NEXT: .cfi_offset %r12, -48 -; AVX2-NEXT: .cfi_offset %r13, -40 -; AVX2-NEXT: .cfi_offset %r14, -32 -; AVX2-NEXT: .cfi_offset %r15, -24 -; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: vmovq %xmm1, %rax ; AVX2-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX2-NEXT: movq %rax, %rcx @@ -3264,43 +3101,23 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: addq $8, %rsp -; AVX2-NEXT: .cfi_def_cfa_offset 56 ; AVX2-NEXT: popq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: popq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: popq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: popq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: popq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: popq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 8 ; AVX2-NEXT: retq ; ; AVX512-LABEL: test_ext_v8i64: ; AVX512: # %bb.0: ; AVX512-NEXT: pushq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: pushq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: pushq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: pushq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: pushq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: pushq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 56 ; AVX512-NEXT: pushq %rax -; AVX512-NEXT: .cfi_def_cfa_offset 64 -; AVX512-NEXT: .cfi_offset %rbx, -56 -; AVX512-NEXT: .cfi_offset %r12, -48 -; AVX512-NEXT: .cfi_offset %r13, -40 -; AVX512-NEXT: .cfi_offset %r14, -32 -; AVX512-NEXT: .cfi_offset %r15, -24 -; AVX512-NEXT: .cfi_offset %rbp, -16 ; AVX512-NEXT: vmovq %xmm0, %rax ; AVX512-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill ; AVX512-NEXT: movq %rax, %rcx @@ -3413,19 +3230,12 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512-NEXT: addq $8, %rsp -; AVX512-NEXT: .cfi_def_cfa_offset 56 ; AVX512-NEXT: popq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: popq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: popq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: popq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: popq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: popq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 8 ; AVX512-NEXT: retq %x0 = sext <8 x i64> %a0 to <8 x i128> %x1 = sext <8 x i64> %a1 to <8 x i128> diff --git a/llvm/test/CodeGen/X86/avgflooru.ll b/llvm/test/CodeGen/X86/avgflooru.ll index e07c1f55991e..000457c5ab1e 100644 --- a/llvm/test/CodeGen/X86/avgflooru.ll +++ b/llvm/test/CodeGen/X86/avgflooru.ll @@ -9,7 +9,7 @@ ; 128-bit vectors ; -define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -53,7 +53,7 @@ define <16 x i8> @test_fixed_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { +define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i8: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm2, %xmm2 @@ -127,7 +127,7 @@ define <16 x i8> @test_ext_v16i8(<16 x i8> %a0, <16 x i8> %a1) { ret <16 x i8> %res } -define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -151,7 +151,7 @@ define <8 x i16> @test_fixed_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { +define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i16: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm2, %xmm2 @@ -227,7 +227,7 @@ define <8 x i16> @test_ext_v8i16(<8 x i16> %a0, <8 x i16> %a1) { ret <8 x i16> %res } -define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v4i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -251,7 +251,7 @@ define <4 x i32> @test_fixed_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { +define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm2, %xmm2 @@ -325,7 +325,7 @@ define <4 x i32> @test_ext_v4i32(<4 x i32> %a0, <4 x i32> %a1) { ret <4 x i32> %res } -define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE-LABEL: test_fixed_v2i64: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm0, %xmm2 @@ -349,7 +349,7 @@ define <2 x i64> @test_fixed_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ret <2 x i64> %res } -define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { +define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm2 = xmm0[2,3,2,3] @@ -458,7 +458,7 @@ define <2 x i64> @test_ext_v2i64(<2 x i64> %a0, <2 x i64> %a1) { ; 256-bit vectors ; -define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -516,7 +516,7 @@ define <32 x i8> @test_fixed_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { +define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v32i8: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm4, %xmm4 @@ -627,7 +627,7 @@ define <32 x i8> @test_ext_v32i8(<32 x i8> %a0, <32 x i8> %a1) { ret <32 x i8> %res } -define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -677,7 +677,7 @@ define <16 x i16> @test_fixed_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { +define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i16: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm4, %xmm4 @@ -792,7 +792,7 @@ define <16 x i16> @test_ext_v16i16(<16 x i16> %a0, <16 x i16> %a1) { ret <16 x i16> %res } -define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -842,7 +842,7 @@ define <8 x i32> @test_fixed_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { +define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm4, %xmm4 @@ -954,7 +954,7 @@ define <8 x i32> @test_ext_v8i32(<8 x i32> %a0, <8 x i32> %a1) { ret <8 x i32> %res } -define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE-LABEL: test_fixed_v4i64: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm1, %xmm4 @@ -1004,7 +1004,7 @@ define <4 x i64> @test_fixed_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ret <4 x i64> %res } -define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { +define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v4i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pshufd {{.*#+}} xmm4 = xmm1[2,3,2,3] @@ -1199,7 +1199,7 @@ define <4 x i64> @test_ext_v4i64(<4 x i64> %a0, <4 x i64> %a1) { ; 512-bit vectors ; -define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE-LABEL: test_fixed_v64i8: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm9 @@ -1286,7 +1286,7 @@ define <64 x i8> @test_fixed_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { +define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) nounwind { ; SSE2-LABEL: test_ext_v64i8: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm8, %xmm8 @@ -1481,7 +1481,7 @@ define <64 x i8> @test_ext_v64i8(<64 x i8> %a0, <64 x i8> %a1) { ret <64 x i8> %res } -define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE-LABEL: test_fixed_v32i16: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -1554,7 +1554,7 @@ define <32 x i16> @test_fixed_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { +define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) nounwind { ; SSE2-LABEL: test_ext_v32i16: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm8, %xmm8 @@ -1757,7 +1757,7 @@ define <32 x i16> @test_ext_v32i16(<32 x i16> %a0, <32 x i16> %a1) { ret <32 x i16> %res } -define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE-LABEL: test_fixed_v16i32: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -1830,7 +1830,7 @@ define <16 x i32> @test_fixed_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { +define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) nounwind { ; SSE2-LABEL: test_ext_v16i32: ; SSE2: # %bb.0: ; SSE2-NEXT: pxor %xmm8, %xmm8 @@ -2027,7 +2027,7 @@ define <16 x i32> @test_ext_v16i32(<16 x i32> %a0, <16 x i32> %a1) { ret <16 x i32> %res } -define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE-LABEL: test_fixed_v8i64: ; SSE: # %bb.0: ; SSE-NEXT: movdqa %xmm3, %xmm8 @@ -2100,27 +2100,15 @@ define <8 x i64> @test_fixed_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ret <8 x i64> %res } -define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { +define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) nounwind { ; SSE2-LABEL: test_ext_v8i64: ; SSE2: # %bb.0: ; SSE2-NEXT: pushq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: pushq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: pushq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: pushq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: pushq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: pushq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 56 -; SSE2-NEXT: .cfi_offset %rbx, -56 -; SSE2-NEXT: .cfi_offset %r12, -48 -; SSE2-NEXT: .cfi_offset %r13, -40 -; SSE2-NEXT: .cfi_offset %r14, -32 -; SSE2-NEXT: .cfi_offset %r15, -24 -; SSE2-NEXT: .cfi_offset %rbp, -16 ; SSE2-NEXT: pshufd {{.*#+}} xmm8 = xmm3[2,3,2,3] ; SSE2-NEXT: movq %xmm3, %rbx ; SSE2-NEXT: pshufd {{.*#+}} xmm3 = xmm2[2,3,2,3] @@ -2194,39 +2182,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE2-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE2-NEXT: popq %rbx -; SSE2-NEXT: .cfi_def_cfa_offset 48 ; SSE2-NEXT: popq %r12 -; SSE2-NEXT: .cfi_def_cfa_offset 40 ; SSE2-NEXT: popq %r13 -; SSE2-NEXT: .cfi_def_cfa_offset 32 ; SSE2-NEXT: popq %r14 -; SSE2-NEXT: .cfi_def_cfa_offset 24 ; SSE2-NEXT: popq %r15 -; SSE2-NEXT: .cfi_def_cfa_offset 16 ; SSE2-NEXT: popq %rbp -; SSE2-NEXT: .cfi_def_cfa_offset 8 ; SSE2-NEXT: retq ; ; SSE4-LABEL: test_ext_v8i64: ; SSE4: # %bb.0: ; SSE4-NEXT: pushq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: pushq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: pushq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: pushq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: pushq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: pushq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 56 -; SSE4-NEXT: .cfi_offset %rbx, -56 -; SSE4-NEXT: .cfi_offset %r12, -48 -; SSE4-NEXT: .cfi_offset %r13, -40 -; SSE4-NEXT: .cfi_offset %r14, -32 -; SSE4-NEXT: .cfi_offset %r15, -24 -; SSE4-NEXT: .cfi_offset %rbp, -16 ; SSE4-NEXT: pextrq $1, %xmm3, %r14 ; SSE4-NEXT: movq %xmm2, %r13 ; SSE4-NEXT: pextrq $1, %xmm2, %rbp @@ -2292,39 +2262,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm2 = xmm2[0],xmm6[0] ; SSE4-NEXT: punpcklqdq {{.*#+}} xmm3 = xmm3[0],xmm7[0] ; SSE4-NEXT: popq %rbx -; SSE4-NEXT: .cfi_def_cfa_offset 48 ; SSE4-NEXT: popq %r12 -; SSE4-NEXT: .cfi_def_cfa_offset 40 ; SSE4-NEXT: popq %r13 -; SSE4-NEXT: .cfi_def_cfa_offset 32 ; SSE4-NEXT: popq %r14 -; SSE4-NEXT: .cfi_def_cfa_offset 24 ; SSE4-NEXT: popq %r15 -; SSE4-NEXT: .cfi_def_cfa_offset 16 ; SSE4-NEXT: popq %rbp -; SSE4-NEXT: .cfi_def_cfa_offset 8 ; SSE4-NEXT: retq ; ; AVX1-LABEL: test_ext_v8i64: ; AVX1: # %bb.0: ; AVX1-NEXT: pushq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: pushq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: pushq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: pushq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: pushq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: pushq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 56 -; AVX1-NEXT: .cfi_offset %rbx, -56 -; AVX1-NEXT: .cfi_offset %r12, -48 -; AVX1-NEXT: .cfi_offset %r13, -40 -; AVX1-NEXT: .cfi_offset %r14, -32 -; AVX1-NEXT: .cfi_offset %r15, -24 -; AVX1-NEXT: .cfi_offset %rbp, -16 ; AVX1-NEXT: vpextrq $1, %xmm1, %rbx ; AVX1-NEXT: vextractf128 $1, %ymm1, %xmm4 ; AVX1-NEXT: vmovq %xmm4, %r15 @@ -2396,39 +2348,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX1-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX1-NEXT: vinsertf128 $1, %xmm1, %ymm2, %ymm1 ; AVX1-NEXT: popq %rbx -; AVX1-NEXT: .cfi_def_cfa_offset 48 ; AVX1-NEXT: popq %r12 -; AVX1-NEXT: .cfi_def_cfa_offset 40 ; AVX1-NEXT: popq %r13 -; AVX1-NEXT: .cfi_def_cfa_offset 32 ; AVX1-NEXT: popq %r14 -; AVX1-NEXT: .cfi_def_cfa_offset 24 ; AVX1-NEXT: popq %r15 -; AVX1-NEXT: .cfi_def_cfa_offset 16 ; AVX1-NEXT: popq %rbp -; AVX1-NEXT: .cfi_def_cfa_offset 8 ; AVX1-NEXT: retq ; ; AVX2-LABEL: test_ext_v8i64: ; AVX2: # %bb.0: ; AVX2-NEXT: pushq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: pushq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: pushq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: pushq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: pushq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: pushq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 56 -; AVX2-NEXT: .cfi_offset %rbx, -56 -; AVX2-NEXT: .cfi_offset %r12, -48 -; AVX2-NEXT: .cfi_offset %r13, -40 -; AVX2-NEXT: .cfi_offset %r14, -32 -; AVX2-NEXT: .cfi_offset %r15, -24 -; AVX2-NEXT: .cfi_offset %rbp, -16 ; AVX2-NEXT: vpextrq $1, %xmm1, %rbx ; AVX2-NEXT: vextracti128 $1, %ymm1, %xmm4 ; AVX2-NEXT: vmovq %xmm4, %r15 @@ -2500,39 +2434,21 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm2 = xmm7[0],xmm6[0] ; AVX2-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX2-NEXT: popq %rbx -; AVX2-NEXT: .cfi_def_cfa_offset 48 ; AVX2-NEXT: popq %r12 -; AVX2-NEXT: .cfi_def_cfa_offset 40 ; AVX2-NEXT: popq %r13 -; AVX2-NEXT: .cfi_def_cfa_offset 32 ; AVX2-NEXT: popq %r14 -; AVX2-NEXT: .cfi_def_cfa_offset 24 ; AVX2-NEXT: popq %r15 -; AVX2-NEXT: .cfi_def_cfa_offset 16 ; AVX2-NEXT: popq %rbp -; AVX2-NEXT: .cfi_def_cfa_offset 8 ; AVX2-NEXT: retq ; ; AVX512-LABEL: test_ext_v8i64: ; AVX512: # %bb.0: ; AVX512-NEXT: pushq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: pushq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: pushq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: pushq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: pushq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: pushq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 56 -; AVX512-NEXT: .cfi_offset %rbx, -56 -; AVX512-NEXT: .cfi_offset %r12, -48 -; AVX512-NEXT: .cfi_offset %r13, -40 -; AVX512-NEXT: .cfi_offset %r14, -32 -; AVX512-NEXT: .cfi_offset %r15, -24 -; AVX512-NEXT: .cfi_offset %rbp, -16 ; AVX512-NEXT: vpextrq $1, %xmm0, %r10 ; AVX512-NEXT: vextracti128 $1, %ymm0, %xmm2 ; AVX512-NEXT: vpextrq $1, %xmm2, %r13 @@ -2607,17 +2523,11 @@ define <8 x i64> @test_ext_v8i64(<8 x i64> %a0, <8 x i64> %a1) { ; AVX512-NEXT: vinserti128 $1, %xmm1, %ymm2, %ymm1 ; AVX512-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 ; AVX512-NEXT: popq %rbx -; AVX512-NEXT: .cfi_def_cfa_offset 48 ; AVX512-NEXT: popq %r12 -; AVX512-NEXT: .cfi_def_cfa_offset 40 ; AVX512-NEXT: popq %r13 -; AVX512-NEXT: .cfi_def_cfa_offset 32 ; AVX512-NEXT: popq %r14 -; AVX512-NEXT: .cfi_def_cfa_offset 24 ; AVX512-NEXT: popq %r15 -; AVX512-NEXT: .cfi_def_cfa_offset 16 ; AVX512-NEXT: popq %rbp -; AVX512-NEXT: .cfi_def_cfa_offset 8 ; AVX512-NEXT: retq %x0 = zext <8 x i64> %a0 to <8 x i128> %x1 = zext <8 x i64> %a1 to <8 x i128> -- GitLab From df762a1643bb5b0b3c907611d118c82d4b68a39d Mon Sep 17 00:00:00 2001 From: Mital Ashok Date: Mon, 29 Apr 2024 11:17:18 +0100 Subject: [PATCH 202/301] [SemaCXX] Recognise initializer_list injected-class-name types as initializer_lists (#90210) This allows the implicitly-generated deduction guide for the copy constructor to be recognised as an initializer-list constructor, allowing CTAD for std::initializer_list --- clang/docs/ReleaseNotes.rst | 2 ++ clang/lib/Sema/SemaDeclCXX.cpp | 16 +++++++++++----- clang/lib/Sema/SemaInit.cpp | 2 -- .../cxx1z-class-template-argument-deduction.cpp | 11 ++++++++--- 4 files changed, 21 insertions(+), 10 deletions(-) diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 64a523a6f25f..50cc9924233b 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -590,6 +590,8 @@ Bug Fixes to C++ Support - Fixed a use-after-free bug in parsing of type constraints with default arguments that involve lambdas. (#GH67235) - Fixed bug in which the body of a consteval lambda within a template was not parsed as within an immediate function context. +- Fix CTAD for ``std::initializer_list``. This allows ``std::initializer_list{1, 2, 3}`` to be deduced as + ``std::initializer_list`` as intended. Bug Fixes to AST Handling ^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/lib/Sema/SemaDeclCXX.cpp b/clang/lib/Sema/SemaDeclCXX.cpp index 1a71a37c0732..338b0ec1e099 100644 --- a/clang/lib/Sema/SemaDeclCXX.cpp +++ b/clang/lib/Sema/SemaDeclCXX.cpp @@ -12054,11 +12054,17 @@ bool Sema::isStdInitializerList(QualType Ty, QualType *Element) { Template = Specialization->getSpecializedTemplate(); Arguments = Specialization->getTemplateArgs().data(); - } else if (const TemplateSpecializationType *TST = - Ty->getAs()) { - Template = dyn_cast_or_null( - TST->getTemplateName().getAsTemplateDecl()); - Arguments = TST->template_arguments().begin(); + } else { + const TemplateSpecializationType *TST = nullptr; + if (auto *ICN = Ty->getAs()) + TST = ICN->getInjectedTST(); + else + TST = Ty->getAs(); + if (TST) { + Template = dyn_cast_or_null( + TST->getTemplateName().getAsTemplateDecl()); + Arguments = TST->template_arguments().begin(); + } } if (!Template) return false; diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 003a157990d3..842d165c60d9 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -10790,8 +10790,6 @@ QualType Sema::DeduceTemplateSpecializationFromInitializer( // FIXME: Perform "exact type" matching first, per CWG discussion? // Or implement this via an implied 'T(T) -> T' deduction guide? - // FIXME: Do we need/want a std::initializer_list special case? - // Look up deduction guides, including those synthesized from constructors. // // C++1z [over.match.class.deduct]p1: diff --git a/clang/test/SemaCXX/cxx1z-class-template-argument-deduction.cpp b/clang/test/SemaCXX/cxx1z-class-template-argument-deduction.cpp index 2f067ea53a50..90404f115c75 100644 --- a/clang/test/SemaCXX/cxx1z-class-template-argument-deduction.cpp +++ b/clang/test/SemaCXX/cxx1z-class-template-argument-deduction.cpp @@ -12,14 +12,19 @@ namespace std { size_t n; initializer_list(); }; - // FIXME: This should probably not be necessary. - template initializer_list(initializer_list) -> initializer_list; } template constexpr bool has_type(...) { return false; } template constexpr bool has_type(T&) { return true; } -std::initializer_list il = {1, 2, 3, 4, 5}; +std::initializer_list il1 = {1, 2, 3, 4, 5}; +auto il2 = std::initializer_list{1, 2, 3, 4}; +auto il3 = std::initializer_list{il1}; +auto il4 = std::initializer_list{il1, il1, il1}; +static_assert(has_type>(il1)); +static_assert(has_type>(il2)); +static_assert(has_type>(il3)); +static_assert(has_type>>(il4)); template struct vector { template vector(Iter, Iter); -- GitLab From d72146f47156dc645b1c0a4cb9c72f01e6d6dd0e Mon Sep 17 00:00:00 2001 From: Utkarsh Saxena Date: Mon, 29 Apr 2024 12:33:46 +0200 Subject: [PATCH 203/301] Re-apply "Emit missing cleanups for stmt-expr" and other commits (#89154) Latest diff: https://github.com/llvm/llvm-project/pull/89154/files/f1ab4c2677394bbfc985d9680d5eecd7b2e6a882..adf9bc902baddb156c83ce0f8ec03c142e806d45 We address two additional bugs here: ### Problem 1: Deactivated normal cleanup still runs, leading to double-free Consider the following: ```cpp struct A { }; struct B { B(const A&); }; struct S { A a; B b; }; int AcceptS(S s); void Accept2(int x, int y); void Test() { Accept2(AcceptS({.a = A{}, .b = A{}}), ({ return; 0; })); } ``` We add cleanups as follows: 1. push dtor for field `S::a` 2. push dtor for temp `A{}` (used by ` B(const A&)` in `.b = A{}`) 3. push dtor for field `S::b` 4. Deactivate 3 `S::b`-> This pops the cleanup. 5. Deactivate 1 `S::a` -> Does not pop the cleanup as *2* is top. Should create _active flag_!! 6. push dtor for `~S()`. 7. ... It is important to deactivate **5** using active flags. Without the active flags, the `return` will fallthrough it and would run both `~S()` and dtor `S::a` leading to **double free** of `~A()`. In this patch, we unconditionally emit active flags while deactivating normal cleanups. These flags are deleted later by the `AllocaTracker` if the cleanup is not emitted. ### Problem 2: Missing cleanup for conditional lifetime extension We push 2 cleanups for lifetime-extended cleanup. The first cleanup is useful if we exit from the middle of the expression (stmt-expr/coro suspensions). This is deactivated after full-expr, and a new cleanup is pushed, extending the lifetime of the temporaries (to the scope of the reference being initialized). If this lifetime extension happens to be conditional, then we use active flags to remember whether the branch was taken and if the object was initialized. Previously, we used a **single** active flag, which was used by both cleanups. This is wrong because the first cleanup will be forced to deactivate after the full-expr and therefore this **active** flag will always be **inactive**. The dtor for the lifetime extended entity would not run as it always sees an **inactive** flag. In this patch, we solve this using two separate active flags for both cleanups. Both of them are activated if the conditional branch is taken, but only one of them is deactivated after the full-expr. --- Fixes https://github.com/llvm/llvm-project/issues/63818 Fixes https://github.com/llvm/llvm-project/issues/88478 --- Previous PR logs: 1. https://github.com/llvm/llvm-project/pull/85398 2. https://github.com/llvm/llvm-project/pull/88670 3. https://github.com/llvm/llvm-project/pull/88751 4. https://github.com/llvm/llvm-project/pull/88884 --- clang/docs/ReleaseNotes.rst | 4 + clang/lib/CodeGen/CGCall.cpp | 13 +- clang/lib/CodeGen/CGCleanup.cpp | 76 +-- clang/lib/CodeGen/CGCleanup.h | 57 +- clang/lib/CodeGen/CGDecl.cpp | 87 ++- clang/lib/CodeGen/CGExpr.cpp | 12 +- clang/lib/CodeGen/CGExprAgg.cpp | 87 +-- clang/lib/CodeGen/CGExprCXX.cpp | 38 +- clang/lib/CodeGen/CodeGenFunction.cpp | 6 + clang/lib/CodeGen/CodeGenFunction.h | 99 +++- clang/test/CodeGenCXX/blocks.cpp | 4 +- .../CodeGenCXX/control-flow-in-stmt-expr.cpp | 522 ++++++++++++++++++ .../coro-suspend-cleanups.cpp | 93 ++++ .../test/CodeGenObjC/arc-blocks-exceptions.m | 15 +- clang/test/CodeGenObjC/arc-blocks.m | 4 +- 15 files changed, 949 insertions(+), 168 deletions(-) create mode 100644 clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp create mode 100644 clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 50cc9924233b..604782ca43dd 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -460,6 +460,10 @@ Bug Fixes in This Version - Fixed an assertion failure on invalid InitListExpr in C89 mode (#GH88008). +- Fixed missing destructor calls when we branch from middle of an expression. + This could happen through a branch in stmt-expr or in an expression containing a coroutine + suspension. Fixes (#GH63818) (#GH88478). + - Clang will no longer diagnose an erroneous non-dependent ``switch`` condition during instantiation, and instead will only diagnose it once, during checking of the function template. diff --git a/clang/lib/CodeGen/CGCall.cpp b/clang/lib/CodeGen/CGCall.cpp index d2d92140b6b2..69548902dc43 100644 --- a/clang/lib/CodeGen/CGCall.cpp +++ b/clang/lib/CodeGen/CGCall.cpp @@ -4698,11 +4698,11 @@ void CodeGenFunction::EmitCallArg(CallArgList &args, const Expr *E, AggValueSlot Slot = args.isUsingInAlloca() ? createPlaceholderSlot(*this, type) : CreateAggTemp(type, "agg.tmp"); - bool DestroyedInCallee = true, NeedsEHCleanup = true; + bool DestroyedInCallee = true, NeedsCleanup = true; if (const auto *RD = type->getAsCXXRecordDecl()) DestroyedInCallee = RD->hasNonTrivialDestructor(); else - NeedsEHCleanup = needsEHCleanup(type.isDestructedType()); + NeedsCleanup = type.isDestructedType(); if (DestroyedInCallee) Slot.setExternallyDestructed(); @@ -4711,14 +4711,15 @@ void CodeGenFunction::EmitCallArg(CallArgList &args, const Expr *E, RValue RV = Slot.asRValue(); args.add(RV, type); - if (DestroyedInCallee && NeedsEHCleanup) { + if (DestroyedInCallee && NeedsCleanup) { // Create a no-op GEP between the placeholder and the cleanup so we can // RAUW it successfully. It also serves as a marker of the first // instruction where the cleanup is active. - pushFullExprCleanup(EHCleanup, Slot.getAddress(), - type); + pushFullExprCleanup(NormalAndEHCleanup, + Slot.getAddress(), type); // This unreachable is a temporary marker which will be removed later. - llvm::Instruction *IsActive = Builder.CreateUnreachable(); + llvm::Instruction *IsActive = + Builder.CreateFlagLoad(llvm::Constant::getNullValue(Int8PtrTy)); args.addArgCleanupDeactivation(EHStack.stable_begin(), IsActive); } return; diff --git a/clang/lib/CodeGen/CGCleanup.cpp b/clang/lib/CodeGen/CGCleanup.cpp index e6f8e6873004..469e0363b744 100644 --- a/clang/lib/CodeGen/CGCleanup.cpp +++ b/clang/lib/CodeGen/CGCleanup.cpp @@ -634,12 +634,19 @@ static void destroyOptimisticNormalEntry(CodeGenFunction &CGF, /// Pops a cleanup block. If the block includes a normal cleanup, the /// current insertion point is threaded through the cleanup, as are /// any branch fixups on the cleanup. -void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { +void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough, + bool ForDeactivation) { assert(!EHStack.empty() && "cleanup stack is empty!"); assert(isa(*EHStack.begin()) && "top not a cleanup!"); EHCleanupScope &Scope = cast(*EHStack.begin()); assert(Scope.getFixupDepth() <= EHStack.getNumBranchFixups()); + // If we are deactivating a normal cleanup, we need to pretend that the + // fallthrough is unreachable. We restore this IP before returning. + CGBuilderTy::InsertPoint NormalDeactivateOrigIP; + if (ForDeactivation && (Scope.isNormalCleanup() || !getLangOpts().EHAsynch)) { + NormalDeactivateOrigIP = Builder.saveAndClearIP(); + } // Remember activation information. bool IsActive = Scope.isActive(); Address NormalActiveFlag = @@ -667,7 +674,8 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { // - whether there's a fallthrough llvm::BasicBlock *FallthroughSource = Builder.GetInsertBlock(); - bool HasFallthrough = (FallthroughSource != nullptr && IsActive); + bool HasFallthrough = + FallthroughSource != nullptr && (IsActive || HasExistingBranches); // Branch-through fall-throughs leave the insertion point set to the // end of the last cleanup, which points to the current scope. The @@ -692,7 +700,11 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { // If we have a prebranched fallthrough into an inactive normal // cleanup, rewrite it so that it leads to the appropriate place. - if (Scope.isNormalCleanup() && HasPrebranchedFallthrough && !IsActive) { + if (Scope.isNormalCleanup() && HasPrebranchedFallthrough && + !RequiresNormalCleanup) { + // FIXME: Come up with a program which would need forwarding prebranched + // fallthrough and add tests. Otherwise delete this and assert against it. + assert(!IsActive); llvm::BasicBlock *prebranchDest; // If the prebranch is semantically branching through the next @@ -724,6 +736,8 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { EHStack.popCleanup(); // safe because there are no fixups assert(EHStack.getNumBranchFixups() == 0 || EHStack.hasNormalCleanups()); + if (NormalDeactivateOrigIP.isSet()) + Builder.restoreIP(NormalDeactivateOrigIP); return; } @@ -760,11 +774,19 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { if (!RequiresNormalCleanup) { // Mark CPP scope end for passed-by-value Arg temp // per Windows ABI which is "normally" Cleanup in callee - if (IsEHa && getInvokeDest() && Builder.GetInsertBlock()) { - if (Personality.isMSVCXXPersonality()) + if (IsEHa && getInvokeDest()) { + // If we are deactivating a normal cleanup then we don't have a + // fallthrough. Restore original IP to emit CPP scope ends in the correct + // block. + if (NormalDeactivateOrigIP.isSet()) + Builder.restoreIP(NormalDeactivateOrigIP); + if (Personality.isMSVCXXPersonality() && Builder.GetInsertBlock()) EmitSehCppScopeEnd(); + if (NormalDeactivateOrigIP.isSet()) + NormalDeactivateOrigIP = Builder.saveAndClearIP(); } destroyOptimisticNormalEntry(*this, Scope); + Scope.MarkEmitted(); EHStack.popCleanup(); } else { // If we have a fallthrough and no other need for the cleanup, @@ -781,6 +803,7 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { } destroyOptimisticNormalEntry(*this, Scope); + Scope.MarkEmitted(); EHStack.popCleanup(); EmitCleanup(*this, Fn, cleanupFlags, NormalActiveFlag); @@ -916,6 +939,7 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { } // IV. Pop the cleanup and emit it. + Scope.MarkEmitted(); EHStack.popCleanup(); assert(EHStack.hasNormalCleanups() == HasEnclosingCleanups); @@ -984,6 +1008,8 @@ void CodeGenFunction::PopCleanupBlock(bool FallthroughIsBranchThrough) { } } + if (NormalDeactivateOrigIP.isSet()) + Builder.restoreIP(NormalDeactivateOrigIP); assert(EHStack.hasNormalCleanups() || EHStack.getNumBranchFixups() == 0); // Emit the EH cleanup if required. @@ -1143,25 +1169,6 @@ void CodeGenFunction::EmitBranchThroughCleanup(JumpDest Dest) { Builder.ClearInsertionPoint(); } -static bool IsUsedAsNormalCleanup(EHScopeStack &EHStack, - EHScopeStack::stable_iterator C) { - // If we needed a normal block for any reason, that counts. - if (cast(*EHStack.find(C)).getNormalBlock()) - return true; - - // Check whether any enclosed cleanups were needed. - for (EHScopeStack::stable_iterator - I = EHStack.getInnermostNormalCleanup(); - I != C; ) { - assert(C.strictlyEncloses(I)); - EHCleanupScope &S = cast(*EHStack.find(I)); - if (S.getNormalBlock()) return true; - I = S.getEnclosingNormalCleanup(); - } - - return false; -} - static bool IsUsedAsEHCleanup(EHScopeStack &EHStack, EHScopeStack::stable_iterator cleanup) { // If we needed an EH block for any reason, that counts. @@ -1210,8 +1217,7 @@ static void SetupCleanupBlockActivation(CodeGenFunction &CGF, // Calculate whether the cleanup was used: // - as a normal cleanup - if (Scope.isNormalCleanup() && - (isActivatedInConditional || IsUsedAsNormalCleanup(CGF.EHStack, C))) { + if (Scope.isNormalCleanup()) { Scope.setTestFlagInNormalCleanup(); needFlag = true; } @@ -1224,13 +1230,16 @@ static void SetupCleanupBlockActivation(CodeGenFunction &CGF, } // If it hasn't yet been used as either, we're done. - if (!needFlag) return; + if (!needFlag) + return; Address var = Scope.getActiveFlag(); if (!var.isValid()) { + CodeGenFunction::AllocaTrackerRAII AllocaTracker(CGF); var = CGF.CreateTempAlloca(CGF.Builder.getInt1Ty(), CharUnits::One(), "cleanup.isactive"); Scope.setActiveFlag(var); + Scope.AddAuxAllocas(AllocaTracker.Take()); assert(dominatingIP && "no existing variable and no dominating IP!"); @@ -1273,17 +1282,8 @@ void CodeGenFunction::DeactivateCleanupBlock(EHScopeStack::stable_iterator C, // to the current RunCleanupsScope. if (C == EHStack.stable_begin() && CurrentCleanupScopeDepth.strictlyEncloses(C)) { - // Per comment below, checking EHAsynch is not really necessary - // it's there to assure zero-impact w/o EHAsynch option - if (!Scope.isNormalCleanup() && getLangOpts().EHAsynch) { - PopCleanupBlock(); - } else { - // If it's a normal cleanup, we need to pretend that the - // fallthrough is unreachable. - CGBuilderTy::InsertPoint SavedIP = Builder.saveAndClearIP(); - PopCleanupBlock(); - Builder.restoreIP(SavedIP); - } + PopCleanupBlock(/*FallthroughIsBranchThrough=*/false, + /*ForDeactivation=*/true); return; } diff --git a/clang/lib/CodeGen/CGCleanup.h b/clang/lib/CodeGen/CGCleanup.h index 03e4a29d7b3d..c73c97146abc 100644 --- a/clang/lib/CodeGen/CGCleanup.h +++ b/clang/lib/CodeGen/CGCleanup.h @@ -16,8 +16,11 @@ #include "EHScopeStack.h" #include "Address.h" +#include "llvm/ADT/STLExtras.h" +#include "llvm/ADT/SetVector.h" #include "llvm/ADT/SmallPtrSet.h" #include "llvm/ADT/SmallVector.h" +#include "llvm/IR/Instruction.h" namespace llvm { class BasicBlock; @@ -266,6 +269,51 @@ class alignas(8) EHCleanupScope : public EHScope { }; mutable struct ExtInfo *ExtInfo; + /// Erases auxillary allocas and their usages for an unused cleanup. + /// Cleanups should mark these allocas as 'used' if the cleanup is + /// emitted, otherwise these instructions would be erased. + struct AuxillaryAllocas { + SmallVector AuxAllocas; + bool used = false; + + // Records a potentially unused instruction to be erased later. + void Add(llvm::AllocaInst *Alloca) { AuxAllocas.push_back(Alloca); } + + // Mark all recorded instructions as used. These will not be erased later. + void MarkUsed() { + used = true; + AuxAllocas.clear(); + } + + ~AuxillaryAllocas() { + if (used) + return; + llvm::SetVector Uses; + for (auto *Inst : llvm::reverse(AuxAllocas)) + CollectUses(Inst, Uses); + // Delete uses in the reverse order of insertion. + for (auto *I : llvm::reverse(Uses)) + I->eraseFromParent(); + } + + private: + void CollectUses(llvm::Instruction *I, + llvm::SetVector &Uses) { + if (!I || !Uses.insert(I)) + return; + for (auto *User : I->users()) + CollectUses(cast(User), Uses); + } + }; + mutable struct AuxillaryAllocas *AuxAllocas; + + AuxillaryAllocas &getAuxillaryAllocas() { + if (!AuxAllocas) { + AuxAllocas = new struct AuxillaryAllocas(); + } + return *AuxAllocas; + } + /// The number of fixups required by enclosing scopes (not including /// this one). If this is the top cleanup scope, all the fixups /// from this index onwards belong to this scope. @@ -298,7 +346,7 @@ public: EHScopeStack::stable_iterator enclosingEH) : EHScope(EHScope::Cleanup, enclosingEH), EnclosingNormal(enclosingNormal), NormalBlock(nullptr), - ActiveFlag(Address::invalid()), ExtInfo(nullptr), + ActiveFlag(Address::invalid()), ExtInfo(nullptr), AuxAllocas(nullptr), FixupDepth(fixupDepth) { CleanupBits.IsNormalCleanup = isNormal; CleanupBits.IsEHCleanup = isEH; @@ -312,8 +360,15 @@ public: } void Destroy() { + if (AuxAllocas) + delete AuxAllocas; delete ExtInfo; } + void AddAuxAllocas(llvm::SmallVector Allocas) { + for (auto *Alloca : Allocas) + getAuxillaryAllocas().Add(Alloca); + } + void MarkEmitted() { getAuxillaryAllocas().MarkUsed(); } // Objects of EHCleanupScope are not destructed. Use Destroy(). ~EHCleanupScope() = delete; diff --git a/clang/lib/CodeGen/CGDecl.cpp b/clang/lib/CodeGen/CGDecl.cpp index ce6d6d895607..9cc67cdbe424 100644 --- a/clang/lib/CodeGen/CGDecl.cpp +++ b/clang/lib/CodeGen/CGDecl.cpp @@ -19,6 +19,7 @@ #include "CodeGenFunction.h" #include "CodeGenModule.h" #include "ConstantEmitter.h" +#include "EHScopeStack.h" #include "PatternInit.h" #include "TargetInfo.h" #include "clang/AST/ASTContext.h" @@ -35,6 +36,7 @@ #include "llvm/Analysis/ValueTracking.h" #include "llvm/IR/DataLayout.h" #include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/Intrinsics.h" #include "llvm/IR/Type.h" #include @@ -2201,6 +2203,27 @@ void CodeGenFunction::pushDestroy(CleanupKind cleanupKind, Address addr, destroyer, useEHCleanupForArray); } +// Pushes a destroy and defers its deactivation until its +// CleanupDeactivationScope is exited. +void CodeGenFunction::pushDestroyAndDeferDeactivation( + QualType::DestructionKind dtorKind, Address addr, QualType type) { + assert(dtorKind && "cannot push destructor for trivial type"); + + CleanupKind cleanupKind = getCleanupKind(dtorKind); + pushDestroyAndDeferDeactivation( + cleanupKind, addr, type, getDestroyer(dtorKind), cleanupKind & EHCleanup); +} + +void CodeGenFunction::pushDestroyAndDeferDeactivation( + CleanupKind cleanupKind, Address addr, QualType type, Destroyer *destroyer, + bool useEHCleanupForArray) { + llvm::Instruction *DominatingIP = + Builder.CreateFlagLoad(llvm::Constant::getNullValue(Int8PtrTy)); + pushDestroy(cleanupKind, addr, type, destroyer, useEHCleanupForArray); + DeferredDeactivationCleanupStack.push_back( + {EHStack.stable_begin(), DominatingIP}); +} + void CodeGenFunction::pushStackRestore(CleanupKind Kind, Address SPMem) { EHStack.pushCleanup(Kind, SPMem); } @@ -2217,39 +2240,48 @@ void CodeGenFunction::pushLifetimeExtendedDestroy(CleanupKind cleanupKind, // If we're not in a conditional branch, we don't need to bother generating a // conditional cleanup. if (!isInConditionalBranch()) { - // Push an EH-only cleanup for the object now. // FIXME: When popping normal cleanups, we need to keep this EH cleanup // around in case a temporary's destructor throws an exception. - if (cleanupKind & EHCleanup) - EHStack.pushCleanup( - static_cast(cleanupKind & ~NormalCleanup), addr, type, - destroyer, useEHCleanupForArray); + // Add the cleanup to the EHStack. After the full-expr, this would be + // deactivated before being popped from the stack. + pushDestroyAndDeferDeactivation(cleanupKind, addr, type, destroyer, + useEHCleanupForArray); + + // Since this is lifetime-extended, push it once again to the EHStack after + // the full expression. return pushCleanupAfterFullExprWithActiveFlag( - cleanupKind, Address::invalid(), addr, type, destroyer, useEHCleanupForArray); + cleanupKind, Address::invalid(), addr, type, destroyer, + useEHCleanupForArray); } // Otherwise, we should only destroy the object if it's been initialized. - // Re-use the active flag and saved address across both the EH and end of - // scope cleanups. - using SavedType = typename DominatingValue
::saved_type; using ConditionalCleanupType = EHScopeStack::ConditionalCleanup; - - Address ActiveFlag = createCleanupActiveFlag(); - SavedType SavedAddr = saveValueInCond(addr); - - if (cleanupKind & EHCleanup) { - EHStack.pushCleanup( - static_cast(cleanupKind & ~NormalCleanup), SavedAddr, type, - destroyer, useEHCleanupForArray); - initFullExprCleanupWithFlag(ActiveFlag); - } - + DominatingValue
::saved_type SavedAddr = saveValueInCond(addr); + + // Remember to emit cleanup if we branch-out before end of full-expression + // (eg: through stmt-expr or coro suspensions). + AllocaTrackerRAII DeactivationAllocas(*this); + Address ActiveFlagForDeactivation = createCleanupActiveFlag(); + + pushCleanupAndDeferDeactivation( + cleanupKind, SavedAddr, type, destroyer, useEHCleanupForArray); + initFullExprCleanupWithFlag(ActiveFlagForDeactivation); + EHCleanupScope &cleanup = cast(*EHStack.begin()); + // Erase the active flag if the cleanup was not emitted. + cleanup.AddAuxAllocas(std::move(DeactivationAllocas).Take()); + + // Since this is lifetime-extended, push it once again to the EHStack after + // the full expression. + // The previous active flag would always be 'false' due to forced deferred + // deactivation. Use a separate flag for lifetime-extension to correctly + // remember if this branch was taken and the object was initialized. + Address ActiveFlagForLifetimeExt = createCleanupActiveFlag(); pushCleanupAfterFullExprWithActiveFlag( - cleanupKind, ActiveFlag, SavedAddr, type, destroyer, + cleanupKind, ActiveFlagForLifetimeExt, SavedAddr, type, destroyer, useEHCleanupForArray); } @@ -2442,9 +2474,9 @@ namespace { }; } // end anonymous namespace -/// pushIrregularPartialArrayCleanup - Push an EH cleanup to destroy -/// already-constructed elements of the given array. The cleanup -/// may be popped with DeactivateCleanupBlock or PopCleanupBlock. +/// pushIrregularPartialArrayCleanup - Push a NormalAndEHCleanup to +/// destroy already-constructed elements of the given array. The cleanup may be +/// popped with DeactivateCleanupBlock or PopCleanupBlock. /// /// \param elementType - the immediate element type of the array; /// possibly still an array type @@ -2453,10 +2485,9 @@ void CodeGenFunction::pushIrregularPartialArrayCleanup(llvm::Value *arrayBegin, QualType elementType, CharUnits elementAlign, Destroyer *destroyer) { - pushFullExprCleanup(EHCleanup, - arrayBegin, arrayEndPointer, - elementType, elementAlign, - destroyer); + pushFullExprCleanup( + NormalAndEHCleanup, arrayBegin, arrayEndPointer, elementType, + elementAlign, destroyer); } /// pushRegularPartialArrayCleanup - Push an EH cleanup to destroy diff --git a/clang/lib/CodeGen/CGExpr.cpp b/clang/lib/CodeGen/CGExpr.cpp index c94322f51e46..d96c7bb1e568 100644 --- a/clang/lib/CodeGen/CGExpr.cpp +++ b/clang/lib/CodeGen/CGExpr.cpp @@ -115,10 +115,16 @@ RawAddress CodeGenFunction::CreateTempAlloca(llvm::Type *Ty, CharUnits Align, llvm::AllocaInst *CodeGenFunction::CreateTempAlloca(llvm::Type *Ty, const Twine &Name, llvm::Value *ArraySize) { + llvm::AllocaInst *Alloca; if (ArraySize) - return Builder.CreateAlloca(Ty, ArraySize, Name); - return new llvm::AllocaInst(Ty, CGM.getDataLayout().getAllocaAddrSpace(), - ArraySize, Name, AllocaInsertPt); + Alloca = Builder.CreateAlloca(Ty, ArraySize, Name); + else + Alloca = new llvm::AllocaInst(Ty, CGM.getDataLayout().getAllocaAddrSpace(), + ArraySize, Name, AllocaInsertPt); + if (Allocas) { + Allocas->Add(Alloca); + } + return Alloca; } /// CreateDefaultAlignTempAlloca - This creates an alloca with the diff --git a/clang/lib/CodeGen/CGExprAgg.cpp b/clang/lib/CodeGen/CGExprAgg.cpp index 355fec42be44..44d476976a55 100644 --- a/clang/lib/CodeGen/CGExprAgg.cpp +++ b/clang/lib/CodeGen/CGExprAgg.cpp @@ -15,6 +15,7 @@ #include "CodeGenFunction.h" #include "CodeGenModule.h" #include "ConstantEmitter.h" +#include "EHScopeStack.h" #include "TargetInfo.h" #include "clang/AST/ASTContext.h" #include "clang/AST/Attr.h" @@ -24,6 +25,7 @@ #include "llvm/IR/Constants.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalVariable.h" +#include "llvm/IR/Instruction.h" #include "llvm/IR/IntrinsicInst.h" #include "llvm/IR/Intrinsics.h" using namespace clang; @@ -558,24 +560,27 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType, // For that, we'll need an EH cleanup. QualType::DestructionKind dtorKind = elementType.isDestructedType(); Address endOfInit = Address::invalid(); - EHScopeStack::stable_iterator cleanup; - llvm::Instruction *cleanupDominator = nullptr; - if (CGF.needsEHCleanup(dtorKind)) { + CodeGenFunction::CleanupDeactivationScope deactivation(CGF); + + if (dtorKind) { + CodeGenFunction::AllocaTrackerRAII allocaTracker(CGF); // In principle we could tell the cleanup where we are more // directly, but the control flow can get so varied here that it // would actually be quite complex. Therefore we go through an // alloca. + llvm::Instruction *dominatingIP = + Builder.CreateFlagLoad(llvm::ConstantInt::getNullValue(CGF.Int8PtrTy)); endOfInit = CGF.CreateTempAlloca(begin->getType(), CGF.getPointerAlign(), "arrayinit.endOfInit"); - cleanupDominator = Builder.CreateStore(begin, endOfInit); + Builder.CreateStore(begin, endOfInit); CGF.pushIrregularPartialArrayCleanup(begin, endOfInit, elementType, elementAlign, CGF.getDestroyer(dtorKind)); - cleanup = CGF.EHStack.stable_begin(); + cast(*CGF.EHStack.find(CGF.EHStack.stable_begin())) + .AddAuxAllocas(allocaTracker.Take()); - // Otherwise, remember that we didn't need a cleanup. - } else { - dtorKind = QualType::DK_none; + CGF.DeferredDeactivationCleanupStack.push_back( + {CGF.EHStack.stable_begin(), dominatingIP}); } llvm::Value *one = llvm::ConstantInt::get(CGF.SizeTy, 1); @@ -671,9 +676,6 @@ void AggExprEmitter::EmitArrayInit(Address DestPtr, llvm::ArrayType *AType, CGF.EmitBlock(endBB); } - - // Leave the partial-array cleanup if we entered one. - if (dtorKind) CGF.DeactivateCleanupBlock(cleanup, cleanupDominator); } //===----------------------------------------------------------------------===// @@ -1374,9 +1376,8 @@ AggExprEmitter::VisitLambdaExpr(LambdaExpr *E) { LValue SlotLV = CGF.MakeAddrLValue(Slot.getAddress(), E->getType()); // We'll need to enter cleanup scopes in case any of the element - // initializers throws an exception. - SmallVector Cleanups; - llvm::Instruction *CleanupDominator = nullptr; + // initializers throws an exception or contains branch out of the expressions. + CodeGenFunction::CleanupDeactivationScope scope(CGF); CXXRecordDecl::field_iterator CurField = E->getLambdaClass()->field_begin(); for (LambdaExpr::const_capture_init_iterator i = E->capture_init_begin(), @@ -1395,28 +1396,12 @@ AggExprEmitter::VisitLambdaExpr(LambdaExpr *E) { if (QualType::DestructionKind DtorKind = CurField->getType().isDestructedType()) { assert(LV.isSimple()); - if (CGF.needsEHCleanup(DtorKind)) { - if (!CleanupDominator) - CleanupDominator = CGF.Builder.CreateAlignedLoad( - CGF.Int8Ty, - llvm::Constant::getNullValue(CGF.Int8PtrTy), - CharUnits::One()); // placeholder - - CGF.pushDestroy(EHCleanup, LV.getAddress(CGF), CurField->getType(), - CGF.getDestroyer(DtorKind), false); - Cleanups.push_back(CGF.EHStack.stable_begin()); - } + if (DtorKind) + CGF.pushDestroyAndDeferDeactivation( + NormalAndEHCleanup, LV.getAddress(CGF), CurField->getType(), + CGF.getDestroyer(DtorKind), false); } } - - // Deactivate all the partial cleanups in reverse order, which - // generally means popping them. - for (unsigned i = Cleanups.size(); i != 0; --i) - CGF.DeactivateCleanupBlock(Cleanups[i-1], CleanupDominator); - - // Destroy the placeholder if we made one. - if (CleanupDominator) - CleanupDominator->eraseFromParent(); } void AggExprEmitter::VisitExprWithCleanups(ExprWithCleanups *E) { @@ -1705,14 +1690,7 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( // We'll need to enter cleanup scopes in case any of the element // initializers throws an exception. SmallVector cleanups; - llvm::Instruction *cleanupDominator = nullptr; - auto addCleanup = [&](const EHScopeStack::stable_iterator &cleanup) { - cleanups.push_back(cleanup); - if (!cleanupDominator) // create placeholder once needed - cleanupDominator = CGF.Builder.CreateAlignedLoad( - CGF.Int8Ty, llvm::Constant::getNullValue(CGF.Int8PtrTy), - CharUnits::One()); - }; + CodeGenFunction::CleanupDeactivationScope DeactivateCleanups(CGF); unsigned curInitIndex = 0; @@ -1735,10 +1713,8 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( CGF.EmitAggExpr(InitExprs[curInitIndex++], AggSlot); if (QualType::DestructionKind dtorKind = - Base.getType().isDestructedType()) { - CGF.pushDestroy(dtorKind, V, Base.getType()); - addCleanup(CGF.EHStack.stable_begin()); - } + Base.getType().isDestructedType()) + CGF.pushDestroyAndDeferDeactivation(dtorKind, V, Base.getType()); } } @@ -1815,10 +1791,10 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( if (QualType::DestructionKind dtorKind = field->getType().isDestructedType()) { assert(LV.isSimple()); - if (CGF.needsEHCleanup(dtorKind)) { - CGF.pushDestroy(EHCleanup, LV.getAddress(CGF), field->getType(), - CGF.getDestroyer(dtorKind), false); - addCleanup(CGF.EHStack.stable_begin()); + if (dtorKind) { + CGF.pushDestroyAndDeferDeactivation( + NormalAndEHCleanup, LV.getAddress(CGF), field->getType(), + CGF.getDestroyer(dtorKind), false); pushedCleanup = true; } } @@ -1831,17 +1807,6 @@ void AggExprEmitter::VisitCXXParenListOrInitListExpr( if (GEP->use_empty()) GEP->eraseFromParent(); } - - // Deactivate all the partial cleanups in reverse order, which - // generally means popping them. - assert((cleanupDominator || cleanups.empty()) && - "Missing cleanupDominator before deactivating cleanup blocks"); - for (unsigned i = cleanups.size(); i != 0; --i) - CGF.DeactivateCleanupBlock(cleanups[i-1], cleanupDominator); - - // Destroy the placeholder if we made one. - if (cleanupDominator) - cleanupDominator->eraseFromParent(); } void AggExprEmitter::VisitArrayInitLoopExpr(const ArrayInitLoopExpr *E, diff --git a/clang/lib/CodeGen/CGExprCXX.cpp b/clang/lib/CodeGen/CGExprCXX.cpp index 673ccef84d67..c18c36d3f3f3 100644 --- a/clang/lib/CodeGen/CGExprCXX.cpp +++ b/clang/lib/CodeGen/CGExprCXX.cpp @@ -1008,8 +1008,8 @@ void CodeGenFunction::EmitNewArrayInitializer( const Expr *Init = E->getInitializer(); Address EndOfInit = Address::invalid(); QualType::DestructionKind DtorKind = ElementType.isDestructedType(); - EHScopeStack::stable_iterator Cleanup; - llvm::Instruction *CleanupDominator = nullptr; + CleanupDeactivationScope deactivation(*this); + bool pushedCleanup = false; CharUnits ElementSize = getContext().getTypeSizeInChars(ElementType); CharUnits ElementAlign = @@ -1105,19 +1105,24 @@ void CodeGenFunction::EmitNewArrayInitializer( } // Enter a partial-destruction Cleanup if necessary. - if (needsEHCleanup(DtorKind)) { + if (DtorKind) { + AllocaTrackerRAII AllocaTracker(*this); // In principle we could tell the Cleanup where we are more // directly, but the control flow can get so varied here that it // would actually be quite complex. Therefore we go through an // alloca. + llvm::Instruction *DominatingIP = + Builder.CreateFlagLoad(llvm::ConstantInt::getNullValue(Int8PtrTy)); EndOfInit = CreateTempAlloca(BeginPtr.getType(), getPointerAlign(), "array.init.end"); - CleanupDominator = - Builder.CreateStore(BeginPtr.emitRawPointer(*this), EndOfInit); pushIrregularPartialArrayCleanup(BeginPtr.emitRawPointer(*this), EndOfInit, ElementType, ElementAlign, getDestroyer(DtorKind)); - Cleanup = EHStack.stable_begin(); + cast(*EHStack.find(EHStack.stable_begin())) + .AddAuxAllocas(AllocaTracker.Take()); + DeferredDeactivationCleanupStack.push_back( + {EHStack.stable_begin(), DominatingIP}); + pushedCleanup = true; } CharUnits StartAlign = CurPtr.getAlignment(); @@ -1164,9 +1169,6 @@ void CodeGenFunction::EmitNewArrayInitializer( // initialization. llvm::ConstantInt *ConstNum = dyn_cast(NumElements); if (ConstNum && ConstNum->getZExtValue() <= InitListElements) { - // If there was a Cleanup, deactivate it. - if (CleanupDominator) - DeactivateCleanupBlock(Cleanup, CleanupDominator); return; } @@ -1281,13 +1283,14 @@ void CodeGenFunction::EmitNewArrayInitializer( Builder.CreateStore(CurPtr.emitRawPointer(*this), EndOfInit); // Enter a partial-destruction Cleanup if necessary. - if (!CleanupDominator && needsEHCleanup(DtorKind)) { - llvm::Value *BeginPtrRaw = BeginPtr.emitRawPointer(*this); - llvm::Value *CurPtrRaw = CurPtr.emitRawPointer(*this); - pushRegularPartialArrayCleanup(BeginPtrRaw, CurPtrRaw, ElementType, + if (!pushedCleanup && needsEHCleanup(DtorKind)) { + llvm::Instruction *DominatingIP = + Builder.CreateFlagLoad(llvm::ConstantInt::getNullValue(Int8PtrTy)); + pushRegularPartialArrayCleanup(BeginPtr.emitRawPointer(*this), + CurPtr.emitRawPointer(*this), ElementType, ElementAlign, getDestroyer(DtorKind)); - Cleanup = EHStack.stable_begin(); - CleanupDominator = Builder.CreateUnreachable(); + DeferredDeactivationCleanupStack.push_back( + {EHStack.stable_begin(), DominatingIP}); } // Emit the initializer into this element. @@ -1295,10 +1298,7 @@ void CodeGenFunction::EmitNewArrayInitializer( AggValueSlot::DoesNotOverlap); // Leave the Cleanup if we entered one. - if (CleanupDominator) { - DeactivateCleanupBlock(Cleanup, CleanupDominator); - CleanupDominator->eraseFromParent(); - } + deactivation.ForceDeactivate(); // Advance to the next element by adjusting the pointer type as necessary. llvm::Value *NextPtr = Builder.CreateConstInBoundsGEP1_32( diff --git a/clang/lib/CodeGen/CodeGenFunction.cpp b/clang/lib/CodeGen/CodeGenFunction.cpp index 86a6ddd80cc1..87766a758311 100644 --- a/clang/lib/CodeGen/CodeGenFunction.cpp +++ b/clang/lib/CodeGen/CodeGenFunction.cpp @@ -91,6 +91,8 @@ CodeGenFunction::CodeGenFunction(CodeGenModule &cgm, bool suppressNewContext) CodeGenFunction::~CodeGenFunction() { assert(LifetimeExtendedCleanupStack.empty() && "failed to emit a cleanup"); + assert(DeferredDeactivationCleanupStack.empty() && + "missed to deactivate a cleanup"); if (getLangOpts().OpenMP && CurFn) CGM.getOpenMPRuntime().functionFinished(*this); @@ -346,6 +348,10 @@ static void EmitIfUsed(CodeGenFunction &CGF, llvm::BasicBlock *BB) { void CodeGenFunction::FinishFunction(SourceLocation EndLoc) { assert(BreakContinueStack.empty() && "mismatched push/pop in break/continue stack!"); + assert(LifetimeExtendedCleanupStack.empty() && + "mismatched push/pop of cleanups in EHStack!"); + assert(DeferredDeactivationCleanupStack.empty() && + "mismatched activate/deactivate of cleanups!"); bool OnlySimpleReturnStmts = NumSimpleReturnExprs > 0 && NumSimpleReturnExprs == NumReturnExprs diff --git a/clang/lib/CodeGen/CodeGenFunction.h b/clang/lib/CodeGen/CodeGenFunction.h index 33fb7a41912b..6e7417fc7f52 100644 --- a/clang/lib/CodeGen/CodeGenFunction.h +++ b/clang/lib/CodeGen/CodeGenFunction.h @@ -39,6 +39,7 @@ #include "llvm/ADT/MapVector.h" #include "llvm/ADT/SmallVector.h" #include "llvm/Frontend/OpenMP/OMPIRBuilder.h" +#include "llvm/IR/Instructions.h" #include "llvm/IR/ValueHandle.h" #include "llvm/Support/Debug.h" #include "llvm/Transforms/Utils/SanitizerStats.h" @@ -670,6 +671,51 @@ public: EHScopeStack EHStack; llvm::SmallVector LifetimeExtendedCleanupStack; + + // A stack of cleanups which were added to EHStack but have to be deactivated + // later before being popped or emitted. These are usually deactivated on + // exiting a `CleanupDeactivationScope` scope. For instance, after a + // full-expr. + // + // These are specially useful for correctly emitting cleanups while + // encountering branches out of expression (through stmt-expr or coroutine + // suspensions). + struct DeferredDeactivateCleanup { + EHScopeStack::stable_iterator Cleanup; + llvm::Instruction *DominatingIP; + }; + llvm::SmallVector DeferredDeactivationCleanupStack; + + // Enters a new scope for capturing cleanups which are deferred to be + // deactivated, all of which will be deactivated once the scope is exited. + struct CleanupDeactivationScope { + CodeGenFunction &CGF; + size_t OldDeactivateCleanupStackSize; + bool Deactivated; + CleanupDeactivationScope(CodeGenFunction &CGF) + : CGF(CGF), OldDeactivateCleanupStackSize( + CGF.DeferredDeactivationCleanupStack.size()), + Deactivated(false) {} + + void ForceDeactivate() { + assert(!Deactivated && "Deactivating already deactivated scope"); + auto &Stack = CGF.DeferredDeactivationCleanupStack; + for (size_t I = Stack.size(); I > OldDeactivateCleanupStackSize; I--) { + CGF.DeactivateCleanupBlock(Stack[I - 1].Cleanup, + Stack[I - 1].DominatingIP); + Stack[I - 1].DominatingIP->eraseFromParent(); + } + Stack.resize(OldDeactivateCleanupStackSize); + Deactivated = true; + } + + ~CleanupDeactivationScope() { + if (Deactivated) + return; + ForceDeactivate(); + } + }; + llvm::SmallVector SEHTryEpilogueStack; llvm::Instruction *CurrentFuncletPad = nullptr; @@ -875,6 +921,19 @@ public: new (Buffer + sizeof(Header) + sizeof(T)) RawAddress(ActiveFlag); } + // Push a cleanup onto EHStack and deactivate it later. It is usually + // deactivated when exiting a `CleanupDeactivationScope` (for example: after a + // full expression). + template + void pushCleanupAndDeferDeactivation(CleanupKind Kind, As... A) { + // Placeholder dominating IP for this cleanup. + llvm::Instruction *DominatingIP = + Builder.CreateFlagLoad(llvm::Constant::getNullValue(Int8PtrTy)); + EHStack.pushCleanup(Kind, A...); + DeferredDeactivationCleanupStack.push_back( + {EHStack.stable_begin(), DominatingIP}); + } + /// Set up the last cleanup that was pushed as a conditional /// full-expression cleanup. void initFullExprCleanup() { @@ -898,7 +957,8 @@ public: /// PopCleanupBlock - Will pop the cleanup entry on the stack and /// process all branch fixups. - void PopCleanupBlock(bool FallThroughIsBranchThrough = false); + void PopCleanupBlock(bool FallThroughIsBranchThrough = false, + bool ForDeactivation = false); /// DeactivateCleanupBlock - Deactivates the given cleanup block. /// The block cannot be reactivated. Pops it if it's the top of the @@ -926,6 +986,7 @@ public: class RunCleanupsScope { EHScopeStack::stable_iterator CleanupStackDepth, OldCleanupScopeDepth; size_t LifetimeExtendedCleanupStackSize; + CleanupDeactivationScope DeactivateCleanups; bool OldDidCallStackSave; protected: bool PerformCleanup; @@ -940,8 +1001,7 @@ public: public: /// Enter a new cleanup scope. explicit RunCleanupsScope(CodeGenFunction &CGF) - : PerformCleanup(true), CGF(CGF) - { + : DeactivateCleanups(CGF), PerformCleanup(true), CGF(CGF) { CleanupStackDepth = CGF.EHStack.stable_begin(); LifetimeExtendedCleanupStackSize = CGF.LifetimeExtendedCleanupStack.size(); @@ -971,6 +1031,7 @@ public: void ForceCleanup(std::initializer_list ValuesToReload = {}) { assert(PerformCleanup && "Already forced cleanup"); CGF.DidCallStackSave = OldDidCallStackSave; + DeactivateCleanups.ForceDeactivate(); CGF.PopCleanupBlocks(CleanupStackDepth, LifetimeExtendedCleanupStackSize, ValuesToReload); PerformCleanup = false; @@ -2160,6 +2221,11 @@ public: Address addr, QualType type); void pushDestroy(CleanupKind kind, Address addr, QualType type, Destroyer *destroyer, bool useEHCleanupForArray); + void pushDestroyAndDeferDeactivation(QualType::DestructionKind dtorKind, + Address addr, QualType type); + void pushDestroyAndDeferDeactivation(CleanupKind cleanupKind, Address addr, + QualType type, Destroyer *destroyer, + bool useEHCleanupForArray); void pushLifetimeExtendedDestroy(CleanupKind kind, Address addr, QualType type, Destroyer *destroyer, bool useEHCleanupForArray); @@ -2698,6 +2764,33 @@ public: TBAAAccessInfo *TBAAInfo = nullptr); LValue EmitLoadOfPointerLValue(Address Ptr, const PointerType *PtrTy); +private: + struct AllocaTracker { + void Add(llvm::AllocaInst *I) { Allocas.push_back(I); } + llvm::SmallVector Take() { return std::move(Allocas); } + + private: + llvm::SmallVector Allocas; + }; + AllocaTracker *Allocas = nullptr; + +public: + // Captures all the allocas created during the scope of its RAII object. + struct AllocaTrackerRAII { + AllocaTrackerRAII(CodeGenFunction &CGF) + : CGF(CGF), OldTracker(CGF.Allocas) { + CGF.Allocas = &Tracker; + } + ~AllocaTrackerRAII() { CGF.Allocas = OldTracker; } + + llvm::SmallVector Take() { return Tracker.Take(); } + + private: + CodeGenFunction &CGF; + AllocaTracker *OldTracker; + AllocaTracker Tracker; + }; + /// CreateTempAlloca - This creates an alloca and inserts it into the entry /// block if \p ArraySize is nullptr, otherwise inserts it at the current /// insertion point of the builder. The caller is responsible for setting an diff --git a/clang/test/CodeGenCXX/blocks.cpp b/clang/test/CodeGenCXX/blocks.cpp index eaab1890dfc4..afe078890553 100644 --- a/clang/test/CodeGenCXX/blocks.cpp +++ b/clang/test/CodeGenCXX/blocks.cpp @@ -149,8 +149,8 @@ namespace test5 { // CHECK-NEXT: [[X:%.*]] = alloca [[A:%.*]], align 4 // CHECK-NEXT: [[B:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[BLOCK:%.*]] = alloca [[BLOCK_T:.*]], align 8 - // CHECK-NEXT: [[CLEANUP_ACTIVE:%.*]] = alloca i1 // CHECK-NEXT: [[COND_CLEANUP_SAVE:%.*]] = alloca ptr, align 8 + // CHECK-NEXT: [[CLEANUP_ACTIVE:%.*]] = alloca i1 // CHECK-NEXT: [[T0:%.*]] = zext i1 // CHECK-NEXT: store i8 [[T0]], ptr [[COND]], align 1 // CHECK-NEXT: call void @_ZN5test51AC1Ev(ptr {{[^,]*}} [[X]]) @@ -162,8 +162,8 @@ namespace test5 { // CHECK-NOT: br // CHECK: [[CAPTURE:%.*]] = getelementptr inbounds [[BLOCK_T]], ptr [[BLOCK]], i32 0, i32 5 // CHECK-NEXT: call void @_ZN5test51AC1ERKS0_(ptr {{[^,]*}} [[CAPTURE]], ptr noundef nonnull align {{[0-9]+}} dereferenceable({{[0-9]+}}) [[X]]) - // CHECK-NEXT: store i1 true, ptr [[CLEANUP_ACTIVE]] // CHECK-NEXT: store ptr [[CAPTURE]], ptr [[COND_CLEANUP_SAVE]], align 8 + // CHECK-NEXT: store i1 true, ptr [[CLEANUP_ACTIVE]] // CHECK-NEXT: br label // CHECK: br label // CHECK: phi diff --git a/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp b/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp new file mode 100644 index 000000000000..ac466ee5bba4 --- /dev/null +++ b/clang/test/CodeGenCXX/control-flow-in-stmt-expr.cpp @@ -0,0 +1,522 @@ +// RUN: %clang_cc1 --std=c++20 -fexceptions -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck -check-prefixes=EH %s +// RUN: %clang_cc1 --std=c++20 -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck -check-prefixes=NOEH,CHECK %s + +struct Printy { + Printy(const char *name) : name(name) {} + ~Printy() {} + const char *name; +}; + +int foo() { return 2; } + +struct Printies { + Printy a; + Printy b; + Printy c; +}; + +void ParenInit() { + // CHECK-LABEL: define dso_local void @_Z9ParenInitv() + // CHECK: [[CLEANUP_DEST:%.+]] = alloca i32, align 4 + Printies ps(Printy("a"), + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + if (foo()) return; + // CHECK: if.then: + // CHECK-NEXT: store i32 1, ptr [[CLEANUP_DEST]], align 4 + // CHECK-NEXT: br label %cleanup + Printy("b"); + // CHECK: if.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + ({ + if (foo()) return; + // CHECK: if.then{{.*}}: + // CHECK-NEXT: store i32 1, ptr [[CLEANUP_DEST]], align 4 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %cleanup + Printy("c"); + // CHECK: if.end{{.*}}: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %return + })); + // CHECK: cleanup: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %return +} + +void break_in_stmt_expr() { + // Verify that the "break" in "if.then".calls dtor before jumping to "for.end". + + // CHECK-LABEL: define dso_local void @_Z18break_in_stmt_exprv() + Printies p{Printy("a"), + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + for (;;) { + Printies ps{ + Printy("b"), + // CHECK: for.cond: + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + if (foo()) { + break; + // CHECK: if.then: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %for.end + } + Printy("c"); + // CHECK: if.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("d")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %for.cond + } + Printy("e"); + // CHECK: for.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("f")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev +} + +void goto_in_stmt_expr() { + // Verify that: + // - correct branch fixups for deactivated normal cleanups are generated correctly. + + // CHECK-LABEL: define dso_local void @_Z17goto_in_stmt_exprv() + // CHECK: [[CLEANUP_DEST_SLOT:%cleanup.dest.slot.*]] = alloca i32, align 4 + { + Printies p1{Printy("a"), // CHECK: call void @_ZN6PrintyC1EPKc + ({ + { + Printies p2{Printy("b"), + // CHECK: call void @_ZN6PrintyC1EPKc + ({ + if (foo() == 1) { + goto in; + // CHECK: if.then: + // CHECK-NEXT: store i32 2, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: br label %[[CLEANUP1:.+]] + } + if (foo() == 2) { + goto out; + // CHECK: if.then{{.*}}: + // CHECK-NEXT: store i32 3, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: br label %[[CLEANUP1]] + } + Printy("c"); + // CHECK: if.end{{.*}}: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("d")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %in + + } + in: + Printy("e"); + // CHECK: in: ; preds = %if.end{{.*}}, %[[CLEANUP1]] + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + }), + Printy("f")}; + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZN8PrintiesD1Ev + // CHECK-NEXT: br label %out + } +out: + return; + // CHECK: out: + // CHECK-NEXT: ret void + + // CHECK: [[CLEANUP1]]: ; preds = %if.then{{.*}}, %if.then + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: %cleanup.dest = load i32, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: switch i32 %cleanup.dest, label %[[CLEANUP2:.+]] [ + // CHECK-NEXT: i32 2, label %in + // CHECK-NEXT: ] + + // CHECK: [[CLEANUP2]]: ; preds = %[[CLEANUP1]] + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: %cleanup.dest{{.*}} = load i32, ptr [[CLEANUP_DEST_SLOT]], align 4 + // CHECK-NEXT: switch i32 %cleanup.dest{{.*}}, label %unreachable [ + // CHECK-NEXT: i32 3, label %out + // CHECK-NEXT: ] +} + +void ArrayInit() { + // Printy arr[4] = {ctorA, ctorB, stmt-exprC, stmt-exprD}; + // Verify that: + // - We do the necessary stores for array cleanups (endOfInit and last constructed element). + // - We update the array init element correctly for ctorA, ctorB and stmt-exprC. + // - stmt-exprC and stmt-exprD share the array body dtor code (see %cleanup). + + // CHECK-LABEL: define dso_local void @_Z9ArrayInitv() + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + // CHECK: %cleanup.dest.slot = alloca i32, align 4 + // CHECK: %arrayinit.begin = getelementptr inbounds [4 x %struct.Printy], ptr %arr, i64 0, i64 0 + // CHECK: store ptr %arrayinit.begin, ptr %arrayinit.endOfInit, align 8 + Printy arr[4] = { + Printy("a"), + // CHECK: call void @_ZN6PrintyC1EPKc(ptr noundef nonnull align 8 dereferenceable(8) %arrayinit.begin, ptr noundef @.str) + // CHECK: [[ARRAYINIT_ELEMENT1:%.+]] = getelementptr inbounds %struct.Printy, ptr %arrayinit.begin, i64 1 + // CHECK: store ptr [[ARRAYINIT_ELEMENT1]], ptr %arrayinit.endOfInit, align 8 + Printy("b"), + // CHECK: call void @_ZN6PrintyC1EPKc(ptr noundef nonnull align 8 dereferenceable(8) [[ARRAYINIT_ELEMENT1]], ptr noundef @.str.1) + // CHECK: [[ARRAYINIT_ELEMENT2:%.+]] = getelementptr inbounds %struct.Printy, ptr [[ARRAYINIT_ELEMENT1]], i64 1 + // CHECK: store ptr [[ARRAYINIT_ELEMENT2]], ptr %arrayinit.endOfInit, align 8 + ({ + // CHECK: br i1 {{.*}}, label %if.then, label %if.end + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: store i32 1, ptr %cleanup.dest.slot, align 4 + // CHECK-NEXT: br label %cleanup + } + // CHECK: if.end: + Printy("c"); + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: %arrayinit.element2 = getelementptr inbounds %struct.Printy, ptr %arrayinit.element1, i64 1 + // CHECK-NEXT: store ptr %arrayinit.element2, ptr %arrayinit.endOfInit, align 8 + }), + ({ + // CHECK: br i1 {{%.+}} label %[[IF_THEN2:.+]], label %[[IF_END2:.+]] + if (foo()) { + return; + // CHECK: [[IF_THEN2]]: + // CHECK-NEXT: store i32 1, ptr %cleanup.dest.slot, align 4 + // CHECK-NEXT: br label %cleanup + } + // CHECK: [[IF_END2]]: + Printy("d"); + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: %array.begin = getelementptr inbounds [4 x %struct.Printy], ptr %arr, i32 0, i32 0 + // CHECK-NEXT: %0 = getelementptr inbounds %struct.Printy, ptr %array.begin, i64 4 + // CHECK-NEXT: br label %[[ARRAY_DESTROY_BODY1:.+]] + }), + }; + + // CHECK: [[ARRAY_DESTROY_BODY1]]: + // CHECK-NEXT: %arraydestroy.elementPast{{.*}} = phi ptr [ %0, %[[IF_END2]] ], [ %arraydestroy.element{{.*}}, %[[ARRAY_DESTROY_BODY1]] ] + // CHECK-NEXT: %arraydestroy.element{{.*}} = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast{{.*}}, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: %arraydestroy.done{{.*}} = icmp eq ptr %arraydestroy.element{{.*}}, %array.begin + // CHECK-NEXT: br i1 %arraydestroy.done{{.*}}, label %[[ARRAY_DESTROY_DONE1:.+]], label %[[ARRAY_DESTROY_BODY1]] + + // CHECK: [[ARRAY_DESTROY_DONE1]]: + // CHECK-NEXT: ret void + + // CHECK: cleanup: + // CHECK-NEXT: %1 = load ptr, ptr %arrayinit.endOfInit, align 8 + // CHECK-NEXT: %arraydestroy.isempty = icmp eq ptr %arrayinit.begin, %1 + // CHECK-NEXT: br i1 %arraydestroy.isempty, label %[[ARRAY_DESTROY_DONE2:.+]], label %[[ARRAY_DESTROY_BODY2:.+]] + + // CHECK: [[ARRAY_DESTROY_BODY2]]: + // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %1, %cleanup ], [ %arraydestroy.element, %[[ARRAY_DESTROY_BODY2]] ] + // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %arrayinit.begin + // CHECK-NEXT: br i1 %arraydestroy.done, label %[[ARRAY_DESTROY_DONE2]], label %[[ARRAY_DESTROY_BODY2]] + + // CHECK: [[ARRAY_DESTROY_DONE2]]: + // CHECK-NEXT: br label %[[ARRAY_DESTROY_DONE1]] +} + +void ArraySubobjects() { + struct S { + Printy arr1[2]; + Printy arr2[2]; + Printy p; + }; + // CHECK-LABEL: define dso_local void @_Z15ArraySubobjectsv() + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + S s{{Printy("a"), Printy("b")}, + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: call void @_ZN6PrintyC1EPKc + {Printy("a"), + // CHECK: [[ARRAYINIT_BEGIN:%.+]] = getelementptr inbounds [2 x %struct.Printy] + // CHECK: store ptr [[ARRAYINIT_BEGIN]], ptr %arrayinit.endOfInit, align 8 + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: [[ARRAYINIT_ELEMENT:%.+]] = getelementptr inbounds %struct.Printy + // CHECK: store ptr [[ARRAYINIT_ELEMENT]], ptr %arrayinit.endOfInit, align 8 + ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: [[V0:%.+]] = load ptr, ptr %arrayinit.endOfInit, align 8 + // CHECK-NEXT: %arraydestroy.isempty = icmp eq ptr [[ARRAYINIT_BEGIN]], [[V0]] + // CHECK-NEXT: br i1 %arraydestroy.isempty, label %[[ARRAY_DESTROY_DONE:.+]], label %[[ARRAY_DESTROY_BODY:.+]] + } + Printy("b"); + }) + }, + Printy("c") + // CHECK: if.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: call void @_ZZ15ArraySubobjectsvEN1SD1Ev + // CHECK-NEXT: br label %return + }; + // CHECK: return: + // CHECK-NEXT: ret void + + // CHECK: [[ARRAY_DESTROY_BODY]]: + // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %0, %if.then ], [ %arraydestroy.element, %[[ARRAY_DESTROY_BODY]] ] + // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, [[ARRAYINIT_BEGIN]] + // CHECK-NEXT: br i1 %arraydestroy.done, label %[[ARRAY_DESTROY_DONE]], label %[[ARRAY_DESTROY_BODY]] + + // CHECK: [[ARRAY_DESTROY_DONE]] + // CHECK-NEXT: [[ARRAY_BEGIN:%.+]] = getelementptr inbounds [2 x %struct.Printy], ptr %arr1, i32 0, i32 0 + // CHECK-NEXT: [[V1:%.+]] = getelementptr inbounds %struct.Printy, ptr [[ARRAY_BEGIN]], i64 2 + // CHECK-NEXT: br label %[[ARRAY_DESTROY_BODY2:.+]] + + // CHECK: [[ARRAY_DESTROY_BODY2]]: + // CHECK-NEXT: %arraydestroy.elementPast5 = phi ptr [ %1, %[[ARRAY_DESTROY_DONE]] ], [ %arraydestroy.element6, %[[ARRAY_DESTROY_BODY2]] ] + // CHECK-NEXT: %arraydestroy.element6 = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast5, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element6) + // CHECK-NEXT: %arraydestroy.done7 = icmp eq ptr %arraydestroy.element6, [[ARRAY_BEGIN]] + // CHECK-NEXT: br i1 %arraydestroy.done7, label %[[ARRAY_DESTROY_DONE2:.+]], label %[[ARRAY_DESTROY_BODY2]] + + + // CHECK: [[ARRAY_DESTROY_DONE2]]: + // CHECK-NEXT: br label %return +} + +void LambdaInit() { + // CHECK-LABEL: define dso_local void @_Z10LambdaInitv() + auto S = [a = Printy("a"), b = ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %return + } + Printy("b"); + })]() { return a; }; +} + +struct PrintyRefBind { + const Printy &a; + const Printy &b; +}; + +struct Temp { + Temp(); + ~Temp(); +}; +Temp CreateTemp(); +Printy CreatePrinty(); +Printy CreatePrinty(const Temp&); + +void LifetimeExtended() { + // CHECK-LABEL: define dso_local void @_Z16LifetimeExtendedv + PrintyRefBind ps = {Printy("a"), ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK-NEXT: call void @_ZN6PrintyD1Ev + // CHECK-NEXT: br label %return + } + Printy("b"); + })}; +} + +void ConditionalLifetimeExtended() { + // CHECK-LABEL: @_Z27ConditionalLifetimeExtendedv() + + // Verify that we create two cleanup flags. + // 1. First for the cleanup which is deactivated after full expression. + // 2. Second for the life-ext cleanup which is activated if the branch is taken. + + // Note: We use `CreateTemp()` to ensure that life-ext destroy cleanup is not at + // the top of EHStack on deactivation. This ensures using active flags. + + Printy* p1 = nullptr; + // CHECK: store i1 false, ptr [[BRANCH1_DEFERRED:%cleanup.cond]], align 1 + // CHECK-NEXT: store i1 false, ptr [[BRANCH1_LIFEEXT:%cleanup.cond.*]], align 1 + PrintyRefBind ps = { + p1 != nullptr ? static_cast(CreatePrinty()) + // CHECK: cond.true: + // CHECK-NEXT: call void @_Z12CreatePrintyv + // CHECK-NEXT: store i1 true, ptr [[BRANCH1_DEFERRED]], align 1 + // CHECK-NEXT: store i1 true, ptr [[BRANCH1_LIFEEXT]], align 1 + // CHECK-NEXT: br label %{{.*}} + : foo() ? static_cast(CreatePrinty(CreateTemp())) + : *p1, + ({ + if (foo()) return; + Printy("c"); + // CHECK: if.end: + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc + // CHECK-NEXT: store ptr + })}; + // CHECK-NEXT: store i1 false, ptr [[BRANCH1_DEFERRED]], align 1 + // CHECK-NEXT: store i32 0, ptr %cleanup.dest.slot, align 4 + // CHECK-NEXT: br label %cleanup + +} + +void NewArrayInit() { + // CHECK-LABEL: define dso_local void @_Z12NewArrayInitv() + // CHECK: %array.init.end = alloca ptr, align 8 + // CHECK: store ptr %0, ptr %array.init.end, align 8 + Printy *array = new Printy[3]{ + "a", + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: store ptr %array.exp.next, ptr %array.init.end, align 8 + "b", + // CHECK: call void @_ZN6PrintyC1EPKc + // CHECK: store ptr %array.exp.next1, ptr %array.init.end, align 8 + ({ + if (foo()) { + return; + // CHECK: if.then: + // CHECK: br i1 %arraydestroy.isempty, label %arraydestroy.done{{.*}}, label %arraydestroy.body + } + "b"; + // CHECK: if.end: + // CHECK: call void @_ZN6PrintyC1EPKc + })}; + // CHECK: arraydestroy.body: + // CHECK-NEXT: %arraydestroy.elementPast = phi ptr [ %{{.*}}, %if.then ], [ %arraydestroy.element, %arraydestroy.body ] + // CHECK-NEXT: %arraydestroy.element = getelementptr inbounds %struct.Printy, ptr %arraydestroy.elementPast, i64 -1 + // CHECK-NEXT: call void @_ZN6PrintyD1Ev(ptr noundef nonnull align 8 dereferenceable(8) %arraydestroy.element) + // CHECK-NEXT: %arraydestroy.done = icmp eq ptr %arraydestroy.element, %0 + // CHECK-NEXT: br i1 %arraydestroy.done, label %arraydestroy.done{{.*}}, label %arraydestroy.body + + // CHECK: arraydestroy.done{{.*}}: ; preds = %arraydestroy.body, %if.then + // CHECK-NEXT: br label %return +} + +void DestroyInConditionalCleanup() { + // EH-LABEL: DestroyInConditionalCleanupv() + // NOEH-LABEL: DestroyInConditionalCleanupv() + struct A { + A() {} + ~A() {} + }; + + struct Value { + Value(A) {} + ~Value() {} + }; + + struct V2 { + Value K; + Value V; + }; + // Verify we use conditional cleanups. + (void)(foo() ? V2{A(), A()} : V2{A(), A()}); + // NOEH: cond.true: + // NOEH: call void @_ZZ27DestroyInConditionalCleanupvEN1AC1Ev + // NOEH: store ptr %{{.*}}, ptr %cond-cleanup.save + + // EH: cond.true: + // EH: invoke void @_ZZ27DestroyInConditionalCleanupvEN1AC1Ev + // EH: store ptr %{{.*}}, ptr %cond-cleanup.save +} + +void ArrayInitWithContinue() { + // CHECK-LABEL: @_Z21ArrayInitWithContinuev + // Verify that we start to emit the array destructor. + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + for (int i = 0; i < 1; ++i) { + Printy arr[2] = {"a", ({ + if (foo()) { + continue; + } + "b"; + })}; + } +} + +struct [[clang::trivial_abi]] HasTrivialABI { + HasTrivialABI(); + ~HasTrivialABI(); +}; +void AcceptTrivialABI(HasTrivialABI, int); +void TrivialABI() { + // CHECK-LABEL: define dso_local void @_Z10TrivialABIv() + AcceptTrivialABI(HasTrivialABI(), ({ + if (foo()) return; + // CHECK: if.then: + // CHECK-NEXT: call void @_ZN13HasTrivialABID1Ev + // CHECK-NEXT: br label %return + 0; + })); +} + +namespace CleanupFlag { +struct A { + A() {} + ~A() {} +}; + +struct B { + B(const A&) {} + B() {} + ~B() {} +}; + +struct S { + A a; + B b; +}; + +int AcceptS(S s); + +void Accept2(int x, int y); + +void InactiveNormalCleanup() { + // CHECK-LABEL: define {{.*}}InactiveNormalCleanupEv() + + // The first A{} below is an inactive normal cleanup which + // is not popped from EHStack on deactivation. This needs an + // "active" cleanup flag. + + // CHECK: [[ACTIVE:%cleanup.isactive.*]] = alloca i1, align 1 + // CHECK: call void [[A_CTOR:@.*AC1Ev]] + // CHECK: store i1 true, ptr [[ACTIVE]], align 1 + // CHECK: call void [[A_CTOR]] + // CHECK: call void [[B_CTOR:@.*BC1ERKNS_1AE]] + // CHECK: store i1 false, ptr [[ACTIVE]], align 1 + // CHECK: call noundef i32 [[ACCEPTS:@.*AcceptSENS_1SE]] + Accept2(AcceptS({.a = A{}, .b = A{}}), ({ + if (foo()) return; + // CHECK: if.then: + // CHECK: br label %cleanup + 0; + // CHECK: if.end: + // CHECK: call void [[ACCEPT2:@.*Accept2Eii]] + // CHECK: br label %cleanup + })); + // CHECK: cleanup: + // CHECK: call void [[S_DTOR:@.*SD1Ev]] + // CHECK: call void [[A_DTOR:@.*AD1Ev]] + // CHECK: %cleanup.is_active = load i1, ptr [[ACTIVE]] + // CHECK: br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done + + // CHECK: cleanup.action: + // CHECK: call void [[A_DTOR]] + + // The "active" cleanup flag is not required for unused cleanups. + Accept2(AcceptS({.a = A{}, .b = A{}}), 0); + // CHECK: cleanup.cont: + // CHECK: call void [[A_CTOR]] + // CHECK-NOT: store i1 true + // CHECK: call void [[A_CTOR]] + // CHECK: call void [[B_CTOR]] + // CHECK-NOT: store i1 false + // CHECK: call noundef i32 [[ACCEPTS]] + // CHECK: call void [[ACCEPT2]] + // CHECK: call void [[S_DTOR]] + // CHECK: call void [[A_DTOR]] + // CHECK: br label %return +} +} // namespace CleanupFlag diff --git a/clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp b/clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp new file mode 100644 index 000000000000..06cc2069dbe9 --- /dev/null +++ b/clang/test/CodeGenCoroutines/coro-suspend-cleanups.cpp @@ -0,0 +1,93 @@ +// RUN: %clang_cc1 --std=c++20 -triple x86_64-linux-gnu -emit-llvm %s -o - | FileCheck %s + +#include "Inputs/coroutine.h" + +struct Printy { + Printy(const char *name) : name(name) {} + ~Printy() {} + const char *name; +}; + +struct coroutine { + struct promise_type; + std::coroutine_handle handle; + ~coroutine() { + if (handle) handle.destroy(); + } +}; + +struct coroutine::promise_type { + coroutine get_return_object() { + return {std::coroutine_handle::from_promise(*this)}; + } + std::suspend_never initial_suspend() noexcept { return {}; } + std::suspend_always final_suspend() noexcept { return {}; } + void return_void() {} + void unhandled_exception() {} +}; + +struct Awaiter : std::suspend_always { + Printy await_resume() { return {"awaited"}; } +}; + +int foo() { return 2; } + +coroutine ArrayInitCoro() { + // Verify that: + // - We do the necessary stores for array cleanups. + // - Array cleanups are called by await.cleanup. + // - We activate the cleanup after the first element and deactivate it in await.ready (see cleanup.isactive). + + // CHECK-LABEL: define dso_local void @_Z13ArrayInitCorov + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + // CHECK: %cleanup.isactive = alloca i1, align 1 + Printy arr[2] = { + Printy("a"), + // CHECK: %arrayinit.begin = getelementptr inbounds [2 x %struct.Printy], ptr %arr.reload.addr, i64 0, i64 0 + // CHECK-NEXT: %arrayinit.begin.spill.addr = getelementptr inbounds %_Z13ArrayInitCorov.Frame, ptr %0, i32 0, i32 10 + // CHECK-NEXT: store ptr %arrayinit.begin, ptr %arrayinit.begin.spill.addr, align 8 + // CHECK-NEXT: store i1 true, ptr %cleanup.isactive.reload.addr, align 1 + // CHECK-NEXT: store ptr %arrayinit.begin, ptr %arrayinit.endOfInit.reload.addr, align 8 + // CHECK-NEXT: call void @_ZN6PrintyC1EPKc(ptr noundef nonnull align 8 dereferenceable(8) %arrayinit.begin, ptr noundef @.str) + // CHECK-NEXT: %arrayinit.element = getelementptr inbounds %struct.Printy, ptr %arrayinit.begin, i64 1 + // CHECK-NEXT: %arrayinit.element.spill.addr = getelementptr inbounds %_Z13ArrayInitCorov.Frame, ptr %0, i32 0, i32 11 + // CHECK-NEXT: store ptr %arrayinit.element, ptr %arrayinit.element.spill.addr, align 8 + // CHECK-NEXT: store ptr %arrayinit.element, ptr %arrayinit.endOfInit.reload.addr, align 8 + co_await Awaiter{} + // CHECK-NEXT: @_ZNSt14suspend_always11await_readyEv + // CHECK-NEXT: br i1 %{{.+}}, label %await.ready, label %CoroSave30 + }; + // CHECK: await.cleanup: ; preds = %AfterCoroSuspend{{.*}} + // CHECK-NEXT: br label %cleanup{{.*}}.from.await.cleanup + + // CHECK: cleanup{{.*}}.from.await.cleanup: ; preds = %await.cleanup + // CHECK: br label %cleanup{{.*}} + + // CHECK: await.ready: + // CHECK-NEXT: %arrayinit.element.reload.addr = getelementptr inbounds %_Z13ArrayInitCorov.Frame, ptr %0, i32 0, i32 11 + // CHECK-NEXT: %arrayinit.element.reload = load ptr, ptr %arrayinit.element.reload.addr, align 8 + // CHECK-NEXT: call void @_ZN7Awaiter12await_resumeEv + // CHECK-NEXT: store i1 false, ptr %cleanup.isactive.reload.addr, align 1 + // CHECK-NEXT: br label %cleanup{{.*}}.from.await.ready + + // CHECK: cleanup{{.*}}: ; preds = %cleanup{{.*}}.from.await.ready, %cleanup{{.*}}.from.await.cleanup + // CHECK: %cleanup.is_active = load i1, ptr %cleanup.isactive.reload.addr, align 1 + // CHECK-NEXT: br i1 %cleanup.is_active, label %cleanup.action, label %cleanup.done + + // CHECK: cleanup.action: + // CHECK: %arraydestroy.isempty = icmp eq ptr %arrayinit.begin.reload{{.*}}, %{{.*}} + // CHECK-NEXT: br i1 %arraydestroy.isempty, label %arraydestroy.done{{.*}}, label %arraydestroy.body.from.cleanup.action + // Ignore rest of the array cleanup. +} + +coroutine ArrayInitWithCoReturn() { + // CHECK-LABEL: define dso_local void @_Z21ArrayInitWithCoReturnv + // Verify that we start to emit the array destructor. + // CHECK: %arrayinit.endOfInit = alloca ptr, align 8 + Printy arr[2] = {"a", ({ + if (foo()) { + co_return; + } + "b"; + })}; +} diff --git a/clang/test/CodeGenObjC/arc-blocks-exceptions.m b/clang/test/CodeGenObjC/arc-blocks-exceptions.m index 821b818d4027..54b043d8ea07 100644 --- a/clang/test/CodeGenObjC/arc-blocks-exceptions.m +++ b/clang/test/CodeGenObjC/arc-blocks-exceptions.m @@ -5,17 +5,22 @@ void test1(_Bool c) { __weak id weakId = 0; test1_fn(c ? ^{ (void)weakId; } : 0); - // CHECK: [[CLEANUP_COND:%.*]] = alloca i1 - // CHECK-NEXT: [[CLEANUP_SAVE:%.*]] = alloca ptr + // CHECK: [[CLEANUP_SAVE:%cond-cleanup.save.*]] = alloca ptr + // CHECK-NEXT: [[CLEANUP_COND:%.*]] = alloca i1 + // CHECK-NEXT: [[CLEANUP_COND1:%.*]] = alloca i1 - // CHECK: store i1 true, ptr [[CLEANUP_COND]] - // CHECK-NEXT: store ptr {{.*}}, ptr [[CLEANUP_SAVE]] + // CHECK: store i1 false, ptr [[CLEANUP_COND]] + // CHECK-NEXT: store i1 false, ptr [[CLEANUP_COND1]] + + // CHECK: store ptr {{.*}}, ptr [[CLEANUP_SAVE]] + // CHECK-NEXT: store i1 true, ptr [[CLEANUP_COND]] + // CHECK-NEXT: store i1 true, ptr [[CLEANUP_COND1]] // CHECK: invoke void @test1_fn( // CHECK-NEXT: to label %[[INVOKE_CONT:.*]] unwind label %[[LANDING_PAD_LAB:.*]] // CHECK: [[INVOKE_CONT]]: - // CHECK-NEXT: [[LOAD:%.*]] = load i1, ptr [[CLEANUP_COND]] + // CHECK-NEXT: [[LOAD:%.*]] = load i1, ptr [[CLEANUP_COND1]] // CHECK-NEXT: br i1 [[LOAD]], label %[[END_OF_SCOPE_LAB:.*]], label // CHECK: [[END_OF_SCOPE_LAB]]: diff --git a/clang/test/CodeGenObjC/arc-blocks.m b/clang/test/CodeGenObjC/arc-blocks.m index 105a72b4af1e..f718e8bbf9a6 100644 --- a/clang/test/CodeGenObjC/arc-blocks.m +++ b/clang/test/CodeGenObjC/arc-blocks.m @@ -445,8 +445,8 @@ void test13(id x) { // CHECK: [[X:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[B:%.*]] = alloca ptr, align 8 // CHECK-NEXT: [[BLOCK:%.*]] = alloca [[BLOCK_T:.*]], align 8 - // CHECK-NEXT: [[CLEANUP_ACTIVE:%.*]] = alloca i1 // CHECK-NEXT: [[COND_CLEANUP_SAVE:%.*]] = alloca ptr, + // CHECK-NEXT: [[CLEANUP_ACTIVE:%.*]] = alloca i1 // CHECK-NEXT: [[T0:%.*]] = call ptr @llvm.objc.retain(ptr {{%.*}}) // CHECK-NEXT: store ptr [[T0]], ptr [[X]], align 8 // CHECK-NEXT: call void @llvm.lifetime.start.p0(i64 8, ptr [[B]]) @@ -460,8 +460,8 @@ void test13(id x) { // CHECK-NEXT: [[T0:%.*]] = load ptr, ptr [[X]], align 8 // CHECK-NEXT: [[T1:%.*]] = call ptr @llvm.objc.retain(ptr [[T0]]) // CHECK-NEXT: store ptr [[T1]], ptr [[CAPTURE]], align 8 - // CHECK-NEXT: store i1 true, ptr [[CLEANUP_ACTIVE]] // CHECK-NEXT: store ptr [[CAPTURE]], ptr [[COND_CLEANUP_SAVE]], align 8 + // CHECK-NEXT: store i1 true, ptr [[CLEANUP_ACTIVE]] // CHECK-NEXT: br label // CHECK: br label // CHECK: [[T0:%.*]] = phi ptr -- GitLab From 0c8151ac809c283187e9b19d0cbe72a09c8d74e0 Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 29 Apr 2024 11:40:00 +0100 Subject: [PATCH 204/301] [lldb][Test] Disable concurrent vfork tests on Arm and AArch64 Linux (again) 5f3e106de3cd5ce6d7ba37fb11f6ad740cb430c5 made them a lot more stable but there are still occasions where they will timeout and leave behind stale processes. For example https://lab.llvm.org/buildbot/#/builders/96/builds/56699. --- .../fork/concurrent_vfork/TestConcurrentVFork.py | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/lldb/test/API/functionalities/fork/concurrent_vfork/TestConcurrentVFork.py b/lldb/test/API/functionalities/fork/concurrent_vfork/TestConcurrentVFork.py index 2dcbb728549f..dd9500c186b2 100644 --- a/lldb/test/API/functionalities/fork/concurrent_vfork/TestConcurrentVFork.py +++ b/lldb/test/API/functionalities/fork/concurrent_vfork/TestConcurrentVFork.py @@ -48,6 +48,8 @@ class TestConcurrentVFork(TestBase): self.expect("continue", patterns=[r"exited with status = 1[0-4]"]) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_parent_vfork_no_exec(self): """ Make sure that debugging concurrent vfork() from multiple threads won't crash lldb during follow-parent. @@ -56,6 +58,8 @@ class TestConcurrentVFork(TestBase): self.follow_parent_helper(use_fork=False, call_exec=False) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_parent_fork_no_exec(self): """ Make sure that debugging concurrent fork() from multiple threads won't crash lldb during follow-parent. @@ -64,6 +68,8 @@ class TestConcurrentVFork(TestBase): self.follow_parent_helper(use_fork=True, call_exec=False) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_parent_vfork_call_exec(self): """ Make sure that debugging concurrent vfork() from multiple threads won't crash lldb during follow-parent. @@ -72,6 +78,8 @@ class TestConcurrentVFork(TestBase): self.follow_parent_helper(use_fork=False, call_exec=True) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_parent_fork_call_exec(self): """ Make sure that debugging concurrent vfork() from multiple threads won't crash lldb during follow-parent. @@ -80,6 +88,8 @@ class TestConcurrentVFork(TestBase): self.follow_parent_helper(use_fork=True, call_exec=True) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_child_vfork_no_exec(self): """ Make sure that debugging concurrent vfork() from multiple threads won't crash lldb during follow-child. @@ -88,6 +98,8 @@ class TestConcurrentVFork(TestBase): self.follow_child_helper(use_fork=False, call_exec=False) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_child_fork_no_exec(self): """ Make sure that debugging concurrent fork() from multiple threads won't crash lldb during follow-child. @@ -96,6 +108,8 @@ class TestConcurrentVFork(TestBase): self.follow_child_helper(use_fork=True, call_exec=False) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_child_vfork_call_exec(self): """ Make sure that debugging concurrent vfork() from multiple threads won't crash lldb during follow-child. @@ -104,6 +118,8 @@ class TestConcurrentVFork(TestBase): self.follow_child_helper(use_fork=False, call_exec=True) @skipUnlessPlatform(["linux"]) + # https://github.com/llvm/llvm-project/issues/85084. + @skipIf(oslist=["linux"], archs=["aarch64", "arm"]) def test_follow_child_fork_call_exec(self): """ Make sure that debugging concurrent fork() from multiple threads won't crash lldb during follow-child. -- GitLab From 2914a11e3fad5d5634272f028b2765ac182d6b20 Mon Sep 17 00:00:00 2001 From: David Stuttard Date: Mon, 29 Apr 2024 11:42:36 +0100 Subject: [PATCH 205/301] [AMDGPU] Fix hard clausing for image instructions on gfx12 (#90221) Also updated hard-clauses.mir to have separate versions for gfx11 and gfx12 since the MIR instructions are different for each of them. --- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp | 6 +- .../CodeGen/AMDGPU/hard-clauses-img-gfx10.mir | 34 +++ .../CodeGen/AMDGPU/hard-clauses-img-gfx11.mir | 40 +++ .../CodeGen/AMDGPU/hard-clauses-img-gfx12.mir | 40 +++ llvm/test/CodeGen/AMDGPU/hard-clauses.mir | 235 ++++++++++++++---- 5 files changed, 302 insertions(+), 53 deletions(-) create mode 100644 llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir create mode 100644 llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir create mode 100644 llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp index e20fe1b716b6..76b90042d65f 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.cpp @@ -461,8 +461,10 @@ bool SIInstrInfo::getMemOperandsWithOffsetWidth( return true; } - if (isMIMG(LdSt)) { - int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::srsrc); + if (isImage(LdSt)) { + auto RsrcOpName = + isMIMG(LdSt) ? AMDGPU::OpName::srsrc : AMDGPU::OpName::rsrc; + int SRsrcIdx = AMDGPU::getNamedOperandIdx(Opc, RsrcOpName); BaseOps.push_back(&LdSt.getOperand(SRsrcIdx)); int VAddr0Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::vaddr0); if (VAddr0Idx >= 0) { diff --git a/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir b/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir new file mode 100644 index 000000000000..50eea4aebd5e --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx10.mir @@ -0,0 +1,34 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s + +--- +name: mimg_nsa +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-LABEL: name: mimg_nsa + ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) +... + +--- +name: mimg_nsa_mixed +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-LABEL: name: mimg_nsa_mixed + ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx10 $vgpr5_vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) + ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx10 $vgpr5_vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) + $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) +... diff --git a/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir b/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir new file mode 100644 index 000000000000..b22de06e68a7 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx11.mir @@ -0,0 +1,40 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s + +--- +name: mimg_nsa +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-LABEL: name: mimg_nsa + ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BUNDLE implicit-def $vgpr10_vgpr11_vgpr12, implicit-def $vgpr10, implicit-def $vgpr10_lo16, implicit-def $vgpr10_hi16, implicit-def $vgpr11, implicit-def $vgpr11_lo16, implicit-def $vgpr11_hi16, implicit-def $vgpr12, implicit-def $vgpr12_lo16, implicit-def $vgpr12_hi16, implicit-def $vgpr10_vgpr11, implicit-def $vgpr11_vgpr12, implicit-def $vgpr20_vgpr21_vgpr22, implicit-def $vgpr20, implicit-def $vgpr20_lo16, implicit-def $vgpr20_hi16, implicit-def $vgpr21, implicit-def $vgpr21_lo16, implicit-def $vgpr21_hi16, implicit-def $vgpr22, implicit-def $vgpr22_lo16, implicit-def $vgpr22_hi16, implicit-def $vgpr20_vgpr21, implicit-def $vgpr21_vgpr22, implicit $vgpr3, implicit $vgpr8, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec { + ; CHECK-NEXT: S_CLAUSE 1 + ; CHECK-NEXT: $vgpr10_vgpr11_vgpr12 = IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: } + $vgpr10_vgpr11_vgpr12 = IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) +... + +--- +name: mimg_nsa_mixed +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-LABEL: name: mimg_nsa_mixed + ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BUNDLE implicit-def $vgpr10, implicit-def $vgpr10_lo16, implicit-def $vgpr10_hi16, implicit-def $vgpr14, implicit-def $vgpr14_lo16, implicit-def $vgpr14_hi16, implicit-def $vgpr20_vgpr21_vgpr22, implicit-def $vgpr20, implicit-def $vgpr20_lo16, implicit-def $vgpr20_hi16, implicit-def $vgpr21, implicit-def $vgpr21_lo16, implicit-def $vgpr21_hi16, implicit-def $vgpr22, implicit-def $vgpr22_lo16, implicit-def $vgpr22_hi16, implicit-def $vgpr20_vgpr21, implicit-def $vgpr21_vgpr22, implicit $vgpr3, implicit $vgpr8, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec, implicit $vgpr5_vgpr6 { + ; CHECK-NEXT: S_CLAUSE 2 + ; CHECK-NEXT: $vgpr10 = IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx11 $vgpr5_vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) + ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: } + $vgpr10 = IMAGE_SAMPLE_LZ_V1_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx11 $vgpr5_vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) + $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_nsa_gfx11 $vgpr3, $vgpr8, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) +... diff --git a/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir b/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir new file mode 100644 index 000000000000..243a84562ab3 --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/hard-clauses-img-gfx12.mir @@ -0,0 +1,40 @@ +# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py +# RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s + +--- +name: mimg +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-LABEL: name: mimg + ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BUNDLE implicit-def $vgpr10_vgpr11_vgpr12, implicit-def $vgpr10, implicit-def $vgpr10_lo16, implicit-def $vgpr10_hi16, implicit-def $vgpr11, implicit-def $vgpr11_lo16, implicit-def $vgpr11_hi16, implicit-def $vgpr12, implicit-def $vgpr12_lo16, implicit-def $vgpr12_hi16, implicit-def $vgpr10_vgpr11, implicit-def $vgpr11_vgpr12, implicit-def $vgpr20_vgpr21_vgpr22, implicit-def $vgpr20, implicit-def $vgpr20_lo16, implicit-def $vgpr20_hi16, implicit-def $vgpr21, implicit-def $vgpr21_lo16, implicit-def $vgpr21_hi16, implicit-def $vgpr22, implicit-def $vgpr22_lo16, implicit-def $vgpr22_hi16, implicit-def $vgpr20_vgpr21, implicit-def $vgpr21_vgpr22, implicit $vgpr3, implicit $vgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec { + ; CHECK-NEXT: S_CLAUSE 1 + ; CHECK-NEXT: $vgpr10_vgpr11_vgpr12 = IMAGE_SAMPLE_LZ_V3_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: } + $vgpr10_vgpr11_vgpr12 = IMAGE_SAMPLE_LZ_V3_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) +... + +--- +name: mimg_mixed +tracksRegLiveness: true +body: | + bb.0: + liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-LABEL: name: mimg_mixed + ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: BUNDLE implicit-def $vgpr10, implicit-def $vgpr10_lo16, implicit-def $vgpr10_hi16, implicit-def $vgpr14, implicit-def $vgpr14_lo16, implicit-def $vgpr14_hi16, implicit-def $vgpr20_vgpr21_vgpr22, implicit-def $vgpr20, implicit-def $vgpr20_lo16, implicit-def $vgpr20_hi16, implicit-def $vgpr21, implicit-def $vgpr21_lo16, implicit-def $vgpr21_hi16, implicit-def $vgpr22, implicit-def $vgpr22_lo16, implicit-def $vgpr22_hi16, implicit-def $vgpr20_vgpr21, implicit-def $vgpr21_vgpr22, implicit $vgpr3, implicit $vgpr4, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec, implicit $vgpr5, implicit $vgpr6 { + ; CHECK-NEXT: S_CLAUSE 2 + ; CHECK-NEXT: $vgpr10 = IMAGE_SAMPLE_LZ_V1_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx12 $vgpr5, $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) + ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + ; CHECK-NEXT: } + $vgpr10 = IMAGE_SAMPLE_LZ_V1_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) + $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx12 $vgpr5, $vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) + $vgpr20_vgpr21_vgpr22 = IMAGE_SAMPLE_LZ_V3_V2_gfx12 $vgpr3, $vgpr4, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 14, 1, -1, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) +... diff --git a/llvm/test/CodeGen/AMDGPU/hard-clauses.mir b/llvm/test/CodeGen/AMDGPU/hard-clauses.mir index 1c6bdff51015..44b988a7121c 100644 --- a/llvm/test/CodeGen/AMDGPU/hard-clauses.mir +++ b/llvm/test/CodeGen/AMDGPU/hard-clauses.mir @@ -1,6 +1,7 @@ # NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py # RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s # RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s -check-prefix=GFX11 +# RUN: llc -mtriple=amdgcn -mcpu=gfx1200 -verify-machineinstrs -run-pass si-insert-hard-clauses %s -o - | FileCheck %s -check-prefix=GFX12 --- name: nop1 @@ -19,6 +20,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 ; GFX11-NEXT: S_NOP 2 + ; + ; GFX12-LABEL: name: nop1 + ; GFX12: liveins: $sgpr0_sgpr1 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 + ; GFX12-NEXT: S_NOP 2 $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 S_NOP 2 ... @@ -48,6 +55,16 @@ body: | ; GFX11-NEXT: S_NOP 2 ; GFX11-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 ; GFX11-NEXT: } + ; + ; GFX12-LABEL: name: nop2 + ; GFX12: liveins: $sgpr0_sgpr1 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: BUNDLE implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit $sgpr0_sgpr1 { + ; GFX12-NEXT: S_CLAUSE 2 + ; GFX12-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 + ; GFX12-NEXT: S_NOP 2 + ; GFX12-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 + ; GFX12-NEXT: } $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 S_NOP 2 $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 @@ -80,6 +97,17 @@ body: | ; GFX11-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 ; GFX11-NEXT: } ; GFX11-NEXT: S_NOP 2 + ; + ; GFX12-LABEL: name: nop3 + ; GFX12: liveins: $sgpr0_sgpr1 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: BUNDLE implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit $sgpr0_sgpr1 { + ; GFX12-NEXT: S_CLAUSE 2 + ; GFX12-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 + ; GFX12-NEXT: S_NOP 2 + ; GFX12-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 + ; GFX12-NEXT: } + ; GFX12-NEXT: S_NOP 2 $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 S_NOP 2 $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 @@ -274,6 +302,99 @@ body: | ; GFX11-NEXT: $vgpr79 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 316, 0, 0, implicit $exec ; GFX11-NEXT: $vgpr80 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 320, 0, 0, implicit $exec ; GFX11-NEXT: } + ; + ; GFX12-LABEL: name: long_clause + ; GFX12: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: BUNDLE implicit-def $vgpr1, implicit-def $vgpr1_lo16, implicit-def $vgpr1_hi16, implicit-def $vgpr2, implicit-def $vgpr2_lo16, implicit-def $vgpr2_hi16, implicit-def $vgpr3, implicit-def $vgpr3_lo16, implicit-def $vgpr3_hi16, implicit-def $vgpr4, implicit-def $vgpr4_lo16, implicit-def $vgpr4_hi16, implicit-def $vgpr5, implicit-def $vgpr5_lo16, implicit-def $vgpr5_hi16, implicit-def $vgpr6, implicit-def $vgpr6_lo16, implicit-def $vgpr6_hi16, implicit-def $vgpr7, implicit-def $vgpr7_lo16, implicit-def $vgpr7_hi16, implicit-def $vgpr8, implicit-def $vgpr8_lo16, implicit-def $vgpr8_hi16, implicit-def $vgpr9, implicit-def $vgpr9_lo16, implicit-def $vgpr9_hi16, implicit-def $vgpr10, implicit-def $vgpr10_lo16, implicit-def $vgpr10_hi16, implicit-def $vgpr11, implicit-def $vgpr11_lo16, implicit-def $vgpr11_hi16, implicit-def $vgpr12, implicit-def $vgpr12_lo16, implicit-def $vgpr12_hi16, implicit-def $vgpr13, implicit-def $vgpr13_lo16, implicit-def $vgpr13_hi16, implicit-def $vgpr14, implicit-def $vgpr14_lo16, implicit-def $vgpr14_hi16, implicit-def $vgpr15, implicit-def $vgpr15_lo16, implicit-def $vgpr15_hi16, implicit-def $vgpr16, implicit-def $vgpr16_lo16, implicit-def $vgpr16_hi16, implicit-def $vgpr17, implicit-def $vgpr17_lo16, implicit-def $vgpr17_hi16, implicit-def $vgpr18, implicit-def $vgpr18_lo16, implicit-def $vgpr18_hi16, implicit-def $vgpr19, implicit-def $vgpr19_lo16, implicit-def $vgpr19_hi16, implicit-def $vgpr20, implicit-def $vgpr20_lo16, implicit-def $vgpr20_hi16, implicit-def $vgpr21, implicit-def $vgpr21_lo16, implicit-def $vgpr21_hi16, implicit-def $vgpr22, implicit-def $vgpr22_lo16, implicit-def $vgpr22_hi16, implicit-def $vgpr23, implicit-def $vgpr23_lo16, implicit-def $vgpr23_hi16, implicit-def $vgpr24, implicit-def $vgpr24_lo16, implicit-def $vgpr24_hi16, implicit-def $vgpr25, implicit-def $vgpr25_lo16, implicit-def $vgpr25_hi16, implicit-def $vgpr26, implicit-def $vgpr26_lo16, implicit-def $vgpr26_hi16, implicit-def $vgpr27, implicit-def $vgpr27_lo16, implicit-def $vgpr27_hi16, implicit-def $vgpr28, implicit-def $vgpr28_lo16, implicit-def $vgpr28_hi16, implicit-def $vgpr29, implicit-def $vgpr29_lo16, implicit-def $vgpr29_hi16, implicit-def $vgpr30, implicit-def $vgpr30_lo16, implicit-def $vgpr30_hi16, implicit-def $vgpr31, implicit-def $vgpr31_lo16, implicit-def $vgpr31_hi16, implicit-def $vgpr32, implicit-def $vgpr32_lo16, implicit-def $vgpr32_hi16, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec { + ; GFX12-NEXT: S_CLAUSE 31 + ; GFX12-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr4 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 16, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr5 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 20, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr6 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 24, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr7 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 28, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr8 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 32, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr9 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 36, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr10 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 40, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr11 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 44, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr12 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 48, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr13 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 52, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr14 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 56, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr15 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 60, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr16 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 64, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr17 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 68, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr18 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 72, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr19 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 76, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr20 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 80, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr21 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 84, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr22 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 88, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr23 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 92, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr24 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 96, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr25 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 100, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr26 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 104, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr27 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 108, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr28 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 112, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr29 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 116, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr30 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 120, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr31 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 124, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr32 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 128, 0, 0, implicit $exec + ; GFX12-NEXT: } + ; GFX12-NEXT: BUNDLE implicit-def $vgpr33, implicit-def $vgpr33_lo16, implicit-def $vgpr33_hi16, implicit-def $vgpr34, implicit-def $vgpr34_lo16, implicit-def $vgpr34_hi16, implicit-def $vgpr35, implicit-def $vgpr35_lo16, implicit-def $vgpr35_hi16, implicit-def $vgpr36, implicit-def $vgpr36_lo16, implicit-def $vgpr36_hi16, implicit-def $vgpr37, implicit-def $vgpr37_lo16, implicit-def $vgpr37_hi16, implicit-def $vgpr38, implicit-def $vgpr38_lo16, implicit-def $vgpr38_hi16, implicit-def $vgpr39, implicit-def $vgpr39_lo16, implicit-def $vgpr39_hi16, implicit-def $vgpr40, implicit-def $vgpr40_lo16, implicit-def $vgpr40_hi16, implicit-def $vgpr41, implicit-def $vgpr41_lo16, implicit-def $vgpr41_hi16, implicit-def $vgpr42, implicit-def $vgpr42_lo16, implicit-def $vgpr42_hi16, implicit-def $vgpr43, implicit-def $vgpr43_lo16, implicit-def $vgpr43_hi16, implicit-def $vgpr44, implicit-def $vgpr44_lo16, implicit-def $vgpr44_hi16, implicit-def $vgpr45, implicit-def $vgpr45_lo16, implicit-def $vgpr45_hi16, implicit-def $vgpr46, implicit-def $vgpr46_lo16, implicit-def $vgpr46_hi16, implicit-def $vgpr47, implicit-def $vgpr47_lo16, implicit-def $vgpr47_hi16, implicit-def $vgpr48, implicit-def $vgpr48_lo16, implicit-def $vgpr48_hi16, implicit-def $vgpr49, implicit-def $vgpr49_lo16, implicit-def $vgpr49_hi16, implicit-def $vgpr50, implicit-def $vgpr50_lo16, implicit-def $vgpr50_hi16, implicit-def $vgpr51, implicit-def $vgpr51_lo16, implicit-def $vgpr51_hi16, implicit-def $vgpr52, implicit-def $vgpr52_lo16, implicit-def $vgpr52_hi16, implicit-def $vgpr53, implicit-def $vgpr53_lo16, implicit-def $vgpr53_hi16, implicit-def $vgpr54, implicit-def $vgpr54_lo16, implicit-def $vgpr54_hi16, implicit-def $vgpr55, implicit-def $vgpr55_lo16, implicit-def $vgpr55_hi16, implicit-def $vgpr56, implicit-def $vgpr56_lo16, implicit-def $vgpr56_hi16, implicit-def $vgpr57, implicit-def $vgpr57_lo16, implicit-def $vgpr57_hi16, implicit-def $vgpr58, implicit-def $vgpr58_lo16, implicit-def $vgpr58_hi16, implicit-def $vgpr59, implicit-def $vgpr59_lo16, implicit-def $vgpr59_hi16, implicit-def $vgpr60, implicit-def $vgpr60_lo16, implicit-def $vgpr60_hi16, implicit-def $vgpr61, implicit-def $vgpr61_lo16, implicit-def $vgpr61_hi16, implicit-def $vgpr62, implicit-def $vgpr62_lo16, implicit-def $vgpr62_hi16, implicit-def $vgpr63, implicit-def $vgpr63_lo16, implicit-def $vgpr63_hi16, implicit-def $vgpr64, implicit-def $vgpr64_lo16, implicit-def $vgpr64_hi16, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec { + ; GFX12-NEXT: S_CLAUSE 31 + ; GFX12-NEXT: $vgpr33 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 132, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr34 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 136, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr35 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 140, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr36 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 144, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr37 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 148, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr38 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 152, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr39 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 156, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr40 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 160, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr41 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 164, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr42 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 168, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr43 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 172, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr44 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 176, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr45 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 180, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr46 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 184, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr47 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 188, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr48 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 192, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr49 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 196, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr50 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 200, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr51 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 204, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr52 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 208, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr53 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 212, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr54 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 216, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr55 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 220, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr56 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 224, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr57 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 228, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr58 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 232, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr59 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 236, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr60 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 240, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr61 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 244, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr62 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 248, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr63 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 252, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr64 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 256, 0, 0, implicit $exec + ; GFX12-NEXT: } + ; GFX12-NEXT: BUNDLE implicit-def $vgpr65, implicit-def $vgpr65_lo16, implicit-def $vgpr65_hi16, implicit-def $vgpr66, implicit-def $vgpr66_lo16, implicit-def $vgpr66_hi16, implicit-def $vgpr67, implicit-def $vgpr67_lo16, implicit-def $vgpr67_hi16, implicit-def $vgpr68, implicit-def $vgpr68_lo16, implicit-def $vgpr68_hi16, implicit-def $vgpr69, implicit-def $vgpr69_lo16, implicit-def $vgpr69_hi16, implicit-def $vgpr70, implicit-def $vgpr70_lo16, implicit-def $vgpr70_hi16, implicit-def $vgpr71, implicit-def $vgpr71_lo16, implicit-def $vgpr71_hi16, implicit-def $vgpr72, implicit-def $vgpr72_lo16, implicit-def $vgpr72_hi16, implicit-def $vgpr73, implicit-def $vgpr73_lo16, implicit-def $vgpr73_hi16, implicit-def $vgpr74, implicit-def $vgpr74_lo16, implicit-def $vgpr74_hi16, implicit-def $vgpr75, implicit-def $vgpr75_lo16, implicit-def $vgpr75_hi16, implicit-def $vgpr76, implicit-def $vgpr76_lo16, implicit-def $vgpr76_hi16, implicit-def $vgpr77, implicit-def $vgpr77_lo16, implicit-def $vgpr77_hi16, implicit-def $vgpr78, implicit-def $vgpr78_lo16, implicit-def $vgpr78_hi16, implicit-def $vgpr79, implicit-def $vgpr79_lo16, implicit-def $vgpr79_hi16, implicit-def $vgpr80, implicit-def $vgpr80_lo16, implicit-def $vgpr80_hi16, implicit $vgpr0, implicit $sgpr0_sgpr1_sgpr2_sgpr3, implicit $exec { + ; GFX12-NEXT: S_CLAUSE 15 + ; GFX12-NEXT: $vgpr65 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 260, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr66 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 264, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr67 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 268, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr68 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 272, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr69 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 276, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr70 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 280, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr71 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 284, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr72 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 288, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr73 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 292, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr74 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 296, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr75 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 300, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr76 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 304, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr77 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 308, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr78 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 312, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr79 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 316, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr80 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 320, 0, 0, implicit $exec + ; GFX12-NEXT: } $vgpr1 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 4, 0, 0, implicit $exec $vgpr2 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 8, 0, 0, implicit $exec $vgpr3 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 12, 0, 0, implicit $exec @@ -356,57 +477,6 @@ body: | $vgpr80 = BUFFER_LOAD_DWORD_OFFEN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 0, 320, 0, 0, implicit $exec ... ---- -name: mimg_nsa -tracksRegLiveness: true -body: | - bb.0: - liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 - ; CHECK-LABEL: name: mimg_nsa - ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; - ; GFX11-LABEL: name: mimg_nsa - ; GFX11: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 - ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: BUNDLE implicit-def $vgpr10_vgpr11_vgpr12_vgpr13, implicit-def $vgpr10, implicit-def $vgpr10_lo16, implicit-def $vgpr10_hi16, implicit-def $vgpr11, implicit-def $vgpr11_lo16, implicit-def $vgpr11_hi16, implicit-def $vgpr12, implicit-def $vgpr12_lo16, implicit-def $vgpr12_hi16, implicit-def $vgpr13, implicit-def $vgpr13_lo16, implicit-def $vgpr13_hi16, implicit-def $vgpr10_vgpr11, implicit-def $vgpr10_vgpr11_vgpr12, implicit-def $vgpr11_vgpr12, implicit-def $vgpr11_vgpr12_vgpr13, implicit-def $vgpr12_vgpr13, implicit-def $vgpr20_vgpr21_vgpr22_vgpr23, implicit-def $vgpr20, implicit-def $vgpr20_lo16, implicit-def $vgpr20_hi16, implicit-def $vgpr21, implicit-def $vgpr21_lo16, implicit-def $vgpr21_hi16, implicit-def $vgpr22, implicit-def $vgpr22_lo16, implicit-def $vgpr22_hi16, implicit-def $vgpr23, implicit-def $vgpr23_lo16, implicit-def $vgpr23_hi16, implicit-def $vgpr20_vgpr21, implicit-def $vgpr20_vgpr21_vgpr22, implicit-def $vgpr21_vgpr22, implicit-def $vgpr21_vgpr22_vgpr23, implicit-def $vgpr22_vgpr23, implicit $vgpr3, implicit $vgpr8, implicit $vgpr7, implicit $vgpr5, implicit $vgpr4, implicit $vgpr6, implicit $vgpr0, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec { - ; GFX11-NEXT: S_CLAUSE 1 - ; GFX11-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; GFX11-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; GFX11-NEXT: } - $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) -... - ---- -name: mimg_nsa_mixed -tracksRegLiveness: true -body: | - bb.0: - liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 - ; CHECK-LABEL: name: mimg_nsa_mixed - ; CHECK: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 - ; CHECK-NEXT: {{ $}} - ; CHECK-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; CHECK-NEXT: $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx10 $vgpr5_vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) - ; CHECK-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; - ; GFX11-LABEL: name: mimg_nsa_mixed - ; GFX11: liveins: $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, $vgpr0, $vgpr1, $vgpr2, $vgpr3, $vgpr4, $vgpr5, $vgpr6, $vgpr7, $vgpr8 - ; GFX11-NEXT: {{ $}} - ; GFX11-NEXT: BUNDLE implicit-def $vgpr10_vgpr11_vgpr12_vgpr13, implicit-def $vgpr10, implicit-def $vgpr10_lo16, implicit-def $vgpr10_hi16, implicit-def $vgpr11, implicit-def $vgpr11_lo16, implicit-def $vgpr11_hi16, implicit-def $vgpr12, implicit-def $vgpr12_lo16, implicit-def $vgpr12_hi16, implicit-def $vgpr13, implicit-def $vgpr13_lo16, implicit-def $vgpr13_hi16, implicit-def $vgpr10_vgpr11, implicit-def $vgpr10_vgpr11_vgpr12, implicit-def $vgpr11_vgpr12, implicit-def $vgpr11_vgpr12_vgpr13, implicit-def $vgpr12_vgpr13, implicit-def $vgpr14, implicit-def $vgpr14_lo16, implicit-def $vgpr14_hi16, implicit-def $vgpr20_vgpr21_vgpr22_vgpr23, implicit-def $vgpr20, implicit-def $vgpr20_lo16, implicit-def $vgpr20_hi16, implicit-def $vgpr21, implicit-def $vgpr21_lo16, implicit-def $vgpr21_hi16, implicit-def $vgpr22, implicit-def $vgpr22_lo16, implicit-def $vgpr22_hi16, implicit-def $vgpr23, implicit-def $vgpr23_lo16, implicit-def $vgpr23_hi16, implicit-def $vgpr20_vgpr21, implicit-def $vgpr20_vgpr21_vgpr22, implicit-def $vgpr21_vgpr22, implicit-def $vgpr21_vgpr22_vgpr23, implicit-def $vgpr22_vgpr23, implicit $vgpr3, implicit $vgpr8, implicit $vgpr7, implicit $vgpr5, implicit $vgpr4, implicit $vgpr6, implicit $vgpr0, implicit $vgpr2, implicit $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, implicit $sgpr8_sgpr9_sgpr10_sgpr11, implicit $exec, implicit $vgpr5_vgpr6 { - ; GFX11-NEXT: S_CLAUSE 2 - ; GFX11-NEXT: $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; GFX11-NEXT: $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx10 $vgpr5_vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) - ; GFX11-NEXT: $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - ; GFX11-NEXT: } - $vgpr10_vgpr11_vgpr12_vgpr13 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) - $vgpr14 = IMAGE_SAMPLE_LZ_V1_V2_gfx10 $vgpr5_vgpr6, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 1, 1, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (dereferenceable load (s128), addrspace 7) - $vgpr20_vgpr21_vgpr22_vgpr23 = IMAGE_SAMPLE_D_V4_V9_nsa_gfx10 $vgpr3, $vgpr8, $vgpr7, $vgpr5, $vgpr4, $vgpr6, $vgpr0, $vgpr2, $vgpr2, $sgpr0_sgpr1_sgpr2_sgpr3_sgpr4_sgpr5_sgpr6_sgpr7, $sgpr8_sgpr9_sgpr10_sgpr11, 15, 2, 0, 0, 0, 0, 0, 0, 0, implicit $exec :: (load (s128)) -... - --- name: kill tracksRegLiveness: true @@ -432,6 +502,16 @@ body: | ; GFX11-NEXT: KILL undef renamable $sgpr4 ; GFX11-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 ; GFX11-NEXT: } + ; + ; GFX12-LABEL: name: kill + ; GFX12: liveins: $sgpr0_sgpr1, $sgpr4 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: BUNDLE implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit $sgpr0_sgpr1, implicit undef $sgpr4 { + ; GFX12-NEXT: S_CLAUSE 1 + ; GFX12-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 + ; GFX12-NEXT: KILL undef renamable $sgpr4 + ; GFX12-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 + ; GFX12-NEXT: } $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 KILL undef renamable $sgpr4 $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 @@ -464,6 +544,17 @@ body: | ; GFX11-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 ; GFX11-NEXT: } ; GFX11-NEXT: KILL undef renamable $sgpr5 + ; + ; GFX12-LABEL: name: kill2 + ; GFX12: liveins: $sgpr0_sgpr1, $sgpr4, $sgpr5 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: BUNDLE implicit-def $sgpr2, implicit-def $sgpr2_lo16, implicit-def $sgpr2_hi16, implicit-def $sgpr3, implicit-def $sgpr3_lo16, implicit-def $sgpr3_hi16, implicit $sgpr0_sgpr1, implicit undef $sgpr4 { + ; GFX12-NEXT: S_CLAUSE 1 + ; GFX12-NEXT: $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 + ; GFX12-NEXT: KILL undef renamable $sgpr4 + ; GFX12-NEXT: $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 + ; GFX12-NEXT: } + ; GFX12-NEXT: KILL undef renamable $sgpr5 $sgpr2 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 0, 0 KILL undef renamable $sgpr4 $sgpr3 = S_LOAD_DWORD_IMM $sgpr0_sgpr1, 4, 0 @@ -490,6 +581,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr ; GFX11-NEXT: $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec, implicit $flat_scr + ; + ; GFX12-LABEL: name: flat_load_atomic + ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr + ; GFX12-NEXT: $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec, implicit $flat_scr $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr $vgpr4 = FLAT_ATOMIC_ADD_RTN $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec, implicit $flat_scr ... @@ -514,6 +611,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec ; GFX11-NEXT: $vgpr4 = GLOBAL_ATOMIC_ADD_RTN $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec + ; + ; GFX12-LABEL: name: global_load_atomic + ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr4 = GLOBAL_ATOMIC_ADD_RTN $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec $vgpr4 = GLOBAL_ATOMIC_ADD_RTN $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec ... @@ -535,6 +638,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr ; GFX11-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr + ; + ; GFX12-LABEL: name: flat_global_load + ; GFX12: liveins: $vgpr0_vgpr1 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr + ; GFX12-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr $vgpr2 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 4, 0, implicit $exec, implicit $flat_scr ... @@ -559,6 +668,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, implicit $exec ; GFX11-NEXT: $vgpr0 = BUFFER_ATOMIC_ADD_OFFSET_RTN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 4, 0, 0, implicit $exec + ; + ; GFX12-LABEL: name: buffer_load_atomic + ; GFX12: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, implicit $exec + ; GFX12-NEXT: $vgpr0 = BUFFER_ATOMIC_ADD_OFFSET_RTN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 4, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, implicit $exec $vgpr0 = BUFFER_ATOMIC_ADD_OFFSET_RTN $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, 4, 0, 0, implicit $exec ... @@ -580,6 +695,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr ; GFX11-NEXT: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec, implicit $flat_scr + ; + ; GFX12-LABEL: name: flat_load_store + ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr + ; GFX12-NEXT: FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec, implicit $flat_scr $vgpr3 = FLAT_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec, implicit $flat_scr FLAT_STORE_DWORD $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec, implicit $flat_scr ... @@ -601,6 +722,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec ; GFX11-NEXT: GLOBAL_STORE_DWORD $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec + ; + ; GFX12-LABEL: name: global_load_store + ; GFX12: liveins: $vgpr0_vgpr1, $vgpr2 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec + ; GFX12-NEXT: GLOBAL_STORE_DWORD $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec $vgpr3 = GLOBAL_LOAD_DWORD $vgpr0_vgpr1, 0, 0, implicit $exec GLOBAL_STORE_DWORD $vgpr0_vgpr1, $vgpr2, 4, 0, implicit $exec ... @@ -622,6 +749,12 @@ body: | ; GFX11-NEXT: {{ $}} ; GFX11-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, implicit $exec ; GFX11-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec + ; + ; GFX12-LABEL: name: buffer_load_store + ; GFX12: liveins: $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, $vgpr0 + ; GFX12-NEXT: {{ $}} + ; GFX12-NEXT: $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, implicit $exec + ; GFX12-NEXT: BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec $vgpr1 = BUFFER_LOAD_DWORD_OFFSET $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 0, 0, 0, implicit $exec BUFFER_STORE_DWORD_OFFSET $vgpr0, $sgpr0_sgpr1_sgpr2_sgpr3, $sgpr4, 4, 0, 0, implicit $exec ... -- GitLab From 5b187751452e0702fc9c29b64ab301737718e604 Mon Sep 17 00:00:00 2001 From: Jay Foad Date: Mon, 29 Apr 2024 11:23:24 +0100 Subject: [PATCH 206/301] [AMDGPU] Fix typo in #89773 Fixes #90281 --- llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp index bf4a501cc315..072c5aedc220 100644 --- a/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp +++ b/llvm/lib/Target/AMDGPU/SIMachineFunctionInfo.cpp @@ -110,7 +110,7 @@ SIMachineFunctionInfo::SIMachineFunctionInfo(const Function &F, } if (!AMDGPU::isGraphics(CC) || - ((CC == CallingConv::AMDGPU_CS || CC == CallingConv::AMDGPU_CS) && + ((CC == CallingConv::AMDGPU_CS || CC == CallingConv::AMDGPU_Gfx) && ST.hasArchitectedSGPRs())) { if (IsKernel || !F.hasFnAttribute("amdgpu-no-workgroup-id-x")) WorkGroupIDX = true; -- GitLab From f2452d4b689469b6da63d9e8ffa96eaf4b39ac5d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Sat, 27 Apr 2024 07:46:59 +0200 Subject: [PATCH 207/301] [clang][Interp] Implement zero-init for record types --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 27 ++++++++++++++++++++++-- clang/test/AST/Interp/records.cpp | 15 +++++++++++-- 2 files changed, 38 insertions(+), 4 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 588ffa55c11e..aebefd716e27 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -924,8 +924,31 @@ bool ByteCodeExprGen::VisitImplicitValueInitExpr(const ImplicitValueIni if (std::optional T = classify(QT)) return this->visitZeroInitializer(*T, QT, E); - if (QT->isRecordType()) - return false; + if (QT->isRecordType()) { + const RecordDecl *RD = QT->getAsRecordDecl(); + assert(RD); + if (RD->isInvalidDecl()) + return false; + if (RD->isUnion()) { + // C++11 [dcl.init]p5: If T is a (possibly cv-qualified) union type, the + // object's first non-static named data member is zero-initialized + // FIXME + return false; + } + + if (const auto *CXXRD = dyn_cast(RD); + CXXRD && CXXRD->getNumVBases() > 0) { + // TODO: Diagnose. + return false; + } + + const Record *R = getRecord(QT); + if (!R) + return false; + + assert(Initializing); + return this->visitZeroRecordInitializer(R, E); + } if (QT->isIncompleteArrayType()) return true; diff --git a/clang/test/AST/Interp/records.cpp b/clang/test/AST/Interp/records.cpp index 9307b9c090c5..ba5c58c96c7b 100644 --- a/clang/test/AST/Interp/records.cpp +++ b/clang/test/AST/Interp/records.cpp @@ -90,8 +90,7 @@ struct Ints2 { int a = 10; int b; }; -constexpr Ints2 ints22; // both-error {{without a user-provided default constructor}} \ - // expected-error {{must be initialized by a constant expression}} +constexpr Ints2 ints22; // both-error {{without a user-provided default constructor}} constexpr Ints2 I2 = Ints2{12, 25}; static_assert(I2.a == 12, ""); @@ -1409,3 +1408,15 @@ namespace VirtualBases { static_assert((X*)(Y1*)&z != (X*)(Y2*)&z, ""); } } + +namespace ZeroInit { + struct S3 { + S3() = default; + S3(const S3&) = default; + S3(S3&&) = default; + constexpr S3(int n) : n(n) {} + int n; + }; + constexpr S3 s3d; // both-error {{default initialization of an object of const type 'const S3' without a user-provided default constructor}} + static_assert(s3d.n == 0, ""); +} -- GitLab From 37f2928ce382603fdadd7bae87fa245ac65b7d4f Mon Sep 17 00:00:00 2001 From: Vlad Serebrennikov Date: Mon, 29 Apr 2024 15:03:13 +0400 Subject: [PATCH 208/301] [clang] Use `cwg_index.html` from GitHub for DR status page (#90352) Currently we're using official publication of CWG issue list available at https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_index.html. Unfortunately, it's not updated as frequently as we sometimes need. For instance, recently there was a confusion during review of CWG2149 test (https://github.com/llvm/llvm-project/pull/90079#discussion_r1580174003). This patch changes our `make_cxx_dr_status` script to use issue list from CWG GitHub repository. I confirmed with CWG chair that this is the most up-to-date source of information on CWG issues. Changing the source of issue list uncovered previously unhandled "tentatively ready" status of an issue. This status is considered unresolved by the script (like `open`, `drafting`, and `review`), as the resolution might change during face-to-face CWG meeting. I also noticed that CWG decided to handle 2561 differently from what we're doing, so this DR is now considered not available in Clang, despite being declared as available since 18. CC @cor3ntin. This patch also brings new issues into our DR list, so if someone was waiting for a newly-filed issue to appear on our status page, it should appear with this PR. --- clang/test/CXX/drs/cwg2149.cpp | 2 +- clang/test/CXX/drs/dr20xx.cpp | 2 +- clang/test/CXX/drs/dr21xx.cpp | 2 + clang/test/CXX/drs/dr24xx.cpp | 4 +- clang/test/CXX/drs/dr25xx.cpp | 4 +- clang/test/CXX/drs/dr28xx.cpp | 2 +- clang/www/cxx_dr_status.html | 553 +++++++++++++++++++++++---------- clang/www/make_cxx_dr_status | 6 +- 8 files changed, 410 insertions(+), 165 deletions(-) diff --git a/clang/test/CXX/drs/cwg2149.cpp b/clang/test/CXX/drs/cwg2149.cpp index d0f8cb2dfc0a..8416e42cbd69 100644 --- a/clang/test/CXX/drs/cwg2149.cpp +++ b/clang/test/CXX/drs/cwg2149.cpp @@ -11,7 +11,7 @@ // cxx98-error@-1 {{variadic macros are a C99 feature}} #endif -namespace cwg2149 { // cwg2149: 3.1 drafting 2024-04 +namespace cwg2149 { // cwg2149: 3.1 #if __cplusplus <= 201103L struct X { int i, j, k; }; #else diff --git a/clang/test/CXX/drs/dr20xx.cpp b/clang/test/CXX/drs/dr20xx.cpp index 291a77e0cc71..9797097acce7 100644 --- a/clang/test/CXX/drs/dr20xx.cpp +++ b/clang/test/CXX/drs/dr20xx.cpp @@ -90,7 +90,7 @@ namespace cwg2026 { // cwg2026: 11 } } -namespace cwg2049 { // cwg2049: 18 drafting P2308R1 +namespace cwg2049 { // cwg2049: 18 #if __cplusplus >= 202302L template struct X {}; X<> a; diff --git a/clang/test/CXX/drs/dr21xx.cpp b/clang/test/CXX/drs/dr21xx.cpp index 4fab10c279aa..082deb42e4fa 100644 --- a/clang/test/CXX/drs/dr21xx.cpp +++ b/clang/test/CXX/drs/dr21xx.cpp @@ -175,6 +175,8 @@ void foo() { } } +// cwg2149 is in cwg2149.cpp + namespace cwg2157 { // cwg2157: 11 #if __cplusplus >= 201103L enum E : int; diff --git a/clang/test/CXX/drs/dr24xx.cpp b/clang/test/CXX/drs/dr24xx.cpp index 5ffaebda68c1..9f876cd87083 100644 --- a/clang/test/CXX/drs/dr24xx.cpp +++ b/clang/test/CXX/drs/dr24xx.cpp @@ -45,7 +45,7 @@ void fallthrough(int n) { #endif } -namespace cwg2450 { // cwg2450: 18 review P2308R1 +namespace cwg2450 { // cwg2450: 18 #if __cplusplus >= 202302L struct S {int a;}; template @@ -59,7 +59,7 @@ f<{.a= 0}>(); #endif } -namespace cwg2459 { // cwg2459: 18 drafting P2308R1 +namespace cwg2459 { // cwg2459: 18 #if __cplusplus >= 202302L struct A { constexpr A(float) {} diff --git a/clang/test/CXX/drs/dr25xx.cpp b/clang/test/CXX/drs/dr25xx.cpp index 62b2a0a088cc..481ae09cdb77 100644 --- a/clang/test/CXX/drs/dr25xx.cpp +++ b/clang/test/CXX/drs/dr25xx.cpp @@ -130,12 +130,14 @@ struct D3 : B { #endif #if __cplusplus >= 202302L -namespace cwg2561 { // cwg2561: 18 review 2023-11-09 +namespace cwg2561 { // cwg2561: no struct C { constexpr C(auto) { } }; void foo() { constexpr auto b = [](this C) { return 1; }; + // FIXME: closure type shouldn't have a conversion function to function + // pointer, because explicit object parameter is present. constexpr int (*fp)(C) = b; static_assert(fp(1) == 1); static_assert((&decltype(b)::operator())(1) == 1); diff --git a/clang/test/CXX/drs/dr28xx.cpp b/clang/test/CXX/drs/dr28xx.cpp index 4d9b0c76758d..1967e8b751db 100644 --- a/clang/test/CXX/drs/dr28xx.cpp +++ b/clang/test/CXX/drs/dr28xx.cpp @@ -10,7 +10,7 @@ // expected-no-diagnostics #endif -namespace cwg2847 { // cwg2847: 19 +namespace cwg2847 { // cwg2847: 19 review 2024-03-01 #if __cplusplus >= 202002L diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index ea8872c91be6..19d29cb55d6e 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -1433,11 +1433,11 @@ accessible? Is indirection through a null pointer undefined behavior? Unknown - + 233 - drafting + tentatively ready References vs pointers in UDC overload resolution - Not resolved + Unknown 234 @@ -2756,7 +2756,7 @@ of class templates 453 - tentatively ready + DR References may only bind to “valid” objects Unknown @@ -5812,7 +5812,7 @@ and POD class 1001 - drafting + review Parameter type adjustment in dependent parameter types Not resolved @@ -6034,7 +6034,7 @@ and POD class 1038 - DR + DRWP Overload resolution of &x.static_func Unknown @@ -9994,7 +9994,7 @@ and POD class 1698 - DR + DRWP Files ending in \ Unknown @@ -10132,7 +10132,7 @@ and POD class 1721 - drafting + review Diagnosing ODR violations for static data members Not resolved @@ -11312,11 +11312,11 @@ and POD class decltype-qualified enumeration names Unknown - + 1918 - open + CD5 friend templates with dependent scopes - Not resolved + Unknown 1919 @@ -11474,11 +11474,11 @@ and POD class New C incompatibilities Not resolved - + 1945 - open + CD5 Friend declarations naming members of class templates in non-templates - Not resolved + Unknown 1946 @@ -11530,7 +11530,7 @@ and POD class 1954 - tentatively ready + DR typeid null dereference check in subexpressions Unknown @@ -12098,11 +12098,11 @@ and POD class C-style casts that cast away constness vs static_cast Not resolved - + 2049 - drafting + DRWP List initializer in non-type template default argument - Not Resolved* + Clang 18 2050 @@ -12130,7 +12130,7 @@ and POD class 2054 - DR + DRWP Missing description of class SFINAE Unknown @@ -12418,7 +12418,7 @@ and POD class 2102 - DR + DRWP Constructor checking in new-expression Unknown @@ -12698,11 +12698,11 @@ and POD class Thread storage duration and order of initialization Not resolved - + 2149 - drafting + DR Brace elision and array length deduction - Not Resolved* + Clang 3.1 2150 @@ -13318,7 +13318,7 @@ and POD class 2252 - DR + DRWP Enumeration list-initialization from the same type Unknown @@ -14410,7 +14410,7 @@ and POD class 2434 - open + review Mandatory copy elision vs non-class objects Not resolved @@ -14504,11 +14504,11 @@ and POD class Thunks as an implementation technique for pointers to virtual functions Extension - + 2450 - review + DRWP braced-init-list as a template-argument - Not Resolved* + Clang 18 2451 @@ -14558,11 +14558,11 @@ and POD class Value category of expressions denoting non-static member functions Unknown - + 2459 - drafting + DRWP Template parameter initialization - Not Resolved* + Clang 18 2460 @@ -14662,7 +14662,7 @@ and POD class 2476 - tentatively ready + DR placeholder-type-specifiers and function declarators Unknown @@ -14830,7 +14830,7 @@ and POD class 2504 - DR + DRWP Inheriting constructors from virtual base classes No @@ -14992,7 +14992,7 @@ and POD class 2531 - DR + DRWP Static data members redeclared as constexpr Unknown @@ -15002,11 +15002,11 @@ and POD class Kind of pointer value returned by new T[0] Not resolved - + 2533 - review + DR Storage duration of implicitly created objects - Not resolved + Unknown 2534 @@ -15082,13 +15082,13 @@ and POD class 2546 - tentatively ready + DR Defaulted secondary comparison operators defined as deleted Unknown 2547 - tentatively ready + DR Defaulted comparison operator function for non-classes Unknown @@ -15142,7 +15142,7 @@ and POD class 2556 - DR + DRWP Unusable promise::return_void Unknown @@ -15166,15 +15166,15 @@ and POD class 2560 - tentatively ready + DR Parameter type determination in a requirement-parameter-list Unknown - + 2561 - review + tentatively ready Conversion to function pointer for lambda with explicit object parameter - Not Resolved* + No 2562 @@ -15214,7 +15214,7 @@ and POD class 2568 - tentatively ready + DR Access checking during synthesis of defaulted comparison operator Unknown @@ -15226,7 +15226,7 @@ and POD class 2570 - DR + DRWP Clarify constexpr for defaulted functions Unknown @@ -15332,11 +15332,11 @@ and POD class Visible side effects and initial value of an object Not resolved - + 2588 - drafting + tentatively ready friend declarations and module linkage - Not resolved + Unknown 2589 @@ -15352,7 +15352,7 @@ and POD class 2591 - DR + DRWP Implicit change of active union member for anonymous union in union Unknown @@ -15376,7 +15376,7 @@ and POD class 2595 - DR + DRWP "More constrained" for eligible special member functions Unknown @@ -15406,7 +15406,7 @@ and POD class 2600 - DR + DRWP Type dependency of placeholder types Unknown @@ -15574,7 +15574,7 @@ and POD class 2628 - DR + DRWP Implicit deduction guides should propagate constraints No @@ -15610,7 +15610,7 @@ and POD class 2634 - tentatively ready + DR Avoid circularity in specification of scope for friend class declarations Unknown @@ -15628,13 +15628,13 @@ and POD class 2637 - tentatively ready + DR Injected-class-name as a simple-template-id Unknown 2638 - tentatively ready + DR Improve the example for initializing by initializer list Unknown @@ -15748,7 +15748,7 @@ and POD class 2657 - tentatively ready + DR Cv-qualification adjustment when binding reference to temporary Unknown @@ -15770,11 +15770,11 @@ and POD class Confusing term "this parameter" Not resolved - + 2661 - open + DR Missing disambiguation rule for pure-specifier vs. brace-or-equal-initializer - Not resolved + Unknown 2662 @@ -15814,7 +15814,7 @@ and POD class 2668 - tentatively ready + DR co_await in a lambda-expression Unknown @@ -15838,7 +15838,7 @@ and POD class 2672 - DR + DRWP Lambda body SFINAE is still required, contrary to intent and note Clang 18 @@ -15940,7 +15940,7 @@ and POD class 2689 - tentatively ready + DR Are cv-qualified std::nullptr_t fundamental types? Unknown @@ -16004,11 +16004,11 @@ and POD class Inconsistency of throw-expression specification Unknown - + 2700 - review + DR #error disallows existing implementation practice - Not resolved + Unknown 2701 @@ -16048,7 +16048,7 @@ and POD class 2707 - tentatively ready + DR Deduction guides cannot have a trailing requires-clause Unknown @@ -16088,11 +16088,11 @@ and POD class Initialization of reference-to-aggregate from designated initializer list Unknown - + 2714 - open + DR Implicit deduction guides omit properties from the parameter-declaration-clause of a constructor - Not resolved + Unknown 2715 @@ -16156,7 +16156,7 @@ and POD class 2725 - DR + DRWP Overload resolution for non-call of class member access Unknown @@ -16172,11 +16172,11 @@ and POD class Importing header units synthesized from source files Not resolved - + 2728 - open + tentatively ready Evaluation of conversions in a delete-expression - Not resolved + Unknown 2729 @@ -16204,7 +16204,7 @@ and POD class 2733 - DR + DRWP Applying [[maybe_unused]] to a label Unknown @@ -16228,7 +16228,7 @@ and POD class 2737 - open + review Temporary lifetime extension for reference init-captures Not resolved @@ -16258,7 +16258,7 @@ and POD class 2742 - open + drafting Guaranteed copy elision for brace-initialization from prvalue Not resolved @@ -16274,33 +16274,33 @@ and POD class Multiple objects of the same type at the same address Not resolved - + 2745 - open + DR Dependent odr-use in generic lambdas - Not resolved + Unknown - + 2746 - open + DR Checking of default template arguments - Not resolved + Unknown 2747 - DR + DRWP Cannot depend on an already-deleted splice Unknown 2748 - tentatively ready + DR Accessing static data members via null pointer Unknown 2749 - DR + DRWP Treatment of "pointer to void" for relational comparisons Unknown @@ -16324,19 +16324,19 @@ and POD class 2753 - DR + DRWP Storage reuse for string literal objects and backing arrays Unknown 2754 - DR + DRWP Using *this in explicit object member functions that are coroutines Unknown 2755 - DR + DRWP Incorrect wording applied by P2738R1 Unknown @@ -16354,43 +16354,43 @@ and POD class 2758 - DR + DRWP What is "access and ambiguity control"? Unknown 2759 - DR + DRWP [[no_unique_address] and common initial sequence Clang 19 2760 - DR + DRWP Defaulted constructor that is an immediate function Unknown 2761 - DR + DRWP Implicitly invoking the deleted destructor of an anonymous union member Unknown 2762 - DR + DRWP Type of implicit object parameter Unknown 2763 - DR + DRWP Ignorability of [[noreturn]] during constant evaluation Unknown 2764 - DR + DRWP Use of placeholders affecting name mangling Unknown @@ -16403,7 +16403,8 @@ and POD class 2766 open - Repeated evaluation of a string-literal may yield different objects + Repeated evaluation of a string-literal may yield different +objects Not resolved @@ -16414,7 +16415,7 @@ and POD class 2768 - DR + DRWP Assignment to enumeration variable with a braced-init-list Unknown @@ -16430,15 +16431,15 @@ and POD class Trailing requires-clause can refer to function parameters before they are substituted into Not resolved - + 2771 - open + DR Transformation for unqualified-ids in address operator - Not resolved + Unknown 2772 - DR + DRWP Missing Annex C entry for linkage effects of linkage-specification Unknown @@ -16456,7 +16457,7 @@ and POD class 2775 - tentatively ready + DR Unclear argument type for copy of exception object Unknown @@ -16466,15 +16467,15 @@ and POD class Substitution failure and implementation limits Not resolved - + 2777 - open + DR Type of id-expression denoting a template parameter object - Not resolved + Unknown 2778 - open + review Trivial destructor does not imply constant destruction Not resolved @@ -16486,7 +16487,7 @@ and POD class 2780 - DR + DRWP reinterpret_cast to reference to function types Unknown @@ -16504,7 +16505,7 @@ and POD class 2783 - DR + DRWP Handling of deduction guides in global-module-fragment Unknown @@ -16516,7 +16517,7 @@ and POD class 2785 - DR + DRWP Type-dependence of requires-expression Unknown @@ -16540,7 +16541,7 @@ and POD class 2789 - DR + DRWP Overload resolution with implicit and explicit object member functions Clang 18 @@ -16552,19 +16553,19 @@ and POD class 2791 - DR + DRWP Unclear phrasing about "returning to the caller" Unknown 2792 - DR + DRWP Clean up specification of noexcept operator Unknown 2793 - DR + DRWP Block-scope declaration conflicting with parameter name Unknown @@ -16576,25 +16577,25 @@ and POD class 2795 - DR + DRWP Overlapping empty subobjects with different cv-qualification Unknown 2796 - DR + DRWP Function pointer conversions for relational operators Unknown 2797 - open + review Meaning of "corresponds" for rewritten operator candidates Not resolved 2798 - DR + DRWP Manifestly constant evaluation of the static_assert message Clang 17 @@ -16612,7 +16613,7 @@ and POD class 2801 - DR + DRWP Reference binding with reference-related types Unknown @@ -16624,7 +16625,7 @@ and POD class 2803 - tentatively ready + DR Overload resolution for reference binding of similar types Unknown @@ -16642,13 +16643,13 @@ and POD class 2806 - DR + DRWP Make a type-requirement a type-only context Unknown 2807 - DR + DRWP Destructors declared consteval Unknown @@ -16660,19 +16661,19 @@ and POD class 2809 - tentatively ready + DR An implicit definition does not redeclare a function Unknown 2810 - tentatively ready + DR Requiring the absence of diagnostics for templates Unknown 2811 - tentatively ready + DR Clarify "use" of main Unknown @@ -16682,11 +16683,11 @@ and POD class Allocation with explicit alignment Not resolved - + 2813 - review + DR Class member access with prvalues - Not resolved + Unknown 2814 @@ -16712,59 +16713,59 @@ and POD class sizeof(abstract class) is underspecified Not resolved - + 2818 - review + tentatively ready Use of predefined reserved identifiers - Not resolved + Unknown - + 2819 - review + tentatively ready Cast from null pointer value in a constant expression - Not resolved + Unknown - + 2820 - open + DR Value-initialization and default constructors - Not resolved + Unknown 2821 - open + review Lifetime, zero-initialization, and dynamic initialization Not resolved 2822 - tentatively ready + DR Side-effect-free pointer zap Unknown 2823 - DR + DRWP Implicit undefined behavior when dereferencing pointers Unknown 2824 - tentatively ready + DR Copy-initialization of arrays Unknown 2825 - tentatively ready + DR Range-based for statement using a braced-init-list Unknown - + 2826 - tentatively ready + drafting Missing definition of "temporary expression" - Unknown + Not resolved 2827 @@ -16772,11 +16773,11 @@ and POD class Representation of unsigned integral types Not resolved - + 2828 - review + DR Ambiguous interpretation of C-style cast - Not resolved + Unknown 2829 @@ -16784,17 +16785,17 @@ and POD class Redundant case in restricting user-defined conversion sequences Not resolved - + 2830 - open + DR Top-level cv-qualification should be ignored for list-initialization - Not resolved + Unknown - + 2831 - open + DR Non-templated function definitions and requires-clauses - Not resolved + Unknown 2832 @@ -16810,7 +16811,7 @@ and POD class 2834 - open + review Partial ordering and explicit object parameters Not resolved @@ -16822,7 +16823,7 @@ and POD class 2836 - open + review Conversion rank of long double and extended floating-point types Not resolved @@ -16855,6 +16856,246 @@ and POD class open When do const objects start being const? Not resolved + + + 2842 + open + Preferring an initializer_list over a single value + Not resolved + + + 2843 + review + Undated reference to Unicode makes C++ a moving target + Not resolved + + + 2844 + open + Enumerating a finite set of built-in candidates + Not resolved + + + 2845 + DR + Make the closure type of a captureless lambda a structural type + Unknown + + + 2846 + DR + Out-of-class definitions of explicit object member functions + Unknown + + + 2847 + review + Constrained explicit specializations of function templates at class scope + Not Resolved* + + + 2848 + DR + Omitting an empty template argument list for explicit instantiation + Unknown + + + 2849 + DR + Parameter objects are not temporary objects + Unknown + + + 2850 + DR + Unclear storage duration for function parameter objects + Unknown + + + 2851 + DR + Allow floating-point conversions in converted constant expressions + Unknown + + + 2852 + open + Complete-class contexts and class-scope lambdas + Not resolved + + + 2853 + DR + Pointer arithmetic with pointer to hypothetical element + Unknown + + + 2854 + DR + Storage duration of exception objects + Unknown + + + 2855 + DR + Undefined behavior in postfix increment + Unknown + + + 2856 + DR + Copy-list-initialization with explicit default constructors + Unknown + + + 2857 + DR + Argument-dependent lookup with incomplete class types + Unknown + + + 2858 + tentatively ready + Declarative nested-name-specifiers and pack-index-specifiers + Clang 19 + + + 2859 + tentatively ready + Value-initialization with multiple default constructors + Unknown + + + 2860 + dup + Remove and fix the term "vacuous initialization" + Unknown + + + 2861 + tentatively ready + dynamic_cast on bad pointer value + Unknown + + + 2862 + tentatively ready + Unclear boundaries of template declarations + Unknown + + + 2863 + tentatively ready + Unclear synchronization requirements for object lifetime rules + Unknown + + + 2864 + tentatively ready + Narrowing floating-point conversions + Unknown + + + 2865 + open + Regression on result of conditional operator + Not resolved + + + 2866 + open + Observing the effects of [[no_unique_address]] + Not resolved + + + 2867 + open + Order of initialization for structured bindings + Not resolved + + + 2868 + open + Self-references in trivially copyable objects as function return values + Not resolved + + + 2869 + open + this in local classes + Not resolved + + + 2870 + open + Combining absent encoding-prefixes + Not resolved + + + 2871 + tentatively ready + User-declared constructor templates inhibiting default constructors + Unknown + + + 2872 + open + Linkage and unclear "can be referred to" + Not resolved + + + 2873 + open + Taking the address of a function involving template argument deduction + Not resolved + + + 2874 + open + Qualified declarations of partial specializations + Not resolved + + + 2875 + open + Missing support for round-tripping nullptr through indirection/address operators + Not resolved + + + 2876 + open + Disambiguation of T x = delete("text") + Not resolved + + + 2877 + open + Type-only lookup for using-enum-declarator + Not resolved + + + 2878 + open + C-style casts to reference types + Not resolved + + + 2879 + open + Undesired outcomes with const_cast + Not resolved + + + 2880 + open + Accessibility check for destructor of incomplete class type + Not resolved + + + 2881 + open + Type restrictions for the explicit object parameter of a lambda + Not resolved diff --git a/clang/www/make_cxx_dr_status b/clang/www/make_cxx_dr_status index 7c0cf77a1524..57f1dc86fd12 100755 --- a/clang/www/make_cxx_dr_status +++ b/clang/www/make_cxx_dr_status @@ -5,7 +5,7 @@ latest_release = 18 clang_www_dir = os.path.dirname(__file__) default_issue_list_path = os.path.join(clang_www_dir, 'cwg_index.html') -issue_list_url = "https://www.open-std.org/jtc1/sc22/wg21/docs/cwg_index.html" +issue_list_url = "https://raw.githubusercontent.com/cplusplus/CWG/gh-pages/issues/cwg_index.html" output = os.path.join(clang_www_dir, 'cxx_dr_status.html') dr_test_dir = os.path.join(clang_www_dir, '../test/CXX/drs') @@ -138,10 +138,10 @@ def availability(issue): unresolved_status = '' proposed_resolution = '' - unresolved_status_match = re.search(r' (open|drafting|review)', status) + unresolved_status_match = re.search(r' (open|drafting|review|tentatively ready)', status) if unresolved_status_match: unresolved_status = unresolved_status_match.group(1) - proposed_resolution_match = re.search(r' (open|drafting|review) (\d{4}-\d{2}(?:-\d{2})?|P\d{4}R\d+)$', status) + proposed_resolution_match = re.search(r' (open|drafting|review|tentatively ready) (\d{4}-\d{2}(?:-\d{2})?|P\d{4}R\d+)$', status) if proposed_resolution_match is None: raise AvailabilityError('Issue {}: \'{}\' status should be followed by a paper number (P1234R5) or proposed resolution in YYYY-MM-DD format'.format(dr.issue, unresolved_status)) proposed_resolution = proposed_resolution_match.group(2) -- GitLab From b35bdb1d7b31c2267af14ee7e097c78d89c3ddb0 Mon Sep 17 00:00:00 2001 From: oltolm Date: Mon, 29 Apr 2024 13:05:19 +0200 Subject: [PATCH 209/301] llvm-rc: add support for MENU in DIALOG(EX) (#89409) Adds support for `MENU` in `DIALOG(EX)` to `llvm-rc`. Fixes #49559. --- .../tools/llvm-rc/Inputs/dialog-with-menu.rc | 16 ++++++++++ llvm/test/tools/llvm-rc/dialog-with-menu.test | 32 +++++++++++++++++++ llvm/tools/llvm-rc/ResourceFileWriter.cpp | 10 ++++-- llvm/tools/llvm-rc/ResourceFileWriter.h | 5 ++- llvm/tools/llvm-rc/ResourceScriptParser.cpp | 7 ++++ llvm/tools/llvm-rc/ResourceScriptParser.h | 1 + llvm/tools/llvm-rc/ResourceScriptStmt.cpp | 4 +++ llvm/tools/llvm-rc/ResourceScriptStmt.h | 13 ++++++++ llvm/tools/llvm-rc/ResourceVisitor.h | 2 ++ 9 files changed, 86 insertions(+), 4 deletions(-) create mode 100644 llvm/test/tools/llvm-rc/Inputs/dialog-with-menu.rc create mode 100644 llvm/test/tools/llvm-rc/dialog-with-menu.test diff --git a/llvm/test/tools/llvm-rc/Inputs/dialog-with-menu.rc b/llvm/test/tools/llvm-rc/Inputs/dialog-with-menu.rc new file mode 100644 index 000000000000..bb79dca399c2 --- /dev/null +++ b/llvm/test/tools/llvm-rc/Inputs/dialog-with-menu.rc @@ -0,0 +1,16 @@ +101 DIALOG 0, 0, 362, 246 +STYLE 0x40l | 0x0004l | 0x0008l | 0x0800l | 0x00020000l | + 0x00010000l | 0x80000000l | 0x10000000l | 0x02000000l | 0x00C00000l | + 0x00080000l | 0x00040000l +CAPTION "MakeNSISW" +MENU 104 +FONT 8, "MS Shell Dlg" +BEGIN + CONTROL "",202,"RichEdit20A",0x0004l | 0x0040l | + 0x0100l | 0x0800l | 0x00008000 | + 0x00010000l | 0x00800000l | 0x00200000l,7,22,348,190 + CONTROL "",-1,"Static",0x00000010l,7,220,346,1 + LTEXT "",200,7,230,200,12,0x08000000l + DEFPUSHBUTTON "Test &Installer",203,230,226,60,15,0x08000000l | 0x00010000l + PUSHBUTTON "&Close",2,296,226,49,15,0x00010000l +END diff --git a/llvm/test/tools/llvm-rc/dialog-with-menu.test b/llvm/test/tools/llvm-rc/dialog-with-menu.test new file mode 100644 index 000000000000..2529e9c1722b --- /dev/null +++ b/llvm/test/tools/llvm-rc/dialog-with-menu.test @@ -0,0 +1,32 @@ +; RUN: llvm-rc -no-preprocess /FO %t -- %p/Inputs/dialog-with-menu.rc +; RUN: llvm-readobj %t | FileCheck %s + +CHECK: Resource type (int): DIALOG (ID 5) +CHECK-NEXT: Resource name (int): 101 +CHECK-NEXT: Data version: 0 +CHECK-NEXT: Memory flags: 0x1030 +CHECK-NEXT: Language ID: 1033 +CHECK-NEXT: Version (major): 0 +CHECK-NEXT: Version (minor): 0 +CHECK-NEXT: Characteristics: 0 +CHECK-NEXT: Data size: 278 +CHECK-NEXT: Data: ( +CHECK-NEXT: 0000: 4C08CF92 00000000 05000000 00006A01 |L.............j.| +CHECK-NEXT: 0010: F600FFFF 68000000 4D006100 6B006500 |....h...M.a.k.e.| +CHECK-NEXT: 0020: 4E005300 49005300 57000000 08004D00 |N.S.I.S.W.....M.| +CHECK-NEXT: 0030: 53002000 53006800 65006C00 6C002000 |S. .S.h.e.l.l. .| +CHECK-NEXT: 0040: 44006C00 67000000 4489A150 00000000 |D.l.g...D..P....| +CHECK-NEXT: 0050: 07001600 5C01BE00 CA005200 69006300 |....\.....R.i.c.| +CHECK-NEXT: 0060: 68004500 64006900 74003200 30004100 |h.E.d.i.t.2.0.A.| +CHECK-NEXT: 0070: 00000000 00000000 10000050 00000000 |...........P....| +CHECK-NEXT: 0080: 0700DC00 5A010100 FFFF5300 74006100 |....Z.....S.t.a.| +CHECK-NEXT: 0090: 74006900 63000000 00000000 00000258 |t.i.c..........X| +CHECK-NEXT: 00A0: 00000000 0700E600 C8000C00 C800FFFF |................| +CHECK-NEXT: 00B0: 82000000 00000000 01000158 00000000 |...........X....| +CHECK-NEXT: 00C0: E600E200 3C000F00 CB00FFFF 80005400 |....<.........T.| +CHECK-NEXT: 00D0: 65007300 74002000 26004900 6E007300 |e.s.t. .&.I.n.s.| +CHECK-NEXT: 00E0: 74006100 6C006C00 65007200 00000000 |t.a.l.l.e.r.....| +CHECK-NEXT: 00F0: 00000150 00000000 2801E200 31000F00 |...P....(...1...| +CHECK-NEXT: 0100: 0200FFFF 80002600 43006C00 6F007300 |......&.C.l.o.s.| +CHECK-NEXT: 0110: 65000000 0000 |e.....| +CHECK-NEXT: ) diff --git a/llvm/tools/llvm-rc/ResourceFileWriter.cpp b/llvm/tools/llvm-rc/ResourceFileWriter.cpp index d507525970ec..85b59532bb83 100644 --- a/llvm/tools/llvm-rc/ResourceFileWriter.cpp +++ b/llvm/tools/llvm-rc/ResourceFileWriter.cpp @@ -550,6 +550,11 @@ Error ResourceFileWriter::visitVersionStmt(const VersionStmt *Stmt) { return Error::success(); } +Error ResourceFileWriter::visitMenuStmt(const MenuStmt *Stmt) { + ObjectData.Menu = Stmt->Value; + return Error::success(); +} + Error ResourceFileWriter::writeResource( const RCResource *Res, Error (ResourceFileWriter::*BodyWriter)(const RCResource *)) { @@ -1132,9 +1137,8 @@ Error ResourceFileWriter::writeDialogBody(const RCResource *Base) { ulittle16_t(Res->Height)}; writeObject(Middle); - // MENU field. As of now, we don't keep them in the state and can peacefully - // think there is no menu attached to the dialog. - writeInt(0); + // MENU field. + RETURN_IF_ERROR(writeIntOrString(ObjectData.Menu)); // Window CLASS field. RETURN_IF_ERROR(writeIntOrString(ObjectData.Class)); diff --git a/llvm/tools/llvm-rc/ResourceFileWriter.h b/llvm/tools/llvm-rc/ResourceFileWriter.h index 9413a0eecdac..82d3e3b9e9e8 100644 --- a/llvm/tools/llvm-rc/ResourceFileWriter.h +++ b/llvm/tools/llvm-rc/ResourceFileWriter.h @@ -16,6 +16,7 @@ #include "ResourceScriptStmt.h" #include "ResourceVisitor.h" +#include "llvm/ADT/StringRef.h" #include "llvm/Support/Endian.h" namespace llvm { @@ -68,6 +69,7 @@ public: Error visitLanguageStmt(const LanguageResource *) override; Error visitStyleStmt(const StyleStmt *) override; Error visitVersionStmt(const VersionStmt *) override; + Error visitMenuStmt(const MenuStmt *) override; // Stringtables are output at the end of .res file. We need a separate // function to do it. @@ -92,10 +94,11 @@ public: }; std::optional Font; IntOrString Class; + IntOrString Menu; ObjectInfo() : LanguageInfo(0), Characteristics(0), VersionInfo(0), - Class(StringRef()) {} + Class(StringRef()), Menu(StringRef()) {} } ObjectData; struct StringTableInfo { diff --git a/llvm/tools/llvm-rc/ResourceScriptParser.cpp b/llvm/tools/llvm-rc/ResourceScriptParser.cpp index 4f02fa502d24..69798152c1f2 100644 --- a/llvm/tools/llvm-rc/ResourceScriptParser.cpp +++ b/llvm/tools/llvm-rc/ResourceScriptParser.cpp @@ -430,6 +430,8 @@ RCParser::parseSingleOptionalStatement(OptStmtType StmtsType) { return parseFontStmt(StmtsType); if (TypeToken->equals_insensitive("STYLE")) return parseStyleStmt(); + if (TypeToken->equals_insensitive("MENU")) + return parseMenuStmt(); } return getExpectedError("optional statement type, BEGIN or '{'", @@ -965,6 +967,11 @@ RCParser::ParseOptionType RCParser::parseExStyleStmt() { return std::make_unique(*Arg); } +RCParser::ParseOptionType RCParser::parseMenuStmt() { + ASSIGN_OR_RETURN(Arg, readIntOrString()); + return std::make_unique(*Arg); +} + Error RCParser::getExpectedError(const Twine &Message, bool IsAlreadyRead) { return make_error( Message, IsAlreadyRead ? std::prev(CurLoc) : CurLoc, End); diff --git a/llvm/tools/llvm-rc/ResourceScriptParser.h b/llvm/tools/llvm-rc/ResourceScriptParser.h index 603afd8d73fb..aa7f847187c4 100644 --- a/llvm/tools/llvm-rc/ResourceScriptParser.h +++ b/llvm/tools/llvm-rc/ResourceScriptParser.h @@ -176,6 +176,7 @@ private: ParseOptionType parseExStyleStmt(); ParseOptionType parseFontStmt(OptStmtType DialogType); ParseOptionType parseStyleStmt(); + ParseOptionType parseMenuStmt(); // Raises an error. If IsAlreadyRead = false (default), this complains about // the token that couldn't be parsed. If the flag is on, this complains about diff --git a/llvm/tools/llvm-rc/ResourceScriptStmt.cpp b/llvm/tools/llvm-rc/ResourceScriptStmt.cpp index 62df7999252f..a7f3df0863e7 100644 --- a/llvm/tools/llvm-rc/ResourceScriptStmt.cpp +++ b/llvm/tools/llvm-rc/ResourceScriptStmt.cpp @@ -309,5 +309,9 @@ raw_ostream &ExStyleStmt::log(raw_ostream &OS) const { return OS << "ExStyle: " << Value << "\n"; } +raw_ostream &MenuStmt::log(raw_ostream &OS) const { + return OS << "Menu: " << Value << "\n"; +} + } // namespace rc } // namespace llvm diff --git a/llvm/tools/llvm-rc/ResourceScriptStmt.h b/llvm/tools/llvm-rc/ResourceScriptStmt.h index 70e7cec9cb84..05865e582859 100644 --- a/llvm/tools/llvm-rc/ResourceScriptStmt.h +++ b/llvm/tools/llvm-rc/ResourceScriptStmt.h @@ -993,6 +993,19 @@ public: Error visit(Visitor *V) const override { return V->visitExStyleStmt(this); } }; +// MENU optional statement. +// +// Ref: https://learn.microsoft.com/en-us/windows/win32/menurc/menu-statement +class MenuStmt : public OptionalStmt { +public: + IntOrString Value; + + MenuStmt(IntOrString NameOrId) : Value(NameOrId) {} + raw_ostream &log(raw_ostream &) const override; + Twine getResourceTypeName() const override { return "MENU"; } + Error visit(Visitor *V) const override { return V->visitMenuStmt(this); } +}; + // CLASS optional statement. // // Ref: msdn.microsoft.com/en-us/library/windows/desktop/aa380883(v=vs.85).aspx diff --git a/llvm/tools/llvm-rc/ResourceVisitor.h b/llvm/tools/llvm-rc/ResourceVisitor.h index a950cd7555ec..a121a0a507c2 100644 --- a/llvm/tools/llvm-rc/ResourceVisitor.h +++ b/llvm/tools/llvm-rc/ResourceVisitor.h @@ -28,6 +28,7 @@ class FontStmt; class LanguageResource; class StyleStmt; class VersionStmt; +class MenuStmt; class Visitor { public: @@ -52,6 +53,7 @@ public: virtual Error visitLanguageStmt(const LanguageResource *) = 0; virtual Error visitStyleStmt(const StyleStmt *) = 0; virtual Error visitVersionStmt(const VersionStmt *) = 0; + virtual Error visitMenuStmt(const MenuStmt *) = 0; virtual ~Visitor() {} }; -- GitLab From 95395ee51124792302390305b02cbeace5f07611 Mon Sep 17 00:00:00 2001 From: Simon Pilgrim Date: Mon, 29 Apr 2024 12:05:37 +0100 Subject: [PATCH 210/301] [X86] memcmp tests - merge check-prefixes. NFC. --- llvm/test/CodeGen/X86/memcmp-minsize-x32.ll | 4 ++-- llvm/test/CodeGen/X86/memcmp-minsize.ll | 6 +++--- llvm/test/CodeGen/X86/memcmp-optsize-x32.ll | 4 ++-- llvm/test/CodeGen/X86/memcmp-optsize.ll | 6 +++--- llvm/test/CodeGen/X86/memcmp-pgso-x32.ll | 4 ++-- llvm/test/CodeGen/X86/memcmp-pgso.ll | 6 +++--- 6 files changed, 15 insertions(+), 15 deletions(-) diff --git a/llvm/test/CodeGen/X86/memcmp-minsize-x32.ll b/llvm/test/CodeGen/X86/memcmp-minsize-x32.ll index ae1320f8b086..200a8184d4bd 100644 --- a/llvm/test/CodeGen/X86/memcmp-minsize-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-minsize-x32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefix=X86 --check-prefix=X86-NOSSE -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE2 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2 ; This tests codegen time inlining/optimization of memcmp ; rdar://6480398 diff --git a/llvm/test/CodeGen/X86/memcmp-minsize.ll b/llvm/test/CodeGen/X86/memcmp-minsize.ll index 544d1c49f26b..9c20f3e0cdef 100644 --- a/llvm/test/CodeGen/X86/memcmp-minsize.ll +++ b/llvm/test/CodeGen/X86/memcmp-minsize.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2 ; This tests codegen time inlining/optimization of memcmp ; rdar://6480398 diff --git a/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll b/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll index 762691151f4b..3db6ae8b76b2 100644 --- a/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-optsize-x32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefix=X86 --check-prefix=X86-NOSSE -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE2 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2 ; This tests codegen time inlining/optimization of memcmp ; rdar://6480398 diff --git a/llvm/test/CodeGen/X86/memcmp-optsize.ll b/llvm/test/CodeGen/X86/memcmp-optsize.ll index c0c7b98d471c..edd61641ad2a 100644 --- a/llvm/test/CodeGen/X86/memcmp-optsize.ll +++ b/llvm/test/CodeGen/X86/memcmp-optsize.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2 ; This tests codegen time inlining/optimization of memcmp ; rdar://6480398 diff --git a/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll b/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll index cb45fd3ebb90..1c301da26bea 100644 --- a/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll +++ b/llvm/test/CodeGen/X86/memcmp-pgso-x32.ll @@ -1,6 +1,6 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefix=X86 --check-prefix=X86-NOSSE -; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefix=X86 --check-prefix=X86-SSE2 +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=cmov | FileCheck %s --check-prefixes=X86,X86-NOSSE +; RUN: llc < %s -mtriple=i686-unknown-unknown -mattr=+sse2 | FileCheck %s --check-prefixes=X86,X86-SSE2 ; This tests codegen time inlining/optimization of memcmp ; rdar://6480398 diff --git a/llvm/test/CodeGen/X86/memcmp-pgso.ll b/llvm/test/CodeGen/X86/memcmp-pgso.ll index 720344a22e43..1ee3317b9c96 100644 --- a/llvm/test/CodeGen/X86/memcmp-pgso.ll +++ b/llvm/test/CodeGen/X86/memcmp-pgso.ll @@ -1,7 +1,7 @@ ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py -; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefix=X64 --check-prefix=X64-SSE2 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX1 -; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefix=X64 --check-prefix=X64-AVX --check-prefix=X64-AVX2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s --check-prefixes=X64,X64-SSE2 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX1 +; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=avx2 | FileCheck %s --check-prefixes=X64,X64-AVX,X64-AVX2 ; This tests codegen time inlining/optimization of memcmp ; rdar://6480398 -- GitLab From 55c6bda01ef5a166a69b43956775272d9d67bda5 Mon Sep 17 00:00:00 2001 From: Bjorn Pettersson Date: Mon, 29 Apr 2024 11:11:59 +0200 Subject: [PATCH 211/301] Revert "Revert "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" and more..." This reverts commit 16bd10a38730fed27a3bf111076b8ef7a7e7b3ee. Re-applies: b3c55b707110084a9f50a16aade34c3be6fa18da - "[SelectionDAG] Handle more opcodes in canCreateUndefOrPoison (#84921)" 8e2f6495c0bac1dd6ee32b6a0d24152c9c343624 - "[DAGCombiner] Do not always fold FREEZE over BUILD_VECTOR (#85932)" 73472c5996716cda0dbb3ddb788304e0e7e6a323 - "[SelectionDAG] Treat CopyFromReg as freezing the value (#85932)" with a fix in DAGCombiner::visitFREEZE. --- llvm/include/llvm/CodeGen/ISDOpcodes.h | 1 + llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp | 26 + .../lib/CodeGen/SelectionDAG/SelectionDAG.cpp | 17 +- llvm/test/CodeGen/AArch64/combine-mul.ll | 7 +- llvm/test/CodeGen/AMDGPU/div_i128.ll | 96 +-- llvm/test/CodeGen/AMDGPU/rem_i128.ll | 475 ++++++------- .../lasx/ir-instruction/insertelement.ll | 42 +- .../lsx/ir-instruction/insertelement.ll | 42 +- llvm/test/CodeGen/RISCV/alu64.ll | 2 +- .../CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll | 16 +- llvm/test/CodeGen/RISCV/bfloat-convert.ll | 108 ++- llvm/test/CodeGen/RISCV/double-convert.ll | 111 ++-- .../CodeGen/RISCV/double-round-conv-sat.ll | 138 ++-- llvm/test/CodeGen/RISCV/float-convert.ll | 158 ++--- .../CodeGen/RISCV/float-round-conv-sat.ll | 288 ++++---- llvm/test/CodeGen/RISCV/forced-atomics.ll | 4 +- llvm/test/CodeGen/RISCV/fpclamptosat.ll | 4 +- llvm/test/CodeGen/RISCV/half-convert.ll | 268 ++++---- .../test/CodeGen/RISCV/half-round-conv-sat.ll | 624 +++++++++--------- llvm/test/CodeGen/RISCV/iabs.ll | 4 +- .../CodeGen/RISCV/rvv/fpclamptosat_vec.ll | 521 +++++++-------- llvm/test/CodeGen/X86/abdu-vector-128.ll | 54 +- .../CodeGen/X86/apx/kmov-postrapseudos.ll | 10 +- .../CodeGen/X86/avx512-broadcast-arith.ll | 10 +- llvm/test/CodeGen/X86/combine-mul.ll | 8 +- .../X86/div-rem-pair-recomposition-signed.ll | 377 ++++++----- llvm/test/CodeGen/X86/fold-masked-merge.ll | 4 +- llvm/test/CodeGen/X86/freeze-binary.ll | 50 +- llvm/test/CodeGen/X86/freeze-combine.ll | 16 +- llvm/test/CodeGen/X86/freeze-vector.ll | 20 + llvm/test/CodeGen/X86/gfni-funnel-shifts.ll | 4 +- llvm/test/CodeGen/X86/gfni-rotates.ll | 14 +- llvm/test/CodeGen/X86/known-never-zero.ll | 30 +- llvm/test/CodeGen/X86/midpoint-int-vec-128.ll | 94 ++- llvm/test/CodeGen/X86/midpoint-int-vec-256.ll | 32 +- llvm/test/CodeGen/X86/midpoint-int-vec-512.ll | 80 ++- llvm/test/CodeGen/X86/pr38539.ll | 202 +++--- llvm/test/CodeGen/X86/pr62286.ll | 31 +- .../CodeGen/X86/scheduler-backtracking.ll | 2 +- llvm/test/CodeGen/X86/sdiv_fix_sat.ll | 250 +++---- .../test/CodeGen/X86/setcc-non-simple-type.ll | 78 ++- llvm/test/CodeGen/X86/vec_saddo.ll | 14 +- llvm/test/CodeGen/X86/vec_ssubo.ll | 14 +- llvm/test/CodeGen/X86/vec_uaddo.ll | 14 +- llvm/test/CodeGen/X86/vec_usubo.ll | 14 +- llvm/test/CodeGen/X86/vector-bo-select.ll | 10 +- llvm/test/CodeGen/X86/vector-fshr-128.ll | 86 +-- llvm/test/CodeGen/X86/vector-fshr-256.ll | 28 +- llvm/test/CodeGen/X86/vector-fshr-sub128.ll | 12 +- llvm/test/CodeGen/X86/vector-shift-shl-128.ll | 12 +- 50 files changed, 2224 insertions(+), 2298 deletions(-) diff --git a/llvm/include/llvm/CodeGen/ISDOpcodes.h b/llvm/include/llvm/CodeGen/ISDOpcodes.h index 078a936b061a..6429947958ee 100644 --- a/llvm/include/llvm/CodeGen/ISDOpcodes.h +++ b/llvm/include/llvm/CodeGen/ISDOpcodes.h @@ -205,6 +205,7 @@ enum NodeType { /// CopyFromReg - This node indicates that the input value is a virtual or /// physical register that is defined outside of the scope of this /// SelectionDAG. The register is available from the RegisterSDNode object. + /// Note that CopyFromReg is considered as also freezing the value. CopyFromReg, /// UNDEF - An undefined node. diff --git a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp index f8949b926922..4b81185c6e31 100644 --- a/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp @@ -15459,6 +15459,12 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { if (DAG.isGuaranteedNotToBeUndefOrPoison(N0, /*PoisonOnly*/ false)) return N0; + // We currently avoid folding freeze over SRA/SRL, due to the problems seen + // with (freeze (assert ext)) blocking simplifications of SRA/SRL. See for + // example https://reviews.llvm.org/D136529#4120959. + if (N0.getOpcode() == ISD::SRA || N0.getOpcode() == ISD::SRL) + return SDValue(); + // Fold freeze(op(x, ...)) -> op(freeze(x), ...). // Try to push freeze through instructions that propagate but don't produce // poison as far as possible. If an operand of freeze follows three @@ -15475,6 +15481,26 @@ SDValue DAGCombiner::visitFREEZE(SDNode *N) { N0.getOpcode() == ISD::BUILD_PAIR || N0.getOpcode() == ISD::CONCAT_VECTORS; + // Avoid turning a BUILD_VECTOR that can be recognized as "all zeros", "all + // ones" or "constant" into something that depends on FrozenUndef. We can + // instead pick undef values to keep those properties, while at the same time + // folding away the freeze. + // If we implement a more general solution for folding away freeze(undef) in + // the future, then this special handling can be removed. + if (N0.getOpcode() == ISD::BUILD_VECTOR) { + SDLoc DL(N0); + EVT VT = N0.getValueType(); + if (llvm::ISD::isBuildVectorAllOnes(N0.getNode())) + return DAG.getAllOnesConstant(DL, VT); + if (llvm::ISD::isBuildVectorOfConstantSDNodes(N0.getNode())) { + SmallVector NewVecC; + for (const SDValue &Op : N0->op_values()) + NewVecC.push_back( + Op.isUndef() ? DAG.getConstant(0, DL, Op.getValueType()) : Op); + return DAG.getBuildVector(VT, DL, NewVecC); + } + } + SmallSetVector MaybePoisonOperands; for (SDValue Op : N0->ops()) { if (DAG.isGuaranteedNotToBeUndefOrPoison(Op, /*PoisonOnly*/ false, diff --git a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp index 224c0c5ee970..dfbfaa8c894f 100644 --- a/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp +++ b/llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp @@ -5063,6 +5063,7 @@ bool SelectionDAG::isGuaranteedNotToBeUndefOrPoison(SDValue Op, case ISD::VALUETYPE: case ISD::FrameIndex: case ISD::TargetFrameIndex: + case ISD::CopyFromReg: return true; case ISD::UNDEF: @@ -5136,6 +5137,16 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::FREEZE: case ISD::CONCAT_VECTORS: case ISD::INSERT_SUBVECTOR: + case ISD::SADDSAT: + case ISD::UADDSAT: + case ISD::SSUBSAT: + case ISD::USUBSAT: + case ISD::MULHU: + case ISD::MULHS: + case ISD::SMIN: + case ISD::SMAX: + case ISD::UMIN: + case ISD::UMAX: case ISD::AND: case ISD::XOR: case ISD::ROTL: @@ -5156,6 +5167,7 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, case ISD::BUILD_PAIR: return false; + case ISD::SELECT_CC: case ISD::SETCC: { // Integer setcc cannot create undef or poison. if (Op.getOperand(0).getValueType().isInteger()) @@ -5165,7 +5177,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, // based on options and flags. The options and flags also cause special // nonan condition codes to be used. Those condition codes may be preserved // even if the nonan flag is dropped somewhere. - ISD::CondCode CCCode = cast(Op.getOperand(2))->get(); + unsigned CCOp = Opcode == ISD::SETCC ? 2 : 4; + ISD::CondCode CCCode = cast(Op.getOperand(CCOp))->get(); if (((unsigned)CCCode & 0x10U)) return true; @@ -5182,6 +5195,8 @@ bool SelectionDAG::canCreateUndefOrPoison(SDValue Op, const APInt &DemandedElts, return false; case ISD::SHL: + case ISD::SRL: + case ISD::SRA: // If the max shift amount isn't in range, then the shift can create poison. return !getValidMaximumShiftAmountConstant(Op, DemandedElts); diff --git a/llvm/test/CodeGen/AArch64/combine-mul.ll b/llvm/test/CodeGen/AArch64/combine-mul.ll index a2b042530809..c49e5ae6620a 100644 --- a/llvm/test/CodeGen/AArch64/combine-mul.ll +++ b/llvm/test/CodeGen/AArch64/combine-mul.ll @@ -44,8 +44,7 @@ define <4 x i1> @PR48683_vec_undef(<4 x i32> %x) { define i64 @combine_mul_self_demandedbits(i64 %x) { ; CHECK-LABEL: combine_mul_self_demandedbits: ; CHECK: // %bb.0: -; CHECK-NEXT: mul x8, x0, x0 -; CHECK-NEXT: and x0, x8, #0xfffffffffffffffd +; CHECK-NEXT: mul x0, x0, x0 ; CHECK-NEXT: ret %1 = mul i64 %x, %x %2 = and i64 %1, -3 @@ -77,7 +76,7 @@ define i8 @one_demanded_bit(i8 %x) { define <2 x i64> @one_demanded_bit_splat(<2 x i64> %x) { ; CHECK-LABEL: one_demanded_bit_splat: ; CHECK: // %bb.0: -; CHECK-NEXT: mov w8, #32 +; CHECK-NEXT: mov w8, #32 // =0x20 ; CHECK-NEXT: shl v0.2d, v0.2d, #5 ; CHECK-NEXT: dup v1.2d, x8 ; CHECK-NEXT: and v0.16b, v0.16b, v1.16b @@ -131,7 +130,7 @@ define i32 @squared_demanded_2_low_bits(i32 %x) { define <2 x i64> @squared_demanded_2_low_bits_splat(<2 x i64> %x) { ; CHECK-LABEL: squared_demanded_2_low_bits_splat: ; CHECK: // %bb.0: -; CHECK-NEXT: mov x8, #-2 +; CHECK-NEXT: mov x8, #-2 // =0xfffffffffffffffe ; CHECK-NEXT: dup v1.2d, x8 ; CHECK-NEXT: orr v0.16b, v0.16b, v1.16b ; CHECK-NEXT: ret diff --git a/llvm/test/CodeGen/AMDGPU/div_i128.ll b/llvm/test/CodeGen/AMDGPU/div_i128.ll index cf99b5d80e13..b2f9bf89d9ec 100644 --- a/llvm/test/CodeGen/AMDGPU/div_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/div_i128.ll @@ -282,21 +282,21 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v16, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v15 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v16 ; GFX9-O0-NEXT: v_mov_b32_e32 v10, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v14 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v4 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v10, v4, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v6, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v10, v4, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v6, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 ; GFX9-O0-NEXT: v_xor_b32_e64 v1, v5, v1 @@ -312,21 +312,21 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, v7 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v8 -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v11 +; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 killed $vgpr7_vgpr8 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v11 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v12 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v3 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v7, vcc, v7, v5, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v8, v3, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v5, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v8, vcc, v8, v5, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v7, v3, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v7, vcc, v2, v5, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v8 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v7 +; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v7 ; GFX9-O0-NEXT: v_xor_b32_e64 v5, v5, v6 ; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v4 ; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 def $vgpr3_vgpr4 killed $exec @@ -339,18 +339,26 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:64 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:52 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:56 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v13 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v14 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:44 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:48 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:36 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:40 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v12 ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v2 ; GFX9-O0-NEXT: v_or_b32_e64 v3, v8, v7 @@ -403,7 +411,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[12:13], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[12:13] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[12:13] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 @@ -439,7 +448,8 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[8:9] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[8:9] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v11 @@ -690,10 +700,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload @@ -903,14 +913,14 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(9) ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) @@ -1028,10 +1038,10 @@ define i128 @v_sdiv_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:36 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:40 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:44 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:48 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:28 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:20 ; 4-byte Folded Reload diff --git a/llvm/test/CodeGen/AMDGPU/rem_i128.ll b/llvm/test/CodeGen/AMDGPU/rem_i128.ll index 6ba66ccf7186..b068d87c4d6f 100644 --- a/llvm/test/CodeGen/AMDGPU/rem_i128.ll +++ b/llvm/test/CodeGen/AMDGPU/rem_i128.ll @@ -242,130 +242,137 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0: ; %bb.0: ; %_udiv-special-cases ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:360 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:352 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-O0-NEXT: ; implicit-def: $vgpr8 : SGPR spill to VGPR lane -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v6 -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v2 -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v1 -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v0 +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:116 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v2 +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:116 ; 4-byte Folded Reload +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v0 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: s_waitcnt vmcnt(1) +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v2 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v6 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v7 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v7 +; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 def $vgpr6_vgpr7 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v9 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr14 killed $vgpr14 def $vgpr14_vgpr15 killed $exec -; GFX9-O0-NEXT: s_waitcnt vmcnt(1) -; GFX9-O0-NEXT: v_mov_b32_e32 v15, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v3 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4_sgpr5 ; GFX9-O0-NEXT: s_mov_b32 s4, 63 -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v14 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v15 -; GFX9-O0-NEXT: v_ashrrev_i64 v[12:13], s4, v[6:7] -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v11, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v8 +; GFX9-O0-NEXT: v_ashrrev_i64 v[11:12], s4, v[10:11] +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:108 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v12 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v13 -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:112 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v12 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, v11 +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:100 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill -; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 -; GFX9-O0-NEXT: v_mov_b32_e32 v7, v9 -; GFX9-O0-NEXT: v_ashrrev_i64 v[6:7], s4, v[6:7] -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v15 -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v13 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v10 -; GFX9-O0-NEXT: v_mov_b32_e32 v11, v14 -; GFX9-O0-NEXT: v_xor_b32_e64 v13, v11, v12 +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:104 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v7 +; GFX9-O0-NEXT: v_mov_b32_e32 v13, v6 +; GFX9-O0-NEXT: v_ashrrev_i64 v[15:16], s4, v[13:14] +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v12 +; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v10 +; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 killed $vgpr8_vgpr9 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v11 +; GFX9-O0-NEXT: v_xor_b32_e64 v13, v8, v12 ; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v5 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v10 -; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v15, v4, v12 -; GFX9-O0-NEXT: ; kill: def $vgpr15 killed $vgpr15 def $vgpr15_vgpr16 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v16, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v9 -; GFX9-O0-NEXT: v_mov_b32_e32 v4, v7 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v4 -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v8 -; GFX9-O0-NEXT: ; kill: def $vgpr6 killed $vgpr6 killed $vgpr6_vgpr7 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v7, v5, v6 +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v2 +; GFX9-O0-NEXT: v_xor_b32_e64 v3, v3, v10 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 killed $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v12 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v7 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v16 +; GFX9-O0-NEXT: v_xor_b32_e64 v9, v8, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 +; GFX9-O0-NEXT: v_mov_b32_e32 v6, v15 +; GFX9-O0-NEXT: v_xor_b32_e64 v7, v7, v6 ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v8, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v3 -; GFX9-O0-NEXT: v_xor_b32_e64 v1, v1, v4 -; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr2_vgpr3 killed $exec -; GFX9-O0-NEXT: v_xor_b32_e64 v2, v2, v6 -; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 def $vgpr2_vgpr3 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v9, v15 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v16 +; GFX9-O0-NEXT: v_mov_b32_e32 v8, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 +; GFX9-O0-NEXT: v_xor_b32_e64 v9, v9, v3 +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 killed $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: v_xor_b32_e64 v4, v4, v6 +; GFX9-O0-NEXT: ; kill: def $vgpr4 killed $vgpr4 def $vgpr4_vgpr5 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v9, v1 +; GFX9-O0-NEXT: ; kill: def $vgpr2 killed $vgpr2 killed $vgpr1_vgpr2 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v11, v13 -; GFX9-O0-NEXT: v_mov_b32_e32 v5, v14 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v14 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v9, vcc, v9, v12 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v10, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v13, vcc, v11, v12, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v5, vcc, v5, v10, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v1, vcc, v1, v10, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v14, v5 +; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v10, v2 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr9 killed $vgpr9 def $vgpr9_vgpr10 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v10, v1 -; GFX9-O0-NEXT: v_mov_b32_e32 v1, v2 -; GFX9-O0-NEXT: ; kill: def $vgpr3 killed $vgpr3 killed $vgpr2_vgpr3 killed $exec +; GFX9-O0-NEXT: ; kill: def $vgpr13 killed $vgpr13 def $vgpr13_vgpr14 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v14, v1 +; GFX9-O0-NEXT: v_mov_b32_e32 v1, v4 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v7 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v8 ; GFX9-O0-NEXT: v_sub_co_u32_e32 v1, vcc, v1, v6 -; GFX9-O0-NEXT: v_subb_co_u32_e32 v3, vcc, v3, v4, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v4, vcc, v4, v3, vcc ; GFX9-O0-NEXT: v_subb_co_u32_e32 v11, vcc, v5, v6, vcc -; GFX9-O0-NEXT: v_subb_co_u32_e32 v2, vcc, v2, v4, vcc +; GFX9-O0-NEXT: v_subb_co_u32_e32 v3, vcc, v2, v3, vcc ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v12, v2 +; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v2, v4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 -; GFX9-O0-NEXT: ; kill: def $vgpr1 killed $vgpr1 def $vgpr1_vgpr2 killed $exec -; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill +; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec +; GFX9-O0-NEXT: v_mov_b32_e32 v12, v3 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v13 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v14 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:92 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:96 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v9 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v10 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:84 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:88 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:76 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:80 ; 4-byte Folded Spill +; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 +; GFX9-O0-NEXT: v_mov_b32_e32 v3, v1 +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:68 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:72 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v11 ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v12 ; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:60 ; 4-byte Folded Spill @@ -438,7 +445,8 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr8 killed $vgpr8 def $vgpr8_vgpr9 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v9, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[12:13], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[12:13], v[11:12], s[12:13] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v10, s[12:13] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v8 @@ -474,7 +482,8 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr11 killed $vgpr11 def $vgpr11_vgpr12 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v12, v5 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v12 -; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[6:7] +; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] +; GFX9-O0-NEXT: v_cmp_ne_u64_e64 s[8:9], v[13:14], s[8:9] ; GFX9-O0-NEXT: v_cndmask_b32_e64 v5, v5, v8, s[8:9] ; GFX9-O0-NEXT: v_mov_b32_e32 v7, v6 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v11 @@ -589,27 +598,27 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_readlane_b32 s5, v0, 5 ; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5] ; GFX9-O0-NEXT: ; %bb.2: ; %Flow -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:156 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:160 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:164 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:168 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:172 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:176 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:180 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(6) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_5 ; GFX9-O0-NEXT: .LBB0_3: ; %Flow2 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -624,22 +633,22 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:4 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:8 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:196 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:192 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:188 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_9 ; GFX9-O0-NEXT: .LBB0_4: ; %udiv-loop-exit -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:204 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:208 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:212 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:224 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:228 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 1 ; GFX9-O0-NEXT: s_waitcnt vmcnt(2) ; GFX9-O0-NEXT: v_lshlrev_b64 v[2:3], s4, v[0:1] @@ -679,27 +688,27 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_readlane_b32 s4, v8, 6 ; GFX9-O0-NEXT: v_readlane_b32 s5, v8, 7 ; GFX9-O0-NEXT: s_or_b64 exec, exec, s[4:5] -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:152 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:144 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:148 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:136 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:140 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:128 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:132 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:120 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:124 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:212 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:200 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:208 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:204 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:228 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:216 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:224 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:220 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_4 ; GFX9-O0-NEXT: .LBB0_6: ; %udiv-do-while ; GFX9-O0-NEXT: ; =>This Inner Loop Header: Depth=1 @@ -709,30 +718,30 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: v_readlane_b32 s6, v16, 8 ; GFX9-O0-NEXT: v_readlane_b32 s7, v16, 9 -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:232 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v7, off, s[0:3], s32 offset:236 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:240 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:244 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v23, off, s[0:3], s32 offset:248 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v24, off, s[0:3], s32 offset:252 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:256 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:260 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:264 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:268 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:272 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:276 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v27, off, s[0:3], s32 offset:280 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v28, off, s[0:3], s32 offset:284 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v25, off, s[0:3], s32 offset:288 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v26, off, s[0:3], s32 offset:292 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:52 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:56 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v21, off, s[0:3], s32 offset:60 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v22, off, s[0:3], s32 offset:64 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:304 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:308 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 63 ; GFX9-O0-NEXT: s_waitcnt vmcnt(16) ; GFX9-O0-NEXT: v_lshrrev_b64 v[29:30], s4, v[2:3] @@ -872,24 +881,24 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v2 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:156 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v1 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v0 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:160 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:164 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v15 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v14 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:168 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:172 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v18, v13 ; GFX9-O0-NEXT: v_mov_b32_e32 v17, v12 -; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v17, off, s[0:3], s32 offset:176 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:184 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v18, off, s[0:3], s32 offset:180 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[6:7], s[4:5] ; GFX9-O0-NEXT: v_writelane_b32 v16, s6, 4 ; GFX9-O0-NEXT: v_writelane_b32 v16, s7, 5 @@ -899,42 +908,42 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_andn2_b64 exec, exec, s[4:5] ; GFX9-O0-NEXT: s_cbranch_execnz .LBB0_6 ; GFX9-O0-NEXT: s_branch .LBB0_1 ; GFX9-O0-NEXT: .LBB0_7: ; %udiv-preheader -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:312 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v1, off, s[0:3], s32 offset:316 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v2, off, s[0:3], s32 offset:320 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v3, off, s[0:3], s32 offset:324 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:332 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:336 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:340 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] @@ -1018,12 +1027,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; kill: def $vgpr12 killed $vgpr12 def $vgpr12_vgpr13 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v13, v17 ; GFX9-O0-NEXT: s_mov_b64 s[8:9], s[6:7] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:300 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:304 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:308 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[4:5], s[6:7] ; GFX9-O0-NEXT: v_mov_b32_e32 v15, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v14, s8 @@ -1034,30 +1043,30 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 ; GFX9-O0-NEXT: buffer_store_dword v16, off, s[0:3], s32 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 exec, s[18:19] -; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v14, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:296 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v15, off, s[0:3], s32 offset:292 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v12, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:288 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v13, off, s[0:3], s32 offset:284 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v10, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:280 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v11, off, s[0:3], s32 offset:276 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:272 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v9, off, s[0:3], s32 offset:268 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:264 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:260 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:256 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:252 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:248 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:244 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v0, off, s[0:3], s32 offset:232 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:240 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:236 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_branch .LBB0_6 ; GFX9-O0-NEXT: .LBB0_8: ; %udiv-bb1 ; GFX9-O0-NEXT: s_or_saveexec_b64 s[18:19], -1 @@ -1099,14 +1108,14 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v2, v3 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v2 ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v1 -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:332 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v5, v9 ; GFX9-O0-NEXT: v_mov_b32_e32 v6, v10 -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:336 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:344 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:340 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b32 s4, 0x7f ; GFX9-O0-NEXT: v_sub_u32_e64 v3, s4, v4 ; GFX9-O0-NEXT: v_lshlrev_b64 v[5:6], v3, v[11:12] @@ -1152,12 +1161,12 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: ; implicit-def: $sgpr4 ; GFX9-O0-NEXT: ; kill: def $vgpr7 killed $vgpr7 def $vgpr7_vgpr8 killed $exec ; GFX9-O0-NEXT: v_mov_b32_e32 v8, v3 -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:328 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:324 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:312 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:320 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:316 ; 4-byte Folded Spill ; GFX9-O0-NEXT: v_mov_b32_e32 v4, v2 ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v10 ; GFX9-O0-NEXT: v_or_b32_e64 v3, v3, v4 @@ -1172,18 +1181,18 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v4, s9 ; GFX9-O0-NEXT: v_mov_b32_e32 v1, s6 ; GFX9-O0-NEXT: v_mov_b32_e32 v2, s7 -; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v7, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:152 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v8, off, s[0:3], s32 offset:148 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v5, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:144 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v6, off, s[0:3], s32 offset:140 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v3, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:136 ; 4-byte Folded Spill -; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v4, off, s[0:3], s32 offset:132 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v1, off, s[0:3], s32 offset:120 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) -; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:128 ; 4-byte Folded Spill +; GFX9-O0-NEXT: buffer_store_dword v2, off, s[0:3], s32 offset:124 ; 4-byte Folded Spill ; GFX9-O0-NEXT: s_mov_b64 s[6:7], exec ; GFX9-O0-NEXT: s_and_b64 s[4:5], s[6:7], s[4:5] ; GFX9-O0-NEXT: s_xor_b64 s[6:7], s[4:5], s[6:7] @@ -1203,18 +1212,18 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:112 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v9, off, s[0:3], s32 offset:100 ; 4-byte Folded Reload ; GFX9-O0-NEXT: buffer_load_dword v10, off, s[0:3], s32 offset:104 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:200 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v13, off, s[0:3], s32 offset:92 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v14, off, s[0:3], s32 offset:96 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v15, off, s[0:3], s32 offset:84 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:88 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v19, off, s[0:3], s32 offset:68 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v20, off, s[0:3], s32 offset:72 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v11, off, s[0:3], s32 offset:192 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v12, off, s[0:3], s32 offset:196 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v5, off, s[0:3], s32 offset:184 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v6, off, s[0:3], s32 offset:188 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v17, off, s[0:3], s32 offset:76 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v18, off, s[0:3], s32 offset:80 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b32 s4, 32 ; GFX9-O0-NEXT: s_waitcnt vmcnt(2) ; GFX9-O0-NEXT: v_lshrrev_b64 v[0:1], s4, v[5:6] @@ -1486,11 +1495,11 @@ define i128 @v_srem_i128_vv(i128 %lhs, i128 %rhs) { ; GFX9-O0-NEXT: v_mov_b32_e32 v3, v5 ; GFX9-O0-NEXT: ; kill: killed $vgpr4 ; GFX9-O0-NEXT: s_xor_saveexec_b64 s[4:5], -1 -; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v0, off, s[0:3], s32 offset:344 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_nop 0 -; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload -; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:360 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v4, off, s[0:3], s32 offset:348 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v8, off, s[0:3], s32 offset:352 ; 4-byte Folded Reload +; GFX9-O0-NEXT: buffer_load_dword v16, off, s[0:3], s32 offset:356 ; 4-byte Folded Reload ; GFX9-O0-NEXT: s_mov_b64 exec, s[4:5] ; GFX9-O0-NEXT: s_waitcnt vmcnt(0) ; GFX9-O0-NEXT: s_setpc_b64 s[30:31] diff --git a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll index 6629d3440549..25106b456d2f 100644 --- a/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll +++ b/llvm/test/CodeGen/LoongArch/lasx/ir-instruction/insertelement.ll @@ -123,10 +123,9 @@ define void @insert_32xi8_idx(ptr %src, ptr %dst, i8 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 0 -; CHECK-NEXT: st.b $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 0 +; CHECK-NEXT: st.b $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -150,10 +149,9 @@ define void @insert_16xi16_idx(ptr %src, ptr %dst, i16 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 1 -; CHECK-NEXT: st.h $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 1 +; CHECK-NEXT: st.h $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -177,10 +175,9 @@ define void @insert_8xi32_idx(ptr %src, ptr %dst, i32 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 2 -; CHECK-NEXT: st.w $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 2 +; CHECK-NEXT: st.w $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -204,10 +201,9 @@ define void @insert_4xi64_idx(ptr %src, ptr %dst, i64 %in, i32 %idx) nounwind { ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr0, $a0, 0 ; CHECK-NEXT: xvst $xr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 4, 3 -; CHECK-NEXT: st.d $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 4, 3 +; CHECK-NEXT: st.d $a2, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -231,10 +227,9 @@ define void @insert_8xfloat_idx(ptr %src, ptr %dst, float %in, i32 %idx) nounwin ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr1, $a0, 0 ; CHECK-NEXT: xvst $xr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 4, 2 -; CHECK-NEXT: fst.s $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 4, 2 +; CHECK-NEXT: fst.s $fa0, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 @@ -258,10 +253,9 @@ define void @insert_4xdouble_idx(ptr %src, ptr %dst, double %in, i32 %idx) nounw ; CHECK-NEXT: bstrins.d $sp, $zero, 4, 0 ; CHECK-NEXT: xvld $xr1, $a0, 0 ; CHECK-NEXT: xvst $xr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 4, 3 -; CHECK-NEXT: fst.d $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 4, 3 +; CHECK-NEXT: fst.d $fa0, $a0, 0 ; CHECK-NEXT: xvld $xr0, $sp, 0 ; CHECK-NEXT: xvst $xr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $fp, -64 diff --git a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll index 19171b7d8ed7..7f232073ae12 100644 --- a/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll +++ b/llvm/test/CodeGen/LoongArch/lsx/ir-instruction/insertelement.ll @@ -87,10 +87,9 @@ define void @insert_16xi8_idx(ptr %src, ptr %dst, i8 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 0 -; CHECK-NEXT: st.b $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 0 +; CHECK-NEXT: st.b $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -107,10 +106,9 @@ define void @insert_8xi16_idx(ptr %src, ptr %dst, i16 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 1 -; CHECK-NEXT: st.h $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 1 +; CHECK-NEXT: st.h $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -127,10 +125,9 @@ define void @insert_4xi32_idx(ptr %src, ptr %dst, i32 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 2 -; CHECK-NEXT: st.w $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 2 +; CHECK-NEXT: st.w $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -147,10 +144,9 @@ define void @insert_2xi64_idx(ptr %src, ptr %dst, i64 %ins, i32 %idx) nounwind { ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr0, $a0, 0 ; CHECK-NEXT: vst $vr0, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a3, 31, 0 -; CHECK-NEXT: addi.d $a3, $sp, 0 -; CHECK-NEXT: bstrins.d $a3, $a0, 3, 3 -; CHECK-NEXT: st.d $a2, $a3, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a3, 3, 3 +; CHECK-NEXT: st.d $a2, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -167,10 +163,9 @@ define void @insert_4xfloat_idx(ptr %src, ptr %dst, float %ins, i32 %idx) nounwi ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr1, $a0, 0 ; CHECK-NEXT: vst $vr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 3, 2 -; CHECK-NEXT: fst.s $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 3, 2 +; CHECK-NEXT: fst.s $fa0, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 @@ -187,10 +182,9 @@ define void @insert_2xdouble_idx(ptr %src, ptr %dst, double %ins, i32 %idx) noun ; CHECK-NEXT: addi.d $sp, $sp, -16 ; CHECK-NEXT: vld $vr1, $a0, 0 ; CHECK-NEXT: vst $vr1, $sp, 0 -; CHECK-NEXT: bstrpick.d $a0, $a2, 31, 0 -; CHECK-NEXT: addi.d $a2, $sp, 0 -; CHECK-NEXT: bstrins.d $a2, $a0, 3, 3 -; CHECK-NEXT: fst.d $fa0, $a2, 0 +; CHECK-NEXT: addi.d $a0, $sp, 0 +; CHECK-NEXT: bstrins.d $a0, $a2, 3, 3 +; CHECK-NEXT: fst.d $fa0, $a0, 0 ; CHECK-NEXT: vld $vr0, $sp, 0 ; CHECK-NEXT: vst $vr0, $a1, 0 ; CHECK-NEXT: addi.d $sp, $sp, 16 diff --git a/llvm/test/CodeGen/RISCV/alu64.ll b/llvm/test/CodeGen/RISCV/alu64.ll index d2ee80e6aa95..f032756e007b 100644 --- a/llvm/test/CodeGen/RISCV/alu64.ll +++ b/llvm/test/CodeGen/RISCV/alu64.ll @@ -57,8 +57,8 @@ define i64 @sltiu(i64 %a) nounwind { ; ; RV32I-LABEL: sltiu: ; RV32I: # %bb.0: -; RV32I-NEXT: seqz a1, a1 ; RV32I-NEXT: sltiu a0, a0, 3 +; RV32I-NEXT: seqz a1, a1 ; RV32I-NEXT: and a0, a1, a0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: ret diff --git a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll index f96e1bad2e38..a5a2ae79966c 100644 --- a/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll +++ b/llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll @@ -372,10 +372,10 @@ define i32 @atomicrmw_uinc_wrap_i32(ptr %ptr, i32 %val) { ; RV32IA-NEXT: # =>This Loop Header: Depth=1 ; RV32IA-NEXT: # Child Loop BB2_3 Depth 2 ; RV32IA-NEXT: mv a3, a2 -; RV32IA-NEXT: addi a4, a2, 1 -; RV32IA-NEXT: sltu a2, a2, a1 -; RV32IA-NEXT: neg a2, a2 -; RV32IA-NEXT: and a4, a2, a4 +; RV32IA-NEXT: addi a2, a2, 1 +; RV32IA-NEXT: sltu a4, a3, a1 +; RV32IA-NEXT: neg a4, a4 +; RV32IA-NEXT: and a4, a4, a2 ; RV32IA-NEXT: .LBB2_3: # %atomicrmw.start ; RV32IA-NEXT: # Parent Loop BB2_1 Depth=1 ; RV32IA-NEXT: # => This Inner Loop Header: Depth=2 @@ -607,10 +607,10 @@ define i64 @atomicrmw_uinc_wrap_i64(ptr %ptr, i64 %val) { ; RV64IA-NEXT: # =>This Loop Header: Depth=1 ; RV64IA-NEXT: # Child Loop BB3_3 Depth 2 ; RV64IA-NEXT: mv a3, a2 -; RV64IA-NEXT: addi a4, a2, 1 -; RV64IA-NEXT: sltu a2, a2, a1 -; RV64IA-NEXT: neg a2, a2 -; RV64IA-NEXT: and a4, a2, a4 +; RV64IA-NEXT: addi a2, a2, 1 +; RV64IA-NEXT: sltu a4, a3, a1 +; RV64IA-NEXT: neg a4, a4 +; RV64IA-NEXT: and a4, a4, a2 ; RV64IA-NEXT: .LBB3_3: # %atomicrmw.start ; RV64IA-NEXT: # Parent Loop BB3_1 Depth=1 ; RV64IA-NEXT: # => This Inner Loop Header: Depth=2 diff --git a/llvm/test/CodeGen/RISCV/bfloat-convert.ll b/llvm/test/CodeGen/RISCV/bfloat-convert.ll index 9e2b0b5c3cbb..770dcccee882 100644 --- a/llvm/test/CodeGen/RISCV/bfloat-convert.ll +++ b/llvm/test/CodeGen/RISCV/bfloat-convert.ll @@ -456,92 +456,80 @@ define i64 @fcvt_l_bf16(bfloat %a) nounwind { define i64 @fcvt_l_bf16_sat(bfloat %a) nounwind { ; RV32IZFBFMIN-LABEL: fcvt_l_bf16_sat: ; RV32IZFBFMIN: # %bb.0: # %start -; RV32IZFBFMIN-NEXT: addi sp, sp, -32 -; RV32IZFBFMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill -; RV32IZFBFMIN-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) +; RV32IZFBFMIN-NEXT: addi sp, sp, -16 +; RV32IZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFBFMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0 -; RV32IZFBFMIN-NEXT: flt.s s0, fa5, fs0 -; RV32IZFBFMIN-NEXT: neg s1, s0 ; RV32IZFBFMIN-NEXT: lui a0, 913408 ; RV32IZFBFMIN-NEXT: fmv.w.x fa5, a0 -; RV32IZFBFMIN-NEXT: fle.s s2, fa5, fs0 -; RV32IZFBFMIN-NEXT: neg s3, s2 +; RV32IZFBFMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IZFBFMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFBFMIN-NEXT: call __fixsfdi -; RV32IZFBFMIN-NEXT: and a0, s3, a0 -; RV32IZFBFMIN-NEXT: or a0, s1, a0 -; RV32IZFBFMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFBFMIN-NEXT: neg a2, a2 ; RV32IZFBFMIN-NEXT: lui a4, 524288 -; RV32IZFBFMIN-NEXT: lui a3, 524288 -; RV32IZFBFMIN-NEXT: beqz s2, .LBB10_2 +; RV32IZFBFMIN-NEXT: lui a2, 524288 +; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_2 ; RV32IZFBFMIN-NEXT: # %bb.1: # %start -; RV32IZFBFMIN-NEXT: mv a3, a1 +; RV32IZFBFMIN-NEXT: mv a2, a1 ; RV32IZFBFMIN-NEXT: .LBB10_2: # %start -; RV32IZFBFMIN-NEXT: and a0, a2, a0 -; RV32IZFBFMIN-NEXT: beqz s0, .LBB10_4 +; RV32IZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IZFBFMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFBFMIN-NEXT: beqz a3, .LBB10_4 ; RV32IZFBFMIN-NEXT: # %bb.3: -; RV32IZFBFMIN-NEXT: addi a3, a4, -1 +; RV32IZFBFMIN-NEXT: addi a2, a4, -1 ; RV32IZFBFMIN-NEXT: .LBB10_4: # %start -; RV32IZFBFMIN-NEXT: and a1, a2, a3 -; RV32IZFBFMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload -; RV32IZFBFMIN-NEXT: addi sp, sp, 32 +; RV32IZFBFMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFBFMIN-NEXT: neg a4, a1 +; RV32IZFBFMIN-NEXT: and a1, a4, a2 +; RV32IZFBFMIN-NEXT: neg a2, a3 +; RV32IZFBFMIN-NEXT: neg a3, s0 +; RV32IZFBFMIN-NEXT: and a0, a3, a0 +; RV32IZFBFMIN-NEXT: or a0, a2, a0 +; RV32IZFBFMIN-NEXT: and a0, a4, a0 +; RV32IZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFBFMIN-NEXT: addi sp, sp, 16 ; RV32IZFBFMIN-NEXT: ret ; ; R32IDZFBFMIN-LABEL: fcvt_l_bf16_sat: ; R32IDZFBFMIN: # %bb.0: # %start -; R32IDZFBFMIN-NEXT: addi sp, sp, -32 -; R32IDZFBFMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; R32IDZFBFMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: addi sp, sp, -16 +; R32IDZFBFMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; R32IDZFBFMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; R32IDZFBFMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; R32IDZFBFMIN-NEXT: lui a0, %hi(.LCPI10_0) -; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; R32IDZFBFMIN-NEXT: fcvt.s.bf16 fs0, fa0 -; R32IDZFBFMIN-NEXT: flt.s s0, fa5, fs0 -; R32IDZFBFMIN-NEXT: neg s1, s0 ; R32IDZFBFMIN-NEXT: lui a0, 913408 ; R32IDZFBFMIN-NEXT: fmv.w.x fa5, a0 -; R32IDZFBFMIN-NEXT: fle.s s2, fa5, fs0 -; R32IDZFBFMIN-NEXT: neg s3, s2 +; R32IDZFBFMIN-NEXT: fle.s s0, fa5, fs0 ; R32IDZFBFMIN-NEXT: fmv.s fa0, fs0 ; R32IDZFBFMIN-NEXT: call __fixsfdi -; R32IDZFBFMIN-NEXT: and a0, s3, a0 -; R32IDZFBFMIN-NEXT: or a0, s1, a0 -; R32IDZFBFMIN-NEXT: feq.s a2, fs0, fs0 -; R32IDZFBFMIN-NEXT: neg a2, a2 ; R32IDZFBFMIN-NEXT: lui a4, 524288 -; R32IDZFBFMIN-NEXT: lui a3, 524288 -; R32IDZFBFMIN-NEXT: beqz s2, .LBB10_2 +; R32IDZFBFMIN-NEXT: lui a2, 524288 +; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_2 ; R32IDZFBFMIN-NEXT: # %bb.1: # %start -; R32IDZFBFMIN-NEXT: mv a3, a1 +; R32IDZFBFMIN-NEXT: mv a2, a1 ; R32IDZFBFMIN-NEXT: .LBB10_2: # %start -; R32IDZFBFMIN-NEXT: and a0, a2, a0 -; R32IDZFBFMIN-NEXT: beqz s0, .LBB10_4 +; R32IDZFBFMIN-NEXT: lui a1, %hi(.LCPI10_0) +; R32IDZFBFMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; R32IDZFBFMIN-NEXT: flt.s a3, fa5, fs0 +; R32IDZFBFMIN-NEXT: beqz a3, .LBB10_4 ; R32IDZFBFMIN-NEXT: # %bb.3: -; R32IDZFBFMIN-NEXT: addi a3, a4, -1 +; R32IDZFBFMIN-NEXT: addi a2, a4, -1 ; R32IDZFBFMIN-NEXT: .LBB10_4: # %start -; R32IDZFBFMIN-NEXT: and a1, a2, a3 -; R32IDZFBFMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; R32IDZFBFMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: feq.s a1, fs0, fs0 +; R32IDZFBFMIN-NEXT: neg a4, a1 +; R32IDZFBFMIN-NEXT: and a1, a4, a2 +; R32IDZFBFMIN-NEXT: neg a2, a3 +; R32IDZFBFMIN-NEXT: neg a3, s0 +; R32IDZFBFMIN-NEXT: and a0, a3, a0 +; R32IDZFBFMIN-NEXT: or a0, a2, a0 +; R32IDZFBFMIN-NEXT: and a0, a4, a0 +; R32IDZFBFMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; R32IDZFBFMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; R32IDZFBFMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; R32IDZFBFMIN-NEXT: addi sp, sp, 32 +; R32IDZFBFMIN-NEXT: addi sp, sp, 16 ; R32IDZFBFMIN-NEXT: ret ; ; RV32ID-LABEL: fcvt_l_bf16_sat: diff --git a/llvm/test/CodeGen/RISCV/double-convert.ll b/llvm/test/CodeGen/RISCV/double-convert.ll index c147d6ec6d9b..6024a29da33d 100644 --- a/llvm/test/CodeGen/RISCV/double-convert.ll +++ b/llvm/test/CodeGen/RISCV/double-convert.ll @@ -692,28 +692,27 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB12_2 +; RV32IFD-NEXT: beqz s0, .LBB12_2 ; RV32IFD-NEXT: # %bb.1: # %start ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB12_2: # %start ; RV32IFD-NEXT: lui a1, %hi(.LCPI12_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI12_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB12_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB12_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB12_4: # %start ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -790,33 +789,32 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s4, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s5, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s6, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a1 ; RV32I-NEXT: mv s1, a0 +; RV32I-NEXT: lui a3, 278016 +; RV32I-NEXT: addi a3, a3, -1 +; RV32I-NEXT: li a2, -1 +; RV32I-NEXT: call __gtdf2 +; RV32I-NEXT: mv s2, a0 ; RV32I-NEXT: lui a3, 802304 +; RV32I-NEXT: mv a0, s1 +; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: li a2, 0 ; RV32I-NEXT: call __gedf2 -; RV32I-NEXT: mv s2, a0 +; RV32I-NEXT: mv s3, a0 ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 ; RV32I-NEXT: call __fixdfdi -; RV32I-NEXT: mv s3, a0 -; RV32I-NEXT: mv s4, a1 -; RV32I-NEXT: lui s6, 524288 -; RV32I-NEXT: bgez s2, .LBB12_2 +; RV32I-NEXT: mv s4, a0 +; RV32I-NEXT: mv s5, a1 +; RV32I-NEXT: lui a0, 524288 +; RV32I-NEXT: bgez s3, .LBB12_2 ; RV32I-NEXT: # %bb.1: # %start -; RV32I-NEXT: lui s4, 524288 +; RV32I-NEXT: lui s5, 524288 ; RV32I-NEXT: .LBB12_2: # %start -; RV32I-NEXT: lui a3, 278016 -; RV32I-NEXT: addi a3, a3, -1 -; RV32I-NEXT: li a2, -1 -; RV32I-NEXT: mv a0, s1 -; RV32I-NEXT: mv a1, s0 -; RV32I-NEXT: call __gtdf2 -; RV32I-NEXT: mv s5, a0 -; RV32I-NEXT: blez a0, .LBB12_4 +; RV32I-NEXT: blez s2, .LBB12_4 ; RV32I-NEXT: # %bb.3: # %start -; RV32I-NEXT: addi s4, s6, -1 +; RV32I-NEXT: addi s5, a0, -1 ; RV32I-NEXT: .LBB12_4: # %start ; RV32I-NEXT: mv a0, s1 ; RV32I-NEXT: mv a1, s0 @@ -825,11 +823,11 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: call __unorddf2 ; RV32I-NEXT: snez a0, a0 ; RV32I-NEXT: addi a0, a0, -1 -; RV32I-NEXT: and a1, a0, s4 -; RV32I-NEXT: slti a2, s2, 0 +; RV32I-NEXT: and a1, a0, s5 +; RV32I-NEXT: slti a2, s3, 0 ; RV32I-NEXT: addi a2, a2, -1 -; RV32I-NEXT: and a2, a2, s3 -; RV32I-NEXT: sgtz a3, s5 +; RV32I-NEXT: and a2, a2, s4 +; RV32I-NEXT: sgtz a3, s2 ; RV32I-NEXT: neg a3, a3 ; RV32I-NEXT: or a2, a3, a2 ; RV32I-NEXT: and a0, a0, a2 @@ -840,7 +838,6 @@ define i64 @fcvt_l_d_sat(double %a) nounwind { ; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s4, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s5, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s6, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; @@ -949,22 +946,23 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IFD-NEXT: addi sp, sp, -16 ; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IFD-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IFD-NEXT: lui a0, %hi(.LCPI14_0) -; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a0) -; RV32IFD-NEXT: flt.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s0, a0 +; RV32IFD-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill +; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fcvt.d.w fa5, zero ; RV32IFD-NEXT: fle.d a0, fa5, fa0 -; RV32IFD-NEXT: neg s1, a0 +; RV32IFD-NEXT: neg s0, a0 ; RV32IFD-NEXT: call __fixunsdfdi -; RV32IFD-NEXT: and a0, s1, a0 -; RV32IFD-NEXT: or a0, s0, a0 -; RV32IFD-NEXT: and a1, s1, a1 -; RV32IFD-NEXT: or a1, s0, a1 +; RV32IFD-NEXT: lui a2, %hi(.LCPI14_0) +; RV32IFD-NEXT: fld fa5, %lo(.LCPI14_0)(a2) +; RV32IFD-NEXT: and a0, s0, a0 +; RV32IFD-NEXT: flt.d a2, fa5, fs0 +; RV32IFD-NEXT: neg a2, a2 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a1, s0, a1 +; RV32IFD-NEXT: or a1, a2, a1 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IFD-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload ; RV32IFD-NEXT: addi sp, sp, 16 ; RV32IFD-NEXT: ret ; @@ -983,27 +981,24 @@ define i64 @fcvt_lu_d_sat(double %a) nounwind { ; RV32IZFINXZDINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINXZDINX-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32IZFINXZDINX-NEXT: mv s1, a1 -; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero ; RV32IZFINXZDINX-NEXT: mv s0, a0 -; RV32IZFINXZDINX-NEXT: fle.d a0, a2, s0 -; RV32IZFINXZDINX-NEXT: neg s2, a0 -; RV32IZFINXZDINX-NEXT: mv a0, s0 ; RV32IZFINXZDINX-NEXT: call __fixunsdfdi -; RV32IZFINXZDINX-NEXT: lui a2, %hi(.LCPI14_0) -; RV32IZFINXZDINX-NEXT: lw a3, %lo(.LCPI14_0+4)(a2) -; RV32IZFINXZDINX-NEXT: lw a2, %lo(.LCPI14_0)(a2) -; RV32IZFINXZDINX-NEXT: and a0, s2, a0 -; RV32IZFINXZDINX-NEXT: flt.d a2, a2, s0 +; RV32IZFINXZDINX-NEXT: fcvt.d.w a2, zero +; RV32IZFINXZDINX-NEXT: lui a4, %hi(.LCPI14_0) +; RV32IZFINXZDINX-NEXT: lw a5, %lo(.LCPI14_0+4)(a4) +; RV32IZFINXZDINX-NEXT: lw a4, %lo(.LCPI14_0)(a4) +; RV32IZFINXZDINX-NEXT: fle.d a2, a2, s0 ; RV32IZFINXZDINX-NEXT: neg a2, a2 -; RV32IZFINXZDINX-NEXT: or a0, a2, a0 -; RV32IZFINXZDINX-NEXT: and a1, s2, a1 -; RV32IZFINXZDINX-NEXT: or a1, a2, a1 +; RV32IZFINXZDINX-NEXT: and a0, a2, a0 +; RV32IZFINXZDINX-NEXT: flt.d a3, a4, s0 +; RV32IZFINXZDINX-NEXT: neg a3, a3 +; RV32IZFINXZDINX-NEXT: or a0, a3, a0 +; RV32IZFINXZDINX-NEXT: and a1, a2, a1 +; RV32IZFINXZDINX-NEXT: or a1, a3, a1 ; RV32IZFINXZDINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFINXZDINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZFINXZDINX-NEXT: addi sp, sp, 16 ; RV32IZFINXZDINX-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll index f1c56b320b76..927eee2e9e54 100644 --- a/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/double-round-conv-sat.ll @@ -53,28 +53,27 @@ define i64 @test_floor_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB1_2 +; RV32IFD-NEXT: beqz s0, .LBB1_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB1_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI1_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI1_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB1_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB1_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB1_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -299,28 +298,27 @@ define i64 @test_ceil_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB5_2 +; RV32IFD-NEXT: beqz s0, .LBB5_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB5_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI5_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI5_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB5_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB5_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB5_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -545,28 +543,27 @@ define i64 @test_trunc_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB9_2 +; RV32IFD-NEXT: beqz s0, .LBB9_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB9_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI9_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI9_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB9_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB9_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB9_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -791,28 +788,27 @@ define i64 @test_round_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB13_2 +; RV32IFD-NEXT: beqz s0, .LBB13_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB13_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI13_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI13_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB13_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB13_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB13_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -1037,28 +1033,27 @@ define i64 @test_roundeven_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB17_2 +; RV32IFD-NEXT: beqz s0, .LBB17_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB17_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI17_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI17_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB17_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB17_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB17_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload @@ -1283,28 +1278,27 @@ define i64 @test_rint_si64(double %x) nounwind { ; RV32IFD-NEXT: fmv.d fs0, fa0 ; RV32IFD-NEXT: fle.d s0, fa5, fa0 ; RV32IFD-NEXT: call __fixdfdi -; RV32IFD-NEXT: lui a3, 524288 -; RV32IFD-NEXT: li a4, 1 +; RV32IFD-NEXT: lui a4, 524288 ; RV32IFD-NEXT: lui a2, 524288 -; RV32IFD-NEXT: bne s0, a4, .LBB21_2 +; RV32IFD-NEXT: beqz s0, .LBB21_2 ; RV32IFD-NEXT: # %bb.1: ; RV32IFD-NEXT: mv a2, a1 ; RV32IFD-NEXT: .LBB21_2: ; RV32IFD-NEXT: lui a1, %hi(.LCPI21_1) ; RV32IFD-NEXT: fld fa5, %lo(.LCPI21_1)(a1) -; RV32IFD-NEXT: flt.d a4, fa5, fs0 -; RV32IFD-NEXT: beqz a4, .LBB21_4 +; RV32IFD-NEXT: flt.d a3, fa5, fs0 +; RV32IFD-NEXT: beqz a3, .LBB21_4 ; RV32IFD-NEXT: # %bb.3: -; RV32IFD-NEXT: addi a2, a3, -1 +; RV32IFD-NEXT: addi a2, a4, -1 ; RV32IFD-NEXT: .LBB21_4: ; RV32IFD-NEXT: feq.d a1, fs0, fs0 -; RV32IFD-NEXT: neg a3, a1 -; RV32IFD-NEXT: and a1, a3, a2 -; RV32IFD-NEXT: neg a2, a4 -; RV32IFD-NEXT: neg a4, s0 -; RV32IFD-NEXT: and a0, a4, a0 -; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: neg a4, a1 +; RV32IFD-NEXT: and a1, a4, a2 +; RV32IFD-NEXT: neg a2, a3 +; RV32IFD-NEXT: neg a3, s0 ; RV32IFD-NEXT: and a0, a3, a0 +; RV32IFD-NEXT: or a0, a2, a0 +; RV32IFD-NEXT: and a0, a4, a0 ; RV32IFD-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IFD-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/float-convert.ll b/llvm/test/CodeGen/RISCV/float-convert.ll index 653b64ec7304..7eabd3f5f227 100644 --- a/llvm/test/CodeGen/RISCV/float-convert.ll +++ b/llvm/test/CodeGen/RISCV/float-convert.ll @@ -275,26 +275,24 @@ define i32 @fcvt_wu_s_sat(float %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a1, 325632 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi -; RV32I-NEXT: and a0, s2, a0 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: and s1, s1, a0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg a0, a0 +; RV32I-NEXT: or a0, a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; @@ -618,38 +616,36 @@ define i64 @fcvt_l_s_sat(float %a) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fa0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI12_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB12_2 ; RV32IF-NEXT: # %bb.1: # %start -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB12_2: # %start -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI12_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI12_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB12_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB12_4: # %start -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -867,22 +863,23 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: lui a0, %hi(.LCPI14_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a0) -; RV32IF-NEXT: flt.s a0, fa5, fa0 -; RV32IF-NEXT: neg s0, a0 +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: fmv.w.x fa5, zero ; RV32IF-NEXT: fle.s a0, fa5, fa0 -; RV32IF-NEXT: neg s1, a0 +; RV32IF-NEXT: neg s0, a0 ; RV32IF-NEXT: call __fixunssfdi -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: or a0, s0, a0 -; RV32IF-NEXT: and a1, s1, a1 -; RV32IF-NEXT: or a1, s0, a1 +; RV32IF-NEXT: lui a2, %hi(.LCPI14_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI14_0)(a2) +; RV32IF-NEXT: and a0, s0, a0 +; RV32IF-NEXT: flt.s a2, fa5, fs0 +; RV32IF-NEXT: neg a2, a2 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a1, s0, a1 +; RV32IF-NEXT: or a1, a2, a1 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -901,17 +898,19 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; RV32IZFINX-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IZFINX-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFINX-NEXT: lui a1, %hi(.LCPI14_0) -; RV32IZFINX-NEXT: lw a1, %lo(.LCPI14_0)(a1) -; RV32IZFINX-NEXT: flt.s a1, a1, a0 -; RV32IZFINX-NEXT: neg s0, a1 -; RV32IZFINX-NEXT: fle.s a1, zero, a0 -; RV32IZFINX-NEXT: neg s1, a1 +; RV32IZFINX-NEXT: mv s0, a0 +; RV32IZFINX-NEXT: fle.s a0, zero, a0 +; RV32IZFINX-NEXT: neg s1, a0 +; RV32IZFINX-NEXT: mv a0, s0 ; RV32IZFINX-NEXT: call __fixunssfdi +; RV32IZFINX-NEXT: lui a2, %hi(.LCPI14_0) +; RV32IZFINX-NEXT: lw a2, %lo(.LCPI14_0)(a2) ; RV32IZFINX-NEXT: and a0, s1, a0 -; RV32IZFINX-NEXT: or a0, s0, a0 +; RV32IZFINX-NEXT: flt.s a2, a2, s0 +; RV32IZFINX-NEXT: neg a2, a2 +; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: and a1, s1, a1 -; RV32IZFINX-NEXT: or a1, s0, a1 +; RV32IZFINX-NEXT: or a1, a2, a1 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -929,33 +928,36 @@ define i64 @fcvt_lu_s_sat(float %a) nounwind { ; ; RV32I-LABEL: fcvt_lu_s_sat: ; RV32I: # %bb.0: # %start -; RV32I-NEXT: addi sp, sp, -16 -; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill +; RV32I-NEXT: addi sp, sp, -32 +; RV32I-NEXT: sw ra, 28(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s0, 24(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s1, 20(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s2, 16(sp) # 4-byte Folded Spill +; RV32I-NEXT: sw s3, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a1, 391168 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 ; RV32I-NEXT: addi s2, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfdi -; RV32I-NEXT: and a0, s2, a0 -; RV32I-NEXT: or a0, s1, a0 -; RV32I-NEXT: and a1, s2, a1 -; RV32I-NEXT: or a1, s1, a1 -; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload -; RV32I-NEXT: addi sp, sp, 16 +; RV32I-NEXT: mv s1, a1 +; RV32I-NEXT: and s3, s2, a0 +; RV32I-NEXT: lui a1, 391168 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg a1, a0 +; RV32I-NEXT: or a0, a1, s3 +; RV32I-NEXT: and a2, s2, s1 +; RV32I-NEXT: or a1, a1, a2 +; RV32I-NEXT: lw ra, 28(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s0, 24(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s1, 20(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s2, 16(sp) # 4-byte Folded Reload +; RV32I-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32I-NEXT: addi sp, sp, 32 ; RV32I-NEXT: ret ; ; RV64I-LABEL: fcvt_lu_s_sat: @@ -2089,26 +2091,24 @@ define zeroext i32 @fcvt_wu_s_sat_zext(float %a) nounwind { ; RV32I-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32I-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32I-NEXT: sw s2, 0(sp) # 4-byte Folded Spill ; RV32I-NEXT: mv s0, a0 -; RV32I-NEXT: lui a1, 325632 -; RV32I-NEXT: addi a1, a1, -1 -; RV32I-NEXT: call __gtsf2 -; RV32I-NEXT: sgtz a0, a0 -; RV32I-NEXT: neg s1, a0 -; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: li a1, 0 ; RV32I-NEXT: call __gesf2 ; RV32I-NEXT: slti a0, a0, 0 -; RV32I-NEXT: addi s2, a0, -1 +; RV32I-NEXT: addi s1, a0, -1 ; RV32I-NEXT: mv a0, s0 ; RV32I-NEXT: call __fixunssfsi -; RV32I-NEXT: and a0, s2, a0 -; RV32I-NEXT: or a0, s1, a0 +; RV32I-NEXT: and s1, s1, a0 +; RV32I-NEXT: lui a1, 325632 +; RV32I-NEXT: addi a1, a1, -1 +; RV32I-NEXT: mv a0, s0 +; RV32I-NEXT: call __gtsf2 +; RV32I-NEXT: sgtz a0, a0 +; RV32I-NEXT: neg a0, a0 +; RV32I-NEXT: or a0, a0, s1 ; RV32I-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32I-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32I-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32I-NEXT: addi sp, sp, 16 ; RV32I-NEXT: ret ; diff --git a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll index 4f747c278da0..5e99c7eb9056 100644 --- a/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/float-round-conv-sat.ll @@ -37,8 +37,7 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -53,33 +52,32 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB1_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB1_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI1_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI1_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB1_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB1_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -117,23 +115,23 @@ define i64 @test_floor_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB1_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB1_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB1_6 +; RV32IZFINX-NEXT: beqz a4, .LBB1_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB1_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -299,8 +297,7 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -315,33 +312,32 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI5_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB5_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB5_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI5_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI5_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB5_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB5_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -379,23 +375,23 @@ define i64 @test_ceil_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB5_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB5_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB5_6 +; RV32IZFINX-NEXT: beqz a4, .LBB5_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB5_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -561,8 +557,7 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -577,33 +572,32 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI9_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB9_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB9_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI9_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI9_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB9_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB9_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -641,23 +635,23 @@ define i64 @test_trunc_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB9_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB9_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB9_6 +; RV32IZFINX-NEXT: beqz a4, .LBB9_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB9_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -823,8 +817,7 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -839,33 +832,32 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI13_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB13_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB13_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI13_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI13_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB13_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB13_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -903,23 +895,23 @@ define i64 @test_round_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB13_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB13_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB13_6 +; RV32IZFINX-NEXT: beqz a4, .LBB13_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB13_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1085,8 +1077,7 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -1101,33 +1092,32 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI17_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB17_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB17_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI17_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI17_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB17_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB17_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1165,23 +1155,23 @@ define i64 @test_roundeven_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB17_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB17_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB17_6 +; RV32IZFINX-NEXT: beqz a4, .LBB17_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB17_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload @@ -1347,8 +1337,7 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IF-NEXT: addi sp, sp, -16 ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IF-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IF-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IF-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IF-NEXT: fmv.s fs0, fa0 ; RV32IF-NEXT: lui a0, 307200 ; RV32IF-NEXT: fmv.w.x fa5, a0 @@ -1363,33 +1352,32 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IF-NEXT: lui a0, 913408 ; RV32IF-NEXT: fmv.w.x fa5, a0 ; RV32IF-NEXT: fle.s s0, fa5, fs0 -; RV32IF-NEXT: neg s1, s0 ; RV32IF-NEXT: fmv.s fa0, fs0 ; RV32IF-NEXT: call __fixsfdi -; RV32IF-NEXT: lui a2, %hi(.LCPI21_0) -; RV32IF-NEXT: flw fa5, %lo(.LCPI21_0)(a2) -; RV32IF-NEXT: and a0, s1, a0 -; RV32IF-NEXT: flt.s a3, fa5, fs0 -; RV32IF-NEXT: neg a2, a3 -; RV32IF-NEXT: or a0, a2, a0 -; RV32IF-NEXT: feq.s a2, fs0, fs0 -; RV32IF-NEXT: neg a2, a2 -; RV32IF-NEXT: lui a5, 524288 ; RV32IF-NEXT: lui a4, 524288 +; RV32IF-NEXT: lui a2, 524288 ; RV32IF-NEXT: beqz s0, .LBB21_4 ; RV32IF-NEXT: # %bb.3: -; RV32IF-NEXT: mv a4, a1 +; RV32IF-NEXT: mv a2, a1 ; RV32IF-NEXT: .LBB21_4: -; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: lui a1, %hi(.LCPI21_0) +; RV32IF-NEXT: flw fa5, %lo(.LCPI21_0)(a1) +; RV32IF-NEXT: flt.s a3, fa5, fs0 ; RV32IF-NEXT: beqz a3, .LBB21_6 ; RV32IF-NEXT: # %bb.5: -; RV32IF-NEXT: addi a4, a5, -1 +; RV32IF-NEXT: addi a2, a4, -1 ; RV32IF-NEXT: .LBB21_6: -; RV32IF-NEXT: and a1, a2, a4 +; RV32IF-NEXT: feq.s a1, fs0, fs0 +; RV32IF-NEXT: neg a4, a1 +; RV32IF-NEXT: and a1, a4, a2 +; RV32IF-NEXT: neg a2, s0 +; RV32IF-NEXT: and a0, a2, a0 +; RV32IF-NEXT: neg a2, a3 +; RV32IF-NEXT: or a0, a2, a0 +; RV32IF-NEXT: and a0, a4, a0 ; RV32IF-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IF-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IF-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IF-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IF-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IF-NEXT: addi sp, sp, 16 ; RV32IF-NEXT: ret ; @@ -1427,23 +1415,23 @@ define i64 @test_rint_si64(float %x) nounwind { ; RV32IZFINX-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZFINX-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZFINX-NEXT: and a0, s2, a0 -; RV32IZFINX-NEXT: flt.s a3, a2, s0 -; RV32IZFINX-NEXT: neg a2, a3 +; RV32IZFINX-NEXT: flt.s a4, a2, s0 +; RV32IZFINX-NEXT: neg a2, a4 ; RV32IZFINX-NEXT: or a0, a2, a0 ; RV32IZFINX-NEXT: feq.s a2, s0, s0 ; RV32IZFINX-NEXT: neg a2, a2 ; RV32IZFINX-NEXT: lui a5, 524288 -; RV32IZFINX-NEXT: lui a4, 524288 +; RV32IZFINX-NEXT: lui a3, 524288 ; RV32IZFINX-NEXT: beqz s1, .LBB21_4 ; RV32IZFINX-NEXT: # %bb.3: -; RV32IZFINX-NEXT: mv a4, a1 +; RV32IZFINX-NEXT: mv a3, a1 ; RV32IZFINX-NEXT: .LBB21_4: ; RV32IZFINX-NEXT: and a0, a2, a0 -; RV32IZFINX-NEXT: beqz a3, .LBB21_6 +; RV32IZFINX-NEXT: beqz a4, .LBB21_6 ; RV32IZFINX-NEXT: # %bb.5: -; RV32IZFINX-NEXT: addi a4, a5, -1 +; RV32IZFINX-NEXT: addi a3, a5, -1 ; RV32IZFINX-NEXT: .LBB21_6: -; RV32IZFINX-NEXT: and a1, a2, a4 +; RV32IZFINX-NEXT: and a1, a2, a3 ; RV32IZFINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IZFINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload diff --git a/llvm/test/CodeGen/RISCV/forced-atomics.ll b/llvm/test/CodeGen/RISCV/forced-atomics.ll index c303690aadff..f6a53a9d76dd 100644 --- a/llvm/test/CodeGen/RISCV/forced-atomics.ll +++ b/llvm/test/CodeGen/RISCV/forced-atomics.ll @@ -3567,8 +3567,8 @@ define i64 @rmw64_umax_seq_cst(ptr %p) nounwind { ; RV32-NEXT: # in Loop: Header=BB51_2 Depth=1 ; RV32-NEXT: neg a3, a0 ; RV32-NEXT: and a3, a3, a1 -; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: sw a4, 0(sp) +; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 @@ -3659,8 +3659,8 @@ define i64 @rmw64_umin_seq_cst(ptr %p) nounwind { ; RV32-NEXT: # in Loop: Header=BB52_2 Depth=1 ; RV32-NEXT: neg a3, a0 ; RV32-NEXT: and a3, a3, a1 -; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: sw a4, 0(sp) +; RV32-NEXT: sw a1, 4(sp) ; RV32-NEXT: mv a1, sp ; RV32-NEXT: li a4, 5 ; RV32-NEXT: li a5, 5 diff --git a/llvm/test/CodeGen/RISCV/fpclamptosat.ll b/llvm/test/CodeGen/RISCV/fpclamptosat.ll index 06ab813faf02..deb5a6d4013d 100644 --- a/llvm/test/CodeGen/RISCV/fpclamptosat.ll +++ b/llvm/test/CodeGen/RISCV/fpclamptosat.ll @@ -114,8 +114,8 @@ define i32 @utest_f64i32(double %x) { ; RV32IF-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IF-NEXT: .cfi_offset ra, -4 ; RV32IF-NEXT: call __fixunsdfdi -; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: sltiu a2, a0, -1 +; RV32IF-NEXT: seqz a1, a1 ; RV32IF-NEXT: and a1, a1, a2 ; RV32IF-NEXT: addi a1, a1, -1 ; RV32IF-NEXT: or a0, a1, a0 @@ -429,8 +429,8 @@ define i32 @utesth_f16i32(half %x) { ; RV32-NEXT: .cfi_offset ra, -4 ; RV32-NEXT: call __extendhfsf2 ; RV32-NEXT: call __fixunssfdi -; RV32-NEXT: seqz a1, a1 ; RV32-NEXT: sltiu a2, a0, -1 +; RV32-NEXT: seqz a1, a1 ; RV32-NEXT: and a1, a1, a2 ; RV32-NEXT: addi a1, a1, -1 ; RV32-NEXT: or a0, a1, a0 diff --git a/llvm/test/CodeGen/RISCV/half-convert.ll b/llvm/test/CodeGen/RISCV/half-convert.ll index 277749c75bbb..31fb6e2ee9c8 100644 --- a/llvm/test/CodeGen/RISCV/half-convert.ll +++ b/llvm/test/CodeGen/RISCV/half-convert.ll @@ -2145,47 +2145,41 @@ define i64 @fcvt_l_h(half %a) nounwind { define i64 @fcvt_l_h_sat(half %a) nounwind { ; RV32IZFH-LABEL: fcvt_l_h_sat: ; RV32IZFH: # %bb.0: # %start -; RV32IZFH-NEXT: addi sp, sp, -32 -; RV32IZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a0) +; RV32IZFH-NEXT: addi sp, sp, -16 +; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IZFH-NEXT: flt.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 -; RV32IZFH-NEXT: fle.s s2, fa5, fs0 -; RV32IZFH-NEXT: neg s3, s2 +; RV32IZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: and a0, s3, a0 -; RV32IZFH-NEXT: or a0, s1, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 ; RV32IZFH-NEXT: lui a4, 524288 -; RV32IZFH-NEXT: lui a3, 524288 -; RV32IZFH-NEXT: beqz s2, .LBB10_2 +; RV32IZFH-NEXT: lui a2, 524288 +; RV32IZFH-NEXT: beqz s0, .LBB10_2 ; RV32IZFH-NEXT: # %bb.1: # %start -; RV32IZFH-NEXT: mv a3, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB10_2: # %start -; RV32IZFH-NEXT: and a0, a2, a0 -; RV32IZFH-NEXT: beqz s0, .LBB10_4 +; RV32IZFH-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB10_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: addi a3, a4, -1 +; RV32IZFH-NEXT: addi a2, a4, -1 ; RV32IZFH-NEXT: .LBB10_4: # %start -; RV32IZFH-NEXT: and a1, a2, a3 -; RV32IZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: addi sp, sp, 32 +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: neg a3, s0 +; RV32IZFH-NEXT: and a0, a3, a0 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 +; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: addi sp, sp, 16 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: fcvt_l_h_sat: @@ -2199,47 +2193,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IDZFH-LABEL: fcvt_l_h_sat: ; RV32IDZFH: # %bb.0: # %start -; RV32IDZFH-NEXT: addi sp, sp, -32 -; RV32IDZFH-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IDZFH-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: addi sp, sp, -16 +; RV32IDZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IDZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFH-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IDZFH-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IDZFH-NEXT: fcvt.s.h fs0, fa0 -; RV32IDZFH-NEXT: flt.s s0, fa5, fs0 -; RV32IDZFH-NEXT: neg s1, s0 ; RV32IDZFH-NEXT: lui a0, 913408 ; RV32IDZFH-NEXT: fmv.w.x fa5, a0 -; RV32IDZFH-NEXT: fle.s s2, fa5, fs0 -; RV32IDZFH-NEXT: neg s3, s2 +; RV32IDZFH-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFH-NEXT: fmv.s fa0, fs0 ; RV32IDZFH-NEXT: call __fixsfdi -; RV32IDZFH-NEXT: and a0, s3, a0 -; RV32IDZFH-NEXT: or a0, s1, a0 -; RV32IDZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IDZFH-NEXT: neg a2, a2 ; RV32IDZFH-NEXT: lui a4, 524288 -; RV32IDZFH-NEXT: lui a3, 524288 -; RV32IDZFH-NEXT: beqz s2, .LBB10_2 +; RV32IDZFH-NEXT: lui a2, 524288 +; RV32IDZFH-NEXT: beqz s0, .LBB10_2 ; RV32IDZFH-NEXT: # %bb.1: # %start -; RV32IDZFH-NEXT: mv a3, a1 +; RV32IDZFH-NEXT: mv a2, a1 ; RV32IDZFH-NEXT: .LBB10_2: # %start -; RV32IDZFH-NEXT: and a0, a2, a0 -; RV32IDZFH-NEXT: beqz s0, .LBB10_4 +; RV32IDZFH-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IDZFH-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IDZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IDZFH-NEXT: beqz a3, .LBB10_4 ; RV32IDZFH-NEXT: # %bb.3: -; RV32IDZFH-NEXT: addi a3, a4, -1 +; RV32IDZFH-NEXT: addi a2, a4, -1 ; RV32IDZFH-NEXT: .LBB10_4: # %start -; RV32IDZFH-NEXT: and a1, a2, a3 -; RV32IDZFH-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IDZFH-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IDZFH-NEXT: neg a4, a1 +; RV32IDZFH-NEXT: and a1, a4, a2 +; RV32IDZFH-NEXT: neg a2, a3 +; RV32IDZFH-NEXT: neg a3, s0 +; RV32IDZFH-NEXT: and a0, a3, a0 +; RV32IDZFH-NEXT: or a0, a2, a0 +; RV32IDZFH-NEXT: and a0, a4, a0 +; RV32IDZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IDZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IDZFH-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32IDZFH-NEXT: addi sp, sp, 32 +; RV32IDZFH-NEXT: addi sp, sp, 16 ; RV32IDZFH-NEXT: ret ; ; RV64IDZFH-LABEL: fcvt_l_h_sat: @@ -2515,47 +2503,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32ID-LABEL: fcvt_l_h_sat: ; RV32ID: # %bb.0: # %start -; RV32ID-NEXT: addi sp, sp, -32 -; RV32ID-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32ID-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32ID-NEXT: addi sp, sp, -16 +; RV32ID-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32ID-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32ID-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill ; RV32ID-NEXT: call __extendhfsf2 -; RV32ID-NEXT: lui a0, %hi(.LCPI10_0) -; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32ID-NEXT: fmv.s fs0, fa0 -; RV32ID-NEXT: flt.s s0, fa5, fa0 -; RV32ID-NEXT: neg s1, s0 ; RV32ID-NEXT: lui a0, 913408 ; RV32ID-NEXT: fmv.w.x fa5, a0 -; RV32ID-NEXT: fle.s s2, fa5, fa0 -; RV32ID-NEXT: neg s3, s2 +; RV32ID-NEXT: fle.s s0, fa5, fa0 ; RV32ID-NEXT: call __fixsfdi -; RV32ID-NEXT: and a0, s3, a0 -; RV32ID-NEXT: or a0, s1, a0 -; RV32ID-NEXT: feq.s a2, fs0, fs0 -; RV32ID-NEXT: neg a2, a2 ; RV32ID-NEXT: lui a4, 524288 -; RV32ID-NEXT: lui a3, 524288 -; RV32ID-NEXT: beqz s2, .LBB10_2 +; RV32ID-NEXT: lui a2, 524288 +; RV32ID-NEXT: beqz s0, .LBB10_2 ; RV32ID-NEXT: # %bb.1: # %start -; RV32ID-NEXT: mv a3, a1 +; RV32ID-NEXT: mv a2, a1 ; RV32ID-NEXT: .LBB10_2: # %start -; RV32ID-NEXT: and a0, a2, a0 -; RV32ID-NEXT: beqz s0, .LBB10_4 +; RV32ID-NEXT: lui a1, %hi(.LCPI10_0) +; RV32ID-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32ID-NEXT: flt.s a3, fa5, fs0 +; RV32ID-NEXT: beqz a3, .LBB10_4 ; RV32ID-NEXT: # %bb.3: -; RV32ID-NEXT: addi a3, a4, -1 +; RV32ID-NEXT: addi a2, a4, -1 ; RV32ID-NEXT: .LBB10_4: # %start -; RV32ID-NEXT: and a1, a2, a3 -; RV32ID-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32ID-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32ID-NEXT: feq.s a1, fs0, fs0 +; RV32ID-NEXT: neg a4, a1 +; RV32ID-NEXT: and a1, a4, a2 +; RV32ID-NEXT: neg a2, s0 +; RV32ID-NEXT: and a0, a2, a0 +; RV32ID-NEXT: neg a2, a3 +; RV32ID-NEXT: or a0, a2, a0 +; RV32ID-NEXT: and a0, a4, a0 +; RV32ID-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32ID-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32ID-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32ID-NEXT: addi sp, sp, 32 +; RV32ID-NEXT: addi sp, sp, 16 ; RV32ID-NEXT: ret ; ; RV64ID-LABEL: fcvt_l_h_sat: @@ -2574,47 +2556,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IFZFHMIN-LABEL: fcvt_l_h_sat: ; RV32IFZFHMIN: # %bb.0: # %start -; RV32IFZFHMIN-NEXT: addi sp, sp, -32 -; RV32IFZFHMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: fsw fs0, 8(sp) # 4-byte Folded Spill -; RV32IFZFHMIN-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) +; RV32IFZFHMIN-NEXT: addi sp, sp, -16 +; RV32IFZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill +; RV32IFZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IFZFHMIN-NEXT: fcvt.s.h fs0, fa0 -; RV32IFZFHMIN-NEXT: flt.s s0, fa5, fs0 -; RV32IFZFHMIN-NEXT: neg s1, s0 ; RV32IFZFHMIN-NEXT: lui a0, 913408 ; RV32IFZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IFZFHMIN-NEXT: fle.s s2, fa5, fs0 -; RV32IFZFHMIN-NEXT: neg s3, s2 +; RV32IFZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IFZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IFZFHMIN-NEXT: call __fixsfdi -; RV32IFZFHMIN-NEXT: and a0, s3, a0 -; RV32IFZFHMIN-NEXT: or a0, s1, a0 -; RV32IFZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IFZFHMIN-NEXT: neg a2, a2 ; RV32IFZFHMIN-NEXT: lui a4, 524288 -; RV32IFZFHMIN-NEXT: lui a3, 524288 -; RV32IFZFHMIN-NEXT: beqz s2, .LBB10_2 +; RV32IFZFHMIN-NEXT: lui a2, 524288 +; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_2 ; RV32IFZFHMIN-NEXT: # %bb.1: # %start -; RV32IFZFHMIN-NEXT: mv a3, a1 +; RV32IFZFHMIN-NEXT: mv a2, a1 ; RV32IFZFHMIN-NEXT: .LBB10_2: # %start -; RV32IFZFHMIN-NEXT: and a0, a2, a0 -; RV32IFZFHMIN-NEXT: beqz s0, .LBB10_4 +; RV32IFZFHMIN-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IFZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IFZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IFZFHMIN-NEXT: beqz a3, .LBB10_4 ; RV32IFZFHMIN-NEXT: # %bb.3: -; RV32IFZFHMIN-NEXT: addi a3, a4, -1 +; RV32IFZFHMIN-NEXT: addi a2, a4, -1 ; RV32IFZFHMIN-NEXT: .LBB10_4: # %start -; RV32IFZFHMIN-NEXT: and a1, a2, a3 -; RV32IFZFHMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: flw fs0, 8(sp) # 4-byte Folded Reload -; RV32IFZFHMIN-NEXT: addi sp, sp, 32 +; RV32IFZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IFZFHMIN-NEXT: neg a4, a1 +; RV32IFZFHMIN-NEXT: and a1, a4, a2 +; RV32IFZFHMIN-NEXT: neg a2, a3 +; RV32IFZFHMIN-NEXT: neg a3, s0 +; RV32IFZFHMIN-NEXT: and a0, a3, a0 +; RV32IFZFHMIN-NEXT: or a0, a2, a0 +; RV32IFZFHMIN-NEXT: and a0, a4, a0 +; RV32IFZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload +; RV32IFZFHMIN-NEXT: addi sp, sp, 16 ; RV32IFZFHMIN-NEXT: ret ; ; CHECK64-IZFHMIN-LABEL: fcvt_l_h_sat: @@ -2629,47 +2605,41 @@ define i64 @fcvt_l_h_sat(half %a) nounwind { ; ; RV32IDZFHMIN-LABEL: fcvt_l_h_sat: ; RV32IDZFHMIN: # %bb.0: # %start -; RV32IDZFHMIN-NEXT: addi sp, sp, -32 -; RV32IDZFHMIN-NEXT: sw ra, 28(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s0, 24(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s1, 20(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s2, 16(sp) # 4-byte Folded Spill -; RV32IDZFHMIN-NEXT: sw s3, 12(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: addi sp, sp, -16 +; RV32IDZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill +; RV32IDZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill ; RV32IDZFHMIN-NEXT: fsd fs0, 0(sp) # 8-byte Folded Spill -; RV32IDZFHMIN-NEXT: lui a0, %hi(.LCPI10_0) -; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a0) ; RV32IDZFHMIN-NEXT: fcvt.s.h fs0, fa0 -; RV32IDZFHMIN-NEXT: flt.s s0, fa5, fs0 -; RV32IDZFHMIN-NEXT: neg s1, s0 ; RV32IDZFHMIN-NEXT: lui a0, 913408 ; RV32IDZFHMIN-NEXT: fmv.w.x fa5, a0 -; RV32IDZFHMIN-NEXT: fle.s s2, fa5, fs0 -; RV32IDZFHMIN-NEXT: neg s3, s2 +; RV32IDZFHMIN-NEXT: fle.s s0, fa5, fs0 ; RV32IDZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IDZFHMIN-NEXT: call __fixsfdi -; RV32IDZFHMIN-NEXT: and a0, s3, a0 -; RV32IDZFHMIN-NEXT: or a0, s1, a0 -; RV32IDZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IDZFHMIN-NEXT: neg a2, a2 ; RV32IDZFHMIN-NEXT: lui a4, 524288 -; RV32IDZFHMIN-NEXT: lui a3, 524288 -; RV32IDZFHMIN-NEXT: beqz s2, .LBB10_2 +; RV32IDZFHMIN-NEXT: lui a2, 524288 +; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_2 ; RV32IDZFHMIN-NEXT: # %bb.1: # %start -; RV32IDZFHMIN-NEXT: mv a3, a1 +; RV32IDZFHMIN-NEXT: mv a2, a1 ; RV32IDZFHMIN-NEXT: .LBB10_2: # %start -; RV32IDZFHMIN-NEXT: and a0, a2, a0 -; RV32IDZFHMIN-NEXT: beqz s0, .LBB10_4 +; RV32IDZFHMIN-NEXT: lui a1, %hi(.LCPI10_0) +; RV32IDZFHMIN-NEXT: flw fa5, %lo(.LCPI10_0)(a1) +; RV32IDZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IDZFHMIN-NEXT: beqz a3, .LBB10_4 ; RV32IDZFHMIN-NEXT: # %bb.3: -; RV32IDZFHMIN-NEXT: addi a3, a4, -1 +; RV32IDZFHMIN-NEXT: addi a2, a4, -1 ; RV32IDZFHMIN-NEXT: .LBB10_4: # %start -; RV32IDZFHMIN-NEXT: and a1, a2, a3 -; RV32IDZFHMIN-NEXT: lw ra, 28(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s0, 24(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s1, 20(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s2, 16(sp) # 4-byte Folded Reload -; RV32IDZFHMIN-NEXT: lw s3, 12(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IDZFHMIN-NEXT: neg a4, a1 +; RV32IDZFHMIN-NEXT: and a1, a4, a2 +; RV32IDZFHMIN-NEXT: neg a2, a3 +; RV32IDZFHMIN-NEXT: neg a3, s0 +; RV32IDZFHMIN-NEXT: and a0, a3, a0 +; RV32IDZFHMIN-NEXT: or a0, a2, a0 +; RV32IDZFHMIN-NEXT: and a0, a4, a0 +; RV32IDZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload +; RV32IDZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload ; RV32IDZFHMIN-NEXT: fld fs0, 0(sp) # 8-byte Folded Reload -; RV32IDZFHMIN-NEXT: addi sp, sp, 32 +; RV32IDZFHMIN-NEXT: addi sp, sp, 16 ; RV32IDZFHMIN-NEXT: ret ; ; CHECK32-IZHINXMIN-LABEL: fcvt_l_h_sat: diff --git a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll index 9c95210bfa7c..04a8a66f4459 100644 --- a/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll +++ b/llvm/test/CodeGen/RISCV/half-round-conv-sat.ll @@ -108,40 +108,38 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI1_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB1_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB1_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI1_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI1_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB1_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB1_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB1_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB1_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_floor_si64: @@ -179,16 +177,16 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI1_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI1_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB1_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB1_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -196,11 +194,11 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB1_6 +; RV32IZHINX-NEXT: beqz a4, .LBB1_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB1_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_floor_si64: @@ -238,41 +236,39 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI1_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB1_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB1_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI1_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI1_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB1_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB1_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB1_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_floor_si64: @@ -324,16 +320,16 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI1_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI1_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB1_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB1_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -341,11 +337,11 @@ define i64 @test_floor_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB1_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB1_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB1_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_floor_si64: @@ -824,40 +820,38 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI5_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB5_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB5_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI5_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI5_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB5_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB5_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB5_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB5_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_ceil_si64: @@ -895,16 +889,16 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI5_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI5_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB5_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB5_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -912,11 +906,11 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB5_6 +; RV32IZHINX-NEXT: beqz a4, .LBB5_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB5_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_ceil_si64: @@ -954,41 +948,39 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI5_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB5_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB5_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI5_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI5_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB5_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB5_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB5_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_ceil_si64: @@ -1040,16 +1032,16 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI5_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI5_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB5_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB5_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1057,11 +1049,11 @@ define i64 @test_ceil_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB5_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB5_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB5_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_ceil_si64: @@ -1540,40 +1532,38 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI9_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB9_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB9_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI9_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI9_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB9_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB9_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB9_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB9_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_trunc_si64: @@ -1611,16 +1601,16 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI9_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI9_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB9_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB9_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1628,11 +1618,11 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB9_6 +; RV32IZHINX-NEXT: beqz a4, .LBB9_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB9_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_trunc_si64: @@ -1670,41 +1660,39 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI9_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB9_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB9_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI9_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI9_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB9_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB9_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB9_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_trunc_si64: @@ -1756,16 +1744,16 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI9_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI9_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB9_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB9_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -1773,11 +1761,11 @@ define i64 @test_trunc_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB9_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB9_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB9_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_trunc_si64: @@ -2256,40 +2244,38 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI13_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB13_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB13_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI13_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI13_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB13_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB13_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB13_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB13_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_round_si64: @@ -2327,16 +2313,16 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI13_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI13_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB13_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB13_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2344,11 +2330,11 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB13_6 +; RV32IZHINX-NEXT: beqz a4, .LBB13_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB13_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_round_si64: @@ -2386,41 +2372,39 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI13_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB13_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB13_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI13_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI13_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB13_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB13_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB13_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_round_si64: @@ -2472,16 +2456,16 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI13_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI13_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB13_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB13_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -2489,11 +2473,11 @@ define i64 @test_round_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB13_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB13_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB13_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_round_si64: @@ -2972,40 +2956,38 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI17_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB17_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB17_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI17_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI17_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB17_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB17_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB17_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB17_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_roundeven_si64: @@ -3043,16 +3025,16 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI17_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI17_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB17_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB17_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3060,11 +3042,11 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB17_6 +; RV32IZHINX-NEXT: beqz a4, .LBB17_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB17_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_roundeven_si64: @@ -3102,41 +3084,39 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI17_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB17_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB17_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI17_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI17_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB17_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB17_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB17_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_roundeven_si64: @@ -3188,16 +3168,16 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI17_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI17_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB17_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB17_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3205,11 +3185,11 @@ define i64 @test_roundeven_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB17_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB17_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB17_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_roundeven_si64: @@ -3688,40 +3668,38 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFH-NEXT: addi sp, sp, -16 ; RV32IZFH-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFH-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFH-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFH-NEXT: fcvt.s.h fs0, fa0 ; RV32IZFH-NEXT: lui a0, 913408 ; RV32IZFH-NEXT: fmv.w.x fa5, a0 ; RV32IZFH-NEXT: fle.s s0, fa5, fs0 -; RV32IZFH-NEXT: neg s1, s0 ; RV32IZFH-NEXT: fmv.s fa0, fs0 ; RV32IZFH-NEXT: call __fixsfdi -; RV32IZFH-NEXT: lui a2, %hi(.LCPI21_1) -; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a2) -; RV32IZFH-NEXT: and a0, s1, a0 -; RV32IZFH-NEXT: flt.s a3, fa5, fs0 -; RV32IZFH-NEXT: neg a2, a3 -; RV32IZFH-NEXT: or a0, a2, a0 -; RV32IZFH-NEXT: feq.s a2, fs0, fs0 -; RV32IZFH-NEXT: neg a2, a2 -; RV32IZFH-NEXT: lui a5, 524288 ; RV32IZFH-NEXT: lui a4, 524288 +; RV32IZFH-NEXT: lui a2, 524288 ; RV32IZFH-NEXT: beqz s0, .LBB21_4 ; RV32IZFH-NEXT: # %bb.3: -; RV32IZFH-NEXT: mv a4, a1 +; RV32IZFH-NEXT: mv a2, a1 ; RV32IZFH-NEXT: .LBB21_4: +; RV32IZFH-NEXT: lui a1, %hi(.LCPI21_1) +; RV32IZFH-NEXT: flw fa5, %lo(.LCPI21_1)(a1) +; RV32IZFH-NEXT: flt.s a3, fa5, fs0 +; RV32IZFH-NEXT: beqz a3, .LBB21_6 +; RV32IZFH-NEXT: # %bb.5: +; RV32IZFH-NEXT: addi a2, a4, -1 +; RV32IZFH-NEXT: .LBB21_6: +; RV32IZFH-NEXT: feq.s a1, fs0, fs0 +; RV32IZFH-NEXT: neg a4, a1 +; RV32IZFH-NEXT: and a1, a4, a2 +; RV32IZFH-NEXT: neg a2, s0 ; RV32IZFH-NEXT: and a0, a2, a0 +; RV32IZFH-NEXT: neg a2, a3 +; RV32IZFH-NEXT: or a0, a2, a0 +; RV32IZFH-NEXT: and a0, a4, a0 ; RV32IZFH-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFH-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFH-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFH-NEXT: addi sp, sp, 16 -; RV32IZFH-NEXT: beqz a3, .LBB21_6 -; RV32IZFH-NEXT: # %bb.5: -; RV32IZFH-NEXT: addi a4, a5, -1 -; RV32IZFH-NEXT: .LBB21_6: -; RV32IZFH-NEXT: and a1, a2, a4 ; RV32IZFH-NEXT: ret ; ; RV64IZFH-LABEL: test_rint_si64: @@ -3759,16 +3737,16 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lui a2, %hi(.LCPI21_1) ; RV32IZHINX-NEXT: lw a2, %lo(.LCPI21_1)(a2) ; RV32IZHINX-NEXT: and a0, s2, a0 -; RV32IZHINX-NEXT: flt.s a3, a2, s0 -; RV32IZHINX-NEXT: neg a2, a3 +; RV32IZHINX-NEXT: flt.s a4, a2, s0 +; RV32IZHINX-NEXT: neg a2, a4 ; RV32IZHINX-NEXT: or a0, a2, a0 ; RV32IZHINX-NEXT: feq.s a2, s0, s0 ; RV32IZHINX-NEXT: neg a2, a2 ; RV32IZHINX-NEXT: lui a5, 524288 -; RV32IZHINX-NEXT: lui a4, 524288 +; RV32IZHINX-NEXT: lui a3, 524288 ; RV32IZHINX-NEXT: beqz s1, .LBB21_4 ; RV32IZHINX-NEXT: # %bb.3: -; RV32IZHINX-NEXT: mv a4, a1 +; RV32IZHINX-NEXT: mv a3, a1 ; RV32IZHINX-NEXT: .LBB21_4: ; RV32IZHINX-NEXT: and a0, a2, a0 ; RV32IZHINX-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3776,11 +3754,11 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINX-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINX-NEXT: addi sp, sp, 16 -; RV32IZHINX-NEXT: beqz a3, .LBB21_6 +; RV32IZHINX-NEXT: beqz a4, .LBB21_6 ; RV32IZHINX-NEXT: # %bb.5: -; RV32IZHINX-NEXT: addi a4, a5, -1 +; RV32IZHINX-NEXT: addi a3, a5, -1 ; RV32IZHINX-NEXT: .LBB21_6: -; RV32IZHINX-NEXT: and a1, a2, a4 +; RV32IZHINX-NEXT: and a1, a2, a3 ; RV32IZHINX-NEXT: ret ; ; RV64IZHINX-LABEL: test_rint_si64: @@ -3818,41 +3796,39 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZFHMIN-NEXT: addi sp, sp, -16 ; RV32IZFHMIN-NEXT: sw ra, 12(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: sw s0, 8(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: sw s1, 4(sp) # 4-byte Folded Spill -; RV32IZFHMIN-NEXT: fsw fs0, 0(sp) # 4-byte Folded Spill +; RV32IZFHMIN-NEXT: fsw fs0, 4(sp) # 4-byte Folded Spill ; RV32IZFHMIN-NEXT: fcvt.h.s fa5, fa5 ; RV32IZFHMIN-NEXT: fcvt.s.h fs0, fa5 ; RV32IZFHMIN-NEXT: lui a0, 913408 ; RV32IZFHMIN-NEXT: fmv.w.x fa5, a0 ; RV32IZFHMIN-NEXT: fle.s s0, fa5, fs0 -; RV32IZFHMIN-NEXT: neg s1, s0 ; RV32IZFHMIN-NEXT: fmv.s fa0, fs0 ; RV32IZFHMIN-NEXT: call __fixsfdi -; RV32IZFHMIN-NEXT: lui a2, %hi(.LCPI21_0) -; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a2) -; RV32IZFHMIN-NEXT: and a0, s1, a0 -; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 -; RV32IZFHMIN-NEXT: neg a2, a3 -; RV32IZFHMIN-NEXT: or a0, a2, a0 -; RV32IZFHMIN-NEXT: feq.s a2, fs0, fs0 -; RV32IZFHMIN-NEXT: neg a2, a2 -; RV32IZFHMIN-NEXT: lui a5, 524288 ; RV32IZFHMIN-NEXT: lui a4, 524288 +; RV32IZFHMIN-NEXT: lui a2, 524288 ; RV32IZFHMIN-NEXT: beqz s0, .LBB21_4 ; RV32IZFHMIN-NEXT: # %bb.3: -; RV32IZFHMIN-NEXT: mv a4, a1 +; RV32IZFHMIN-NEXT: mv a2, a1 ; RV32IZFHMIN-NEXT: .LBB21_4: +; RV32IZFHMIN-NEXT: lui a1, %hi(.LCPI21_0) +; RV32IZFHMIN-NEXT: flw fa5, %lo(.LCPI21_0)(a1) +; RV32IZFHMIN-NEXT: flt.s a3, fa5, fs0 +; RV32IZFHMIN-NEXT: beqz a3, .LBB21_6 +; RV32IZFHMIN-NEXT: # %bb.5: +; RV32IZFHMIN-NEXT: addi a2, a4, -1 +; RV32IZFHMIN-NEXT: .LBB21_6: +; RV32IZFHMIN-NEXT: feq.s a1, fs0, fs0 +; RV32IZFHMIN-NEXT: neg a4, a1 +; RV32IZFHMIN-NEXT: and a1, a4, a2 +; RV32IZFHMIN-NEXT: neg a2, s0 ; RV32IZFHMIN-NEXT: and a0, a2, a0 +; RV32IZFHMIN-NEXT: neg a2, a3 +; RV32IZFHMIN-NEXT: or a0, a2, a0 +; RV32IZFHMIN-NEXT: and a0, a4, a0 ; RV32IZFHMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: lw s0, 8(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload -; RV32IZFHMIN-NEXT: flw fs0, 0(sp) # 4-byte Folded Reload +; RV32IZFHMIN-NEXT: flw fs0, 4(sp) # 4-byte Folded Reload ; RV32IZFHMIN-NEXT: addi sp, sp, 16 -; RV32IZFHMIN-NEXT: beqz a3, .LBB21_6 -; RV32IZFHMIN-NEXT: # %bb.5: -; RV32IZFHMIN-NEXT: addi a4, a5, -1 -; RV32IZFHMIN-NEXT: .LBB21_6: -; RV32IZFHMIN-NEXT: and a1, a2, a4 ; RV32IZFHMIN-NEXT: ret ; ; RV64IZFHMIN-LABEL: test_rint_si64: @@ -3904,16 +3880,16 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lui a2, %hi(.LCPI21_0) ; RV32IZHINXMIN-NEXT: lw a2, %lo(.LCPI21_0)(a2) ; RV32IZHINXMIN-NEXT: and a0, s2, a0 -; RV32IZHINXMIN-NEXT: flt.s a3, a2, s0 -; RV32IZHINXMIN-NEXT: neg a2, a3 +; RV32IZHINXMIN-NEXT: flt.s a4, a2, s0 +; RV32IZHINXMIN-NEXT: neg a2, a4 ; RV32IZHINXMIN-NEXT: or a0, a2, a0 ; RV32IZHINXMIN-NEXT: feq.s a2, s0, s0 ; RV32IZHINXMIN-NEXT: neg a2, a2 ; RV32IZHINXMIN-NEXT: lui a5, 524288 -; RV32IZHINXMIN-NEXT: lui a4, 524288 +; RV32IZHINXMIN-NEXT: lui a3, 524288 ; RV32IZHINXMIN-NEXT: beqz s1, .LBB21_4 ; RV32IZHINXMIN-NEXT: # %bb.3: -; RV32IZHINXMIN-NEXT: mv a4, a1 +; RV32IZHINXMIN-NEXT: mv a3, a1 ; RV32IZHINXMIN-NEXT: .LBB21_4: ; RV32IZHINXMIN-NEXT: and a0, a2, a0 ; RV32IZHINXMIN-NEXT: lw ra, 12(sp) # 4-byte Folded Reload @@ -3921,11 +3897,11 @@ define i64 @test_rint_si64(half %x) nounwind { ; RV32IZHINXMIN-NEXT: lw s1, 4(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: lw s2, 0(sp) # 4-byte Folded Reload ; RV32IZHINXMIN-NEXT: addi sp, sp, 16 -; RV32IZHINXMIN-NEXT: beqz a3, .LBB21_6 +; RV32IZHINXMIN-NEXT: beqz a4, .LBB21_6 ; RV32IZHINXMIN-NEXT: # %bb.5: -; RV32IZHINXMIN-NEXT: addi a4, a5, -1 +; RV32IZHINXMIN-NEXT: addi a3, a5, -1 ; RV32IZHINXMIN-NEXT: .LBB21_6: -; RV32IZHINXMIN-NEXT: and a1, a2, a4 +; RV32IZHINXMIN-NEXT: and a1, a2, a3 ; RV32IZHINXMIN-NEXT: ret ; ; RV64IZHINXMIN-LABEL: test_rint_si64: diff --git a/llvm/test/CodeGen/RISCV/iabs.ll b/llvm/test/CodeGen/RISCV/iabs.ll index 98c886333d69..a0c85ab4dca7 100644 --- a/llvm/test/CodeGen/RISCV/iabs.ll +++ b/llvm/test/CodeGen/RISCV/iabs.ll @@ -630,8 +630,8 @@ define void @zext16_abs8(i8 %x, ptr %p) { ; RV32I-LABEL: zext16_abs8: ; RV32I: # %bb.0: ; RV32I-NEXT: slli a0, a0, 24 -; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: srai a2, a0, 31 +; RV32I-NEXT: srai a0, a0, 24 ; RV32I-NEXT: xor a0, a0, a2 ; RV32I-NEXT: sub a0, a0, a2 ; RV32I-NEXT: sh a0, 0(a1) @@ -648,8 +648,8 @@ define void @zext16_abs8(i8 %x, ptr %p) { ; RV64I-LABEL: zext16_abs8: ; RV64I: # %bb.0: ; RV64I-NEXT: slli a0, a0, 56 -; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: srai a2, a0, 63 +; RV64I-NEXT: srai a0, a0, 56 ; RV64I-NEXT: xor a0, a0, a2 ; RV64I-NEXT: subw a0, a0, a2 ; RV64I-NEXT: sh a0, 0(a1) diff --git a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll index b3bda5973eb8..a6b2d3141f22 100644 --- a/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll +++ b/llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll @@ -2190,65 +2190,66 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.d fs0, fa0 -; CHECK-NOV-NEXT: fmv.d fa0, fa1 +; CHECK-NOV-NEXT: fmv.d fs0, fa1 ; CHECK-NOV-NEXT: call __fixdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixdfti -; CHECK-NOV-NEXT: li a2, -1 -; CHECK-NOV-NEXT: srli a3, a2, 1 -; CHECK-NOV-NEXT: beqz s1, .LBB18_3 +; CHECK-NOV-NEXT: mv a2, a0 +; CHECK-NOV-NEXT: li a0, -1 +; CHECK-NOV-NEXT: srli a3, a0, 1 +; CHECK-NOV-NEXT: beqz a1, .LBB18_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 0 -; CHECK-NOV-NEXT: bnez a1, .LBB18_4 +; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: bnez s1, .LBB18_4 ; CHECK-NOV-NEXT: .LBB18_2: -; CHECK-NOV-NEXT: sltu a5, a0, a3 +; CHECK-NOV-NEXT: sltu a5, s0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB18_5 ; CHECK-NOV-NEXT: j .LBB18_6 ; CHECK-NOV-NEXT: .LBB18_3: -; CHECK-NOV-NEXT: sltu a4, s0, a3 -; CHECK-NOV-NEXT: beqz a1, .LBB18_2 +; CHECK-NOV-NEXT: sltu a4, a2, a3 +; CHECK-NOV-NEXT: beqz s1, .LBB18_2 ; CHECK-NOV-NEXT: .LBB18_4: # %entry -; CHECK-NOV-NEXT: slti a5, a1, 0 +; CHECK-NOV-NEXT: slti a5, s1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB18_6 ; CHECK-NOV-NEXT: .LBB18_5: # %entry -; CHECK-NOV-NEXT: mv a0, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB18_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, s1 +; CHECK-NOV-NEXT: and a5, a5, a1 ; CHECK-NOV-NEXT: bnez a4, .LBB18_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a2, a3 ; CHECK-NOV-NEXT: .LBB18_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, a1 -; CHECK-NOV-NEXT: slli a1, a2, 63 -; CHECK-NOV-NEXT: beq a5, a2, .LBB18_11 +; CHECK-NOV-NEXT: and a4, a6, s1 +; CHECK-NOV-NEXT: slli a1, a0, 63 +; CHECK-NOV-NEXT: beq a5, a0, .LBB18_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a2, .LBB18_12 +; CHECK-NOV-NEXT: bne a4, a0, .LBB18_12 ; CHECK-NOV-NEXT: .LBB18_10: -; CHECK-NOV-NEXT: sltu a2, a1, a0 -; CHECK-NOV-NEXT: beqz a2, .LBB18_13 +; CHECK-NOV-NEXT: sltu a0, a1, s0 +; CHECK-NOV-NEXT: beqz a0, .LBB18_13 ; CHECK-NOV-NEXT: j .LBB18_14 ; CHECK-NOV-NEXT: .LBB18_11: -; CHECK-NOV-NEXT: sltu a3, a1, s0 -; CHECK-NOV-NEXT: beq a4, a2, .LBB18_10 +; CHECK-NOV-NEXT: sltu a3, a1, a2 +; CHECK-NOV-NEXT: beq a4, a0, .LBB18_10 ; CHECK-NOV-NEXT: .LBB18_12: # %entry -; CHECK-NOV-NEXT: slti a2, a4, 0 -; CHECK-NOV-NEXT: xori a2, a2, 1 -; CHECK-NOV-NEXT: bnez a2, .LBB18_14 +; CHECK-NOV-NEXT: slti a0, a4, 0 +; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: bnez a0, .LBB18_14 ; CHECK-NOV-NEXT: .LBB18_13: # %entry -; CHECK-NOV-NEXT: mv a0, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB18_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB18_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: .LBB18_16: # %entry -; CHECK-NOV-NEXT: mv a1, s0 +; CHECK-NOV-NEXT: mv a0, s0 +; CHECK-NOV-NEXT: mv a1, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2273,43 +2274,43 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixdfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz s1, .LBB18_3 +; CHECK-V-NEXT: beqz a1, .LBB18_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, s1, 0 -; CHECK-V-NEXT: bnez a1, .LBB18_4 +; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: bnez s1, .LBB18_4 ; CHECK-V-NEXT: .LBB18_2: -; CHECK-V-NEXT: sltu a5, a0, a3 +; CHECK-V-NEXT: sltu a5, s0, a3 ; CHECK-V-NEXT: beqz a5, .LBB18_5 ; CHECK-V-NEXT: j .LBB18_6 ; CHECK-V-NEXT: .LBB18_3: -; CHECK-V-NEXT: sltu a4, s0, a3 -; CHECK-V-NEXT: beqz a1, .LBB18_2 +; CHECK-V-NEXT: sltu a4, a0, a3 +; CHECK-V-NEXT: beqz s1, .LBB18_2 ; CHECK-V-NEXT: .LBB18_4: # %entry -; CHECK-V-NEXT: slti a5, a1, 0 +; CHECK-V-NEXT: slti a5, s1, 0 ; CHECK-V-NEXT: bnez a5, .LBB18_6 ; CHECK-V-NEXT: .LBB18_5: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB18_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, s1 +; CHECK-V-NEXT: and a5, a5, a1 ; CHECK-V-NEXT: bnez a4, .LBB18_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB18_8: # %entry -; CHECK-V-NEXT: and a4, a6, a1 +; CHECK-V-NEXT: and a4, a6, s1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB18_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -2317,26 +2318,26 @@ define <2 x i64> @stest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB18_12 ; CHECK-V-NEXT: .LBB18_10: -; CHECK-V-NEXT: sltu a2, a1, a0 +; CHECK-V-NEXT: sltu a2, a1, s0 ; CHECK-V-NEXT: beqz a2, .LBB18_13 ; CHECK-V-NEXT: j .LBB18_14 ; CHECK-V-NEXT: .LBB18_11: -; CHECK-V-NEXT: sltu a3, a1, s0 +; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB18_10 ; CHECK-V-NEXT: .LBB18_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB18_14 ; CHECK-V-NEXT: .LBB18_13: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB18_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB18_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB18_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, s0 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, s0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2369,19 +2370,19 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.d fs0, fa0 -; CHECK-NOV-NEXT: fmv.d fa0, fa1 +; CHECK-NOV-NEXT: fmv.d fs0, fa1 ; CHECK-NOV-NEXT: call __fixunsdfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixunsdfti -; CHECK-NOV-NEXT: snez a2, s1 ; CHECK-NOV-NEXT: snez a1, a1 +; CHECK-NOV-NEXT: snez a2, s1 +; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a2, a2, s0 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a0, a1, a0 -; CHECK-NOV-NEXT: addi a1, a2, -1 -; CHECK-NOV-NEXT: and a1, a1, s0 +; CHECK-NOV-NEXT: and a1, a1, a0 +; CHECK-NOV-NEXT: mv a0, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2406,25 +2407,25 @@ define <2 x i64> @utest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixunsdfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e64, m1, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunsdfti -; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: snez a1, a1 -; CHECK-V-NEXT: addi a1, a1, -1 -; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s0 +; CHECK-V-NEXT: addi a1, a1, -1 +; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a2 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2466,32 +2467,32 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB20_2: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: slti a3, a1, 1 +; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB20_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB20_4: # %entry +; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB20_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB20_8 ; CHECK-NOV-NEXT: .LBB20_6: -; CHECK-NOV-NEXT: snez a2, a0 +; CHECK-NOV-NEXT: snez a0, a4 ; CHECK-NOV-NEXT: j .LBB20_9 ; CHECK-NOV-NEXT: .LBB20_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB20_6 ; CHECK-NOV-NEXT: .LBB20_8: # %entry -; CHECK-NOV-NEXT: sgtz a2, a2 +; CHECK-NOV-NEXT: sgtz a0, a2 ; CHECK-NOV-NEXT: .LBB20_9: # %entry -; CHECK-NOV-NEXT: neg a2, a2 -; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: neg a0, a0 +; CHECK-NOV-NEXT: and a0, a0, a4 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -2533,15 +2534,15 @@ define <2 x i64> @ustest_f64i64(<2 x double> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB20_2: # %entry -; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: slti a4, a1, 1 +; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: blez a1, .LBB20_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB20_4: # %entry +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB20_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -2596,65 +2597,66 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.s fs0, fa0 -; CHECK-NOV-NEXT: fmv.s fa0, fa1 +; CHECK-NOV-NEXT: fmv.s fs0, fa1 ; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: li a2, -1 -; CHECK-NOV-NEXT: srli a3, a2, 1 -; CHECK-NOV-NEXT: beqz s1, .LBB21_3 +; CHECK-NOV-NEXT: mv a2, a0 +; CHECK-NOV-NEXT: li a0, -1 +; CHECK-NOV-NEXT: srli a3, a0, 1 +; CHECK-NOV-NEXT: beqz a1, .LBB21_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 0 -; CHECK-NOV-NEXT: bnez a1, .LBB21_4 +; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: bnez s1, .LBB21_4 ; CHECK-NOV-NEXT: .LBB21_2: -; CHECK-NOV-NEXT: sltu a5, a0, a3 +; CHECK-NOV-NEXT: sltu a5, s0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB21_5 ; CHECK-NOV-NEXT: j .LBB21_6 ; CHECK-NOV-NEXT: .LBB21_3: -; CHECK-NOV-NEXT: sltu a4, s0, a3 -; CHECK-NOV-NEXT: beqz a1, .LBB21_2 +; CHECK-NOV-NEXT: sltu a4, a2, a3 +; CHECK-NOV-NEXT: beqz s1, .LBB21_2 ; CHECK-NOV-NEXT: .LBB21_4: # %entry -; CHECK-NOV-NEXT: slti a5, a1, 0 +; CHECK-NOV-NEXT: slti a5, s1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB21_6 ; CHECK-NOV-NEXT: .LBB21_5: # %entry -; CHECK-NOV-NEXT: mv a0, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB21_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, s1 +; CHECK-NOV-NEXT: and a5, a5, a1 ; CHECK-NOV-NEXT: bnez a4, .LBB21_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a2, a3 ; CHECK-NOV-NEXT: .LBB21_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, a1 -; CHECK-NOV-NEXT: slli a1, a2, 63 -; CHECK-NOV-NEXT: beq a5, a2, .LBB21_11 +; CHECK-NOV-NEXT: and a4, a6, s1 +; CHECK-NOV-NEXT: slli a1, a0, 63 +; CHECK-NOV-NEXT: beq a5, a0, .LBB21_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a2, .LBB21_12 +; CHECK-NOV-NEXT: bne a4, a0, .LBB21_12 ; CHECK-NOV-NEXT: .LBB21_10: -; CHECK-NOV-NEXT: sltu a2, a1, a0 -; CHECK-NOV-NEXT: beqz a2, .LBB21_13 +; CHECK-NOV-NEXT: sltu a0, a1, s0 +; CHECK-NOV-NEXT: beqz a0, .LBB21_13 ; CHECK-NOV-NEXT: j .LBB21_14 ; CHECK-NOV-NEXT: .LBB21_11: -; CHECK-NOV-NEXT: sltu a3, a1, s0 -; CHECK-NOV-NEXT: beq a4, a2, .LBB21_10 +; CHECK-NOV-NEXT: sltu a3, a1, a2 +; CHECK-NOV-NEXT: beq a4, a0, .LBB21_10 ; CHECK-NOV-NEXT: .LBB21_12: # %entry -; CHECK-NOV-NEXT: slti a2, a4, 0 -; CHECK-NOV-NEXT: xori a2, a2, 1 -; CHECK-NOV-NEXT: bnez a2, .LBB21_14 +; CHECK-NOV-NEXT: slti a0, a4, 0 +; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: bnez a0, .LBB21_14 ; CHECK-NOV-NEXT: .LBB21_13: # %entry -; CHECK-NOV-NEXT: mv a0, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB21_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB21_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: .LBB21_16: # %entry -; CHECK-NOV-NEXT: mv a1, s0 +; CHECK-NOV-NEXT: mv a0, s0 +; CHECK-NOV-NEXT: mv a1, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2679,43 +2681,43 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz s1, .LBB21_3 +; CHECK-V-NEXT: beqz a1, .LBB21_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, s1, 0 -; CHECK-V-NEXT: bnez a1, .LBB21_4 +; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: bnez s1, .LBB21_4 ; CHECK-V-NEXT: .LBB21_2: -; CHECK-V-NEXT: sltu a5, a0, a3 +; CHECK-V-NEXT: sltu a5, s0, a3 ; CHECK-V-NEXT: beqz a5, .LBB21_5 ; CHECK-V-NEXT: j .LBB21_6 ; CHECK-V-NEXT: .LBB21_3: -; CHECK-V-NEXT: sltu a4, s0, a3 -; CHECK-V-NEXT: beqz a1, .LBB21_2 +; CHECK-V-NEXT: sltu a4, a0, a3 +; CHECK-V-NEXT: beqz s1, .LBB21_2 ; CHECK-V-NEXT: .LBB21_4: # %entry -; CHECK-V-NEXT: slti a5, a1, 0 +; CHECK-V-NEXT: slti a5, s1, 0 ; CHECK-V-NEXT: bnez a5, .LBB21_6 ; CHECK-V-NEXT: .LBB21_5: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB21_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, s1 +; CHECK-V-NEXT: and a5, a5, a1 ; CHECK-V-NEXT: bnez a4, .LBB21_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB21_8: # %entry -; CHECK-V-NEXT: and a4, a6, a1 +; CHECK-V-NEXT: and a4, a6, s1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB21_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -2723,26 +2725,26 @@ define <2 x i64> @stest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB21_12 ; CHECK-V-NEXT: .LBB21_10: -; CHECK-V-NEXT: sltu a2, a1, a0 +; CHECK-V-NEXT: sltu a2, a1, s0 ; CHECK-V-NEXT: beqz a2, .LBB21_13 ; CHECK-V-NEXT: j .LBB21_14 ; CHECK-V-NEXT: .LBB21_11: -; CHECK-V-NEXT: sltu a3, a1, s0 +; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB21_10 ; CHECK-V-NEXT: .LBB21_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB21_14 ; CHECK-V-NEXT: .LBB21_13: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB21_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB21_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB21_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, s0 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, s0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2775,19 +2777,19 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset fs0, -32 -; CHECK-NOV-NEXT: fmv.s fs0, fa0 -; CHECK-NOV-NEXT: fmv.s fa0, fa1 +; CHECK-NOV-NEXT: fmv.s fs0, fa1 ; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s0, a0 ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixunssfti -; CHECK-NOV-NEXT: snez a2, s1 ; CHECK-NOV-NEXT: snez a1, a1 +; CHECK-NOV-NEXT: snez a2, s1 +; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a2, a2, s0 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a0, a1, a0 -; CHECK-NOV-NEXT: addi a1, a2, -1 -; CHECK-NOV-NEXT: and a1, a1, s0 +; CHECK-NOV-NEXT: and a1, a1, a0 +; CHECK-NOV-NEXT: mv a0, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -2812,25 +2814,25 @@ define <2 x i64> @utest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vs1r.v v8, (a0) # Unknown-size Folded Spill ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma -; CHECK-V-NEXT: vfmv.f.s fa0, v8 +; CHECK-V-NEXT: vslidedown.vi v9, v8, 1 +; CHECK-V-NEXT: vfmv.f.s fa0, v9 ; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s0, a0 ; CHECK-V-NEXT: mv s1, a1 ; CHECK-V-NEXT: vsetivli zero, 1, e32, mf2, ta, ma ; CHECK-V-NEXT: addi a0, sp, 32 ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload -; CHECK-V-NEXT: vslidedown.vi v8, v8, 1 ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixunssfti -; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: snez a1, a1 -; CHECK-V-NEXT: addi a1, a1, -1 -; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: snez a2, s1 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s0 +; CHECK-V-NEXT: addi a1, a1, -1 +; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v8, a2 -; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a2 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: csrr a0, vlenb ; CHECK-V-NEXT: slli a0, a0, 1 @@ -2872,32 +2874,32 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB23_2: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: slti a3, a1, 1 +; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB23_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB23_4: # %entry +; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB23_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB23_8 ; CHECK-NOV-NEXT: .LBB23_6: -; CHECK-NOV-NEXT: snez a2, a0 +; CHECK-NOV-NEXT: snez a0, a4 ; CHECK-NOV-NEXT: j .LBB23_9 ; CHECK-NOV-NEXT: .LBB23_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB23_6 ; CHECK-NOV-NEXT: .LBB23_8: # %entry -; CHECK-NOV-NEXT: sgtz a2, a2 +; CHECK-NOV-NEXT: sgtz a0, a2 ; CHECK-NOV-NEXT: .LBB23_9: # %entry -; CHECK-NOV-NEXT: neg a2, a2 -; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: neg a0, a0 +; CHECK-NOV-NEXT: and a0, a0, a4 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -2939,15 +2941,15 @@ define <2 x i64> @ustest_f32i64(<2 x float> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB23_2: # %entry -; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: slti a4, a1, 1 +; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: blez a1, .LBB23_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB23_4: # %entry +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB23_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -3002,8 +3004,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset s2, -32 -; CHECK-NOV-NEXT: mv s2, a0 -; CHECK-NOV-NEXT: fmv.w.x fa0, a1 +; CHECK-NOV-NEXT: mv s2, a1 +; CHECK-NOV-NEXT: fmv.w.x fa0, a0 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti ; CHECK-NOV-NEXT: mv s0, a0 @@ -3011,58 +3013,60 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: li a2, -1 -; CHECK-NOV-NEXT: srli a3, a2, 1 -; CHECK-NOV-NEXT: beqz s1, .LBB24_3 +; CHECK-NOV-NEXT: mv a2, a0 +; CHECK-NOV-NEXT: li a0, -1 +; CHECK-NOV-NEXT: srli a3, a0, 1 +; CHECK-NOV-NEXT: beqz a1, .LBB24_3 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 0 -; CHECK-NOV-NEXT: bnez a1, .LBB24_4 +; CHECK-NOV-NEXT: slti a4, a1, 0 +; CHECK-NOV-NEXT: bnez s1, .LBB24_4 ; CHECK-NOV-NEXT: .LBB24_2: -; CHECK-NOV-NEXT: sltu a5, a0, a3 +; CHECK-NOV-NEXT: sltu a5, s0, a3 ; CHECK-NOV-NEXT: beqz a5, .LBB24_5 ; CHECK-NOV-NEXT: j .LBB24_6 ; CHECK-NOV-NEXT: .LBB24_3: -; CHECK-NOV-NEXT: sltu a4, s0, a3 -; CHECK-NOV-NEXT: beqz a1, .LBB24_2 +; CHECK-NOV-NEXT: sltu a4, a2, a3 +; CHECK-NOV-NEXT: beqz s1, .LBB24_2 ; CHECK-NOV-NEXT: .LBB24_4: # %entry -; CHECK-NOV-NEXT: slti a5, a1, 0 +; CHECK-NOV-NEXT: slti a5, s1, 0 ; CHECK-NOV-NEXT: bnez a5, .LBB24_6 ; CHECK-NOV-NEXT: .LBB24_5: # %entry -; CHECK-NOV-NEXT: mv a0, a3 +; CHECK-NOV-NEXT: mv s0, a3 ; CHECK-NOV-NEXT: .LBB24_6: # %entry ; CHECK-NOV-NEXT: neg a6, a5 ; CHECK-NOV-NEXT: neg a5, a4 -; CHECK-NOV-NEXT: and a5, a5, s1 +; CHECK-NOV-NEXT: and a5, a5, a1 ; CHECK-NOV-NEXT: bnez a4, .LBB24_8 ; CHECK-NOV-NEXT: # %bb.7: # %entry -; CHECK-NOV-NEXT: mv s0, a3 +; CHECK-NOV-NEXT: mv a2, a3 ; CHECK-NOV-NEXT: .LBB24_8: # %entry -; CHECK-NOV-NEXT: and a4, a6, a1 -; CHECK-NOV-NEXT: slli a1, a2, 63 -; CHECK-NOV-NEXT: beq a5, a2, .LBB24_11 +; CHECK-NOV-NEXT: and a4, a6, s1 +; CHECK-NOV-NEXT: slli a1, a0, 63 +; CHECK-NOV-NEXT: beq a5, a0, .LBB24_11 ; CHECK-NOV-NEXT: # %bb.9: # %entry ; CHECK-NOV-NEXT: slti a3, a5, 0 ; CHECK-NOV-NEXT: xori a3, a3, 1 -; CHECK-NOV-NEXT: bne a4, a2, .LBB24_12 +; CHECK-NOV-NEXT: bne a4, a0, .LBB24_12 ; CHECK-NOV-NEXT: .LBB24_10: -; CHECK-NOV-NEXT: sltu a2, a1, a0 -; CHECK-NOV-NEXT: beqz a2, .LBB24_13 +; CHECK-NOV-NEXT: sltu a0, a1, s0 +; CHECK-NOV-NEXT: beqz a0, .LBB24_13 ; CHECK-NOV-NEXT: j .LBB24_14 ; CHECK-NOV-NEXT: .LBB24_11: -; CHECK-NOV-NEXT: sltu a3, a1, s0 -; CHECK-NOV-NEXT: beq a4, a2, .LBB24_10 +; CHECK-NOV-NEXT: sltu a3, a1, a2 +; CHECK-NOV-NEXT: beq a4, a0, .LBB24_10 ; CHECK-NOV-NEXT: .LBB24_12: # %entry -; CHECK-NOV-NEXT: slti a2, a4, 0 -; CHECK-NOV-NEXT: xori a2, a2, 1 -; CHECK-NOV-NEXT: bnez a2, .LBB24_14 +; CHECK-NOV-NEXT: slti a0, a4, 0 +; CHECK-NOV-NEXT: xori a0, a0, 1 +; CHECK-NOV-NEXT: bnez a0, .LBB24_14 ; CHECK-NOV-NEXT: .LBB24_13: # %entry -; CHECK-NOV-NEXT: mv a0, a1 +; CHECK-NOV-NEXT: mv s0, a1 ; CHECK-NOV-NEXT: .LBB24_14: # %entry ; CHECK-NOV-NEXT: bnez a3, .LBB24_16 ; CHECK-NOV-NEXT: # %bb.15: # %entry -; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: .LBB24_16: # %entry -; CHECK-NOV-NEXT: mv a1, s0 +; CHECK-NOV-NEXT: mv a0, s0 +; CHECK-NOV-NEXT: mv a1, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -3082,8 +3086,8 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s2, -32 -; CHECK-V-NEXT: mv s2, a0 -; CHECK-V-NEXT: fmv.w.x fa0, a1 +; CHECK-V-NEXT: mv s2, a1 +; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: mv s0, a0 @@ -3093,31 +3097,31 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: call __fixsfti ; CHECK-V-NEXT: li a2, -1 ; CHECK-V-NEXT: srli a3, a2, 1 -; CHECK-V-NEXT: beqz s1, .LBB24_3 +; CHECK-V-NEXT: beqz a1, .LBB24_3 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: slti a4, s1, 0 -; CHECK-V-NEXT: bnez a1, .LBB24_4 +; CHECK-V-NEXT: slti a4, a1, 0 +; CHECK-V-NEXT: bnez s1, .LBB24_4 ; CHECK-V-NEXT: .LBB24_2: -; CHECK-V-NEXT: sltu a5, a0, a3 +; CHECK-V-NEXT: sltu a5, s0, a3 ; CHECK-V-NEXT: beqz a5, .LBB24_5 ; CHECK-V-NEXT: j .LBB24_6 ; CHECK-V-NEXT: .LBB24_3: -; CHECK-V-NEXT: sltu a4, s0, a3 -; CHECK-V-NEXT: beqz a1, .LBB24_2 +; CHECK-V-NEXT: sltu a4, a0, a3 +; CHECK-V-NEXT: beqz s1, .LBB24_2 ; CHECK-V-NEXT: .LBB24_4: # %entry -; CHECK-V-NEXT: slti a5, a1, 0 +; CHECK-V-NEXT: slti a5, s1, 0 ; CHECK-V-NEXT: bnez a5, .LBB24_6 ; CHECK-V-NEXT: .LBB24_5: # %entry -; CHECK-V-NEXT: mv a0, a3 +; CHECK-V-NEXT: mv s0, a3 ; CHECK-V-NEXT: .LBB24_6: # %entry ; CHECK-V-NEXT: neg a6, a5 ; CHECK-V-NEXT: neg a5, a4 -; CHECK-V-NEXT: and a5, a5, s1 +; CHECK-V-NEXT: and a5, a5, a1 ; CHECK-V-NEXT: bnez a4, .LBB24_8 ; CHECK-V-NEXT: # %bb.7: # %entry -; CHECK-V-NEXT: mv s0, a3 +; CHECK-V-NEXT: mv a0, a3 ; CHECK-V-NEXT: .LBB24_8: # %entry -; CHECK-V-NEXT: and a4, a6, a1 +; CHECK-V-NEXT: and a4, a6, s1 ; CHECK-V-NEXT: slli a1, a2, 63 ; CHECK-V-NEXT: beq a5, a2, .LBB24_11 ; CHECK-V-NEXT: # %bb.9: # %entry @@ -3125,26 +3129,26 @@ define <2 x i64> @stest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: xori a3, a3, 1 ; CHECK-V-NEXT: bne a4, a2, .LBB24_12 ; CHECK-V-NEXT: .LBB24_10: -; CHECK-V-NEXT: sltu a2, a1, a0 +; CHECK-V-NEXT: sltu a2, a1, s0 ; CHECK-V-NEXT: beqz a2, .LBB24_13 ; CHECK-V-NEXT: j .LBB24_14 ; CHECK-V-NEXT: .LBB24_11: -; CHECK-V-NEXT: sltu a3, a1, s0 +; CHECK-V-NEXT: sltu a3, a1, a0 ; CHECK-V-NEXT: beq a4, a2, .LBB24_10 ; CHECK-V-NEXT: .LBB24_12: # %entry ; CHECK-V-NEXT: slti a2, a4, 0 ; CHECK-V-NEXT: xori a2, a2, 1 ; CHECK-V-NEXT: bnez a2, .LBB24_14 ; CHECK-V-NEXT: .LBB24_13: # %entry -; CHECK-V-NEXT: mv a0, a1 +; CHECK-V-NEXT: mv s0, a1 ; CHECK-V-NEXT: .LBB24_14: # %entry ; CHECK-V-NEXT: bnez a3, .LBB24_16 ; CHECK-V-NEXT: # %bb.15: # %entry -; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: mv a0, a1 ; CHECK-V-NEXT: .LBB24_16: # %entry ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v9, s0 -; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, s0 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -3175,8 +3179,8 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: .cfi_offset s0, -16 ; CHECK-NOV-NEXT: .cfi_offset s1, -24 ; CHECK-NOV-NEXT: .cfi_offset s2, -32 -; CHECK-NOV-NEXT: mv s0, a0 -; CHECK-NOV-NEXT: fmv.w.x fa0, a1 +; CHECK-NOV-NEXT: mv s0, a1 +; CHECK-NOV-NEXT: fmv.w.x fa0, a0 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixunssfti ; CHECK-NOV-NEXT: mv s1, a0 @@ -3184,12 +3188,13 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s0 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixunssfti -; CHECK-NOV-NEXT: snez a2, s2 ; CHECK-NOV-NEXT: snez a1, a1 +; CHECK-NOV-NEXT: snez a2, s2 +; CHECK-NOV-NEXT: addi a2, a2, -1 +; CHECK-NOV-NEXT: and a2, a2, s1 ; CHECK-NOV-NEXT: addi a1, a1, -1 -; CHECK-NOV-NEXT: and a0, a1, a0 -; CHECK-NOV-NEXT: addi a1, a2, -1 -; CHECK-NOV-NEXT: and a1, a1, s1 +; CHECK-NOV-NEXT: and a1, a1, a0 +; CHECK-NOV-NEXT: mv a0, a2 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s1, 8(sp) # 8-byte Folded Reload @@ -3209,8 +3214,8 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: .cfi_offset s0, -16 ; CHECK-V-NEXT: .cfi_offset s1, -24 ; CHECK-V-NEXT: .cfi_offset s2, -32 -; CHECK-V-NEXT: mv s0, a0 -; CHECK-V-NEXT: fmv.w.x fa0, a1 +; CHECK-V-NEXT: mv s0, a1 +; CHECK-V-NEXT: fmv.w.x fa0, a0 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixunssfti ; CHECK-V-NEXT: mv s1, a0 @@ -3218,15 +3223,15 @@ define <2 x i64> @utesth_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: fmv.w.x fa0, s0 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixunssfti -; CHECK-V-NEXT: snez a2, s2 ; CHECK-V-NEXT: snez a1, a1 -; CHECK-V-NEXT: addi a1, a1, -1 -; CHECK-V-NEXT: and a0, a1, a0 +; CHECK-V-NEXT: snez a2, s2 ; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a2, a2, s1 +; CHECK-V-NEXT: addi a1, a1, -1 +; CHECK-V-NEXT: and a0, a1, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma -; CHECK-V-NEXT: vmv.s.x v9, a2 -; CHECK-V-NEXT: vmv.s.x v8, a0 +; CHECK-V-NEXT: vmv.s.x v9, a0 +; CHECK-V-NEXT: vmv.s.x v8, a2 ; CHECK-V-NEXT: vslideup.vi v8, v9, 1 ; CHECK-V-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-V-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -3269,32 +3274,32 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-NOV-NEXT: # %bb.1: # %entry ; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB26_2: # %entry -; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: slti a3, a1, 1 +; CHECK-NOV-NEXT: slti a4, s1, 1 ; CHECK-NOV-NEXT: blez a1, .LBB26_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry ; CHECK-NOV-NEXT: li a1, 1 ; CHECK-NOV-NEXT: .LBB26_4: # %entry +; CHECK-NOV-NEXT: neg a4, a4 ; CHECK-NOV-NEXT: neg a3, a3 ; CHECK-NOV-NEXT: and a3, a3, a0 -; CHECK-NOV-NEXT: neg a0, a4 ; CHECK-NOV-NEXT: beqz a1, .LBB26_7 ; CHECK-NOV-NEXT: # %bb.5: # %entry ; CHECK-NOV-NEXT: sgtz a1, a1 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: bnez a2, .LBB26_8 ; CHECK-NOV-NEXT: .LBB26_6: -; CHECK-NOV-NEXT: snez a2, a0 +; CHECK-NOV-NEXT: snez a0, a4 ; CHECK-NOV-NEXT: j .LBB26_9 ; CHECK-NOV-NEXT: .LBB26_7: ; CHECK-NOV-NEXT: snez a1, a3 -; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: and a4, a4, s0 ; CHECK-NOV-NEXT: beqz a2, .LBB26_6 ; CHECK-NOV-NEXT: .LBB26_8: # %entry -; CHECK-NOV-NEXT: sgtz a2, a2 +; CHECK-NOV-NEXT: sgtz a0, a2 ; CHECK-NOV-NEXT: .LBB26_9: # %entry -; CHECK-NOV-NEXT: neg a2, a2 -; CHECK-NOV-NEXT: and a0, a2, a0 +; CHECK-NOV-NEXT: neg a0, a0 +; CHECK-NOV-NEXT: and a0, a0, a4 ; CHECK-NOV-NEXT: neg a1, a1 ; CHECK-NOV-NEXT: and a1, a1, a3 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload @@ -3330,15 +3335,15 @@ define <2 x i64> @ustest_f16i64(<2 x half> %x) { ; CHECK-V-NEXT: # %bb.1: # %entry ; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB26_2: # %entry -; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: slti a4, a1, 1 +; CHECK-V-NEXT: slti a3, s1, 1 ; CHECK-V-NEXT: blez a1, .LBB26_4 ; CHECK-V-NEXT: # %bb.3: # %entry ; CHECK-V-NEXT: li a1, 1 ; CHECK-V-NEXT: .LBB26_4: # %entry +; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: neg a4, a4 ; CHECK-V-NEXT: and a0, a4, a0 -; CHECK-V-NEXT: neg a3, a3 ; CHECK-V-NEXT: beqz a1, .LBB26_7 ; CHECK-V-NEXT: # %bb.5: # %entry ; CHECK-V-NEXT: sgtz a1, a1 @@ -5811,15 +5816,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.d fa0, fs0 ; CHECK-NOV-NEXT: call __fixdfti -; CHECK-NOV-NEXT: mv a2, s1 -; CHECK-NOV-NEXT: mv a3, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB47_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB47_2: # %entry -; CHECK-NOV-NEXT: blez a2, .LBB47_4 +; CHECK-NOV-NEXT: mv a3, s1 +; CHECK-NOV-NEXT: blez s1, .LBB47_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB47_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -5827,11 +5832,11 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: slti a3, a3, 0 +; CHECK-NOV-NEXT: addi a3, a3, -1 +; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a0, a2, a0 -; CHECK-NOV-NEXT: slti a2, a3, 0 -; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -5867,15 +5872,15 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixdfti -; CHECK-V-NEXT: mv a2, s1 -; CHECK-V-NEXT: mv a3, a1 +; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB47_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB47_2: # %entry -; CHECK-V-NEXT: blez a2, .LBB47_4 +; CHECK-V-NEXT: mv a3, s1 +; CHECK-V-NEXT: blez s1, .LBB47_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB47_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -5883,11 +5888,11 @@ define <2 x i64> @ustest_f64i64_mm(<2 x double> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 +; CHECK-V-NEXT: slti a3, a3, 0 +; CHECK-V-NEXT: addi a3, a3, -1 +; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a1, a2, a1 -; CHECK-V-NEXT: slti a2, a3, 0 -; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -6197,15 +6202,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: mv s1, a1 ; CHECK-NOV-NEXT: fmv.s fa0, fs0 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, s1 -; CHECK-NOV-NEXT: mv a3, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB50_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB50_2: # %entry -; CHECK-NOV-NEXT: blez a2, .LBB50_4 +; CHECK-NOV-NEXT: mv a3, s1 +; CHECK-NOV-NEXT: blez s1, .LBB50_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB50_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -6213,11 +6218,11 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: slti a3, a3, 0 +; CHECK-NOV-NEXT: addi a3, a3, -1 +; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a0, a2, a0 -; CHECK-NOV-NEXT: slti a2, a3, 0 -; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -6253,15 +6258,15 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: vl1r.v v8, (a0) # Unknown-size Folded Reload ; CHECK-V-NEXT: vfmv.f.s fa0, v8 ; CHECK-V-NEXT: call __fixsfti -; CHECK-V-NEXT: mv a2, s1 -; CHECK-V-NEXT: mv a3, a1 +; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB50_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB50_2: # %entry -; CHECK-V-NEXT: blez a2, .LBB50_4 +; CHECK-V-NEXT: mv a3, s1 +; CHECK-V-NEXT: blez s1, .LBB50_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB50_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -6269,11 +6274,11 @@ define <2 x i64> @ustest_f32i64_mm(<2 x float> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 +; CHECK-V-NEXT: slti a3, a3, 0 +; CHECK-V-NEXT: addi a3, a3, -1 +; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a1, a2, a1 -; CHECK-V-NEXT: slti a2, a3, 0 -; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v8, a0 @@ -6575,15 +6580,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: fmv.w.x fa0, s2 ; CHECK-NOV-NEXT: call __extendhfsf2 ; CHECK-NOV-NEXT: call __fixsfti -; CHECK-NOV-NEXT: mv a2, s1 -; CHECK-NOV-NEXT: mv a3, a1 +; CHECK-NOV-NEXT: mv a2, a1 ; CHECK-NOV-NEXT: blez a1, .LBB53_2 ; CHECK-NOV-NEXT: # %bb.1: # %entry -; CHECK-NOV-NEXT: li a3, 1 +; CHECK-NOV-NEXT: li a2, 1 ; CHECK-NOV-NEXT: .LBB53_2: # %entry -; CHECK-NOV-NEXT: blez a2, .LBB53_4 +; CHECK-NOV-NEXT: mv a3, s1 +; CHECK-NOV-NEXT: blez s1, .LBB53_4 ; CHECK-NOV-NEXT: # %bb.3: # %entry -; CHECK-NOV-NEXT: li a2, 1 +; CHECK-NOV-NEXT: li a3, 1 ; CHECK-NOV-NEXT: .LBB53_4: # %entry ; CHECK-NOV-NEXT: slti a1, a1, 1 ; CHECK-NOV-NEXT: neg a1, a1 @@ -6591,11 +6596,11 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-NOV-NEXT: slti a0, s1, 1 ; CHECK-NOV-NEXT: neg a0, a0 ; CHECK-NOV-NEXT: and a0, a0, s0 +; CHECK-NOV-NEXT: slti a3, a3, 0 +; CHECK-NOV-NEXT: addi a3, a3, -1 +; CHECK-NOV-NEXT: and a0, a3, a0 ; CHECK-NOV-NEXT: slti a2, a2, 0 ; CHECK-NOV-NEXT: addi a2, a2, -1 -; CHECK-NOV-NEXT: and a0, a2, a0 -; CHECK-NOV-NEXT: slti a2, a3, 0 -; CHECK-NOV-NEXT: addi a2, a2, -1 ; CHECK-NOV-NEXT: and a1, a2, a1 ; CHECK-NOV-NEXT: ld ra, 24(sp) # 8-byte Folded Reload ; CHECK-NOV-NEXT: ld s0, 16(sp) # 8-byte Folded Reload @@ -6625,15 +6630,15 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: fmv.w.x fa0, s2 ; CHECK-V-NEXT: call __extendhfsf2 ; CHECK-V-NEXT: call __fixsfti -; CHECK-V-NEXT: mv a2, s1 -; CHECK-V-NEXT: mv a3, a1 +; CHECK-V-NEXT: mv a2, a1 ; CHECK-V-NEXT: blez a1, .LBB53_2 ; CHECK-V-NEXT: # %bb.1: # %entry -; CHECK-V-NEXT: li a3, 1 +; CHECK-V-NEXT: li a2, 1 ; CHECK-V-NEXT: .LBB53_2: # %entry -; CHECK-V-NEXT: blez a2, .LBB53_4 +; CHECK-V-NEXT: mv a3, s1 +; CHECK-V-NEXT: blez s1, .LBB53_4 ; CHECK-V-NEXT: # %bb.3: # %entry -; CHECK-V-NEXT: li a2, 1 +; CHECK-V-NEXT: li a3, 1 ; CHECK-V-NEXT: .LBB53_4: # %entry ; CHECK-V-NEXT: slti a1, a1, 1 ; CHECK-V-NEXT: neg a1, a1 @@ -6641,11 +6646,11 @@ define <2 x i64> @ustest_f16i64_mm(<2 x half> %x) { ; CHECK-V-NEXT: slti a1, s1, 1 ; CHECK-V-NEXT: neg a1, a1 ; CHECK-V-NEXT: and a1, a1, s0 +; CHECK-V-NEXT: slti a3, a3, 0 +; CHECK-V-NEXT: addi a3, a3, -1 +; CHECK-V-NEXT: and a1, a3, a1 ; CHECK-V-NEXT: slti a2, a2, 0 ; CHECK-V-NEXT: addi a2, a2, -1 -; CHECK-V-NEXT: and a1, a2, a1 -; CHECK-V-NEXT: slti a2, a3, 0 -; CHECK-V-NEXT: addi a2, a2, -1 ; CHECK-V-NEXT: and a0, a2, a0 ; CHECK-V-NEXT: vsetivli zero, 2, e64, m1, ta, ma ; CHECK-V-NEXT: vmv.s.x v9, a0 diff --git a/llvm/test/CodeGen/X86/abdu-vector-128.ll b/llvm/test/CodeGen/X86/abdu-vector-128.ll index dd180b67e492..0c33e8973c2d 100644 --- a/llvm/test/CodeGen/X86/abdu-vector-128.ll +++ b/llvm/test/CodeGen/X86/abdu-vector-128.ll @@ -715,43 +715,41 @@ define <2 x i64> @abd_cmp_v2i64_multiuse_cmp(<2 x i64> %a, <2 x i64> %b) nounwin ; ; SSE42-LABEL: abd_cmp_v2i64_multiuse_cmp: ; SSE42: # %bb.0: -; SSE42-NEXT: movdqa {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: movdqa %xmm0, %xmm2 +; SSE42-NEXT: psubq %xmm1, %xmm2 ; SSE42-NEXT: movdqa %xmm1, %xmm3 -; SSE42-NEXT: pxor %xmm2, %xmm3 -; SSE42-NEXT: pxor %xmm0, %xmm2 -; SSE42-NEXT: pcmpgtq %xmm3, %xmm2 -; SSE42-NEXT: movdqa %xmm0, %xmm3 -; SSE42-NEXT: psubq %xmm1, %xmm3 -; SSE42-NEXT: psubq %xmm0, %xmm1 -; SSE42-NEXT: movdqa %xmm2, %xmm0 -; SSE42-NEXT: blendvpd %xmm0, %xmm3, %xmm1 -; SSE42-NEXT: paddq %xmm1, %xmm2 -; SSE42-NEXT: movdqa %xmm2, %xmm0 +; SSE42-NEXT: psubq %xmm0, %xmm3 +; SSE42-NEXT: movdqa {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] +; SSE42-NEXT: pxor %xmm4, %xmm1 +; SSE42-NEXT: pxor %xmm4, %xmm0 +; SSE42-NEXT: pcmpgtq %xmm1, %xmm0 +; SSE42-NEXT: blendvpd %xmm0, %xmm2, %xmm3 +; SSE42-NEXT: paddq %xmm3, %xmm0 ; SSE42-NEXT: retq ; ; AVX1-LABEL: abd_cmp_v2i64_multiuse_cmp: ; AVX1: # %bb.0: -; AVX1-NEXT: vmovddup {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] -; AVX1-NEXT: # xmm2 = mem[0,0] -; AVX1-NEXT: vpxor %xmm2, %xmm1, %xmm3 -; AVX1-NEXT: vpxor %xmm2, %xmm0, %xmm2 -; AVX1-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm3 -; AVX1-NEXT: vpsubq %xmm0, %xmm1, %xmm0 -; AVX1-NEXT: vblendvpd %xmm2, %xmm3, %xmm0, %xmm0 -; AVX1-NEXT: vpaddq %xmm0, %xmm2, %xmm0 +; AVX1-NEXT: vpsubq %xmm1, %xmm0, %xmm2 +; AVX1-NEXT: vpsubq %xmm0, %xmm1, %xmm3 +; AVX1-NEXT: vmovddup {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] +; AVX1-NEXT: # xmm4 = mem[0,0] +; AVX1-NEXT: vpxor %xmm4, %xmm1, %xmm1 +; AVX1-NEXT: vpxor %xmm4, %xmm0, %xmm0 +; AVX1-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX1-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm1 +; AVX1-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: retq ; ; AVX2-LABEL: abd_cmp_v2i64_multiuse_cmp: ; AVX2: # %bb.0: -; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm2 = [9223372036854775808,9223372036854775808] -; AVX2-NEXT: vpxor %xmm2, %xmm1, %xmm3 -; AVX2-NEXT: vpxor %xmm2, %xmm0, %xmm2 -; AVX2-NEXT: vpcmpgtq %xmm3, %xmm2, %xmm2 -; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm3 -; AVX2-NEXT: vpsubq %xmm0, %xmm1, %xmm0 -; AVX2-NEXT: vblendvpd %xmm2, %xmm3, %xmm0, %xmm0 -; AVX2-NEXT: vpaddq %xmm0, %xmm2, %xmm0 +; AVX2-NEXT: vpsubq %xmm1, %xmm0, %xmm2 +; AVX2-NEXT: vpsubq %xmm0, %xmm1, %xmm3 +; AVX2-NEXT: vpbroadcastq {{.*#+}} xmm4 = [9223372036854775808,9223372036854775808] +; AVX2-NEXT: vpxor %xmm4, %xmm1, %xmm1 +; AVX2-NEXT: vpxor %xmm4, %xmm0, %xmm0 +; AVX2-NEXT: vpcmpgtq %xmm1, %xmm0, %xmm0 +; AVX2-NEXT: vblendvpd %xmm0, %xmm2, %xmm3, %xmm1 +; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 ; AVX2-NEXT: retq ; ; AVX512-LABEL: abd_cmp_v2i64_multiuse_cmp: diff --git a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll index 017024c173c3..b2cb2c3e04b3 100644 --- a/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll +++ b/llvm/test/CodeGen/X86/apx/kmov-postrapseudos.ll @@ -52,10 +52,7 @@ alloca_21: define i32 @kmovrk_1(<4 x ptr> %arg) { ; AVX512-LABEL: kmovrk_1: ; AVX512: # %bb.0: # %bb -; AVX512-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512-NEXT: vptestmq %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc0] -; AVX512-NEXT: kmovw %k0, %eax # EVEX TO VEX Compression encoding: [0xc5,0xf8,0x93,0xc0] -; AVX512-NEXT: testb $15, %al # encoding: [0xa8,0x0f] +; AVX512-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] ; AVX512-NEXT: jne .LBB2_1 # encoding: [0x75,A] ; AVX512-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 ; AVX512-NEXT: # %bb.2: # %bb3 @@ -66,10 +63,7 @@ define i32 @kmovrk_1(<4 x ptr> %arg) { ; ; AVX512BW-LABEL: kmovrk_1: ; AVX512BW: # %bb.0: # %bb -; AVX512BW-NEXT: # kill: def $ymm0 killed $ymm0 def $zmm0 -; AVX512BW-NEXT: vptestmq %zmm0, %zmm0, %k0 # encoding: [0x62,0xf2,0xfd,0x48,0x27,0xc0] -; AVX512BW-NEXT: kmovd %k0, %eax # EVEX TO VEX Compression encoding: [0xc5,0xfb,0x93,0xc0] -; AVX512BW-NEXT: testb $15, %al # encoding: [0xa8,0x0f] +; AVX512BW-NEXT: vptest %ymm0, %ymm0 # encoding: [0xc4,0xe2,0x7d,0x17,0xc0] ; AVX512BW-NEXT: jne .LBB2_1 # encoding: [0x75,A] ; AVX512BW-NEXT: # fixup A - offset: 1, value: .LBB2_1-1, kind: FK_PCRel_1 ; AVX512BW-NEXT: # %bb.2: # %bb3 diff --git a/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll b/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll index 13d1265a249d..7e48b3719cf0 100644 --- a/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll +++ b/llvm/test/CodeGen/X86/avx512-broadcast-arith.ll @@ -30,13 +30,13 @@ define <64 x i8> @add_v64i8_broadcasts(<64 x i8> %a0, i64 %a1, i8 %a2) { ; AVX512F-NEXT: vinserti128 $1, %xmm4, %ymm3, %ymm3 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm3, %zmm2 ; AVX512F-NEXT: vpternlogq $216, %zmm2, %zmm1, %zmm0 -; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm3 -; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm0 +; AVX512F-NEXT: vextracti64x4 $1, %zmm0, %ymm3 +; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0 -; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm3, %zmm4 +; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm4 +; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm3 ; AVX512F-NEXT: vpaddb %ymm1, %ymm0, %ymm0 -; AVX512F-NEXT: vpaddb %ymm1, %ymm3, %ymm1 -; AVX512F-NEXT: vinserti64x4 $1, %ymm0, %zmm1, %zmm0 +; AVX512F-NEXT: vinserti64x4 $1, %ymm3, %zmm0, %zmm0 ; AVX512F-NEXT: vpternlogq $226, %zmm4, %zmm2, %zmm0 ; AVX512F-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/combine-mul.ll b/llvm/test/CodeGen/X86/combine-mul.ll index 8d2bb77a9e1a..5d7bf4a2c978 100644 --- a/llvm/test/CodeGen/X86/combine-mul.ll +++ b/llvm/test/CodeGen/X86/combine-mul.ll @@ -80,13 +80,13 @@ define <4 x i32> @combine_vec_mul_pow2b(<4 x i32> %x) { define <4 x i64> @combine_vec_mul_pow2c(<4 x i64> %x) { ; SSE-LABEL: combine_vec_mul_pow2c: ; SSE: # %bb.0: +; SSE-NEXT: movdqa %xmm0, %xmm2 +; SSE-NEXT: paddq %xmm0, %xmm2 +; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: movdqa %xmm1, %xmm2 ; SSE-NEXT: psllq $4, %xmm2 ; SSE-NEXT: psllq $2, %xmm1 ; SSE-NEXT: pblendw {{.*#+}} xmm1 = xmm1[0,1,2,3],xmm2[4,5,6,7] -; SSE-NEXT: movdqa %xmm0, %xmm2 -; SSE-NEXT: paddq %xmm0, %xmm2 -; SSE-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm2[4,5,6,7] ; SSE-NEXT: retq ; ; AVX-LABEL: combine_vec_mul_pow2c: @@ -399,14 +399,12 @@ define i64 @combine_mul_self_demandedbits(i64 %x) { ; SSE: # %bb.0: ; SSE-NEXT: movq %rdi, %rax ; SSE-NEXT: imulq %rdi, %rax -; SSE-NEXT: andq $-3, %rax ; SSE-NEXT: retq ; ; AVX-LABEL: combine_mul_self_demandedbits: ; AVX: # %bb.0: ; AVX-NEXT: movq %rdi, %rax ; AVX-NEXT: imulq %rdi, %rax -; AVX-NEXT: andq $-3, %rax ; AVX-NEXT: retq %1 = mul i64 %x, %x %2 = and i64 %1, -3 diff --git a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll index e12ca56023a7..33cc8e96f663 100644 --- a/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll +++ b/llvm/test/CodeGen/X86/div-rem-pair-recomposition-signed.ll @@ -182,101 +182,101 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: sarl $31, %eax -; X86-NEXT: movl %edx, %edi -; X86-NEXT: sarl $31, %edi +; X86-NEXT: movl %edx, %ebx +; X86-NEXT: sarl $31, %ebx ; X86-NEXT: movl %eax, %esi ; X86-NEXT: xorl %ecx, %esi ; X86-NEXT: movl %esi, %ebp ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx -; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: movl %ecx, %edi ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl %eax, %esi ; X86-NEXT: xorl {{[0-9]+}}(%esp), %esi ; X86-NEXT: subl %eax, %esi -; X86-NEXT: movl %esi, (%esp) # 4-byte Spill +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %eax, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %eax, %edi +; X86-NEXT: movl %edi, (%esp) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ebp ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, %esi +; X86-NEXT: movl %ebx, %esi ; X86-NEXT: xorl %edx, %esi -; X86-NEXT: movl %edi, %edx +; X86-NEXT: movl %ebx, %edx ; X86-NEXT: xorl {{[0-9]+}}(%esp), %edx -; X86-NEXT: movl %edi, %ebx -; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebx -; X86-NEXT: movl %edi, %ebp +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: xorl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %ebx, %ebp ; X86-NEXT: xorl {{[0-9]+}}(%esp), %ebp -; X86-NEXT: subl %edi, %ebp -; X86-NEXT: sbbl %edi, %ebx -; X86-NEXT: sbbl %edi, %edx -; X86-NEXT: sbbl %edi, %esi -; X86-NEXT: xorl %eax, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, %eax +; X86-NEXT: subl %ebx, %ebp +; X86-NEXT: sbbl %ebx, %edi +; X86-NEXT: sbbl %ebx, %edx +; X86-NEXT: sbbl %ebx, %esi +; X86-NEXT: xorl %eax, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edi, %eax ; X86-NEXT: orl %esi, %eax ; X86-NEXT: movl %ebp, %ecx ; X86-NEXT: orl %edx, %ecx -; X86-NEXT: movl %edx, %edi +; X86-NEXT: movl %edx, %ebx ; X86-NEXT: orl %eax, %ecx ; X86-NEXT: sete %cl ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: movl (%esp), %edx # 4-byte Reload -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: orl (%esp), %edx # 4-byte Folded Reload ; X86-NEXT: orl %eax, %edx ; X86-NEXT: sete %al ; X86-NEXT: orb %cl, %al ; X86-NEXT: movb %al, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Spill ; X86-NEXT: bsrl %esi, %edx ; X86-NEXT: xorl $31, %edx -; X86-NEXT: bsrl %edi, %ecx +; X86-NEXT: bsrl %ebx, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx ; X86-NEXT: testl %esi, %esi ; X86-NEXT: cmovnel %edx, %ecx -; X86-NEXT: bsrl %ebx, %edx +; X86-NEXT: bsrl %edi, %edx ; X86-NEXT: xorl $31, %edx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: bsrl %ebp, %ebp ; X86-NEXT: xorl $31, %ebp ; X86-NEXT: addl $32, %ebp -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: testl %ebx, %ebx +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: testl %edi, %edi ; X86-NEXT: cmovnel %edx, %ebp ; X86-NEXT: addl $64, %ebp -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %edi +; X86-NEXT: orl %esi, %ebx ; X86-NEXT: cmovnel %ecx, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: bsrl %edi, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: bsrl %ebx, %edx ; X86-NEXT: xorl $31, %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: movl (%esp), %eax # 4-byte Reload ; X86-NEXT: bsrl %eax, %ecx ; X86-NEXT: xorl $31, %ecx ; X86-NEXT: addl $32, %ecx -; X86-NEXT: testl %edi, %edi +; X86-NEXT: testl %ebx, %ebx ; X86-NEXT: cmovnel %edx, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: bsrl %ebx, %esi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: bsrl %edi, %esi ; X86-NEXT: xorl $31, %esi -; X86-NEXT: bsrl (%esp), %edx # 4-byte Folded Reload +; X86-NEXT: bsrl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload ; X86-NEXT: xorl $31, %edx ; X86-NEXT: addl $32, %edx -; X86-NEXT: testl %ebx, %ebx +; X86-NEXT: testl %edi, %edi ; X86-NEXT: cmovnel %esi, %edx ; X86-NEXT: addl $64, %edx ; X86-NEXT: movl %eax, %esi -; X86-NEXT: orl %edi, %esi +; X86-NEXT: orl %ebx, %esi ; X86-NEXT: cmovnel %ecx, %edx ; X86-NEXT: xorl %esi, %esi ; X86-NEXT: subl %edx, %ebp -; X86-NEXT: movl $0, %ebx -; X86-NEXT: sbbl %ebx, %ebx +; X86-NEXT: movl $0, %edi +; X86-NEXT: sbbl %edi, %edi ; X86-NEXT: movl $0, %edx ; X86-NEXT: sbbl %edx, %edx ; X86-NEXT: movl $0, %eax @@ -284,40 +284,40 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: movl $127, %ecx ; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: cmpl %ebp, %ecx +; X86-NEXT: movl %edx, %ebp ; X86-NEXT: movl $0, %ecx -; X86-NEXT: sbbl %ebx, %ecx +; X86-NEXT: sbbl %edi, %ecx ; X86-NEXT: movl $0, %ecx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %edx, %ecx ; X86-NEXT: movl $0, %ecx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: setb %cl ; X86-NEXT: orb {{[-0-9]+}}(%e{{[sb]}}p), %cl # 1-byte Folded Reload -; X86-NEXT: cmovnel %esi, %edi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: movl %ebx, %edx ; X86-NEXT: cmovnel %esi, %edx +; X86-NEXT: movl (%esp), %ebx # 4-byte Reload +; X86-NEXT: cmovnel %esi, %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: cmovnel %esi, %eax -; X86-NEXT: cmovel (%esp), %esi # 4-byte Folded Reload -; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: cmovel {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; X86-NEXT: jne .LBB4_8 ; X86-NEXT: # %bb.1: # %_udiv-special-cases -; X86-NEXT: movl %ebx, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: xorl $127, %ebx -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload +; X86-NEXT: movl %edi, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: xorl $127, %edi +; X86-NEXT: orl %ebp, %edi ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: orl %ebx, %ecx +; X86-NEXT: orl %edi, %ecx ; X86-NEXT: je .LBB4_8 ; X86-NEXT: # %bb.2: # %udiv-bb1 -; X86-NEXT: movl (%esp), %eax # 4-byte Reload -; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) +; X86-NEXT: movl (%esp), %eax # 4-byte Reload +; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: movl %eax, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -332,234 +332,233 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: shrb $3, %al ; X86-NEXT: andb $15, %al ; X86-NEXT: negb %al -; X86-NEXT: movsbl %al, %ebx -; X86-NEXT: movl 144(%esp,%ebx), %edx -; X86-NEXT: movl 148(%esp,%ebx), %edi +; X86-NEXT: movsbl %al, %edi +; X86-NEXT: movl 144(%esp,%edi), %edx +; X86-NEXT: movl 148(%esp,%edi), %esi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %edx, %edi +; X86-NEXT: shldl %cl, %edx, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: shll %cl, %edx ; X86-NEXT: notb %cl -; X86-NEXT: movl 140(%esp,%ebx), %eax -; X86-NEXT: movl %eax, %esi -; X86-NEXT: shrl %esi -; X86-NEXT: shrl %cl, %esi -; X86-NEXT: orl %edx, %esi -; X86-NEXT: movl %esi, %edx -; X86-NEXT: movl 136(%esp,%ebx), %esi +; X86-NEXT: movl 140(%esp,%edi), %eax +; X86-NEXT: movl %eax, %ebx +; X86-NEXT: shrl %ebx +; X86-NEXT: shrl %cl, %ebx +; X86-NEXT: orl %edx, %ebx +; X86-NEXT: movl 136(%esp,%edi), %edx ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %esi, %eax -; X86-NEXT: shll %cl, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl %cl, %edx, %eax +; X86-NEXT: shll %cl, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: addl $1, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: adcl $0, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: adcl $0, %ebx -; X86-NEXT: adcl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill +; X86-NEXT: adcl $0, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: adcl $0, %edx ; X86-NEXT: jae .LBB4_3 ; X86-NEXT: # %bb.6: -; X86-NEXT: xorl %ebx, %ebx -; X86-NEXT: xorl %esi, %esi +; X86-NEXT: xorl %edi, %edi +; X86-NEXT: xorl %ecx, %ecx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload ; X86-NEXT: jmp .LBB4_7 ; X86-NEXT: .LBB4_3: # %udiv-preheader -; X86-NEXT: movl (%esp), %esi # 4-byte Reload -; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) +; X86-NEXT: movl (%esp), %esi # 4-byte Reload +; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: movb %bl, %ch +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movb %dl, %ch ; X86-NEXT: andb $7, %ch -; X86-NEXT: movb %bl, %cl +; X86-NEXT: movb %dl, %cl ; X86-NEXT: shrb $3, %cl ; X86-NEXT: andb $15, %cl -; X86-NEXT: movzbl %cl, %ebp -; X86-NEXT: movl 100(%esp,%ebp), %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl 96(%esp,%ebp), %ebx -; X86-NEXT: movl %ebp, %eax -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ebx, %edx -; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrdl %cl, %esi, %edx -; X86-NEXT: movl 88(%esp,%ebp), %ebp -; X86-NEXT: movl 92(%esp,%eax), %esi -; X86-NEXT: movl %esi, %eax -; X86-NEXT: shrl %cl, %eax -; X86-NEXT: notb %cl -; X86-NEXT: addl %ebx, %ebx -; X86-NEXT: shll %cl, %ebx -; X86-NEXT: orl %eax, %ebx +; X86-NEXT: movzbl %cl, %edx +; X86-NEXT: movl 100(%esp,%edx), %esi +; X86-NEXT: movl %esi, (%esp) # 4-byte Spill +; X86-NEXT: movl 96(%esp,%edx), %edi ; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edi, %ebp ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrl %cl, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: shrdl %cl, %esi, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: addl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 88(%esp,%edx), %ebx +; X86-NEXT: movl 92(%esp,%edx), %esi +; X86-NEXT: movl %esi, %edx +; X86-NEXT: shrl %cl, %edx +; X86-NEXT: notb %cl +; X86-NEXT: addl %edi, %edi +; X86-NEXT: shll %cl, %edi +; X86-NEXT: orl %edx, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movb %ch, %cl +; X86-NEXT: shrl %cl, (%esp) # 4-byte Folded Spill +; X86-NEXT: shrdl %cl, %esi, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: adcl $-1, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: xorl %esi, %esi +; X86-NEXT: addl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: adcl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: adcl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: adcl $-1, %ecx +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload ; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .LBB4_4: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: shldl $1, %edx, %ebx +; X86-NEXT: movl %ebp, %esi +; X86-NEXT: shldl $1, %ebp, (%esp) # 4-byte Folded Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Reload +; X86-NEXT: shldl $1, %ebp, %esi ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: shldl $1, %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill -; X86-NEXT: shldl $1, %ebp, %edx -; X86-NEXT: shldl $1, %edi, %ebp -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: shldl $1, %eax, %edi -; X86-NEXT: orl %esi, %edi -; X86-NEXT: movl %edi, (%esp) # 4-byte Spill -; X86-NEXT: movl %ecx, %edi +; X86-NEXT: shldl $1, %edx, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload +; X86-NEXT: shldl $1, %edi, %edx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: shldl $1, %ecx, %eax -; X86-NEXT: orl %esi, %eax -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: shldl $1, %ecx, %edi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: orl %ebx, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: shldl $1, %eax, %ecx -; X86-NEXT: orl %esi, %ecx +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: addl %eax, %eax -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: shldl $1, %ecx, %eax +; X86-NEXT: orl %ebx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: cmpl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload +; X86-NEXT: addl %ecx, %ecx +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl %edx, %ecx +; X86-NEXT: sbbl %ebp, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: sbbl %esi, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: sbbl %ebx, %ecx +; X86-NEXT: sbbl (%esp), %ecx # 4-byte Folded Reload ; X86-NEXT: sarl $31, %ecx ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: andl $1, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ecx, %esi -; X86-NEXT: andl %edi, %esi +; X86-NEXT: movl %ecx, %ebx +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload ; X86-NEXT: movl %ecx, %edi ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload ; X86-NEXT: movl %ecx, %eax ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload -; X86-NEXT: subl %ecx, %ebp -; X86-NEXT: sbbl %eax, %edx +; X86-NEXT: subl %ecx, %edx ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: sbbl %edi, %edx -; X86-NEXT: movl (%esp), %edi # 4-byte Reload -; X86-NEXT: sbbl %esi, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: sbbl %eax, %ebp +; X86-NEXT: movl %ebp, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %edi, %esi +; X86-NEXT: movl %esi, %ebp +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload +; X86-NEXT: sbbl %ebx, (%esp) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: addl $-1, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: adcl $-1, %eax +; X86-NEXT: adcl $-1, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: adcl $-1, %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: adcl $-1, %esi -; X86-NEXT: adcl $-1, %ebx -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %ebx, %eax -; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %edx, %edi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %esi, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: orl %eax, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: orl %esi, %edi +; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %ebx, %ecx +; X86-NEXT: orl %edi, %ecx ; X86-NEXT: jne .LBB4_4 ; X86-NEXT: # %bb.5: -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload ; X86-NEXT: .LBB4_7: # %udiv-loop-exit -; X86-NEXT: shldl $1, %edx, %edi -; X86-NEXT: orl %esi, %edi -; X86-NEXT: shldl $1, %eax, %edx -; X86-NEXT: orl %esi, %edx -; X86-NEXT: movl %esi, %ecx +; X86-NEXT: shldl $1, %ebx, %edx +; X86-NEXT: orl %ecx, %edx +; X86-NEXT: shldl $1, %eax, %ebx +; X86-NEXT: orl %ecx, %ebx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: shldl $1, %esi, %eax ; X86-NEXT: orl %ecx, %eax ; X86-NEXT: addl %esi, %esi -; X86-NEXT: orl %ebx, %esi +; X86-NEXT: orl %edi, %esi ; X86-NEXT: .LBB4_8: # %udiv-end ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: xorl %ecx, %edi ; X86-NEXT: xorl %ecx, %edx +; X86-NEXT: xorl %ecx, %ebx ; X86-NEXT: xorl %ecx, %eax ; X86-NEXT: xorl %ecx, %esi ; X86-NEXT: subl %ecx, %esi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: sbbl %ecx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %ecx, %ebx ; X86-NEXT: sbbl %ecx, %edx -; X86-NEXT: sbbl %ecx, %edi -; X86-NEXT: movl %edi, (%esp) # 4-byte Spill -; X86-NEXT: movl %esi, (%ebp) -; X86-NEXT: movl %eax, 4(%ebp) -; X86-NEXT: movl %edx, 8(%ebp) -; X86-NEXT: movl %edi, 12(%ebp) -; X86-NEXT: movl {{[0-9]+}}(%esp), %edi +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx +; X86-NEXT: movl %esi, (%ecx) +; X86-NEXT: movl %eax, 4(%ecx) +; X86-NEXT: movl %ebx, 8(%ecx) +; X86-NEXT: movl %edx, 12(%ecx) +; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: movl {{[0-9]+}}(%esp), %ebp +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: mull %ecx ; X86-NEXT: movl %edx, %ebx -; X86-NEXT: mull %edi -; X86-NEXT: movl %edx, %ecx ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl %esi, %eax -; X86-NEXT: mull %edi -; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edx, %edi -; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload -; X86-NEXT: adcl $0, %ecx +; X86-NEXT: mull %ecx +; X86-NEXT: movl %eax, (%esp) # 4-byte Spill +; X86-NEXT: movl %edx, %ecx +; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: adcl $0, %ebx ; X86-NEXT: movl %esi, %eax ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: mull %esi -; X86-NEXT: addl %edi, %eax +; X86-NEXT: addl %ecx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: adcl %ecx, %edx -; X86-NEXT: movl %edx, %edi +; X86-NEXT: adcl %ebx, %edx +; X86-NEXT: movl %edx, %ebx ; X86-NEXT: setb %cl ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload ; X86-NEXT: movl %esi, %eax ; X86-NEXT: mull {{[0-9]+}}(%esp) -; X86-NEXT: addl %edi, %eax +; X86-NEXT: addl %ebx, %eax ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movzbl %cl, %eax ; X86-NEXT: adcl %eax, %edx ; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax -; X86-NEXT: movl (%esp), %ecx # 4-byte Reload ; X86-NEXT: imull %eax, %ecx -; X86-NEXT: mull %ebx -; X86-NEXT: movl %eax, (%esp) # 4-byte Spill -; X86-NEXT: imull {{[0-9]+}}(%esp), %ebx -; X86-NEXT: addl %edx, %ebx -; X86-NEXT: addl %ecx, %ebx +; X86-NEXT: mull %edi +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: imull {{[0-9]+}}(%esp), %edi +; X86-NEXT: addl %edx, %edi +; X86-NEXT: addl %ecx, %edi ; X86-NEXT: movl {{[0-9]+}}(%esp), %eax ; X86-NEXT: movl %eax, %ecx ; X86-NEXT: imull %esi, %ecx @@ -568,12 +567,12 @@ define i128 @scalar_i128(i128 %x, i128 %y, ptr %divdst) nounwind { ; X86-NEXT: mull %edx ; X86-NEXT: addl %edx, %ebp ; X86-NEXT: addl %ecx, %ebp -; X86-NEXT: addl (%esp), %eax # 4-byte Folded Reload -; X86-NEXT: adcl %ebx, %ebp +; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload +; X86-NEXT: adcl %edi, %ebp ; X86-NEXT: addl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: adcl {{[-0-9]+}}(%e{{[sb]}}p), %ebp # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %edx -; X86-NEXT: subl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: subl (%esp), %edx # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %ecx ; X86-NEXT: sbbl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi diff --git a/llvm/test/CodeGen/X86/fold-masked-merge.ll b/llvm/test/CodeGen/X86/fold-masked-merge.ll index 135494ac25f8..b2614c5fe049 100644 --- a/llvm/test/CodeGen/X86/fold-masked-merge.ll +++ b/llvm/test/CodeGen/X86/fold-masked-merge.ll @@ -56,9 +56,7 @@ define i8 @masked_merge2(i8 %a0, i8 %a1, i8 %a2) { ; NOBMI-LABEL: masked_merge2: ; NOBMI: # %bb.0: ; NOBMI-NEXT: movl %esi, %eax -; NOBMI-NEXT: xorb %sil, %al -; NOBMI-NEXT: andb %dil, %al -; NOBMI-NEXT: xorb %sil, %al +; NOBMI-NEXT: # kill: def $al killed $al killed $eax ; NOBMI-NEXT: retq ; ; BMI-LABEL: masked_merge2: diff --git a/llvm/test/CodeGen/X86/freeze-binary.ll b/llvm/test/CodeGen/X86/freeze-binary.ll index b212e9438e1b..c79da37988e4 100644 --- a/llvm/test/CodeGen/X86/freeze-binary.ll +++ b/llvm/test/CodeGen/X86/freeze-binary.ll @@ -459,8 +459,7 @@ define i32 @freeze_ashr(i32 %a0) nounwind { ; X64-LABEL: freeze_ashr: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: sarl $3, %eax -; X64-NEXT: sarl $3, %eax +; X64-NEXT: sarl $6, %eax ; X64-NEXT: retq %x = ashr i32 %a0, 3 %y = freeze i32 %x @@ -531,30 +530,12 @@ define i32 @freeze_ashr_outofrange(i32 %a0) nounwind { define <8 x i16> @freeze_ashr_vec(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_ashr_vec: ; X86: # %bb.0: -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psraw $1, %xmm2 -; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] -; X86-NEXT: movdqa %xmm1, %xmm3 -; X86-NEXT: pandn %xmm2, %xmm3 -; X86-NEXT: psraw $3, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: por %xmm3, %xmm0 -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psraw $3, %xmm2 -; X86-NEXT: psraw $1, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: pandn %xmm2, %xmm1 -; X86-NEXT: por %xmm1, %xmm0 +; X86-NEXT: psraw $4, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_ashr_vec: ; X64: # %bb.0: -; X64-NEXT: vpsraw $1, %xmm0, %xmm1 -; X64-NEXT: vpsraw $3, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; X64-NEXT: vpsraw $3, %xmm0, %xmm1 -; X64-NEXT: vpsraw $1, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; X64-NEXT: vpsraw $4, %xmm0, %xmm0 ; X64-NEXT: retq %x = ashr <8 x i16> %a0, %y = freeze <8 x i16> %x @@ -592,8 +573,7 @@ define i32 @freeze_lshr(i32 %a0) nounwind { ; X64-LABEL: freeze_lshr: ; X64: # %bb.0: ; X64-NEXT: movl %edi, %eax -; X64-NEXT: shrl $2, %eax -; X64-NEXT: shrl %eax +; X64-NEXT: shrl $3, %eax ; X64-NEXT: retq %x = lshr i32 %a0, 2 %y = freeze i32 %x @@ -664,30 +644,12 @@ define i32 @freeze_lshr_outofrange(i32 %a0) nounwind { define <8 x i16> @freeze_lshr_vec(<8 x i16> %a0) nounwind { ; X86-LABEL: freeze_lshr_vec: ; X86: # %bb.0: -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psrlw $1, %xmm2 -; X86-NEXT: movdqa {{.*#+}} xmm1 = [65535,0,65535,0,65535,0,65535,0] -; X86-NEXT: movdqa %xmm1, %xmm3 -; X86-NEXT: pandn %xmm2, %xmm3 -; X86-NEXT: psrlw $2, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: por %xmm3, %xmm0 -; X86-NEXT: movdqa %xmm0, %xmm2 -; X86-NEXT: psrlw $2, %xmm2 -; X86-NEXT: psrlw $1, %xmm0 -; X86-NEXT: pand %xmm1, %xmm0 -; X86-NEXT: pandn %xmm2, %xmm1 -; X86-NEXT: por %xmm1, %xmm0 +; X86-NEXT: psrlw $3, %xmm0 ; X86-NEXT: retl ; ; X64-LABEL: freeze_lshr_vec: ; X64: # %bb.0: -; X64-NEXT: vpsrlw $1, %xmm0, %xmm1 -; X64-NEXT: vpsrlw $2, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] -; X64-NEXT: vpsrlw $2, %xmm0, %xmm1 -; X64-NEXT: vpsrlw $1, %xmm0, %xmm0 -; X64-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2],xmm1[3],xmm0[4],xmm1[5],xmm0[6],xmm1[7] +; X64-NEXT: vpsrlw $3, %xmm0, %xmm0 ; X64-NEXT: retq %x = lshr <8 x i16> %a0, %y = freeze <8 x i16> %x diff --git a/llvm/test/CodeGen/X86/freeze-combine.ll b/llvm/test/CodeGen/X86/freeze-combine.ll index b037a6d9a1b9..1cfb8627a4dd 100644 --- a/llvm/test/CodeGen/X86/freeze-combine.ll +++ b/llvm/test/CodeGen/X86/freeze-combine.ll @@ -3,9 +3,9 @@ define i32 @const() { ; CHECK-LABEL: name: const ; CHECK: bb.0 (%ir-block.0): - ; CHECK: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 - ; CHECK: $eax = COPY [[MOV32ri]] - ; CHECK: RET 0, $eax + ; CHECK-NEXT: [[MOV32ri:%[0-9]+]]:gr32 = MOV32ri 1 + ; CHECK-NEXT: $eax = COPY [[MOV32ri]] + ; CHECK-NEXT: RET 0, $eax %y = freeze i32 1 ret i32 %y } @@ -13,11 +13,11 @@ define i32 @const() { define i32 @fold(i32 %x) { ; CHECK-LABEL: name: fold ; CHECK: bb.0 (%ir-block.0): - ; CHECK: liveins: $edi - ; CHECK: [[COPY:%[0-9]+]]:gr32 = COPY $edi - ; CHECK: [[COPY1:%[0-9]+]]:gr32 = COPY [[COPY]] - ; CHECK: $eax = COPY [[COPY1]] - ; CHECK: RET 0, $eax + ; CHECK-NEXT: liveins: $edi + ; CHECK-NEXT: {{ $}} + ; CHECK-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi + ; CHECK-NEXT: $eax = COPY [[COPY]] + ; CHECK-NEXT: RET 0, $eax %y = freeze i32 %x %z = freeze i32 %y ret i32 %z diff --git a/llvm/test/CodeGen/X86/freeze-vector.ll b/llvm/test/CodeGen/X86/freeze-vector.ll index ee7f4aea02c0..fe240286462e 100644 --- a/llvm/test/CodeGen/X86/freeze-vector.ll +++ b/llvm/test/CodeGen/X86/freeze-vector.ll @@ -672,3 +672,23 @@ define void @pr59677(i32 %x, ptr %out) nounwind { ret void } declare <4 x float> @llvm.sin.v4f32(<4 x float>) + +; Test that we can eliminate freeze by changing the BUILD_VECTOR to a splat +; zero vector. +define void @freeze_buildvector_not_simple_type(ptr %dst) nounwind { +; X86-LABEL: freeze_buildvector_not_simple_type: +; X86: # %bb.0: +; X86-NEXT: movl {{[0-9]+}}(%esp), %eax +; X86-NEXT: movb $0, 4(%eax) +; X86-NEXT: movl $0, (%eax) +; X86-NEXT: retl +; +; X64-LABEL: freeze_buildvector_not_simple_type: +; X64: # %bb.0: +; X64-NEXT: movb $0, 4(%rdi) +; X64-NEXT: movl $0, (%rdi) +; X64-NEXT: retq + %i0 = freeze <5 x i8> + store <5 x i8> %i0, ptr %dst + ret void +} diff --git a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll index 0c341dc63a9e..afe0ebb9dcb4 100644 --- a/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll +++ b/llvm/test/CodeGen/X86/gfni-funnel-shifts.ll @@ -522,17 +522,17 @@ declare <16 x i8> @llvm.fshl.v16i8(<16 x i8>, <16 x i8>, <16 x i8>) define <16 x i8> @splatconstant_fshr_v16i8(<16 x i8> %a, <16 x i8> %b) nounwind { ; GFNISSE-LABEL: splatconstant_fshr_v16i8: ; GFNISSE: # %bb.0: +; GFNISSE-NEXT: paddb %xmm0, %xmm0 ; GFNISSE-NEXT: psrlw $7, %xmm1 ; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; GFNISSE-NEXT: paddb %xmm0, %xmm0 ; GFNISSE-NEXT: por %xmm1, %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: splatconstant_fshr_v16i8: ; GFNIAVX1OR2: # %bb.0: +; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm1, %xmm1 ; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/gfni-rotates.ll b/llvm/test/CodeGen/X86/gfni-rotates.ll index 7ab8300b269a..96aff5b2af31 100644 --- a/llvm/test/CodeGen/X86/gfni-rotates.ll +++ b/llvm/test/CodeGen/X86/gfni-rotates.ll @@ -421,18 +421,18 @@ define <16 x i8> @splatconstant_rotr_v16i8(<16 x i8> %a) nounwind { ; GFNISSE-LABEL: splatconstant_rotr_v16i8: ; GFNISSE: # %bb.0: ; GFNISSE-NEXT: movdqa %xmm0, %xmm1 -; GFNISSE-NEXT: psrlw $7, %xmm1 -; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 -; GFNISSE-NEXT: paddb %xmm0, %xmm0 +; GFNISSE-NEXT: paddb %xmm0, %xmm1 +; GFNISSE-NEXT: psrlw $7, %xmm0 +; GFNISSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 ; GFNISSE-NEXT: por %xmm1, %xmm0 ; GFNISSE-NEXT: retq ; ; GFNIAVX1OR2-LABEL: splatconstant_rotr_v16i8: ; GFNIAVX1OR2: # %bb.0: -; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm1 -; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; GFNIAVX1OR2-NEXT: vpor %xmm1, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpaddb %xmm0, %xmm0, %xmm1 +; GFNIAVX1OR2-NEXT: vpsrlw $7, %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; GFNIAVX1OR2-NEXT: vpor %xmm0, %xmm1, %xmm0 ; GFNIAVX1OR2-NEXT: retq ; ; GFNIAVX512-LABEL: splatconstant_rotr_v16i8: diff --git a/llvm/test/CodeGen/X86/known-never-zero.ll b/llvm/test/CodeGen/X86/known-never-zero.ll index 39d02f9112f4..2f780e3c6fe1 100644 --- a/llvm/test/CodeGen/X86/known-never-zero.ll +++ b/llvm/test/CodeGen/X86/known-never-zero.ll @@ -676,12 +676,13 @@ define i32 @rotr_known_nonzero(i32 %xx, i32 %y) { ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx ; X64-NEXT: orl $256, %edi # imm = 0x100 +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %edi +; X64-NEXT: rorl %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB22_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB22_1: ; X64-NEXT: movl $32, %eax @@ -713,12 +714,13 @@ define i32 @rotr_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotr_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %edi +; X64-NEXT: rorl %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB23_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB23_1: ; X64-NEXT: movl $32, %eax @@ -773,12 +775,13 @@ define i32 @rotr_with_fshr_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotr_with_fshr_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: rorl %cl, %edi +; X64-NEXT: rorl %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB25_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB25_1: ; X64-NEXT: movl $32, %eax @@ -808,12 +811,13 @@ define i32 @rotl_known_nonzero(i32 %xx, i32 %y) { ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx ; X64-NEXT: orl $256, %edi # imm = 0x100 +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %edi +; X64-NEXT: roll %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB26_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB26_1: ; X64-NEXT: movl $32, %eax @@ -845,12 +849,13 @@ define i32 @rotl_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotl_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %edi +; X64-NEXT: roll %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB27_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB27_1: ; X64-NEXT: movl $32, %eax @@ -905,12 +910,13 @@ define i32 @rotl_with_fshl_maybe_zero(i32 %x, i32 %y) { ; X64-LABEL: rotl_with_fshl_maybe_zero: ; X64: # %bb.0: ; X64-NEXT: movl %esi, %ecx +; X64-NEXT: movl %edi, %eax ; X64-NEXT: # kill: def $cl killed $cl killed $ecx -; X64-NEXT: roll %cl, %edi +; X64-NEXT: roll %cl, %eax ; X64-NEXT: testl %edi, %edi ; X64-NEXT: je .LBB29_1 ; X64-NEXT: # %bb.2: # %cond.false -; X64-NEXT: rep bsfl %edi, %eax +; X64-NEXT: rep bsfl %eax, %eax ; X64-NEXT: retq ; X64-NEXT: .LBB29_1: ; X64-NEXT: movl $32, %eax diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll index d3cced3233ea..5a6375e08bca 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-128.ll @@ -893,27 +893,26 @@ define <2 x i64> @vec128_i64_signed_reg_reg(<2 x i64> %a1, <2 x i64> %a2) nounwi ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm5, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3] -; SSE41-NEXT: por %xmm3, %xmm6 -; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 -; SSE41-NEXT: pand %xmm5, %xmm0 -; SSE41-NEXT: por %xmm4, %xmm0 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psubq %xmm1, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] +; SSE41-NEXT: por %xmm3, %xmm0 +; SSE41-NEXT: pmovsxbq {{.*#+}} xmm3 = [1,1] +; SSE41-NEXT: por %xmm0, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psubq %xmm1, %xmm4 ; SSE41-NEXT: psubq %xmm2, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 +; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 ; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: psrlq $1, %xmm0 ; SSE41-NEXT: psrlq $33, %xmm1 -; SSE41-NEXT: pmuludq %xmm6, %xmm1 -; SSE41-NEXT: movdqa %xmm6, %xmm3 -; SSE41-NEXT: psrlq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm0, %xmm3 -; SSE41-NEXT: paddq %xmm1, %xmm3 -; SSE41-NEXT: psllq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm6, %xmm0 +; SSE41-NEXT: pmuludq %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psrlq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm0, %xmm4 +; SSE41-NEXT: paddq %xmm1, %xmm4 +; SSE41-NEXT: psllq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm3, %xmm0 ; SSE41-NEXT: paddq %xmm2, %xmm0 -; SSE41-NEXT: paddq %xmm3, %xmm0 +; SSE41-NEXT: paddq %xmm4, %xmm0 ; SSE41-NEXT: retq ; ; AVX-LABEL: vec128_i64_signed_reg_reg: @@ -1077,27 +1076,26 @@ define <2 x i64> @vec128_i64_unsigned_reg_reg(<2 x i64> %a1, <2 x i64> %a2) noun ; SSE41-NEXT: pcmpeqd %xmm3, %xmm0 ; SSE41-NEXT: pshufd {{.*#+}} xmm3 = xmm0[1,1,3,3] ; SSE41-NEXT: pand %xmm5, %xmm3 -; SSE41-NEXT: pshufd {{.*#+}} xmm6 = xmm4[1,1,3,3] -; SSE41-NEXT: por %xmm3, %xmm6 -; SSE41-NEXT: por {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm6 -; SSE41-NEXT: pand %xmm5, %xmm0 -; SSE41-NEXT: por %xmm4, %xmm0 -; SSE41-NEXT: movdqa %xmm2, %xmm3 -; SSE41-NEXT: psubq %xmm1, %xmm3 +; SSE41-NEXT: pshufd {{.*#+}} xmm0 = xmm4[1,1,3,3] +; SSE41-NEXT: por %xmm3, %xmm0 +; SSE41-NEXT: pmovsxbq {{.*#+}} xmm3 = [1,1] +; SSE41-NEXT: por %xmm0, %xmm3 +; SSE41-NEXT: movdqa %xmm2, %xmm4 +; SSE41-NEXT: psubq %xmm1, %xmm4 ; SSE41-NEXT: psubq %xmm2, %xmm1 -; SSE41-NEXT: blendvpd %xmm0, %xmm3, %xmm1 +; SSE41-NEXT: blendvpd %xmm0, %xmm4, %xmm1 ; SSE41-NEXT: movapd %xmm1, %xmm0 ; SSE41-NEXT: psrlq $1, %xmm0 ; SSE41-NEXT: psrlq $33, %xmm1 -; SSE41-NEXT: pmuludq %xmm6, %xmm1 -; SSE41-NEXT: movdqa %xmm6, %xmm3 -; SSE41-NEXT: psrlq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm0, %xmm3 -; SSE41-NEXT: paddq %xmm1, %xmm3 -; SSE41-NEXT: psllq $32, %xmm3 -; SSE41-NEXT: pmuludq %xmm6, %xmm0 +; SSE41-NEXT: pmuludq %xmm3, %xmm1 +; SSE41-NEXT: movdqa %xmm3, %xmm4 +; SSE41-NEXT: psrlq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm0, %xmm4 +; SSE41-NEXT: paddq %xmm1, %xmm4 +; SSE41-NEXT: psllq $32, %xmm4 +; SSE41-NEXT: pmuludq %xmm3, %xmm0 ; SSE41-NEXT: paddq %xmm2, %xmm0 -; SSE41-NEXT: paddq %xmm3, %xmm0 +; SSE41-NEXT: paddq %xmm4, %xmm0 ; SSE41-NEXT: retq ; ; AVX1-LABEL: vec128_i64_unsigned_reg_reg: @@ -1993,14 +1991,14 @@ define <8 x i16> @vec128_i16_unsigned_reg_reg(<8 x i16> %a1, <8 x i16> %a2) noun ; ; AVX512VL-FALLBACK-LABEL: vec128_i16_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminuw %xmm1, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqw %xmm2, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm2, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm2, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %xmm2, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpmaxuw %xmm1, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpminuw %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %xmm1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqw %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsubw %xmm1, %xmm2, %xmm1 ; AVX512VL-FALLBACK-NEXT: vpaddw %xmm0, %xmm1, %xmm0 ; AVX512VL-FALLBACK-NEXT: retq ; @@ -2786,14 +2784,14 @@ define <16 x i8> @vec128_i8_unsigned_reg_reg(<16 x i8> %a1, <16 x i8> %a2) nounw ; ; AVX512VL-FALLBACK-LABEL: vec128_i8_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm1, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqb %xmm2, %xmm0, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm2, %xmm2, %xmm2 -; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm2, %xmm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %xmm2, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpmaxub %xmm1, %xmm0, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpminub %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %xmm1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %xmm2, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqb %xmm1, %xmm0, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %xmm1, %xmm1, %xmm1 +; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to4}, %xmm1, %xmm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %xmm1, %xmm2, %xmm1 ; AVX512VL-FALLBACK-NEXT: vpaddb %xmm0, %xmm1, %xmm0 ; AVX512VL-FALLBACK-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll index cc08396ae8c7..e880a1acc9e8 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-256.ll @@ -1445,14 +1445,14 @@ define <16 x i16> @vec256_i16_unsigned_reg_reg(<16 x i16> %a1, <16 x i16> %a2) n ; ; AVX512VL-FALLBACK-LABEL: vec256_i16_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm2, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm2, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpxor %ymm2, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubw %ymm2, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpmaxuw %ymm1, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpminuw %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqw %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpxor %ymm1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubw %ymm1, %ymm2, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpaddw %ymm0, %ymm1, %ymm0 ; AVX512VL-FALLBACK-NEXT: retq ; @@ -2210,14 +2210,14 @@ define <32 x i8> @vec256_i8_unsigned_reg_reg(<32 x i8> %a1, <32 x i8> %a2) nounw ; ; AVX512VL-FALLBACK-LABEL: vec256_i8_unsigned_reg_reg: ; AVX512VL-FALLBACK: # %bb.0: -; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm2, %ymm0, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm2, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm2, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm1, %ymm0, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpternlogq $15, %ymm1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpternlogd $108, {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %ymm1, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm2, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpaddb %ymm0, %ymm1, %ymm0 ; AVX512VL-FALLBACK-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll index 2fdf6ef224ca..366dad1612b4 100644 --- a/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll +++ b/llvm/test/CodeGen/X86/midpoint-int-vec-512.ll @@ -684,22 +684,21 @@ define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwin ; AVX512F-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4 ; AVX512F-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5 ; AVX512F-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4 -; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5 -; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 -; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512F-NEXT: vpminsb %ymm1, %ymm0, %ymm5 ; AVX512F-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 ; AVX512F-NEXT: vpsubb %ymm5, %ymm1, %ymm1 -; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpminsb %ymm2, %ymm3, %ymm5 +; AVX512F-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 +; AVX512F-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512F-NEXT: vpand %ymm5, %ymm2, %ymm2 +; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5 -; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512F-NEXT: vpandq %zmm6, %zmm5, %zmm5 -; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512F-NEXT: vpternlogq $226, %zmm5, %zmm4, %zmm1 ; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -715,22 +714,21 @@ define <64 x i8> @vec512_i8_signed_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounwin ; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm2, %ymm3, %ymm4 ; AVX512VL-FALLBACK-NEXT: vpcmpgtb %ymm1, %ymm0, %ymm5 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm4, %zmm5, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpminsb %ymm2, %ymm3, %ymm5 -; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpminsb %ymm1, %ymm0, %ymm5 ; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm1, %ymm0, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpminsb %ymm2, %ymm3, %ymm5 +; AVX512VL-FALLBACK-NEXT: vpmaxsb %ymm2, %ymm3, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm5, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm5 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpand %ymm5, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm5, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512VL-FALLBACK-NEXT: vpternlogq $226, %zmm5, %zmm4, %zmm1 ; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -772,20 +770,19 @@ define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounw ; AVX512F-NEXT: vpminub %ymm1, %ymm0, %ymm6 ; AVX512F-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7 ; AVX512F-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5 -; AVX512F-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 -; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 ; AVX512F-NEXT: vpsubb %ymm6, %ymm1, %ymm1 -; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 +; AVX512F-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512F-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512F-NEXT: vpbroadcastb {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512F-NEXT: vpand %ymm4, %ymm2, %ymm2 +; AVX512F-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512F-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4 -; AVX512F-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512F-NEXT: vpandq %zmm6, %zmm4, %zmm4 -; AVX512F-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512F-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512F-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512F-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512F-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512F-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512F-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512F-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512F-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512F-NEXT: vpternlogq $184, %zmm4, %zmm5, %zmm1 ; AVX512F-NEXT: vextracti64x4 $1, %zmm1, %ymm2 @@ -803,20 +800,19 @@ define <64 x i8> @vec512_i8_unsigned_reg_reg(<64 x i8> %a1, <64 x i8> %a2) nounw ; AVX512VL-FALLBACK-NEXT: vpminub %ymm1, %ymm0, %ymm6 ; AVX512VL-FALLBACK-NEXT: vpcmpeqb %ymm6, %ymm0, %ymm7 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm5, %zmm7, %zmm5 -; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm1, %ymm0, %ymm1 ; AVX512VL-FALLBACK-NEXT: vpsubb %ymm6, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpmaxub %ymm2, %ymm3, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm4, %ymm2, %ymm2 ; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} ymm4 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] +; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm2, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsrlw $1, %ymm1, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpand %ymm4, %ymm1, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpbroadcastd {{.*#+}} zmm6 = [127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127,127] -; AVX512VL-FALLBACK-NEXT: vpandq %zmm6, %zmm4, %zmm4 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm2, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpxor %xmm7, %xmm7, %xmm7 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm7, %ymm2 -; AVX512VL-FALLBACK-NEXT: vpand %ymm6, %ymm1, %ymm1 -; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm7, %ymm1 +; AVX512VL-FALLBACK-NEXT: vpxor %xmm6, %xmm6, %xmm6 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm2, %ymm6, %ymm2 +; AVX512VL-FALLBACK-NEXT: vpsubb %ymm1, %ymm6, %ymm1 ; AVX512VL-FALLBACK-NEXT: vinserti64x4 $1, %ymm2, %zmm1, %zmm1 ; AVX512VL-FALLBACK-NEXT: vpternlogq $184, %zmm4, %zmm5, %zmm1 ; AVX512VL-FALLBACK-NEXT: vextracti64x4 $1, %zmm1, %ymm2 diff --git a/llvm/test/CodeGen/X86/pr38539.ll b/llvm/test/CodeGen/X86/pr38539.ll index 04aff9b7d2e5..ace78b38d53e 100644 --- a/llvm/test/CodeGen/X86/pr38539.ll +++ b/llvm/test/CodeGen/X86/pr38539.ll @@ -22,7 +22,7 @@ define void @f() nounwind { ; X86-NEXT: pushl %edi ; X86-NEXT: pushl %esi ; X86-NEXT: andl $-16, %esp -; X86-NEXT: subl $176, %esp +; X86-NEXT: subl $160, %esp ; X86-NEXT: movzbl {{[0-9]+}}(%esp), %edx ; X86-NEXT: movl {{[0-9]+}}(%esp), %esi ; X86-NEXT: movl {{[0-9]+}}(%esp), %edi @@ -47,55 +47,54 @@ define void @f() nounwind { ; X86-NEXT: testl %edi, %edi ; X86-NEXT: jne .LBB0_1 ; X86-NEXT: # %bb.2: # %BB_udiv-special-cases -; X86-NEXT: bsrl %esi, %ecx -; X86-NEXT: xorl $31, %ecx -; X86-NEXT: addl $32, %ecx +; X86-NEXT: bsrl %esi, %eax +; X86-NEXT: xorl $31, %eax +; X86-NEXT: addl $32, %eax ; X86-NEXT: jmp .LBB0_3 ; X86-NEXT: .LBB0_1: -; X86-NEXT: bsrl %edi, %ecx -; X86-NEXT: xorl $31, %ecx +; X86-NEXT: bsrl %edi, %eax +; X86-NEXT: xorl $31, %eax ; X86-NEXT: .LBB0_3: # %BB_udiv-special-cases -; X86-NEXT: xorl %eax, %eax +; X86-NEXT: xorl %ecx, %ecx ; X86-NEXT: testl %edx, %edx -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: jne .LBB0_4 ; X86-NEXT: # %bb.5: # %BB_udiv-special-cases -; X86-NEXT: addl $64, %ecx +; X86-NEXT: addl $64, %eax ; X86-NEXT: jmp .LBB0_6 ; X86-NEXT: .LBB0_4: -; X86-NEXT: bsrl %edx, %ecx -; X86-NEXT: xorl $31, %ecx -; X86-NEXT: addl $32, %ecx +; X86-NEXT: bsrl %edx, %eax +; X86-NEXT: xorl $31, %eax +; X86-NEXT: addl $32, %eax ; X86-NEXT: .LBB0_6: # %BB_udiv-special-cases -; X86-NEXT: subl $62, %ecx +; X86-NEXT: subl $62, %eax ; X86-NEXT: movl $0, %ebx ; X86-NEXT: sbbl %ebx, %ebx -; X86-NEXT: sbbl %eax, %eax -; X86-NEXT: addl $-66, %ecx +; X86-NEXT: sbbl %ecx, %ecx +; X86-NEXT: addl $-66, %eax ; X86-NEXT: adcl $-1, %ebx -; X86-NEXT: adcl $3, %eax -; X86-NEXT: movl %eax, %edi -; X86-NEXT: movb $1, %al -; X86-NEXT: testb %al, %al +; X86-NEXT: adcl $3, %ecx +; X86-NEXT: movl %ecx, %esi +; X86-NEXT: movb $1, %cl +; X86-NEXT: testb %cl, %cl ; X86-NEXT: jne .LBB0_11 ; X86-NEXT: # %bb.7: # %BB_udiv-special-cases -; X86-NEXT: andl $3, %edi -; X86-NEXT: movl %ecx, %eax -; X86-NEXT: xorl $65, %eax -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %edi, %eax -; X86-NEXT: orl %ebx, %eax +; X86-NEXT: andl $3, %esi +; X86-NEXT: movl %eax, %ecx +; X86-NEXT: xorl $65, %ecx +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %esi, %ecx +; X86-NEXT: orl %ebx, %ecx ; X86-NEXT: je .LBB0_11 ; X86-NEXT: # %bb.8: # %udiv-bb1 -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %ecx, %eax +; X86-NEXT: movl %eax, %ecx ; X86-NEXT: addl $1, %ecx ; X86-NEXT: movl %ecx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: adcl $0, %ebx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: adcl $0, %esi -; X86-NEXT: andl $3, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload +; X86-NEXT: adcl $0, %ebx +; X86-NEXT: andl $3, %ebx ; X86-NEXT: movb $65, %cl ; X86-NEXT: subb %al, %cl ; X86-NEXT: movb %cl, %ch @@ -112,29 +111,31 @@ define void @f() nounwind { ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl 136(%esp,%eax), %edx +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 120(%esp,%eax), %edi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shll %cl, %edx +; X86-NEXT: shll %cl, %edi ; X86-NEXT: notb %cl -; X86-NEXT: movl 128(%esp,%eax), %edi -; X86-NEXT: movl 132(%esp,%eax), %esi -; X86-NEXT: movl %esi, %eax +; X86-NEXT: movl 112(%esp,%eax), %esi +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl 116(%esp,%eax), %edx +; X86-NEXT: movl %edx, %eax ; X86-NEXT: shrl %eax ; X86-NEXT: shrl %cl, %eax ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shldl %cl, %edi, %esi +; X86-NEXT: shldl %cl, %esi, %edx +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shll %cl, %esi ; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: shll %cl, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Reload -; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: orl %ebx, %ecx +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %ecx # 4-byte Folded Reload ; X86-NEXT: je .LBB0_11 ; X86-NEXT: # %bb.9: # %udiv-preheader -; X86-NEXT: orl %eax, %edx -; X86-NEXT: andl $3, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %eax, %edi +; X86-NEXT: andl $3, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) ; X86-NEXT: movl $0, {{[0-9]+}}(%esp) @@ -149,20 +150,20 @@ define void @f() nounwind { ; X86-NEXT: # kill: def $al killed $al killed $eax ; X86-NEXT: shrb $3, %al ; X86-NEXT: andb $15, %al -; X86-NEXT: movzbl %al, %esi -; X86-NEXT: movl 80(%esp,%esi), %edx -; X86-NEXT: movl 84(%esp,%esi), %eax -; X86-NEXT: movl %eax, %edi +; X86-NEXT: movzbl %al, %eax +; X86-NEXT: movl 64(%esp,%eax), %edi +; X86-NEXT: movl 68(%esp,%eax), %edx +; X86-NEXT: movl %edx, %esi ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrl %cl, %edi +; X86-NEXT: shrl %cl, %esi ; X86-NEXT: notb %cl -; X86-NEXT: movl 88(%esp,%esi), %esi -; X86-NEXT: addl %esi, %esi -; X86-NEXT: shll %cl, %esi -; X86-NEXT: orl %edi, %esi +; X86-NEXT: movl 72(%esp,%eax), %ebx +; X86-NEXT: addl %ebx, %ebx +; X86-NEXT: shll %cl, %ebx +; X86-NEXT: orl %esi, %ebx ; X86-NEXT: movb %ch, %cl -; X86-NEXT: shrdl %cl, %eax, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shrdl %cl, %edx, %edi +; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: movl $0, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Spill ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: addl $-1, %eax @@ -179,63 +180,62 @@ define void @f() nounwind { ; X86-NEXT: .p2align 4, 0x90 ; X86-NEXT: .LBB0_10: # %udiv-do-while ; X86-NEXT: # =>This Inner Loop Header: Depth=1 -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: shldl $1, %esi, %ecx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload -; X86-NEXT: shldl $1, %edx, %esi -; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: movl %ebx, %edi +; X86-NEXT: shldl $1, %ebx, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: movl %ebx, %eax -; X86-NEXT: andl $2, %eax -; X86-NEXT: shrl %eax -; X86-NEXT: leal (%eax,%edx,2), %edx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: shldl $1, %edi, %ebx +; X86-NEXT: shldl $1, %ebx, %edi ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: orl %esi, %ebx +; X86-NEXT: movl %esi, %edx +; X86-NEXT: andl $2, %edx +; X86-NEXT: shrl %edx +; X86-NEXT: leal (%edx,%ebx,2), %ebx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: shldl $1, %edx, %esi +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: shldl $1, %eax, %edi -; X86-NEXT: orl %esi, %edi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: shldl $1, %eax, %edx +; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill ; X86-NEXT: addl %eax, %eax ; X86-NEXT: orl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: andl $3, %ebx -; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: cmpl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload -; X86-NEXT: sbbl %esi, %eax -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: sbbl %ecx, %ebx -; X86-NEXT: shll $30, %ebx -; X86-NEXT: movl %ebx, %eax -; X86-NEXT: sarl $30, %eax -; X86-NEXT: sarl $31, %ebx -; X86-NEXT: shrdl $1, %ebx, %eax -; X86-NEXT: movl %eax, %edi -; X86-NEXT: andl $1, %edi -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: andl $3, %esi +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: cmpl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Folded Reload +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: sbbl %edi, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: sbbl %ecx, %esi +; X86-NEXT: shll $30, %esi +; X86-NEXT: movl %esi, %edx +; X86-NEXT: sarl $30, %edx +; X86-NEXT: sarl $31, %esi +; X86-NEXT: shrdl $1, %esi, %edx +; X86-NEXT: movl %edx, %eax +; X86-NEXT: andl $1, %eax +; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Folded Reload +; X86-NEXT: movl %esi, %eax ; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Folded Reload -; X86-NEXT: movl %ebx, %edi -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Folded Reload -; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Folded Reload -; X86-NEXT: subl %eax, %edx -; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: sbbl %ebx, %esi -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %ebx # 4-byte Reload -; X86-NEXT: sbbl %edi, %ecx +; X86-NEXT: andl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Folded Reload +; X86-NEXT: subl %edx, %ebx +; X86-NEXT: movl %ebx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: sbbl %esi, %edi +; X86-NEXT: movl %edi, %ebx +; X86-NEXT: sbbl %eax, %ecx ; X86-NEXT: andl $3, %ecx ; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %eax # 4-byte Reload ; X86-NEXT: addl $-1, %eax -; X86-NEXT: adcl $-1, %ebx -; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edi # 4-byte Reload -; X86-NEXT: adcl $3, %edi -; X86-NEXT: andl $3, %edi +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %edx # 4-byte Reload +; X86-NEXT: adcl $-1, %edx +; X86-NEXT: movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload +; X86-NEXT: adcl $3, %esi +; X86-NEXT: andl $3, %esi ; X86-NEXT: movl %eax, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: movl %edi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill -; X86-NEXT: orl %edi, %eax -; X86-NEXT: orl %ebx, %eax +; X86-NEXT: movl %esi, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %esi, %eax +; X86-NEXT: movl %edx, {{[-0-9]+}}(%e{{[sb]}}p) # 4-byte Spill +; X86-NEXT: orl %edx, %eax ; X86-NEXT: jne .LBB0_10 ; X86-NEXT: .LBB0_11: # %udiv-end ; X86-NEXT: cmpb $0, {{[-0-9]+}}(%e{{[sb]}}p) # 1-byte Folded Reload diff --git a/llvm/test/CodeGen/X86/pr62286.ll b/llvm/test/CodeGen/X86/pr62286.ll index 782c84408f25..1b13cee628df 100644 --- a/llvm/test/CodeGen/X86/pr62286.ll +++ b/llvm/test/CodeGen/X86/pr62286.ll @@ -8,21 +8,20 @@ define i64 @PR62286(i32 %a) { ; SSE-LABEL: PR62286: ; SSE: # %bb.0: ; SSE-NEXT: movd %edi, %xmm0 -; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[0,1,1,0] -; SSE-NEXT: paddd %xmm1, %xmm1 +; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,0,1,0] +; SSE-NEXT: paddd %xmm0, %xmm0 ; SSE-NEXT: pxor %xmm2, %xmm2 -; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] -; SSE-NEXT: pxor %xmm3, %xmm3 -; SSE-NEXT: pcmpgtd %xmm1, %xmm3 -; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm3[0],xmm1[1],xmm3[1] -; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm0[1,0,1,0] -; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0 -; SSE-NEXT: pcmpgtd %xmm0, %xmm2 ; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] -; SSE-NEXT: paddq %xmm1, %xmm0 -; SSE-NEXT: pshufd {{.*#+}} xmm1 = xmm0[2,3,2,3] +; SSE-NEXT: pxor %xmm3, %xmm3 +; SSE-NEXT: pcmpgtd %xmm0, %xmm3 +; SSE-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm3[0],xmm0[1],xmm3[1] +; SSE-NEXT: pand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1 +; SSE-NEXT: pcmpgtd %xmm1, %xmm2 +; SSE-NEXT: punpckldq {{.*#+}} xmm1 = xmm1[0],xmm2[0],xmm1[1],xmm2[1] ; SSE-NEXT: paddq %xmm0, %xmm1 -; SSE-NEXT: movq %xmm1, %rax +; SSE-NEXT: pshufd {{.*#+}} xmm0 = xmm1[2,3,2,3] +; SSE-NEXT: paddq %xmm1, %xmm0 +; SSE-NEXT: movq %xmm0, %rax ; SSE-NEXT: retq ; ; AVX1-LABEL: PR62286: @@ -47,10 +46,10 @@ define i64 @PR62286(i32 %a) { ; AVX2-LABEL: PR62286: ; AVX2: # %bb.0: ; AVX2-NEXT: vmovd %edi, %xmm0 -; AVX2-NEXT: vpslldq {{.*#+}} xmm1 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] -; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1 -; AVX2-NEXT: vpor %xmm0, %xmm1, %xmm0 +; AVX2-NEXT: vpaddd %xmm0, %xmm0, %xmm1 +; AVX2-NEXT: vpslldq {{.*#+}} xmm0 = zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,zero,xmm0[0,1,2,3] +; AVX2-NEXT: vpand {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm0, %xmm0 +; AVX2-NEXT: vpblendd {{.*#+}} xmm0 = xmm1[0],xmm0[1,2,3] ; AVX2-NEXT: vpmovsxdq %xmm0, %ymm0 ; AVX2-NEXT: vextracti128 $1, %ymm0, %xmm1 ; AVX2-NEXT: vpaddq %xmm1, %xmm0, %xmm0 diff --git a/llvm/test/CodeGen/X86/scheduler-backtracking.ll b/llvm/test/CodeGen/X86/scheduler-backtracking.ll index a9f3e8b22fb6..785b97d8c240 100644 --- a/llvm/test/CodeGen/X86/scheduler-backtracking.ll +++ b/llvm/test/CodeGen/X86/scheduler-backtracking.ll @@ -14,7 +14,6 @@ define i256 @test1(i256 %a) nounwind { ; ILP: # %bb.0: ; ILP-NEXT: movq %rdi, %rax ; ILP-NEXT: leal (%rsi,%rsi), %ecx -; ILP-NEXT: addb $3, %cl ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) @@ -23,6 +22,7 @@ define i256 @test1(i256 %a) nounwind { ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) ; ILP-NEXT: movq $0, -{{[0-9]+}}(%rsp) +; ILP-NEXT: addb $3, %cl ; ILP-NEXT: movl %ecx, %edx ; ILP-NEXT: shrb $3, %dl ; ILP-NEXT: andb $7, %cl diff --git a/llvm/test/CodeGen/X86/sdiv_fix_sat.ll b/llvm/test/CodeGen/X86/sdiv_fix_sat.ll index 31297a06f809..a1cabb433d87 100644 --- a/llvm/test/CodeGen/X86/sdiv_fix_sat.ll +++ b/llvm/test/CodeGen/X86/sdiv_fix_sat.ll @@ -563,18 +563,20 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: subq $120, %rsp ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: pshufd {{.*#+}} xmm3 = xmm0[2,1,3,3] -; X64-NEXT: psllq $32, %xmm3 +; X64-NEXT: pxor %xmm3, %xmm3 +; X64-NEXT: punpckhdq {{.*#+}} xmm3 = xmm3[2],xmm0[2],xmm3[3],xmm0[3] ; X64-NEXT: pshufd {{.*#+}} xmm2 = xmm3[1,3,2,3] ; X64-NEXT: psrad $31, %xmm2 ; X64-NEXT: psrlq $31, %xmm3 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm3[0,2,2,3] ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm2[0],xmm0[1],xmm2[1] ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm1[2,3,2,3] ; X64-NEXT: pxor %xmm0, %xmm0 ; X64-NEXT: pcmpgtd %xmm1, %xmm0 @@ -582,113 +584,113 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movq %xmm1, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: xorl %ecx, %ecx ; X64-NEXT: movl $4294967295, %edx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rdx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rdx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax -; X64-NEXT: cmovgeq %rcx, %r14 -; X64-NEXT: cmovgeq %rdx, %rbp +; X64-NEXT: cmovgeq %rdx, %r13 +; X64-NEXT: cmovgeq %rcx, %r12 ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rcx +; X64-NEXT: cmpq %r13, %rcx ; X64-NEXT: movq $-1, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r14, %rax -; X64-NEXT: cmovgeq %rcx, %rbp -; X64-NEXT: movq %rbp, %xmm0 +; X64-NEXT: sbbq %r12, %rax +; X64-NEXT: cmovgeq %rcx, %r13 +; X64-NEXT: movq %r13, %xmm0 ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rcx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax +; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r14 -; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: cmovgeq %rax, %r12 ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rcx +; X64-NEXT: cmpq %r13, %rcx ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r14, %rax -; X64-NEXT: cmovgeq %rcx, %rbp -; X64-NEXT: movq %rbp, %xmm0 +; X64-NEXT: sbbq %r12, %rax +; X64-NEXT: cmovgeq %rcx, %r13 +; X64-NEXT: movq %r13, %xmm0 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 16-byte Reload ; X64-NEXT: punpcklqdq {{.*#+}} xmm1 = xmm1[0],xmm0[0] ; X64-NEXT: psrlq $1, %xmm1 ; X64-NEXT: movdqa %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: pshufd $212, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload -; X64-NEXT: # xmm0 = mem[0,1,1,3] -; X64-NEXT: psllq $32, %xmm0 +; X64-NEXT: pxor %xmm0, %xmm0 +; X64-NEXT: punpckldq {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload +; X64-NEXT: # xmm0 = xmm0[0],mem[0],xmm0[1],mem[1] ; X64-NEXT: pshufd {{.*#+}} xmm1 = xmm0[1,3,2,3] ; X64-NEXT: psrad $31, %xmm1 ; X64-NEXT: psrlq $31, %xmm0 ; X64-NEXT: pshufd {{.*#+}} xmm0 = xmm0[0,2,2,3] ; X64-NEXT: punpckldq {{.*#+}} xmm0 = xmm0[0],xmm1[0],xmm0[1],xmm1[1] ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; X64-NEXT: pxor %xmm1, %xmm1 ; X64-NEXT: pcmpgtd %xmm0, %xmm1 @@ -696,94 +698,92 @@ define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind { ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rcx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax +; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r14 -; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: cmovgeq %rax, %r12 ; X64-NEXT: movabsq $-4294967296, %rcx # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rcx +; X64-NEXT: cmpq %r13, %rcx ; X64-NEXT: movq $-1, %rax -; X64-NEXT: sbbq %r14, %rax -; X64-NEXT: cmovgeq %rcx, %rbp -; X64-NEXT: movq %rbp, %xmm0 +; X64-NEXT: sbbq %r12, %rax +; X64-NEXT: cmovgeq %rcx, %r13 +; X64-NEXT: movq %r13, %xmm0 ; X64-NEXT: movdqa %xmm0, {{[-0-9]+}}(%r{{[sb]}}p) # 16-byte Spill ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] -; X64-NEXT: movq %xmm0, %rbx -; X64-NEXT: movq %rbx, %r13 -; X64-NEXT: sarq $63, %r13 -; X64-NEXT: shldq $31, %rbx, %r13 +; X64-NEXT: movq %xmm0, %rbp +; X64-NEXT: movq %rbp, %r14 +; X64-NEXT: sarq $63, %r14 +; X64-NEXT: shldq $31, %rbp, %r14 +; X64-NEXT: movq %rbp, %r15 +; X64-NEXT: shlq $31, %r15 ; X64-NEXT: pshufd $238, {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Folded Reload ; X64-NEXT: # xmm0 = mem[2,3,2,3] ; X64-NEXT: movq %xmm0, %rdx ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r15 -; X64-NEXT: sarq $63, %r15 -; X64-NEXT: movq %rbx, %r12 -; X64-NEXT: shlq $31, %r12 -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rdx, %rbx +; X64-NEXT: sarq $63, %rbx +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __divti3@PLT -; X64-NEXT: movq %rax, %rbp +; X64-NEXT: movq %rax, %r13 ; X64-NEXT: movq %rax, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: movq %rdx, %r14 +; X64-NEXT: movq %rdx, %r12 ; X64-NEXT: movq %rdx, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Spill -; X64-NEXT: subq $1, %rbp -; X64-NEXT: sbbq $0, %r14 -; X64-NEXT: shrq $63, %rbx -; X64-NEXT: xorl %r15d, %ebx -; X64-NEXT: movq %r12, %rdi -; X64-NEXT: movq %r13, %rsi +; X64-NEXT: subq $1, %r13 +; X64-NEXT: sbbq $0, %r12 +; X64-NEXT: movq %r15, %rdi +; X64-NEXT: movq %r14, %rsi ; X64-NEXT: movq {{[-0-9]+}}(%r{{[sb]}}p), %rdx # 8-byte Reload -; X64-NEXT: movq %r15, %rcx +; X64-NEXT: movq %rbx, %rcx ; X64-NEXT: callq __modti3@PLT ; X64-NEXT: orq %rax, %rdx ; X64-NEXT: setne %al +; X64-NEXT: shrq $63, %rbp +; X64-NEXT: xorl %ebp, %ebx ; X64-NEXT: testb %bl, %al -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r14 # 8-byte Folded Reload -; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %rbp # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r13 # 8-byte Folded Reload +; X64-NEXT: cmoveq {{[-0-9]+}}(%r{{[sb]}}p), %r12 # 8-byte Folded Reload ; X64-NEXT: movl $4294967295, %ecx # imm = 0xFFFFFFFF -; X64-NEXT: cmpq %rcx, %rbp -; X64-NEXT: movq %r14, %rax +; X64-NEXT: cmpq %rcx, %r13 +; X64-NEXT: movq %r12, %rax ; X64-NEXT: sbbq $0, %rax +; X64-NEXT: cmovgeq %rcx, %r13 ; X64-NEXT: movl $0, %eax -; X64-NEXT: cmovgeq %rax, %r14 -; X64-NEXT: cmovgeq %rcx, %rbp +; X64-NEXT: cmovgeq %rax, %r12 ; X64-NEXT: movabsq $-4294967296, %rax # imm = 0xFFFFFFFF00000000 -; X64-NEXT: cmpq %rbp, %rax -; X64-NEXT: sbbq %r14, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill -; X64-NEXT: cmovgeq %rax, %rbp -; X64-NEXT: movq %rbp, %xmm1 +; X64-NEXT: cmpq %r13, %rax +; X64-NEXT: sbbq %r12, {{[-0-9]+}}(%r{{[sb]}}p) # 8-byte Folded Spill +; X64-NEXT: cmovgeq %rax, %r13 +; X64-NEXT: movq %r13, %xmm1 ; X64-NEXT: movdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm0 # 16-byte Reload ; X64-NEXT: punpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm1[0] ; X64-NEXT: psrlq $1, %xmm0 diff --git a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll index 97c3c2040b29..a80d8d8cd01b 100644 --- a/llvm/test/CodeGen/X86/setcc-non-simple-type.ll +++ b/llvm/test/CodeGen/X86/setcc-non-simple-type.ll @@ -46,7 +46,6 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: movq 24(%rsi), %rcx ; CHECK-NEXT: movq 32(%rsi), %rdx ; CHECK-NEXT: movdqa {{.*#+}} xmm0 = [0,0,0,0,0,0,0,0,1,0,0,0,0,0,0,0] -; CHECK-NEXT: xorl %esi, %esi ; CHECK-NEXT: movdqa {{.*#+}} xmm1 = [1,1] ; CHECK-NEXT: movdqa {{.*#+}} xmm2 = [2,2] ; CHECK-NEXT: .p2align 4, 0x90 @@ -54,39 +53,45 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-NEXT: # =>This Loop Header: Depth=1 ; CHECK-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-NEXT: xorpd %xmm3, %xmm3 -; CHECK-NEXT: movq $-1024, %rdi # imm = 0xFC00 +; CHECK-NEXT: movq $-1024, %rsi # imm = 0xFC00 ; CHECK-NEXT: movdqa %xmm0, %xmm4 ; CHECK-NEXT: .p2align 4, 0x90 ; CHECK-NEXT: .LBB0_2: # %vector.body ; CHECK-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-NEXT: cmpq 1024(%rdx,%rdi), %rsi -; CHECK-NEXT: movq %rcx, %r8 -; CHECK-NEXT: sbbq 1032(%rdx,%rdi), %r8 -; CHECK-NEXT: setge %r8b -; CHECK-NEXT: movzbl %r8b, %r8d -; CHECK-NEXT: andl $1, %r8d +; CHECK-NEXT: movdqu 1024(%rdx,%rsi), %xmm5 +; CHECK-NEXT: movdqu 1040(%rdx,%rsi), %xmm6 +; CHECK-NEXT: movq %xmm5, %rdi +; CHECK-NEXT: movq %xmm6, %r8 +; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm5[2,3,2,3] +; CHECK-NEXT: movq %xmm5, %r9 +; CHECK-NEXT: pshufd {{.*#+}} xmm5 = xmm6[2,3,2,3] +; CHECK-NEXT: movq %xmm5, %r10 ; CHECK-NEXT: negq %r8 -; CHECK-NEXT: movq %r8, %xmm5 -; CHECK-NEXT: cmpq 1040(%rdx,%rdi), %rsi ; CHECK-NEXT: movq %rcx, %r8 -; CHECK-NEXT: sbbq 1048(%rdx,%rdi), %r8 +; CHECK-NEXT: sbbq %r10, %r8 ; CHECK-NEXT: setge %r8b ; CHECK-NEXT: movzbl %r8b, %r8d -; CHECK-NEXT: andl $1, %r8d ; CHECK-NEXT: negq %r8 -; CHECK-NEXT: movq %r8, %xmm6 -; CHECK-NEXT: punpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0] -; CHECK-NEXT: movdqa %xmm1, %xmm6 -; CHECK-NEXT: psllq %xmm4, %xmm6 +; CHECK-NEXT: movq %r8, %xmm5 +; CHECK-NEXT: negq %rdi +; CHECK-NEXT: movq %rcx, %rdi +; CHECK-NEXT: sbbq %r9, %rdi +; CHECK-NEXT: setge %dil +; CHECK-NEXT: movzbl %dil, %edi +; CHECK-NEXT: negq %rdi +; CHECK-NEXT: movq %rdi, %xmm6 +; CHECK-NEXT: punpcklqdq {{.*#+}} xmm6 = xmm6[0],xmm5[0] +; CHECK-NEXT: movdqa %xmm1, %xmm5 +; CHECK-NEXT: psllq %xmm4, %xmm5 ; CHECK-NEXT: pshufd {{.*#+}} xmm7 = xmm4[2,3,2,3] ; CHECK-NEXT: movdqa %xmm1, %xmm8 ; CHECK-NEXT: psllq %xmm7, %xmm8 -; CHECK-NEXT: movsd {{.*#+}} xmm8 = xmm6[0],xmm8[1] -; CHECK-NEXT: andpd %xmm5, %xmm8 +; CHECK-NEXT: movsd {{.*#+}} xmm8 = xmm5[0],xmm8[1] +; CHECK-NEXT: andpd %xmm6, %xmm8 ; CHECK-NEXT: orpd %xmm8, %xmm3 ; CHECK-NEXT: paddq %xmm2, %xmm4 -; CHECK-NEXT: addq $32, %rdi +; CHECK-NEXT: addq $32, %rsi ; CHECK-NEXT: jne .LBB0_2 ; CHECK-NEXT: # %bb.3: # %middle.block ; CHECK-NEXT: # in Loop: Header=BB0_1 Depth=1 @@ -101,7 +106,6 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-AVX2-NEXT: movq 24(%rsi), %rcx ; CHECK-AVX2-NEXT: movq 32(%rsi), %rdx ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm0 = [0,1] -; CHECK-AVX2-NEXT: xorl %esi, %esi ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm1 = [1,1] ; CHECK-AVX2-NEXT: vpmovsxbq {{.*#+}} xmm2 = [2,2] ; CHECK-AVX2-NEXT: .p2align 4, 0x90 @@ -109,34 +113,40 @@ define void @failing(ptr %0, ptr %1) nounwind { ; CHECK-AVX2-NEXT: # =>This Loop Header: Depth=1 ; CHECK-AVX2-NEXT: # Child Loop BB0_2 Depth 2 ; CHECK-AVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 -; CHECK-AVX2-NEXT: movq $-1024, %rdi # imm = 0xFC00 +; CHECK-AVX2-NEXT: movq $-1024, %rsi # imm = 0xFC00 ; CHECK-AVX2-NEXT: vmovdqa %xmm0, %xmm4 ; CHECK-AVX2-NEXT: .p2align 4, 0x90 ; CHECK-AVX2-NEXT: .LBB0_2: # %vector.body ; CHECK-AVX2-NEXT: # Parent Loop BB0_1 Depth=1 ; CHECK-AVX2-NEXT: # => This Inner Loop Header: Depth=2 -; CHECK-AVX2-NEXT: cmpq 1024(%rdx,%rdi), %rsi -; CHECK-AVX2-NEXT: movq %rcx, %r8 -; CHECK-AVX2-NEXT: sbbq 1032(%rdx,%rdi), %r8 +; CHECK-AVX2-NEXT: vmovdqu 1024(%rdx,%rsi), %xmm5 +; CHECK-AVX2-NEXT: vmovdqu 1040(%rdx,%rsi), %xmm6 +; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm7 = xmm5[0],xmm6[0] +; CHECK-AVX2-NEXT: vpunpckhqdq {{.*#+}} xmm5 = xmm5[1],xmm6[1] +; CHECK-AVX2-NEXT: vmovq %xmm5, %rdi +; CHECK-AVX2-NEXT: vpextrq $1, %xmm5, %r8 +; CHECK-AVX2-NEXT: vmovq %xmm7, %r9 +; CHECK-AVX2-NEXT: vpextrq $1, %xmm7, %r10 +; CHECK-AVX2-NEXT: negq %r10 +; CHECK-AVX2-NEXT: movq %rcx, %r10 +; CHECK-AVX2-NEXT: sbbq %r8, %r10 ; CHECK-AVX2-NEXT: setge %r8b ; CHECK-AVX2-NEXT: movzbl %r8b, %r8d -; CHECK-AVX2-NEXT: andl $1, %r8d ; CHECK-AVX2-NEXT: negq %r8 ; CHECK-AVX2-NEXT: vmovq %r8, %xmm5 -; CHECK-AVX2-NEXT: cmpq 1040(%rdx,%rdi), %rsi +; CHECK-AVX2-NEXT: negq %r9 ; CHECK-AVX2-NEXT: movq %rcx, %r8 -; CHECK-AVX2-NEXT: sbbq 1048(%rdx,%rdi), %r8 -; CHECK-AVX2-NEXT: setge %r8b -; CHECK-AVX2-NEXT: movzbl %r8b, %r8d -; CHECK-AVX2-NEXT: andl $1, %r8d -; CHECK-AVX2-NEXT: negq %r8 -; CHECK-AVX2-NEXT: vmovq %r8, %xmm6 -; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm5[0],xmm6[0] +; CHECK-AVX2-NEXT: sbbq %rdi, %r8 +; CHECK-AVX2-NEXT: setge %dil +; CHECK-AVX2-NEXT: movzbl %dil, %edi +; CHECK-AVX2-NEXT: negq %rdi +; CHECK-AVX2-NEXT: vmovq %rdi, %xmm6 +; CHECK-AVX2-NEXT: vpunpcklqdq {{.*#+}} xmm5 = xmm6[0],xmm5[0] ; CHECK-AVX2-NEXT: vpsllvq %xmm4, %xmm1, %xmm6 ; CHECK-AVX2-NEXT: vpand %xmm6, %xmm5, %xmm5 ; CHECK-AVX2-NEXT: vpor %xmm3, %xmm5, %xmm3 ; CHECK-AVX2-NEXT: vpaddq %xmm2, %xmm4, %xmm4 -; CHECK-AVX2-NEXT: addq $32, %rdi +; CHECK-AVX2-NEXT: addq $32, %rsi ; CHECK-AVX2-NEXT: jne .LBB0_2 ; CHECK-AVX2-NEXT: # %bb.3: # %middle.block ; CHECK-AVX2-NEXT: # in Loop: Header=BB0_1 Depth=1 diff --git a/llvm/test/CodeGen/X86/vec_saddo.ll b/llvm/test/CodeGen/X86/vec_saddo.ll index cee30f5fe5da..460c5fe11f82 100644 --- a/llvm/test/CodeGen/X86/vec_saddo.ll +++ b/llvm/test/CodeGen/X86/vec_saddo.ll @@ -1045,16 +1045,12 @@ define <4 x i32> @saddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: saddo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k2 -; AVX512-NEXT: kandw %k1, %k0, %k1 -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k2, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_ssubo.ll b/llvm/test/CodeGen/X86/vec_ssubo.ll index 64ed08104885..d06993da6365 100644 --- a/llvm/test/CodeGen/X86/vec_ssubo.ll +++ b/llvm/test/CodeGen/X86/vec_ssubo.ll @@ -1062,16 +1062,12 @@ define <4 x i32> @ssubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: ssubo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm1 -; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k0 -; AVX512-NEXT: vptestnmd %xmm0, %xmm0, %k1 {%k1} -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k0, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_uaddo.ll b/llvm/test/CodeGen/X86/vec_uaddo.ll index 950e943bd902..bac118095331 100644 --- a/llvm/test/CodeGen/X86/vec_uaddo.ll +++ b/llvm/test/CodeGen/X86/vec_uaddo.ll @@ -1098,16 +1098,12 @@ define <4 x i32> @uaddo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: uaddo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpand %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k2 -; AVX512-NEXT: kandw %k1, %k0, %k1 -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k2, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vec_usubo.ll b/llvm/test/CodeGen/X86/vec_usubo.ll index 7de972770d8d..ab75ada72f25 100644 --- a/llvm/test/CodeGen/X86/vec_usubo.ll +++ b/llvm/test/CodeGen/X86/vec_usubo.ll @@ -1145,16 +1145,12 @@ define <4 x i32> @usubo_v4i1(<4 x i1> %a0, <4 x i1> %a1, ptr %p2) nounwind { ; ; AVX512-LABEL: usubo_v4i1: ; AVX512: # %bb.0: +; AVX512-NEXT: vpxor %xmm1, %xmm0, %xmm2 +; AVX512-NEXT: vpslld $31, %xmm2, %xmm2 +; AVX512-NEXT: vptestmd %xmm2, %xmm2, %k0 +; AVX512-NEXT: vpandn %xmm1, %xmm0, %xmm0 ; AVX512-NEXT: vpslld $31, %xmm0, %xmm0 -; AVX512-NEXT: vptestmd %xmm0, %xmm0, %k0 -; AVX512-NEXT: vpslld $31, %xmm1, %xmm1 -; AVX512-NEXT: vptestmd %xmm1, %xmm1, %k1 -; AVX512-NEXT: kxorw %k1, %k0, %k0 -; AVX512-NEXT: vptestnmd %xmm0, %xmm0, %k1 {%k1} -; AVX512-NEXT: vpcmpeqd %xmm0, %xmm0, %xmm0 -; AVX512-NEXT: vmovdqa32 %xmm0, %xmm0 {%k1} {z} -; AVX512-NEXT: kshiftlw $12, %k0, %k0 -; AVX512-NEXT: kshiftrw $12, %k0, %k0 +; AVX512-NEXT: vpsrad $31, %xmm0, %xmm0 ; AVX512-NEXT: kmovd %k0, %eax ; AVX512-NEXT: movb %al, (%rdi) ; AVX512-NEXT: retq diff --git a/llvm/test/CodeGen/X86/vector-bo-select.ll b/llvm/test/CodeGen/X86/vector-bo-select.ll index 78797b9acc2e..27aaad6353ed 100644 --- a/llvm/test/CodeGen/X86/vector-bo-select.ll +++ b/llvm/test/CodeGen/X86/vector-bo-select.ll @@ -3137,11 +3137,11 @@ define <8 x i64> @mul_v8i64_cast_cond(i8 noundef zeroext %pb, <8 x i64> noundef ; AVX512-LABEL: mul_v8i64_cast_cond: ; AVX512: # %bb.0: ; AVX512-NEXT: kmovw %edi, %k1 -; AVX512-NEXT: vpsrlq $32, %zmm1, %zmm2 -; AVX512-NEXT: vpmuludq %zmm2, %zmm0, %zmm2 -; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm3 -; AVX512-NEXT: vpmuludq %zmm1, %zmm3, %zmm3 -; AVX512-NEXT: vpaddq %zmm3, %zmm2, %zmm2 +; AVX512-NEXT: vpsrlq $32, %zmm0, %zmm2 +; AVX512-NEXT: vpmuludq %zmm1, %zmm2, %zmm2 +; AVX512-NEXT: vpsrlq $32, %zmm1, %zmm3 +; AVX512-NEXT: vpmuludq %zmm3, %zmm0, %zmm3 +; AVX512-NEXT: vpaddq %zmm2, %zmm3, %zmm2 ; AVX512-NEXT: vpsllq $32, %zmm2, %zmm2 ; AVX512-NEXT: vpmuludq %zmm1, %zmm0, %zmm1 ; AVX512-NEXT: vpaddq %zmm2, %zmm1, %zmm0 {%k1} diff --git a/llvm/test/CodeGen/X86/vector-fshr-128.ll b/llvm/test/CodeGen/X86/vector-fshr-128.ll index b839452725a9..3aaa9268a8d8 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-128.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-128.ll @@ -58,12 +58,12 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; SSE41-NEXT: psrlq %xmm4, %xmm1 ; SSE41-NEXT: pblendw {{.*#+}} xmm5 = xmm5[0,1,2,3],xmm1[4,5,6,7] ; SSE41-NEXT: pandn %xmm3, %xmm2 -; SSE41-NEXT: pshufd {{.*#+}} xmm1 = xmm2[2,3,2,3] ; SSE41-NEXT: paddq %xmm0, %xmm0 -; SSE41-NEXT: movdqa %xmm0, %xmm3 -; SSE41-NEXT: psllq %xmm1, %xmm3 +; SSE41-NEXT: movdqa %xmm0, %xmm1 +; SSE41-NEXT: psllq %xmm2, %xmm1 +; SSE41-NEXT: pshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] ; SSE41-NEXT: psllq %xmm2, %xmm0 -; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7] +; SSE41-NEXT: pblendw {{.*#+}} xmm0 = xmm1[0,1,2,3],xmm0[4,5,6,7] ; SSE41-NEXT: por %xmm5, %xmm0 ; SSE41-NEXT: retq ; @@ -76,11 +76,11 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; AVX1-NEXT: vpsrlq %xmm4, %xmm1, %xmm1 ; AVX1-NEXT: vpblendw {{.*#+}} xmm1 = xmm5[0,1,2,3],xmm1[4,5,6,7] ; AVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 -; AVX1-NEXT: vpshufd {{.*#+}} xmm3 = xmm2[2,3,2,3] ; AVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 -; AVX1-NEXT: vpsllq %xmm3, %xmm0, %xmm3 +; AVX1-NEXT: vpsllq %xmm2, %xmm0, %xmm3 +; AVX1-NEXT: vpshufd {{.*#+}} xmm2 = xmm2[2,3,2,3] ; AVX1-NEXT: vpsllq %xmm2, %xmm0, %xmm0 -; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3],xmm3[4,5,6,7] +; AVX1-NEXT: vpblendw {{.*#+}} xmm0 = xmm3[0,1,2,3],xmm0[4,5,6,7] ; AVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; AVX1-NEXT: retq ; @@ -158,13 +158,13 @@ define <2 x i64> @var_funnnel_v2i64(<2 x i64> %x, <2 x i64> %y, <2 x i64> %amt) ; XOPAVX1-LABEL: var_funnnel_v2i64: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vpmovsxbq {{.*#+}} xmm3 = [63,63] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubq %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshlq %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddq %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlq %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshlq %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubq %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshlq %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; @@ -366,13 +366,13 @@ define <4 x i32> @var_funnnel_v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %amt) ; XOPAVX1-LABEL: var_funnnel_v4i32: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [31,31,31,31] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubd %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshld %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshld %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshld %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshld %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; @@ -646,26 +646,26 @@ define <8 x i16> @var_funnnel_v8i16(<8 x i16> %x, <8 x i16> %y, <8 x i16> %amt) ; XOPAVX1-LABEL: var_funnnel_v8i16: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubw %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshlw %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddw %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlw %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshlw %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubw %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshlw %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_funnnel_v8i16: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastw {{.*#+}} xmm3 = [15,15,15,15,15,15,15,15] -; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX2-NEXT: vpsubw %xmm4, %xmm5, %xmm4 -; XOPAVX2-NEXT: vpshlw %xmm4, %xmm1, %xmm1 -; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX2-NEXT: vpaddw %xmm0, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpshlw %xmm2, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpshlw %xmm4, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX2-NEXT: vpsubw %xmm2, %xmm3, %xmm2 +; XOPAVX2-NEXT: vpshlw %xmm2, %xmm1, %xmm1 ; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: retq ; @@ -995,26 +995,26 @@ define <16 x i8> @var_funnnel_v16i8(<16 x i8> %x, <16 x i8> %y, <16 x i8> %amt) ; XOPAVX1-LABEL: var_funnnel_v16i8: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubb %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshlb %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshlb %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshlb %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubb %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshlb %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; ; XOPAVX2-LABEL: var_funnnel_v16i8: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastb {{.*#+}} xmm3 = [7,7,7,7,7,7,7,7,7,7,7,7,7,7,7,7] -; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX2-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX2-NEXT: vpsubb %xmm4, %xmm5, %xmm4 -; XOPAVX2-NEXT: vpshlb %xmm4, %xmm1, %xmm1 -; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX2-NEXT: vpaddb %xmm0, %xmm0, %xmm0 -; XOPAVX2-NEXT: vpshlb %xmm2, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpshlb %xmm4, %xmm0, %xmm0 +; XOPAVX2-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX2-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX2-NEXT: vpsubb %xmm2, %xmm3, %xmm2 +; XOPAVX2-NEXT: vpshlb %xmm2, %xmm1, %xmm1 ; XOPAVX2-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX2-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/vector-fshr-256.ll b/llvm/test/CodeGen/X86/vector-fshr-256.ll index 7b6b0ea83c7e..fc65f759f5fb 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-256.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-256.ll @@ -486,22 +486,22 @@ define <16 x i16> @var_funnnel_v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> % ; XOPAVX2-LABEL: var_funnnel_v16i16: ; XOPAVX2: # %bb.0: ; XOPAVX2-NEXT: vpbroadcastw {{.*#+}} ymm3 = [15,15,15,15,15,15,15,15,15,15,15,15,15,15,15,15] -; XOPAVX2-NEXT: vpand %ymm3, %ymm2, %ymm4 +; XOPAVX2-NEXT: vpandn %ymm3, %ymm2, %ymm4 ; XOPAVX2-NEXT: vextracti128 $1, %ymm4, %xmm5 -; XOPAVX2-NEXT: vpxor %xmm6, %xmm6, %xmm6 -; XOPAVX2-NEXT: vpsubw %xmm5, %xmm6, %xmm5 -; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm7 -; XOPAVX2-NEXT: vpshlw %xmm5, %xmm7, %xmm5 -; XOPAVX2-NEXT: vpsubw %xmm4, %xmm6, %xmm4 -; XOPAVX2-NEXT: vpshlw %xmm4, %xmm1, %xmm1 -; XOPAVX2-NEXT: vinserti128 $1, %xmm5, %ymm1, %ymm1 -; XOPAVX2-NEXT: vpandn %ymm3, %ymm2, %ymm2 -; XOPAVX2-NEXT: vextracti128 $1, %ymm2, %xmm3 ; XOPAVX2-NEXT: vpaddw %ymm0, %ymm0, %ymm0 -; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm4 -; XOPAVX2-NEXT: vpshlw %xmm3, %xmm4, %xmm3 -; XOPAVX2-NEXT: vpshlw %xmm2, %xmm0, %xmm0 -; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm0, %ymm0 +; XOPAVX2-NEXT: vextracti128 $1, %ymm0, %xmm6 +; XOPAVX2-NEXT: vpshlw %xmm5, %xmm6, %xmm5 +; XOPAVX2-NEXT: vpshlw %xmm4, %xmm0, %xmm0 +; XOPAVX2-NEXT: vinserti128 $1, %xmm5, %ymm0, %ymm0 +; XOPAVX2-NEXT: vpand %ymm3, %ymm2, %ymm2 +; XOPAVX2-NEXT: vextracti128 $1, %ymm2, %xmm3 +; XOPAVX2-NEXT: vpxor %xmm4, %xmm4, %xmm4 +; XOPAVX2-NEXT: vpsubw %xmm3, %xmm4, %xmm3 +; XOPAVX2-NEXT: vextracti128 $1, %ymm1, %xmm5 +; XOPAVX2-NEXT: vpshlw %xmm3, %xmm5, %xmm3 +; XOPAVX2-NEXT: vpsubw %xmm2, %xmm4, %xmm2 +; XOPAVX2-NEXT: vpshlw %xmm2, %xmm1, %xmm1 +; XOPAVX2-NEXT: vinserti128 $1, %xmm3, %ymm1, %ymm1 ; XOPAVX2-NEXT: vpor %ymm1, %ymm0, %ymm0 ; XOPAVX2-NEXT: retq %res = call <16 x i16> @llvm.fshr.v16i16(<16 x i16> %x, <16 x i16> %y, <16 x i16> %amt) diff --git a/llvm/test/CodeGen/X86/vector-fshr-sub128.ll b/llvm/test/CodeGen/X86/vector-fshr-sub128.ll index 0426c48aecfc..a6067a960fc0 100644 --- a/llvm/test/CodeGen/X86/vector-fshr-sub128.ll +++ b/llvm/test/CodeGen/X86/vector-fshr-sub128.ll @@ -185,13 +185,13 @@ define <2 x i32> @var_funnnel_v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %amt) ; XOPAVX1-LABEL: var_funnnel_v2i32: ; XOPAVX1: # %bb.0: ; XOPAVX1-NEXT: vbroadcastss {{.*#+}} xmm3 = [31,31,31,31] -; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm4 -; XOPAVX1-NEXT: vpxor %xmm5, %xmm5, %xmm5 -; XOPAVX1-NEXT: vpsubd %xmm4, %xmm5, %xmm4 -; XOPAVX1-NEXT: vpshld %xmm4, %xmm1, %xmm1 -; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpandn %xmm3, %xmm2, %xmm4 ; XOPAVX1-NEXT: vpaddd %xmm0, %xmm0, %xmm0 -; XOPAVX1-NEXT: vpshld %xmm2, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpshld %xmm4, %xmm0, %xmm0 +; XOPAVX1-NEXT: vpand %xmm3, %xmm2, %xmm2 +; XOPAVX1-NEXT: vpxor %xmm3, %xmm3, %xmm3 +; XOPAVX1-NEXT: vpsubd %xmm2, %xmm3, %xmm2 +; XOPAVX1-NEXT: vpshld %xmm2, %xmm1, %xmm1 ; XOPAVX1-NEXT: vpor %xmm1, %xmm0, %xmm0 ; XOPAVX1-NEXT: retq ; diff --git a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll index c54da38ef10c..75baba5f35f7 100644 --- a/llvm/test/CodeGen/X86/vector-shift-shl-128.ll +++ b/llvm/test/CodeGen/X86/vector-shift-shl-128.ll @@ -927,9 +927,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; SSE2-LABEL: constant_shift_v2i64: ; SSE2: # %bb.0: ; SSE2-NEXT: movdqa %xmm0, %xmm1 -; SSE2-NEXT: psllq $7, %xmm1 -; SSE2-NEXT: paddq %xmm0, %xmm0 -; SSE2-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; SSE2-NEXT: paddq %xmm0, %xmm1 +; SSE2-NEXT: psllq $7, %xmm0 +; SSE2-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; SSE2-NEXT: retq ; ; SSE41-LABEL: constant_shift_v2i64: @@ -975,9 +975,9 @@ define <2 x i64> @constant_shift_v2i64(<2 x i64> %a) nounwind { ; X86-SSE-LABEL: constant_shift_v2i64: ; X86-SSE: # %bb.0: ; X86-SSE-NEXT: movdqa %xmm0, %xmm1 -; X86-SSE-NEXT: psllq $7, %xmm1 -; X86-SSE-NEXT: paddq %xmm0, %xmm0 -; X86-SSE-NEXT: shufps {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3] +; X86-SSE-NEXT: paddq %xmm0, %xmm1 +; X86-SSE-NEXT: psllq $7, %xmm0 +; X86-SSE-NEXT: movsd {{.*#+}} xmm0 = xmm1[0],xmm0[1] ; X86-SSE-NEXT: retl %shift = shl <2 x i64> %a, ret <2 x i64> %shift -- GitLab From 179e174945b6c0da462c534504720c9544aebf84 Mon Sep 17 00:00:00 2001 From: Matthias Springer Date: Mon, 29 Apr 2024 13:23:37 +0200 Subject: [PATCH 212/301] [mlir][bufferization][NFC] More documentation for `runOneShotBufferize` (#90445) --- .../Transforms/OneShotAnalysis.cpp | 21 +++++++++++++++---- 1 file changed, 17 insertions(+), 4 deletions(-) diff --git a/mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp b/mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp index 531016130d1d..2d329a1f3d88 100644 --- a/mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp +++ b/mlir/lib/Dialect/Bufferization/Transforms/OneShotAnalysis.cpp @@ -1382,14 +1382,27 @@ LogicalResult bufferization::runOneShotBufferize(Operation *op, const OneShotBufferizationOptions &options, BufferizationStatistics *statistics) { + // copy-before-write deactivates the analysis. It cannot be used together with + // test-analysis-only. assert(!(options.copyBeforeWrite && options.testAnalysisOnly) && "invalid combination of bufferization flags"); - if (!options.copyBeforeWrite) { - // If a buffer is copied before every write, no analysis is needed. + + if (options.copyBeforeWrite) { + // Copy buffer before each write. No analysis is needed. + } else { + // Run One-Shot Analysis and insert buffer copies (on the tensor level) + // only where needed. This is the default and much more efficient than + // copy-before-write. if (failed(insertTensorCopies(op, options, statistics))) return failure(); + + // If test-analysis-only is set, the IR was annotated with RaW conflict + // markers (attributes) during One-Shot Analysis. + if (options.testAnalysisOnly) + return success(); } - if (options.testAnalysisOnly) - return success(); + + // Bufferize the op and its nested ops. If options.copyBeforeWrite is set, + // a new buffer copy is allocated every time a buffer is written to. return bufferizeOp(op, options, statistics); } -- GitLab From cb3174bd7895535d2f397695b5b20b1e90876997 Mon Sep 17 00:00:00 2001 From: nihui Date: Mon, 29 Apr 2024 20:18:37 +0800 Subject: [PATCH 213/301] [clang][CodeGen] fix UB in aarch64 bfloat16 scalar conversion (#89062) do not bitcast 16bit `bfloat16` to 32bit `int32_t` directly bitcast to `int16_t`, and then upcast to `int32_t` Fix ASAN runtime error when calling vcvtah_f32_bf16 `==21842==ERROR: AddressSanitizer: stack-buffer-overflow on address 0x007fda1dd063 at pc 0x005c0361c234 bp 0x007fda1dd030 sp 0x007fda1dd028 ` without patch ```c __ai __attribute__((target("bf16"))) float32_t vcvtah_f32_bf16(bfloat16_t __p0) { float32_t __ret; bfloat16_t __reint = __p0; int32_t __reint1 = *(int32_t *) &__reint << 16; __ret = *(float32_t *) &__reint1; return __ret; } ``` with this patch ```c __ai __attribute__((target("bf16"))) float32_t vcvtah_f32_bf16(bfloat16_t __p0) { float32_t __ret; bfloat16_t __reint = __p0; int32_t __reint1 = (int32_t)(*(int16_t *) &__reint) << 16; __ret = *(float32_t *) &__reint1; return __ret; } ``` fix issue https://github.com/llvm/llvm-project/issues/61983 --- clang/include/clang/Basic/arm_neon.td | 2 +- clang/test/CodeGen/arm-bf16-convert-intrinsics.c | 9 +++++---- 2 files changed, 6 insertions(+), 5 deletions(-) diff --git a/clang/include/clang/Basic/arm_neon.td b/clang/include/clang/Basic/arm_neon.td index 6d655c39360d..6390ba3f9fe5 100644 --- a/clang/include/clang/Basic/arm_neon.td +++ b/clang/include/clang/Basic/arm_neon.td @@ -275,7 +275,7 @@ def OP_VCVT_BF16_F32_HI_A32 (call "vget_low", $p0))>; def OP_CVT_F32_BF16 - : Op<(bitcast "R", (op "<<", (bitcast "int32_t", $p0), + : Op<(bitcast "R", (op "<<", (cast "int32_t", (bitcast "int16_t", $p0)), (literal "int32_t", "16")))>; //===----------------------------------------------------------------------===// diff --git a/clang/test/CodeGen/arm-bf16-convert-intrinsics.c b/clang/test/CodeGen/arm-bf16-convert-intrinsics.c index f50eaf371028..0f2c5b2546fa 100644 --- a/clang/test/CodeGen/arm-bf16-convert-intrinsics.c +++ b/clang/test/CodeGen/arm-bf16-convert-intrinsics.c @@ -426,11 +426,12 @@ bfloat16_t test_vcvth_bf16_f32(float32_t a) { // CHECK-NEXT: [[__REINT_I:%.*]] = alloca bfloat, align 2 // CHECK-NEXT: [[__REINT1_I:%.*]] = alloca i32, align 4 // CHECK-NEXT: store bfloat [[A:%.*]], ptr [[__REINT_I]], align 2 -// CHECK-NEXT: [[TMP1:%.*]] = load i32, ptr [[__REINT_I]], align 2 -// CHECK-NEXT: [[SHL_I:%.*]] = shl i32 [[TMP1]], 16 +// CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[__REINT_I]], align 2 +// CHECK-NEXT: [[CONV_I:%.*]] = sext i16 [[TMP0]] to i32 +// CHECK-NEXT: [[SHL_I:%.*]] = shl i32 [[CONV_I]], 16 // CHECK-NEXT: store i32 [[SHL_I]], ptr [[__REINT1_I]], align 4 -// CHECK-NEXT: [[TMP3:%.*]] = load float, ptr [[__REINT1_I]], align 4 -// CHECK-NEXT: ret float [[TMP3]] +// CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[__REINT1_I]], align 4 +// CHECK-NEXT: ret float [[TMP1]] // float32_t test_vcvtah_f32_bf16(bfloat16_t a) { return vcvtah_f32_bf16(a); -- GitLab From 959d98c05ecacf79bbe78bc83e6dd99a3d58cab2 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 29 Apr 2024 08:09:12 +0200 Subject: [PATCH 214/301] [clang][Interp][NFC] Fix a typo --- clang/lib/AST/Interp/Disasm.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/clang/lib/AST/Interp/Disasm.cpp b/clang/lib/AST/Interp/Disasm.cpp index 01cc88ea9a84..ccdc96a79436 100644 --- a/clang/lib/AST/Interp/Disasm.cpp +++ b/clang/lib/AST/Interp/Disasm.cpp @@ -200,7 +200,7 @@ LLVM_DUMP_METHOD void Descriptor::dump(llvm::raw_ostream &OS) const { OS << " primitive"; if (isZeroSizeArray()) - OS << " zero-size-arrary"; + OS << " zero-size-array"; else if (isUnknownSizeArray()) OS << " unknown-size-array"; -- GitLab From 6e473307ab74263e3b72e67b592579e36cee5b6b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 29 Apr 2024 10:29:02 +0200 Subject: [PATCH 215/301] [clang][Interp] Ignore FunctionDecls in compound statements --- clang/lib/AST/Interp/ByteCodeStmtGen.cpp | 3 ++- clang/test/AST/Interp/functions.cpp | 10 ++++++++++ 2 files changed, 12 insertions(+), 1 deletion(-) diff --git a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp index ec2fe39a8aea..ff91baf595f1 100644 --- a/clang/lib/AST/Interp/ByteCodeStmtGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeStmtGen.cpp @@ -332,7 +332,8 @@ bool ByteCodeStmtGen::visitCompoundStmt( template bool ByteCodeStmtGen::visitDeclStmt(const DeclStmt *DS) { for (auto *D : DS->decls()) { - if (isa(D)) + if (isa(D)) continue; const auto *VD = dyn_cast(D); diff --git a/clang/test/AST/Interp/functions.cpp b/clang/test/AST/Interp/functions.cpp index f9bb5d53634e..a4ae73e423e7 100644 --- a/clang/test/AST/Interp/functions.cpp +++ b/clang/test/AST/Interp/functions.cpp @@ -601,3 +601,13 @@ namespace FromIntegral { // both-warning {{variable length arrays}} #endif } + +namespace { + template using id = T; + template + constexpr void g() { + constexpr id f; + } + + static_assert((g(), true), ""); +} -- GitLab From f5ed9170464b73a7a0a386358e995ce8373ef153 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 29 Apr 2024 12:57:51 +0200 Subject: [PATCH 216/301] [clang][Interp] Fix creating variables for TemplateParamObjectDecls Actually initialize them with their value. While at it, fix doing it for non-primitive (only struct so far) types as well. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 99 +++++++++++++++--------- clang/lib/AST/Interp/ByteCodeExprGen.h | 1 + clang/lib/AST/Interp/Program.cpp | 3 +- clang/test/AST/Interp/records.cpp | 14 ++++ 4 files changed, 78 insertions(+), 39 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index aebefd716e27..626c30157b22 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -2372,41 +2372,8 @@ bool ByteCodeExprGen::VisitCXXUuidofExpr(const CXXUuidofExpr *E) { assert(V.isStruct()); assert(V.getStructNumBases() == 0); - // FIXME: This could be useful in visitAPValue, too. - for (unsigned I = 0, N = V.getStructNumFields(); I != N; ++I) { - const APValue &F = V.getStructField(I); - const Record::Field *RF = R->getField(I); - - if (F.isInt()) { - PrimType T = classifyPrim(RF->Decl->getType()); - if (!this->visitAPValue(F, T, E)) - return false; - if (!this->emitInitField(T, RF->Offset, E)) - return false; - } else if (F.isArray()) { - assert(RF->Desc->isPrimitiveArray()); - const auto *ArrType = RF->Decl->getType()->getAsArrayTypeUnsafe(); - PrimType ElemT = classifyPrim(ArrType->getElementType()); - assert(ArrType); - - if (!this->emitDupPtr(E)) - return false; - if (!this->emitGetPtrField(RF->Offset, E)) - return false; - - for (unsigned A = 0, AN = F.getArraySize(); A != AN; ++A) { - if (!this->visitAPValue(F.getArrayInitializedElt(A), ElemT, E)) - return false; - if (!this->emitInitElem(ElemT, A, E)) - return false; - } - - if (!this->emitPopPtr(E)) - return false; - } else { - assert(false && "I don't think this should be possible"); - } - } + if (!this->visitAPValueInitializer(V, E)) + return false; return this->emitFinishInit(E); } @@ -2971,6 +2938,54 @@ bool ByteCodeExprGen::visitAPValue(const APValue &Val, return false; } +template +bool ByteCodeExprGen::visitAPValueInitializer(const APValue &Val, + const Expr *E) { + if (Val.isStruct()) { + const Record *R = this->getRecord(E->getType()); + assert(R); + + for (unsigned I = 0, N = Val.getStructNumFields(); I != N; ++I) { + const APValue &F = Val.getStructField(I); + const Record::Field *RF = R->getField(I); + + if (F.isInt()) { + PrimType T = classifyPrim(RF->Decl->getType()); + if (!this->visitAPValue(F, T, E)) + return false; + if (!this->emitInitField(T, RF->Offset, E)) + return false; + } else if (F.isArray()) { + assert(RF->Desc->isPrimitiveArray()); + const auto *ArrType = RF->Decl->getType()->getAsArrayTypeUnsafe(); + PrimType ElemT = classifyPrim(ArrType->getElementType()); + assert(ArrType); + + if (!this->emitDupPtr(E)) + return false; + if (!this->emitGetPtrField(RF->Offset, E)) + return false; + + for (unsigned A = 0, AN = F.getArraySize(); A != AN; ++A) { + if (!this->visitAPValue(F.getArrayInitializedElt(A), ElemT, E)) + return false; + if (!this->emitInitElem(ElemT, A, E)) + return false; + } + + if (!this->emitPopPtr(E)) + return false; + } else { + assert(false && "I don't think this should be possible"); + } + } + return true; + } + // TODO: Other types. + + return false; +} + template bool ByteCodeExprGen::VisitBuiltinCallExpr(const CallExpr *E) { const Function *Func = getFunction(E->getDirectCallee()); @@ -3492,9 +3507,17 @@ bool ByteCodeExprGen::VisitDeclRefExpr(const DeclRefExpr *E) { } else if (const auto *FuncDecl = dyn_cast(D)) { const Function *F = getFunction(FuncDecl); return F && this->emitGetFnPtr(F, E); - } else if (isa(D)) { - if (std::optional Index = P.getOrCreateGlobal(D)) - return this->emitGetPtrGlobal(*Index, E); + } else if (const auto *TPOD = dyn_cast(D)) { + if (std::optional Index = P.getOrCreateGlobal(D)) { + if (!this->emitGetPtrGlobal(*Index, E)) + return false; + if (std::optional T = classify(E->getType())) { + if (!this->visitAPValue(TPOD->getValue(), *T, E)) + return false; + return this->emitInitGlobal(*T, *Index, E); + } + return this->visitAPValueInitializer(TPOD->getValue(), E); + } return false; } diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.h b/clang/lib/AST/Interp/ByteCodeExprGen.h index 4a57f76ae5b3..2c3127968a1c 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.h +++ b/clang/lib/AST/Interp/ByteCodeExprGen.h @@ -181,6 +181,7 @@ protected: bool visitVarDecl(const VarDecl *VD); /// Visit an APValue. bool visitAPValue(const APValue &Val, PrimType ValType, const Expr *E); + bool visitAPValueInitializer(const APValue &Val, const Expr *E); /// Visits an expression and converts it to a boolean. bool visitBool(const Expr *E); diff --git a/clang/lib/AST/Interp/Program.cpp b/clang/lib/AST/Interp/Program.cpp index 3773e0662f78..02075c20cf55 100644 --- a/clang/lib/AST/Interp/Program.cpp +++ b/clang/lib/AST/Interp/Program.cpp @@ -173,7 +173,8 @@ std::optional Program::createGlobal(const ValueDecl *VD, if (const auto *Var = dyn_cast(VD)) { IsStatic = Context::shouldBeGloballyIndexed(VD); IsExtern = Var->hasExternalStorage(); - } else if (isa(VD)) { + } else if (isa(VD)) { IsStatic = true; IsExtern = false; } else { diff --git a/clang/test/AST/Interp/records.cpp b/clang/test/AST/Interp/records.cpp index ba5c58c96c7b..866fa7240d2f 100644 --- a/clang/test/AST/Interp/records.cpp +++ b/clang/test/AST/Interp/records.cpp @@ -1420,3 +1420,17 @@ namespace ZeroInit { constexpr S3 s3d; // both-error {{default initialization of an object of const type 'const S3' without a user-provided default constructor}} static_assert(s3d.n == 0, ""); } + +namespace { +#if __cplusplus >= 202002L + struct C { + template constexpr C(const char (&)[N]) : n(N) {} + unsigned n; + }; + template + constexpr auto operator""_c() { return c.n; } + + constexpr auto waldo = "abc"_c; + static_assert(waldo == 4, ""); +#endif +} -- GitLab From 217c099eadfb9f2c5b5caf1af7b1ceb6a632cf74 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 29 Apr 2024 05:33:45 -0700 Subject: [PATCH 217/301] [SLP][NFC]Add a test for strided stores support, NFC. --- .../RISCV/strided-stores-vectorized.ll | 65 +++++++++++++++++++ 1 file changed, 65 insertions(+) create mode 100644 llvm/test/Transforms/SLPVectorizer/RISCV/strided-stores-vectorized.ll diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/strided-stores-vectorized.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-stores-vectorized.ll new file mode 100644 index 000000000000..0dfa45da9d87 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/strided-stores-vectorized.ll @@ -0,0 +1,65 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py +; RUN: opt -passes=slp-vectorizer -S < %s -mtriple=riscv64-unknown-linux -mattr=+v | FileCheck %s + +define void @store_reverse(ptr %p3) { +; CHECK-LABEL: @store_reverse( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = load i64, ptr [[P3:%.*]], align 8 +; CHECK-NEXT: [[ARRAYIDX1:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 8 +; CHECK-NEXT: [[TMP1:%.*]] = load i64, ptr [[ARRAYIDX1]], align 8 +; CHECK-NEXT: [[SHL:%.*]] = shl i64 [[TMP0]], [[TMP1]] +; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 7 +; CHECK-NEXT: store i64 [[SHL]], ptr [[ARRAYIDX2]], align 8 +; CHECK-NEXT: [[ARRAYIDX3:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 1 +; CHECK-NEXT: [[TMP2:%.*]] = load i64, ptr [[ARRAYIDX3]], align 8 +; CHECK-NEXT: [[ARRAYIDX4:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 9 +; CHECK-NEXT: [[TMP3:%.*]] = load i64, ptr [[ARRAYIDX4]], align 8 +; CHECK-NEXT: [[SHL5:%.*]] = shl i64 [[TMP2]], [[TMP3]] +; CHECK-NEXT: [[ARRAYIDX6:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 6 +; CHECK-NEXT: store i64 [[SHL5]], ptr [[ARRAYIDX6]], align 8 +; CHECK-NEXT: [[ARRAYIDX7:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 2 +; CHECK-NEXT: [[TMP4:%.*]] = load i64, ptr [[ARRAYIDX7]], align 8 +; CHECK-NEXT: [[ARRAYIDX8:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 10 +; CHECK-NEXT: [[TMP5:%.*]] = load i64, ptr [[ARRAYIDX8]], align 8 +; CHECK-NEXT: [[SHL9:%.*]] = shl i64 [[TMP4]], [[TMP5]] +; CHECK-NEXT: [[ARRAYIDX10:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 5 +; CHECK-NEXT: store i64 [[SHL9]], ptr [[ARRAYIDX10]], align 8 +; CHECK-NEXT: [[ARRAYIDX11:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 3 +; CHECK-NEXT: [[TMP6:%.*]] = load i64, ptr [[ARRAYIDX11]], align 8 +; CHECK-NEXT: [[ARRAYIDX12:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 11 +; CHECK-NEXT: [[TMP7:%.*]] = load i64, ptr [[ARRAYIDX12]], align 8 +; CHECK-NEXT: [[SHL13:%.*]] = shl i64 [[TMP6]], [[TMP7]] +; CHECK-NEXT: [[ARRAYIDX14:%.*]] = getelementptr inbounds i64, ptr [[P3]], i64 4 +; CHECK-NEXT: store i64 [[SHL13]], ptr [[ARRAYIDX14]], align 8 +; CHECK-NEXT: ret void +; +entry: + %0 = load i64, ptr %p3, align 8 + %arrayidx1 = getelementptr inbounds i64, ptr %p3, i64 8 + %1 = load i64, ptr %arrayidx1, align 8 + %shl = shl i64 %0, %1 + %arrayidx2 = getelementptr inbounds i64, ptr %p3, i64 7 + store i64 %shl, ptr %arrayidx2, align 8 + %arrayidx3 = getelementptr inbounds i64, ptr %p3, i64 1 + %2 = load i64, ptr %arrayidx3, align 8 + %arrayidx4 = getelementptr inbounds i64, ptr %p3, i64 9 + %3 = load i64, ptr %arrayidx4, align 8 + %shl5 = shl i64 %2, %3 + %arrayidx6 = getelementptr inbounds i64, ptr %p3, i64 6 + store i64 %shl5, ptr %arrayidx6, align 8 + %arrayidx7 = getelementptr inbounds i64, ptr %p3, i64 2 + %4 = load i64, ptr %arrayidx7, align 8 + %arrayidx8 = getelementptr inbounds i64, ptr %p3, i64 10 + %5 = load i64, ptr %arrayidx8, align 8 + %shl9 = shl i64 %4, %5 + %arrayidx10 = getelementptr inbounds i64, ptr %p3, i64 5 + store i64 %shl9, ptr %arrayidx10, align 8 + %arrayidx11 = getelementptr inbounds i64, ptr %p3, i64 3 + %6 = load i64, ptr %arrayidx11, align 8 + %arrayidx12 = getelementptr inbounds i64, ptr %p3, i64 11 + %7 = load i64, ptr %arrayidx12, align 8 + %shl13 = shl i64 %6, %7 + %arrayidx14 = getelementptr inbounds i64, ptr %p3, i64 4 + store i64 %shl13, ptr %arrayidx14, align 8 + ret void +} -- GitLab From e5c92c51e9869a6f109381d9e565b36cd4fb7b34 Mon Sep 17 00:00:00 2001 From: Ivan Kosarev Date: Mon, 29 Apr 2024 16:06:39 +0300 Subject: [PATCH 218/301] [AMDGPU][AsmParser] Do not use predicates for validation of NamedIntOperands. (#90251) Their job is to discriminate between different types of operands, not to check if they are valid. For validation we can use conversion functions. Clears the road to generating predicates automatically. Part of . --- .../AMDGPU/AsmParser/AMDGPUAsmParser.cpp | 28 +++++-------- llvm/lib/Target/AMDGPU/SIInstrInfo.td | 40 ++++++++++++++----- llvm/test/MC/AMDGPU/ds-err.s | 8 ++-- llvm/test/MC/AMDGPU/gfx11_asm_err.s | 4 +- llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s | 2 +- 5 files changed, 45 insertions(+), 37 deletions(-) diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp index c4ec7a7befd4..510f5bbf2555 100644 --- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp +++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp @@ -385,8 +385,8 @@ public: bool isIdxen() const { return isImmTy(ImmTyIdxen); } bool isAddr64() const { return isImmTy(ImmTyAddr64); } bool isOffset() const { return isImmTy(ImmTyOffset); } - bool isOffset0() const { return isImmTy(ImmTyOffset0) && isUInt<8>(getImm()); } - bool isOffset1() const { return isImmTy(ImmTyOffset1) && isUInt<8>(getImm()); } + bool isOffset0() const { return isImmTy(ImmTyOffset0); } + bool isOffset1() const { return isImmTy(ImmTyOffset1); } bool isSMEMOffsetMod() const { return isImmTy(ImmTySMEMOffsetMod); } bool isFlatOffset() const { return isImmTy(ImmTyOffset) || isImmTy(ImmTyInstOffset); } bool isGDS() const { return isImmTy(ImmTyGDS); } @@ -411,9 +411,7 @@ public: bool isOpSelHi() const { return isImmTy(ImmTyOpSelHi); } bool isNegLo() const { return isImmTy(ImmTyNegLo); } bool isNegHi() const { return isImmTy(ImmTyNegHi); } - bool isByteSel() const { - return isImmTy(ImmTyByteSel) && isUInt<2>(getImm()); - } + bool isByteSel() const { return isImmTy(ImmTyByteSel); } bool isRegOrImm() const { return isReg() || isImm(); @@ -8939,11 +8937,11 @@ bool AMDGPUOperand::isBLGP() const { } bool AMDGPUOperand::isCBSZ() const { - return isImm() && getImmTy() == ImmTyCBSZ && isUInt<3>(getImm()); + return isImm() && getImmTy() == ImmTyCBSZ; } bool AMDGPUOperand::isABID() const { - return isImm() && getImmTy() == ImmTyABID && isUInt<4>(getImm()); + return isImm() && getImmTy() == ImmTyABID; } bool AMDGPUOperand::isS16Imm() const { @@ -9670,25 +9668,17 @@ bool AMDGPUOperand::isEndpgm() const { return isImmTy(ImmTyEndpgm); } // LDSDIR //===----------------------------------------------------------------------===// -bool AMDGPUOperand::isWaitVDST() const { - return isImmTy(ImmTyWaitVDST) && isUInt<4>(getImm()); -} +bool AMDGPUOperand::isWaitVDST() const { return isImmTy(ImmTyWaitVDST); } -bool AMDGPUOperand::isWaitVAVDst() const { - return isImmTy(ImmTyWaitVAVDst) && isUInt<4>(getImm()); -} +bool AMDGPUOperand::isWaitVAVDst() const { return isImmTy(ImmTyWaitVAVDst); } -bool AMDGPUOperand::isWaitVMVSrc() const { - return isImmTy(ImmTyWaitVMVSrc) && isUInt<1>(getImm()); -} +bool AMDGPUOperand::isWaitVMVSrc() const { return isImmTy(ImmTyWaitVMVSrc); } //===----------------------------------------------------------------------===// // VINTERP //===----------------------------------------------------------------------===// -bool AMDGPUOperand::isWaitEXP() const { - return isImmTy(ImmTyWaitEXP) && isUInt<3>(getImm()); -} +bool AMDGPUOperand::isWaitEXP() const { return isImmTy(ImmTyWaitEXP); } //===----------------------------------------------------------------------===// // Split Barrier diff --git a/llvm/lib/Target/AMDGPU/SIInstrInfo.td b/llvm/lib/Target/AMDGPU/SIInstrInfo.td index bf6cfe90ebfb..7189e6e40506 100644 --- a/llvm/lib/Target/AMDGPU/SIInstrInfo.td +++ b/llvm/lib/Target/AMDGPU/SIInstrInfo.td @@ -1000,8 +1000,10 @@ def SDWAVopcDst : BoolRC { } class NamedIntOperand + string name = NAME> : CustomOperand { + string Validator = "[](int64_t V) { return true; }"; + string ConvertMethod = "[](int64_t &V) { return "#Validator#"(V); }"; let ParserMethod = "[this](OperandVector &Operands) -> ParseStatus { "# "return parseIntWithPrefix(\""#Prefix#"\", Operands, "# @@ -1045,8 +1047,10 @@ class ArrayOperand0 let ImmTy = "ImmTyOffset" in def flat_offset : CustomOperand; def Offset : NamedIntOperand; +let Validator = "isUInt<8>" in { def Offset0 : NamedIntOperand; def Offset1 : NamedIntOperand; +} def gds : NamedBitOperand<"gds", "GDS">; @@ -1103,27 +1107,41 @@ let DefaultValue = "0xf" in { def DppRowMask : NamedIntOperand; def DppBankMask : NamedIntOperand; } -def DppBoundCtrl : NamedIntOperand bool { return convertDppBoundCtrl(BC); }">; +def DppBoundCtrl : NamedIntOperand { + let ConvertMethod = "[this] (int64_t &BC) -> bool { return convertDppBoundCtrl(BC); }"; +} let DecoderMethod = "decodeDpp8FI" in def Dpp8FI : NamedIntOperand; def Dpp16FI : NamedIntOperand; def blgp : CustomOperand; -def CBSZ : NamedIntOperand; -def ABID : NamedIntOperand; - +def CBSZ : NamedIntOperand { + let Validator = "isUInt<3>"; +} +def ABID : NamedIntOperand { + let Validator = "isUInt<4>"; +} def hwreg : CustomOperand; def exp_tgt : CustomOperand; -def WaitVDST : NamedIntOperand; -def WaitEXP : NamedIntOperand; -def WaitVAVDst : NamedIntOperand; -def WaitVMVSrc : NamedIntOperand; +def WaitVDST : NamedIntOperand { + let Validator = "isUInt<4>"; +} +def WaitEXP : NamedIntOperand { + let Validator = "isUInt<3>"; +} +def WaitVAVDst : NamedIntOperand { + let Validator = "isUInt<4>"; +} +def WaitVMVSrc : NamedIntOperand { + let Validator = "isUInt<1>"; +} -def ByteSel : NamedIntOperand; +def ByteSel : NamedIntOperand { + let Validator = "isUInt<2>"; +} class KImmFPOperand : ImmOperand { let OperandNamespace = "AMDGPU"; diff --git a/llvm/test/MC/AMDGPU/ds-err.s b/llvm/test/MC/AMDGPU/ds-err.s index 2d25fdf5e302..c31f4c759395 100644 --- a/llvm/test/MC/AMDGPU/ds-err.s +++ b/llvm/test/MC/AMDGPU/ds-err.s @@ -18,19 +18,19 @@ ds_write2_b32 v2, v4, v6 offset0:4 offset0:8 ds_write2_b32 v2, v4, v6 offset1:4 offset1:8 // offset0 too big -// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset0 value. ds_write2_b32 v2, v4, v6 offset0:1000000000 // offset0 too big -// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset0 value. ds_write2_b32 v2, v4, v6 offset0:0x100 // offset1 too big -// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset1 value. ds_write2_b32 v2, v4, v6 offset1:1000000000 // offset1 too big -// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid operand for instruction +// CHECK: :[[@LINE+1]]:{{[0-9]+}}: error: invalid offset1 value. ds_write2_b32 v2, v4, v6 offset1:0x100 //===----------------------------------------------------------------------===// diff --git a/llvm/test/MC/AMDGPU/gfx11_asm_err.s b/llvm/test/MC/AMDGPU/gfx11_asm_err.s index 3ec31626be5b..7f99afe01925 100644 --- a/llvm/test/MC/AMDGPU/gfx11_asm_err.s +++ b/llvm/test/MC/AMDGPU/gfx11_asm_err.s @@ -22,13 +22,13 @@ s_delay_alu instid0(VALU_DEP_1) | SALU_CYCLE_1) // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: expected a left parenthesis lds_direct_load v15 wait_vdst:16 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid wait_vdst value. lds_direct_load v15 wait_vdst // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction v_interp_p10_f32 v0, v1, v2, v3 wait_exp:8 -// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid wait_exp value. v_interp_p2_f32 v0, -v1, v2, v3 wait_exp // GFX11: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction diff --git a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s index 31ed577ac0a2..a9dd290ea67d 100644 --- a/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s +++ b/llvm/test/MC/AMDGPU/gfx12_asm_vop3_err.s @@ -103,6 +103,6 @@ v_permlane16_var_b32 v5, v1, v2 op_sel:[0, 0, 1] // GFX12-NEXT:{{^}} ^ v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4 -// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction +// GFX12: :[[@LINE-1]]:{{[0-9]+}}: error: invalid byte_sel value. // GFX12-NEXT:{{^}}v_cvt_sr_bf8_f32 v1, v2, v3 byte_sel:4 // GFX12-NEXT:{{^}} ^ -- GitLab From 8e17c84836b08be9a23d76c2cc234777712347de Mon Sep 17 00:00:00 2001 From: Shilei Tian Date: Mon, 29 Apr 2024 09:08:54 -0400 Subject: [PATCH 219/301] [AMDGPU][ISel] Set trunc store action to expand for v4f32->v4bf16 (#90427) --- llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp | 5 + .../CodeGen/AMDGPU/fp_trunc_store_bf16.ll | 426 ++++++++++++++++++ 2 files changed, 431 insertions(+) create mode 100644 llvm/test/CodeGen/AMDGPU/fp_trunc_store_bf16.ll diff --git a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp index 7993b6312111..7f4a2437f62e 100644 --- a/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ b/llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp @@ -313,11 +313,16 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(const TargetMachine &TM, setTruncStoreAction(MVT::f32, MVT::bf16, Expand); setTruncStoreAction(MVT::f32, MVT::f16, Expand); + setTruncStoreAction(MVT::v2f32, MVT::v2bf16, Expand); setTruncStoreAction(MVT::v2f32, MVT::v2f16, Expand); setTruncStoreAction(MVT::v3f32, MVT::v3f16, Expand); + setTruncStoreAction(MVT::v4f32, MVT::v4bf16, Expand); setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand); + setTruncStoreAction(MVT::v8f32, MVT::v8bf16, Expand); setTruncStoreAction(MVT::v8f32, MVT::v8f16, Expand); + setTruncStoreAction(MVT::v16f32, MVT::v16bf16, Expand); setTruncStoreAction(MVT::v16f32, MVT::v16f16, Expand); + setTruncStoreAction(MVT::v32f32, MVT::v32bf16, Expand); setTruncStoreAction(MVT::v32f32, MVT::v32f16, Expand); setTruncStoreAction(MVT::f64, MVT::bf16, Expand); diff --git a/llvm/test/CodeGen/AMDGPU/fp_trunc_store_bf16.ll b/llvm/test/CodeGen/AMDGPU/fp_trunc_store_bf16.ll new file mode 100644 index 000000000000..5aaff773689f --- /dev/null +++ b/llvm/test/CodeGen/AMDGPU/fp_trunc_store_bf16.ll @@ -0,0 +1,426 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 4 +; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx90a %s -o - | FileCheck %s + +define void @v2(<2 x float> %num, ptr addrspace(1) %p) { +; CHECK-LABEL: v2: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfe_u32 v4, v0, 16, 1 +; CHECK-NEXT: s_movk_i32 s4, 0x7fff +; CHECK-NEXT: v_add3_u32 v4, v4, v0, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v0 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v4, v5, vcc +; CHECK-NEXT: v_bfe_u32 v4, v1, 16, 1 +; CHECK-NEXT: v_add3_u32 v4, v4, v1, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v1 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v4, v5, vcc +; CHECK-NEXT: s_mov_b32 s4, 0x7060302 +; CHECK-NEXT: v_perm_b32 v0, v1, v0, s4 +; CHECK-NEXT: global_store_dword v[2:3], v0, off +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + %conv = fptrunc <2 x float> %num to <2 x bfloat> + store <2 x bfloat> %conv, ptr addrspace(1) %p, align 8 + ret void +} + +define void @v4(<4 x float> %num, ptr addrspace(1) %p) { +; CHECK-LABEL: v4: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfe_u32 v6, v2, 16, 1 +; CHECK-NEXT: s_movk_i32 s4, 0x7fff +; CHECK-NEXT: v_add3_u32 v6, v6, v2, s4 +; CHECK-NEXT: v_or_b32_e32 v7, 0x400000, v2 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; CHECK-NEXT: v_cndmask_b32_e32 v2, v6, v7, vcc +; CHECK-NEXT: v_bfe_u32 v6, v3, 16, 1 +; CHECK-NEXT: v_add3_u32 v6, v6, v3, s4 +; CHECK-NEXT: v_or_b32_e32 v7, 0x400000, v3 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v3, v6, v7, vcc +; CHECK-NEXT: s_mov_b32 s5, 0x7060302 +; CHECK-NEXT: v_perm_b32 v3, v3, v2, s5 +; CHECK-NEXT: v_bfe_u32 v2, v0, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v0, s4 +; CHECK-NEXT: v_or_b32_e32 v6, 0x400000, v0 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v6, vcc +; CHECK-NEXT: v_bfe_u32 v2, v1, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v1, s4 +; CHECK-NEXT: v_or_b32_e32 v6, 0x400000, v1 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v6, vcc +; CHECK-NEXT: v_perm_b32 v2, v1, v0, s5 +; CHECK-NEXT: global_store_dwordx2 v[4:5], v[2:3], off +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + %conv = fptrunc <4 x float> %num to <4 x bfloat> + store <4 x bfloat> %conv, ptr addrspace(1) %p, align 8 + ret void +} + +define void @v8(<8 x float> %num, ptr addrspace(1) %p) { +; CHECK-LABEL: v8: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfe_u32 v10, v6, 16, 1 +; CHECK-NEXT: s_movk_i32 s4, 0x7fff +; CHECK-NEXT: v_add3_u32 v10, v10, v6, s4 +; CHECK-NEXT: v_or_b32_e32 v11, 0x400000, v6 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 +; CHECK-NEXT: v_cndmask_b32_e32 v6, v10, v11, vcc +; CHECK-NEXT: v_bfe_u32 v10, v7, 16, 1 +; CHECK-NEXT: v_add3_u32 v10, v10, v7, s4 +; CHECK-NEXT: v_or_b32_e32 v11, 0x400000, v7 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; CHECK-NEXT: v_cndmask_b32_e32 v7, v10, v11, vcc +; CHECK-NEXT: s_mov_b32 s5, 0x7060302 +; CHECK-NEXT: v_perm_b32 v7, v7, v6, s5 +; CHECK-NEXT: v_bfe_u32 v6, v4, 16, 1 +; CHECK-NEXT: v_add3_u32 v6, v6, v4, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v4 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v6, v10, vcc +; CHECK-NEXT: v_bfe_u32 v6, v5, 16, 1 +; CHECK-NEXT: v_add3_u32 v6, v6, v5, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v5 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v10, vcc +; CHECK-NEXT: v_perm_b32 v6, v5, v4, s5 +; CHECK-NEXT: v_bfe_u32 v4, v2, 16, 1 +; CHECK-NEXT: v_add3_u32 v4, v4, v2, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v2 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; CHECK-NEXT: v_bfe_u32 v4, v3, 16, 1 +; CHECK-NEXT: v_add3_u32 v4, v4, v3, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v3 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc +; CHECK-NEXT: v_perm_b32 v5, v3, v2, s5 +; CHECK-NEXT: v_bfe_u32 v2, v0, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v0, s4 +; CHECK-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; CHECK-NEXT: v_bfe_u32 v2, v1, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v1, s4 +; CHECK-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc +; CHECK-NEXT: v_perm_b32 v4, v1, v0, s5 +; CHECK-NEXT: global_store_dwordx4 v[8:9], v[4:7], off +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + %conv = fptrunc <8 x float> %num to <8 x bfloat> + store <8 x bfloat> %conv, ptr addrspace(1) %p, align 8 + ret void +} + +define void @v16(<16 x float> %num, ptr addrspace(1) %p) { +; CHECK-LABEL: v16: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: v_bfe_u32 v18, v6, 16, 1 +; CHECK-NEXT: s_movk_i32 s4, 0x7fff +; CHECK-NEXT: v_add3_u32 v18, v18, v6, s4 +; CHECK-NEXT: v_or_b32_e32 v19, 0x400000, v6 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 +; CHECK-NEXT: v_cndmask_b32_e32 v6, v18, v19, vcc +; CHECK-NEXT: v_bfe_u32 v18, v7, 16, 1 +; CHECK-NEXT: v_add3_u32 v18, v18, v7, s4 +; CHECK-NEXT: v_or_b32_e32 v19, 0x400000, v7 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; CHECK-NEXT: v_cndmask_b32_e32 v7, v18, v19, vcc +; CHECK-NEXT: s_mov_b32 s5, 0x7060302 +; CHECK-NEXT: v_perm_b32 v7, v7, v6, s5 +; CHECK-NEXT: v_bfe_u32 v6, v4, 16, 1 +; CHECK-NEXT: v_add3_u32 v6, v6, v4, s4 +; CHECK-NEXT: v_or_b32_e32 v18, 0x400000, v4 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v6, v18, vcc +; CHECK-NEXT: v_bfe_u32 v6, v5, 16, 1 +; CHECK-NEXT: v_add3_u32 v6, v6, v5, s4 +; CHECK-NEXT: v_or_b32_e32 v18, 0x400000, v5 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v18, vcc +; CHECK-NEXT: v_perm_b32 v6, v5, v4, s5 +; CHECK-NEXT: v_bfe_u32 v4, v2, 16, 1 +; CHECK-NEXT: v_add3_u32 v4, v4, v2, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v2 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; CHECK-NEXT: v_bfe_u32 v4, v3, 16, 1 +; CHECK-NEXT: v_add3_u32 v4, v4, v3, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v3 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc +; CHECK-NEXT: v_perm_b32 v5, v3, v2, s5 +; CHECK-NEXT: v_bfe_u32 v2, v0, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v0, s4 +; CHECK-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; CHECK-NEXT: v_bfe_u32 v2, v1, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v1, s4 +; CHECK-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc +; CHECK-NEXT: v_perm_b32 v4, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v14, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v14, s4 +; CHECK-NEXT: v_or_b32_e32 v1, 0x400000, v14 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CHECK-NEXT: v_bfe_u32 v1, v15, 16, 1 +; CHECK-NEXT: v_add3_u32 v1, v1, v15, s4 +; CHECK-NEXT: v_or_b32_e32 v2, 0x400000, v15 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CHECK-NEXT: v_perm_b32 v3, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v12, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v12, s4 +; CHECK-NEXT: v_or_b32_e32 v1, 0x400000, v12 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CHECK-NEXT: v_bfe_u32 v1, v13, 16, 1 +; CHECK-NEXT: v_add3_u32 v1, v1, v13, s4 +; CHECK-NEXT: v_or_b32_e32 v2, 0x400000, v13 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CHECK-NEXT: v_perm_b32 v2, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v10, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v10, s4 +; CHECK-NEXT: v_or_b32_e32 v1, 0x400000, v10 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CHECK-NEXT: v_bfe_u32 v1, v11, 16, 1 +; CHECK-NEXT: v_add3_u32 v1, v1, v11, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v11 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc +; CHECK-NEXT: v_perm_b32 v1, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v8, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v8, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v8 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 +; CHECK-NEXT: v_bfe_u32 v8, v9, 16, 1 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc +; CHECK-NEXT: v_add3_u32 v8, v8, v9, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v9 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; CHECK-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc +; CHECK-NEXT: v_perm_b32 v0, v8, v0, s5 +; CHECK-NEXT: global_store_dwordx4 v[16:17], v[0:3], off offset:16 +; CHECK-NEXT: global_store_dwordx4 v[16:17], v[4:7], off +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + %conv = fptrunc <16 x float> %num to <16 x bfloat> + store <16 x bfloat> %conv, ptr addrspace(1) %p, align 8 + ret void +} + +define void @v32(<32 x float> %num, ptr addrspace(1) %p) { +; CHECK-LABEL: v32: +; CHECK: ; %bb.0: ; %entry +; CHECK-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0) +; CHECK-NEXT: buffer_load_dword v33, off, s[0:3], s32 offset:8 +; CHECK-NEXT: buffer_load_dword v32, off, s[0:3], s32 offset:4 +; CHECK-NEXT: buffer_load_dword v31, off, s[0:3], s32 +; CHECK-NEXT: v_bfe_u32 v34, v6, 16, 1 +; CHECK-NEXT: s_movk_i32 s4, 0x7fff +; CHECK-NEXT: v_add3_u32 v34, v34, v6, s4 +; CHECK-NEXT: v_or_b32_e32 v35, 0x400000, v6 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v6, v6 +; CHECK-NEXT: v_cndmask_b32_e32 v6, v34, v35, vcc +; CHECK-NEXT: v_bfe_u32 v34, v7, 16, 1 +; CHECK-NEXT: v_add3_u32 v34, v34, v7, s4 +; CHECK-NEXT: v_or_b32_e32 v35, 0x400000, v7 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v7, v7 +; CHECK-NEXT: v_cndmask_b32_e32 v7, v34, v35, vcc +; CHECK-NEXT: s_mov_b32 s5, 0x7060302 +; CHECK-NEXT: v_perm_b32 v7, v7, v6, s5 +; CHECK-NEXT: v_bfe_u32 v6, v4, 16, 1 +; CHECK-NEXT: v_add3_u32 v6, v6, v4, s4 +; CHECK-NEXT: v_or_b32_e32 v34, 0x400000, v4 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v4, v4 +; CHECK-NEXT: v_cndmask_b32_e32 v4, v6, v34, vcc +; CHECK-NEXT: v_bfe_u32 v6, v5, 16, 1 +; CHECK-NEXT: v_add3_u32 v6, v6, v5, s4 +; CHECK-NEXT: v_or_b32_e32 v34, 0x400000, v5 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v5, v5 +; CHECK-NEXT: v_cndmask_b32_e32 v5, v6, v34, vcc +; CHECK-NEXT: v_perm_b32 v6, v5, v4, s5 +; CHECK-NEXT: v_bfe_u32 v4, v2, 16, 1 +; CHECK-NEXT: v_add3_u32 v4, v4, v2, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v2 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v2, v2 +; CHECK-NEXT: v_cndmask_b32_e32 v2, v4, v5, vcc +; CHECK-NEXT: v_bfe_u32 v4, v3, 16, 1 +; CHECK-NEXT: v_add3_u32 v4, v4, v3, s4 +; CHECK-NEXT: v_or_b32_e32 v5, 0x400000, v3 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v3, v3 +; CHECK-NEXT: v_cndmask_b32_e32 v3, v4, v5, vcc +; CHECK-NEXT: v_perm_b32 v5, v3, v2, s5 +; CHECK-NEXT: v_bfe_u32 v2, v0, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v0, s4 +; CHECK-NEXT: v_or_b32_e32 v3, 0x400000, v0 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v0, v0 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v2, v3, vcc +; CHECK-NEXT: v_bfe_u32 v2, v1, 16, 1 +; CHECK-NEXT: v_add3_u32 v2, v2, v1, s4 +; CHECK-NEXT: v_or_b32_e32 v3, 0x400000, v1 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v1, v1 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v2, v3, vcc +; CHECK-NEXT: v_perm_b32 v4, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v14, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v14, s4 +; CHECK-NEXT: v_or_b32_e32 v1, 0x400000, v14 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v14, v14 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CHECK-NEXT: v_bfe_u32 v1, v15, 16, 1 +; CHECK-NEXT: v_add3_u32 v1, v1, v15, s4 +; CHECK-NEXT: v_or_b32_e32 v2, 0x400000, v15 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v15, v15 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CHECK-NEXT: v_perm_b32 v3, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v12, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v12, s4 +; CHECK-NEXT: v_or_b32_e32 v1, 0x400000, v12 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v12, v12 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CHECK-NEXT: v_bfe_u32 v1, v13, 16, 1 +; CHECK-NEXT: v_add3_u32 v1, v1, v13, s4 +; CHECK-NEXT: v_or_b32_e32 v2, 0x400000, v13 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v13, v13 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v2, vcc +; CHECK-NEXT: v_perm_b32 v2, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v10, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v10, s4 +; CHECK-NEXT: v_or_b32_e32 v1, 0x400000, v10 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v10, v10 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v1, vcc +; CHECK-NEXT: v_bfe_u32 v1, v11, 16, 1 +; CHECK-NEXT: v_add3_u32 v1, v1, v11, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v11 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v11, v11 +; CHECK-NEXT: v_cndmask_b32_e32 v1, v1, v10, vcc +; CHECK-NEXT: v_perm_b32 v1, v1, v0, s5 +; CHECK-NEXT: v_bfe_u32 v0, v8, 16, 1 +; CHECK-NEXT: v_add3_u32 v0, v0, v8, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v8 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v8, v8 +; CHECK-NEXT: v_bfe_u32 v8, v9, 16, 1 +; CHECK-NEXT: v_cndmask_b32_e32 v0, v0, v10, vcc +; CHECK-NEXT: v_add3_u32 v8, v8, v9, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v9 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v9, v9 +; CHECK-NEXT: v_cndmask_b32_e32 v8, v8, v10, vcc +; CHECK-NEXT: v_perm_b32 v0, v8, v0, s5 +; CHECK-NEXT: v_bfe_u32 v8, v22, 16, 1 +; CHECK-NEXT: v_add3_u32 v8, v8, v22, s4 +; CHECK-NEXT: v_or_b32_e32 v9, 0x400000, v22 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v22, v22 +; CHECK-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc +; CHECK-NEXT: v_bfe_u32 v9, v23, 16, 1 +; CHECK-NEXT: v_add3_u32 v9, v9, v23, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v23 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v23, v23 +; CHECK-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc +; CHECK-NEXT: v_perm_b32 v11, v9, v8, s5 +; CHECK-NEXT: v_bfe_u32 v8, v20, 16, 1 +; CHECK-NEXT: v_add3_u32 v8, v8, v20, s4 +; CHECK-NEXT: v_or_b32_e32 v9, 0x400000, v20 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v20, v20 +; CHECK-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc +; CHECK-NEXT: v_bfe_u32 v9, v21, 16, 1 +; CHECK-NEXT: v_add3_u32 v9, v9, v21, s4 +; CHECK-NEXT: v_or_b32_e32 v10, 0x400000, v21 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v21, v21 +; CHECK-NEXT: v_cndmask_b32_e32 v9, v9, v10, vcc +; CHECK-NEXT: v_perm_b32 v10, v9, v8, s5 +; CHECK-NEXT: v_bfe_u32 v8, v18, 16, 1 +; CHECK-NEXT: v_add3_u32 v8, v8, v18, s4 +; CHECK-NEXT: v_or_b32_e32 v9, 0x400000, v18 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v18, v18 +; CHECK-NEXT: v_cndmask_b32_e32 v8, v8, v9, vcc +; CHECK-NEXT: v_bfe_u32 v9, v19, 16, 1 +; CHECK-NEXT: v_add3_u32 v9, v9, v19, s4 +; CHECK-NEXT: v_or_b32_e32 v12, 0x400000, v19 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v19, v19 +; CHECK-NEXT: v_cndmask_b32_e32 v9, v9, v12, vcc +; CHECK-NEXT: v_perm_b32 v9, v9, v8, s5 +; CHECK-NEXT: v_bfe_u32 v8, v16, 16, 1 +; CHECK-NEXT: v_add3_u32 v8, v8, v16, s4 +; CHECK-NEXT: v_or_b32_e32 v12, 0x400000, v16 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v16, v16 +; CHECK-NEXT: v_cndmask_b32_e32 v8, v8, v12, vcc +; CHECK-NEXT: v_bfe_u32 v12, v17, 16, 1 +; CHECK-NEXT: v_add3_u32 v12, v12, v17, s4 +; CHECK-NEXT: v_or_b32_e32 v13, 0x400000, v17 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v17, v17 +; CHECK-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc +; CHECK-NEXT: v_perm_b32 v8, v12, v8, s5 +; CHECK-NEXT: v_bfe_u32 v12, v30, 16, 1 +; CHECK-NEXT: v_add3_u32 v12, v12, v30, s4 +; CHECK-NEXT: v_or_b32_e32 v13, 0x400000, v30 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v30, v30 +; CHECK-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: v_bfe_u32 v13, v31, 16, 1 +; CHECK-NEXT: v_add3_u32 v13, v13, v31, s4 +; CHECK-NEXT: v_or_b32_e32 v14, 0x400000, v31 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v31, v31 +; CHECK-NEXT: v_cndmask_b32_e32 v13, v13, v14, vcc +; CHECK-NEXT: v_perm_b32 v15, v13, v12, s5 +; CHECK-NEXT: v_bfe_u32 v12, v28, 16, 1 +; CHECK-NEXT: v_add3_u32 v12, v12, v28, s4 +; CHECK-NEXT: v_or_b32_e32 v13, 0x400000, v28 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v28, v28 +; CHECK-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc +; CHECK-NEXT: v_bfe_u32 v13, v29, 16, 1 +; CHECK-NEXT: v_add3_u32 v13, v13, v29, s4 +; CHECK-NEXT: v_or_b32_e32 v14, 0x400000, v29 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v29, v29 +; CHECK-NEXT: v_cndmask_b32_e32 v13, v13, v14, vcc +; CHECK-NEXT: v_perm_b32 v14, v13, v12, s5 +; CHECK-NEXT: v_bfe_u32 v12, v26, 16, 1 +; CHECK-NEXT: v_add3_u32 v12, v12, v26, s4 +; CHECK-NEXT: v_or_b32_e32 v13, 0x400000, v26 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v26, v26 +; CHECK-NEXT: v_cndmask_b32_e32 v12, v12, v13, vcc +; CHECK-NEXT: v_bfe_u32 v13, v27, 16, 1 +; CHECK-NEXT: v_add3_u32 v13, v13, v27, s4 +; CHECK-NEXT: v_or_b32_e32 v16, 0x400000, v27 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v27, v27 +; CHECK-NEXT: v_cndmask_b32_e32 v13, v13, v16, vcc +; CHECK-NEXT: v_perm_b32 v13, v13, v12, s5 +; CHECK-NEXT: v_bfe_u32 v12, v24, 16, 1 +; CHECK-NEXT: v_add3_u32 v12, v12, v24, s4 +; CHECK-NEXT: v_or_b32_e32 v16, 0x400000, v24 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v24, v24 +; CHECK-NEXT: v_cndmask_b32_e32 v12, v12, v16, vcc +; CHECK-NEXT: v_bfe_u32 v16, v25, 16, 1 +; CHECK-NEXT: v_add3_u32 v16, v16, v25, s4 +; CHECK-NEXT: v_or_b32_e32 v17, 0x400000, v25 +; CHECK-NEXT: v_cmp_u_f32_e32 vcc, v25, v25 +; CHECK-NEXT: v_cndmask_b32_e32 v16, v16, v17, vcc +; CHECK-NEXT: v_perm_b32 v12, v16, v12, s5 +; CHECK-NEXT: global_store_dwordx4 v[32:33], v[12:15], off offset:48 +; CHECK-NEXT: global_store_dwordx4 v[32:33], v[8:11], off offset:32 +; CHECK-NEXT: global_store_dwordx4 v[32:33], v[0:3], off offset:16 +; CHECK-NEXT: global_store_dwordx4 v[32:33], v[4:7], off +; CHECK-NEXT: s_waitcnt vmcnt(0) +; CHECK-NEXT: s_setpc_b64 s[30:31] +entry: + %conv = fptrunc <32 x float> %num to <32 x bfloat> + store <32 x bfloat> %conv, ptr addrspace(1) %p, align 8 + ret void +} -- GitLab From de6b2b9dbf9a18e9e160cff60f7eb238909a931c Mon Sep 17 00:00:00 2001 From: Kohei Asano <32860920+khei4@users.noreply.github.com> Date: Mon, 29 Apr 2024 22:14:22 +0900 Subject: [PATCH 220/301] [Clang][Docs] use CommonOptionsParser::create instead of protected constructor on libTooling tutorial (NFC) (#70427) This patch fixes the code example on CommonOptionParser on https://intel.github.io/llvm-docs/clang/LibTooling.html CommonOptionParser's constructor is protected, and we can use `CommonOptionParser::create` instead of that. It seems like the LibASTMatcher tutorial already uses that. https://clang.llvm.org/docs/LibASTMatchersTutorial.html --------- Co-authored-by: Sirraide --- clang/docs/LibTooling.rst | 22 +++++++++++++++++----- 1 file changed, 17 insertions(+), 5 deletions(-) diff --git a/clang/docs/LibTooling.rst b/clang/docs/LibTooling.rst index df50dcebf9b8..87d84321ab28 100644 --- a/clang/docs/LibTooling.rst +++ b/clang/docs/LibTooling.rst @@ -63,15 +63,22 @@ and automatic location of the compilation database using source files paths. #include "llvm/Support/CommandLine.h" using namespace clang::tooling; + using namespace llvm; // Apply a custom category to all command-line options so that they are the // only ones displayed. - static llvm::cl::OptionCategory MyToolCategory("my-tool options"); + static cl::OptionCategory MyToolCategory("my-tool options"); int main(int argc, const char **argv) { - // CommonOptionsParser constructor will parse arguments and create a - // CompilationDatabase. In case of error it will terminate the program. - CommonOptionsParser OptionsParser(argc, argv, MyToolCategory); + // CommonOptionsParser::create will parse arguments and create a + // CompilationDatabase. + auto ExpectedParser = CommonOptionsParser::create(argc, argv, MyToolCategory); + if (!ExpectedParser) { + // Fail gracefully for unsupported options. + llvm::errs() << ExpectedParser.takeError(); + return 1; + } + CommonOptionsParser& OptionsParser = ExpectedParser.get(); // Use OptionsParser.getCompilations() and OptionsParser.getSourcePathList() // to retrieve CompilationDatabase and the list of input file paths. @@ -133,7 +140,12 @@ version of this example tool is also checked into the clang tree at static cl::extrahelp MoreHelp("\nMore help text...\n"); int main(int argc, const char **argv) { - CommonOptionsParser OptionsParser(argc, argv, MyToolCategory); + auto ExpectedParser = CommonOptionsParser::create(argc, argv, MyToolCategory); + if (!ExpectedParser) { + llvm::errs() << ExpectedParser.takeError(); + return 1; + } + CommonOptionsParser& OptionsParser = ExpectedParser.get(); ClangTool Tool(OptionsParser.getCompilations(), OptionsParser.getSourcePathList()); return Tool.run(newFrontendActionFactory().get()); -- GitLab From 8d5386669ed63548daf1bee415596582d6d78d7d Mon Sep 17 00:00:00 2001 From: David Truby Date: Mon, 29 Apr 2024 14:16:25 +0100 Subject: [PATCH 221/301] [flang] Generate main only when a Fortran program statement is present (#89938) This patch changes the behaviour for flang to only create and link to a `main` entry point when the Fortran code has a program statement in it. This means that flang-new can be used to link even when the program is a mixed C/Fortran code with `main` present in C and no entry point present in Fortran. This also removes the `-fno-fortran-main` flag as this no longer has any functionality. --- clang/include/clang/Driver/Options.td | 6 - clang/lib/Driver/ToolChains/CommonArgs.cpp | 110 +---------- clang/lib/Driver/ToolChains/Flang.cpp | 9 - flang/docs/FlangDriver.md | 32 +--- .../Builder/Runtime/EnvironmentDefaults.h | 3 +- .../flang/Optimizer/Builder/Runtime/Main.h | 28 +++ flang/lib/Lower/Bridge.cpp | 7 +- flang/lib/Optimizer/Builder/CMakeLists.txt | 1 + .../Builder/Runtime/EnvironmentDefaults.cpp | 7 +- flang/lib/Optimizer/Builder/Runtime/Main.cpp | 62 +++++++ flang/runtime/CMakeLists.txt | 1 - flang/runtime/FortranMain/CMakeLists.txt | 23 --- flang/runtime/FortranMain/Fortran_main.c | 23 --- flang/test/CMakeLists.txt | 1 - flang/test/Driver/driver-help-hidden.f90 | 172 ++++++++++++++++++ flang/test/Driver/dynamic-linker.f90 | 2 - flang/test/Driver/emit-mlir.f90 | 10 + flang/test/Driver/linker-flags.f90 | 8 - .../test/Driver/msvc-dependent-lib-flags.f90 | 4 - flang/test/Driver/no-duplicate-main.f90 | 2 - flang/tools/flang-driver/CMakeLists.txt | 1 - lld/COFF/MinGW.cpp | 1 - 22 files changed, 287 insertions(+), 226 deletions(-) create mode 100644 flang/include/flang/Optimizer/Builder/Runtime/Main.h create mode 100644 flang/lib/Optimizer/Builder/Runtime/Main.cpp delete mode 100644 flang/runtime/FortranMain/CMakeLists.txt delete mode 100644 flang/runtime/FortranMain/Fortran_main.c create mode 100644 flang/test/Driver/driver-help-hidden.f90 diff --git a/clang/include/clang/Driver/Options.td b/clang/include/clang/Driver/Options.td index 086aedefc118..263d1edf141a 100644 --- a/clang/include/clang/Driver/Options.td +++ b/clang/include/clang/Driver/Options.td @@ -6589,12 +6589,6 @@ def J : JoinedOrSeparate<["-"], "J">, Group, Alias; -let Visibility = [FlangOption] in { -def no_fortran_main : Flag<["-"], "fno-fortran-main">, - Visibility<[FlangOption]>, Group, - HelpText<"Do not include Fortran_main.a (provided by Flang) when linking">; -} // let Visibility = [ FlangOption ] - //===----------------------------------------------------------------------===// // FC1 Options //===----------------------------------------------------------------------===// diff --git a/clang/lib/Driver/ToolChains/CommonArgs.cpp b/clang/lib/Driver/ToolChains/CommonArgs.cpp index b65b96db16bd..fec11c7e716f 100644 --- a/clang/lib/Driver/ToolChains/CommonArgs.cpp +++ b/clang/lib/Driver/ToolChains/CommonArgs.cpp @@ -1191,118 +1191,10 @@ bool tools::addOpenMPRuntime(const Compilation &C, ArgStringList &CmdArgs, return true; } -/// Determines if --whole-archive is active in the list of arguments. -static bool isWholeArchivePresent(const ArgList &Args) { - bool WholeArchiveActive = false; - for (auto *Arg : Args.filtered(options::OPT_Wl_COMMA)) { - if (Arg) { - for (StringRef ArgValue : Arg->getValues()) { - if (ArgValue == "--whole-archive") - WholeArchiveActive = true; - if (ArgValue == "--no-whole-archive") - WholeArchiveActive = false; - } - } - } - - return WholeArchiveActive; -} - -/// Determine if driver is invoked to create a shared object library (-static) -static bool isSharedLinkage(const ArgList &Args) { - return Args.hasArg(options::OPT_shared); -} - -/// Determine if driver is invoked to create a static object library (-shared) -static bool isStaticLinkage(const ArgList &Args) { - return Args.hasArg(options::OPT_static); -} - -/// Add Fortran runtime libs for MSVC -static void addFortranRuntimeLibsMSVC(const ArgList &Args, - llvm::opt::ArgStringList &CmdArgs) { - unsigned RTOptionID = options::OPT__SLASH_MT; - if (auto *rtl = Args.getLastArg(options::OPT_fms_runtime_lib_EQ)) { - RTOptionID = llvm::StringSwitch(rtl->getValue()) - .Case("static", options::OPT__SLASH_MT) - .Case("static_dbg", options::OPT__SLASH_MTd) - .Case("dll", options::OPT__SLASH_MD) - .Case("dll_dbg", options::OPT__SLASH_MDd) - .Default(options::OPT__SLASH_MT); - } - switch (RTOptionID) { - case options::OPT__SLASH_MT: - CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static.lib"); - break; - case options::OPT__SLASH_MTd: - CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.static_dbg.lib"); - break; - case options::OPT__SLASH_MD: - CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic.lib"); - break; - case options::OPT__SLASH_MDd: - CmdArgs.push_back("/WHOLEARCHIVE:Fortran_main.dynamic_dbg.lib"); - break; - } -} - -// Add FortranMain runtime lib -static void addFortranMain(const ToolChain &TC, const ArgList &Args, - llvm::opt::ArgStringList &CmdArgs) { - // 0. Shared-library linkage - // If we are attempting to link a library, we should not add - // -lFortran_main.a to the link line, as the `main` symbol is not - // required for a library and should also be provided by one of - // the translation units of the code that this shared library - // will be linked against eventually. - if (isSharedLinkage(Args) || isStaticLinkage(Args)) { - return; - } - - // 1. MSVC - if (TC.getTriple().isKnownWindowsMSVCEnvironment()) { - addFortranRuntimeLibsMSVC(Args, CmdArgs); - return; - } - - // 2. GNU and similar - const Driver &D = TC.getDriver(); - const char *FortranMainLinkFlag = "-lFortran_main"; - - // Warn if the user added `-lFortran_main` - this library is an implementation - // detail of Flang and should be handled automaticaly by the driver. - for (const char *arg : CmdArgs) { - if (strncmp(arg, FortranMainLinkFlag, strlen(FortranMainLinkFlag)) == 0) - D.Diag(diag::warn_drv_deprecated_custom) - << FortranMainLinkFlag - << "see the Flang driver documentation for correct usage"; - } - - // The --whole-archive option needs to be part of the link line to make - // sure that the main() function from Fortran_main.a is pulled in by the - // linker. However, it shouldn't be used if it's already active. - // TODO: Find an equivalent of `--whole-archive` for Darwin and AIX. - if (!isWholeArchivePresent(Args) && !TC.getTriple().isMacOSX() && - !TC.getTriple().isOSAIX()) { - CmdArgs.push_back("--whole-archive"); - CmdArgs.push_back(FortranMainLinkFlag); - CmdArgs.push_back("--no-whole-archive"); - return; - } - - CmdArgs.push_back(FortranMainLinkFlag); -} - /// Add Fortran runtime libs void tools::addFortranRuntimeLibs(const ToolChain &TC, const ArgList &Args, llvm::opt::ArgStringList &CmdArgs) { - // 1. Link FortranMain - // FortranMain depends on FortranRuntime, so needs to be listed first. If - // -fno-fortran-main has been passed, skip linking Fortran_main.a - if (!Args.hasArg(options::OPT_no_fortran_main)) - addFortranMain(TC, Args, CmdArgs); - - // 2. Link FortranRuntime and FortranDecimal + // Link FortranRuntime and FortranDecimal // These are handled earlier on Windows by telling the frontend driver to // add the correct libraries to link against as dependents in the object // file. diff --git a/clang/lib/Driver/ToolChains/Flang.cpp b/clang/lib/Driver/ToolChains/Flang.cpp index 6d93c1f3d703..8955b9fb653c 100644 --- a/clang/lib/Driver/ToolChains/Flang.cpp +++ b/clang/lib/Driver/ToolChains/Flang.cpp @@ -282,7 +282,6 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args, assert(TC.getTriple().isKnownWindowsMSVCEnvironment() && "can only add VS runtime library on Windows!"); // if -fno-fortran-main has been passed, skip linking Fortran_main.a - bool LinkFortranMain = !Args.hasArg(options::OPT_no_fortran_main); if (TC.getTriple().isKnownWindowsMSVCEnvironment()) { CmdArgs.push_back(Args.MakeArgString( "--dependent-lib=" + TC.getCompilerRTBasename(Args, "builtins"))); @@ -300,8 +299,6 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args, case options::OPT__SLASH_MT: CmdArgs.push_back("-D_MT"); CmdArgs.push_back("--dependent-lib=libcmt"); - if (LinkFortranMain) - CmdArgs.push_back("--dependent-lib=Fortran_main.static.lib"); CmdArgs.push_back("--dependent-lib=FortranRuntime.static.lib"); CmdArgs.push_back("--dependent-lib=FortranDecimal.static.lib"); break; @@ -309,8 +306,6 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args, CmdArgs.push_back("-D_MT"); CmdArgs.push_back("-D_DEBUG"); CmdArgs.push_back("--dependent-lib=libcmtd"); - if (LinkFortranMain) - CmdArgs.push_back("--dependent-lib=Fortran_main.static_dbg.lib"); CmdArgs.push_back("--dependent-lib=FortranRuntime.static_dbg.lib"); CmdArgs.push_back("--dependent-lib=FortranDecimal.static_dbg.lib"); break; @@ -318,8 +313,6 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args, CmdArgs.push_back("-D_MT"); CmdArgs.push_back("-D_DLL"); CmdArgs.push_back("--dependent-lib=msvcrt"); - if (LinkFortranMain) - CmdArgs.push_back("--dependent-lib=Fortran_main.dynamic.lib"); CmdArgs.push_back("--dependent-lib=FortranRuntime.dynamic.lib"); CmdArgs.push_back("--dependent-lib=FortranDecimal.dynamic.lib"); break; @@ -328,8 +321,6 @@ static void processVSRuntimeLibrary(const ToolChain &TC, const ArgList &Args, CmdArgs.push_back("-D_DEBUG"); CmdArgs.push_back("-D_DLL"); CmdArgs.push_back("--dependent-lib=msvcrtd"); - if (LinkFortranMain) - CmdArgs.push_back("--dependent-lib=Fortran_main.dynamic_dbg.lib"); CmdArgs.push_back("--dependent-lib=FortranRuntime.dynamic_dbg.lib"); CmdArgs.push_back("--dependent-lib=FortranDecimal.dynamic_dbg.lib"); break; diff --git a/flang/docs/FlangDriver.md b/flang/docs/FlangDriver.md index ac120b4ff09b..351595ac0afd 100644 --- a/flang/docs/FlangDriver.md +++ b/flang/docs/FlangDriver.md @@ -179,46 +179,20 @@ like this: ``` $ flang -v -o example example.o -"/usr/bin/ld" [...] example.o [...] "--whole-archive" "-lFortran_main" -"--no-whole-archive" "-lFortranRuntime" "-lFortranDecimal" [...] +"/usr/bin/ld" [...] example.o [...] "-lFortranRuntime" "-lFortranDecimal" [...] ``` The automatically added libraries are: -* `Fortran_main`: Provides the main entry point `main` that then invokes - `_QQmain` with the Fortran program unit. This library has a dependency to - the `FortranRuntime` library. * `FortranRuntime`: Provides most of the Flang runtime library. * `FortranDecimal`: Provides operations for decimal numbers. -The default is that, when using Flang as the linker, one of the Fortran -translation units provides the program unit and therefore it is assumed that -Fortran is the main code part (calling into C/C++ routines via `BIND (C)` -interfaces). When composing the linker commandline, Flang uses -`--whole-archive` and `--no-whole-archive` (Windows: `/WHOLEARCHIVE:`, -Darwin & AIX: *not implemented yet*) to make sure that all for `Fortran_main` -is processed by the linker. This is done to issue a proper error message when -multiple definitions of `main` occur. This happens, for instance, when linking -a code that has a Fortran program unit with a C/C++ code that also defines a -`main` function. A user may be required to explicitly provide the C++ runtime -libraries at link time (e.g., via `-lstdc++` for STL) - If the code is C/C++ based and invokes Fortran routines, one can either use Clang or Flang as the linker driver. If Clang is used, it will automatically all required runtime libraries needed by C++ (e.g., for STL) to the linker invocation. In this case, one has to explicitly provide the Fortran runtime libraries -`FortranRuntime` and/or `FortranDecimal`. An alternative is to use Flang to link -and use the `-fno-fortran-main` flag. This flag removes -`Fortran_main` from the linker stage and hence requires one of the C/C++ -translation units to provide a definition of the `main` function. In this case, -it may be required to explicitly supply C++ runtime libraries as mentioned above. - -When creating shared or static libraries using Flang with `-shared` or `-static` -flag, Fortran_main is automatically removed from the linker stage (i.e., -`-fno-fortran-main` is on by default). It is assumed that when creating a -static or shared library, the generated library does not need a `main` -function, as a final link stage will occur that will provide the `Fortran_main` -library when creating the final executable. +`FortranRuntime` and/or `FortranDecimal`. An alternative is to use Flang to link. +In this case, it may be required to explicitly supply C++ runtime libraries. On Darwin, the logical root where the system libraries are located (sysroot) must be specified. This can be done with the CMake build flag `DEFAULT_SYSROOT` diff --git a/flang/include/flang/Optimizer/Builder/Runtime/EnvironmentDefaults.h b/flang/include/flang/Optimizer/Builder/Runtime/EnvironmentDefaults.h index 18a24bad3960..216d3bcec137 100755 --- a/flang/include/flang/Optimizer/Builder/Runtime/EnvironmentDefaults.h +++ b/flang/include/flang/Optimizer/Builder/Runtime/EnvironmentDefaults.h @@ -22,6 +22,7 @@ namespace fir { class FirOpBuilder; +class GlobalOp; } // namespace fir namespace mlir { @@ -37,7 +38,7 @@ namespace fir::runtime { /// Create the list of environment variable defaults for the runtime to set. The /// form of the generated list is defined in the runtime header file /// environment-default-list.h -void genEnvironmentDefaults( +fir::GlobalOp genEnvironmentDefaults( fir::FirOpBuilder &builder, mlir::Location loc, const std::vector &envDefaults); diff --git a/flang/include/flang/Optimizer/Builder/Runtime/Main.h b/flang/include/flang/Optimizer/Builder/Runtime/Main.h new file mode 100644 index 000000000000..62faf46e1fc7 --- /dev/null +++ b/flang/include/flang/Optimizer/Builder/Runtime/Main.h @@ -0,0 +1,28 @@ +//===-- Main.h - generate main runtime API calls ----------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#ifndef FORTRAN_OPTIMIZER_BUILDER_RUNTIME_MAIN_H +#define FORTRAN_OPTIMIZER_BUILDER_RUNTIME_MAIN_H + +namespace mlir { +class Location; +} // namespace mlir + +namespace fir { +class FirOpBuilder; +class GlobalOp; +} // namespace fir + +namespace fir::runtime { + +void genMain(fir::FirOpBuilder &builder, mlir::Location loc, + fir::GlobalOp &env); + +} + +#endif // FORTRAN_OPTIMIZER_BUILDER_RUNTIME_MAIN_H diff --git a/flang/lib/Lower/Bridge.cpp b/flang/lib/Lower/Bridge.cpp index c05bf010b2bd..b42909eaaacc 100644 --- a/flang/lib/Lower/Bridge.cpp +++ b/flang/lib/Lower/Bridge.cpp @@ -36,6 +36,7 @@ #include "flang/Optimizer/Builder/Runtime/Character.h" #include "flang/Optimizer/Builder/Runtime/Derived.h" #include "flang/Optimizer/Builder/Runtime/EnvironmentDefaults.h" +#include "flang/Optimizer/Builder/Runtime/Main.h" #include "flang/Optimizer/Builder/Runtime/Ragged.h" #include "flang/Optimizer/Builder/Runtime/Stop.h" #include "flang/Optimizer/Builder/Todo.h" @@ -359,8 +360,10 @@ public: // not need to be generated even if no defaults are specified. // However, generating main or changing when the runtime reads // environment variables is required to do so. - fir::runtime::genEnvironmentDefaults(*builder, toLocation(), - bridge.getEnvironmentDefaults()); + auto env = fir::runtime::genEnvironmentDefaults( + *builder, toLocation(), bridge.getEnvironmentDefaults()); + + fir::runtime::genMain(*builder, toLocation(), env); }); finalizeOpenACCLowering(); diff --git a/flang/lib/Optimizer/Builder/CMakeLists.txt b/flang/lib/Optimizer/Builder/CMakeLists.txt index 06339b116cd8..6d0aeb429d35 100644 --- a/flang/lib/Optimizer/Builder/CMakeLists.txt +++ b/flang/lib/Optimizer/Builder/CMakeLists.txt @@ -23,6 +23,7 @@ add_flang_library(FIRBuilder Runtime/Execute.cpp Runtime/Inquiry.cpp Runtime/Intrinsics.cpp + Runtime/Main.cpp Runtime/Numeric.cpp Runtime/Pointer.cpp Runtime/Ragged.cpp diff --git a/flang/lib/Optimizer/Builder/Runtime/EnvironmentDefaults.cpp b/flang/lib/Optimizer/Builder/Runtime/EnvironmentDefaults.cpp index a11b9339681e..6e280ac0c06c 100755 --- a/flang/lib/Optimizer/Builder/Runtime/EnvironmentDefaults.cpp +++ b/flang/lib/Optimizer/Builder/Runtime/EnvironmentDefaults.cpp @@ -13,7 +13,7 @@ #include "flang/Optimizer/Support/InternalNames.h" #include "llvm/ADT/ArrayRef.h" -void fir::runtime::genEnvironmentDefaults( +fir::GlobalOp fir::runtime::genEnvironmentDefaults( fir::FirOpBuilder &builder, mlir::Location loc, const std::vector &envDefaults) { std::string envDefaultListPtrName = @@ -34,14 +34,13 @@ void fir::runtime::genEnvironmentDefaults( // If no defaults were specified, initialize with a null pointer. if (envDefaults.empty()) { - builder.createGlobalConstant( + return builder.createGlobalConstant( loc, envDefaultListRefTy, envDefaultListPtrName, [&](fir::FirOpBuilder &builder) { mlir::Value nullVal = builder.createNullConstant(loc, envDefaultListRefTy); builder.create(loc, nullVal); }); - return; } // Create the Item list. @@ -99,7 +98,7 @@ void fir::runtime::genEnvironmentDefaults( envDefaultListBuilder, linkOnce); // Define the pointer to the list used by the runtime. - builder.createGlobalConstant( + return builder.createGlobalConstant( loc, envDefaultListRefTy, envDefaultListPtrName, [&](fir::FirOpBuilder &builder) { mlir::Value addr = builder.create( diff --git a/flang/lib/Optimizer/Builder/Runtime/Main.cpp b/flang/lib/Optimizer/Builder/Runtime/Main.cpp new file mode 100644 index 000000000000..3b24fbca9cdb --- /dev/null +++ b/flang/lib/Optimizer/Builder/Runtime/Main.cpp @@ -0,0 +1,62 @@ +//===-- Main.cpp - generate main runtime API calls --------------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "flang/Optimizer/Builder/Runtime/Main.h" +#include "flang/Optimizer/Builder/BoxValue.h" +#include "flang/Optimizer/Builder/FIRBuilder.h" +#include "flang/Optimizer/Builder/Runtime/RTBuilder.h" +#include "flang/Optimizer/Dialect/FIROps.h" +#include "flang/Optimizer/Dialect/FIRType.h" +#include "flang/Runtime/main.h" +#include "flang/Runtime/stop.h" + +using namespace Fortran::runtime; + +/// Create a `int main(...)` that calls the Fortran entry point +void fir::runtime::genMain(fir::FirOpBuilder &builder, mlir::Location loc, + fir::GlobalOp &env) { + auto *context = builder.getContext(); + auto argcTy = builder.getDefaultIntegerType(); + auto ptrTy = mlir::LLVM::LLVMPointerType::get(context); + + // void ProgramStart(int argc, char** argv, char** envp, + // _QQEnvironmentDefaults* env) + auto startFn = builder.createFunction( + loc, RTNAME_STRING(ProgramStart), + mlir::FunctionType::get(context, {argcTy, ptrTy, ptrTy, ptrTy}, {})); + // void ProgramStop() + auto stopFn = + builder.createFunction(loc, RTNAME_STRING(ProgramEndStatement), + mlir::FunctionType::get(context, {}, {})); + + // int main(int argc, char** argv, char** envp) + auto mainFn = builder.createFunction( + loc, "main", + mlir::FunctionType::get(context, {argcTy, ptrTy, ptrTy}, argcTy)); + // void _QQmain() + auto qqMainFn = builder.createFunction( + loc, "_QQmain", mlir::FunctionType::get(context, {}, {})); + + mainFn.setPublic(); + + auto *block = mainFn.addEntryBlock(); + mlir::OpBuilder::InsertionGuard insertGuard(builder); + builder.setInsertionPointToStart(block); + + llvm::SmallVector args(block->getArguments()); + auto envAddr = + builder.create(loc, env.getType(), env.getSymbol()); + args.push_back(envAddr); + + builder.create(loc, startFn, args); + builder.create(loc, qqMainFn); + builder.create(loc, stopFn); + + mlir::Value ret = builder.createIntegerConstant(loc, argcTy, 0); + builder.create(loc, ret); +} diff --git a/flang/runtime/CMakeLists.txt b/flang/runtime/CMakeLists.txt index bdd0e07bbfd4..9f25c5dfcad1 100644 --- a/flang/runtime/CMakeLists.txt +++ b/flang/runtime/CMakeLists.txt @@ -103,7 +103,6 @@ append(${NO_LTO_FLAGS} CMAKE_CXX_FLAGS) add_definitions(-U_GLIBCXX_ASSERTIONS) add_definitions(-U_LIBCPP_ENABLE_ASSERTIONS) -add_subdirectory(FortranMain) add_subdirectory(Float128Math) set(sources diff --git a/flang/runtime/FortranMain/CMakeLists.txt b/flang/runtime/FortranMain/CMakeLists.txt deleted file mode 100644 index deb7bd10acf5..000000000000 --- a/flang/runtime/FortranMain/CMakeLists.txt +++ /dev/null @@ -1,23 +0,0 @@ -add_flang_library(Fortran_main STATIC INSTALL_WITH_TOOLCHAIN - Fortran_main.c -) -if (DEFINED MSVC) - set(CMAKE_MSVC_RUNTIME_LIBRARY MultiThreaded) - add_flang_library(Fortran_main.static STATIC INSTALL_WITH_TOOLCHAIN - Fortran_main.c - ) - set(CMAKE_MSVC_RUNTIME_LIBRARY MultiThreadedDLL) - add_flang_library(Fortran_main.dynamic STATIC INSTALL_WITH_TOOLCHAIN - Fortran_main.c - ) - set(CMAKE_MSVC_RUNTIME_LIBRARY MultiThreadedDebug) - add_flang_library(Fortran_main.static_dbg STATIC INSTALL_WITH_TOOLCHAIN - Fortran_main.c - ) - set(CMAKE_MSVC_RUNTIME_LIBRARY MultiThreadedDebugDLL) - add_flang_library(Fortran_main.dynamic_dbg STATIC INSTALL_WITH_TOOLCHAIN - Fortran_main.c - ) - add_dependencies(Fortran_main Fortran_main.static Fortran_main.dynamic - Fortran_main.static_dbg Fortran_main.dynamic_dbg) -endif() diff --git a/flang/runtime/FortranMain/Fortran_main.c b/flang/runtime/FortranMain/Fortran_main.c deleted file mode 100644 index 5d3eaced001e..000000000000 --- a/flang/runtime/FortranMain/Fortran_main.c +++ /dev/null @@ -1,23 +0,0 @@ -//===-- runtime/FortranMain/Fortran_main.c --------------------------------===// -// -// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. -// See https://llvm.org/LICENSE.txt for license information. -// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception -// -//===----------------------------------------------------------------------===// - -#include "flang/Runtime/main.h" -#include "flang/Runtime/stop.h" - -/* main entry into PROGRAM */ -void _QQmain(void); - -extern const struct EnvironmentDefaultList *_QQEnvironmentDefaults; - -/* C main stub */ -int main(int argc, const char *argv[], const char *envp[]) { - RTNAME(ProgramStart)(argc, argv, envp, _QQEnvironmentDefaults); - _QQmain(); - RTNAME(ProgramEndStatement)(); - return 0; -} diff --git a/flang/test/CMakeLists.txt b/flang/test/CMakeLists.txt index 7d96a72e5f36..7e036ad539df 100644 --- a/flang/test/CMakeLists.txt +++ b/flang/test/CMakeLists.txt @@ -62,7 +62,6 @@ set(FLANG_TEST_DEPENDS llvm-readobj split-file FortranRuntime - Fortran_main FortranDecimal ) if (LLVM_ENABLE_PLUGINS AND NOT WIN32) diff --git a/flang/test/Driver/driver-help-hidden.f90 b/flang/test/Driver/driver-help-hidden.f90 new file mode 100644 index 000000000000..706b2cb6c245 --- /dev/null +++ b/flang/test/Driver/driver-help-hidden.f90 @@ -0,0 +1,172 @@ + +!-------------------------- +! FLANG DRIVER (flang-new) +!-------------------------- +! RUN: %flang --help-hidden 2>&1 | FileCheck %s +! RUN: not %flang -help-hidden 2>&1 | FileCheck %s --check-prefix=ERROR-FLANG + +!---------------------------------------- +! FLANG FRONTEND DRIVER (flang-new -fc1) +!---------------------------------------- +! RUN: not %flang_fc1 --help-hidden 2>&1 | FileCheck %s --check-prefix=ERROR-FLANG-FC1 +! RUN: not %flang_fc1 -help-hidden 2>&1 | FileCheck %s --check-prefix=ERROR-FLANG-FC1 + +! CHECK:USAGE: flang-new +! CHECK-EMPTY: +! CHECK-NEXT: DRIVER OPTIONS: +! CHECK-NEXT: --driver-mode= Set the driver mode to either 'gcc', 'g++', 'cpp', 'cl' or 'flang' +! CHECK-EMPTY: +! CHECK-NEXT:OPTIONS: +! CHECK-NEXT: -### Print (but do not run) the commands to run for this compilation +! CHECK-NEXT: -ccc-print-phases Dump list of actions to perform +! CHECK-NEXT: -cpp Enable predefined and command line preprocessor macros +! CHECK-NEXT: -c Only run preprocess, compile, and assemble steps +! CHECK-NEXT: -dM Print macro definitions in -E mode instead of normal output +! CHECK-NEXT: -dumpmachine Display the compiler's target processor +! CHECK-NEXT: -dumpversion Display the version of the compiler +! CHECK-NEXT: -D = Define to (or 1 if omitted) +! CHECK-NEXT: -emit-llvm Use the LLVM representation for assembler and object files +! CHECK-NEXT: -E Only run the preprocessor +! CHECK-NEXT: -falternative-parameter-statement +! CHECK-NEXT: Enable the old style PARAMETER statement +! CHECK-NEXT: -fapprox-func Allow certain math function calls to be replaced with an approximately equivalent calculation +! CHECK-NEXT: -fbackslash Specify that backslash in string introduces an escape character +! CHECK-NEXT: -fcolor-diagnostics Enable colors in diagnostics +! CHECK-NEXT: -fconvert= Set endian conversion of data for unformatted files +! CHECK-NEXT: -fdefault-double-8 Set the default double precision kind to an 8 byte wide type +! CHECK-NEXT: -fdefault-integer-8 Set the default integer and logical kind to an 8 byte wide type +! CHECK-NEXT: -fdefault-real-8 Set the default real kind to an 8 byte wide type +! CHECK-NEXT: -ffast-math Allow aggressive, lossy floating-point optimizations +! CHECK-NEXT: -ffixed-form Process source files in fixed form +! CHECK-NEXT: -ffixed-line-length= +! CHECK-NEXT: Use as character line width in fixed mode +! CHECK-NEXT: -ffp-contract= Form fused FP ops (e.g. FMAs) +! CHECK-NEXT: -ffree-form Process source files in free form +! CHECK-NEXT: -fhonor-infinities Specify that floating-point optimizations are not allowed that assume arguments and results are not +-inf. +! CHECK-NEXT: -fhonor-nans Specify that floating-point optimizations are not allowed that assume arguments and results are not NANs. +! CHECK-NEXT: -fimplicit-none No implicit typing allowed unless overridden by IMPLICIT statements +! CHECK-NEXT: -finput-charset= Specify the default character set for source files +! CHECK-NEXT: -fintegrated-as Enable the integrated assembler +! CHECK-NEXT: -fintrinsic-modules-path +! CHECK-NEXT: Specify where to find the compiled intrinsic modules +! CHECK-NEXT: -flang-deprecated-no-hlfir +! CHECK-NEXT: Do not use HLFIR lowering (deprecated) +! CHECK-NEXT: -flang-experimental-hlfir +! CHECK-NEXT: Use HLFIR lowering (experimental) +! CHECK-NEXT: -flarge-sizes Use INTEGER(KIND=8) for the result type in size-related intrinsics +! CHECK-NEXT: -flogical-abbreviations Enable logical abbreviations +! CHECK-NEXT: -flto=auto Enable LTO in 'full' mode +! CHECK-NEXT: -flto=jobserver Enable LTO in 'full' mode +! CHECK-NEXT: -flto= Set LTO mode +! CHECK-NEXT: -flto Enable LTO in 'full' mode +! CHECK-NEXT: -fms-runtime-lib= +! CHECK-NEXT: Select Windows run-time library +! CHECK-NEXT: -fno-automatic Implies the SAVE attribute for non-automatic local objects in subprograms unless RECURSIVE +! CHECK-NEXT: -fno-color-diagnostics Disable colors in diagnostics +! CHECK-NEXT: -fno-integrated-as Disable the integrated assembler +! CHECK-NEXT: -fno-lto Disable LTO mode (default) +! CHECK-NEXT: -fno-ppc-native-vector-element-order +! CHECK-NEXT: Specifies PowerPC non-native vector element order +! CHECK-NEXT: -fno-rtlib-add-rpath Do not add -rpath with architecture-specific resource directory to the linker flags. When --hip-link is specified, do not add -rpath with HIP runtime library directory to the linker flags +! CHECK-NEXT: -fno-signed-zeros Allow optimizations that ignore the sign of floating point zeros +! CHECK-NEXT: -fno-stack-arrays Allocate array temporaries on the heap (default) +! CHECK-NEXT: -fno-version-loops-for-stride +! CHECK-NEXT: Do not create unit-strided loops (default) +! CHECK-NEXT: -fomit-frame-pointer Omit the frame pointer from functions that don't need it. Some stack unwinding cases, such as profilers and sanitizers, may prefer specifying -fno-omit-frame-pointer. On many targets, -O1 and higher omit the frame pointer by default. -m[no-]omit-leaf-frame-pointer takes precedence for leaf functions +! CHECK-NEXT: -fopenacc Enable OpenACC +! CHECK-NEXT: -fopenmp-assume-no-nested-parallelism +! CHECK-NEXT: Assert no nested parallel regions in the GPU +! CHECK-NEXT: -fopenmp-assume-no-thread-state +! CHECK-NEXT: Assert no thread in a parallel region modifies an ICV +! CHECK-NEXT: -fopenmp-target-debug Enable debugging in the OpenMP offloading device RTL +! CHECK-NEXT: -fopenmp-targets= +! CHECK-NEXT: Specify comma-separated list of triples OpenMP offloading targets to be supported +! CHECK-NEXT: -fopenmp-version= +! CHECK-NEXT: Set OpenMP version (e.g. 45 for OpenMP 4.5, 51 for OpenMP 5.1). Default value is 11 for Flang +! CHECK-NEXT: -fopenmp Parse OpenMP pragmas and generate parallel code. +! CHECK-NEXT: -foptimization-record-file= +! CHECK-NEXT: Specify the output name of the file containing the optimization remarks. Implies -fsave-optimization-record. On Darwin platforms, this cannot be used with multiple -arch options. +! CHECK-NEXT: -foptimization-record-passes= +! CHECK-NEXT: Only include passes which match a specified regular expression in the generated optimization record (by default, include all passes) +! CHECK-NEXT: -fpass-plugin= Load pass plugin from a dynamic shared object file (only with new pass manager). +! CHECK-NEXT: -fppc-native-vector-element-order +! CHECK-NEXT: Specifies PowerPC native vector element order (default) +! CHECK-NEXT: -freciprocal-math Allow division operations to be reassociated +! CHECK-NEXT: -fropi Generate read-only position independent code (ARM only) +! CHECK-NEXT: -frtlib-add-rpath Add -rpath with architecture-specific resource directory to the linker flags. When --hip-link is specified, also add -rpath with HIP runtime library directory to the linker flags +! CHECK-NEXT: -frwpi Generate read-write position independent code (ARM only) +! CHECK-NEXT: -fsave-optimization-record= +! CHECK-NEXT: Generate an optimization record file in a specific format +! CHECK-NEXT: -fsave-optimization-record +! CHECK-NEXT: Generate a YAML optimization record file +! CHECK-NEXT: -fstack-arrays Attempt to allocate array temporaries on the stack, no matter their size +! CHECK-NEXT: -fsyntax-only Run the preprocessor, parser and semantic analysis stages +! CHECK-NEXT: -funderscoring Appends one trailing underscore to external names +! CHECK-NEXT: -fveclib= Use the given vector functions library +! CHECK-NEXT: -fversion-loops-for-stride +! CHECK-NEXT: Create unit-strided versions of loops +! CHECK-NEXT: -fxor-operator Enable .XOR. as a synonym of .NEQV. +! CHECK-NEXT: --gcc-install-dir= +! CHECK-NEXT: Use GCC installation in the specified directory. The directory ends with path components like 'lib{,32,64}/gcc{,-cross}/$triple/$version'. Note: executables (e.g. ld) used by the compiler are not overridden by the selected GCC installation +! CHECK-NEXT: --gcc-toolchain= Specify a directory where Flang can find 'lib{,32,64}/gcc{,-cross}/$triple/$version'. Flang will use the GCC installation with the largest version +! CHECK-NEXT: -gline-directives-only Emit debug line info directives only +! CHECK-NEXT: -gline-tables-only Emit debug line number tables only +! CHECK-NEXT: -gpulibc Link the LLVM C Library for GPUs +! CHECK-NEXT: -g Generate source-level debug information +! CHECK-NEXT: --help-hidden Display help for hidden options +! CHECK-NEXT: -help Display available options +! CHECK-NEXT: -isysroot Set the system root directory (usually /) +! CHECK-NEXT: -I Add directory to the end of the list of include search paths +! CHECK-NEXT: -L Add directory to library search path +! CHECK-NEXT: -march= For a list of available architectures for the target use '-mcpu=help' +! CHECK-NEXT: -mcode-object-version= +! CHECK-NEXT: Specify code object ABI version. Defaults to 5. (AMDGPU only) +! CHECK-NEXT: -mcpu= For a list of available CPUs for the target use '-mcpu=help' +! CHECK-NEXT: -mllvm= Alias for -mllvm +! CHECK-NEXT: -mllvm Additional arguments to forward to LLVM's option processing +! CHECK-NEXT: -mmlir Additional arguments to forward to MLIR's option processing +! CHECK-NEXT: -mno-outline-atomics Don't generate local calls to out-of-line atomic operations +! CHECK-NEXT: -module-dir Put MODULE files in +! CHECK-NEXT: -moutline-atomics Generate local calls to out-of-line atomic operations +! CHECK-NEXT: -mrvv-vector-bits= +! CHECK-NEXT: Specify the size in bits of an RVV vector register +! CHECK-NEXT: -msve-vector-bits= +! CHECK-NEXT: Specify the size in bits of an SVE vector register. Defaults to the vector length agnostic value of "scalable". (AArch64 only) +! CHECK-NEXT: --no-offload-arch= +! CHECK-NEXT: Remove CUDA/HIP offloading device architecture (e.g. sm_35, gfx906) from the list of devices to compile for. 'all' resets the list to its default value. +! CHECK-NEXT: -nocpp Disable predefined and command line preprocessor macros +! CHECK-NEXT: -nogpulib Do not link device library for CUDA/HIP device compilation +! CHECK-NEXT: --offload-arch= Specify an offloading device architecture for CUDA, HIP, or OpenMP. (e.g. sm_35). If 'native' is used the compiler will detect locally installed architectures. For HIP offloading, the device architecture can be followed by target ID features delimited by a colon (e.g. gfx908:xnack+:sramecc-). May be specified more than once. +! CHECK-NEXT: --offload-device-only Only compile for the offloading device. +! CHECK-NEXT: --offload-host-device Compile for both the offloading host and device (default). +! CHECK-NEXT: --offload-host-only Only compile for the offloading host. +! CHECK-NEXT: -o Write output to +! CHECK-NEXT: -pedantic Warn on language extensions +! CHECK-NEXT: -print-effective-triple Print the effective target triple +! CHECK-NEXT: -print-target-triple Print the normalized target triple +! CHECK-NEXT: -pthread Support POSIX threads in generated code +! CHECK-NEXT: -P Disable linemarker output in -E mode +! CHECK-NEXT: -resource-dir The directory which holds the compiler resource files +! CHECK-NEXT: --rocm-path= ROCm installation path, used for finding and automatically linking required bitcode libraries. +! CHECK-NEXT: -Rpass-analysis= Report transformation analysis from optimization passes whose name matches the given POSIX regular expression +! CHECK-NEXT: -Rpass-missed= Report missed transformations by optimization passes whose name matches the given POSIX regular expression +! CHECK-NEXT: -Rpass= Report transformations performed by optimization passes whose name matches the given POSIX regular expression +! CHECK-NEXT: -R Enable the specified remark +! CHECK-NEXT: -save-temps= Save intermediate compilation results. +! CHECK-NEXT: -save-temps Alias for --save-temps=cwd +! CHECK-NEXT: -std= Language standard to compile for +! CHECK-NEXT: -S Only run preprocess and compilation steps +! CHECK-NEXT: --target= Generate code for the given target +! CHECK-NEXT: -U Undefine macro +! CHECK-NEXT: --version Print version information +! CHECK-NEXT: -v Show commands to run and use verbose output +! CHECK-NEXT: -Wl, Pass the comma separated arguments in to the linker +! CHECK-NEXT: -W Enable the specified warning +! CHECK-NEXT: -Xflang Pass to the flang compiler +! CHECK-NEXT: -x Treat subsequent input files as having type + + +! ERROR-FLANG: error: unknown argument '-help-hidden'; did you mean '--help-hidden'? + +! Frontend driver -help-hidden is not supported +! ERROR-FLANG-FC1: error: unknown argument: '{{.*}}' diff --git a/flang/test/Driver/dynamic-linker.f90 b/flang/test/Driver/dynamic-linker.f90 index 7c3f1b5a53fe..6d5c443ab75c 100644 --- a/flang/test/Driver/dynamic-linker.f90 +++ b/flang/test/Driver/dynamic-linker.f90 @@ -16,7 +16,6 @@ ! GNU-LINKER-OPTIONS-SAME: "-shared" ! GNU-LINKER-OPTIONS-SAME: "-static" ! GNU-LINKER-OPTIONS-SAME: "-rpath" "/path/to/dir" -! GNU-LINKER-OPTIONS-NOT: "-lFortran_main.a" ! RDYNAMIC-LINKER-OPTION: "{{.*}}ld" ! RDYNAMIC-LINKER-OPTION-SAME: "-export-dynamic" @@ -25,4 +24,3 @@ ! MSVC-LINKER-OPTIONS: "{{.*}}link{{(.exe)?}}" ! MSVC-LINKER-OPTIONS-SAME: "-dll" ! MSVC-LINKER-OPTIONS-SAME: "-rpath" "/path/to/dir" -! MSVC-LINKER-OPTIONS-NOT: "/WHOLEARCHIVE:Fortran_main" diff --git a/flang/test/Driver/emit-mlir.f90 b/flang/test/Driver/emit-mlir.f90 index 191ee13396ef..83bb8fc1eddc 100644 --- a/flang/test/Driver/emit-mlir.f90 +++ b/flang/test/Driver/emit-mlir.f90 @@ -19,6 +19,16 @@ ! CHECK-NEXT: %[[VAL_0:.*]] = fir.zero_bits !fir.ref, !fir.ref>>>>> ! CHECK-NEXT: fir.has_value %[[VAL_0]] : !fir.ref, !fir.ref>>>>> ! CHECK-NEXT: } +! CHECK-NEXT: func.func private @_FortranAProgramStart(i32, !llvm.ptr, !llvm.ptr, !llvm.ptr) +! CHECK-NEXT: func.func private @_FortranAProgramEndStatement() +! CHECK-NEXT: func.func @main(%arg0: i32, %arg1: !llvm.ptr, %arg2: !llvm.ptr) -> i32 { +! CHECK-NEXT: %c0_i32 = arith.constant 0 : i32 +! CHECK-NEXT: %0 = fir.address_of(@_QQEnvironmentDefaults) : !fir.ref, !fir.ref>>>>> +! CHECK-NEXT: ir.call @_FortranAProgramStart(%arg0, %arg1, %arg2, %0) {{.*}} : (i32, !llvm.ptr, !llvm.ptr, !fir.ref, !fir.ref>>>>>) +! CHECK-NEXT: fir.call @_QQmain() fastmath : () -> () +! CHECK-NEXT: fir.call @_FortranAProgramEndStatement() {{.*}} : () -> () +! CHECK-NEXT: return %c0_i32 : i32 +! CHECK-NEXT: } ! CHECK-NEXT: } end program diff --git a/flang/test/Driver/linker-flags.f90 b/flang/test/Driver/linker-flags.f90 index 4d3d528b5e99..02e217494f81 100644 --- a/flang/test/Driver/linker-flags.f90 +++ b/flang/test/Driver/linker-flags.f90 @@ -11,7 +11,6 @@ ! RUN: %flang -### --target=x86_64-unknown-dragonfly %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,UNIX,UNIX-F128%f128-lib ! RUN: %flang -### --target=x86_64-unknown-haiku %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,HAIKU,HAIKU-F128%f128-lib ! RUN: %flang -### --target=x86_64-windows-gnu %S/Inputs/hello.f90 2>&1 | FileCheck %s --check-prefixes=CHECK,MINGW,MINGW-F128%f128-lib -! RUN: %flang -### --target=aarch64-unknown-linux-gnu %S/Inputs/hello.f90 -lFortran_main 2>&1 | FileCheck %s --check-prefixes=DEPRECATED ! NOTE: Clang's driver library, clangDriver, usually adds 'oldnames' on Windows, ! but it is not needed when compiling Fortran code and they might bring in @@ -29,7 +28,6 @@ ! executable and may find the GNU linker from MinGW or Cygwin. ! UNIX-LABEL: "{{.*}}ld{{(\.exe)?}}" ! UNIX-SAME: "[[object_file]]" -! UNIX-SAME: "--whole-archive" "-lFortran_main" "--no-whole-archive" ! UNIX-F128NONE-NOT: FortranFloat128Math ! SOLARIS-F128NONE-NOT: FortranFloat128Math ! UNIX-F128LIBQUADMATH-SAME: "-lFortranFloat128Math" "--as-needed" "-lquadmath" "--no-as-needed" @@ -38,7 +36,6 @@ ! DARWIN-LABEL: "{{.*}}ld{{(\.exe)?}}" ! DARWIN-SAME: "[[object_file]]" -! DARWIN-SAME: -lFortran_main ! DARWIN-F128NONE-NOT: FortranFloat128Math ! DARWIN-F128LIBQUADMATH-SAME: "-lFortranFloat128Math" "--as-needed" "-lquadmath" "--no-as-needed" ! DARWIN-SAME: -lFortranRuntime @@ -46,14 +43,12 @@ ! HAIKU-LABEL: "{{.*}}ld{{(\.exe)?}}" ! HAIKU-SAME: "[[object_file]]" -! HAIKU-SAME: "--whole-archive" "-lFortran_main" "--no-whole-archive" ! HAIKU-F128NONE-NOT: FortranFloat128Math ! HAIKU-F128LIBQUADMATH-SAME: "-lFortranFloat128Math" "--as-needed" "-lquadmath" "--no-as-needed" ! HAIKU-SAME: "-lFortranRuntime" "-lFortranDecimal" ! MINGW-LABEL: "{{.*}}ld{{(\.exe)?}}" ! MINGW-SAME: "[[object_file]]" -! MINGW-SAME: -lFortran_main ! MINGW-F128NONE-NOT: FortranFloat128Math ! MINGW-F128LIBQUADMATH-SAME: "-lFortranFloat128Math" "--as-needed" "-lquadmath" "--no-as-needed" ! MINGW-SAME: -lFortranRuntime @@ -66,6 +61,3 @@ ! MSVC-LABEL: link ! MSVC-SAME: /subsystem:console ! MSVC-SAME: "[[object_file]]" - -! Check that we warn when using -lFortran_main -! DEPRECATED: warning: argument '-lFortran_main' is deprecated, see the Flang driver documentation for correct usage [-Wdeprecated] diff --git a/flang/test/Driver/msvc-dependent-lib-flags.f90 b/flang/test/Driver/msvc-dependent-lib-flags.f90 index 6cfc969e92b2..765917f07d8e 100644 --- a/flang/test/Driver/msvc-dependent-lib-flags.f90 +++ b/flang/test/Driver/msvc-dependent-lib-flags.f90 @@ -7,7 +7,6 @@ ! MSVC-SAME: --dependent-lib=clang_rt.builtins.lib ! MSVC-SAME: -D_MT ! MSVC-SAME: --dependent-lib=libcmt -! MSVC-SAME: --dependent-lib=Fortran_main.static.lib ! MSVC-SAME: --dependent-lib=FortranRuntime.static.lib ! MSVC-SAME: --dependent-lib=FortranDecimal.static.lib @@ -16,7 +15,6 @@ ! MSVC-DEBUG-SAME: -D_MT ! MSVC-DEBUG-SAME: -D_DEBUG ! MSVC-DEBUG-SAME: --dependent-lib=libcmtd -! MSVC-DEBUG-SAME: --dependent-lib=Fortran_main.static_dbg.lib ! MSVC-DEBUG-SAME: --dependent-lib=FortranRuntime.static_dbg.lib ! MSVC-DEBUG-SAME: --dependent-lib=FortranDecimal.static_dbg.lib @@ -25,7 +23,6 @@ ! MSVC-DLL-SAME: -D_MT ! MSVC-DLL-SAME: -D_DLL ! MSVC-DLL-SAME: --dependent-lib=msvcrt -! MSVC-DLL-SAME: --dependent-lib=Fortran_main.dynamic.lib ! MSVC-DLL-SAME: --dependent-lib=FortranRuntime.dynamic.lib ! MSVC-DLL-SAME: --dependent-lib=FortranDecimal.dynamic.lib @@ -35,6 +32,5 @@ ! MSVC-DLL-DEBUG-SAME: -D_DEBUG ! MSVC-DLL-DEBUG-SAME: -D_DLL ! MSVC-DLL-DEBUG-SAME: --dependent-lib=msvcrtd -! MSVC-DLL-DEBUG-SAME: --dependent-lib=Fortran_main.dynamic_dbg.lib ! MSVC-DLL-DEBUG-SAME: --dependent-lib=FortranRuntime.dynamic_dbg.lib ! MSVC-DLL-DEBUG-SAME: --dependent-lib=FortranDecimal.dynamic_dbg.lib diff --git a/flang/test/Driver/no-duplicate-main.f90 b/flang/test/Driver/no-duplicate-main.f90 index 88f4430828e0..b0bb6c2a2fef 100644 --- a/flang/test/Driver/no-duplicate-main.f90 +++ b/flang/test/Driver/no-duplicate-main.f90 @@ -4,8 +4,6 @@ ! RUN: %flang -o %t -c %s ! RUN: not %flang -o %t.exe %t %t.c-object 2>&1 -! RUN: %flang -fno-fortran-main -o %t.exe %t %t.c-object 2>&1 - ! TODO: potentially add further checks to ensure that proper ! linker error messages are detected and checked via ! FileCheck. diff --git a/flang/tools/flang-driver/CMakeLists.txt b/flang/tools/flang-driver/CMakeLists.txt index 3ce8b407450d..ce30ecff028d 100644 --- a/flang/tools/flang-driver/CMakeLists.txt +++ b/flang/tools/flang-driver/CMakeLists.txt @@ -21,7 +21,6 @@ add_flang_tool(flang-new # unable to generate executables. FortranRuntime FortranDecimal - Fortran_main ) target_link_libraries(flang-new diff --git a/lld/COFF/MinGW.cpp b/lld/COFF/MinGW.cpp index e46f5277a8c3..29c01da9e28f 100644 --- a/lld/COFF/MinGW.cpp +++ b/lld/COFF/MinGW.cpp @@ -50,7 +50,6 @@ AutoExporter::AutoExporter( "libclang_rt.profile-x86_64", "libc++", "libc++abi", - "libFortran_main", "libFortranRuntime", "libFortranDecimal", "libunwind", -- GitLab From e57b8724140664da408da92d5d50f9a1e0c9828a Mon Sep 17 00:00:00 2001 From: Danial Klimkin Date: Mon, 29 Apr 2024 15:23:29 +0200 Subject: [PATCH 222/301] Avoid unusable variable in ByteCodeExprGen.cpp (#90469) Inline assert to avoid unusable variable warning/error when asserts are disabled. --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 626c30157b22..568a929c6a16 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -2363,8 +2363,7 @@ bool ByteCodeExprGen::VisitCXXUuidofExpr(const CXXUuidofExpr *E) { if (!this->emitGetPtrGlobal(*GlobalIndex, E)) return false; - const Record *R = this->getRecord(E->getType()); - assert(R); + assert(this->getRecord(E->getType())); const APValue &V = E->getGuidDecl()->getAsAPValue(); if (V.getKind() == APValue::None) -- GitLab From caa902613a96f63c3855b3a0bcd82d1b1db49408 Mon Sep 17 00:00:00 2001 From: offsetof <131769984+offsetof@users.noreply.github.com> Date: Mon, 29 Apr 2024 13:23:50 +0000 Subject: [PATCH 223/301] [clang] Allow constexpr cast from `void*` in more cases (#89484) [[expr.const]/5.14](https://eel.is/c++draft/expr.const#5.14) says that constexpr cast from *cv* void\* to `T*` is OK if the pointee type is similar to `T`, but Clang currently only permits the conversion if the types are the same except top-level cv-qualifiers. This patch also allows casting `(void*)nullptr`, implementing the resolution of [CWG2819](https://cplusplus.github.io/CWG/issues/2819). --------- Co-authored-by: Vlad Serebrennikov --- clang/lib/AST/ExprConstant.cpp | 7 +- clang/test/CXX/drs/dr25xx.cpp | 2 +- clang/test/CXX/drs/dr28xx.cpp | 10 ++- clang/test/CXX/expr/expr.const/p5-26.cpp | 7 ++ clang/www/cxx_dr_status.html | 82 ++++++++++++++++-------- clang/www/make_cxx_dr_status | 2 +- 6 files changed, 78 insertions(+), 32 deletions(-) diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index ea3e7304a742..71b5f91b4d25 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -9237,9 +9237,10 @@ bool PointerExprEvaluator::VisitCastExpr(const CastExpr *E) { bool HasValidResult = !Result.InvalidBase && !Result.Designator.Invalid && !Result.IsNullPtr; bool VoidPtrCastMaybeOK = - HasValidResult && - Info.Ctx.hasSameUnqualifiedType(Result.Designator.getType(Info.Ctx), - E->getType()->getPointeeType()); + Result.IsNullPtr || + (HasValidResult && + Info.Ctx.hasSimilarType(Result.Designator.getType(Info.Ctx), + E->getType()->getPointeeType())); // 1. We'll allow it in std::allocator::allocate, and anything which that // calls. // 2. HACK 2022-03-28: Work around an issue with libstdc++'s diff --git a/clang/test/CXX/drs/dr25xx.cpp b/clang/test/CXX/drs/dr25xx.cpp index 481ae09cdb77..8bca58f44944 100644 --- a/clang/test/CXX/drs/dr25xx.cpp +++ b/clang/test/CXX/drs/dr25xx.cpp @@ -130,7 +130,7 @@ struct D3 : B { #endif #if __cplusplus >= 202302L -namespace cwg2561 { // cwg2561: no +namespace cwg2561 { // cwg2561: no tentatively ready 2024-03-18 struct C { constexpr C(auto) { } }; diff --git a/clang/test/CXX/drs/dr28xx.cpp b/clang/test/CXX/drs/dr28xx.cpp index 1967e8b751db..be35d366bdd6 100644 --- a/clang/test/CXX/drs/dr28xx.cpp +++ b/clang/test/CXX/drs/dr28xx.cpp @@ -10,6 +10,14 @@ // expected-no-diagnostics #endif +namespace cwg2819 { // cwg2819: 19 tentatively ready 2023-12-01 +#if __cpp_constexpr >= 202306L + constexpr void* p = nullptr; + constexpr int* q = static_cast(p); + static_assert(q == nullptr); +#endif +} + namespace cwg2847 { // cwg2847: 19 review 2024-03-01 #if __cplusplus >= 202002L @@ -59,7 +67,7 @@ void B::g() requires true; } // namespace cwg2847 -namespace cwg2858 { // cwg2858: 19 +namespace cwg2858 { // cwg2858: 19 tentatively ready 2024-04-05 #if __cplusplus > 202302L diff --git a/clang/test/CXX/expr/expr.const/p5-26.cpp b/clang/test/CXX/expr/expr.const/p5-26.cpp index 3624b1e5a3e3..7513b11c09aa 100644 --- a/clang/test/CXX/expr/expr.const/p5-26.cpp +++ b/clang/test/CXX/expr/expr.const/p5-26.cpp @@ -37,3 +37,10 @@ void err() { // cxx23-note {{cast from 'void *' is not allowed in a constant expression in C++ standards before C++2c}} \ // cxx26-note {{cast from 'void *' is not allowed in a constant expression because the pointed object type 'T' is not similar to the target type 'S'}} } + +int* p; +constexpr int** pp = &p; +constexpr void* vp = pp; +constexpr auto cvp = static_cast(vp); +// cxx23-error@-1 {{constant expression}} +// cxx23-note@-2 {{cast from 'void *' is not allowed in a constant expression}} diff --git a/clang/www/cxx_dr_status.html b/clang/www/cxx_dr_status.html index 19d29cb55d6e..875521bd505d 100755 --- a/clang/www/cxx_dr_status.html +++ b/clang/www/cxx_dr_status.html @@ -1433,11 +1433,11 @@ accessible? Is indirection through a null pointer undefined behavior? Unknown - + 233 tentatively ready References vs pointers in UDC overload resolution - Unknown + Not resolved 234 @@ -15170,11 +15170,11 @@ and POD class Parameter type determination in a requirement-parameter-list Unknown - + 2561 tentatively ready Conversion to function pointer for lambda with explicit object parameter - No + Not Resolved* 2562 @@ -15332,11 +15332,11 @@ and POD class Visible side effects and initial value of an object Not resolved - + 2588 tentatively ready friend declarations and module linkage - Unknown + Not resolved 2589 @@ -16172,11 +16172,11 @@ and POD class Importing header units synthesized from source files Not resolved - + 2728 tentatively ready Evaluation of conversions in a delete-expression - Unknown + Not resolved 2729 @@ -16713,17 +16713,17 @@ objects sizeof(abstract class) is underspecified Not resolved - + 2818 tentatively ready Use of predefined reserved identifiers - Unknown + Not resolved - + 2819 tentatively ready Cast from null pointer value in a constant expression - Unknown + Not Resolved* 2820 @@ -16953,17 +16953,17 @@ objects Argument-dependent lookup with incomplete class types Unknown - + 2858 tentatively ready Declarative nested-name-specifiers and pack-index-specifiers - Clang 19 + Not Resolved* - + 2859 tentatively ready Value-initialization with multiple default constructors - Unknown + Not resolved 2860 @@ -16971,29 +16971,29 @@ objects Remove and fix the term "vacuous initialization" Unknown - + 2861 tentatively ready dynamic_cast on bad pointer value - Unknown + Not resolved - + 2862 tentatively ready Unclear boundaries of template declarations - Unknown + Not resolved - + 2863 tentatively ready Unclear synchronization requirements for object lifetime rules - Unknown + Not resolved - + 2864 tentatively ready Narrowing floating-point conversions - Unknown + Not resolved 2865 @@ -17031,11 +17031,11 @@ objects Combining absent encoding-prefixes Not resolved - + 2871 tentatively ready User-declared constructor templates inhibiting default constructors - Unknown + Not resolved 2872 @@ -17096,6 +17096,36 @@ objects open Type restrictions for the explicit object parameter of a lambda Not resolved + + + 2882 + open + Unclear treatment of conversion to void + Not resolved + + + 2883 + open + Definition of "odr-usable" ignores lambda scopes + Not resolved + + + 2884 + open + Qualified declarations of partial specializations + Not resolved + + + 2885 + open + Non-eligible trivial default constructors + Not resolved + + + 2886 + open + Temporaries and trivial potentially-throwing special member functions + Not resolved diff --git a/clang/www/make_cxx_dr_status b/clang/www/make_cxx_dr_status index 57f1dc86fd12..47c8b3bae4a1 100755 --- a/clang/www/make_cxx_dr_status +++ b/clang/www/make_cxx_dr_status @@ -236,7 +236,7 @@ for dr in drs: avail = 'Extension' avail_style = '' - elif dr.status in ('open', 'drafting', 'review'): + elif dr.status in ('open', 'drafting', 'review', 'tentatively ready'): row_style = ' class="open"' try: avail, avail_style, unresolved_status = availability(dr.issue) -- GitLab From 5f9ae61dee0f6432c1dcc16b4412bb99803fa7d5 Mon Sep 17 00:00:00 2001 From: Jannik Silvanus <37809848+jasilvanus@users.noreply.github.com> Date: Mon, 29 Apr 2024 15:37:42 +0200 Subject: [PATCH 224/301] [Support][YamlTraits] Add quoting for keys in textual YAML representation (#88763) The support library contains helpers to parse and emit YAML documents. In the textual YAML representation, some strings need to be quoted, e.g. when containing unprintable characters. We already have such quoting implemented for YAML values. This patch applies the same quoting to YAML *keys*. One affected case is output of control registers in AMDGPU Msgpack metadata, which are printed in a format like this: ``` 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 42 ``` With this patch, the key is quoted: ``` '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 42 ``` Most test changes come from this pattern. --- llvm/include/llvm/Support/YAMLTraits.h | 21 +++-- llvm/lib/Support/YAMLTraits.cpp | 80 +++++++++--------- llvm/test/CodeGen/AMDGPU/amdpal-callable.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdpal-cs.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdpal-es.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-gs.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-hs.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-ls.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll | 2 +- .../CodeGen/AMDGPU/amdpal-msgpack-default.ll | 44 +++++----- .../CodeGen/AMDGPU/amdpal-msgpack-denormal.ll | 44 +++++----- .../AMDGPU/amdpal-msgpack-dx10-clamp.ll | 44 +++++----- llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll | 2 +- .../CodeGen/AMDGPU/amdpal-msgpack-ieee.ll | 58 ++++++------- llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll | 8 +- .../CodeGen/AMDGPU/amdpal-msgpack-psenable.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll | 2 +- llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll | 8 +- .../CodeGen/AMDGPU/amdpal-usersgpr-init.ll | 4 +- llvm/test/CodeGen/AMDGPU/amdpal-vs.ll | 2 +- llvm/test/CodeGen/AMDGPU/extra-lds-size.ll | 4 +- llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll | 12 +-- .../test/CodeGen/AMDGPU/wave_dispatch_regs.ll | 8 +- llvm/test/MC/AMDGPU/pal-msgpack.s | 16 ++-- llvm/unittests/Support/YAMLIOTest.cpp | 81 +++++++++++++++++++ 28 files changed, 281 insertions(+), 185 deletions(-) diff --git a/llvm/include/llvm/Support/YAMLTraits.h b/llvm/include/llvm/Support/YAMLTraits.h index 3b1f4bad57fc..33aeb039320d 100644 --- a/llvm/include/llvm/Support/YAMLTraits.h +++ b/llvm/include/llvm/Support/YAMLTraits.h @@ -671,7 +671,11 @@ inline bool isBool(StringRef S) { // (except for TAB #x9, LF #xA, and CR #xD which are allowed), DEL #x7F, the C1 // control block #x80-#x9F (except for NEL #x85 which is allowed), the surrogate // block #xD800-#xDFFF, #xFFFE, and #xFFFF. -inline QuotingType needsQuotes(StringRef S) { +// +// Some strings are valid YAML values even unquoted, but without quotes are +// interpreted as non-string type, for instance null, boolean or numeric values. +// If ForcePreserveAsString is set, such strings are quoted. +inline QuotingType needsQuotes(StringRef S, bool ForcePreserveAsString = true) { if (S.empty()) return QuotingType::Single; @@ -679,12 +683,14 @@ inline QuotingType needsQuotes(StringRef S) { if (isSpace(static_cast(S.front())) || isSpace(static_cast(S.back()))) MaxQuotingNeeded = QuotingType::Single; - if (isNull(S)) - MaxQuotingNeeded = QuotingType::Single; - if (isBool(S)) - MaxQuotingNeeded = QuotingType::Single; - if (isNumeric(S)) - MaxQuotingNeeded = QuotingType::Single; + if (ForcePreserveAsString) { + if (isNull(S)) + MaxQuotingNeeded = QuotingType::Single; + if (isBool(S)) + MaxQuotingNeeded = QuotingType::Single; + if (isNumeric(S)) + MaxQuotingNeeded = QuotingType::Single; + } // 7.3.3 Plain Style // Plain scalars must not begin with most indicators, as this would cause @@ -1636,6 +1642,7 @@ public: private: void output(StringRef s); + void output(StringRef, QuotingType); void outputUpToEndOfLine(StringRef s); void newLineCheck(bool EmptySequence = false); void outputNewLine(); diff --git a/llvm/lib/Support/YAMLTraits.cpp b/llvm/lib/Support/YAMLTraits.cpp index 4aaf59be2ce5..7bb60894b335 100644 --- a/llvm/lib/Support/YAMLTraits.cpp +++ b/llvm/lib/Support/YAMLTraits.cpp @@ -718,40 +718,8 @@ void Output::scalarString(StringRef &S, QuotingType MustQuote) { outputUpToEndOfLine("''"); return; } - if (MustQuote == QuotingType::None) { - // Only quote if we must. - outputUpToEndOfLine(S); - return; - } - - const char *const Quote = MustQuote == QuotingType::Single ? "'" : "\""; - output(Quote); // Starting quote. - - // When using double-quoted strings (and only in that case), non-printable characters may be - // present, and will be escaped using a variety of unicode-scalar and special short-form - // escapes. This is handled in yaml::escape. - if (MustQuote == QuotingType::Double) { - output(yaml::escape(S, /* EscapePrintable= */ false)); - outputUpToEndOfLine(Quote); - return; - } - - unsigned i = 0; - unsigned j = 0; - unsigned End = S.size(); - const char *Base = S.data(); - - // When using single-quoted strings, any single quote ' must be doubled to be escaped. - while (j < End) { - if (S[j] == '\'') { // Escape quotes. - output(StringRef(&Base[i], j - i)); // "flush". - output(StringLiteral("''")); // Print it as '' - i = j + 1; - } - ++j; - } - output(StringRef(&Base[i], j - i)); - outputUpToEndOfLine(Quote); // Ending quote. + output(S, MustQuote); + outputUpToEndOfLine(""); } void Output::blockScalarString(StringRef &S) { @@ -801,6 +769,46 @@ void Output::output(StringRef s) { Out << s; } +void Output::output(StringRef S, QuotingType MustQuote) { + if (MustQuote == QuotingType::None) { + // Only quote if we must. + output(S); + return; + } + + StringLiteral Quote = MustQuote == QuotingType::Single ? StringLiteral("'") + : StringLiteral("\""); + output(Quote); // Starting quote. + + // When using double-quoted strings (and only in that case), non-printable + // characters may be present, and will be escaped using a variety of + // unicode-scalar and special short-form escapes. This is handled in + // yaml::escape. + if (MustQuote == QuotingType::Double) { + output(yaml::escape(S, /* EscapePrintable= */ false)); + output(Quote); + return; + } + + unsigned i = 0; + unsigned j = 0; + unsigned End = S.size(); + const char *Base = S.data(); + + // When using single-quoted strings, any single quote ' must be doubled to be + // escaped. + while (j < End) { + if (S[j] == '\'') { // Escape quotes. + output(StringRef(&Base[i], j - i)); // "flush". + output(StringLiteral("''")); // Print it as '' + i = j + 1; + } + ++j; + } + output(StringRef(&Base[i], j - i)); + output(Quote); // Ending quote. +} + void Output::outputUpToEndOfLine(StringRef s) { output(s); if (StateStack.empty() || (!inFlowSeqAnyElement(StateStack.back()) && @@ -853,7 +861,7 @@ void Output::newLineCheck(bool EmptySequence) { } void Output::paddedKey(StringRef key) { - output(key); + output(key, needsQuotes(key, false)); output(":"); const char *spaces = " "; if (key.size() < strlen(spaces)) @@ -872,7 +880,7 @@ void Output::flowKey(StringRef Key) { Column = ColumnAtMapFlowStart; output(" "); } - output(Key); + output(Key, needsQuotes(Key, false)); output(": "); } diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll index b7b2cb22c1b6..9d4f9434aa31 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-callable.ll @@ -142,8 +142,8 @@ attributes #0 = { nounwind } ; GCN: amdpal.pipelines: ; GCN-NEXT: - .registers: -; GCN-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf01ca{{$}} -; GCN-NEXT: 0x2e13 (COMPUTE_PGM_RSRC2): 0x8001{{$}} +; GCN-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xaf01ca{{$}} +; GCN-NEXT: '0x2e13 (COMPUTE_PGM_RSRC2)': 0x8001{{$}} ; GCN-NEXT: .shader_functions: ; GCN-NEXT: dynamic_stack: ; GCN-NEXT: .backend_stack_size: 0x10{{$}} diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll index 98aa04f6d26e..a3fd2a942bc2 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-cs.ll @@ -11,8 +11,8 @@ ; GCN-NEXT: .entry_point: cs_amdpal ; GCN-NEXT: .scratch_memory_size: 0 ; GCN: .registers: -; GCN-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): -; GCN-NEXT: 0x2e13 (COMPUTE_PGM_RSRC2): +; GCN-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': +; GCN-NEXT: '0x2e13 (COMPUTE_PGM_RSRC2)': ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata define amdgpu_cs half @cs_amdpal(half %arg0) { diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-es.ll b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll index 012b2061756b..679e0858819e 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-es.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-es.ll @@ -10,7 +10,7 @@ ; GCN-NEXT: .entry_point: es_amdpal ; GCN-NEXT: .scratch_memory_size: 0 ; GCN: .registers: -; GCN-NEXT: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0 +; GCN-NEXT: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0 ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata define amdgpu_es half @es_amdpal(half %arg0) { diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll index e2f67398d18a..75f7a1dc266d 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-gs.ll @@ -11,7 +11,7 @@ ; GCN-NEXT: .entry_point: gs_amdpal ; GCN-NEXT: .scratch_memory_size: 0 ; GCN: .registers: -; GCN-NEXT: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0 +; GCN-NEXT: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0 ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata define amdgpu_gs half @gs_amdpal(half %arg0) { diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll index 9ad47c1d604f..c61578a967b6 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-hs.ll @@ -11,7 +11,7 @@ ; GCN-NEXT: .entry_point: hs_amdpal ; GCN-NEXT: .scratch_memory_size: 0 ; GCN: .registers: -; GCN-NEXT: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0 +; GCN-NEXT: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0 ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata define amdgpu_hs half @hs_amdpal(half %arg0) { diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll index 8ee6f7283ce7..8162c824dc2c 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-ls.ll @@ -10,7 +10,7 @@ ; GCN-NEXT: .entry_point: ls_amdpal ; GCN-NEXT: .scratch_memory_size: 0 ; GCN: .registers: -; GCN-NEXT: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0 +; GCN-NEXT: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0 ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata define amdgpu_ls half @ls_amdpal(half %arg0) { diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll index 0d0c70c38ace..5e21ba494df1 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-cs.ll @@ -5,7 +5,7 @@ ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata ; GCN-LABEL: {{^}}cs_amdpal: ; GCN: .amdgpu_pal_metadata -; GCN: 0x2e12 (COMPUTE_PGM_RSRC1) +; GCN: '0x2e12 (COMPUTE_PGM_RSRC1)' define amdgpu_cs half @cs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll index b82e3ebdde4b..dc9a33ac0141 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-default.ll @@ -3,45 +3,45 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata -; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000{{$}} -; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f02c0{{$}} -; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2f0000{{$}} +; SI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x2f0000{{$}} +; VI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x2f02c0{{$}} +; GFX9-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x2f0000{{$}} define amdgpu_cs half @cs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata -; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f0000{{$}} -; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f02c0{{$}} -; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2f0000{{$}} +; SI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0x2f0000{{$}} +; VI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0x2f02c0{{$}} +; GFX9-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0x2f0000{{$}} define amdgpu_es half @es_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata -; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f0000{{$}} -; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f02c0{{$}} -; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2f0000{{$}} +; SI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0x2f0000{{$}} +; VI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0x2f02c0{{$}} +; GFX9-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0x2f0000{{$}} define amdgpu_gs half @gs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata -; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f0000{{$}} -; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f02c0{{$}} -; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2f0000{{$}} +; SI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0x2f0000{{$}} +; VI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0x2f02c0{{$}} +; GFX9-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0x2f0000{{$}} define amdgpu_hs half @hs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata -; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f0000{{$}} -; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f02c0{{$}} -; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2f0000{{$}} +; SI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0x2f0000{{$}} +; VI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0x2f02c0{{$}} +; GFX9-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0x2f0000{{$}} define amdgpu_ls half @ls_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add @@ -49,18 +49,18 @@ define amdgpu_ls half @ls_amdpal(half %arg0) { ; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata ; below. -; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f0000{{$}} -; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f02c0{{$}} -; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2f0000{{$}} +; SI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0x2f0000{{$}} +; VI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0x2f02c0{{$}} +; GFX9-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0x2f0000{{$}} define amdgpu_ps half @ps_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata -; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f0000{{$}} -; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f02c0{{$}} -; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2f0000{{$}} +; SI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0x2f0000{{$}} +; VI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0x2f02c0{{$}} +; GFX9-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0x2f0000{{$}} define amdgpu_vs half @vs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add @@ -75,7 +75,7 @@ define amdgpu_vs half @vs_amdpal(half %arg0) { ; - 0x123456789abcdef0 ; - 0xfedcba9876543210 ; .registers: -; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42000000 ; ... ; .end_amdgpu_pal_metadata diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll index b86b42868005..ffce3ed08509 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-denormal.ll @@ -3,45 +3,45 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata -; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000{{$}} -; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c02c0{{$}} -; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x2c0000{{$}} +; SI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x2c0000{{$}} +; VI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x2c02c0{{$}} +; GFX9-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x2c0000{{$}} define amdgpu_cs half @cs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata -; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0000{{$}} -; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c02c0{{$}} -; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0x2c0000{{$}} +; SI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0x2c0000{{$}} +; VI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0x2c02c0{{$}} +; GFX9-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0x2c0000{{$}} define amdgpu_es half @es_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata -; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0000{{$}} -; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c02c0{{$}} -; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0x2c0000{{$}} +; SI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0x2c0000{{$}} +; VI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0x2c02c0{{$}} +; GFX9-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0x2c0000{{$}} define amdgpu_gs half @gs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata -; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0000{{$}} -; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c02c0{{$}} -; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x2c0000{{$}} +; SI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0x2c0000{{$}} +; VI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0x2c02c0{{$}} +; GFX9-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0x2c0000{{$}} define amdgpu_hs half @hs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata -; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0000{{$}} -; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c02c0{{$}} -; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0x2c0000{{$}} +; SI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0x2c0000{{$}} +; VI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0x2c02c0{{$}} +; GFX9-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0x2c0000{{$}} define amdgpu_ls half @ls_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -49,18 +49,18 @@ define amdgpu_ls half @ls_amdpal(half %arg0) #0 { ; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata ; below. -; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0000{{$}} -; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c02c0{{$}} -; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x2c0000{{$}} +; SI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0x2c0000{{$}} +; VI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0x2c02c0{{$}} +; GFX9-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0x2c0000{{$}} define amdgpu_ps half @ps_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata -; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0000{{$}} -; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c02c0{{$}} -; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x2c0000{{$}} +; SI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0x2c0000{{$}} +; VI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0x2c02c0{{$}} +; GFX9-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0x2c0000{{$}} define amdgpu_vs half @vs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -77,7 +77,7 @@ attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" } ; - 0x123456789abcdef0 ; - 0xfedcba9876543210 ; .registers: -; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42000000 ; ... ; .end_amdgpu_pal_metadata diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll index b1db7aafacab..3ea3064fa743 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-dx10-clamp.ll @@ -3,45 +3,45 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX9 -enable-var-scope %s ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata -; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000{{$}} -; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf02c0{{$}} -; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xf0000{{$}} +; SI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xf0000{{$}} +; VI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xf02c0{{$}} +; GFX9-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xf0000{{$}} define amdgpu_cs half @cs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata -; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000{{$}} -; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf02c0{{$}} -; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000{{$}} +; SI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0xf0000{{$}} +; VI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0xf02c0{{$}} +; GFX9-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0xf0000{{$}} define amdgpu_es half @es_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata -; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf0000{{$}} -; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf02c0{{$}} -; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xf0000{{$}} +; SI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0xf0000{{$}} +; VI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0xf02c0{{$}} +; GFX9-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0xf0000{{$}} define amdgpu_gs half @gs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata -; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf0000{{$}} -; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf02c0{{$}} -; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xf0000{{$}} +; SI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0xf0000{{$}} +; VI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0xf02c0{{$}} +; GFX9-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0xf0000{{$}} define amdgpu_hs half @hs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata -; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000{{$}} -; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf02c0{{$}} -; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000{{$}} +; SI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0xf0000{{$}} +; VI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0xf02c0{{$}} +; GFX9-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0xf0000{{$}} define amdgpu_ls half @ls_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -49,18 +49,18 @@ define amdgpu_ls half @ls_amdpal(half %arg0) #0 { ; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata ; below. -; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf0000{{$}} -; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf02c0{{$}} -; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xf0000{{$}} +; SI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0xf0000{{$}} +; VI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0xf02c0{{$}} +; GFX9-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0xf0000{{$}} define amdgpu_ps half @ps_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata -; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf0000{{$}} -; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf02c0{{$}} -; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xf0000{{$}} +; SI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0xf0000{{$}} +; VI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0xf02c0{{$}} +; GFX9-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0xf0000{{$}} define amdgpu_vs half @vs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -77,7 +77,7 @@ attributes #0 = { "amdgpu-dx10-clamp"="false" } ; - 0x123456789abcdef0 ; - 0xfedcba9876543210 ; .registers: -; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42000000 ; ... ; .end_amdgpu_pal_metadata diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll index f97117f3d909..bcc8da6e1bf4 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-es.ll @@ -4,7 +4,7 @@ ; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata ; GCN-LABEL: {{^}}es_amdpal: ; GCN: .amdgpu_pal_metadata -; GCN: 0x2cca (SPI_SHADER_PGM_RSRC1_ES) +; GCN: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)' define amdgpu_es half @es_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll index a32d10390b98..ef4c9cbd5006 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-gs.ll @@ -5,7 +5,7 @@ ; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata ; GCN-LABEL: {{^}}gs_amdpal: ; GCN: .amdgpu_pal_metadata -; GCN: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) +; GCN: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)' define amdgpu_gs half @gs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll index be08c93cdb31..eb814c11bceb 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-hs.ll @@ -5,7 +5,7 @@ ; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata ; GCN-LABEL: {{^}}hs_amdpal: ; GCN: .amdgpu_pal_metadata -; GCN: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) +; GCN: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)' define amdgpu_hs half @hs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll index 95d533544c30..d4826a22db79 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ieee.ll @@ -4,50 +4,50 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1200 -verify-machineinstrs < %s | FileCheck -check-prefix=GFX12 -enable-var-scope %s ; amdpal compute shader: check for 0x2e12 (COMPUTE_PGM_RSRC1) in pal metadata -; SI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}} -; VI-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf02c0{{$}} -; GFX9-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0xaf0000{{$}} -; GFX12-DAG: 0x2e12 (COMPUTE_PGM_RSRC1): 0x600f0000{{$}} +; SI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xaf0000{{$}} +; VI-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xaf02c0{{$}} +; GFX9-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0xaf0000{{$}} +; GFX12-DAG: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x600f0000{{$}} define amdgpu_cs half @cs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal evaluation shader: check for 0x2cca (SPI_SHADER_PGM_RSRC1_ES) in pal metadata -; SI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000{{$}} -; VI-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf02c0{{$}} -; GFX9-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xaf0000{{$}} -; GFX12-DAG: 0x2cca (SPI_SHADER_PGM_RSRC1_ES): 0xf0000{{$}} +; SI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0xaf0000{{$}} +; VI-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0xaf02c0{{$}} +; GFX9-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0xaf0000{{$}} +; GFX12-DAG: '0x2cca (SPI_SHADER_PGM_RSRC1_ES)': 0xf0000{{$}} define amdgpu_es half @es_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal geometry shader: check for 0x2c8a (SPI_SHADER_PGM_RSRC1_GS) in pal metadata -; SI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000{{$}} -; VI-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf02c0{{$}} -; GFX9-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xaf0000{{$}} -; GFX12-DAG: 0x2c8a (SPI_SHADER_PGM_RSRC1_GS): 0xa0f0000{{$}} +; SI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0xaf0000{{$}} +; VI-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0xaf02c0{{$}} +; GFX9-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0xaf0000{{$}} +; GFX12-DAG: '0x2c8a (SPI_SHADER_PGM_RSRC1_GS)': 0xa0f0000{{$}} define amdgpu_gs half @gs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal hull shader: check for 0x2d0a (SPI_SHADER_PGM_RSRC1_HS) in pal metadata -; SI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000{{$}} -; VI-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf02c0{{$}} -; GFX9-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0xaf0000{{$}} -; GFX12-DAG: 0x2d0a (SPI_SHADER_PGM_RSRC1_HS): 0x50f0000{{$}} +; SI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0xaf0000{{$}} +; VI-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0xaf02c0{{$}} +; GFX9-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0xaf0000{{$}} +; GFX12-DAG: '0x2d0a (SPI_SHADER_PGM_RSRC1_HS)': 0x50f0000{{$}} define amdgpu_hs half @hs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata -; SI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000{{$}} -; VI-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf02c0{{$}} -; GFX9-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xaf0000{{$}} -; GFX12-DAG: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS): 0xf0000{{$}} +; SI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0xaf0000{{$}} +; VI-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0xaf02c0{{$}} +; GFX9-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0xaf0000{{$}} +; GFX12-DAG: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)': 0xf0000{{$}} define amdgpu_ls half @ls_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -55,20 +55,20 @@ define amdgpu_ls half @ls_amdpal(half %arg0) #0 { ; amdpal pixel shader: check for 0x2c0a (SPI_SHADER_PGM_RSRC1_PS) in pal metadata ; below. -; SI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000{{$}} -; VI-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf02c0{{$}} -; GFX9-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0xaf0000{{$}} -; GFX12-DAG: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0x20f0000{{$}} +; SI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0xaf0000{{$}} +; VI-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0xaf02c0{{$}} +; GFX9-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0xaf0000{{$}} +; GFX12-DAG: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0x20f0000{{$}} define amdgpu_ps half @ps_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add } ; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata -; SI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000{{$}} -; VI-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf02c0{{$}} -; GFX9-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0xaf0000{{$}} -; GFX12-DAG: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0x80f0000{{$}} +; SI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0xaf0000{{$}} +; VI-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0xaf02c0{{$}} +; GFX9-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0xaf0000{{$}} +; GFX12-DAG: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0x80f0000{{$}} define amdgpu_vs half @vs_amdpal(half %arg0) #0 { %add = fadd half %arg0, 1.0 ret half %add @@ -85,7 +85,7 @@ attributes #0 = { "amdgpu-ieee"="true" } ; - 0x123456789abcdef0 ; - 0xfedcba9876543210 ; .registers: -; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42000000 ; ... ; .end_amdgpu_pal_metadata diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll index 46097fa20608..0d81e70b2e4f 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ls.ll @@ -4,7 +4,7 @@ ; amdpal load shader: check for 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) in pal metadata ; GCN-LABEL: {{^}}ls_amdpal: ; GCN: .amdgpu_pal_metadata -; GCN: 0x2d4a (SPI_SHADER_PGM_RSRC1_LS) +; GCN: '0x2d4a (SPI_SHADER_PGM_RSRC1_LS)' define amdgpu_ls half @ls_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll index 9169c651f129..d31732f995b1 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-ps.ll @@ -12,8 +12,8 @@ ; GCN-NEXT: - 0x123456789abcdef0 ; GCN-NEXT: - 0xfedcba9876543210 ; GCN: .registers: -; GCN: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): -; GCN: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42 +; GCN: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': +; GCN: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42 define amdgpu_ps half @ps_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add @@ -23,12 +23,12 @@ define amdgpu_ps half @ps_amdpal(half %arg0) { ; ; .amdgpu_pal_metadata ; --- -; amdpal.pipelines: +; amdpal.pipelines: ; - .internal_pipeline_hash: ; - 0x123456789abcdef0 ; - 0xfedcba9876543210 ; .registers: -; 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 +; '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42000000 ; ... ; .end_amdgpu_pal_metadata diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll index d6322e2b4d3e..15b1a652077e 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-psenable.ll @@ -7,8 +7,8 @@ ; the workaround that ensures that an interpolation mode is also set in PSEnable. ; GCN-LABEL: {{^}}amdpal_psenable: ; GCN: .amdgpu_pal_metadata -; GCN: 0xa1b3 (SPI_PS_INPUT_ENA): 0x2 -; GCN: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x2 +; GCN: '0xa1b3 (SPI_PS_INPUT_ENA)': 0x2 +; GCN: '0xa1b4 (SPI_PS_INPUT_ADDR)': 0x2 define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 { %inst23 = extractelement <2 x float> %pos, i32 0 %inst24 = extractelement <2 x float> %pos, i32 1 diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll index 7c47129c28ce..42de6007f7e2 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-msgpack-vs.ll @@ -5,7 +5,7 @@ ; amdpal vertex shader: check for 45352 (SPI_SHADER_PGM_RSRC1_VS) in pal metadata ; GCN-LABEL: {{^}}vs_amdpal: ; GCN: .amdgpu_pal_metadata -; GCN: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS) +; GCN: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)' define amdgpu_vs half @vs_amdpal(half %arg0) { %add = fadd half %arg0, 1.0 ret half %add diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll b/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll index 13d2050c491f..ace21207a7eb 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-psenable.ll @@ -14,10 +14,10 @@ ; GCN-NEXT: .entry_point: amdpal_psenable ; GCN-NEXT: .scratch_memory_size: 0 ; GCN: .registers: -; GCN-NEXT: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): -; GCN-NEXT: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): -; GCN-NEXT: 0xa1b3 (SPI_PS_INPUT_ENA): 0x2 -; GCN-NEXT: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x2 +; GCN-NEXT: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': +; GCN-NEXT: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': +; GCN-NEXT: '0xa1b3 (SPI_PS_INPUT_ENA)': 0x2 +; GCN-NEXT: '0xa1b4 (SPI_PS_INPUT_ADDR)': 0x2 ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata define amdgpu_ps void @amdpal_psenable(i32 inreg, i32 inreg, i32 inreg, i32 inreg %m0, <2 x float> %pos) #6 { diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll b/llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll index 52a9d57244c2..086a126b1ddc 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-usersgpr-init.ll @@ -1,7 +1,7 @@ ; RUN: llc -mtriple=amdgcn--amdpal -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefix=GCN -enable-var-scope %s ; We want to make sure that RSRC2 is left untouched -; GCN: 0x2e13 (COMPUTE_PGM_RSRC2): 0x78a +; GCN: '0x2e13 (COMPUTE_PGM_RSRC2)': 0x78a define amdgpu_cs half @cs_amdpal(half %arg0, half inreg %arg1) { %add = fadd half %arg0, 1.0 ret half %add @@ -9,4 +9,4 @@ define amdgpu_cs half @cs_amdpal(half %arg0, half inreg %arg1) { !amdgpu.pal.metadata.msgpack = !{!0} -!0 = !{!"\82\B0amdpal.pipelines\91\89\A4.api\A6Vulkan\B0.hardware_stages\81\A3.cs\83\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\AF.wavefront_size@\B7.internal_pipeline_hash\92\CF\E83\B3\C2\D1)\7FG\CF[\8A\DF\EE[\7FD,\AA.registers\8A\CD.\07\01\CD.\08\01\CD.\09\01\CD.\12\CE@,\00\00\CD.\13\CD\07\8A\CD.(\00\CD.*\CE\16\0B\22Y\CD.@\CE\10\00\00\00\CD.B\CE\10\00\00\06\CD.D\00\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\CF\D3s\A6\8D\C5x\84\D4\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CE\FF\FF\FF\FF\A5.type\A2Cs\B0.user_data_limit\01\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\E5\A0\EB\F9}\C6\C1\13\CF\1A_\E7\F7\F2.mR\AD.llpc_version\A454.5\AEamdpal.version\92\02\03"} \ No newline at end of file +!0 = !{!"\82\B0amdpal.pipelines\91\89\A4.api\A6Vulkan\B0.hardware_stages\81\A3.cs\83\AB.sgpr_limith\AB.vgpr_limit\CD\01\00\AF.wavefront_size@\B7.internal_pipeline_hash\92\CF\E83\B3\C2\D1)\7FG\CF[\8A\DF\EE[\7FD,\AA.registers\8A\CD.\07\01\CD.\08\01\CD.\09\01\CD.\12\CE@,\00\00\CD.\13\CD\07\8A\CD.(\00\CD.*\CE\16\0B\22Y\CD.@\CE\10\00\00\00\CD.B\CE\10\00\00\06\CD.D\00\A8.shaders\81\A8.compute\82\B0.api_shader_hash\92\CF\D3s\A6\8D\C5x\84\D4\00\B1.hardware_mapping\91\A3.cs\B0.spill_threshold\CE\FF\FF\FF\FF\A5.type\A2Cs\B0.user_data_limit\01\AF.xgl_cache_info\82\B3.128_bit_cache_hash\92\CF\E5\A0\EB\F9}\C6\C1\13\CF\1A_\E7\F7\F2.mR\AD.llpc_version\A454.5\AEamdpal.version\92\02\03"} diff --git a/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll index ec8f698d69c2..c300ba187740 100644 --- a/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll +++ b/llvm/test/CodeGen/AMDGPU/amdpal-vs.ll @@ -11,7 +11,7 @@ ; GCN-NEXT: .entry_point: vs_amdpal ; GCN-NEXT: .scratch_memory_size: 0 ; GCN: .registers: -; GCN-NEXT: 0x2c4a (SPI_SHADER_PGM_RSRC1_VS): 0 +; GCN-NEXT: '0x2c4a (SPI_SHADER_PGM_RSRC1_VS)': 0 ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata define amdgpu_vs half @vs_amdpal(half %arg0) { diff --git a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll index e376c3df1ac9..96ec90b1f4d0 100644 --- a/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll +++ b/llvm/test/CodeGen/AMDGPU/extra-lds-size.ll @@ -5,12 +5,12 @@ ; Check EXTRA_LDS_SIZE in SPI_SHADER_PGM_RSRC2_PS. -; GFX10-PAL: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x800 +; GFX10-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x800 ; GFX10-MESA: .long 45100 ; GFX10-MESA-NEXT: .long 2048 -; GFX11-PAL: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x400 +; GFX11-PAL: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x400 ; GFX11-MESA: .long 45100 ; GFX11-MESA-NEXT: .long 1024 diff --git a/llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll b/llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll index 6d043e2b6b0a..591deda611b2 100644 --- a/llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll +++ b/llvm/test/CodeGen/AMDGPU/pal-userdata-regs.ll @@ -4,12 +4,12 @@ ; full tessellation-and-geometry pipeline, compiled on gfx8 so it uses all six ; hardware shader types. -; CHECK-DAG: 0x2c0c (SPI_SHADER_USER_DATA_PS_0): 0x10000000 -; CHECK-DAG: 0x2c4c (SPI_SHADER_USER_DATA_VS_0): 0x10000000 -; CHECK-DAG: 0x2c8c (SPI_SHADER_USER_DATA_GS_0): 0x10000000 -; CHECK-DAG: 0x2ccc (SPI_SHADER_USER_DATA_ES_0): 0x10000000 -; CHECK-DAG: 0x2d0c (SPI_SHADER_USER_DATA_HS_0): 0x10000000 -; CHECK-DAG: 0x2d4c (SPI_SHADER_USER_DATA_LS_0): 0x10000000 +; CHECK-DAG: '0x2c0c (SPI_SHADER_USER_DATA_PS_0)': 0x10000000 +; CHECK-DAG: '0x2c4c (SPI_SHADER_USER_DATA_VS_0)': 0x10000000 +; CHECK-DAG: '0x2c8c (SPI_SHADER_USER_DATA_GS_0)': 0x10000000 +; CHECK-DAG: '0x2ccc (SPI_SHADER_USER_DATA_ES_0)': 0x10000000 +; CHECK-DAG: '0x2d0c (SPI_SHADER_USER_DATA_HS_0)': 0x10000000 +; CHECK-DAG: '0x2d4c (SPI_SHADER_USER_DATA_LS_0)': 0x10000000 !amdgpu.pal.metadata.msgpack = !{!0} diff --git a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll index e73235857728..29520cb7468c 100644 --- a/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll +++ b/llvm/test/CodeGen/AMDGPU/wave_dispatch_regs.ll @@ -21,10 +21,10 @@ ; VI-NEXT: .vgpr_count: 0x5 ; GFX9-NEXT: .vgpr_count: 0x5 ; GCN-NEXT: .registers: -; SI-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81 -; VI-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}c1 -; GFX9-NEXT: 0x2e12 (COMPUTE_PGM_RSRC1): 0x{{[0-9a-f]*}}81 -; GCN-NEXT: 0x2e13 (COMPUTE_PGM_RSRC2): 0 +; SI-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}81 +; VI-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}c1 +; GFX9-NEXT: '0x2e12 (COMPUTE_PGM_RSRC1)': 0x{{[0-9a-f]*}}81 +; GCN-NEXT: '0x2e13 (COMPUTE_PGM_RSRC2)': 0 ; GCN-NEXT: ... ; GCN-NEXT: .end_amdgpu_pal_metadata diff --git a/llvm/test/MC/AMDGPU/pal-msgpack.s b/llvm/test/MC/AMDGPU/pal-msgpack.s index 886cc8b0538b..03c6c547af8a 100644 --- a/llvm/test/MC/AMDGPU/pal-msgpack.s +++ b/llvm/test/MC/AMDGPU/pal-msgpack.s @@ -14,10 +14,10 @@ amdpal.pipelines: - 0x123456789abcdef0 - 0xfedcba9876543210 .registers: - 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0 - 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 - 0xa1b3 (SPI_PS_INPUT_ENA): 0x1 - 0xa1b4 (SPI_PS_INPUT_ADDR): 0x1 + '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0 + '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42000000 + '0xa1b3 (SPI_PS_INPUT_ENA)': 0x1 + '0xa1b4 (SPI_PS_INPUT_ADDR)': 0x1 ... .end_amdgpu_pal_metadata @@ -34,10 +34,10 @@ amdpal.pipelines: // ASM: - 0x123456789abcdef0 // ASM: - 0xfedcba9876543210 // ASM: .registers: -// ASM: 0x2c0a (SPI_SHADER_PGM_RSRC1_PS): 0 -// ASM: 0x2c0b (SPI_SHADER_PGM_RSRC2_PS): 0x42000000 -// ASM: 0xa1b3 (SPI_PS_INPUT_ENA): 0x1 -// ASM: 0xa1b4 (SPI_PS_INPUT_ADDR): 0x1 +// ASM: '0x2c0a (SPI_SHADER_PGM_RSRC1_PS)': 0 +// ASM: '0x2c0b (SPI_SHADER_PGM_RSRC2_PS)': 0x42000000 +// ASM: '0xa1b3 (SPI_PS_INPUT_ENA)': 0x1 +// ASM: '0xa1b4 (SPI_PS_INPUT_ADDR)': 0x1 // ASM: ... // ASM: .end_amdgpu_pal_metadata diff --git a/llvm/unittests/Support/YAMLIOTest.cpp b/llvm/unittests/Support/YAMLIOTest.cpp index 401981f3841e..6ac0d1b412f0 100644 --- a/llvm/unittests/Support/YAMLIOTest.cpp +++ b/llvm/unittests/Support/YAMLIOTest.cpp @@ -2905,6 +2905,87 @@ TEST(YAMLIO, Numeric) { EXPECT_FALSE(isNumeric("1,230.15")); } +//===----------------------------------------------------------------------===// +// Test writing and reading escaped keys +//===----------------------------------------------------------------------===// + +// Struct with dynamic string key +struct QuotedKeyStruct { + int unquoted_bool; + int unquoted_null; + int unquoted_numeric; + int unquoted_str; + int colon; + int just_space; + int unprintable; +}; + +namespace llvm { +namespace yaml { +template <> struct MappingTraits { + static void mapping(IO &io, QuotedKeyStruct &map) { + io.mapRequired("true", map.unquoted_bool); + io.mapRequired("null", map.unquoted_null); + io.mapRequired("42", map.unquoted_numeric); + io.mapRequired("unquoted", map.unquoted_str); + io.mapRequired(":", map.colon); + io.mapRequired(" ", map.just_space); + char unprintableKey[] = {/* \f, form-feed */ 0xC, 0}; + io.mapRequired(unprintableKey, map.unprintable); + } +}; +} // namespace yaml +} // namespace llvm + +TEST(YAMLIO, TestQuotedKeyRead) { + QuotedKeyStruct map = {}; + Input yin("---\ntrue: 1\nnull: 2\n42: 3\nunquoted: 4\n':': 5\n' ': " + "6\n\"\\f\": 7\n...\n"); + yin >> map; + + EXPECT_FALSE(yin.error()); + EXPECT_EQ(map.unquoted_bool, 1); + EXPECT_EQ(map.unquoted_null, 2); + EXPECT_EQ(map.unquoted_numeric, 3); + EXPECT_EQ(map.unquoted_str, 4); + EXPECT_EQ(map.colon, 5); + EXPECT_EQ(map.just_space, 6); + EXPECT_EQ(map.unprintable, 7); +} + +TEST(YAMLIO, TestQuotedKeyWriteRead) { + std::string intermediate; + { + QuotedKeyStruct map = {1, 2, 3, 4, 5, 6, 7}; + llvm::raw_string_ostream ostr(intermediate); + Output yout(ostr); + yout << map; + } + + EXPECT_NE(std::string::npos, intermediate.find("true:")); + EXPECT_NE(std::string::npos, intermediate.find("null:")); + EXPECT_NE(std::string::npos, intermediate.find("42:")); + EXPECT_NE(std::string::npos, intermediate.find("unquoted:")); + EXPECT_NE(std::string::npos, intermediate.find("':':")); + EXPECT_NE(std::string::npos, intermediate.find("' '")); + EXPECT_NE(std::string::npos, intermediate.find("\"\\f\":")); + + { + Input yin(intermediate); + QuotedKeyStruct map; + yin >> map; + + EXPECT_FALSE(yin.error()); + EXPECT_EQ(map.unquoted_bool, 1); + EXPECT_EQ(map.unquoted_null, 2); + EXPECT_EQ(map.unquoted_numeric, 3); + EXPECT_EQ(map.unquoted_str, 4); + EXPECT_EQ(map.colon, 5); + EXPECT_EQ(map.just_space, 6); + EXPECT_EQ(map.unprintable, 7); + } +} + //===----------------------------------------------------------------------===// // Test PolymorphicTraits and TaggedScalarTraits //===----------------------------------------------------------------------===// -- GitLab From 86b9a4f892b9fc6cf5929f33a529570acd7abc71 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 29 Apr 2024 06:42:35 -0700 Subject: [PATCH 225/301] [SLP][NFC]Add a test with the skipped gather node, which is same, as vectorized node. --- .../X86/gather-node-same-as-vect-but-order.ll | 144 ++++++++++++++++++ 1 file changed, 144 insertions(+) create mode 100644 llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll b/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll new file mode 100644 index 000000000000..e66d38b54af3 --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll @@ -0,0 +1,144 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu -mcpu=x86-64-v4 < %s | FileCheck %s + +%struct.rect = type { float, float, float, float } + +define void @foo(ptr %i7, i32 %0, i1 %tobool62.not) { +; CHECK-LABEL: define void @foo( +; CHECK-SAME: ptr [[I7:%.*]], i32 [[TMP0:%.*]], i1 [[TOBOOL62_NOT:%.*]]) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[RC21:%.*]] = alloca [0 x [0 x %struct.rect]], i32 0, align 4 +; CHECK-NEXT: [[TMP1:%.*]] = load float, ptr [[RC21]], align 4 +; CHECK-NEXT: [[TMP2:%.*]] = insertelement <2 x i32> poison, i32 [[TMP0]], i32 0 +; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <2 x i32> [[TMP2]], <2 x i32> poison, <2 x i32> zeroinitializer +; CHECK-NEXT: [[TMP4:%.*]] = sitofp <2 x i32> [[TMP3]] to <2 x float> +; CHECK-NEXT: [[TMP5:%.*]] = shufflevector <2 x float> [[TMP4]], <2 x float> poison, <4 x i32> +; CHECK-NEXT: [[X1:%.*]] = getelementptr i8, ptr [[RC21]], i64 4 +; CHECK-NEXT: [[TMP6:%.*]] = load <2 x float>, ptr [[X1]], align 4 +; CHECK-NEXT: [[TMP7:%.*]] = load float, ptr [[I7]], align 4 +; CHECK-NEXT: [[TMP8:%.*]] = insertelement <4 x float> poison, float [[TMP1]], i32 0 +; CHECK-NEXT: [[TMP9:%.*]] = shufflevector <2 x float> [[TMP6]], <2 x float> poison, <4 x i32> +; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> [[TMP9]], <4 x i32> +; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP7]], i32 3 +; CHECK-NEXT: [[TMP12:%.*]] = fcmp olt <4 x float> [[TMP11]], zeroinitializer +; CHECK-NEXT: [[TMP13:%.*]] = load <4 x float>, ptr poison, align 16 +; CHECK-NEXT: [[TMP14:%.*]] = fcmp olt <4 x float> [[TMP13]], zeroinitializer +; CHECK-NEXT: [[TMP15:%.*]] = select <4 x i1> [[TMP14]], <4 x float> [[TMP5]], <4 x float> zeroinitializer +; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP12]], <4 x float> zeroinitializer, <4 x float> [[TMP15]] +; CHECK-NEXT: store <4 x float> [[TMP16]], ptr [[RC21]], align 4 +; CHECK-NEXT: br label [[IF_END:%.*]] +; CHECK: entry.if.end72_crit_edge: +; CHECK-NEXT: br label [[IF_END72:%.*]] +; CHECK: if.then63: +; CHECK-NEXT: br label [[IF_END]] +; CHECK: if.end: +; CHECK-NEXT: [[TMP17:%.*]] = phi <4 x float> [ poison, [[IF_THEN63:%.*]] ], [ [[TMP16]], [[ENTRY:%.*]] ] +; CHECK-NEXT: [[TMP18:%.*]] = call <4 x float> @llvm.round.v4f32(<4 x float> [[TMP17]]) +; CHECK-NEXT: [[TMP19:%.*]] = fptosi <4 x float> [[TMP18]] to <4 x i32> +; CHECK-NEXT: br label [[IF_END72]] +; CHECK: if.end72: +; CHECK-NEXT: [[TMP20:%.*]] = phi <4 x i32> [ poison, [[ENTRY_IF_END72_CRIT_EDGE:%.*]] ], [ [[TMP19]], [[IF_END]] ] +; CHECK-NEXT: [[TMP21:%.*]] = shufflevector <4 x i32> [[TMP20]], <4 x i32> poison, <4 x i32> +; CHECK-NEXT: br i1 [[TOBOOL62_NOT]], label [[IF_END75:%.*]], label [[IF_THEN74:%.*]] +; CHECK: if.then74: +; CHECK-NEXT: br label [[IF_END75]] +; CHECK: if.end75: +; CHECK-NEXT: [[TMP22:%.*]] = phi <4 x i32> [ [[TMP20]], [[IF_THEN74]] ], [ [[TMP21]], [[IF_END72]] ] +; CHECK-NEXT: [[TMP23:%.*]] = or <4 x i32> [[TMP22]], +; CHECK-NEXT: [[TMP24:%.*]] = shufflevector <2 x i32> [[TMP3]], <2 x i32> poison, <4 x i32> zeroinitializer +; CHECK-NEXT: [[TMP25:%.*]] = mul <4 x i32> [[TMP23]], [[TMP24]] +; CHECK-NEXT: [[TMP26:%.*]] = sitofp <4 x i32> [[TMP25]] to <4 x float> +; CHECK-NEXT: [[TMP27:%.*]] = shufflevector <4 x float> [[TMP26]], <4 x float> poison, <4 x i32> +; CHECK-NEXT: store <4 x float> [[TMP27]], ptr [[RC21]], align 4 +; CHECK-NEXT: ret void +; +entry: + %rc21 = alloca [0 x [0 x %struct.rect]], i32 0, align 4 + %1 = load float, ptr %rc21, align 4 + %cmp = fcmp olt float %1, 0.000000e+00 + %conv = sitofp i32 %0 to float + %cmp2 = fcmp olt float %conv, 0.000000e+00 + %cond = select i1 %cmp2, float %conv, float 0.000000e+00 + %cond9 = select i1 %cmp, float 0.000000e+00, float %cond + store float %cond9, ptr %rc21, align 4 + %x1 = getelementptr i8, ptr %rc21, i64 4 + %2 = load float, ptr %x1, align 4 + %cmp11 = fcmp olt float %2, 0.000000e+00 + %conv16 = sitofp i32 %0 to float + %cmp17 = fcmp olt float %conv16, 0.000000e+00 + %cond24 = select i1 %cmp17, float %conv16, float 0.000000e+00 + %cond26 = select i1 %cmp11, float 0.000000e+00, float %cond24 + store float %cond26, ptr %x1, align 4 + %y0 = getelementptr i8, ptr %rc21, i64 8 + %3 = load float, ptr %y0, align 4 + %cmp28 = fcmp olt float %3, 0.000000e+00 + %cmp34 = fcmp olt float %conv, 0.000000e+00 + %cond41 = select i1 %cmp34, float %conv, float 0.000000e+00 + %cond43 = select i1 %cmp28, float 0.000000e+00, float %cond41 + store float %cond43, ptr %y0, align 4 + %y11 = getelementptr i8, ptr %rc21, i64 12 + %4 = load float, ptr %i7, align 4 + %cmp45 = fcmp olt float %4, 0.000000e+00 + %cmp51 = fcmp olt float %conv16, 0.000000e+00 + %cond58 = select i1 %cmp51, float %conv16, float 0.000000e+00 + %cond60 = select i1 %cmp45, float 0.000000e+00, float %cond58 + store float %cond60, ptr %y11, align 4 + br label %if.end + +entry.if.end72_crit_edge: + br label %if.end72 + +if.then63: + br label %if.end + +if.end: + %5 = phi float [ 0.000000e+00, %if.then63 ], [ %cond60, %entry ] + %6 = phi float [ 0.000000e+00, %if.then63 ], [ %cond26, %entry ] + %7 = phi float [ 0.000000e+00, %if.then63 ], [ %cond43, %entry ] + %8 = phi float [ 0.000000e+00, %if.then63 ], [ %cond9, %entry ] + %9 = call float @llvm.round.f32(float %8) + %conv65 = fptosi float %9 to i32 + %10 = call float @llvm.round.f32(float %7) + %conv67 = fptosi float %10 to i32 + %11 = call float @llvm.round.f32(float %6) + %conv69 = fptosi float %11 to i32 + %12 = call float @llvm.round.f32(float %5) + %conv71 = fptosi float %12 to i32 + br label %if.end72 + +if.end72: + %.pre100 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv71, %if.end ] + %.pre99 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv67, %if.end ] + %.pre98 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv69, %if.end ] + %.pre97 = phi i32 [ 0, %entry.if.end72_crit_edge ], [ %conv65, %if.end ] + br i1 %tobool62.not, label %if.end75, label %if.then74 + +if.then74: + br label %if.end75 + +if.end75: + %13 = phi i32 [ %.pre99, %if.then74 ], [ %.pre100, %if.end72 ] + %14 = phi i32 [ %.pre100, %if.then74 ], [ %.pre99, %if.end72 ] + %15 = phi i32 [ %.pre97, %if.then74 ], [ %.pre98, %if.end72 ] + %16 = phi i32 [ %.pre98, %if.then74 ], [ %.pre97, %if.end72 ] + %sub = or i32 %16, 1 + %mul = mul i32 %sub, %0 + %conv77 = sitofp i32 %mul to float + store float %conv77, ptr %rc21, align 4 + %x178 = getelementptr i8, ptr %rc21, i64 4 + %sub79 = or i32 %15, 1 + %mul80 = mul i32 %sub79, %0 + %conv81 = sitofp i32 %mul80 to float + store float %conv81, ptr %x178, align 4 + %y082 = getelementptr i8, ptr %rc21, i64 8 + %sub83 = or i32 %14, 1 + %mul84 = mul i32 %sub83, %0 + %conv85 = sitofp i32 %mul84 to float + store float %conv85, ptr %y082, align 4 + %y186 = getelementptr i8, ptr %rc21, i64 12 + %sub87 = or i32 %13, 1 + %mul88 = mul i32 %sub87, %0 + %conv89 = sitofp i32 %mul88 to float + store float %conv89, ptr %y186, align 4 + ret void +} -- GitLab From 040b5a1255dba79f6e6819ac4864256127f810a0 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 29 Apr 2024 06:51:11 -0700 Subject: [PATCH 226/301] [SLP]Fix PR90211: vectorized node must match completely to be reused. If the gather node matches the vectorized node, it must also match with the scalars completely. Otherwise, need to revectorize the gather node to generate correct code. --- llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp | 3 ++- .../SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll | 3 +-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index f62270fe62eb..2facd03f5419 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -13166,7 +13166,8 @@ Value *BoUpSLP::vectorizeTree( auto *TE = const_cast(E); if (auto *VecTE = getTreeEntry(TE->Scalars.front())) if (VecTE->isSame(TE->UserTreeIndices.front().UserTE->getOperand( - TE->UserTreeIndices.front().EdgeIdx))) + TE->UserTreeIndices.front().EdgeIdx)) && + VecTE->isSame(TE->Scalars)) // Found gather node which is absolutely the same as one of the // vectorized nodes. It may happen after reordering. continue; diff --git a/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll b/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll index e66d38b54af3..d80d7b5ecd4e 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/gather-node-same-as-vect-but-order.ll @@ -21,8 +21,7 @@ define void @foo(ptr %i7, i32 %0, i1 %tobool62.not) { ; CHECK-NEXT: [[TMP10:%.*]] = shufflevector <4 x float> [[TMP8]], <4 x float> [[TMP9]], <4 x i32> ; CHECK-NEXT: [[TMP11:%.*]] = insertelement <4 x float> [[TMP10]], float [[TMP7]], i32 3 ; CHECK-NEXT: [[TMP12:%.*]] = fcmp olt <4 x float> [[TMP11]], zeroinitializer -; CHECK-NEXT: [[TMP13:%.*]] = load <4 x float>, ptr poison, align 16 -; CHECK-NEXT: [[TMP14:%.*]] = fcmp olt <4 x float> [[TMP13]], zeroinitializer +; CHECK-NEXT: [[TMP14:%.*]] = fcmp olt <4 x float> [[TMP5]], zeroinitializer ; CHECK-NEXT: [[TMP15:%.*]] = select <4 x i1> [[TMP14]], <4 x float> [[TMP5]], <4 x float> zeroinitializer ; CHECK-NEXT: [[TMP16:%.*]] = select <4 x i1> [[TMP12]], <4 x float> zeroinitializer, <4 x float> [[TMP15]] ; CHECK-NEXT: store <4 x float> [[TMP16]], ptr [[RC21]], align 4 -- GitLab From 37ae4ad0eef338776c7e2cffb3896153d43dcd90 Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 29 Apr 2024 09:57:37 -0400 Subject: [PATCH 227/301] [SLP]Support minbitwidth analisys for buildvector nodes. Metric: size..text Program size..text exp ref diff test-suite :: MultiSource/Benchmarks/mediabench/gsm/toast/toast.test 42906.00 42986.00 0.2% test-suite :: MultiSource/Benchmarks/MiBench/telecomm-gsm/telecomm-gsm.test 42909.00 42989.00 0.2% test-suite :: External/SPEC/CINT2017rate/525.x264_r/525.x264_r.test 664581.00 664661.00 0.0% test-suite :: External/SPEC/CINT2017speed/625.x264_s/625.x264_s.test 664581.00 664661.00 0.0% Less is better. Replaces `buildvector

+ trunc

to

` sequences to `buildvector

of { trunc in to im }` scalars, which is free in most cases, results in better code. Reviewers: RKSimon Reviewed By: RKSimon Pull Request: https://github.com/llvm/llvm-project/pull/88504 --- .../Transforms/Vectorize/SLPVectorizer.cpp | 328 +++++++++++------- ...ather-buildvector-with-minbitwidth-user.ll | 7 +- .../AArch64/gather-with-minbith-user.ll | 3 +- .../AArch64/user-node-not-in-bitwidths.ll | 7 +- .../SystemZ/minbitwidth-root-trunc.ll | 6 +- .../X86/minbitwidth-node-with-multi-users.ll | 3 +- 6 files changed, 217 insertions(+), 137 deletions(-) diff --git a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp index 2facd03f5419..e3a1b0d39a4d 100644 --- a/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp +++ b/llvm/lib/Transforms/Vectorize/SLPVectorizer.cpp @@ -2487,12 +2487,12 @@ private: /// which exploits values reused across lanes, and arranges the inserts /// for ease of later optimization. template - ResTy processBuildVector(const TreeEntry *E, Args &...Params); + ResTy processBuildVector(const TreeEntry *E, Type *ScalarTy, Args &...Params); /// Create a new vector from a list of scalar values. Produces a sequence /// which exploits values reused across lanes, and arranges the inserts /// for ease of later optimization. - Value *createBuildVector(const TreeEntry *E); + Value *createBuildVector(const TreeEntry *E, Type *ScalarTy); /// Returns the instruction in the bundle, which can be used as a base point /// for scheduling. Usually it is the last instruction in the bundle, except @@ -2556,7 +2556,8 @@ private: /// this subtree gets vectorized, we may need to extract the values from the /// roots. This method calculates the cost of extracting the values. /// \param ForPoisonSrc true if initial vector is poison, false otherwise. - InstructionCost getGatherCost(ArrayRef VL, bool ForPoisonSrc) const; + InstructionCost getGatherCost(ArrayRef VL, bool ForPoisonSrc, + Type *ScalarTy) const; /// Set the Builder insert point to one after the last instruction in /// the bundle @@ -2564,7 +2565,7 @@ private: /// \returns a vector from a collection of scalars in \p VL. if \p Root is not /// specified, the starting vector value is poison. - Value *gather(ArrayRef VL, Value *Root); + Value *gather(ArrayRef VL, Value *Root, Type *ScalarTy); /// \returns whether the VectorizableTree is fully vectorizable and will /// be beneficial even the tree height is tiny. @@ -7876,6 +7877,7 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { bool IsFinalized = false; SmallVector CommonMask; SmallVector, 2> InVectors; + Type *ScalarTy = nullptr; const TargetTransformInfo &TTI; InstructionCost Cost = 0; SmallDenseSet VectorizedVals; @@ -7905,13 +7907,13 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { InstructionCost getBuildVectorCost(ArrayRef VL, Value *Root) { if ((!Root && allConstant(VL)) || all_of(VL, IsaPred)) return TTI::TCC_Free; - auto *VecTy = FixedVectorType::get(VL.front()->getType(), VL.size()); + auto *VecTy = FixedVectorType::get(ScalarTy, VL.size()); InstructionCost GatherCost = 0; SmallVector Gathers(VL.begin(), VL.end()); // Improve gather cost for gather of loads, if we can group some of the // loads into vector loads. InstructionsState S = getSameOpcode(VL, *R.TLI); - const unsigned Sz = R.DL->getTypeSizeInBits(VL.front()->getType()); + const unsigned Sz = R.DL->getTypeSizeInBits(ScalarTy); unsigned MinVF = R.getMinVF(2 * Sz); if (VL.size() > 2 && ((S.getOpcode() == Instruction::Load && !S.isAltShuffle()) || @@ -7925,7 +7927,7 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { }))) && !all_of(Gathers, [&](Value *V) { return R.getTreeEntry(V); }) && !isSplat(Gathers)) { - InstructionCost BaseCost = R.getGatherCost(Gathers, !Root); + InstructionCost BaseCost = R.getGatherCost(Gathers, !Root, ScalarTy); SetVector VectorizedLoads; SmallVector> VectorizedStarts; SmallVector ScatterVectorized; @@ -8053,7 +8055,8 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { VecTy, Mask, CostKind); } } else { - GatherCost += R.getGatherCost(PointerOps, /*ForPoisonSrc=*/true); + GatherCost += R.getGatherCost(PointerOps, /*ForPoisonSrc=*/true, + PointerOps.front()->getType()); } } if (NeedInsertSubvectorAnalysis) { @@ -8087,18 +8090,19 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { transform(VL, ShuffleMask.begin(), [](Value *V) { return isa(V) ? PoisonMaskElem : 0; }); - InstructionCost InsertCost = TTI.getVectorInstrCost( - Instruction::InsertElement, VecTy, CostKind, 0, - PoisonValue::get(VecTy), *It); - return InsertCost + - TTI.getShuffleCost(TargetTransformInfo::SK_Broadcast, VecTy, - ShuffleMask, CostKind, /*Index=*/0, - /*SubTp=*/nullptr, /*Args=*/*It); + InstructionCost InsertCost = + TTI.getVectorInstrCost(Instruction::InsertElement, VecTy, CostKind, 0, + PoisonValue::get(VecTy), *It); + return InsertCost + TTI.getShuffleCost(TargetTransformInfo::SK_Broadcast, + VecTy, ShuffleMask, CostKind, + /*Index=*/0, /*SubTp=*/nullptr, + /*Args=*/*It); } return GatherCost + (all_of(Gathers, IsaPred) ? TTI::TCC_Free - : R.getGatherCost(Gathers, !Root && VL.equals(Gathers))); + : R.getGatherCost(Gathers, !Root && VL.equals(Gathers), + ScalarTy)); }; /// Compute the cost of creating a vector containing the extracted values from @@ -8118,8 +8122,8 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { return Sz; return std::max(Sz, VecTy->getNumElements()); }); - unsigned NumSrcRegs = TTI.getNumberOfParts( - FixedVectorType::get(VL.front()->getType(), NumElts)); + unsigned NumSrcRegs = + TTI.getNumberOfParts(FixedVectorType::get(ScalarTy, NumElts)); if (NumSrcRegs == 0) NumSrcRegs = 1; // FIXME: this must be moved to TTI for better estimation. @@ -8165,17 +8169,16 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { std::optional RegShuffleKind = CheckPerRegistersShuffle(SubMask); if (!RegShuffleKind) { - Cost += ::getShuffleCost( - TTI, *ShuffleKinds[Part], - FixedVectorType::get(VL.front()->getType(), NumElts), MaskSlice); + Cost += ::getShuffleCost(TTI, *ShuffleKinds[Part], + FixedVectorType::get(ScalarTy, NumElts), + MaskSlice); continue; } if (*RegShuffleKind != TTI::SK_PermuteSingleSrc || !ShuffleVectorInst::isIdentityMask(SubMask, EltsPerVector)) { - Cost += ::getShuffleCost( - TTI, *RegShuffleKind, - FixedVectorType::get(VL.front()->getType(), EltsPerVector), - SubMask); + Cost += ::getShuffleCost(TTI, *RegShuffleKind, + FixedVectorType::get(ScalarTy, EltsPerVector), + SubMask); } } return Cost; @@ -8292,6 +8295,48 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { SmallVector CommonMask(Mask.begin(), Mask.end()); Value *V1 = P1.dyn_cast(), *V2 = P2.dyn_cast(); unsigned CommonVF = Mask.size(); + InstructionCost ExtraCost = 0; + auto GetNodeMinBWAffectedCost = [&](const TreeEntry &E, + unsigned VF) -> InstructionCost { + if (E.State == TreeEntry::NeedToGather && allConstant(E.Scalars)) + return TTI::TCC_Free; + Type *EScalarTy = E.Scalars.front()->getType(); + bool IsSigned = true; + if (auto It = R.MinBWs.find(&E); It != R.MinBWs.end()) { + EScalarTy = IntegerType::get(EScalarTy->getContext(), It->second.first); + IsSigned = It->second.second; + } + if (EScalarTy != ScalarTy) { + unsigned CastOpcode = Instruction::Trunc; + unsigned DstSz = R.DL->getTypeSizeInBits(ScalarTy); + unsigned SrcSz = R.DL->getTypeSizeInBits(EScalarTy); + if (DstSz > SrcSz) + CastOpcode = IsSigned ? Instruction::SExt : Instruction::ZExt; + return TTI.getCastInstrCost(CastOpcode, + FixedVectorType::get(ScalarTy, VF), + FixedVectorType::get(EScalarTy, VF), + TTI::CastContextHint::None, CostKind); + } + return TTI::TCC_Free; + }; + auto GetValueMinBWAffectedCost = [&](const Value *V) -> InstructionCost { + if (isa(V)) + return TTI::TCC_Free; + auto *VecTy = cast(V->getType()); + Type *EScalarTy = VecTy->getElementType(); + if (EScalarTy != ScalarTy) { + bool IsSigned = !isKnownNonNegative(V, SimplifyQuery(*R.DL)); + unsigned CastOpcode = Instruction::Trunc; + unsigned DstSz = R.DL->getTypeSizeInBits(ScalarTy); + unsigned SrcSz = R.DL->getTypeSizeInBits(EScalarTy); + if (DstSz > SrcSz) + CastOpcode = IsSigned ? Instruction::SExt : Instruction::ZExt; + return TTI.getCastInstrCost( + CastOpcode, VectorType::get(ScalarTy, VecTy->getElementCount()), + VecTy, TTI::CastContextHint::None, CostKind); + } + return TTI::TCC_Free; + }; if (!V1 && !V2 && !P2.isNull()) { // Shuffle 2 entry nodes. const TreeEntry *E = P1.get(); @@ -8318,11 +8363,14 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { } } CommonVF = E->Scalars.size(); + ExtraCost += GetNodeMinBWAffectedCost(*E, CommonVF) + + GetNodeMinBWAffectedCost(*E2, CommonVF); + } else { + ExtraCost += GetNodeMinBWAffectedCost(*E, E->getVectorFactor()) + + GetNodeMinBWAffectedCost(*E2, E2->getVectorFactor()); } - V1 = Constant::getNullValue( - FixedVectorType::get(E->Scalars.front()->getType(), CommonVF)); - V2 = getAllOnesValue( - *R.DL, FixedVectorType::get(E->Scalars.front()->getType(), CommonVF)); + V1 = Constant::getNullValue(FixedVectorType::get(ScalarTy, CommonVF)); + V2 = getAllOnesValue(*R.DL, FixedVectorType::get(ScalarTy, CommonVF)); } else if (!V1 && P2.isNull()) { // Shuffle single entry node. const TreeEntry *E = P1.get(); @@ -8341,8 +8389,8 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { } CommonVF = E->Scalars.size(); } - V1 = Constant::getNullValue( - FixedVectorType::get(E->Scalars.front()->getType(), CommonVF)); + ExtraCost += GetNodeMinBWAffectedCost(*E, CommonVF); + V1 = Constant::getNullValue(FixedVectorType::get(ScalarTy, CommonVF)); // Not identity/broadcast? Try to see if the original vector is better. if (!E->ReorderIndices.empty() && CommonVF == E->ReorderIndices.size() && CommonVF == CommonMask.size() && @@ -8359,6 +8407,7 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { } } else if (V1 && P2.isNull()) { // Shuffle single vector. + ExtraCost += GetValueMinBWAffectedCost(V1); CommonVF = cast(V1->getType())->getNumElements(); assert( all_of(Mask, @@ -8385,11 +8434,11 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { } CommonVF = VF; } - V1 = Constant::getNullValue( - FixedVectorType::get(E2->Scalars.front()->getType(), CommonVF)); - V2 = getAllOnesValue( - *R.DL, - FixedVectorType::get(E2->Scalars.front()->getType(), CommonVF)); + ExtraCost += GetValueMinBWAffectedCost(V1); + V1 = Constant::getNullValue(FixedVectorType::get(ScalarTy, CommonVF)); + ExtraCost += GetNodeMinBWAffectedCost( + *E2, std::min(CommonVF, E2->getVectorFactor())); + V2 = getAllOnesValue(*R.DL, FixedVectorType::get(ScalarTy, CommonVF)); } else if (!V1 && V2) { // Shuffle vector and tree node. unsigned VF = cast(V2->getType())->getNumElements(); @@ -8413,11 +8462,11 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { } CommonVF = VF; } - V1 = Constant::getNullValue( - FixedVectorType::get(E1->Scalars.front()->getType(), CommonVF)); - V2 = getAllOnesValue( - *R.DL, - FixedVectorType::get(E1->Scalars.front()->getType(), CommonVF)); + ExtraCost += GetNodeMinBWAffectedCost( + *E1, std::min(CommonVF, E1->getVectorFactor())); + V1 = Constant::getNullValue(FixedVectorType::get(ScalarTy, CommonVF)); + ExtraCost += GetValueMinBWAffectedCost(V2); + V2 = getAllOnesValue(*R.DL, FixedVectorType::get(ScalarTy, CommonVF)); } else { assert(V1 && V2 && "Expected both vectors."); unsigned VF = cast(V1->getType())->getNumElements(); @@ -8428,30 +8477,33 @@ class BoUpSLP::ShuffleCostEstimator : public BaseShuffleAnalysis { return Idx < 2 * static_cast(CommonVF); }) && "All elements in mask must be less than 2 * CommonVF."); + ExtraCost += + GetValueMinBWAffectedCost(V1) + GetValueMinBWAffectedCost(V2); if (V1->getType() != V2->getType()) { - V1 = Constant::getNullValue(FixedVectorType::get( - cast(V1->getType())->getElementType(), CommonVF)); - V2 = getAllOnesValue( - *R.DL, FixedVectorType::get( - cast(V1->getType())->getElementType(), - CommonVF)); + V1 = Constant::getNullValue(FixedVectorType::get(ScalarTy, CommonVF)); + V2 = getAllOnesValue(*R.DL, FixedVectorType::get(ScalarTy, CommonVF)); + } else { + if (cast(V1->getType())->getElementType() != ScalarTy) + V1 = Constant::getNullValue(FixedVectorType::get(ScalarTy, CommonVF)); + if (cast(V2->getType())->getElementType() != ScalarTy) + V2 = getAllOnesValue(*R.DL, FixedVectorType::get(ScalarTy, CommonVF)); } } - InVectors.front() = Constant::getNullValue(FixedVectorType::get( - cast(V1->getType())->getElementType(), - CommonMask.size())); + InVectors.front() = Constant::getNullValue( + FixedVectorType::get(ScalarTy, CommonMask.size())); if (InVectors.size() == 2) InVectors.pop_back(); - return BaseShuffleAnalysis::createShuffle( - V1, V2, CommonMask, Builder); + return ExtraCost + BaseShuffleAnalysis::createShuffle( + V1, V2, CommonMask, Builder); } public: - ShuffleCostEstimator(TargetTransformInfo &TTI, + ShuffleCostEstimator(Type *ScalarTy, TargetTransformInfo &TTI, ArrayRef VectorizedVals, BoUpSLP &R, SmallPtrSetImpl &CheckedExtracts) - : TTI(TTI), VectorizedVals(VectorizedVals.begin(), VectorizedVals.end()), - R(R), CheckedExtracts(CheckedExtracts) {} + : ScalarTy(ScalarTy), TTI(TTI), + VectorizedVals(VectorizedVals.begin(), VectorizedVals.end()), R(R), + CheckedExtracts(CheckedExtracts) {} Value *adjustExtracts(const TreeEntry *E, MutableArrayRef Mask, ArrayRef> ShuffleKinds, unsigned NumParts, bool &UseVecBaseAsInput) { @@ -8547,7 +8599,7 @@ public: if (NumParts != 1 && UniqueBases.size() != 1) { UseVecBaseAsInput = true; VecBase = Constant::getNullValue( - FixedVectorType::get(VL.front()->getType(), CommonMask.size())); + FixedVectorType::get(ScalarTy, CommonMask.size())); } return VecBase; } @@ -8575,8 +8627,7 @@ public: return; } assert(!CommonMask.empty() && "Expected non-empty common mask."); - auto *MaskVecTy = - FixedVectorType::get(E1.Scalars.front()->getType(), Mask.size()); + auto *MaskVecTy = FixedVectorType::get(ScalarTy, Mask.size()); unsigned NumParts = TTI.getNumberOfParts(MaskVecTy); if (NumParts == 0 || NumParts >= Mask.size()) NumParts = 1; @@ -8593,8 +8644,7 @@ public: return; } assert(!CommonMask.empty() && "Expected non-empty common mask."); - auto *MaskVecTy = - FixedVectorType::get(E1.Scalars.front()->getType(), Mask.size()); + auto *MaskVecTy = FixedVectorType::get(ScalarTy, Mask.size()); unsigned NumParts = TTI.getNumberOfParts(MaskVecTy); if (NumParts == 0 || NumParts >= Mask.size()) NumParts = 1; @@ -8694,7 +8744,7 @@ public: return ConstantVector::getSplat( ElementCount::getFixed( cast(Root->getType())->getNumElements()), - getAllOnesValue(*R.DL, VL.front()->getType())); + getAllOnesValue(*R.DL, ScalarTy)); } InstructionCost createFreeze(InstructionCost Cost) { return Cost; } /// Finalize emission of the shuffles. @@ -8840,7 +8890,7 @@ BoUpSLP::getEntryCost(const TreeEntry *E, ArrayRef VectorizedVals, if (isa(VL[0])) return InstructionCost::getInvalid(); return processBuildVector( - E, *TTI, VectorizedVals, *this, CheckedExtracts); + E, ScalarTy, *TTI, VectorizedVals, *this, CheckedExtracts); } InstructionCost CommonCost = 0; SmallVector Mask; @@ -10880,12 +10930,8 @@ BoUpSLP::isGatherShuffledEntry( return Res; } -InstructionCost BoUpSLP::getGatherCost(ArrayRef VL, - bool ForPoisonSrc) const { - // Find the type of the operands in VL. - Type *ScalarTy = VL[0]->getType(); - if (StoreInst *SI = dyn_cast(VL[0])) - ScalarTy = SI->getValueOperand()->getType(); +InstructionCost BoUpSLP::getGatherCost(ArrayRef VL, bool ForPoisonSrc, + Type *ScalarTy) const { auto *VecTy = FixedVectorType::get(ScalarTy, VL.size()); bool DuplicateNonConst = false; // Find the cost of inserting/extracting values from the vector. @@ -10896,6 +10942,11 @@ InstructionCost BoUpSLP::getGatherCost(ArrayRef VL, constexpr TTI::TargetCostKind CostKind = TTI::TCK_RecipThroughput; InstructionCost Cost; auto EstimateInsertCost = [&](unsigned I, Value *V) { + if (V->getType() != ScalarTy) { + Cost += TTI->getCastInstrCost(Instruction::Trunc, ScalarTy, V->getType(), + TTI::CastContextHint::None, CostKind); + V = nullptr; + } if (!ForPoisonSrc) Cost += TTI->getVectorInstrCost(Instruction::InsertElement, VecTy, CostKind, @@ -11123,7 +11174,7 @@ void BoUpSLP::setInsertPointAfterBundle(const TreeEntry *E) { Builder.SetCurrentDebugLocation(Front->getDebugLoc()); } -Value *BoUpSLP::gather(ArrayRef VL, Value *Root) { +Value *BoUpSLP::gather(ArrayRef VL, Value *Root, Type *ScalarTy) { // List of instructions/lanes from current block and/or the blocks which are // part of the current loop. These instructions will be inserted at the end to // make it possible to optimize loops and hoist invariant instructions out of @@ -11149,14 +11200,11 @@ Value *BoUpSLP::gather(ArrayRef VL, Value *Root) { auto &&CreateInsertElement = [this](Value *Vec, Value *V, unsigned Pos, Type *Ty) { Value *Scalar = V; - if (cast(Vec->getType())->getElementType() != Ty) { - assert(V->getType()->isIntegerTy() && Ty->isIntegerTy() && + if (Scalar->getType() != Ty) { + assert(Scalar->getType()->isIntegerTy() && Ty->isIntegerTy() && "Expected integer types only."); - Vec = Builder.CreateIntCast( - Vec, - VectorType::get(Ty, - cast(Vec->getType())->getElementCount()), - !isKnownNonNegative(Vec, SimplifyQuery(*DL))); + Scalar = Builder.CreateIntCast( + Scalar, Ty, !isKnownNonNegative(Scalar, SimplifyQuery(*DL))); } Vec = Builder.CreateInsertElement(Vec, Scalar, Builder.getInt32(Pos)); @@ -11184,10 +11232,7 @@ Value *BoUpSLP::gather(ArrayRef VL, Value *Root) { } return Vec; }; - Value *Val0 = - isa(VL[0]) ? cast(VL[0])->getValueOperand() : VL[0]; - Type *ScalarTy = Val0->getType(); - FixedVectorType *VecTy = FixedVectorType::get(ScalarTy, VL.size()); + auto *VecTy = FixedVectorType::get(ScalarTy, VL.size()); Value *Vec = Root ? Root : PoisonValue::get(VecTy); SmallVector NonConsts; // Insert constant values at first. @@ -11266,6 +11311,7 @@ class BoUpSLP::ShuffleInstructionBuilder final : public BaseShuffleAnalysis { /// resulting shuffle and the second operand sets to be the newly added /// operand. The \p CommonMask is transformed in the proper way after that. SmallVector InVectors; + Type *ScalarTy = nullptr; IRBuilderBase &Builder; BoUpSLP &R; @@ -11376,9 +11422,20 @@ class BoUpSLP::ShuffleInstructionBuilder final : public BaseShuffleAnalysis { CommonMask[Idx] = Idx; } + /// Cast value \p V to the vector type with the same number of elements, but + /// the base type \p ScalarTy. + Value *castToScalarTyElem(Value *V) { + auto *VecTy = cast(V->getType()); + if (VecTy->getElementType() == ScalarTy) + return V; + return Builder.CreateIntCast( + V, VectorType::get(ScalarTy, VecTy->getElementCount()), + !isKnownNonNegative(V, SimplifyQuery(*R.DL))); + } + public: - ShuffleInstructionBuilder(IRBuilderBase &Builder, BoUpSLP &R) - : Builder(Builder), R(R) {} + ShuffleInstructionBuilder(Type *ScalarTy, IRBuilderBase &Builder, BoUpSLP &R) + : ScalarTy(ScalarTy), Builder(Builder), R(R) {} /// Adjusts extractelements after reusing them. Value *adjustExtracts(const TreeEntry *E, MutableArrayRef Mask, @@ -11417,8 +11474,10 @@ public: continue; R.eraseInstruction(EI); } - if (NumParts == 1 || UniqueBases.size() == 1) + if (NumParts == 1 || UniqueBases.size() == 1) { + VecBase = castToScalarTyElem(VecBase); return VecBase; + } UseVecBaseAsInput = true; auto TransformToIdentity = [](MutableArrayRef Mask) { for (auto [I, Idx] : enumerate(Mask)) @@ -11455,6 +11514,7 @@ public: "Expected vectors of the same size."); PrevSize = Size; #endif // NDEBUG + VecOp = castToScalarTyElem(VecOp); Bases[SubMask[I] < Size ? 0 : 1] = VecOp; } if (!Bases.front()) @@ -11510,10 +11570,10 @@ public: return std::nullopt; // Postpone gather emission, will be emitted after the end of the // process to keep correct order. - auto *VecTy = FixedVectorType::get(E->Scalars.front()->getType(), - E->getVectorFactor()); + auto *ResVecTy = FixedVectorType::get(ScalarTy, E->getVectorFactor()); return Builder.CreateAlignedLoad( - VecTy, PoisonValue::get(PointerType::getUnqual(VecTy->getContext())), + ResVecTy, + PoisonValue::get(PointerType::getUnqual(ScalarTy->getContext())), MaybeAlign()); } /// Adds 2 input vectors (in form of tree entries) and the mask for their @@ -11529,6 +11589,8 @@ public: /// Adds 2 input vectors and the mask for their shuffling. void add(Value *V1, Value *V2, ArrayRef Mask) { assert(V1 && V2 && !Mask.empty() && "Expected non-empty input vectors."); + V1 = castToScalarTyElem(V1); + V2 = castToScalarTyElem(V2); if (InVectors.empty()) { InVectors.push_back(V1); InVectors.push_back(V2); @@ -11556,6 +11618,7 @@ public: } /// Adds another one input vector and the mask for the shuffling. void add(Value *V1, ArrayRef Mask, bool = false) { + V1 = castToScalarTyElem(V1); if (InVectors.empty()) { if (!isa(V1->getType())) { V1 = createShuffle(V1, nullptr, CommonMask); @@ -11619,7 +11682,7 @@ public: } Value *gather(ArrayRef VL, unsigned MaskVF = 0, Value *Root = nullptr) { - return R.gather(VL, Root); + return R.gather(VL, Root, ScalarTy); } Value *createFreeze(Value *V) { return Builder.CreateFreeze(V); } /// Finalize emission of the shuffles. @@ -11719,7 +11782,8 @@ Value *BoUpSLP::vectorizeOperand(TreeEntry *E, unsigned NodeIdx, } if (IsSameVE) { auto FinalShuffle = [&](Value *V, ArrayRef Mask) { - ShuffleInstructionBuilder ShuffleBuilder(Builder, *this); + ShuffleInstructionBuilder ShuffleBuilder( + cast(V->getType())->getElementType(), Builder, *this); ShuffleBuilder.add(V, Mask); return ShuffleBuilder.finalize(std::nullopt); }; @@ -11794,7 +11858,8 @@ Value *BoUpSLP::vectorizeOperand(TreeEntry *E, unsigned NodeIdx, } template -ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { +ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Type *ScalarTy, + Args &...Params) { assert(E->State == TreeEntry::NeedToGather && "Expected gather node."); unsigned VF = E->getVectorFactor(); @@ -11842,7 +11907,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { } return true; }; - BVTy ShuffleBuilder(Params...); + BVTy ShuffleBuilder(ScalarTy, Params...); ResTy Res = ResTy(); SmallVector Mask; SmallVector ExtractMask(GatheredScalars.size(), PoisonMaskElem); @@ -11851,7 +11916,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { bool UseVecBaseAsInput = false; SmallVector> GatherShuffles; SmallVector> Entries; - Type *ScalarTy = GatheredScalars.front()->getType(); + Type *OrigScalarTy = GatheredScalars.front()->getType(); auto *VecTy = FixedVectorType::get(ScalarTy, GatheredScalars.size()); unsigned NumParts = TTI->getNumberOfParts(VecTy); if (NumParts == 0 || NumParts >= GatheredScalars.size()) @@ -11886,7 +11951,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { GatheredScalars.size() != VF) { Resized = true; GatheredScalars.append(VF - GatheredScalars.size(), - PoisonValue::get(ScalarTy)); + PoisonValue::get(OrigScalarTy)); } } } @@ -11946,12 +12011,12 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { }); })) GatheredScalars.append(VF - GatheredScalars.size(), - PoisonValue::get(ScalarTy)); + PoisonValue::get(OrigScalarTy)); } // Remove shuffled elements from list of gathers. for (int I = 0, Sz = Mask.size(); I < Sz; ++I) { if (Mask[I] != PoisonMaskElem) - GatheredScalars[I] = PoisonValue::get(ScalarTy); + GatheredScalars[I] = PoisonValue::get(OrigScalarTy); } } } @@ -11962,7 +12027,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { // such sequences. bool IsSplat = IsRootPoison && isSplat(Scalars) && (Scalars.size() > 2 || Scalars.front() == Scalars.back()); - Scalars.append(VF - Scalars.size(), PoisonValue::get(ScalarTy)); + Scalars.append(VF - Scalars.size(), PoisonValue::get(OrigScalarTy)); SmallVector UndefPos; DenseMap UniquePositions; // Gather unique non-const values and all constant values. @@ -11984,7 +12049,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { ++NumNonConsts; SinglePos = I; Value *OrigV = V; - Scalars[I] = PoisonValue::get(ScalarTy); + Scalars[I] = PoisonValue::get(OrigScalarTy); if (IsSplat) { Scalars.front() = OrigV; ReuseMask[I] = 0; @@ -12000,7 +12065,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { ReuseMask.assign(VF, PoisonMaskElem); std::swap(Scalars.front(), Scalars[SinglePos]); if (!UndefPos.empty() && UndefPos.front() == 0) - Scalars.front() = UndefValue::get(ScalarTy); + Scalars.front() = UndefValue::get(OrigScalarTy); } ReuseMask[SinglePos] = SinglePos; } else if (!UndefPos.empty() && IsSplat) { @@ -12030,7 +12095,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { // Replace the undef by the poison, in the mask it is replaced by // non-poisoned scalar already. if (I != Pos) - Scalars[I] = PoisonValue::get(ScalarTy); + Scalars[I] = PoisonValue::get(OrigScalarTy); } } else { // Replace undefs by the poisons, emit broadcast and then emit @@ -12038,7 +12103,7 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { for (int I : UndefPos) { ReuseMask[I] = PoisonMaskElem; if (isa(Scalars[I])) - Scalars[I] = PoisonValue::get(ScalarTy); + Scalars[I] = PoisonValue::get(OrigScalarTy); } NeedFreeze = true; } @@ -12093,9 +12158,8 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { IsNonPoisoned &= isGuaranteedNotToBePoison(Vec1); } else { IsUsedInExpr = false; - ShuffleBuilder.add(PoisonValue::get(FixedVectorType::get( - ScalarTy, GatheredScalars.size())), - ExtractMask, /*ForExtracts=*/true); + ShuffleBuilder.add(PoisonValue::get(VecTy), ExtractMask, + /*ForExtracts=*/true); } } if (!GatherShuffles.empty()) { @@ -12176,9 +12240,9 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { // contains only constant to build final vector and then shuffle. for (int I = 0, Sz = GatheredScalars.size(); I < Sz; ++I) { if (EnoughConstsForShuffle && isa(GatheredScalars[I])) - NonConstants[I] = PoisonValue::get(ScalarTy); + NonConstants[I] = PoisonValue::get(OrigScalarTy); else - GatheredScalars[I] = PoisonValue::get(ScalarTy); + GatheredScalars[I] = PoisonValue::get(OrigScalarTy); } // Generate constants for final shuffle and build a mask for them. if (!all_of(GatheredScalars, IsaPred)) { @@ -12224,9 +12288,9 @@ ResTy BoUpSLP::processBuildVector(const TreeEntry *E, Args &...Params) { return Res; } -Value *BoUpSLP::createBuildVector(const TreeEntry *E) { - return processBuildVector(E, Builder, - *this); +Value *BoUpSLP::createBuildVector(const TreeEntry *E, Type *ScalarTy) { + return processBuildVector(E, ScalarTy, + Builder, *this); } Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { @@ -12239,18 +12303,28 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { return E->VectorizedValue; } + Value *V = E->Scalars.front(); + Type *ScalarTy = V->getType(); + if (auto *Store = dyn_cast(V)) + ScalarTy = Store->getValueOperand()->getType(); + else if (auto *IE = dyn_cast(V)) + ScalarTy = IE->getOperand(1)->getType(); + auto It = MinBWs.find(E); + if (It != MinBWs.end()) + ScalarTy = IntegerType::get(F->getContext(), It->second.first); + auto *VecTy = FixedVectorType::get(ScalarTy, E->Scalars.size()); if (E->State == TreeEntry::NeedToGather) { // Set insert point for non-reduction initial nodes. if (E->getMainOp() && E->Idx == 0 && !UserIgnoreList) setInsertPointAfterBundle(E); - Value *Vec = createBuildVector(E); + Value *Vec = createBuildVector(E, ScalarTy); E->VectorizedValue = Vec; return Vec; } bool IsReverseOrder = isReverseOrder(E->ReorderIndices); auto FinalShuffle = [&](Value *V, const TreeEntry *E, VectorType *VecTy) { - ShuffleInstructionBuilder ShuffleBuilder(Builder, *this); + ShuffleInstructionBuilder ShuffleBuilder(ScalarTy, Builder, *this); if (E->getOpcode() == Instruction::Store) { ArrayRef Mask = ArrayRef(reinterpret_cast(E->ReorderIndices.begin()), @@ -12271,14 +12345,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { unsigned ShuffleOrOp = E->isAltShuffle() ? (unsigned)Instruction::ShuffleVector : E->getOpcode(); Instruction *VL0 = E->getMainOp(); - Type *ScalarTy = VL0->getType(); - if (auto *Store = dyn_cast(VL0)) - ScalarTy = Store->getValueOperand()->getType(); - else if (auto *IE = dyn_cast(VL0)) - ScalarTy = IE->getOperand(1)->getType(); - auto It = MinBWs.find(E); - if (It != MinBWs.end()) - ScalarTy = IntegerType::get(F->getContext(), It->second.first); auto GetOperandSignedness = [&](unsigned Idx) { const TreeEntry *OpE = getOperandEntry(E, Idx); bool IsSigned = false; @@ -12291,7 +12357,6 @@ Value *BoUpSLP::vectorizeTree(TreeEntry *E, bool PostponedPHIs) { }); return IsSigned; }; - auto *VecTy = FixedVectorType::get(ScalarTy, E->Scalars.size()); switch (ShuffleOrOp) { case Instruction::PHI: { assert((E->ReorderIndices.empty() || !E->ReuseShuffleIndices.empty() || @@ -13545,7 +13610,8 @@ Value *BoUpSLP::vectorizeTree( else CombinedMask2[I] = Mask[I] - VF; } - ShuffleInstructionBuilder ShuffleBuilder(Builder, *this); + ShuffleInstructionBuilder ShuffleBuilder( + cast(V1->getType())->getElementType(), Builder, *this); ShuffleBuilder.add(V1, CombinedMask1); if (V2) ShuffleBuilder.add(V2, CombinedMask2); @@ -14580,13 +14646,27 @@ bool BoUpSLP::collectValuesToDemote( return false; bool Res = all_of( E.Scalars, std::bind(IsPotentiallyTruncated, _1, std::ref(BitWidth))); - // Gather demoted constant operands. - if (Res && E.State == TreeEntry::NeedToGather && - all_of(E.Scalars, IsaPred)) - ToDemote.push_back(E.Idx); + // Demote gathers. + if (Res && E.State == TreeEntry::NeedToGather) { + // Check possible extractelement instructions bases and final vector + // length. + SmallPtrSet UniqueBases; + for (Value *V : E.Scalars) { + auto *EE = dyn_cast(V); + if (!EE) + continue; + UniqueBases.insert(EE->getVectorOperand()); + } + const unsigned VF = E.Scalars.size(); + Type *OrigScalarTy = E.Scalars.front()->getType(); + if (UniqueBases.size() <= 2 || + TTI->getNumberOfParts(FixedVectorType::get(OrigScalarTy, VF)) == + TTI->getNumberOfParts(FixedVectorType::get( + IntegerType::get(OrigScalarTy->getContext(), BitWidth), VF))) + ToDemote.push_back(E.Idx); + } return Res; }; - // TODO: improve handling of gathered values and others. if (E.State == TreeEntry::NeedToGather || !Visited.insert(&E).second || any_of(E.Scalars, [&](Value *V) { return all_of(V->users(), [&](User *U) { diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll index 690772472975..3771ec4bda88 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-buildvector-with-minbitwidth-user.ll @@ -5,12 +5,7 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i32> , i32 0, i32 0 -; CHECK-NEXT: [[TMP1:%.*]] = trunc <8 x i32> [[TMP0]] to <8 x i1> -; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i1> zeroinitializer, [[TMP1]] -; CHECK-NEXT: [[TMP4:%.*]] = or <8 x i1> [[TMP2]], zeroinitializer -; CHECK-NEXT: [[TMP3:%.*]] = zext <8 x i1> [[TMP4]] to <8 x i16> -; CHECK-NEXT: store <8 x i16> [[TMP3]], ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll index d51ef0bce3a4..76bb882171b1 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/gather-with-minbith-user.ll @@ -5,7 +5,8 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: [[TMP0:%.*]] = trunc <8 x i32> zeroinitializer to <8 x i1> +; CHECK-NEXT: [[TMP6:%.*]] = trunc i32 0 to i1 +; CHECK-NEXT: [[TMP0:%.*]] = insertelement <8 x i1> , i1 [[TMP6]], i32 4 ; CHECK-NEXT: [[TMP1:%.*]] = sub <8 x i1> [[TMP0]], zeroinitializer ; CHECK-NEXT: [[TMP2:%.*]] = add <8 x i1> [[TMP0]], zeroinitializer ; CHECK-NEXT: [[TMP3:%.*]] = shufflevector <8 x i1> [[TMP1]], <8 x i1> [[TMP2]], <8 x i32> diff --git a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll index 6404cf4a2cd1..2ab6e919c23b 100644 --- a/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll +++ b/llvm/test/Transforms/SLPVectorizer/AArch64/user-node-not-in-bitwidths.ll @@ -5,7 +5,12 @@ define void @h() { ; CHECK-LABEL: define void @h() { ; CHECK-NEXT: entry: ; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr i8, ptr null, i64 16 -; CHECK-NEXT: store <8 x i16> zeroinitializer, ptr [[ARRAYIDX2]], align 2 +; CHECK-NEXT: [[TMP0:%.*]] = trunc i32 0 to i1 +; CHECK-NEXT: [[TMP1:%.*]] = insertelement <8 x i1> , i1 [[TMP0]], i32 4 +; CHECK-NEXT: [[TMP2:%.*]] = or <8 x i1> zeroinitializer, [[TMP1]] +; CHECK-NEXT: [[TMP3:%.*]] = or <8 x i1> zeroinitializer, [[TMP2]] +; CHECK-NEXT: [[TMP4:%.*]] = zext <8 x i1> [[TMP3]] to <8 x i16> +; CHECK-NEXT: store <8 x i16> [[TMP4]], ptr [[ARRAYIDX2]], align 2 ; CHECK-NEXT: ret void ; entry: diff --git a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll index 7b4e2b0ce911..1bb87bf6205f 100644 --- a/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll +++ b/llvm/test/Transforms/SLPVectorizer/SystemZ/minbitwidth-root-trunc.ll @@ -7,9 +7,9 @@ define void @test(ptr %a, i8 %0, i16 %b.promoted.i) { ; CHECK-NEXT: [[TMP2:%.*]] = zext i8 [[TMP0]] to i128 ; CHECK-NEXT: [[TMP3:%.*]] = insertelement <4 x i16> poison, i16 [[B_PROMOTED_I]], i32 0 ; CHECK-NEXT: [[TMP4:%.*]] = shufflevector <4 x i16> [[TMP3]], <4 x i16> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP5:%.*]] = insertelement <4 x i128> poison, i128 [[TMP2]], i32 0 -; CHECK-NEXT: [[TMP6:%.*]] = shufflevector <4 x i128> [[TMP5]], <4 x i128> poison, <4 x i32> zeroinitializer -; CHECK-NEXT: [[TMP7:%.*]] = trunc <4 x i128> [[TMP6]] to <4 x i16> +; CHECK-NEXT: [[TMP5:%.*]] = trunc i128 [[TMP2]] to i16 +; CHECK-NEXT: [[TMP6:%.*]] = insertelement <4 x i16> poison, i16 [[TMP5]], i32 0 +; CHECK-NEXT: [[TMP7:%.*]] = shufflevector <4 x i16> [[TMP6]], <4 x i16> poison, <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP8:%.*]] = or <4 x i16> [[TMP4]], [[TMP7]] ; CHECK-NEXT: [[TMP9:%.*]] = call i16 @llvm.vector.reduce.and.v4i16(<4 x i16> [[TMP8]]) ; CHECK-NEXT: [[TMP11:%.*]] = zext i16 [[TMP9]] to i64 diff --git a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll index 668d3c3c8c82..0ab56279fe47 100644 --- a/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll +++ b/llvm/test/Transforms/SLPVectorizer/X86/minbitwidth-node-with-multi-users.ll @@ -16,8 +16,7 @@ define void @test() { ; CHECK-NEXT: [[TMP9:%.*]] = trunc <4 x i8> [[TMP8]] to <4 x i1> ; CHECK-NEXT: [[TMP10:%.*]] = or <4 x i1> zeroinitializer, [[TMP15]] ; CHECK-NEXT: [[TMP11:%.*]] = icmp eq <4 x i1> [[TMP9]], [[TMP10]] -; CHECK-NEXT: [[TMP16:%.*]] = shufflevector <4 x i1> [[TMP15]], <4 x i1> poison, <4 x i32> -; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP16]] to <4 x i32> +; CHECK-NEXT: [[TMP6:%.*]] = zext <4 x i1> [[TMP15]] to <4 x i32> ; CHECK-NEXT: [[TMP12:%.*]] = shufflevector <4 x i32> [[TMP6]], <4 x i32> , <4 x i32> ; CHECK-NEXT: [[TMP13:%.*]] = select <4 x i1> [[TMP11]], <4 x i32> [[TMP12]], <4 x i32> zeroinitializer ; CHECK-NEXT: [[TMP14:%.*]] = call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[TMP13]]) -- GitLab From e71840305d621dcc43d5253e332db990220b7fcb Mon Sep 17 00:00:00 2001 From: yronglin Date: Mon, 29 Apr 2024 22:00:10 +0800 Subject: [PATCH 228/301] [Clang] Implement C++26 P2748R5 "Disallow Binding a Returned Glvalue to a Temporary" (#89942) Implement P2748R5 "Disallow Binding a Returned Glvalue to a Temporary" https://wg21.link/P2748R5 --------- Signed-off-by: yronglin --- clang/docs/ReleaseNotes.rst | 1 + .../clang/Basic/DiagnosticSemaKinds.td | 2 ++ clang/lib/Sema/SemaInit.cpp | 13 +++++++-- clang/test/CXX/drs/cwg650.cpp | 2 +- clang/test/CXX/stmt.stmt/stmt.return/p6.cpp | 25 +++++++++++++++++ clang/test/SemaCXX/type-traits.cpp | 28 +++++++++++++++++++ clang/www/cxx_status.html | 2 +- 7 files changed, 69 insertions(+), 4 deletions(-) create mode 100644 clang/test/CXX/stmt.stmt/stmt.return/p6.cpp diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 604782ca43dd..347c81253d39 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -145,6 +145,7 @@ C++2c Feature Support - Implemented `P0609R3: Attributes for Structured Bindings `_ +- Implemented `P2748R5 Disallow Binding a Returned Glvalue to a Temporary `_. Resolutions to C++ Defect Reports ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index fdca82934cb4..8486fa3a02e8 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -9950,6 +9950,8 @@ def warn_ret_stack_addr_ref : Warning< def warn_ret_local_temp_addr_ref : Warning< "returning %select{address of|reference to}0 local temporary object">, InGroup; +def err_ret_local_temp_ref : Error< + "returning reference to local temporary object">; def warn_ret_addr_label : Warning< "returning address of label, which is local">, InGroup; diff --git a/clang/lib/Sema/SemaInit.cpp b/clang/lib/Sema/SemaInit.cpp index 842d165c60d9..7d9eaf672046 100644 --- a/clang/lib/Sema/SemaInit.cpp +++ b/clang/lib/Sema/SemaInit.cpp @@ -8340,8 +8340,17 @@ void Sema::checkInitializerLifetime(const InitializedEntity &Entity, << Entity.getType()->isReferenceType() << CLE->getInitializer() << 2 << DiagRange; } else { - Diag(DiagLoc, diag::warn_ret_local_temp_addr_ref) - << Entity.getType()->isReferenceType() << DiagRange; + // P2748R5: Disallow Binding a Returned Glvalue to a Temporary. + // [stmt.return]/p6: In a function whose return type is a reference, + // other than an invented function for std::is_convertible ([meta.rel]), + // a return statement that binds the returned reference to a temporary + // expression ([class.temporary]) is ill-formed. + if (getLangOpts().CPlusPlus26 && Entity.getType()->isReferenceType()) + Diag(DiagLoc, diag::err_ret_local_temp_ref) + << Entity.getType()->isReferenceType() << DiagRange; + else + Diag(DiagLoc, diag::warn_ret_local_temp_addr_ref) + << Entity.getType()->isReferenceType() << DiagRange; } break; } diff --git a/clang/test/CXX/drs/cwg650.cpp b/clang/test/CXX/drs/cwg650.cpp index dcb844095b05..33ea179986e3 100644 --- a/clang/test/CXX/drs/cwg650.cpp +++ b/clang/test/CXX/drs/cwg650.cpp @@ -4,7 +4,7 @@ // RUN: %clang_cc1 -std=c++17 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK // RUN: %clang_cc1 -std=c++20 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK // RUN: %clang_cc1 -std=c++23 %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK -// RUN: %clang_cc1 -std=c++2c %s -triple x86_64-linux-gnu -emit-llvm -o - -fexceptions -fcxx-exceptions -pedantic-errors | llvm-cxxfilt -n | FileCheck %s --check-prefixes CHECK +// We aren't testing this since C++26 because of P2748R5 "Disallow Binding a Returned Glvalue to a Temporary". #if __cplusplus == 199711L #define NOTHROW throw() diff --git a/clang/test/CXX/stmt.stmt/stmt.return/p6.cpp b/clang/test/CXX/stmt.stmt/stmt.return/p6.cpp new file mode 100644 index 000000000000..c192b0c8112a --- /dev/null +++ b/clang/test/CXX/stmt.stmt/stmt.return/p6.cpp @@ -0,0 +1,25 @@ +// RUN: %clang_cc1 -std=c++26 -fsyntax-only -verify %s + +auto&& f1() { + return 42; // expected-error{{returning reference to local temporary object}} +} +const double& f2() { + static int x = 42; + return x; // expected-error{{returning reference to local temporary object}} +} +auto&& id(auto&& r) { + return static_cast(r); +} +auto&& f3() { + return id(42); // OK, but probably a bug +} + +void unevaluated() { + using a = decltype ([] () -> const int & { + const int &i = 0; // expected-note {{binding reference variable 'i' here}} + return i; // expected-error{{returning reference to local temporary object}} +} ()); +} + +static_assert(__is_convertible(int, const int &)); +static_assert(__is_nothrow_convertible(int, const int &)); diff --git a/clang/test/SemaCXX/type-traits.cpp b/clang/test/SemaCXX/type-traits.cpp index dee4a29bd2bf..01991887b284 100644 --- a/clang/test/SemaCXX/type-traits.cpp +++ b/clang/test/SemaCXX/type-traits.cpp @@ -2509,6 +2509,20 @@ void is_convertible() static_assert(__is_convertible(FloatWrapper, IntWrapper)); static_assert(__is_convertible(FloatWrapper, float)); static_assert(__is_convertible(float, FloatWrapper)); + static_assert(__is_convertible(IntWrapper, IntWrapper&&)); + static_assert(__is_convertible(IntWrapper, const IntWrapper&)); + static_assert(__is_convertible(IntWrapper, int&&)); + static_assert(__is_convertible(IntWrapper, const int&)); + static_assert(__is_convertible(int, IntWrapper&&)); + static_assert(__is_convertible(int, const IntWrapper&)); + static_assert(__is_convertible(IntWrapper, FloatWrapper&&)); + static_assert(__is_convertible(IntWrapper, const FloatWrapper&)); + static_assert(__is_convertible(FloatWrapper, IntWrapper&&)); + static_assert(__is_convertible(FloatWrapper, const IntWrapper&&)); + static_assert(__is_convertible(FloatWrapper, float&&)); + static_assert(__is_convertible(FloatWrapper, const float&)); + static_assert(__is_convertible(float, FloatWrapper&&)); + static_assert(__is_convertible(float, const FloatWrapper&)); } void is_nothrow_convertible() @@ -2521,6 +2535,20 @@ void is_nothrow_convertible() static_assert(!__is_nothrow_convertible(FloatWrapper, IntWrapper)); static_assert(!__is_nothrow_convertible(FloatWrapper, float)); static_assert(__is_nothrow_convertible(float, FloatWrapper)); + static_assert(__is_nothrow_convertible(IntWrapper, IntWrapper&&)); + static_assert(__is_nothrow_convertible(IntWrapper, const IntWrapper&)); + static_assert(__is_nothrow_convertible(IntWrapper, int&&)); + static_assert(__is_nothrow_convertible(IntWrapper, const int&)); + static_assert(!__is_nothrow_convertible(int, IntWrapper&&)); + static_assert(!__is_nothrow_convertible(int, const IntWrapper&)); + static_assert(!__is_nothrow_convertible(IntWrapper, FloatWrapper&&)); + static_assert(!__is_nothrow_convertible(IntWrapper, const FloatWrapper&)); + static_assert(!__is_nothrow_convertible(FloatWrapper, IntWrapper&&)); + static_assert(!__is_nothrow_convertible(FloatWrapper, const IntWrapper&)); + static_assert(!__is_nothrow_convertible(FloatWrapper, float&&)); + static_assert(!__is_nothrow_convertible(FloatWrapper, const float&)); + static_assert(__is_nothrow_convertible(float, FloatWrapper&&)); + static_assert(__is_nothrow_convertible(float, const FloatWrapper&)); } struct FromInt { FromInt(int); }; diff --git a/clang/www/cxx_status.html b/clang/www/cxx_status.html index 0d796597d05c..d58c35b72c22 100755 --- a/clang/www/cxx_status.html +++ b/clang/www/cxx_status.html @@ -167,7 +167,7 @@ C++23, informally referred to as C++26.

Disallow Binding a Returned Glvalue to a Temporary P2748R5 - No + Clang 19 Clarifying rules for brace elision in aggregate initialization -- GitLab From c4c8d08b81e622529aaf0bfc3020d2b9e87267b3 Mon Sep 17 00:00:00 2001 From: yronglin Date: Mon, 29 Apr 2024 22:00:41 +0800 Subject: [PATCH 229/301] [Clang] Fix incorrect handling of #pragma {GCC} unroll N in dependent context (#90240) PR https://github.com/llvm/llvm-project/pull/89567 fix the `#pragma unroll N` crash issue in dependent context, but it's introduce an new issue: Since https://github.com/llvm/llvm-project/pull/89567, if `N` is value dependent, 'option' and 'state' were ` (LoopHintAttr::Unroll, LoopHintAttr::Enable)`. Therefor, clang's code generator generated incorrect IR metadata. For the situation `#pragma {GCC} unroll {0|1}`, before template instantiation, this PR tweak the 'option' to `LoopHintAttr::UnrollCount` and 'state' to `LoopHintAttr::Numeric`. During template instantiation and if unroll count is 0 or 1 this PR tweak 'option' to `LoopHintAttr::Unroll` and 'state' to `LoopHintAttr::Disable`. We don't use `LoopHintAttr::UnrollCount` here because it's will emit an redundant LLVM IR metadata `!{!"llvm.loop.unroll.count", i32 1}` when unroll count is 1. --------- Signed-off-by: yronglin --- clang/lib/CodeGen/CGLoopInfo.cpp | 2 - clang/lib/Sema/SemaStmtAttr.cpp | 18 ++++--- clang/lib/Sema/SemaTemplateInstantiate.cpp | 18 +++++-- clang/test/AST/ast-dump-pragma-unroll.cpp | 31 ++++++++++++ clang/test/CodeGenCXX/pragma-gcc-unroll.cpp | 30 ++++++++++++ clang/test/CodeGenCXX/pragma-unroll.cpp | 52 +++++++++++++++++++++ clang/test/Parser/pragma-unroll.cpp | 29 ++++++++++++ 7 files changed, 165 insertions(+), 15 deletions(-) create mode 100644 clang/test/AST/ast-dump-pragma-unroll.cpp diff --git a/clang/lib/CodeGen/CGLoopInfo.cpp b/clang/lib/CodeGen/CGLoopInfo.cpp index 72d1471021ac..0d4800b90a2f 100644 --- a/clang/lib/CodeGen/CGLoopInfo.cpp +++ b/clang/lib/CodeGen/CGLoopInfo.cpp @@ -673,8 +673,6 @@ void LoopInfoStack::push(BasicBlock *Header, clang::ASTContext &Ctx, setPipelineDisabled(true); break; case LoopHintAttr::UnrollCount: - setUnrollState(LoopAttributes::Disable); - break; case LoopHintAttr::UnrollAndJamCount: case LoopHintAttr::VectorizeWidth: case LoopHintAttr::InterleaveCount: diff --git a/clang/lib/Sema/SemaStmtAttr.cpp b/clang/lib/Sema/SemaStmtAttr.cpp index 9d44c22c8ddc..1c84830b6ddd 100644 --- a/clang/lib/Sema/SemaStmtAttr.cpp +++ b/clang/lib/Sema/SemaStmtAttr.cpp @@ -109,16 +109,14 @@ static Attr *handleLoopHintAttr(Sema &S, Stmt *St, const ParsedAttr &A, SetHints(LoopHintAttr::Unroll, LoopHintAttr::Disable); } else if (PragmaName == "unroll") { // #pragma unroll N - if (ValueExpr && !ValueExpr->isValueDependent()) { - llvm::APSInt ValueAPS; - ExprResult R = S.VerifyIntegerConstantExpression(ValueExpr, &ValueAPS); - assert(!R.isInvalid() && "unroll count value must be a valid value, it's " - "should be checked in Sema::CheckLoopHintExpr"); - (void)R; - // The values of 0 and 1 block any unrolling of the loop. - if (ValueAPS.isZero() || ValueAPS.isOne()) - SetHints(LoopHintAttr::UnrollCount, LoopHintAttr::Disable); - else + if (ValueExpr) { + if (!ValueExpr->isValueDependent()) { + auto Value = ValueExpr->EvaluateKnownConstInt(S.getASTContext()); + if (Value.isZero() || Value.isOne()) + SetHints(LoopHintAttr::Unroll, LoopHintAttr::Disable); + else + SetHints(LoopHintAttr::UnrollCount, LoopHintAttr::Numeric); + } else SetHints(LoopHintAttr::UnrollCount, LoopHintAttr::Numeric); } else SetHints(LoopHintAttr::Unroll, LoopHintAttr::Enable); diff --git a/clang/lib/Sema/SemaTemplateInstantiate.cpp b/clang/lib/Sema/SemaTemplateInstantiate.cpp index 98d5c7cb3a8a..3a9fd906b7af 100644 --- a/clang/lib/Sema/SemaTemplateInstantiate.cpp +++ b/clang/lib/Sema/SemaTemplateInstantiate.cpp @@ -2151,13 +2151,25 @@ TemplateInstantiator::TransformLoopHintAttr(const LoopHintAttr *LH) { // Generate error if there is a problem with the value. if (getSema().CheckLoopHintExpr(TransformedExpr, LH->getLocation(), - LH->getOption() == LoopHintAttr::UnrollCount)) + LH->getSemanticSpelling() == + LoopHintAttr::Pragma_unroll)) return LH; + LoopHintAttr::OptionType Option = LH->getOption(); + LoopHintAttr::LoopHintState State = LH->getState(); + + llvm::APSInt ValueAPS = + TransformedExpr->EvaluateKnownConstInt(getSema().getASTContext()); + // The values of 0 and 1 block any unrolling of the loop. + if (ValueAPS.isZero() || ValueAPS.isOne()) { + Option = LoopHintAttr::Unroll; + State = LoopHintAttr::Disable; + } + // Create new LoopHintValueAttr with integral expression in place of the // non-type template parameter. - return LoopHintAttr::CreateImplicit(getSema().Context, LH->getOption(), - LH->getState(), TransformedExpr, *LH); + return LoopHintAttr::CreateImplicit(getSema().Context, Option, State, + TransformedExpr, *LH); } const NoInlineAttr *TemplateInstantiator::TransformStmtNoInlineAttr( const Stmt *OrigS, const Stmt *InstS, const NoInlineAttr *A) { diff --git a/clang/test/AST/ast-dump-pragma-unroll.cpp b/clang/test/AST/ast-dump-pragma-unroll.cpp new file mode 100644 index 000000000000..f9c254b803ff --- /dev/null +++ b/clang/test/AST/ast-dump-pragma-unroll.cpp @@ -0,0 +1,31 @@ +// RUN: %clang_cc1 -triple x86_64-unknown-unknown -ast-dump %s | FileCheck %s + +using size_t = unsigned long long; + +// CHECK: LoopHintAttr {{.*}} Implicit unroll UnrollCount Numeric +// CHECK: LoopHintAttr {{.*}} Implicit unroll UnrollCount Numeric +// CHECK: LoopHintAttr {{.*}} Implicit unroll Unroll Disable +// CHECK: LoopHintAttr {{.*}} Implicit unroll Unroll Disable +template +int value_dependent(int n) { + constexpr int N = 100; + auto init = [=]() { return Flag ? n : 0UL; }; + auto cond = [=](size_t ix) { return Flag ? ix != 0 : ix < 10; }; + auto iter = [=](size_t ix) { + return Flag ? ix & ~(1ULL << __builtin_clzll(ix)) : ix + 1; + }; + +#pragma unroll Flag ? 1 : N + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + n *= n; + } +#pragma unroll Flag ? 0 : N + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + n *= n; + } + return n; +} + +void test_value_dependent(int n) { + value_dependent(n); +} diff --git a/clang/test/CodeGenCXX/pragma-gcc-unroll.cpp b/clang/test/CodeGenCXX/pragma-gcc-unroll.cpp index 8a94a5cc91e2..85f10fcdff14 100644 --- a/clang/test/CodeGenCXX/pragma-gcc-unroll.cpp +++ b/clang/test/CodeGenCXX/pragma-gcc-unroll.cpp @@ -116,6 +116,34 @@ void while_unroll_zero_test(int *List, int Length) { } } +using size_t = unsigned long long; + +template +int value_dependent(int n) { + // CHECK: define {{.*}} @_Z15value_dependentILb1EEii + constexpr int N = 100; + auto init = [=]() { return Flag ? n : 0UL; }; + auto cond = [=](size_t ix) { return Flag ? ix != 0 : ix < 10; }; + auto iter = [=](size_t ix) { + return Flag ? ix & ~(1ULL << __builtin_clzll(ix)) : ix + 1; + }; +#pragma GCC unroll Flag ? 1 : N + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + // CHECK: br label {{.*}}, !llvm.loop ![[LOOP_16:.*]] + n *= n; + } +#pragma GCC unroll Flag ? 0 : N + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + // CHECK: br label {{.*}}, !llvm.loop ![[LOOP_17:.*]] + n *= n; + } + return n; +} + +void test_value_dependent(int n) { + value_dependent(n); +} + // CHECK: ![[LOOP_1]] = distinct !{![[LOOP_1]], [[MP:![0-9]+]], ![[UNROLL_ENABLE:.*]]} // CHECK: ![[UNROLL_ENABLE]] = !{!"llvm.loop.unroll.enable"} // CHECK: ![[LOOP_2]] = distinct !{![[LOOP_2:.*]], ![[UNROLL_DISABLE:.*]]} @@ -129,3 +157,5 @@ void while_unroll_zero_test(int *List, int Length) { // CHECK: ![[LOOP_7]] = distinct !{![[LOOP_7]], ![[UNROLL_8:.*]]} // CHECK: ![[LOOP_14]] = distinct !{![[LOOP_14]], [[MP]], ![[UNROLL_DISABLE:.*]]} // CHECK: ![[LOOP_15]] = distinct !{![[LOOP_15]], [[MP]], ![[UNROLL_DISABLE:.*]]} +// CHECK: ![[LOOP_16]] = distinct !{![[LOOP_16]], [[MP]], ![[UNROLL_DISABLE:.*]]} +// CHECK: ![[LOOP_17]] = distinct !{![[LOOP_17]], [[MP]], ![[UNROLL_DISABLE:.*]]} diff --git a/clang/test/CodeGenCXX/pragma-unroll.cpp b/clang/test/CodeGenCXX/pragma-unroll.cpp index 02d9bad7148d..6754788b7243 100644 --- a/clang/test/CodeGenCXX/pragma-unroll.cpp +++ b/clang/test/CodeGenCXX/pragma-unroll.cpp @@ -96,6 +96,54 @@ void template_test(double *List, int Length) { for_template_define_test(List, Length, Value); } +void for_unroll_zero_test(int *List, int Length) { + // CHECK: define {{.*}} @_Z20for_unroll_zero_testPii + #pragma unroll 0 + for (int i = 0; i < Length; i++) { + // CHECK: br label {{.*}}, !llvm.loop ![[LOOP_14:.*]] + List[i] = i * 2; + } +} + +void while_unroll_zero_test(int *List, int Length) { + // CHECK: define {{.*}} @_Z22while_unroll_zero_testPii + int i = 0; +#pragma unroll(0) + while (i < Length) { + // CHECK: br label {{.*}}, !llvm.loop ![[LOOP_15:.*]] + List[i] = i * 2; + i++; + } +} + +using size_t = unsigned long long; + +template +int value_dependent(int n) { + // CHECK: define {{.*}} @_Z15value_dependentILb1EEii + constexpr int N = 100; + auto init = [=]() { return Flag ? n : 0UL; }; + auto cond = [=](size_t ix) { return Flag ? ix != 0 : ix < 10; }; + auto iter = [=](size_t ix) { + return Flag ? ix & ~(1ULL << __builtin_clzll(ix)) : ix + 1; + }; +#pragma unroll Flag ? 1 : N + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + // CHECK: br label {{.*}}, !llvm.loop ![[LOOP_16:.*]] + n *= n; + } +#pragma unroll Flag ? 0 : N + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + // CHECK: br label {{.*}}, !llvm.loop ![[LOOP_17:.*]] + n *= n; + } + return n; +} + +void test_value_dependent(int n) { + value_dependent(n); +} + // CHECK: ![[LOOP_1]] = distinct !{![[LOOP_1]], [[MP:![0-9]+]], ![[UNROLL_ENABLE:.*]]} // CHECK: ![[UNROLL_ENABLE]] = !{!"llvm.loop.unroll.enable"} // CHECK: ![[LOOP_2]] = distinct !{![[LOOP_2:.*]], ![[UNROLL_DISABLE:.*]]} @@ -107,3 +155,7 @@ void template_test(double *List, int Length) { // CHECK: ![[LOOP_5]] = distinct !{![[LOOP_5]], ![[UNROLL_8:.*]]} // CHECK: ![[LOOP_6]] = distinct !{![[LOOP_6]], ![[UNROLL_8:.*]]} // CHECK: ![[LOOP_7]] = distinct !{![[LOOP_7]], ![[UNROLL_8:.*]]} +// CHECK: ![[LOOP_14]] = distinct !{![[LOOP_14]], [[MP]], ![[UNROLL_DISABLE:.*]]} +// CHECK: ![[LOOP_15]] = distinct !{![[LOOP_15]], [[MP]], ![[UNROLL_DISABLE:.*]]} +// CHECK: ![[LOOP_16]] = distinct !{![[LOOP_16]], [[MP]], ![[UNROLL_DISABLE:.*]]} +// CHECK: ![[LOOP_17]] = distinct !{![[LOOP_17]], [[MP]], ![[UNROLL_DISABLE:.*]]} diff --git a/clang/test/Parser/pragma-unroll.cpp b/clang/test/Parser/pragma-unroll.cpp index f41bd7a18d5a..19066acddcef 100644 --- a/clang/test/Parser/pragma-unroll.cpp +++ b/clang/test/Parser/pragma-unroll.cpp @@ -124,3 +124,32 @@ void test(int *List, int Length) { #pragma unroll /* expected-error {{expected statement}} */ } + +using size_t = unsigned long long; + +template +int FailToBuild(int n) { + constexpr int N = 100; + auto init = [=]() { return Flag ? n : 0UL; }; + auto cond = [=](size_t ix) { return Flag ? ix != 0 : ix < 10; }; + auto iter = [=](size_t ix) { + return Flag ? ix & ~(1ULL << __builtin_clzll(ix)) : ix + 1; + }; +#pragma unroll Flag ? 0 : N // Ok, allow 0. + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + n *= n; + } +#pragma GCC unroll Flag ? 0 : N // Ok, allow 0. + for (size_t ix = init(); cond(ix); ix = iter(ix)) { + n *= n; + } + return n; +} + +int foo(int n) { + return FailToBuild(n); +} + +int bar(int n) { + return FailToBuild(n); +} -- GitLab From 6561fa3d02b746743139212f31f24c4a81e5138c Mon Sep 17 00:00:00 2001 From: Matthew Devereau Date: Mon, 29 Apr 2024 15:17:48 +0100 Subject: [PATCH 230/301] [LoopUnswitch] Allow i1 truncs in loop unswitch (#89738) With the addition of #84628, truncs to i1 are being emitted as conditions to branch instructions. This caused significant regressions in cases which were previously improved by loop unswitch. Adding truncs to i1 restore the previous performance seen. --- llvm/lib/Transforms/Utils/LoopUtils.cpp | 6 +- .../SimpleLoopUnswitch/endless-unswitch.ll | 93 +++++++++++++ .../SimpleLoopUnswitch/partial-unswitch.ll | 130 ++++++++++++++++++ 3 files changed, 227 insertions(+), 2 deletions(-) diff --git a/llvm/lib/Transforms/Utils/LoopUtils.cpp b/llvm/lib/Transforms/Utils/LoopUtils.cpp index 73c5d6367822..e3e09d11ba8c 100644 --- a/llvm/lib/Transforms/Utils/LoopUtils.cpp +++ b/llvm/lib/Transforms/Utils/LoopUtils.cpp @@ -1930,10 +1930,12 @@ llvm::hasPartialIVCondition(const Loop &L, unsigned MSSAThreshold, if (!TI || !TI->isConditional()) return {}; - auto *CondI = dyn_cast(TI->getCondition()); + auto *CondI = dyn_cast(TI->getCondition()); // The case with the condition outside the loop should already be handled // earlier. - if (!CondI || !L.contains(CondI)) + // Allow CmpInst and TruncInsts as they may be users of load instructions + // and have potential for partial unswitching + if (!CondI || !isa(CondI) || !L.contains(CondI)) return {}; SmallVector InstToDuplicate; diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/endless-unswitch.ll b/llvm/test/Transforms/SimpleLoopUnswitch/endless-unswitch.ll index 0d3aa8b24310..e70bea2d2f7a 100644 --- a/llvm/test/Transforms/SimpleLoopUnswitch/endless-unswitch.ll +++ b/llvm/test/Transforms/SimpleLoopUnswitch/endless-unswitch.ll @@ -106,3 +106,96 @@ for.inc: ; preds = %for.cond5 store i8 0, ptr @b, align 1 br label %for.cond5 } + +define void @e(ptr %p) { +; CHECK-LABEL: @e( +; CHECK-NEXT: entry: +; CHECK-NEXT: br label [[FOR_COND:%.*]] +; CHECK: for.cond: +; CHECK-NEXT: br i1 false, label [[FOR_END:%.*]], label [[FOR_COND]] +; CHECK: for.end: +; CHECK-NEXT: [[TMP0:%.*]] = load i16, ptr [[P:%.*]], align 2 +; CHECK-NEXT: [[TMP1:%.*]] = trunc i16 [[TMP0]] to i1 +; CHECK-NEXT: br i1 [[TMP1]], label [[FOR_END_SPLIT:%.*]], label [[FOR_END_SPLIT_US:%.*]] +; CHECK: for.end.split.us: +; CHECK-NEXT: br label [[G_US:%.*]] +; CHECK: g.us: +; CHECK-NEXT: br label [[G_SPLIT_US6:%.*]] +; CHECK: for.cond1.us1: +; CHECK-NEXT: [[TMP2:%.*]] = load i16, ptr [[P]], align 2 +; CHECK-NEXT: [[TOBOOL4_NOT_US:%.*]] = trunc i16 [[TMP2]] to i1 +; CHECK-NEXT: br i1 [[TOBOOL4_NOT_US]], label [[FOR_COND5_PREHEADER_US4:%.*]], label [[G_LOOPEXIT_US:%.*]] +; CHECK: for.cond5.us2: +; CHECK-NEXT: br i1 false, label [[FOR_COND1_LOOPEXIT_US5:%.*]], label [[FOR_INC_US3:%.*]] +; CHECK: for.inc.us3: +; CHECK-NEXT: store i8 0, ptr @b, align 1 +; CHECK-NEXT: br label [[FOR_COND5_US2:%.*]] +; CHECK: for.cond5.preheader.us4: +; CHECK-NEXT: br label [[FOR_COND5_US2]] +; CHECK: for.cond1.loopexit.us5: +; CHECK-NEXT: br label [[FOR_COND1_US1:%.*]], !llvm.loop [[LOOP3:![0-9]+]] +; CHECK: g.loopexit.us: +; CHECK-NEXT: br label [[G_US]] +; CHECK: g.split.us6: +; CHECK-NEXT: br label [[FOR_COND1_US1]] +; CHECK: for.end.split: +; CHECK-NEXT: br label [[G:%.*]] +; CHECK: g.loopexit: +; CHECK-NEXT: br label [[G]], !llvm.loop [[LOOP4:![0-9]+]] +; CHECK: g: +; CHECK-NEXT: [[TMP3:%.*]] = load i16, ptr [[P]], align 2 +; CHECK-NEXT: [[TMP4:%.*]] = trunc i16 [[TMP3]] to i1 +; CHECK-NEXT: br i1 [[TMP4]], label [[G_SPLIT_US:%.*]], label [[G_SPLIT:%.*]] +; CHECK: g.split.us: +; CHECK-NEXT: br label [[FOR_COND1_US:%.*]] +; CHECK: for.cond1.us: +; CHECK-NEXT: br label [[FOR_COND5_PREHEADER_US:%.*]] +; CHECK: for.cond5.us: +; CHECK-NEXT: br i1 false, label [[FOR_COND1_LOOPEXIT_US:%.*]], label [[FOR_INC_US:%.*]] +; CHECK: for.inc.us: +; CHECK-NEXT: store i8 0, ptr @b, align 1 +; CHECK-NEXT: br label [[FOR_COND5_US:%.*]] +; CHECK: for.cond5.preheader.us: +; CHECK-NEXT: br label [[FOR_COND5_US]] +; CHECK: for.cond1.loopexit.us: +; CHECK-NEXT: br label [[FOR_COND1_US]] +; CHECK: g.split: +; CHECK-NEXT: br label [[FOR_COND1:%.*]] +; CHECK: for.cond1.loopexit: +; CHECK-NEXT: br label [[FOR_COND1]], !llvm.loop [[LOOP3]] +; CHECK: for.cond1: +; CHECK-NEXT: [[TMP5:%.*]] = load i16, ptr [[P]], align 2 +; CHECK-NEXT: [[TOBOOL4_NOT:%.*]] = trunc i16 [[TMP5]] to i1 +; CHECK-NEXT: br i1 [[TOBOOL4_NOT]], label [[FOR_COND5_PREHEADER:%.*]], label [[G_LOOPEXIT:%.*]] +; CHECK: for.cond5.preheader: +; CHECK-NEXT: br label [[FOR_COND5:%.*]] +; CHECK: for.cond5: +; CHECK-NEXT: br i1 false, label [[FOR_COND1_LOOPEXIT:%.*]], label [[FOR_INC:%.*]] +; CHECK: for.inc: +; CHECK-NEXT: store i8 0, ptr @b, align 1 +; CHECK-NEXT: br label [[FOR_COND5]] +; +entry: + br label %for.cond + +for.cond: ; preds = %for.cond, %entry + br i1 false, label %for.end, label %for.cond + +for.end: ; preds = %for.cond + br label %g + +g: ; preds = %for.cond1, %for.end + br label %for.cond1 + +for.cond1: ; preds = %for.cond5, %g + %0 = load i16, ptr %p, align 2 + %tobool4.not = trunc i16 %0 to i1 + br i1 %tobool4.not, label %for.cond5, label %g + +for.cond5: ; preds = %for.inc, %for.cond1 + br i1 false, label %for.cond1, label %for.inc + +for.inc: ; preds = %for.cond5 + store i8 0, ptr @b, align 1 + br label %for.cond5 +} diff --git a/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll b/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll index f97e5c3eec9d..1d8942079ffd 100644 --- a/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll +++ b/llvm/test/Transforms/SimpleLoopUnswitch/partial-unswitch.ll @@ -1326,6 +1326,136 @@ exit: ret i32 10 } +define i32 @partial_unswitch_true_successor_trunc(ptr %ptr, i32 %N) { +; CHECK-LABEL: @partial_unswitch_true_successor_trunc( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1 +; CHECK-NEXT: br i1 [[TMP1]], label [[ENTRY_SPLIT_US:%.*]], label [[ENTRY_SPLIT:%.*]] +; CHECK: entry.split.us: +; CHECK-NEXT: br label [[LOOP_HEADER_US:%.*]] +; CHECK: loop.header.us: +; CHECK-NEXT: [[IV_US:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT_US]] ], [ [[IV_NEXT_US:%.*]], [[LOOP_LATCH_US:%.*]] ] +; CHECK-NEXT: br label [[NOCLOBBER_US:%.*]] +; CHECK: noclobber.us: +; CHECK-NEXT: br label [[LOOP_LATCH_US]] +; CHECK: loop.latch.us: +; CHECK-NEXT: [[C_US:%.*]] = icmp ult i32 [[IV_US]], [[N:%.*]] +; CHECK-NEXT: [[IV_NEXT_US]] = add i32 [[IV_US]], 1 +; CHECK-NEXT: br i1 [[C_US]], label [[LOOP_HEADER_US]], label [[EXIT_SPLIT_US:%.*]] +; CHECK: exit.split.us: +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: entry.split: +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] +; CHECK: loop.header: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4 +; CHECK-NEXT: [[SC:%.*]] = trunc i32 [[LV]] to i1 +; CHECK-NEXT: br i1 [[SC]], label [[NOCLOBBER:%.*]], label [[CLOBBER:%.*]] +; CHECK: noclobber: +; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK: clobber: +; CHECK-NEXT: call void @clobber() +; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK: loop.latch: +; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]] +; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 +; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP12:![0-9]+]] +; CHECK: exit.split: +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: ret i32 10 +; +entry: + br label %loop.header + +loop.header: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ] + %lv = load i32, ptr %ptr + %sc = trunc i32 %lv to i1 + br i1 %sc, label %noclobber, label %clobber + +noclobber: + br label %loop.latch + +clobber: + call void @clobber() + br label %loop.latch + +loop.latch: + %c = icmp ult i32 %iv, %N + %iv.next = add i32 %iv, 1 + br i1 %c, label %loop.header, label %exit + +exit: + ret i32 10 +} + +define i32 @partial_unswitch_false_successor_trunc(ptr %ptr, i32 %N) { +; CHECK-LABEL: @partial_unswitch_false_successor_trunc( +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[PTR:%.*]], align 4 +; CHECK-NEXT: [[TMP1:%.*]] = trunc i32 [[TMP0]] to i1 +; CHECK-NEXT: br i1 [[TMP1]], label [[ENTRY_SPLIT:%.*]], label [[ENTRY_SPLIT_US:%.*]] +; CHECK: entry.split.us: +; CHECK-NEXT: br label [[LOOP_HEADER_US:%.*]] +; CHECK: loop.header.us: +; CHECK-NEXT: [[IV_US:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT_US]] ], [ [[IV_NEXT_US:%.*]], [[LOOP_LATCH_US:%.*]] ] +; CHECK-NEXT: br label [[NOCLOBBER_US:%.*]] +; CHECK: noclobber.us: +; CHECK-NEXT: br label [[LOOP_LATCH_US]] +; CHECK: loop.latch.us: +; CHECK-NEXT: [[C_US:%.*]] = icmp ult i32 [[IV_US]], [[N:%.*]] +; CHECK-NEXT: [[IV_NEXT_US]] = add i32 [[IV_US]], 1 +; CHECK-NEXT: br i1 [[C_US]], label [[LOOP_HEADER_US]], label [[EXIT_SPLIT_US:%.*]] +; CHECK: exit.split.us: +; CHECK-NEXT: br label [[EXIT:%.*]] +; CHECK: entry.split: +; CHECK-NEXT: br label [[LOOP_HEADER:%.*]] +; CHECK: loop.header: +; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, [[ENTRY_SPLIT]] ], [ [[IV_NEXT:%.*]], [[LOOP_LATCH:%.*]] ] +; CHECK-NEXT: [[LV:%.*]] = load i32, ptr [[PTR]], align 4 +; CHECK-NEXT: [[SC:%.*]] = trunc i32 [[LV]] to i1 +; CHECK-NEXT: br i1 [[SC]], label [[CLOBBER:%.*]], label [[NOCLOBBER:%.*]] +; CHECK: clobber: +; CHECK-NEXT: call void @clobber() +; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK: noclobber: +; CHECK-NEXT: br label [[LOOP_LATCH]] +; CHECK: loop.latch: +; CHECK-NEXT: [[C:%.*]] = icmp ult i32 [[IV]], [[N]] +; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1 +; CHECK-NEXT: br i1 [[C]], label [[LOOP_HEADER]], label [[EXIT_SPLIT:%.*]], !llvm.loop [[LOOP13:![0-9]+]] +; CHECK: exit.split: +; CHECK-NEXT: br label [[EXIT]] +; CHECK: exit: +; CHECK-NEXT: ret i32 10 +; +entry: + br label %loop.header + +loop.header: + %iv = phi i32 [ 0, %entry ], [ %iv.next, %loop.latch ] + %lv = load i32, ptr %ptr + %sc = trunc i32 %lv to i1 + br i1 %sc, label %clobber, label %noclobber + +clobber: + call void @clobber() + br label %loop.latch + +noclobber: + br label %loop.latch + +loop.latch: + %c = icmp ult i32 %iv, %N + %iv.next = add i32 %iv, 1 + br i1 %c, label %loop.header, label %exit + +exit: + ret i32 10 +} + ; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[UNSWITCH_PARTIAL_DISABLE:![0-9]+]]} ; CHECK: [[UNSWITCH_PARTIAL_DISABLE]] = !{!"llvm.loop.unswitch.partial.disable"} ; CHECK: [[LOOP2]] = distinct !{[[LOOP2]], [[UNSWITCH_PARTIAL_DISABLE]]} -- GitLab From bb770deb9acf554a17ad49c0b3af9b8cf83ec221 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 29 Apr 2024 15:38:56 +0200 Subject: [PATCH 231/301] [clang][Interp] Reject void-typed InitListExprs --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 3 +++ clang/test/AST/Interp/functions.cpp | 6 ++++++ 2 files changed, 9 insertions(+) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 568a929c6a16..0a93a6a198a9 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -1114,6 +1114,9 @@ bool ByteCodeExprGen::visitArrayElemInit(unsigned ElemIndex, template bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { + if (E->getType()->isVoidType()) + return this->emitInvalid(E); + // Handle discarding first. if (DiscardResult) { for (const Expr *Init : E->inits()) { diff --git a/clang/test/AST/Interp/functions.cpp b/clang/test/AST/Interp/functions.cpp index a4ae73e423e7..a5bb9f1a19aa 100644 --- a/clang/test/AST/Interp/functions.cpp +++ b/clang/test/AST/Interp/functions.cpp @@ -611,3 +611,9 @@ namespace { static_assert((g(), true), ""); } + +namespace { + /// The InitListExpr here is of void type. + void bir [[clang::annotate("B", {1, 2, 3, 4})]] (); // both-error {{'annotate' attribute requires parameter 1 to be a constant expression}} \ + // both-note {{subexpression not valid in a constant expression}} +} -- GitLab From e34b41c707a8cc589725d5f996e1a40e9631a495 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 29 Apr 2024 16:17:23 +0200 Subject: [PATCH 232/301] [clang][Interp] Support CXXParenListInitExprs for non-record types Merge the non-record code paths into visitInitList(). --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 210 +++++++++++------------ clang/lib/AST/Interp/ByteCodeExprGen.h | 3 +- clang/test/AST/Interp/records.cpp | 6 + 3 files changed, 109 insertions(+), 110 deletions(-) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 0a93a6a198a9..accaea0a8442 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -1023,125 +1023,98 @@ bool ByteCodeExprGen::VisitArraySubscriptExpr( template bool ByteCodeExprGen::visitInitList(ArrayRef Inits, + const Expr *ArrayFiller, const Expr *E) { - assert(E->getType()->isRecordType()); - const Record *R = getRecord(E->getType()); + if (E->getType()->isVoidType()) + return this->emitInvalid(E); - if (Inits.size() == 1 && E->getType() == Inits[0]->getType()) { - return this->visitInitializer(Inits[0]); + // Handle discarding first. + if (DiscardResult) { + for (const Expr *Init : Inits) { + if (!this->discard(Init)) + return false; + } + return true; } - unsigned InitIndex = 0; - for (const Expr *Init : Inits) { - // Skip unnamed bitfields. - while (InitIndex < R->getNumFields() && - R->getField(InitIndex)->Decl->isUnnamedBitField()) - ++InitIndex; + // Primitive values. + if (std::optional T = classify(E->getType())) { + assert(!DiscardResult); + if (Inits.size() == 0) + return this->visitZeroInitializer(*T, E->getType(), E); + assert(Inits.size() == 1); + return this->delegate(Inits[0]); + } - if (!this->emitDupPtr(E)) - return false; + QualType T = E->getType(); + if (T->isRecordType()) { + const Record *R = getRecord(E->getType()); - if (std::optional T = classify(Init)) { - const Record::Field *FieldToInit = R->getField(InitIndex); - if (!this->visit(Init)) - return false; + if (Inits.size() == 1 && E->getType() == Inits[0]->getType()) { + return this->visitInitializer(Inits[0]); + } - if (FieldToInit->isBitField()) { - if (!this->emitInitBitField(*T, FieldToInit, E)) - return false; - } else { - if (!this->emitInitField(*T, FieldToInit->Offset, E)) - return false; - } + unsigned InitIndex = 0; + for (const Expr *Init : Inits) { + // Skip unnamed bitfields. + while (InitIndex < R->getNumFields() && + R->getField(InitIndex)->Decl->isUnnamedBitField()) + ++InitIndex; - if (!this->emitPopPtr(E)) + if (!this->emitDupPtr(E)) return false; - ++InitIndex; - } else { - // Initializer for a direct base class. - if (const Record::Base *B = R->getBase(Init->getType())) { - if (!this->emitGetPtrBasePop(B->Offset, Init)) - return false; - - if (!this->visitInitializer(Init)) - return false; - if (!this->emitFinishInitPop(E)) - return false; - // Base initializers don't increase InitIndex, since they don't count - // into the Record's fields. - } else { + if (std::optional T = classify(Init)) { const Record::Field *FieldToInit = R->getField(InitIndex); - // Non-primitive case. Get a pointer to the field-to-initialize - // on the stack and recurse into visitInitializer(). - if (!this->emitGetPtrField(FieldToInit->Offset, Init)) + if (!this->visit(Init)) return false; - if (!this->visitInitializer(Init)) - return false; + if (FieldToInit->isBitField()) { + if (!this->emitInitBitField(*T, FieldToInit, E)) + return false; + } else { + if (!this->emitInitField(*T, FieldToInit->Offset, E)) + return false; + } if (!this->emitPopPtr(E)) return false; ++InitIndex; - } - } - } - return true; -} + } else { + // Initializer for a direct base class. + if (const Record::Base *B = R->getBase(Init->getType())) { + if (!this->emitGetPtrBasePop(B->Offset, Init)) + return false; -/// Pointer to the array(not the element!) must be on the stack when calling -/// this. -template -bool ByteCodeExprGen::visitArrayElemInit(unsigned ElemIndex, - const Expr *Init) { - if (std::optional T = classify(Init->getType())) { - // Visit the primitive element like normal. - if (!this->visit(Init)) - return false; - return this->emitInitElem(*T, ElemIndex, Init); - } + if (!this->visitInitializer(Init)) + return false; - // Advance the pointer currently on the stack to the given - // dimension. - if (!this->emitConstUint32(ElemIndex, Init)) - return false; - if (!this->emitArrayElemPtrUint32(Init)) - return false; - if (!this->visitInitializer(Init)) - return false; - return this->emitFinishInitPop(Init); -} + if (!this->emitFinishInitPop(E)) + return false; + // Base initializers don't increase InitIndex, since they don't count + // into the Record's fields. + } else { + const Record::Field *FieldToInit = R->getField(InitIndex); + // Non-primitive case. Get a pointer to the field-to-initialize + // on the stack and recurse into visitInitializer(). + if (!this->emitGetPtrField(FieldToInit->Offset, Init)) + return false; -template -bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { - if (E->getType()->isVoidType()) - return this->emitInvalid(E); + if (!this->visitInitializer(Init)) + return false; - // Handle discarding first. - if (DiscardResult) { - for (const Expr *Init : E->inits()) { - if (!this->discard(Init)) - return false; + if (!this->emitPopPtr(E)) + return false; + ++InitIndex; + } + } } return true; } - // Primitive values. - if (std::optional T = classify(E->getType())) { - assert(!DiscardResult); - if (E->getNumInits() == 0) - return this->visitZeroInitializer(*T, E->getType(), E); - assert(E->getNumInits() == 1); - return this->delegate(E->inits()[0]); - } - - QualType T = E->getType(); - if (T->isRecordType()) - return this->visitInitList(E->inits(), E); - if (T->isArrayType()) { unsigned ElementIndex = 0; - for (const Expr *Init : E->inits()) { + for (const Expr *Init : Inits) { if (!this->visitArrayElemInit(ElementIndex, Init)) return false; ++ElementIndex; @@ -1149,13 +1122,13 @@ bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { // Expand the filler expression. // FIXME: This should go away. - if (const Expr *Filler = E->getArrayFiller()) { + if (ArrayFiller) { const ConstantArrayType *CAT = Ctx.getASTContext().getAsConstantArrayType(E->getType()); uint64_t NumElems = CAT->getZExtSize(); for (; ElementIndex != NumElems; ++ElementIndex) { - if (!this->visitArrayElemInit(ElementIndex, Filler)) + if (!this->visitArrayElemInit(ElementIndex, ArrayFiller)) return false; } } @@ -1164,10 +1137,10 @@ bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { } if (const auto *ComplexTy = E->getType()->getAs()) { - unsigned NumInits = E->getNumInits(); + unsigned NumInits = Inits.size(); if (NumInits == 1) - return this->delegate(E->inits()[0]); + return this->delegate(Inits[0]); QualType ElemQT = ComplexTy->getElementType(); PrimType ElemT = classifyPrim(ElemQT); @@ -1181,7 +1154,7 @@ bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { } } else if (NumInits == 2) { unsigned InitIndex = 0; - for (const Expr *Init : E->inits()) { + for (const Expr *Init : Inits) { if (!this->visit(Init)) return false; @@ -1195,14 +1168,14 @@ bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { if (const auto *VecT = E->getType()->getAs()) { unsigned NumVecElements = VecT->getNumElements(); - assert(NumVecElements >= E->getNumInits()); + assert(NumVecElements >= Inits.size()); QualType ElemQT = VecT->getElementType(); PrimType ElemT = classifyPrim(ElemQT); // All initializer elements. unsigned InitIndex = 0; - for (const Expr *Init : E->inits()) { + for (const Expr *Init : Inits) { if (!this->visit(Init)) return false; @@ -1224,19 +1197,38 @@ bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { return false; } +/// Pointer to the array(not the element!) must be on the stack when calling +/// this. +template +bool ByteCodeExprGen::visitArrayElemInit(unsigned ElemIndex, + const Expr *Init) { + if (std::optional T = classify(Init->getType())) { + // Visit the primitive element like normal. + if (!this->visit(Init)) + return false; + return this->emitInitElem(*T, ElemIndex, Init); + } + + // Advance the pointer currently on the stack to the given + // dimension. + if (!this->emitConstUint32(ElemIndex, Init)) + return false; + if (!this->emitArrayElemPtrUint32(Init)) + return false; + if (!this->visitInitializer(Init)) + return false; + return this->emitFinishInitPop(Init); +} + +template +bool ByteCodeExprGen::VisitInitListExpr(const InitListExpr *E) { + return this->visitInitList(E->inits(), E->getArrayFiller(), E); +} + template bool ByteCodeExprGen::VisitCXXParenListInitExpr( const CXXParenListInitExpr *E) { - if (DiscardResult) { - for (const Expr *Init : E->getInitExprs()) { - if (!this->discard(Init)) - return false; - } - return true; - } - - assert(E->getType()->isRecordType()); - return this->visitInitList(E->getInitExprs(), E); + return this->visitInitList(E->getInitExprs(), E->getArrayFiller(), E); } template diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.h b/clang/lib/AST/Interp/ByteCodeExprGen.h index 2c3127968a1c..a89e37c67aa6 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.h +++ b/clang/lib/AST/Interp/ByteCodeExprGen.h @@ -225,7 +225,8 @@ protected: return this->emitFinishInitPop(I); } - bool visitInitList(ArrayRef Inits, const Expr *E); + bool visitInitList(ArrayRef Inits, const Expr *ArrayFiller, + const Expr *E); bool visitArrayElemInit(unsigned ElemIndex, const Expr *Init); /// Creates a local primitive value. diff --git a/clang/test/AST/Interp/records.cpp b/clang/test/AST/Interp/records.cpp index 866fa7240d2f..771e5adfca34 100644 --- a/clang/test/AST/Interp/records.cpp +++ b/clang/test/AST/Interp/records.cpp @@ -1030,6 +1030,12 @@ namespace ParenInit { // both-note {{required by 'constinit' specifier}} \ // both-note {{reference to temporary is not a constant expression}} \ // both-note {{temporary created here}} + + + /// Initializing an array. + constexpr void bar(int i, int j) { + int arr[4](i, j); + } } #endif -- GitLab From 45bd85e4815254a4528cc337447fd6a8eb6fd583 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 29 Apr 2024 16:29:38 +0200 Subject: [PATCH 233/301] [clang][Interp] Fix casting function pointers to integers --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 7 +++++++ clang/test/AST/Interp/c.c | 7 +++++++ 2 files changed, 14 insertions(+) diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index accaea0a8442..3ceccfdebfca 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -212,6 +212,13 @@ bool ByteCodeExprGen::VisitCastExpr(const CastExpr *CE) { if (!this->visit(SubExpr)) return false; + // If SubExpr doesn't result in a pointer, make it one. + if (PrimType FromT = classifyPrim(SubExpr->getType()); FromT != PT_Ptr) { + assert(isPtrType(FromT)); + if (!this->emitDecayPtr(FromT, PT_Ptr, CE)) + return false; + } + PrimType T = classifyPrim(CE->getType()); if (T == PT_IntAP) return this->emitCastPointerIntegralAP(Ctx.getBitWidth(CE->getType()), diff --git a/clang/test/AST/Interp/c.c b/clang/test/AST/Interp/c.c index a5951158ed0e..207da5fe8126 100644 --- a/clang/test/AST/Interp/c.c +++ b/clang/test/AST/Interp/c.c @@ -263,3 +263,10 @@ const int *p = &b; const __int128 K = (__int128)(int*)0; const unsigned __int128 KU = (unsigned __int128)(int*)0; #endif + + +int test3(void) { + int a[2]; + a[0] = test3; // all-error {{incompatible pointer to integer conversion assigning to 'int' from 'int (void)'}} + return 0; +} -- GitLab From 5e3032638e2df5f301dee21f072acc4d6cc806c8 Mon Sep 17 00:00:00 2001 From: Renato Golin Date: Mon, 29 Apr 2024 15:42:35 +0100 Subject: [PATCH 234/301] [MLIR][Linalg] Left over Linalg named ops from previous PR (#90405) Adding `erf` as unary and `powf` as binary. Same as `max(arg, 0.0)` for `ReLU`, `powf(arg, const)` can be either a generic (with broadcast) or a pair (`linalg.broadcast + linalg.powf`) and then lowered "correctly". Either way, the lower dialects need to know what kind of broadcast anyway, so no materialization of the constant tensors should remain. I want to flush the easy ones before we start working on type cast & softmax. --- .../mlir/Dialect/Linalg/IR/LinalgEnums.td | 6 +- .../Linalg/IR/LinalgNamedStructuredOps.yaml | 86 +++++++++++++++++++ mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp | 5 ++ .../linalg/opdsl/lang/comprehension.py | 2 + .../linalg/opdsl/ops/core_named_ops.py | 33 +++++++ .../Dialect/Linalg/generalize-named-ops.mlir | 48 +++++++++++ mlir/test/Dialect/Linalg/named-ops-fail.mlir | 33 +++++++ mlir/test/Dialect/Linalg/named-ops.mlir | 65 ++++++++++++++ 8 files changed, 276 insertions(+), 2 deletions(-) diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td b/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td index 7a350d2c0142..6b4b073fc672 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgEnums.td @@ -28,7 +28,8 @@ def UnaryFn : I32EnumAttr<"UnaryFn", "", [ I32EnumAttrCase<"sqrt", 8>, I32EnumAttrCase<"rsqrt", 9>, I32EnumAttrCase<"square", 10>, - I32EnumAttrCase<"tanh", 11> + I32EnumAttrCase<"tanh", 11>, + I32EnumAttrCase<"erf", 12> ]> { let genSpecializedAttr = 0; let cppNamespace = "::mlir::linalg"; @@ -42,7 +43,8 @@ def BinaryFn : I32EnumAttr<"BinaryFn", "", [ I32EnumAttrCase<"max_signed", 5>, I32EnumAttrCase<"min_signed", 6>, I32EnumAttrCase<"max_unsigned", 7>, - I32EnumAttrCase<"min_unsigned", 8> + I32EnumAttrCase<"min_unsigned", 8>, + I32EnumAttrCase<"powf", 9> ]> { let genSpecializedAttr = 0; let cppNamespace = "::mlir::linalg"; diff --git a/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml b/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml index b75675773475..584bfcd8b59d 100644 --- a/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml +++ b/mlir/include/mlir/Dialect/Linalg/IR/LinalgNamedStructuredOps.yaml @@ -514,6 +514,41 @@ structured_op: !LinalgStructuredOpConfig - !ScalarExpression scalar_arg: I --- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: erf + cpp_class_name: erfOp + doc: |- + Applies erf(x) elementwise. + + No numeric casting is performed on the input operand. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: I + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: unary + fn_name: erf + operands: + - !ScalarExpression + scalar_arg: I +--- !LinalgOpConfig metadata: !LinalgOpMetadata name: elemwise_binary cpp_class_name: ElemwiseBinaryOp @@ -922,6 +957,57 @@ structured_op: !LinalgStructuredOpConfig - !ScalarExpression scalar_arg: rhs --- !LinalgOpConfig +metadata: !LinalgOpMetadata + name: powf + cpp_class_name: PowFOp + doc: |- + Takes the powf(lhs, rhs) between two inputs, elementwise. For powf(arg, 2) use `linalg.square`. + + Only applies to floating point values. + + The shapes and element types must be identical. The appropriate casts, + broadcasts and reductions should be done previously to calling this op. + + This means reduction/broadcast/element cast semantics is explicit. Further + passes can take that into account when lowering this code. For example, + a `linalg.broadcast` + `linalg.powf` sequence can be lowered to a + `linalg.generic` with different affine maps for the two operands. +structured_op: !LinalgStructuredOpConfig + args: + - !LinalgOperandDefConfig + name: lhs + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: rhs + kind: input_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + - !LinalgOperandDefConfig + name: O + kind: output_tensor + type_var: T1 + shape_map: affine_map<() -> ()> + indexing_maps: !LinalgIndexingMapsConfig + static_indexing_maps: + - affine_map<() -> ()> + - affine_map<() -> ()> + - affine_map<() -> ()> + iterator_types: [] + assignments: + - !ScalarAssign + arg: O + value: !ScalarExpression + scalar_fn: + kind: binary + fn_name: powf + operands: + - !ScalarExpression + scalar_arg: lhs + - !ScalarExpression + scalar_arg: rhs +--- !LinalgOpConfig metadata: !LinalgOpMetadata name: matmul cpp_class_name: MatmulOp diff --git a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp index 5d10b59373ad..036005ce9d92 100644 --- a/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp +++ b/mlir/lib/Dialect/Linalg/IR/LinalgOps.cpp @@ -411,6 +411,8 @@ public: return builder.create(arg.getLoc(), arg, arg); case UnaryFn::tanh: return builder.create(arg.getLoc(), arg); + case UnaryFn::erf: + return builder.create(arg.getLoc(), arg); } llvm_unreachable("unsupported unary function"); } @@ -483,6 +485,9 @@ public: if (allFloatingPoint) return builder.create(arg0.getLoc(), arg0, arg1); return builder.create(arg0.getLoc(), arg0, arg1); + case BinaryFn::powf: + assert(allFloatingPoint); + return builder.create(arg0.getLoc(), arg0, arg1); } llvm_unreachable("unsupported binary function"); } diff --git a/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py b/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py index f7bc81bd2f68..bb43ebf2b692 100644 --- a/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py +++ b/mlir/python/mlir/dialects/linalg/opdsl/lang/comprehension.py @@ -296,6 +296,7 @@ class UnaryFn: rsqrt = UnaryFnType("rsqrt") square = UnaryFnType("square") tanh = UnaryFnType("tanh") + erf = UnaryFnType("erf") class BinaryFnType: @@ -335,6 +336,7 @@ class BinaryFn: min_signed = BinaryFnType("min_signed") max_unsigned = BinaryFnType("max_unsigned") min_unsigned = BinaryFnType("min_unsigned") + powf = BinaryFnType("powf") class TypeFnType: diff --git a/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py b/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py index 2c8864be1107..ca2bb0c5f7f8 100644 --- a/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py +++ b/mlir/python/mlir/dialects/linalg/opdsl/ops/core_named_ops.py @@ -168,6 +168,18 @@ def tanh( O[None] = UnaryFn.tanh(I[None]) +@linalg_structured_op +def erf( + I=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Applies erf(x) elementwise. + + No numeric casting is performed on the input operand. + """ + O[None] = UnaryFn.erf(I[None]) + + @linalg_structured_op def elemwise_binary( lhs=TensorDef(T1), @@ -318,6 +330,27 @@ def min( O[None] = BinaryFn.min_signed(lhs[None], rhs[None]) +@linalg_structured_op +def powf( + lhs=TensorDef(T1), + rhs=TensorDef(T1), + O=TensorDef(T1, output=True), +): + """Takes the powf(lhs, rhs) between two inputs, elementwise. For powf(arg, 2) use `linalg.square`. + + Only applies to floating point values. + + The shapes and element types must be identical. The appropriate casts, + broadcasts and reductions should be done previously to calling this op. + + This means reduction/broadcast/element cast semantics is explicit. Further + passes can take that into account when lowering this code. For example, + a `linalg.broadcast` + `linalg.powf` sequence can be lowered to a + `linalg.generic` with different affine maps for the two operands. + """ + O[None] = BinaryFn.powf(lhs[None], rhs[None]) + + @linalg_structured_op def matmul( A=TensorDef(T1, S.M, S.K), diff --git a/mlir/test/Dialect/Linalg/generalize-named-ops.mlir b/mlir/test/Dialect/Linalg/generalize-named-ops.mlir index add34412b92f..667ea3c18c8a 100644 --- a/mlir/test/Dialect/Linalg/generalize-named-ops.mlir +++ b/mlir/test/Dialect/Linalg/generalize-named-ops.mlir @@ -693,6 +693,27 @@ func.func @generalize_tanh(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) // ----- +func.func @generalize_erf(%arg: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { + linalg.erf ins(%arg : memref<7x14x21xf32>) outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_erf +// CHECK-SAME: (%[[ARG:.+]]: memref<7x14x21xf32>, %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]] : memref<7x14x21xf32>) outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32) +// CHECK-NEXT: %[[erf:.+]] = math.erf %[[BBARG0]] : f32 +// CHECK-NEXT: linalg.yield %[[erf]] : f32 + +// ----- + func.func @generalize_max(%lhs: memref<7x14x21xf32>, %rhs: memref<7x14x21xf32>, %out: memref<7x14x21xf32>) { linalg.max ins(%lhs, %rhs : memref<7x14x21xf32>, memref<7x14x21xf32>) @@ -741,6 +762,33 @@ func.func @generalize_min(%lhs: memref<7x14x21xf32>, %rhs: memref<7x14x21xf32>, // CHECK-NEXT: %[[min:.+]] = arith.minimumf %[[BBARG0]], %[[BBARG1]] : f32 // CHECK-NEXT: linalg.yield %[[min]] : f32 + +// ----- + +func.func @generalize_powf(%lhs: memref<7x14x21xf32>, %rhs: memref<7x14x21xf32>, + %out: memref<7x14x21xf32>) { + linalg.powf ins(%lhs, %rhs : memref<7x14x21xf32>, memref<7x14x21xf32>) + outs(%out : memref<7x14x21xf32>) + return +} + +// CHECK: #[[MAP:.+]] = affine_map<(d0, d1, d2) -> (d0, d1, d2)> + +// CHECK: func @generalize_powf +// CHECK-SAME: (%[[LHS:.+]]: memref<7x14x21xf32>, %[[RHS:.+]]: memref<7x14x21xf32>, +// CHECK-SAME: %[[OUT:.+]]: memref<7x14x21xf32>) + +// CHECK: linalg.generic +// CHECK-SAME: indexing_maps = [#[[MAP]], #[[MAP]], #[[MAP]]] +// CHECK-SAME: iterator_types = ["parallel", "parallel", "parallel"]} +// CHECK-SAME: ins(%[[LHS]], %[[RHS]] : memref<7x14x21xf32>, memref<7x14x21xf32>) +// CHECK-SAME: outs(%[[OUT]] : memref<7x14x21xf32>) + +// CHECK: ^{{.+}}(%[[BBARG0:.+]]: f32, %[[BBARG1:.+]]: f32, %[[BBARG2:.+]]: f32) +// CHECK-NEXT: %[[powf:.+]] = math.powf %[[BBARG0]], %[[BBARG1]] : f32 +// CHECK-NEXT: linalg.yield %[[powf]] : f32 + + // ----- diff --git a/mlir/test/Dialect/Linalg/named-ops-fail.mlir b/mlir/test/Dialect/Linalg/named-ops-fail.mlir index f66608e71ffc..e92a77aa7ad0 100644 --- a/mlir/test/Dialect/Linalg/named-ops-fail.mlir +++ b/mlir/test/Dialect/Linalg/named-ops-fail.mlir @@ -272,6 +272,22 @@ func.func @tanh_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { // ----- +func.func @erf_type_cast(%arg: memref<4x8x16xf16>, %out: memref<4x8x16xf32>) { + // CHECK: operand 1 ('f16') doesn't match the element type of the enclosing linalg.generic op ('f32') + linalg.erf ins(%arg : memref<4x8x16xf16>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @erf_broadcast(%arg: memref<8x16xf32>, %out: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.erf ins(%arg : memref<8x16xf32>) outs(%out: memref<4x8x16xf32>) + return +} + +// ----- + func.func @max_type_cast(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf16>, %arg2: memref<4x8x16xf32>) { // CHECK: op requires the same type for all operands and results linalg.max ins(%arg0, %arg1 : memref<4x8x16xf32>, memref<4x8x16xf16>) outs(%arg2: memref<4x8x16xf32>) @@ -301,3 +317,20 @@ func.func @min_broadcast(%arg0: memref<8x16xf32>, %arg1: memref<4x8x16xf32>, %ar linalg.min ins(%arg0, %arg1 : memref<8x16xf32>, memref<4x8x16xf32>) outs(%arg2: memref<4x8x16xf32>) return } + +// ----- + +func.func @powf_type_cast(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf16>, %arg2: memref<4x8x16xf32>) { + // CHECK: op requires the same type for all operands and results + linalg.powf ins(%arg0, %arg1 : memref<4x8x16xf32>, memref<4x8x16xf16>) outs(%arg2: memref<4x8x16xf32>) + return +} + +// ----- + +func.func @powf_broadcast(%arg0: memref<8x16xf32>, %arg1: memref<4x8x16xf32>, %arg2: memref<4x8x16xf32>) { + // CHECK: op expected operand rank (2) to match the result rank of indexing_map #0 (3) + linalg.powf ins(%arg0, %arg1 : memref<8x16xf32>, memref<4x8x16xf32>) outs(%arg2: memref<4x8x16xf32>) + return +} + diff --git a/mlir/test/Dialect/Linalg/named-ops.mlir b/mlir/test/Dialect/Linalg/named-ops.mlir index cf59f6736100..fefe5578947f 100644 --- a/mlir/test/Dialect/Linalg/named-ops.mlir +++ b/mlir/test/Dialect/Linalg/named-ops.mlir @@ -1783,6 +1783,37 @@ func.func @tanh_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { // ----- +// CHECK-LABEL: func @erf_dynamic +func.func @erf_dynamic(%arg0: memref, %arg1: memref) { + // CHECK: linalg.erf + // CHECK-SAME: ins(%{{.+}} : memref) outs(%{{.+}} : memref) + linalg.erf ins(%arg0 : memref) outs(%arg1: memref) + return +} + +// ----- + +// CHECK-LABEL: func @erf_static +func.func @erf_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>) { + // CHECK: linalg.erf + // CHECK-SAME: ins(%{{.+}} : memref<4x8x16xf32>) outs(%{{.+}} : memref<4x8x16xf32>) + linalg.erf ins(%arg0 : memref<4x8x16xf32>) outs(%arg1: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @erf_tensor +func.func @erf_tensor(%arg0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.erf + // CHECK-SAME: ins(%{{.+}} : tensor<4x8x16xf32>) outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.erf ins(%arg0 : tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + // CHECK-LABEL: func @max_dynamic func.func @max_dynamic(%arg0: memref, %arg1: memref, %arg2: memref) { // CHECK: linalg.max @@ -1851,6 +1882,40 @@ func.func @min_tensor(%arg0: tensor<4x8x16xf32>, %arg1: tensor<4x8x16xf32>) -> t // ----- +// CHECK-LABEL: func @powf_dynamic +func.func @powf_dynamic(%arg0: memref, %arg1: memref, %arg2: memref) { + // CHECK: linalg.powf + // CHECK-SAME: ins(%{{.+}}, %{{.+}} : memref, memref) + // CHECK-SAME: outs(%{{.+}} : memref) + linalg.powf ins(%arg0, %arg1 : memref, memref) outs(%arg2: memref) + return +} + +// ----- + +// CHECK-LABEL: func @powf_static +func.func @powf_static(%arg0: memref<4x8x16xf32>, %arg1: memref<4x8x16xf32>, %arg2: memref<4x8x16xf32>) { + // CHECK: linalg.powf + // CHECK-SAME: ins(%{{.+}}, %{{.+}} : memref<4x8x16xf32>, memref<4x8x16xf32>) + // CHECK-SAME: outs(%{{.+}} : memref<4x8x16xf32>) + linalg.powf ins(%arg0, %arg1 : memref<4x8x16xf32>, memref<4x8x16xf32>) outs(%arg2: memref<4x8x16xf32>) + return +} + +// ----- + +// CHECK-LABEL: func @powf_tensor +func.func @powf_tensor(%arg0: tensor<4x8x16xf32>, %arg1: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> { + %0 = tensor.empty() : tensor<4x8x16xf32> + // CHECK: linalg.powf + // CHECK-SAME: ins(%{{.+}}, %{{.+}} : tensor<4x8x16xf32>, tensor<4x8x16xf32>) + // CHECK-SAME: outs(%{{.+}} : tensor<4x8x16xf32>) + %1 = linalg.powf ins(%arg0, %arg1 : tensor<4x8x16xf32>, tensor<4x8x16xf32>) outs(%0: tensor<4x8x16xf32>) -> tensor<4x8x16xf32> + return %1 : tensor<4x8x16xf32> +} + +// ----- + // CHECK-LABEL: func @fill_tensor func.func @fill_tensor(%f: f32, %v: vector<2x4xf32>) -> (tensor, tensor>) { %e0 = tensor.empty() : tensor -- GitLab From bd07c22e5372789c3eb47b9009029d5e99e0ef9f Mon Sep 17 00:00:00 2001 From: Lawrence Benson Date: Mon, 29 Apr 2024 16:45:33 +0200 Subject: [PATCH 235/301] [Clang] Add support for scalable vectors in __builtin_reduce_* functions (#87750) Currently, a lot of `__builtin_reduce_*` function do not support scalable vectors, i.e., ARM SVE and RISCV V. This PR adds support for them. The main code change is to use a different path to extract the type from the vectors, the rest is the same and LLVM supports the reduce functions for `vscale` vectors. This PR adds scalable vector support for: - `__builtin_reduce_add` - `__builtin_reduce_mul` - `__builtin_reduce_xor` - `__builtin_reduce_or` - `__builtin_reduce_and` - `__builtin_reduce_min` - `__builtin_reduce_max` Note: For all except `min/max`, the element type must still be an integer value. Adding floating point support for `add` and `mul` is still an open TODO. --- clang/docs/LanguageExtensions.rst | 2 + clang/docs/ReleaseNotes.rst | 1 + clang/include/clang/AST/Type.h | 4 ++ clang/lib/AST/Type.cpp | 12 +++++ clang/lib/CodeGen/CGBuiltin.cpp | 10 +++- clang/lib/Sema/SemaChecking.cpp | 23 +++++++-- clang/test/CodeGen/builtins-reduction-math.c | 53 ++++++++++++++++++++ 7 files changed, 99 insertions(+), 6 deletions(-) diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 127d1b6dd482..87cb743856b0 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -711,6 +711,8 @@ even-odd element pair with indices ``i * 2`` and ``i * 2 + 1`` with power of 2, the vector is widened with neutral elements for the reduction at the end to the next power of 2. +These reductions support both fixed-sized and scalable vector types. + Example: .. code-block:: c++ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 347c81253d39..4cb2462ae649 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -222,6 +222,7 @@ Non-comprehensive list of changes in this release - ``__typeof_unqual__`` is available in all C modes as an extension, which behaves like ``typeof_unqual`` from C23, similar to ``__typeof__`` and ``typeof``. +- ``__builtin_reduce_{add|mul|xor|or|and|min|max}`` builtins now support scalable vectors. * Shared libraries linked with either the ``-ffast-math``, ``-Ofast``, or ``-funsafe-math-optimizations`` flags will no longer enable flush-to-zero diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index dff02d4861b3..fa2b47ed3d23 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -2378,6 +2378,10 @@ public: /// 'riscv_rvv_vector_bits' type attribute as VectorType. QualType getRVVEltType(const ASTContext &Ctx) const; + /// Returns the representative type for the element of a sizeless vector + /// builtin type. + QualType getSizelessVectorEltType(const ASTContext &Ctx) const; + /// Types are partitioned into 3 broad categories (C99 6.2.5p1): /// object types, function types, and incomplete types. diff --git a/clang/lib/AST/Type.cpp b/clang/lib/AST/Type.cpp index 8aaa6801d85b..68e81f45b4c2 100644 --- a/clang/lib/AST/Type.cpp +++ b/clang/lib/AST/Type.cpp @@ -2510,6 +2510,18 @@ bool Type::isSveVLSBuiltinType() const { return false; } +QualType Type::getSizelessVectorEltType(const ASTContext &Ctx) const { + assert(isSizelessVectorType() && "Must be sizeless vector type"); + // Currently supports SVE and RVV + if (isSVESizelessBuiltinType()) + return getSveEltType(Ctx); + + if (isRVVSizelessBuiltinType()) + return getRVVEltType(Ctx); + + llvm_unreachable("Unhandled type"); +} + QualType Type::getSveEltType(const ASTContext &Ctx) const { assert(isSveVLSBuiltinType() && "unsupported type!"); diff --git a/clang/lib/CodeGen/CGBuiltin.cpp b/clang/lib/CodeGen/CGBuiltin.cpp index d08ab5391489..a370734e00d3 100644 --- a/clang/lib/CodeGen/CGBuiltin.cpp +++ b/clang/lib/CodeGen/CGBuiltin.cpp @@ -3885,9 +3885,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } case Builtin::BI__builtin_reduce_max: { - auto GetIntrinsicID = [](QualType QT) { + auto GetIntrinsicID = [this](QualType QT) { if (auto *VecTy = QT->getAs()) QT = VecTy->getElementType(); + else if (QT->isSizelessVectorType()) + QT = QT->getSizelessVectorEltType(CGM.getContext()); + if (QT->isSignedIntegerType()) return llvm::Intrinsic::vector_reduce_smax; if (QT->isUnsignedIntegerType()) @@ -3900,9 +3903,12 @@ RValue CodeGenFunction::EmitBuiltinExpr(const GlobalDecl GD, unsigned BuiltinID, } case Builtin::BI__builtin_reduce_min: { - auto GetIntrinsicID = [](QualType QT) { + auto GetIntrinsicID = [this](QualType QT) { if (auto *VecTy = QT->getAs()) QT = VecTy->getElementType(); + else if (QT->isSizelessVectorType()) + QT = QT->getSizelessVectorEltType(CGM.getContext()); + if (QT->isSignedIntegerType()) return llvm::Intrinsic::vector_reduce_smin; if (QT->isUnsignedIntegerType()) diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index e33113ab9c4c..e26cf20d1036 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -3164,13 +3164,20 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, const Expr *Arg = TheCall->getArg(0); const auto *TyA = Arg->getType()->getAs(); - if (!TyA) { + + QualType ElTy; + if (TyA) + ElTy = TyA->getElementType(); + else if (Arg->getType()->isSizelessVectorType()) + ElTy = Arg->getType()->getSizelessVectorEltType(Context); + + if (ElTy.isNull()) { Diag(Arg->getBeginLoc(), diag::err_builtin_invalid_arg_type) << 1 << /* vector ty*/ 4 << Arg->getType(); return ExprError(); } - TheCall->setType(TyA->getElementType()); + TheCall->setType(ElTy); break; } @@ -3186,12 +3193,20 @@ Sema::CheckBuiltinFunctionCall(FunctionDecl *FDecl, unsigned BuiltinID, const Expr *Arg = TheCall->getArg(0); const auto *TyA = Arg->getType()->getAs(); - if (!TyA || !TyA->getElementType()->isIntegerType()) { + + QualType ElTy; + if (TyA) + ElTy = TyA->getElementType(); + else if (Arg->getType()->isSizelessVectorType()) + ElTy = Arg->getType()->getSizelessVectorEltType(Context); + + if (ElTy.isNull() || !ElTy->isIntegerType()) { Diag(Arg->getBeginLoc(), diag::err_builtin_invalid_arg_type) << 1 << /* vector of integers */ 6 << Arg->getType(); return ExprError(); } - TheCall->setType(TyA->getElementType()); + + TheCall->setType(ElTy); break; } diff --git a/clang/test/CodeGen/builtins-reduction-math.c b/clang/test/CodeGen/builtins-reduction-math.c index 34f39cea5265..acafe9222d59 100644 --- a/clang/test/CodeGen/builtins-reduction-math.c +++ b/clang/test/CodeGen/builtins-reduction-math.c @@ -1,5 +1,8 @@ // RUN: %clang_cc1 -triple x86_64-apple-darwin %s -emit-llvm -disable-llvm-passes -o - | FileCheck %s +// REQUIRES: aarch64-registered-target +// RUN: %clang_cc1 -O1 -triple aarch64 -target-feature +sve %s -emit-llvm -disable-llvm-passes -o - | FileCheck --check-prefixes=SVE %s + typedef float float4 __attribute__((ext_vector_type(4))); typedef short int si8 __attribute__((ext_vector_type(8))); typedef unsigned int u4 __attribute__((ext_vector_type(4))); @@ -134,3 +137,53 @@ void test_builtin_reduce_and(si8 vi1, u4 vu1) { // CHECK-NEXT: call i32 @llvm.vector.reduce.and.v4i32(<4 x i32> [[VU1]]) unsigned r3 = __builtin_reduce_and(vu1); } + +#if defined(__ARM_FEATURE_SVE) +#include + +void test_builtin_reduce_SVE(int a, unsigned long long b, short c, float d) { + // SVE-LABEL: void @test_builtin_reduce_SVE( + + svint32_t vec_a = svdup_s32(a); + svuint64_t vec_b = svdup_u64(b); + svint16_t vec_c1 = svdup_s16(c); + svuint16_t vec_c2 = svdup_u16(c); + svfloat32_t vec_d = svdup_f32(d); + + // SVE: [[VF1:%.+]] = load , ptr %vec_a + // SVE-NEXT: call i32 @llvm.vector.reduce.add.nxv4i32( [[VF1]]) + int r1 = __builtin_reduce_add(vec_a); + + // SVE: [[VF2:%.+]] = load , ptr %vec_a + // SVE-NEXT: call i32 @llvm.vector.reduce.mul.nxv4i32( [[VF2]]) + int r2 = __builtin_reduce_mul(vec_a); + + // SVE: [[VF3:%.+]] = load , ptr %vec_b + // SVE-NEXT: call i64 @llvm.vector.reduce.xor.nxv2i64( [[VF3]]) + long long r3 = __builtin_reduce_xor(vec_b); + + // SVE: [[VF4:%.+]] = load , ptr %vec_b + // SVE-NEXT: call i64 @llvm.vector.reduce.or.nxv2i64( [[VF4]]) + long long r4 = __builtin_reduce_or(vec_b); + + // SVE: [[VF5:%.+]] = load , ptr %vec_b + // SVE-NEXT: call i64 @llvm.vector.reduce.and.nxv2i64( [[VF5]]) + long long r5 = __builtin_reduce_and(vec_b); + + // SVE: [[VF6:%.+]] = load , ptr %vec_c1 + // SVE-NEXT: call i16 @llvm.vector.reduce.smax.nxv8i16( [[VF6]]) + short r6 = __builtin_reduce_max(vec_c1); + + // SVE: [[VF7:%.+]] = load , ptr %vec_c2 + // SVE-NEXT: call i16 @llvm.vector.reduce.umin.nxv8i16( [[VF7]]) + unsigned short r7 = __builtin_reduce_min(vec_c2); + + // SVE: [[VF8:%.+]] = load , ptr %vec_d + // SVE-NEXT: call float @llvm.vector.reduce.fmax.nxv4f32( [[VF8]]) + float r8 = __builtin_reduce_max(vec_d); + + // SVE: [[VF9:%.+]] = load , ptr %vec_d + // SVE-NEXT: call float @llvm.vector.reduce.fmin.nxv4f32( [[VF9]]) + float r9 = __builtin_reduce_min(vec_d); +} +#endif -- GitLab From ef78edafabe72fac1dad1675a5a25d7e2d62bb2c Mon Sep 17 00:00:00 2001 From: Alexey Bataev Date: Mon, 29 Apr 2024 07:41:22 -0700 Subject: [PATCH 236/301] [SLP][NFC]Add a test with the optimizable and and final ext, NFC. --- .../RISCV/minbw-with-and-and-scalar-trunc.ll | 44 +++++++++++++++++++ 1 file changed, 44 insertions(+) create mode 100644 llvm/test/Transforms/SLPVectorizer/RISCV/minbw-with-and-and-scalar-trunc.ll diff --git a/llvm/test/Transforms/SLPVectorizer/RISCV/minbw-with-and-and-scalar-trunc.ll b/llvm/test/Transforms/SLPVectorizer/RISCV/minbw-with-and-and-scalar-trunc.ll new file mode 100644 index 000000000000..fc977585614b --- /dev/null +++ b/llvm/test/Transforms/SLPVectorizer/RISCV/minbw-with-and-and-scalar-trunc.ll @@ -0,0 +1,44 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 +; RUN: opt -S --passes=slp-vectorizer -mtriple=riscv64-unknown-linux-gnu -mattr=+v < %s | FileCheck %s +@c = global [12 x i64] zeroinitializer + +; FIXME: after minbitwidth analysis and i32 conv.., 65535 is transformed to +; and <4 x i16> , -1, which must be dropped. +; FIXME: need to adjust the cost of the final transformation, since the user is +; just a trunc to i16 (it must be free). +define i16 @test() { +; CHECK-LABEL: define i16 @test( +; CHECK-SAME: ) #[[ATTR0:[0-9]+]] { +; CHECK-NEXT: entry: +; CHECK-NEXT: [[TMP0:%.*]] = call <4 x i64> @llvm.experimental.vp.strided.load.v4i64.p0.i64(ptr align 8 @c, i64 24, <4 x i1> , i32 4) +; CHECK-NEXT: [[TMP1:%.*]] = trunc <4 x i64> [[TMP0]] to <4 x i16> +; CHECK-NEXT: [[TMP2:%.*]] = and <4 x i16> [[TMP1]], +; CHECK-NEXT: [[TMP3:%.*]] = xor <4 x i16> [[TMP2]], +; CHECK-NEXT: [[TMP4:%.*]] = call i16 @llvm.vector.reduce.umax.v4i16(<4 x i16> [[TMP3]]) +; CHECK-NEXT: [[TMP5:%.*]] = zext i16 [[TMP4]] to i32 +; CHECK-NEXT: [[T:%.*]] = trunc i32 [[TMP5]] to i16 +; CHECK-NEXT: ret i16 [[T]] +; +entry: + %0 = load i64, ptr @c, align 8 + %conv = trunc i64 %0 to i32 + %conv3 = and i32 %conv, 65535 + %conv4 = xor i32 %conv3, 65535 + %1 = load i64, ptr getelementptr inbounds ([12 x i64], ptr @c, i64 0, i64 3), align 8 + %conv.1 = trunc i64 %1 to i32 + %conv3.1 = and i32 %conv.1, 65535 + %conv4.1 = xor i32 %conv3.1, 65535 + %.conv4.1 = tail call i32 @llvm.umax.i32(i32 %conv4, i32 %conv4.1) + %2 = load i64, ptr getelementptr inbounds ([12 x i64], ptr @c, i64 0, i64 6), align 8 + %conv.2 = trunc i64 %2 to i32 + %conv3.2 = and i32 %conv.2, 65535 + %conv4.2 = xor i32 %conv3.2, 65535 + %.conv4.2 = tail call i32 @llvm.umax.i32(i32 %.conv4.1, i32 %conv4.2) + %3 = load i64, ptr getelementptr inbounds ([12 x i64], ptr @c, i64 0, i64 9), align 8 + %conv.3 = trunc i64 %3 to i32 + %conv3.3 = and i32 %conv.3, 65535 + %conv4.3 = xor i32 %conv3.3, 65535 + %.conv4.3 = tail call i32 @llvm.umax.i32(i32 %.conv4.2, i32 %conv4.3) + %t = trunc i32 %.conv4.3 to i16 + ret i16 %t +} -- GitLab From 3044eaf40932c23d668483c6557fa3877f979e62 Mon Sep 17 00:00:00 2001 From: Kiran Chandramohan Date: Mon, 29 Apr 2024 15:47:17 +0100 Subject: [PATCH 237/301] [Flang][OpenMP] Use a label to avoid complexity of too many CHECK-DAGs in a test (#90190) This speeds up the test. --- .../OpenMP/threadprivate-real-logical-complex-derivedtype.f90 | 1 + 1 file changed, 1 insertion(+) diff --git a/flang/test/Lower/OpenMP/threadprivate-real-logical-complex-derivedtype.f90 b/flang/test/Lower/OpenMP/threadprivate-real-logical-complex-derivedtype.f90 index 55f806962a60..0a249ff101a0 100644 --- a/flang/test/Lower/OpenMP/threadprivate-real-logical-complex-derivedtype.f90 +++ b/flang/test/Lower/OpenMP/threadprivate-real-logical-complex-derivedtype.f90 @@ -21,6 +21,7 @@ module test !CHECK-DAG: fir.global @_QMtestEz : !fir.logical<4> { contains +!CHECK-LABEL: func.func @_QMtestPsub subroutine sub() !CHECK-DAG: %[[T:.*]] = fir.address_of(@_QMtestEt) : !fir.ref}>> !CHECK-DAG: %[[T_DECL:.*]]:2 = hlfir.declare %[[T]] {uniq_name = "_QMtestEt"} : (!fir.ref}>>) -> (!fir.ref}>>, !fir.ref}>>) -- GitLab From d486a4c29a331d3bfb3649a8a0aa2ba4970a6455 Mon Sep 17 00:00:00 2001 From: David Green Date: Mon, 29 Apr 2024 15:47:24 +0100 Subject: [PATCH 238/301] [ARM] Ensure extra uses are not dead in tail-folding-counting-down.ll. NFC This might help keep the test valid if vplan is removing dead intructions. --- .../Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll index 5c1966fa7a2d..0f524561eadc 100644 --- a/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll +++ b/llvm/test/Transforms/LoopVectorize/ARM/tail-folding-counting-down.ll @@ -107,9 +107,10 @@ while.body: %1 = load i8, ptr %b.addr.07, align 1 %add = add i8 %1, %0 %incdec.ptr4 = getelementptr inbounds i8, ptr %c.addr.08, i32 1 - store i8 %add, ptr %c.addr.08, align 1 %cmp = icmp sgt i32 %N.addr.09, 1 %select = select i1 %cmp, i8 %0, i8 %1 + %add2 = add i8 %add, %select + store i8 %add2, ptr %c.addr.08, align 1 br i1 %cmp, label %while.body, label %while.end.loopexit while.end.loopexit: -- GitLab From f6187c76595d576ee75252eee3bf199e91bd276f Mon Sep 17 00:00:00 2001 From: Thomas Preud'homme Date: Mon, 29 Apr 2024 15:40:16 +0100 Subject: [PATCH 239/301] [llvm-driver] Fix header order of llvm-driver-template --- llvm/cmake/modules/llvm-driver-template.cpp.in | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/llvm/cmake/modules/llvm-driver-template.cpp.in b/llvm/cmake/modules/llvm-driver-template.cpp.in index 71aca6cd140c..1470ef1f0616 100644 --- a/llvm/cmake/modules/llvm-driver-template.cpp.in +++ b/llvm/cmake/modules/llvm-driver-template.cpp.in @@ -6,9 +6,9 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Support/LLVMDriver.h" #include "llvm/ADT/ArrayRef.h" #include "llvm/Support/InitLLVM.h" +#include "llvm/Support/LLVMDriver.h" int @TOOL_NAME@_main(int argc, char **, const llvm::ToolContext &); -- GitLab From b811ad6f348db076b995fdd8f688d72e5a40f7f9 Mon Sep 17 00:00:00 2001 From: Brian Gesiak Date: Mon, 29 Apr 2024 10:54:31 -0400 Subject: [PATCH 240/301] [mlir-lsp] Un-revert unit test additions (#90232) This reverts the revert commit 6844c2feae93dd4251, which was comprised of the following commits: 1. f3f6f22dfcced - [mlir-lsp] Initialize `Reply::method` member (#89857) 2. 37e13d4924841 - [mlir-lsp] Log invalid notification params (#89856) 3. ba1b52e6e764a - [mlir-lsp] Add `outgoingNotification` unit test 4. 84bc21f910173 - [mlir-lsp] Add transport unit tests (#89855) Of these, (4) specifically caused issues in Windows pre-merge buildbots, in the `TransportTest.MethodNotFound` unit test that it added. The failure was caused by a statement that asserted that opening a file stream on a newly created temporary file did not result in an error, but this assert failed on Windows. This patch adds additional error logging for failures, to make it clearer what went wrong when failures occur. This patch also addresses the Windows failure by ensuring temporary files are created in the system temporary directory. --- .../mlir/Tools/lsp-server-support/Transport.h | 12 +- .../Tools/lsp-server-support/Transport.cpp | 6 +- mlir/unittests/CMakeLists.txt | 1 + mlir/unittests/Tools/CMakeLists.txt | 1 + .../Tools/lsp-server-support/CMakeLists.txt | 6 + .../Tools/lsp-server-support/Transport.cpp | 134 ++++++++++++++++++ 6 files changed, 154 insertions(+), 6 deletions(-) create mode 100644 mlir/unittests/Tools/CMakeLists.txt create mode 100644 mlir/unittests/Tools/lsp-server-support/CMakeLists.txt create mode 100644 mlir/unittests/Tools/lsp-server-support/Transport.cpp diff --git a/mlir/include/mlir/Tools/lsp-server-support/Transport.h b/mlir/include/mlir/Tools/lsp-server-support/Transport.h index ce742be7a941..44c71058cf71 100644 --- a/mlir/include/mlir/Tools/lsp-server-support/Transport.h +++ b/mlir/include/mlir/Tools/lsp-server-support/Transport.h @@ -147,9 +147,15 @@ public: void (ThisT::*handler)(const Param &)) { notificationHandlers[method] = [method, handler, thisPtr](llvm::json::Value rawParams) { - llvm::Expected param = parse(rawParams, method, "request"); - if (!param) - return llvm::consumeError(param.takeError()); + llvm::Expected param = + parse(rawParams, method, "notification"); + if (!param) { + return llvm::consumeError( + llvm::handleErrors(param.takeError(), [](const LSPError &lspError) { + Logger::error("JSON parsing error: {0}", + lspError.message.c_str()); + })); + } (thisPtr->*handler)(*param); }; } diff --git a/mlir/lib/Tools/lsp-server-support/Transport.cpp b/mlir/lib/Tools/lsp-server-support/Transport.cpp index 64dea35614c0..339c5f382516 100644 --- a/mlir/lib/Tools/lsp-server-support/Transport.cpp +++ b/mlir/lib/Tools/lsp-server-support/Transport.cpp @@ -51,12 +51,12 @@ private: Reply::Reply(const llvm::json::Value &id, llvm::StringRef method, JSONTransport &transport, std::mutex &transportOutputMutex) - : id(id), transport(&transport), + : method(method), id(id), transport(&transport), transportOutputMutex(transportOutputMutex) {} Reply::Reply(Reply &&other) - : replied(other.replied.load()), id(std::move(other.id)), - transport(other.transport), + : method(other.method), replied(other.replied.load()), + id(std::move(other.id)), transport(other.transport), transportOutputMutex(other.transportOutputMutex) { other.transport = nullptr; } diff --git a/mlir/unittests/CMakeLists.txt b/mlir/unittests/CMakeLists.txt index 6fad249a0b2f..6d8aa290e82f 100644 --- a/mlir/unittests/CMakeLists.txt +++ b/mlir/unittests/CMakeLists.txt @@ -20,6 +20,7 @@ add_subdirectory(Support) add_subdirectory(Rewrite) add_subdirectory(TableGen) add_subdirectory(Target) +add_subdirectory(Tools) add_subdirectory(Transforms) if(MLIR_ENABLE_EXECUTION_ENGINE) diff --git a/mlir/unittests/Tools/CMakeLists.txt b/mlir/unittests/Tools/CMakeLists.txt new file mode 100644 index 000000000000..a97588d92866 --- /dev/null +++ b/mlir/unittests/Tools/CMakeLists.txt @@ -0,0 +1 @@ +add_subdirectory(lsp-server-support) diff --git a/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt b/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt new file mode 100644 index 000000000000..3aa8b9c4bc77 --- /dev/null +++ b/mlir/unittests/Tools/lsp-server-support/CMakeLists.txt @@ -0,0 +1,6 @@ +add_mlir_unittest(MLIRLspServerSupportTests + Transport.cpp +) +target_link_libraries(MLIRLspServerSupportTests + PRIVATE + MLIRLspServerSupportLib) diff --git a/mlir/unittests/Tools/lsp-server-support/Transport.cpp b/mlir/unittests/Tools/lsp-server-support/Transport.cpp new file mode 100644 index 000000000000..a086964cd366 --- /dev/null +++ b/mlir/unittests/Tools/lsp-server-support/Transport.cpp @@ -0,0 +1,134 @@ +//===- Transport.cpp - LSP JSON transport unit tests ----------------------===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// + +#include "mlir/Tools/lsp-server-support/Transport.h" +#include "mlir/Tools/lsp-server-support/Logging.h" +#include "mlir/Tools/lsp-server-support/Protocol.h" +#include "llvm/Support/FileSystem.h" +#include "gmock/gmock.h" +#include "gtest/gtest.h" + +using namespace mlir; +using namespace mlir::lsp; +using namespace testing; + +namespace { + +TEST(TransportTest, SendReply) { + std::string out; + llvm::raw_string_ostream os(out); + JSONTransport transport(nullptr, os); + MessageHandler handler(transport); + + transport.reply(1989, nullptr); + EXPECT_THAT(out, HasSubstr("\"id\":1989")); + EXPECT_THAT(out, HasSubstr("\"result\":null")); +} + +class TransportInputTest : public Test { + llvm::SmallVector inputPath; + std::FILE *in = nullptr; + std::string output = ""; + llvm::raw_string_ostream os; + std::optional transport = std::nullopt; + std::optional messageHandler = std::nullopt; + +protected: + TransportInputTest() : os(output) {} + + void SetUp() override { + std::error_code ec = + llvm::sys::fs::createTemporaryFile("lsp-unittest", "json", inputPath); + ASSERT_FALSE(ec) << "Could not create temporary file: " << ec.message(); + + in = std::fopen(inputPath.data(), "r"); + ASSERT_TRUE(in) << "Could not open temporary file: " + << std::strerror(errno); + transport.emplace(in, os, JSONStreamStyle::Delimited); + messageHandler.emplace(*transport); + } + + void TearDown() override { + EXPECT_EQ(std::fclose(in), 0) + << "Could not close temporary file FD: " << std::strerror(errno); + std::error_code ec = + llvm::sys::fs::remove(inputPath, /*IgnoreNonExisting=*/false); + EXPECT_FALSE(ec) << "Could not remove temporary file '" << inputPath.data() + << "': " << ec.message(); + } + + void writeInput(StringRef buffer) { + std::error_code ec; + llvm::raw_fd_ostream os(inputPath.data(), ec); + ASSERT_FALSE(ec) << "Could not write to '" << inputPath.data() + << "': " << ec.message(); + os << buffer; + os.close(); + } + + StringRef getOutput() const { return output; } + MessageHandler &getMessageHandler() { return *messageHandler; } + + void runTransport() { + bool gotEOF = false; + llvm::Error err = llvm::handleErrors( + transport->run(*messageHandler), [&](const llvm::ECError &ecErr) { + gotEOF = ecErr.convertToErrorCode() == std::errc::io_error; + }); + llvm::consumeError(std::move(err)); + EXPECT_TRUE(gotEOF); + } +}; + +TEST_F(TransportInputTest, RequestWithInvalidParams) { + struct Handler { + void onMethod(const TextDocumentItem ¶ms, + mlir::lsp::Callback callback) {} + } handler; + getMessageHandler().method("invalid-params-request", &handler, + &Handler::onMethod); + + writeInput("{\"jsonrpc\":\"2.0\",\"id\":92," + "\"method\":\"invalid-params-request\",\"params\":{}}\n"); + runTransport(); + EXPECT_THAT(getOutput(), HasSubstr("error")); + EXPECT_THAT(getOutput(), HasSubstr("missing value at (root).uri")); +} + +TEST_F(TransportInputTest, NotificationWithInvalidParams) { + // JSON parsing errors are only reported via error logging. As a result, this + // test can't make any expectations -- but it prints the output anyway, by way + // of demonstration. + Logger::setLogLevel(Logger::Level::Error); + + struct Handler { + void onNotification(const TextDocumentItem ¶ms) {} + } handler; + getMessageHandler().notification("invalid-params-notification", &handler, + &Handler::onNotification); + + writeInput("{\"jsonrpc\":\"2.0\",\"method\":\"invalid-params-notification\"," + "\"params\":{}}\n"); + runTransport(); +} + +TEST_F(TransportInputTest, MethodNotFound) { + writeInput("{\"jsonrpc\":\"2.0\",\"id\":29,\"method\":\"ack\"}\n"); + runTransport(); + EXPECT_THAT(getOutput(), HasSubstr("\"id\":29")); + EXPECT_THAT(getOutput(), HasSubstr("\"error\"")); + EXPECT_THAT(getOutput(), HasSubstr("\"message\":\"method not found: ack\"")); +} + +TEST_F(TransportInputTest, OutgoingNotification) { + auto notifyFn = getMessageHandler().outgoingNotification( + "outgoing-notification"); + notifyFn(CompletionList{}); + EXPECT_THAT(getOutput(), HasSubstr("\"method\":\"outgoing-notification\"")); +} +} // namespace -- GitLab From 91f251c31fbbc9b9d8ce69fce4fb50faa0179ef4 Mon Sep 17 00:00:00 2001 From: Daniil Kovalev Date: Mon, 29 Apr 2024 17:56:54 +0300 Subject: [PATCH 241/301] [clang] Fix `remove{CVR|Fast}Qualifiers` with 64-bit `Qualifiers::Mask` (#90329) After #84384, `Qualifiers::Mask` becomes 64-bit. So, operations like `Mask &= ~U32` where `U32` is `unsigned` produce undesirable results since higher 32 bits of `Mask` become zeroed while they should be preserved. Fix that by explicitly casting `unsigned` values to `uint64_t` in such operations. Signatures of fixed functions are intentionally left intact instead of changing the argument itself to `uint64_t` to keep things consistent with other functions working with the same qualifiers and to emphasize that 64-bit masks should not be used for these types of qualifiers. --- clang/include/clang/AST/Type.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/clang/include/clang/AST/Type.h b/clang/include/clang/AST/Type.h index fa2b47ed3d23..e6643469e0b3 100644 --- a/clang/include/clang/AST/Type.h +++ b/clang/include/clang/AST/Type.h @@ -480,7 +480,7 @@ public: } void removeCVRQualifiers(unsigned mask) { assert(!(mask & ~CVRMask) && "bitmask contains non-CVR bits"); - Mask &= ~mask; + Mask &= ~static_cast(mask); } void removeCVRQualifiers() { removeCVRQualifiers(CVRMask); @@ -609,7 +609,7 @@ public: } void removeFastQualifiers(unsigned mask) { assert(!(mask & ~FastMask) && "bitmask contains non-fast qualifier bits"); - Mask &= ~mask; + Mask &= ~static_cast(mask); } void removeFastQualifiers() { removeFastQualifiers(FastMask); -- GitLab From 3ba079183f82191d8b6a26dedfebc4a031a3fb6d Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Mon, 29 Apr 2024 08:18:51 -0700 Subject: [PATCH 242/301] [flang][runtime] Added missing routines into CUDA build. (#90272) Apparently, nvcc does not compile for device the routines whose definitions are not marked with device attribute (note that the forward declarations are already marked). It looks like it is different for class members, i.e. marking just the declarations is enough. --- flang/runtime/CMakeLists.txt | 1 + flang/runtime/file.cpp | 12 ++++++------ flang/runtime/namelist.cpp | 2 +- 3 files changed, 8 insertions(+), 7 deletions(-) diff --git a/flang/runtime/CMakeLists.txt b/flang/runtime/CMakeLists.txt index 9f25c5dfcad1..bc81e1b1887b 100644 --- a/flang/runtime/CMakeLists.txt +++ b/flang/runtime/CMakeLists.txt @@ -192,6 +192,7 @@ set(supported_files environment.cpp extrema.cpp external-unit.cpp + file.cpp findloc.cpp format.cpp inquiry.cpp diff --git a/flang/runtime/file.cpp b/flang/runtime/file.cpp index acd5d33d4bb8..79db17e70acd 100644 --- a/flang/runtime/file.cpp +++ b/flang/runtime/file.cpp @@ -457,22 +457,22 @@ std::int64_t SizeInBytes(const char *path) { return -1; } #else // defined(RT_DEVICE_COMPILATION) -bool IsATerminal(int fd) { +RT_API_ATTRS bool IsATerminal(int fd) { Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -bool IsExtant(const char *path) { +RT_API_ATTRS bool IsExtant(const char *path) { Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -bool MayRead(const char *path) { +RT_API_ATTRS bool MayRead(const char *path) { Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -bool MayWrite(const char *path) { +RT_API_ATTRS bool MayWrite(const char *path) { Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -bool MayReadAndWrite(const char *path) { +RT_API_ATTRS bool MayReadAndWrite(const char *path) { Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } -std::int64_t SizeInBytes(const char *path) { +RT_API_ATTRS std::int64_t SizeInBytes(const char *path) { Terminator{__FILE__, __LINE__}.Crash("%s: unsupported", RT_PRETTY_FUNCTION); } #endif // defined(RT_DEVICE_COMPILATION) diff --git a/flang/runtime/namelist.cpp b/flang/runtime/namelist.cpp index b9eed2101ecf..af092de70f78 100644 --- a/flang/runtime/namelist.cpp +++ b/flang/runtime/namelist.cpp @@ -596,7 +596,7 @@ bool IODEF(InputNamelist)(Cookie cookie, const NamelistGroup &group) { return true; } -bool IsNamelistNameOrSlash(IoStatementState &io) { +RT_API_ATTRS bool IsNamelistNameOrSlash(IoStatementState &io) { if (auto *listInput{ io.get_if>()}) { if (listInput->inNamelistSequence()) { -- GitLab From 1563a8752b33a854c3ab5a4e8b3dce39ac9831b8 Mon Sep 17 00:00:00 2001 From: Slava Zakharin Date: Mon, 29 Apr 2024 08:19:45 -0700 Subject: [PATCH 243/301] [flang][runtime] Allow building CUDA PTX library without global vars definitions. (#90280) --- flang/cmake/modules/AddFlangOffloadRuntime.cmake | 9 +++++++++ flang/runtime/environment.cpp | 2 ++ flang/runtime/unit.cpp | 2 ++ flang/runtime/utf.cpp | 2 ++ 4 files changed, 15 insertions(+) diff --git a/flang/cmake/modules/AddFlangOffloadRuntime.cmake b/flang/cmake/modules/AddFlangOffloadRuntime.cmake index e34d3851187a..0af12c8cfd54 100644 --- a/flang/cmake/modules/AddFlangOffloadRuntime.cmake +++ b/flang/cmake/modules/AddFlangOffloadRuntime.cmake @@ -2,6 +2,10 @@ option(FLANG_EXPERIMENTAL_CUDA_RUNTIME "Compile Fortran runtime as CUDA sources (experimental)" OFF ) +option(FLANG_CUDA_RUNTIME_PTX_WITHOUT_GLOBAL_VARS + "Do not compile global variables' definitions when producing PTX library" OFF + ) + set(FLANG_LIBCUDACXX_PATH "" CACHE PATH "Path to libcu++ package installation") set(FLANG_EXPERIMENTAL_OMP_OFFLOAD_BUILD "off" CACHE STRING @@ -56,6 +60,11 @@ macro(enable_cuda_compilation name files) # Add an OBJECT library consisting of CUDA PTX. llvm_add_library(${name}PTX OBJECT PARTIAL_SOURCES_INTENDED ${files}) set_property(TARGET obj.${name}PTX PROPERTY CUDA_PTX_COMPILATION ON) + if (FLANG_CUDA_RUNTIME_PTX_WITHOUT_GLOBAL_VARS) + target_compile_definitions(obj.${name}PTX + PRIVATE FLANG_RUNTIME_NO_GLOBAL_VAR_DEFS + ) + endif() endif() endmacro() diff --git a/flang/runtime/environment.cpp b/flang/runtime/environment.cpp index b2c9665a28df..52b1d99ba536 100644 --- a/flang/runtime/environment.cpp +++ b/flang/runtime/environment.cpp @@ -23,9 +23,11 @@ extern char **environ; namespace Fortran::runtime { +#ifndef FLANG_RUNTIME_NO_GLOBAL_VAR_DEFS RT_OFFLOAD_VAR_GROUP_BEGIN RT_VAR_ATTRS ExecutionEnvironment executionEnvironment; RT_OFFLOAD_VAR_GROUP_END +#endif // FLANG_RUNTIME_NO_GLOBAL_VAR_DEFS static void SetEnvironmentDefaults(const EnvironmentDefaultList *envDefaults) { if (!envDefaults) { diff --git a/flang/runtime/unit.cpp b/flang/runtime/unit.cpp index 0e38cffdf907..3b42f45d5588 100644 --- a/flang/runtime/unit.cpp +++ b/flang/runtime/unit.cpp @@ -19,11 +19,13 @@ namespace Fortran::runtime::io { +#ifndef FLANG_RUNTIME_NO_GLOBAL_VAR_DEFS RT_OFFLOAD_VAR_GROUP_BEGIN RT_VAR_ATTRS ExternalFileUnit *defaultInput{nullptr}; // unit 5 RT_VAR_ATTRS ExternalFileUnit *defaultOutput{nullptr}; // unit 6 RT_VAR_ATTRS ExternalFileUnit *errorOutput{nullptr}; // unit 0 extension RT_OFFLOAD_VAR_GROUP_END +#endif // FLANG_RUNTIME_NO_GLOBAL_VAR_DEFS RT_OFFLOAD_API_GROUP_BEGIN diff --git a/flang/runtime/utf.cpp b/flang/runtime/utf.cpp index 9945dc6509ec..f4b38d5225ce 100644 --- a/flang/runtime/utf.cpp +++ b/flang/runtime/utf.cpp @@ -10,6 +10,7 @@ namespace Fortran::runtime { +#ifndef FLANG_RUNTIME_NO_GLOBAL_VAR_DEFS // clang-format off RT_OFFLOAD_VAR_GROUP_BEGIN const RT_CONST_VAR_ATTRS std::uint8_t UTF8FirstByteTable[256]{ @@ -40,6 +41,7 @@ const RT_CONST_VAR_ATTRS std::uint8_t UTF8FirstByteTable[256]{ }; RT_OFFLOAD_VAR_GROUP_END // clang-format on +#endif // FLANG_RUNTIME_NO_GLOBAL_VAR_DEFS RT_OFFLOAD_API_GROUP_BEGIN // Non-minimal encodings are accepted. -- GitLab From 11f4f458d985ba20aae58df1c3092655ec2310bd Mon Sep 17 00:00:00 2001 From: ChiaHungDuan Date: Mon, 29 Apr 2024 08:41:46 -0700 Subject: [PATCH 244/301] [scudo] Support setting default value of ReleaseToOsIntervalMs in config (#90256) --- compiler-rt/lib/scudo/standalone/allocator_config.def | 2 ++ compiler-rt/lib/scudo/standalone/combined.h | 3 +++ compiler-rt/lib/scudo/standalone/flags.inc | 2 +- compiler-rt/lib/scudo/standalone/primary32.h | 4 ++++ compiler-rt/lib/scudo/standalone/primary64.h | 3 +++ compiler-rt/lib/scudo/standalone/secondary.h | 3 +++ 6 files changed, 16 insertions(+), 1 deletion(-) diff --git a/compiler-rt/lib/scudo/standalone/allocator_config.def b/compiler-rt/lib/scudo/standalone/allocator_config.def index 9691a007eed5..dcd130ac449a 100644 --- a/compiler-rt/lib/scudo/standalone/allocator_config.def +++ b/compiler-rt/lib/scudo/standalone/allocator_config.def @@ -89,6 +89,7 @@ PRIMARY_REQUIRED(const s32, MaxReleaseToOsIntervalMs) // Indicates support for offsetting the start of a region by a random number of // pages. This is only used if `EnableContiguousRegions` is enabled. PRIMARY_OPTIONAL(const bool, EnableRandomOffset, false) +PRIMARY_OPTIONAL(const s32, DefaultReleaseToOsIntervalMs, INT32_MIN) // When `EnableContiguousRegions` is true, all regions will be be arranged in // adjacency. This will reduce the fragmentation caused by region allocations @@ -118,6 +119,7 @@ SECONDARY_CACHE_OPTIONAL(const u32, DefaultMaxEntriesCount, 0) SECONDARY_CACHE_OPTIONAL(const uptr, DefaultMaxEntrySize, 0) SECONDARY_CACHE_OPTIONAL(const s32, MinReleaseToOsIntervalMs, INT32_MIN) SECONDARY_CACHE_OPTIONAL(const s32, MaxReleaseToOsIntervalMs, INT32_MAX) +SECONDARY_CACHE_OPTIONAL(const s32, DefaultReleaseToOsIntervalMs, INT32_MIN) #undef SECONDARY_CACHE_OPTIONAL #undef SECONDARY_REQUIRED_TEMPLATE_TYPE diff --git a/compiler-rt/lib/scudo/standalone/combined.h b/compiler-rt/lib/scudo/standalone/combined.h index e7bc90cd0960..927513dea92d 100644 --- a/compiler-rt/lib/scudo/standalone/combined.h +++ b/compiler-rt/lib/scudo/standalone/combined.h @@ -173,6 +173,9 @@ public: static_cast(getFlags()->quarantine_max_chunk_size); Stats.init(); + // TODO(chiahungduan): Given that we support setting the default value in + // the PrimaryConfig and CacheConfig, consider to deprecate the use of + // `release_to_os_interval_ms` flag. const s32 ReleaseToOsIntervalMs = getFlags()->release_to_os_interval_ms; Primary.init(ReleaseToOsIntervalMs); Secondary.init(&Stats, ReleaseToOsIntervalMs); diff --git a/compiler-rt/lib/scudo/standalone/flags.inc b/compiler-rt/lib/scudo/standalone/flags.inc index f5a2bab5057a..ff0c28e1db7c 100644 --- a/compiler-rt/lib/scudo/standalone/flags.inc +++ b/compiler-rt/lib/scudo/standalone/flags.inc @@ -42,7 +42,7 @@ SCUDO_FLAG(bool, may_return_null, true, "returning NULL in otherwise non-fatal error scenarios, eg: OOM, " "invalid allocation alignments, etc.") -SCUDO_FLAG(int, release_to_os_interval_ms, SCUDO_ANDROID ? INT32_MIN : 5000, +SCUDO_FLAG(int, release_to_os_interval_ms, 5000, "Interval (in milliseconds) at which to attempt release of unused " "memory to the OS. Negative values disable the feature.") diff --git a/compiler-rt/lib/scudo/standalone/primary32.h b/compiler-rt/lib/scudo/standalone/primary32.h index 1d8a77b73e5c..ebfb8dfe0a31 100644 --- a/compiler-rt/lib/scudo/standalone/primary32.h +++ b/compiler-rt/lib/scudo/standalone/primary32.h @@ -88,6 +88,10 @@ public: Sci->MinRegionIndex = NumRegions; Sci->ReleaseInfo.LastReleaseAtNs = Time; } + + // The default value in the primary config has the higher priority. + if (Config::getDefaultReleaseToOsIntervalMs() != INT32_MIN) + ReleaseToOsInterval = Config::getDefaultReleaseToOsIntervalMs(); setOption(Option::ReleaseInterval, static_cast(ReleaseToOsInterval)); } diff --git a/compiler-rt/lib/scudo/standalone/primary64.h b/compiler-rt/lib/scudo/standalone/primary64.h index d6119051b162..bed2ccb8b992 100644 --- a/compiler-rt/lib/scudo/standalone/primary64.h +++ b/compiler-rt/lib/scudo/standalone/primary64.h @@ -147,6 +147,9 @@ public: for (uptr I = 0; I < NumClasses; I++) getRegionInfo(I)->FLLockCV.bindTestOnly(getRegionInfo(I)->FLLock); + // The default value in the primary config has the higher priority. + if (Config::getDefaultReleaseToOsIntervalMs() != INT32_MIN) + ReleaseToOsInterval = Config::getDefaultReleaseToOsIntervalMs(); setOption(Option::ReleaseInterval, static_cast(ReleaseToOsInterval)); } diff --git a/compiler-rt/lib/scudo/standalone/secondary.h b/compiler-rt/lib/scudo/standalone/secondary.h index 674af5071775..d8c9f5bcfcaf 100644 --- a/compiler-rt/lib/scudo/standalone/secondary.h +++ b/compiler-rt/lib/scudo/standalone/secondary.h @@ -209,6 +209,9 @@ public: static_cast(Config::getDefaultMaxEntriesCount())); setOption(Option::MaxCacheEntrySize, static_cast(Config::getDefaultMaxEntrySize())); + // The default value in the cache config has the higher priority. + if (Config::getDefaultReleaseToOsIntervalMs() != INT32_MIN) + ReleaseToOsInterval = Config::getDefaultReleaseToOsIntervalMs(); setOption(Option::ReleaseInterval, static_cast(ReleaseToOsInterval)); } -- GitLab From 6f02120ac4463e5e0cda25e2aafc485a4fe634ea Mon Sep 17 00:00:00 2001 From: David Spickett Date: Mon, 29 Apr 2024 16:51:09 +0100 Subject: [PATCH 245/301] [llvm][RISCV] Improve error message for invalid extension letters (#90468) Previously you got: clang: error: invalid arch name 'rv64v', first letter should be 'e', 'i' or 'g' Which to me, unfamiliar with riscv, reads as if I should have used "[eig]rv64v". Which is not what clang means. Include the first bit in the error message to make this clearer: clang: error: invalid arch name 'rv64v', first letter after 'rv64' should be 'e', 'i' or 'g' --- clang/test/Driver/riscv-arch.c | 6 +++--- llvm/lib/TargetParser/RISCVISAInfo.cpp | 3 ++- llvm/unittests/TargetParser/RISCVISAInfoTest.cpp | 10 +++++++--- 3 files changed, 12 insertions(+), 7 deletions(-) diff --git a/clang/test/Driver/riscv-arch.c b/clang/test/Driver/riscv-arch.c index 8399b4e97f86..abbe8612b378 100644 --- a/clang/test/Driver/riscv-arch.c +++ b/clang/test/Driver/riscv-arch.c @@ -209,7 +209,7 @@ // RUN: not %clang --target=riscv32-unknown-elf -march=rv32q -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-LETTER %s // RV32-LETTER: error: invalid arch name 'rv32q', -// RV32-LETTER: first letter should be 'e', 'i' or 'g' +// RV32-LETTER: first letter after 'rv32' should be 'e', 'i' or 'g' // RUN: not %clang --target=riscv32-unknown-elf -march=rv32imcq -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32-ORDER %s @@ -239,12 +239,12 @@ // RUN: not %clang --target=riscv32-unknown-elf -march=rv32xabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X %s // RV32X: error: invalid arch name 'rv32xabc', -// RV32X: first letter should be 'e', 'i' or 'g' +// RV32X: first letter after 'rv32' should be 'e', 'i' or 'g' // RUN: not %clang --target=riscv32-unknown-elf -march=rv32sabc -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32S %s // RV32S: error: invalid arch name 'rv32sabc', -// RV32S: first letter should be 'e', 'i' or 'g' +// RV32S: first letter after 'rv32' should be 'e', 'i' or 'g' // RUN: not %clang --target=riscv32-unknown-elf -march=rv32ix -### %s \ // RUN: -fsyntax-only 2>&1 | FileCheck -check-prefix=RV32X-NAME %s diff --git a/llvm/lib/TargetParser/RISCVISAInfo.cpp b/llvm/lib/TargetParser/RISCVISAInfo.cpp index 494dc76a1852..20182fb06037 100644 --- a/llvm/lib/TargetParser/RISCVISAInfo.cpp +++ b/llvm/lib/TargetParser/RISCVISAInfo.cpp @@ -639,7 +639,8 @@ RISCVISAInfo::parseArchString(StringRef Arch, bool EnableExperimentalExtension, switch (Baseline) { default: return createStringError(errc::invalid_argument, - "first letter should be 'e', 'i' or 'g'"); + "first letter after \'" + Arch.slice(0, 4) + + "\' should be 'e', 'i' or 'g'"); case 'e': case 'i': break; diff --git a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp index c945c4fbcf63..9f23000d733d 100644 --- a/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp +++ b/llvm/unittests/TargetParser/RISCVISAInfoTest.cpp @@ -120,10 +120,14 @@ TEST(ParseArchString, RejectsInvalidBaseISA) { EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), "string must begin with rv32{i,e,g} or rv64{i,e,g}"); } - for (StringRef Input : {"rv32j", "rv64k", "rv32_i"}) { + + for (StringRef Input : {"rv32j", "rv32_i"}) { EXPECT_EQ(toString(RISCVISAInfo::parseArchString(Input, true).takeError()), - "first letter should be 'e', 'i' or 'g'"); + "first letter after 'rv32' should be 'e', 'i' or 'g'"); } + + EXPECT_EQ(toString(RISCVISAInfo::parseArchString("rv64k", true).takeError()), + "first letter after 'rv64' should be 'e', 'i' or 'g'"); } TEST(ParseArchString, RejectsUnsupportedBaseISA) { @@ -395,7 +399,7 @@ TEST(ParseArchString, AcceptsAmbiguousFromRelaxExtensions) { TEST(ParseArchString, RejectsRelaxExtensionsNotStartWithEorIorG) { EXPECT_EQ( toString(RISCVISAInfo::parseArchString("rv32zba_im", true).takeError()), - "first letter should be 'e', 'i' or 'g'"); + "first letter after 'rv32' should be 'e', 'i' or 'g'"); } TEST(ParseArchString, -- GitLab From 1e174a7656f943fa2cad2489a226c90e03ca29ac Mon Sep 17 00:00:00 2001 From: Kai Nacke Date: Mon, 29 Apr 2024 12:06:26 -0400 Subject: [PATCH 246/301] [TableGen][GISel] Handle frameindex/tframeindex (#90475) Support patterns like Pat<(p0 frameindex:$fi), (ADD tframeindex:$fi, 0)>; in the GlobalISel emitter in TableGen. Currently, using such a pattern results in an error message. --- .../TableGen/GlobalISelEmitter-frameindex.td | 29 +++++++++++++++++++ llvm/utils/TableGen/GlobalISelEmitter.cpp | 9 ++++++ 2 files changed, 38 insertions(+) create mode 100644 llvm/test/TableGen/GlobalISelEmitter-frameindex.td diff --git a/llvm/test/TableGen/GlobalISelEmitter-frameindex.td b/llvm/test/TableGen/GlobalISelEmitter-frameindex.td new file mode 100644 index 000000000000..232691465bb3 --- /dev/null +++ b/llvm/test/TableGen/GlobalISelEmitter-frameindex.td @@ -0,0 +1,29 @@ +// RUN: llvm-tblgen -gen-global-isel -optimize-match-table=false -I %p/../../include -I %p/Common %s -o - < %s | FileCheck %s + +include "llvm/Target/Target.td" +include "GlobalISelEmitterCommon.td" + +def ADD : I<(outs GPR32:$dst), (ins GPR32:$src1, GPR32:$src2), []>; + +//===- Test a simple pattern with frame index operands. ----------------------===// +// +// CHECK: GIM_Try, /*On fail goto*//*Label [[LABEL_NUM:[0-9]+]]*/ GIMT_Encode4([[LABEL:[0-9]+]]), +// CHECK-NEXT: GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, +// CHECK-NEXT: GIM_CheckOpcode, /*MI*/0, GIMT_Encode2(TargetOpcode::G_FRAME_INDEX), +// CHECK-NEXT: // MIs[0] DstI[dst] +// CHECK-NEXT: GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s32, +// CHECK-NEXT: GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(MyTarget::GPR32RegClassID), +// CHECK-NEXT: // MIs[0] fi +// CHECK-NEXT: // No operand predicates +// CHECK-NEXT: // (frameindex:{ *:[i32] }):$fi => (ADD:{ *:[i32] } (tframeindex:{ *:[i32] }):$fi, 0:{ *:[i32] }) +// CHECK-NEXT: GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(MyTarget::ADD), +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] +// CHECK-NEXT: GIR_RootToRootCopy, /*OpIdx*/1, // fi +// CHECK-NEXT: GIR_AddImm8, /*InsnID*/0, /*Imm*/0, +// CHECK-NEXT: GIR_RootConstrainSelectedInstOperands, +// CHECK-NEXT: // GIR_Coverage, 0, +// CHECK-NEXT: GIR_EraseRootFromParent_Done, +// CHECK-NEXT: // Label [[LABEL_NUM]]: @[[LABEL]] +// CHECK-NEXT: GIM_Reject, + +def : Pat<(p0 frameindex:$fi), (ADD tframeindex:$fi, 0)>; diff --git a/llvm/utils/TableGen/GlobalISelEmitter.cpp b/llvm/utils/TableGen/GlobalISelEmitter.cpp index 78abf80e7aec..0eb258ff89a2 100644 --- a/llvm/utils/TableGen/GlobalISelEmitter.cpp +++ b/llvm/utils/TableGen/GlobalISelEmitter.cpp @@ -834,6 +834,11 @@ Expected GlobalISelEmitter::createAndImportSelDAGMatcher( return InsnMatcher; } + if (SrcGIOrNull->TheDef->getName() == "G_FRAME_INDEX") { + InsnMatcher.addOperand(OpIdx++, Src.getName(), TempOpIdx); + return InsnMatcher; + } + // Special case because the operand order is changed from setcc. The // predicate operand needs to be swapped from the last operand to the first // source. @@ -1223,6 +1228,10 @@ Expected GlobalISelEmitter::importExplicitUseRenderer( if (DstChild.getOperator()->getName() == "timm") { DstMIBuilder.addRenderer(DstChild.getName()); return InsertPt; + } + if (DstChild.getOperator()->getName() == "tframeindex") { + DstMIBuilder.addRenderer(DstChild.getName()); + return InsertPt; } else if (DstChild.getOperator()->getName() == "imm") { DstMIBuilder.addRenderer(DstChild.getName()); return InsertPt; -- GitLab From df6d2faa22bf19fb27b5c083e590d13024a8d7cd Mon Sep 17 00:00:00 2001 From: Amir Ayupov Date: Mon, 29 Apr 2024 18:07:26 +0200 Subject: [PATCH 247/301] [Object] Provide operator< for ELFSymbolRef (#89861) Normally, operator< accepting DataRefImpl is used when comparing SymbolRef/ELFSymbolRef. However, it uses std::memcmp which interprets DataRefImpl union as char string so that the result depends on host endianness. For ELFSymbolRef a specialized operator< can be used instead to produce consistent ordering regardless of endianness by comparing the symbol table index and symbol index fields separately. --- llvm/include/llvm/Object/ELFObjectFile.h | 8 ++++ llvm/unittests/Object/ELFObjectFileTest.cpp | 43 +++++++++++++++++++++ 2 files changed, 51 insertions(+) diff --git a/llvm/include/llvm/Object/ELFObjectFile.h b/llvm/include/llvm/Object/ELFObjectFile.h index 4494d9b96189..8cc09e7fd7d5 100644 --- a/llvm/include/llvm/Object/ELFObjectFile.h +++ b/llvm/include/llvm/Object/ELFObjectFile.h @@ -199,6 +199,14 @@ public: } }; +inline bool operator<(const ELFSymbolRef &A, const ELFSymbolRef &B) { + const DataRefImpl &DRIA = A.getRawDataRefImpl(); + const DataRefImpl &DRIB = B.getRawDataRefImpl(); + if (DRIA.d.a == DRIB.d.a) + return DRIA.d.b < DRIB.d.b; + return DRIA.d.a < DRIB.d.a; +} + class elf_symbol_iterator : public symbol_iterator { public: elf_symbol_iterator(const basic_symbol_iterator &B) diff --git a/llvm/unittests/Object/ELFObjectFileTest.cpp b/llvm/unittests/Object/ELFObjectFileTest.cpp index c4d2b4ae8b9a..c13dc0e3fab8 100644 --- a/llvm/unittests/Object/ELFObjectFileTest.cpp +++ b/llvm/unittests/Object/ELFObjectFileTest.cpp @@ -1504,3 +1504,46 @@ Sections: "SHT_RELA section with index 1: failed to get a " "relocated section: invalid section index: 255"); } + +TEST(ELFObjectFileTest, ELFSymbolRefLess) { + SmallString<0> Storage; + Expected> ElfOrErr = toBinary(Storage, R"( +--- !ELF +FileHeader: + Class: ELFCLASS64 + Data: ELFDATA2LSB + Type: ET_DYN + Machine: EM_X86_64 +)"); + + ASSERT_THAT_EXPECTED(ElfOrErr, Succeeded()); + const ELFObjectFile &Obj = *ElfOrErr; + + const uint32_t ValLow = 0x00000001; + const uint32_t ValHigh = 0x00000100; + + auto MakeSymbol = [&Obj](size_t SymtabIndex, size_t SymbolIndex) { + DataRefImpl Data; + Data.d.a = SymtabIndex; + Data.d.b = SymbolIndex; + SymbolRef Sym(Data, &Obj); + return ELFSymbolRef(Sym); + }; + + ELFSymbolRef ELFSymLowLow = MakeSymbol(ValLow, ValLow); + ELFSymbolRef ELFSymLowHigh = MakeSymbol(ValLow, ValHigh); + ELFSymbolRef ELFSymHighLow = MakeSymbol(ValHigh, ValLow); + ELFSymbolRef ELFSymHighHigh = MakeSymbol(ValHigh, ValHigh); + + EXPECT_TRUE(ELFSymLowLow < ELFSymLowHigh); + EXPECT_FALSE(ELFSymLowHigh < ELFSymLowLow); + EXPECT_FALSE(ELFSymLowLow < ELFSymLowLow); + + EXPECT_TRUE(ELFSymLowLow < ELFSymHighHigh); + EXPECT_TRUE(ELFSymLowHigh < ELFSymHighLow); + EXPECT_TRUE(ELFSymLowLow < ELFSymHighLow); + + EXPECT_FALSE(ELFSymHighLow < ELFSymLowHigh); + EXPECT_FALSE(ELFSymHighHigh < ELFSymLowLow); + EXPECT_FALSE(ELFSymHighLow < ELFSymLowLow); +} -- GitLab From 2903df02fb3c057849aaa796a91289b01950a5f0 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Pol=20Marcet=20Sard=C3=A0?= Date: Mon, 29 Apr 2024 08:59:02 -0700 Subject: [PATCH 248/301] Squashed commit of the following: MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit commit 8d41d93e3fceb3f3af77266f5a8388fc585150a5 Author: Pol Marcet Sardà Date: Sat Apr 20 12:19:49 2024 +0200 Address some misc comments; added a diagnostic and expanded macros in testing. commit 9493c0f290b558947d8b3ae8e1adf909b0fb9dcd Author: Pol Marcet Sardà Date: Sun Mar 31 18:18:45 2024 +0200 Following the review of sethp, I have made the following changes: -- Added diagnostic for the undefined shuffle of -1 -- Validated support for _BitInt -- A bunch of other minnor tweaks here and there commit 8273abc8d56ef8225cf4dba84f66a1e54a2ef036 Author: Pol Marcet Sardà Date: Thu Jan 4 12:31:08 2024 +0100 Fix typo in file name commit ff68f23921966c7d9605f91a47d6b481bf1d7a7b Author: Pol Marcet Sardà Date: Thu Jan 4 11:26:08 2024 +0100 Address suggestions from RKSimon commit c14783de45687c754253c0cbf8a7834c7f986d80 Author: Pol Marcet Sardà Date: Sat Dec 30 13:59:00 2023 +0100 [clang] Constexpr for __builtin_shufflevector and __builtin_convertvector Summary: This patch adds constexpr support for __builtin_shufflevector and __builtin_convertvector. A small oddity encountered was that the arg to the intrinsics may be an lvalue without any sort of implicit cast of any kind. I solved this through the EvaluateVectorOrLValue function, which treats the lvalue as if it was in an rvalue cast, which gets me the desired vector. Co-Authored-By: Seth Pellegrino --- clang/docs/LanguageExtensions.rst | 8 +- clang/docs/ReleaseNotes.rst | 3 + .../clang/Basic/DiagnosticSemaKinds.td | 4 + clang/lib/AST/ExprConstant.cpp | 127 ++- clang/test/Sema/constant_builtins_vector.cpp | 723 ++++++++++++++++++ clang/test/Sema/convertvector.c | 3 + 6 files changed, 863 insertions(+), 5 deletions(-) create mode 100644 clang/test/Sema/constant_builtins_vector.cpp diff --git a/clang/docs/LanguageExtensions.rst b/clang/docs/LanguageExtensions.rst index 87cb743856b0..c2e90f4e7d58 100644 --- a/clang/docs/LanguageExtensions.rst +++ b/clang/docs/LanguageExtensions.rst @@ -2931,7 +2931,7 @@ Query for this feature with ``__has_builtin(__builtin_dump_struct)`` ``__builtin_shufflevector`` is used to express generic vector permutation/shuffle/swizzle operations. This builtin is also very important for the implementation of various target-specific header files like -````. +````. This builtin can be used within constant expressions. **Syntax**: @@ -2958,7 +2958,7 @@ for the implementation of various target-specific header files like // Concatenate every other element of 8-element vectors V1 and V2. __builtin_shufflevector(V1, V2, 0, 2, 4, 6, 8, 10, 12, 14) - // Shuffle v1 with some elements being undefined + // Shuffle v1 with some elements being undefined. Not allowed in constexpr. __builtin_shufflevector(v1, v1, 3, -1, 1, -1) **Description**: @@ -2971,6 +2971,7 @@ starting with the first vector, continuing into the second vector. Thus, if ``vec1`` is a 4-element vector, index 5 would refer to the second element of ``vec2``. An index of -1 can be used to indicate that the corresponding element in the returned vector is a don't care and can be optimized by the backend. +Values of -1 are not supported in constant expressions. The result of ``__builtin_shufflevector`` is a vector with the same element type as ``vec1``/``vec2`` but that has an element count equal to the number of @@ -2985,7 +2986,8 @@ Query for this feature with ``__has_builtin(__builtin_shufflevector)``. ``__builtin_convertvector`` is used to express generic vector type-conversion operations. The input vector and the output vector -type must have the same number of elements. +type must have the same number of elements. This builtin can be used within +constant expressions. **Syntax**: diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 4cb2462ae649..2d0e663d93e4 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -233,6 +233,9 @@ Non-comprehensive list of changes in this release * ``-fdenormal-fp-math=preserve-sign`` is no longer implied by ``-ffast-math`` on x86 systems. +- Builtins ``__builtin_shufflevector()`` and ``__builtin_convertvector()`` may + now be used within constant expressions. + New Compiler Flags ------------------ - ``-fsanitize=implicit-bitfield-conversion`` checks implicit truncation and diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 8486fa3a02e8..502c771a2d67 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -10330,9 +10330,13 @@ def err_shufflevector_nonconstant_argument : Error< def err_shufflevector_argument_too_large : Error< "index for __builtin_shufflevector must be less than the total number " "of vector elements">; +def err_shufflevector_minus_one_is_undefined_behavior_constexpr : Error< + "index for __builtin_shufflevector not within the bounds of the input vectors; index of -1 found at position %0 not permitted in a constexpr context.">; def err_convertvector_non_vector : Error< "first argument to __builtin_convertvector must be a vector">; +def err_convertvector_constexpr_unsupported_vector_cast : Error< + "unsupported vector cast from %0 to %1 in a constant expression.">; def err_builtin_non_vector_type : Error< "%0 argument to %1 must be of vector type">; def err_convertvector_incompatible_vector : Error< diff --git a/clang/lib/AST/ExprConstant.cpp b/clang/lib/AST/ExprConstant.cpp index 71b5f91b4d25..f1aa19e4409e 100644 --- a/clang/lib/AST/ExprConstant.cpp +++ b/clang/lib/AST/ExprConstant.cpp @@ -2706,7 +2706,11 @@ static bool checkFloatingPointResult(EvalInfo &Info, const Expr *E, static bool HandleFloatToFloatCast(EvalInfo &Info, const Expr *E, QualType SrcType, QualType DestType, APFloat &Result) { - assert(isa(E) || isa(E)); + assert((isa(E) || isa(E) || + isa(E)) && + "HandleFloatToFloatCast has been checked with only CastExpr, " + "CompoundAssignOperator and ConvertVectorExpr. Please either validate " + "the new expression or address the root cause of this usage."); llvm::RoundingMode RM = getActiveRoundingMode(Info, E); APFloat::opStatus St; APFloat Value = Result; @@ -10710,8 +10714,11 @@ namespace { bool VisitUnaryImag(const UnaryOperator *E); bool VisitBinaryOperator(const BinaryOperator *E); bool VisitUnaryOperator(const UnaryOperator *E); + bool VisitConvertVectorExpr(const ConvertVectorExpr *E); + bool VisitShuffleVectorExpr(const ShuffleVectorExpr *E); + // FIXME: Missing: conditional operator (for GNU - // conditional select), shufflevector, ExtVectorElementExpr + // conditional select), ExtVectorElementExpr }; } // end anonymous namespace @@ -10962,6 +10969,122 @@ bool VectorExprEvaluator::VisitUnaryOperator(const UnaryOperator *E) { return Success(APValue(ResultElements.data(), ResultElements.size()), E); } +static bool handleVectorElementCast(EvalInfo &Info, const FPOptions FPO, + const Expr *E, QualType SourceTy, + QualType DestTy, APValue const &Original, + APValue &Result) { + if (SourceTy->isIntegerType()) { + if (DestTy->isRealFloatingType()) { + Result = APValue(APFloat(0.0)); + return HandleIntToFloatCast(Info, E, FPO, SourceTy, Original.getInt(), + DestTy, Result.getFloat()); + } + if (DestTy->isIntegerType()) { + Result = APValue( + HandleIntToIntCast(Info, E, DestTy, SourceTy, Original.getInt())); + return true; + } + } else if (SourceTy->isRealFloatingType()) { + if (DestTy->isRealFloatingType()) { + Result = Original; + return HandleFloatToFloatCast(Info, E, SourceTy, DestTy, + Result.getFloat()); + } + if (DestTy->isIntegerType()) { + Result = APValue(APSInt()); + return HandleFloatToIntCast(Info, E, SourceTy, Original.getFloat(), + DestTy, Result.getInt()); + } + } + + Info.FFDiag(E, diag::err_convertvector_constexpr_unsupported_vector_cast) + << SourceTy << DestTy; + return false; +} + +bool VectorExprEvaluator::VisitConvertVectorExpr(const ConvertVectorExpr *E) { + APValue Source; + QualType SourceVecType = E->getSrcExpr()->getType(); + if (!EvaluateAsRValue(Info, E->getSrcExpr(), Source)) + return false; + + QualType DestTy = E->getType()->castAs()->getElementType(); + QualType SourceTy = SourceVecType->castAs()->getElementType(); + + const FPOptions FPO = E->getFPFeaturesInEffect(Info.Ctx.getLangOpts()); + + auto SourceLen = Source.getVectorLength(); + SmallVector ResultElements; + ResultElements.reserve(SourceLen); + for (unsigned EltNum = 0; EltNum < SourceLen; ++EltNum) { + APValue Elt; + if (!handleVectorElementCast(Info, FPO, E, SourceTy, DestTy, + Source.getVectorElt(EltNum), Elt)) + return false; + ResultElements.push_back(std::move(Elt)); + } + + return Success(APValue(ResultElements.data(), ResultElements.size()), E); +} + +static bool handleVectorShuffle(EvalInfo &Info, const ShuffleVectorExpr *E, + QualType ElemType, APValue const &VecVal1, + APValue const &VecVal2, unsigned EltNum, + APValue &Result) { + unsigned const TotalElementsInInputVector1 = VecVal1.getVectorLength(); + unsigned const TotalElementsInInputVector2 = VecVal2.getVectorLength(); + + APSInt IndexVal = E->getShuffleMaskIdx(Info.Ctx, EltNum); + int64_t index = IndexVal.getExtValue(); + // The spec says that -1 should be treated as undef for optimizations, + // but in constexpr we'd have to produce an APValue::Indeterminate, + // which is prohibited from being a top-level constant value. Emit a + // diagnostic instead. + if (index == -1) { + Info.FFDiag( + E, diag::err_shufflevector_minus_one_is_undefined_behavior_constexpr) + << EltNum; + return false; + } + + if (index < 0 || + index >= TotalElementsInInputVector1 + TotalElementsInInputVector2) + llvm_unreachable("Out of bounds shuffle index"); + + if (index >= TotalElementsInInputVector1) + Result = VecVal2.getVectorElt(index - TotalElementsInInputVector1); + else + Result = VecVal1.getVectorElt(index); + return true; +} + +bool VectorExprEvaluator::VisitShuffleVectorExpr(const ShuffleVectorExpr *E) { + APValue VecVal1; + const Expr *Vec1 = E->getExpr(0); + if (!EvaluateAsRValue(Info, Vec1, VecVal1)) + return false; + APValue VecVal2; + const Expr *Vec2 = E->getExpr(1); + if (!EvaluateAsRValue(Info, Vec2, VecVal2)) + return false; + + VectorType const *DestVecTy = E->getType()->castAs(); + QualType DestElTy = DestVecTy->getElementType(); + + auto TotalElementsInOutputVector = DestVecTy->getNumElements(); + + SmallVector ResultElements; + ResultElements.reserve(TotalElementsInOutputVector); + for (unsigned EltNum = 0; EltNum < TotalElementsInOutputVector; ++EltNum) { + APValue Elt; + if (!handleVectorShuffle(Info, E, DestElTy, VecVal1, VecVal2, EltNum, Elt)) + return false; + ResultElements.push_back(std::move(Elt)); + } + + return Success(APValue(ResultElements.data(), ResultElements.size()), E); +} + //===----------------------------------------------------------------------===// // Array Evaluation //===----------------------------------------------------------------------===// diff --git a/clang/test/Sema/constant_builtins_vector.cpp b/clang/test/Sema/constant_builtins_vector.cpp new file mode 100644 index 000000000000..68620d436fc4 --- /dev/null +++ b/clang/test/Sema/constant_builtins_vector.cpp @@ -0,0 +1,723 @@ +// RUN: %clang_cc1 -verify -std=c++2a -fsyntax-only -Wno-bit-int-extension %s + +#if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ +#define LITTLE_END 1 +#elif __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__ +#define LITTLE_END 0 +#else +#error "huh?" +#endif + +// We also support _BitInt as long as it is >=8 and a power of 2. +typedef _BitInt(8) BitInt8; +typedef _BitInt(32) BitInt32; +typedef _BitInt(128) BitInt128; + +typedef double vector4double __attribute__((__vector_size__(32))); +typedef float vector4float __attribute__((__vector_size__(16))); +typedef long long vector4long __attribute__((__vector_size__(32))); +typedef int vector4int __attribute__((__vector_size__(16))); +typedef short vector4short __attribute__((__vector_size__(8))); +typedef char vector4char __attribute__((__vector_size__(4))); +typedef BitInt8 vector4BitInt8 __attribute__((__vector_size__(4))); +typedef BitInt32 vector4BitInt32 __attribute__((__vector_size__(16))); +typedef BitInt128 vector4BitInt128 __attribute__((__vector_size__(64))); +typedef double vector8double __attribute__((__vector_size__(64))); +typedef float vector8float __attribute__((__vector_size__(32))); +typedef long long vector8long __attribute__((__vector_size__(64))); +typedef int vector8int __attribute__((__vector_size__(32))); +typedef short vector8short __attribute__((__vector_size__(16))); +typedef char vector8char __attribute__((__vector_size__(8))); +typedef BitInt8 vector8BitInt8 __attribute__((__vector_size__(8))); +typedef BitInt32 vector8BitInt32 __attribute__((__vector_size__(32))); +typedef BitInt128 vector8BitInt128 __attribute__((__vector_size__(128))); + +#define CHECK_NUM(__size, __typeFrom, __typeTo, ...) \ + constexpr vector##__size##__typeTo \ + from_##vector##__size##__typeFrom##_to_##vector##__size##__typeTo##_var = \ + __builtin_convertvector((vector##__size##__typeFrom){__VA_ARGS__}, \ + vector##__size##__typeTo); +#define CHECK_TO_ALL_TYPES(__size, __typeFrom, ...) \ + CHECK_NUM(__size, __typeFrom, double, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, float, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, long, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, int, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, short, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, char, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, BitInt8, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, BitInt32, __VA_ARGS__) \ + CHECK_NUM(__size, __typeFrom, BitInt128, __VA_ARGS__) \ + static_assert( \ + __builtin_bit_cast( \ + unsigned, \ + __builtin_shufflevector( \ + from_vector##__size##__typeFrom##_to_vector##__size##char_var, \ + from_vector##__size##__typeFrom##_to_vector##__size##char_var, \ + 0, 1, 2, 3)) == (LITTLE_END ? 0x03020100 : 0x00010203)); \ + static_assert( \ + __builtin_bit_cast( \ + unsigned long long, \ + __builtin_shufflevector( \ + from_vector##__size##__typeFrom##_to_vector##__size##short_var, \ + from_vector##__size##__typeFrom##_to_vector##__size##short_var, \ + 0, 1, 2, 3)) == \ + (LITTLE_END ? 0x0003000200010000 : 0x0000000100020003)); + +#define CHECK_ALL_COMBINATIONS(__size, ...) \ + CHECK_TO_ALL_TYPES(__size, double, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, float, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, long, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, int, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, short, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, char, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, BitInt8, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, BitInt32, __VA_ARGS__) \ + CHECK_TO_ALL_TYPES(__size, BitInt128, __VA_ARGS__) + +// The result below is expanded from these macros. Use them to autogenerate the +// test cases below. +// CHECK_ALL_COMBINATIONS(4, 0, 1, 2, 3); +// CHECK_ALL_COMBINATIONS(8, 0, 1, 2, 3, 4, 5, 6, 7); + +constexpr vector4double from_vector4double_to_vector4double_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4double_to_vector4float_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4double_to_vector4long_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4double_to_vector4int_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4double_to_vector4short_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4double_to_vector4char_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4double_to_vector4BitInt8_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4double_to_vector4BitInt32_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4double_to_vector4BitInt128_var = + __builtin_convertvector((vector4double){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast( + unsigned, + __builtin_shufflevector(from_vector4double_to_vector4char_var, + from_vector4double_to_vector4char_var, + 0, 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector4double_to_vector4short_var, + from_vector4double_to_vector4short_var, 0, + 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4float_to_vector4double_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4float_to_vector4float_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4float_to_vector4long_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4float_to_vector4int_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4float_to_vector4short_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4float_to_vector4char_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4float_to_vector4BitInt8_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4float_to_vector4BitInt32_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4float_to_vector4BitInt128_var = + __builtin_convertvector((vector4float){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4float_to_vector4char_var, + from_vector4float_to_vector4char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector4float_to_vector4short_var, + from_vector4float_to_vector4short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4long_to_vector4double_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4long_to_vector4float_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4long_to_vector4long_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4long_to_vector4int_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4long_to_vector4short_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4long_to_vector4char_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4long_to_vector4BitInt8_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4long_to_vector4BitInt32_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4long_to_vector4BitInt128_var = + __builtin_convertvector((vector4long){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4long_to_vector4char_var, + from_vector4long_to_vector4char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector4long_to_vector4short_var, + from_vector4long_to_vector4short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4int_to_vector4double_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4int_to_vector4float_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4int_to_vector4long_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4int_to_vector4int_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4int_to_vector4short_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4int_to_vector4char_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4int_to_vector4BitInt8_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4int_to_vector4BitInt32_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4int_to_vector4BitInt128_var = + __builtin_convertvector((vector4int){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4int_to_vector4char_var, + from_vector4int_to_vector4char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector4int_to_vector4short_var, + from_vector4int_to_vector4short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4short_to_vector4double_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4short_to_vector4float_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4short_to_vector4long_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4short_to_vector4int_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4short_to_vector4short_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4short_to_vector4char_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4short_to_vector4BitInt8_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4short_to_vector4BitInt32_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4short_to_vector4BitInt128_var = + __builtin_convertvector((vector4short){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4short_to_vector4char_var, + from_vector4short_to_vector4char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector4short_to_vector4short_var, + from_vector4short_to_vector4short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4char_to_vector4double_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4char_to_vector4float_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4char_to_vector4long_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4char_to_vector4int_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4char_to_vector4short_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4char_to_vector4char_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4char_to_vector4BitInt8_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4char_to_vector4BitInt32_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4char_to_vector4BitInt128_var = + __builtin_convertvector((vector4char){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4char_to_vector4char_var, + from_vector4char_to_vector4char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector4char_to_vector4short_var, + from_vector4char_to_vector4short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4BitInt8_to_vector4double_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4BitInt8_to_vector4float_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4BitInt8_to_vector4long_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4BitInt8_to_vector4int_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4BitInt8_to_vector4short_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4BitInt8_to_vector4char_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4BitInt8_to_vector4BitInt8_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4BitInt8_to_vector4BitInt32_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4BitInt8_to_vector4BitInt128_var = + __builtin_convertvector((vector4BitInt8){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4BitInt8_to_vector4char_var, + from_vector4BitInt8_to_vector4char_var, 0, + 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector4BitInt8_to_vector4short_var, + from_vector4BitInt8_to_vector4short_var, 0, + 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4BitInt32_to_vector4double_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4BitInt32_to_vector4float_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4BitInt32_to_vector4long_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4BitInt32_to_vector4int_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4BitInt32_to_vector4short_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4BitInt32_to_vector4char_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4BitInt32_to_vector4BitInt8_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4BitInt32_to_vector4BitInt32_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4BitInt32_to_vector4BitInt128_var = + __builtin_convertvector((vector4BitInt32){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4BitInt32_to_vector4char_var, + from_vector4BitInt32_to_vector4char_var, 0, + 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector4BitInt32_to_vector4short_var, + from_vector4BitInt32_to_vector4short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector4double from_vector4BitInt128_to_vector4double_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4double); +constexpr vector4float from_vector4BitInt128_to_vector4float_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4float); +constexpr vector4long from_vector4BitInt128_to_vector4long_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4long); +constexpr vector4int from_vector4BitInt128_to_vector4int_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4int); +constexpr vector4short from_vector4BitInt128_to_vector4short_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4short); +constexpr vector4char from_vector4BitInt128_to_vector4char_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4char); +constexpr vector4BitInt8 from_vector4BitInt128_to_vector4BitInt8_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4BitInt8); +constexpr vector4BitInt32 from_vector4BitInt128_to_vector4BitInt32_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4BitInt32); +constexpr vector4BitInt128 from_vector4BitInt128_to_vector4BitInt128_var = + __builtin_convertvector((vector4BitInt128){0, 1, 2, 3}, vector4BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector4BitInt128_to_vector4char_var, + from_vector4BitInt128_to_vector4char_var, + 0, 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector4BitInt128_to_vector4short_var, + from_vector4BitInt128_to_vector4short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +; +constexpr vector8double from_vector8double_to_vector8double_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8double_to_vector8float_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8double_to_vector8long_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8long); +constexpr vector8int from_vector8double_to_vector8int_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8int); +constexpr vector8short from_vector8double_to_vector8short_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8double_to_vector8char_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8char); +constexpr vector8BitInt8 from_vector8double_to_vector8BitInt8_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8double_to_vector8BitInt32_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8double_to_vector8BitInt128_var = + __builtin_convertvector((vector8double){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast( + unsigned, + __builtin_shufflevector(from_vector8double_to_vector8char_var, + from_vector8double_to_vector8char_var, + 0, 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector8double_to_vector8short_var, + from_vector8double_to_vector8short_var, 0, + 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8float_to_vector8double_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8float_to_vector8float_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8float_to_vector8long_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8long); +constexpr vector8int from_vector8float_to_vector8int_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, vector8int); +constexpr vector8short from_vector8float_to_vector8short_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8float_to_vector8char_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8char); +constexpr vector8BitInt8 from_vector8float_to_vector8BitInt8_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8float_to_vector8BitInt32_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8float_to_vector8BitInt128_var = + __builtin_convertvector((vector8float){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8float_to_vector8char_var, + from_vector8float_to_vector8char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector8float_to_vector8short_var, + from_vector8float_to_vector8short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8long_to_vector8double_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8long_to_vector8float_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8long_to_vector8long_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, vector8long); +constexpr vector8int from_vector8long_to_vector8int_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, vector8int); +constexpr vector8short from_vector8long_to_vector8short_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8long_to_vector8char_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, vector8char); +constexpr vector8BitInt8 from_vector8long_to_vector8BitInt8_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8long_to_vector8BitInt32_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8long_to_vector8BitInt128_var = + __builtin_convertvector((vector8long){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8long_to_vector8char_var, + from_vector8long_to_vector8char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector8long_to_vector8short_var, + from_vector8long_to_vector8short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8int_to_vector8double_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8int_to_vector8float_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, vector8float); +constexpr vector8long from_vector8int_to_vector8long_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, vector8long); +constexpr vector8int from_vector8int_to_vector8int_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, vector8int); +constexpr vector8short from_vector8int_to_vector8short_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, vector8short); +constexpr vector8char from_vector8int_to_vector8char_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, vector8char); +constexpr vector8BitInt8 from_vector8int_to_vector8BitInt8_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8int_to_vector8BitInt32_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8int_to_vector8BitInt128_var = + __builtin_convertvector((vector8int){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8int_to_vector8char_var, + from_vector8int_to_vector8char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector8int_to_vector8short_var, + from_vector8int_to_vector8short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8short_to_vector8double_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8short_to_vector8float_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8short_to_vector8long_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8long); +constexpr vector8int from_vector8short_to_vector8int_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, vector8int); +constexpr vector8short from_vector8short_to_vector8short_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8short_to_vector8char_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8char); +constexpr vector8BitInt8 from_vector8short_to_vector8BitInt8_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8short_to_vector8BitInt32_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8short_to_vector8BitInt128_var = + __builtin_convertvector((vector8short){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8short_to_vector8char_var, + from_vector8short_to_vector8char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector8short_to_vector8short_var, + from_vector8short_to_vector8short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8char_to_vector8double_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8char_to_vector8float_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8char_to_vector8long_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, vector8long); +constexpr vector8int from_vector8char_to_vector8int_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, vector8int); +constexpr vector8short from_vector8char_to_vector8short_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8char_to_vector8char_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, vector8char); +constexpr vector8BitInt8 from_vector8char_to_vector8BitInt8_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8char_to_vector8BitInt32_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8char_to_vector8BitInt128_var = + __builtin_convertvector((vector8char){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8char_to_vector8char_var, + from_vector8char_to_vector8char_var, 0, 1, + 2, 3)) == (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast( + unsigned long long, + __builtin_shufflevector(from_vector8char_to_vector8short_var, + from_vector8char_to_vector8short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8BitInt8_to_vector8double_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8BitInt8_to_vector8float_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8BitInt8_to_vector8long_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8long); +constexpr vector8int from_vector8BitInt8_to_vector8int_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8int); +constexpr vector8short from_vector8BitInt8_to_vector8short_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8BitInt8_to_vector8char_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8char); +constexpr vector8BitInt8 from_vector8BitInt8_to_vector8BitInt8_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8BitInt8_to_vector8BitInt32_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8BitInt8_to_vector8BitInt128_var = + __builtin_convertvector((vector8BitInt8){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8BitInt8_to_vector8char_var, + from_vector8BitInt8_to_vector8char_var, 0, + 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector8BitInt8_to_vector8short_var, + from_vector8BitInt8_to_vector8short_var, 0, + 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8BitInt32_to_vector8double_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8BitInt32_to_vector8float_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8BitInt32_to_vector8long_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8long); +constexpr vector8int from_vector8BitInt32_to_vector8int_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8int); +constexpr vector8short from_vector8BitInt32_to_vector8short_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8BitInt32_to_vector8char_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8char); +constexpr vector8BitInt8 from_vector8BitInt32_to_vector8BitInt8_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8BitInt32_to_vector8BitInt32_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8BitInt32_to_vector8BitInt128_var = + __builtin_convertvector((vector8BitInt32){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8BitInt32_to_vector8char_var, + from_vector8BitInt32_to_vector8char_var, 0, + 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector8BitInt32_to_vector8short_var, + from_vector8BitInt32_to_vector8short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +constexpr vector8double from_vector8BitInt128_to_vector8double_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8double); +constexpr vector8float from_vector8BitInt128_to_vector8float_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8float); +constexpr vector8long from_vector8BitInt128_to_vector8long_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8long); +constexpr vector8int from_vector8BitInt128_to_vector8int_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8int); +constexpr vector8short from_vector8BitInt128_to_vector8short_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8short); +constexpr vector8char from_vector8BitInt128_to_vector8char_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8char); +constexpr vector8BitInt8 from_vector8BitInt128_to_vector8BitInt8_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt8); +constexpr vector8BitInt32 from_vector8BitInt128_to_vector8BitInt32_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt32); +constexpr vector8BitInt128 from_vector8BitInt128_to_vector8BitInt128_var = + __builtin_convertvector((vector8BitInt128){0, 1, 2, 3, 4, 5, 6, 7}, + vector8BitInt128); +static_assert(__builtin_bit_cast(unsigned, + __builtin_shufflevector( + from_vector8BitInt128_to_vector8char_var, + from_vector8BitInt128_to_vector8char_var, + 0, 1, 2, 3)) == + (1 ? 0x03020100 : 0x00010203)); +static_assert(__builtin_bit_cast(unsigned long long, + __builtin_shufflevector( + from_vector8BitInt128_to_vector8short_var, + from_vector8BitInt128_to_vector8short_var, + 0, 1, 2, 3)) == + (1 ? 0x0003000200010000 : 0x0000000100020003)); +; +#undef CHECK_ALL_COMBINATIONS +#undef CHECK_TO_ALL_TYPES +#undef CHECK_NUM + +// Shuffle vector +constexpr vector4char vector4charConst1 = {0, 1, 2, 3}; +constexpr vector4char vector4charConst2 = {4, 5, 6, 7}; +constexpr vector8char vector8intConst = {8, 9, 10, 11, 12, 13, 14, 15}; + +constexpr vector4char vectorShuffle1 = + __builtin_shufflevector(vector4charConst1, vector4charConst2, 0, 1, 2, 3); +static_assert(__builtin_bit_cast(unsigned, vectorShuffle1) == + (LITTLE_END ? 0x03020100 : 0x00010203)); +constexpr vector4char vectorShuffle2 = + __builtin_shufflevector(vector4charConst1, vector4charConst2, 4, 5, 6, 7); +static_assert(__builtin_bit_cast(unsigned, vectorShuffle2) == + (LITTLE_END ? 0x07060504 : 0x04050607)); +constexpr vector4char vectorShuffle3 = + __builtin_shufflevector(vector4charConst1, vector4charConst2, 0, 2, 4, 6); +static_assert(__builtin_bit_cast(unsigned, vectorShuffle3) == + (LITTLE_END ? 0x06040200 : 0x00020406)); +constexpr vector8char vectorShuffle4 = __builtin_shufflevector( + vector8intConst, vector8intConst, 0, 2, 4, 6, 8, 10, 12, 14); +static_assert(__builtin_bit_cast(unsigned long long, vectorShuffle4) == + (LITTLE_END ? 0x0E0C0A080E0C0A08 : 0x080A0C0E080A0C0E)); +constexpr vector4char vectorShuffle5 = + __builtin_shufflevector(vector8intConst, vector8intConst, 0, 2, 4, 6); +static_assert(__builtin_bit_cast(unsigned, vectorShuffle5) == + (LITTLE_END ? 0x0E0C0A08 : 0x080A0C0E)); +constexpr vector8char vectorShuffle6 = __builtin_shufflevector( + vector4charConst1, vector4charConst2, 0, 2, 4, 6, 1, 3, 5, 7); +static_assert(__builtin_bit_cast(unsigned long long, vectorShuffle6) == + (LITTLE_END ? 0x0705030106040200 : 0x0002040601030507)); + +constexpr vector4char + vectorShuffleFail1 = // expected-error {{constexpr variable 'vectorShuffleFail1'\ + must be initialized by a constant expression}} + __builtin_shufflevector( // expected-error {{index for __builtin_shufflevector \ +not within the bounds of the input vectors; index of -1 found at position 0 not \ +permitted in a constexpr context.}} + vector4charConst1, + vector4charConst2, -1, -1, -1, -1); diff --git a/clang/test/Sema/convertvector.c b/clang/test/Sema/convertvector.c index 8ae43c3ba3d4..1ff04af90981 100644 --- a/clang/test/Sema/convertvector.c +++ b/clang/test/Sema/convertvector.c @@ -15,3 +15,6 @@ vector8float foo3(double x) { return __builtin_convertvector(x, vector8float); // expected-error {{must be a vector}} } +float foo4(float x) { + return __builtin_convertvector(x, float); // expected-error {{first argument to __builtin_convertvector must be a vector}} +} -- GitLab From e3750fb65acf0f7447f6a49a0ba5d3197f4d9766 Mon Sep 17 00:00:00 2001 From: Jared Grubb Date: Mon, 29 Apr 2024 09:16:00 -0700 Subject: [PATCH 249/301] [Clang] Add diagnostic about "%P" specifier with Objective-C pointers (#89977) A Darwin extension '%P' combined with an Objective-C pointer seems to always be a bug. '%P' will dump bytes at the pointed-to address (in contrast to '%p' which dumps the pointer itself). This extension is only allowed in "OS Log" contexts and is intended to be used like `%{uuid_t}.*16P` or `%{timeval}.*P`. If an ObjC pointer is used, then the internal runtime structure (aka, the is-a pointer and other runtime metadata) will be dumped, which (IMO) is never the expectation. A simple diagnostic can help flag these scenarios. Resolves https://github.com/llvm/llvm-project/issues/89968 Co-authored-by: Jared Grubb --- clang/include/clang/Basic/DiagnosticSemaKinds.td | 3 +++ clang/lib/Sema/SemaChecking.cpp | 11 +++++++++++ clang/test/SemaObjC/format-strings-oslog.m | 5 ++++- 3 files changed, 18 insertions(+), 1 deletion(-) diff --git a/clang/include/clang/Basic/DiagnosticSemaKinds.td b/clang/include/clang/Basic/DiagnosticSemaKinds.td index 502c771a2d67..f72d5c252b86 100644 --- a/clang/include/clang/Basic/DiagnosticSemaKinds.td +++ b/clang/include/clang/Basic/DiagnosticSemaKinds.td @@ -9901,6 +9901,9 @@ def warn_format_invalid_annotation : Warning< def warn_format_P_no_precision : Warning< "using '%%P' format specifier without precision">, InGroup; +def warn_format_P_with_objc_pointer : Warning< + "using '%%P' format specifier with an Objective-C pointer results in dumping runtime object structure, not object value">, + InGroup; def warn_printf_ignored_flag: Warning< "flag '%0' is ignored when flag '%1' is present">, InGroup; diff --git a/clang/lib/Sema/SemaChecking.cpp b/clang/lib/Sema/SemaChecking.cpp index e26cf20d1036..cf8840c63024 100644 --- a/clang/lib/Sema/SemaChecking.cpp +++ b/clang/lib/Sema/SemaChecking.cpp @@ -12559,6 +12559,17 @@ CheckPrintfHandler::checkFormatExpr(const analyze_printf::PrintfSpecifier &FS, return true; } + // Diagnose attempts to use '%P' with ObjC object types, which will result in + // dumping raw class data (like is-a pointer), not actual data. + if (FS.getConversionSpecifier().getKind() == ConversionSpecifier::PArg && + ExprTy->isObjCObjectPointerType()) { + const CharSourceRange &CSR = + getSpecifierRange(StartSpecifier, SpecifierLen); + EmitFormatDiagnostic(S.PDiag(diag::warn_format_P_with_objc_pointer), + E->getExprLoc(), false, CSR); + return true; + } + ArgType::MatchKind ImplicitMatch = ArgType::NoMatch; ArgType::MatchKind Match = AT.matchesType(S.Context, ExprTy); ArgType::MatchKind OrigMatch = Match; diff --git a/clang/test/SemaObjC/format-strings-oslog.m b/clang/test/SemaObjC/format-strings-oslog.m index 20fec93b653b..af5aef3d6179 100644 --- a/clang/test/SemaObjC/format-strings-oslog.m +++ b/clang/test/SemaObjC/format-strings-oslog.m @@ -44,15 +44,18 @@ void test_os_log_format(const char *pc, int i, void *p, void *buf) { } // Test os_log_format primitive with ObjC string literal format argument. -void test_objc(const char *pc, int i, void *p, void *buf, NSString *nss) { +void test_objc(const char *pc, int i, void *p, void *buf, NSString *nss, id obj) { __builtin_os_log_format(buf, @""); __builtin_os_log_format(buf, @"%d"); // expected-warning {{more '%' conversions than data arguments}} __builtin_os_log_format(buf, @"%d", i); + __builtin_os_log_format(buf, @"%P", p); // expected-warning {{using '%P' format specifier without precision}} __builtin_os_log_format(buf, @"%.10P", p); __builtin_os_log_format(buf, @"%.*P", p); // expected-warning {{field precision should have type 'int', but argument has type 'void *'}} __builtin_os_log_format(buf, @"%.*P", i, p); __builtin_os_log_format(buf, @"%.*P", i, i); // expected-warning {{format specifies type 'void *' but the argument has type 'int'}} + __builtin_os_log_format(buf, @"%.8P", nss); // expected-warning {{using '%P' format specifier with an Objective-C pointer results in dumping runtime object structure, not object value}} + __builtin_os_log_format(buf, @"%.*P", i, obj); // expected-warning {{using '%P' format specifier with an Objective-C pointer results in dumping runtime object structure, not object value}} __builtin_os_log_format(buf, @"%{private}s", pc); __builtin_os_log_format(buf, @"%@", nss); -- GitLab From b07177fb68d396cc9063ac4899e4d67f6765597f Mon Sep 17 00:00:00 2001 From: Joseph Huber Date: Mon, 29 Apr 2024 11:18:37 -0500 Subject: [PATCH 250/301] [Libomptarget] Rework interface for enabling plugins (#86875) Summary: Previously we would build all of the plugins by default and then only load some using the `LIBOMPTARGET_PLUGINS_TO_LOAD` variable. This patch renamed this to `LIBOMPTARGET_PLUGINS_TO_BUILD` and changes whether or not it will include the plugin in CMake. Additionally this patch creates a new `Targets.def` file that allows us to enumerate all of the enabled plugins. This is somewhat different from the old method, and it's done this way for future use that will need to be shared. This follows the same method that LLVM uses for its targets, however it does require adding an extra include path. Depends on https://github.com/llvm/llvm-project/pull/86868 --- offload/CMakeLists.txt | 20 ++++++++++++++ offload/include/Shared/Targets.def.in | 20 ++++++++++++++ offload/plugins-nextgen/CMakeLists.txt | 9 ++++--- offload/plugins-nextgen/common/CMakeLists.txt | 1 + offload/src/CMakeLists.txt | 19 +++---------- offload/src/PluginManager.cpp | 27 +++++++++---------- 6 files changed, 64 insertions(+), 32 deletions(-) create mode 100644 offload/include/Shared/Targets.def.in diff --git a/offload/CMakeLists.txt b/offload/CMakeLists.txt index abc8baa0805f..a416ac29873f 100644 --- a/offload/CMakeLists.txt +++ b/offload/CMakeLists.txt @@ -151,6 +151,25 @@ if (NOT LIBOMPTARGET_LLVM_INCLUDE_DIRS) message(FATAL_ERROR "Missing definition for LIBOMPTARGET_LLVM_INCLUDE_DIRS") endif() +set(LIBOMPTARGET_ALL_PLUGIN_TARGETS amdgpu cuda host) +set(LIBOMPTARGET_PLUGINS_TO_BUILD "all" CACHE STRING + "Semicolon-separated list of plugins to use: cuda, amdgpu, host or \"all\".") + +if(LIBOMPTARGET_PLUGINS_TO_BUILD STREQUAL "all") + set(LIBOMPTARGET_PLUGINS_TO_BUILD ${LIBOMPTARGET_ALL_PLUGIN_TARGETS}) +endif() + +set(LIBOMPTARGET_ENUM_PLUGIN_TARGETS "") +foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) + set(LIBOMPTARGET_ENUM_PLUGIN_TARGETS + "${LIBOMPTARGET_ENUM_PLUGIN_TARGETS}PLUGIN_TARGET(${plugin})\n") +endforeach() +string(STRIP ${LIBOMPTARGET_ENUM_PLUGIN_TARGETS} LIBOMPTARGET_ENUM_PLUGIN_TARGETS) +configure_file( + ${CMAKE_CURRENT_SOURCE_DIR}/include/Shared/Targets.def.in + ${CMAKE_CURRENT_BINARY_DIR}/include/Shared/Targets.def +) + include_directories(${LIBOMPTARGET_LLVM_INCLUDE_DIRS}) # This is a list of all the targets that are supported/tested right now. @@ -288,6 +307,7 @@ set(LIBOMPTARGET_GPU_LIBC_SUPPORT ${LLVM_LIBC_GPU_BUILD} CACHE BOOL pythonize_bool(LIBOMPTARGET_GPU_LIBC_SUPPORT) set(LIBOMPTARGET_INCLUDE_DIR ${CMAKE_CURRENT_SOURCE_DIR}/include) +set(LIBOMPTARGET_BINARY_INCLUDE_DIR ${CMAKE_CURRENT_BINARY_DIR}/include) message(STATUS "OpenMP tools dir in libomptarget: ${LIBOMP_OMP_TOOLS_INCLUDE_DIR}") if(LIBOMP_OMP_TOOLS_INCLUDE_DIR) include_directories(${LIBOMP_OMP_TOOLS_INCLUDE_DIR}) diff --git a/offload/include/Shared/Targets.def.in b/offload/include/Shared/Targets.def.in new file mode 100644 index 000000000000..f34b523b4542 --- /dev/null +++ b/offload/include/Shared/Targets.def.in @@ -0,0 +1,20 @@ +//===-- Shared/Targets.def - Target plugin enumerator -----------*- C++ -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception +// +//===----------------------------------------------------------------------===// +// +// Enumerates over all of the supported target plugins that are available to +// the offloading library. +// +//===----------------------------------------------------------------------===// + +#ifndef PLUGIN_TARGET +# error Please define the macro PLUGIN_TARGET(TargetName) +#endif + +@LIBOMPTARGET_ENUM_PLUGIN_TARGETS@ + +#undef PLUGIN_TARGET diff --git a/offload/plugins-nextgen/CMakeLists.txt b/offload/plugins-nextgen/CMakeLists.txt index dbd82ac94517..df625e97c7eb 100644 --- a/offload/plugins-nextgen/CMakeLists.txt +++ b/offload/plugins-nextgen/CMakeLists.txt @@ -69,9 +69,12 @@ function(add_target_library target_name lib_name) set_target_properties(${target_name} PROPERTIES CXX_VISIBILITY_PRESET protected) endfunction() -add_subdirectory(amdgpu) -add_subdirectory(cuda) -add_subdirectory(host) +foreach(plugin IN LISTS LIBOMPTARGET_PLUGINS_TO_BUILD) + if(NOT EXISTS ${CMAKE_CURRENT_SOURCE_DIR}/${plugin}) + message(FATAL_ERROR "Unknown plugin target '${plugin}'") + endif() + add_subdirectory(${plugin}) +endforeach() # Make sure the parent scope can see the plugins that will be created. set(LIBOMPTARGET_SYSTEM_TARGETS "${LIBOMPTARGET_SYSTEM_TARGETS}" PARENT_SCOPE) diff --git a/offload/plugins-nextgen/common/CMakeLists.txt b/offload/plugins-nextgen/common/CMakeLists.txt index a7350e662a7c..acf0af63f050 100644 --- a/offload/plugins-nextgen/common/CMakeLists.txt +++ b/offload/plugins-nextgen/common/CMakeLists.txt @@ -62,6 +62,7 @@ target_link_options(PluginCommon PUBLIC ${offload_link_flags}) target_include_directories(PluginCommon PUBLIC ${CMAKE_CURRENT_SOURCE_DIR}/include ${LIBOMPTARGET_LLVM_INCLUDE_DIRS} + ${LIBOMPTARGET_BINARY_INCLUDE_DIR} ${LIBOMPTARGET_INCLUDE_DIR} ) diff --git a/offload/src/CMakeLists.txt b/offload/src/CMakeLists.txt index 8b7be98771a9..eda5a85ff1ab 100644 --- a/offload/src/CMakeLists.txt +++ b/offload/src/CMakeLists.txt @@ -37,6 +37,7 @@ add_llvm_library(omptarget ADDITIONAL_HEADER_DIRS ${LIBOMPTARGET_INCLUDE_DIR} + ${LIBOMPTARGET_BINARY_INCLUDE_DIR} LINK_COMPONENTS Support @@ -49,7 +50,9 @@ add_llvm_library(omptarget NO_INSTALL_RPATH BUILDTREE_ONLY ) -target_include_directories(omptarget PRIVATE ${LIBOMPTARGET_INCLUDE_DIR}) +target_include_directories(omptarget PRIVATE + ${LIBOMPTARGET_INCLUDE_DIR} ${LIBOMPTARGET_BINARY_INCLUDE_DIR} +) if (LIBOMP_HAVE_VERSION_SCRIPT_FLAG) target_link_libraries(omptarget PRIVATE @@ -65,20 +68,6 @@ target_compile_definitions(omptarget PRIVATE target_compile_options(omptarget PUBLIC ${offload_compile_flags}) target_link_options(omptarget PUBLIC ${offload_link_flags}) -macro(check_plugin_target target) -if (TARGET omptarget.rtl.${target}) - list(APPEND LIBOMPTARGET_PLUGINS_TO_LOAD ${target}) -endif() -endmacro() - -set(LIBOMPTARGET_PLUGINS_TO_LOAD "" CACHE STRING - "Comma separated list of plugin names to look for at runtime") -if (NOT LIBOMPTARGET_PLUGINS_TO_LOAD) - check_plugin_target(cuda) - check_plugin_target(amdgpu) - check_plugin_target(host) -endif() - list(TRANSFORM LIBOMPTARGET_PLUGINS_TO_LOAD PREPEND "\"libomptarget.rtl.") list(TRANSFORM LIBOMPTARGET_PLUGINS_TO_LOAD APPEND "\"") list(JOIN LIBOMPTARGET_PLUGINS_TO_LOAD "," ENABLED_OFFLOAD_PLUGINS) diff --git a/offload/src/PluginManager.cpp b/offload/src/PluginManager.cpp index 792cae3e3dd5..dbb556c179e5 100644 --- a/offload/src/PluginManager.cpp +++ b/offload/src/PluginManager.cpp @@ -23,9 +23,6 @@ using namespace llvm::sys; PluginManager *PM = nullptr; -// List of all plugins that can support offloading. -static const char *RTLNames[] = {ENABLED_OFFLOAD_PLUGINS}; - Expected> PluginAdaptorTy::create(const std::string &Name) { DP("Attempting to load library '%s'...\n", Name.c_str()); @@ -95,17 +92,19 @@ void PluginManager::init() { // Attempt to open all the plugins and, if they exist, check if the interface // is correct and if they are supporting any devices. - for (const char *Name : RTLNames) { - auto PluginAdaptorOrErr = - PluginAdaptorTy::create(std::string(Name) + ".so"); - if (!PluginAdaptorOrErr) { - [[maybe_unused]] std::string InfoMsg = - toString(PluginAdaptorOrErr.takeError()); - DP("%s", InfoMsg.c_str()); - } else { - PluginAdaptors.push_back(std::move(*PluginAdaptorOrErr)); - } - } +#define PLUGIN_TARGET(Name) \ + do { \ + auto PluginAdaptorOrErr = \ + PluginAdaptorTy::create("libomptarget.rtl." #Name ".so"); \ + if (!PluginAdaptorOrErr) { \ + [[maybe_unused]] std::string InfoMsg = \ + toString(PluginAdaptorOrErr.takeError()); \ + DP("%s", InfoMsg.c_str()); \ + } else { \ + PluginAdaptors.push_back(std::move(*PluginAdaptorOrErr)); \ + } \ + } while (false); +#include "Shared/Targets.def" DP("RTLs loaded!\n"); } -- GitLab From 4c701577cd4175068e4f8dda250f2a5f5aefbe24 Mon Sep 17 00:00:00 2001 From: yonghong-song Date: Mon, 29 Apr 2024 09:20:56 -0700 Subject: [PATCH 251/301] BPF: Use DebugLoc to find Filename for BTF line info (#90302) Andrii found an issue where the BTF line info may have empty source which seems wrong. The program is a Meta internal bpf program. I can reproduce with latest upstream compiler as well. Let the bpf program built without this patch and then with the following veristat check where veristat is a bpf verifier tool to do kernel verification for bpf programs: $ veristat -vl2 yhs.bpf.o --log-size=150000000 >& log $ rg '^;' log | sort | uniq -c | sort -nr | head -n10 4206 ; } else if (action->dry_run) { @ src_mitigations.h:57 3907 ; if (now < start_allow_time) { @ ban.h:17 3674 ; @ src_mitigations.h:0 3223 ; if (action->vip_id != ALL_VIPS_ID && action->vip_id != vip_id) { @ src_mitigations.h:85 1737 ; pkt_info->is_dry_run_drop = action->dry_run; @ src_mitigations.h:26 1737 ; if (mitigation == ALLOW) { @ src_mitigations.h:28 1737 ; enum match_action mitigation = action->action; @ src_mitigations.h:25 1727 ; void* res = bpf_map_lookup_elem(bpf_map, key); @ filter_helpers.h:498 1691 ; bpf_map_lookup_elem(&rate_limit_config_map, rule_id); @ rate_limit.h:76 1688 ; if (throttle_cfg) { @ rate_limit.h:85 You can see 3674 ; @ src_mitigations.h:0 where we do not have proper line information and line number. In LLVM Machine IR, some instructions may carry DebugLoc information to specify where the corresponding source is for this instruction. The information includes file_name, line_num and col_num. Each instruction may also attribute to a function in debuginfo. So there are two ways to find file_name for a particular insn: (1) find the corresponding function in debuginfo (MI->getMF()->getFunction().getSubprogram()) and then find the file_name from DISubprogram. (2) find the corresponding file_name from DebugLoc. The option (1) is used in current implementation. This mostly works. But if one instruction is somehow generated from multiple functions, the compiler has to pick just one. This may cause a mismatch between file_name and line_num/col_num. Besides potential incorrect mismatch of file_name vs. line_num/col_num, There is another issue where some DebugLoc has line number 0. For example, I dumped the dwarf line table for the above bpf program: Address Line Column File ISA Discriminator OpIndex Flags ------------------ ------ ------ ------ --- ------------- ------- ------------- 0x0000000000000000 96 0 17 0 0 0 is_stmt 0x0000000000000010 100 12 17 0 0 0 is_stmt prologue_end 0x0000000000000020 0 12 17 0 0 0 0x0000000000000058 37 7 17 0 0 0 is_stmt 0x0000000000000060 0 0 17 0 0 0 0x0000000000000088 37 7 17 0 0 0 0x0000000000000090 42 75 17 0 0 0 is_stmt 0x00000000000000a8 42 52 17 0 0 0 0x00000000000000c0 120 9 17 0 0 0 is_stmt 0x00000000000000c8 0 9 17 0 0 0 0x00000000000000d0 106 21 17 0 0 0 is_stmt 0x00000000000000d8 106 3 17 0 0 0 0x00000000000000e0 110 25 17 0 0 0 is_stmt 0x00000000000000f8 110 36 17 0 0 0 0x0000000000000100 0 36 17 0 0 0 ... These DebugLoc with line number 0 needs to be skipped since we cannot map them to the correct source code. Note that selftest offset-reloc-basic.ll has this issue as well which is adjusted by this patch. With the above two fixes, empty lines for source annotation are removed. $ veristat -vl2 yhs.bpf.o --log-size=150000000 >& log $ rg '^;' log.latest | sort | uniq -c | sort -nr | head -n10 4206 ; } else if (action->dry_run) { @ src_mitigations.h:57 3907 ; if (now < start_allow_time) { @ ban.h:17 3223 ; if (action->vip_id != ALL_VIPS_ID && action->vip_id != vip_id) { @ src_mitigations.h:85 1737 ; pkt_info->is_dry_run_drop = action->dry_run; @ src_mitigations.h:26 1737 ; if (mitigation == ALLOW) { @ src_mitigations.h:28 1737 ; enum match_action mitigation = action->action; @ src_mitigations.h:25 1727 ; void* res = bpf_map_lookup_elem(bpf_map, key); @ filter_helpers.h:498 1691 ; bpf_map_lookup_elem(&rate_limit_config_map, rule_id); @ rate_limit.h:76 1688 ; if (throttle_cfg) { @ rate_limit.h:85 1670 ; if (rl_cfg) { @ rate_limit.h:77 You can see that we do not have empty line any more. 3223 ; if (action->vip_id != ALL_VIPS_ID && action->vip_id != vip_id) { @ src_mitigations.h:85 Signed-off-by: Yonghong Song --- llvm/lib/Target/BPF/BTFDebug.cpp | 18 ++++++++---------- llvm/lib/Target/BPF/BTFDebug.h | 4 ++-- .../CodeGen/BPF/CORE/offset-reloc-basic.ll | 4 ++-- 3 files changed, 12 insertions(+), 14 deletions(-) diff --git a/llvm/lib/Target/BPF/BTFDebug.cpp b/llvm/lib/Target/BPF/BTFDebug.cpp index ebd8447eba85..8c9f5c4dc554 100644 --- a/llvm/lib/Target/BPF/BTFDebug.cpp +++ b/llvm/lib/Target/BPF/BTFDebug.cpp @@ -973,8 +973,7 @@ void BTFDebug::visitMapDefType(const DIType *Ty, uint32_t &TypeId) { } /// Read file contents from the actual file or from the source -std::string BTFDebug::populateFileContent(const DISubprogram *SP) { - auto File = SP->getFile(); +std::string BTFDebug::populateFileContent(const DIFile *File) { std::string FileName; if (!File->getFilename().starts_with("/") && File->getDirectory().size()) @@ -1005,9 +1004,9 @@ std::string BTFDebug::populateFileContent(const DISubprogram *SP) { return FileName; } -void BTFDebug::constructLineInfo(const DISubprogram *SP, MCSymbol *Label, +void BTFDebug::constructLineInfo(MCSymbol *Label, const DIFile *File, uint32_t Line, uint32_t Column) { - std::string FileName = populateFileContent(SP); + std::string FileName = populateFileContent(File); BTFLineInfo LineInfo; LineInfo.Label = Label; @@ -1366,10 +1365,10 @@ void BTFDebug::beginInstruction(const MachineInstr *MI) { if (!CurMI) // no debug info return; - // Skip this instruction if no DebugLoc or the DebugLoc - // is the same as the previous instruction. + // Skip this instruction if no DebugLoc, the DebugLoc + // is the same as the previous instruction or Line is 0. const DebugLoc &DL = MI->getDebugLoc(); - if (!DL || PrevInstLoc == DL) { + if (!DL || PrevInstLoc == DL || DL.getLine() == 0) { // This instruction will be skipped, no LineInfo has // been generated, construct one based on function signature. if (LineInfoGenerated == false) { @@ -1377,7 +1376,7 @@ void BTFDebug::beginInstruction(const MachineInstr *MI) { if (!S) return; MCSymbol *FuncLabel = Asm->getFunctionBegin(); - constructLineInfo(S, FuncLabel, S->getLine(), 0); + constructLineInfo(FuncLabel, S->getFile(), S->getLine(), 0); LineInfoGenerated = true; } @@ -1389,8 +1388,7 @@ void BTFDebug::beginInstruction(const MachineInstr *MI) { OS.emitLabel(LineSym); // Construct the lineinfo. - auto SP = DL->getScope()->getSubprogram(); - constructLineInfo(SP, LineSym, DL.getLine(), DL.getCol()); + constructLineInfo(LineSym, DL->getFile(), DL.getLine(), DL.getCol()); LineInfoGenerated = true; PrevInstLoc = DL; diff --git a/llvm/lib/Target/BPF/BTFDebug.h b/llvm/lib/Target/BPF/BTFDebug.h index 7536006ed21c..11a0c59ba6c9 100644 --- a/llvm/lib/Target/BPF/BTFDebug.h +++ b/llvm/lib/Target/BPF/BTFDebug.h @@ -343,10 +343,10 @@ class BTFDebug : public DebugHandlerBase { /// Get the file content for the subprogram. Certain lines of the file /// later may be put into string table and referenced by line info. - std::string populateFileContent(const DISubprogram *SP); + std::string populateFileContent(const DIFile *File); /// Construct a line info. - void constructLineInfo(const DISubprogram *SP, MCSymbol *Label, uint32_t Line, + void constructLineInfo(MCSymbol *Label, const DIFile *File, uint32_t Line, uint32_t Column); /// Generate types and variables for globals. diff --git a/llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll b/llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll index 8ca8a6602737..024ed04f6e5e 100644 --- a/llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll +++ b/llvm/test/CodeGen/BPF/CORE/offset-reloc-basic.ll @@ -108,8 +108,8 @@ define dso_local i32 @bpf_prog(ptr) local_unnamed_addr #0 !dbg !15 { ; CHECK-NEXT: .long 0 ; CHECK-NEXT: .long 20 ; CHECK-NEXT: .long 20 -; CHECK-NEXT: .long 124 -; CHECK-NEXT: .long 144 +; CHECK-NEXT: .long 108 +; CHECK-NEXT: .long 128 ; CHECK-NEXT: .long 28 ; CHECK-NEXT: .long 8 # FuncInfo -- GitLab From 3590ede848d67cf7d49d43e1830f90b053e3e76f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Timm=20B=C3=A4der?= Date: Mon, 29 Apr 2024 17:32:30 +0200 Subject: [PATCH 252/301] [clang][Interp] Support vec_step --- clang/lib/AST/Interp/ByteCodeExprGen.cpp | 14 +++++++++++ clang/test/AST/Interp/opencl.cl | 32 ++++++++++++++++++++++++ clang/test/SemaOpenCL/vec_step.cl | 2 +- 3 files changed, 47 insertions(+), 1 deletion(-) create mode 100644 clang/test/AST/Interp/opencl.cl diff --git a/clang/lib/AST/Interp/ByteCodeExprGen.cpp b/clang/lib/AST/Interp/ByteCodeExprGen.cpp index 3ceccfdebfca..17f95e7f3cac 100644 --- a/clang/lib/AST/Interp/ByteCodeExprGen.cpp +++ b/clang/lib/AST/Interp/ByteCodeExprGen.cpp @@ -1358,6 +1358,20 @@ bool ByteCodeExprGen::VisitUnaryExprOrTypeTraitExpr( assert(E->getTypeOfArgument()->isSizelessVectorType()); } + if (Kind == UETT_VecStep) { + if (const auto *VT = E->getTypeOfArgument()->getAs()) { + unsigned N = VT->getNumElements(); + + // The vec_step built-in functions that take a 3-component + // vector return 4. (OpenCL 1.1 spec 6.11.12) + if (N == 3) + N = 4; + + return this->emitConst(N, E); + } + return this->emitConst(1, E); + } + return false; } diff --git a/clang/test/AST/Interp/opencl.cl b/clang/test/AST/Interp/opencl.cl new file mode 100644 index 000000000000..b9ba4f8b9b55 --- /dev/null +++ b/clang/test/AST/Interp/opencl.cl @@ -0,0 +1,32 @@ +// RUN: %clang_cc1 -fsyntax-only -verify=ref,both %s +// RUN: %clang_cc1 -fsyntax-only -verify=expected,both %s -fexperimental-new-constant-interpreter + +// both-no-diagnostics + +typedef int int2 __attribute__((ext_vector_type(2))); +typedef int int3 __attribute__((ext_vector_type(3))); +typedef int int4 __attribute__((ext_vector_type(4))); +typedef int int8 __attribute__((ext_vector_type(8))); +typedef int int16 __attribute__((ext_vector_type(16))); + +void foo(int3 arg1, int8 arg2) { + int4 auto1; + int16 *auto2; + int auto3; + int2 auto4; + struct S *incomplete1; + + int res1[vec_step(arg1) == 4 ? 1 : -1]; + int res2[vec_step(arg2) == 8 ? 1 : -1]; + int res3[vec_step(auto1) == 4 ? 1 : -1]; + int res4[vec_step(*auto2) == 16 ? 1 : -1]; + int res5[vec_step(auto3) == 1 ? 1 : -1]; + int res6[vec_step(auto4) == 2 ? 1 : -1]; + int res7[vec_step(int2) == 2 ? 1 : -1]; + int res8[vec_step(int3) == 4 ? 1 : -1]; + int res9[vec_step(int4) == 4 ? 1 : -1]; + int res10[vec_step(int8) == 8 ? 1 : -1]; + int res11[vec_step(int16) == 16 ? 1 : -1]; + int res12[vec_step(void) == 1 ? 1 : -1]; +} + diff --git a/clang/test/SemaOpenCL/vec_step.cl b/clang/test/SemaOpenCL/vec_step.cl index afb6dc94d92e..c116f09b351f 100644 --- a/clang/test/SemaOpenCL/vec_step.cl +++ b/clang/test/SemaOpenCL/vec_step.cl @@ -1,4 +1,4 @@ -// RUN: %clang_cc1 -fsyntax-only -pedantic -verify %s +// RUN: %clang_cc1 -fsyntax-only -pedantic -verify %s -fexperimental-new-constant-interpreter typedef int int2 __attribute__((ext_vector_type(2))); typedef int int3 __attribute__((ext_vector_type(3))); -- GitLab From dede19caf0da31d9b8b69d014602cde41ab9a96e Mon Sep 17 00:00:00 2001 From: Matthias Braun Date: Mon, 29 Apr 2024 09:21:50 -0700 Subject: [PATCH 253/301] GlobalOpt: Handle threadlocal.address intrinsic (#88454) This changes `GlobalOpt` to skip/look-through `threadlocal.address` intrinsic where apropriate. This fixes issue #73314 --- .../llvm/Transforms/Utils/GlobalStatus.h | 6 +++--- llvm/lib/Transforms/IPO/GlobalOpt.cpp | 7 +++++++ llvm/lib/Transforms/Utils/GlobalStatus.cpp | 11 +++++++--- llvm/test/Transforms/GlobalOpt/basictest.ll | 20 ++++++++++++++++--- .../GlobalOpt/constantfold-initializers.ll | 5 +++-- .../GlobalOpt/stored-once-forward-value.ll | 6 ++++-- llvm/test/Transforms/GlobalOpt/tls.ll | 12 +++++++---- 7 files changed, 50 insertions(+), 17 deletions(-) diff --git a/llvm/include/llvm/Transforms/Utils/GlobalStatus.h b/llvm/include/llvm/Transforms/Utils/GlobalStatus.h index 60c91fc30174..c001e587313c 100644 --- a/llvm/include/llvm/Transforms/Utils/GlobalStatus.h +++ b/llvm/include/llvm/Transforms/Utils/GlobalStatus.h @@ -24,9 +24,9 @@ class Value; /// bool isSafeToDestroyConstant(const Constant *C); -/// As we analyze each global, keep track of some information about it. If we -/// find out that the address of the global is taken, none of this info will be -/// accurate. +/// As we analyze each global or thread-local variable, keep track of some +/// information about it. If we find out that the address of the global is +/// taken, none of this info will be accurate. struct GlobalStatus { /// True if the global's address is used in a comparison. bool IsCompared = false; diff --git a/llvm/lib/Transforms/IPO/GlobalOpt.cpp b/llvm/lib/Transforms/IPO/GlobalOpt.cpp index da714c9a7570..fbb83e787f63 100644 --- a/llvm/lib/Transforms/IPO/GlobalOpt.cpp +++ b/llvm/lib/Transforms/IPO/GlobalOpt.cpp @@ -306,6 +306,10 @@ static bool CleanupConstantGlobalUsers(GlobalVariable *GV, APInt Offset(DL.getIndexTypeSizeInBits(PtrOp->getType()), 0); PtrOp = PtrOp->stripAndAccumulateConstantOffsets( DL, Offset, /* AllowNonInbounds */ true); + if (IntrinsicInst *II = dyn_cast(PtrOp)) { + if (II->getIntrinsicID() == Intrinsic::threadlocal_address) + PtrOp = II->getArgOperand(0); + } if (PtrOp == GV) { if (auto *Value = ConstantFoldLoadFromConst(Init, Ty, Offset, DL)) { LI->replaceAllUsesWith(Value); @@ -318,6 +322,9 @@ static bool CleanupConstantGlobalUsers(GlobalVariable *GV, } else if (MemIntrinsic *MI = dyn_cast(U)) { // memset/cpy/mv if (getUnderlyingObject(MI->getRawDest()) == GV) EraseFromParent(MI); + } else if (IntrinsicInst *II = dyn_cast(U)) { + if (II->getIntrinsicID() == Intrinsic::threadlocal_address) + append_range(WorkList, II->users()); } } diff --git a/llvm/lib/Transforms/Utils/GlobalStatus.cpp b/llvm/lib/Transforms/Utils/GlobalStatus.cpp index c5aded3c45f4..b177e048faae 100644 --- a/llvm/lib/Transforms/Utils/GlobalStatus.cpp +++ b/llvm/lib/Transforms/Utils/GlobalStatus.cpp @@ -172,9 +172,14 @@ static bool analyzeGlobalAux(const Value *V, GlobalStatus &GS, return true; GS.StoredType = GlobalStatus::Stored; } else if (const auto *CB = dyn_cast(I)) { - if (!CB->isCallee(&U)) - return true; - GS.IsLoaded = true; + if (CB->getIntrinsicID() == Intrinsic::threadlocal_address) { + if (analyzeGlobalAux(I, GS, VisitedUsers)) + return true; + } else { + if (!CB->isCallee(&U)) + return true; + GS.IsLoaded = true; + } } else { return true; // Any other non-load instruction might take address! } diff --git a/llvm/test/Transforms/GlobalOpt/basictest.ll b/llvm/test/Transforms/GlobalOpt/basictest.ll index 6d7fcdd96dfd..72d38a1e8845 100644 --- a/llvm/test/Transforms/GlobalOpt/basictest.ll +++ b/llvm/test/Transforms/GlobalOpt/basictest.ll @@ -1,9 +1,23 @@ +; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4 ; RUN: opt < %s -passes=globalopt -S | FileCheck %s -; CHECK-NOT: global @X = internal global i32 4 ; [#uses=1] define i32 @foo() { - %V = load i32, ptr @X ; [#uses=1] - ret i32 %V +; CHECK-LABEL: define i32 @foo() local_unnamed_addr { +; CHECK-NEXT: ret i32 4 +; + %V = load i32, ptr @X ; [#uses=1] + ret i32 %V +} + +@X_tls = internal thread_local global i32 13 + +define i32 @bar() { +; CHECK-LABEL: define i32 @bar() local_unnamed_addr { +; CHECK-NEXT: ret i32 13 +; + %p = call ptr @llvm.threadlocal.address(ptr @X_tls) + %v = load i32, ptr %p + ret i32 %v } diff --git a/llvm/test/Transforms/GlobalOpt/constantfold-initializers.ll b/llvm/test/Transforms/GlobalOpt/constantfold-initializers.ll index ca844f63937c..f82942e73d92 100644 --- a/llvm/test/Transforms/GlobalOpt/constantfold-initializers.ll +++ b/llvm/test/Transforms/GlobalOpt/constantfold-initializers.ll @@ -72,11 +72,12 @@ entry: } @threadlocalptr = global ptr null, align 4 -; CHECK: @threadlocalptr = global ptr null, align 4 +; CHECK: @threadlocalptr = local_unnamed_addr global ptr null, align 4 @threadlocalvar = external thread_local global i32 define internal void @test5() { entry: - store ptr @threadlocalvar, ptr @threadlocalptr, align 4 + %p = call ptr @llvm.threadlocal.address(ptr @threadlocalvar) + store ptr %p, ptr @threadlocalptr, align 4 ret void } diff --git a/llvm/test/Transforms/GlobalOpt/stored-once-forward-value.ll b/llvm/test/Transforms/GlobalOpt/stored-once-forward-value.ll index 7b845070bbd0..2b7ceb4169f3 100644 --- a/llvm/test/Transforms/GlobalOpt/stored-once-forward-value.ll +++ b/llvm/test/Transforms/GlobalOpt/stored-once-forward-value.ll @@ -39,12 +39,14 @@ define i32 @dom_arg(i32 %a) { define ptr @dom_thread_local_global() { ; CHECK-LABEL: @dom_thread_local_global( -; CHECK-NEXT: store ptr @tl, ptr @g3, align 8 +; CHECK-NEXT: [[P:%.*]] = call ptr @llvm.threadlocal.address.p0(ptr @tl) +; CHECK-NEXT: store ptr [[P]], ptr @g3, align 8 ; CHECK-NEXT: call void @b() ; CHECK-NEXT: [[R:%.*]] = load ptr, ptr @g3, align 8 ; CHECK-NEXT: ret ptr [[R]] ; - store ptr @tl, ptr @g3 + %p = call ptr @llvm.threadlocal.address(ptr @tl) + store ptr %p, ptr @g3 call void @b() %r = load ptr, ptr @g3 ret ptr %r diff --git a/llvm/test/Transforms/GlobalOpt/tls.ll b/llvm/test/Transforms/GlobalOpt/tls.ll index 6ba003ff30b2..2cc2ea4e366e 100644 --- a/llvm/test/Transforms/GlobalOpt/tls.ll +++ b/llvm/test/Transforms/GlobalOpt/tls.ll @@ -15,14 +15,16 @@ declare void @start_thread(ptr) define i32 @f() { entry: ; Set @ip to point to x[1] for thread 1. - store ptr getelementptr inbounds ([100 x i32], ptr @x, i64 0, i64 1), ptr @ip, align 8 + %p = call ptr @llvm.threadlocal.address(ptr @x) + %addr = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 1 + store ptr %addr, ptr @ip, align 8 ; Run g on a new thread. tail call void @start_thread(ptr @g) nounwind tail call void @wait() nounwind ; Reset x[1] for thread 1. - store i32 0, ptr getelementptr inbounds ([100 x i32], ptr @x, i64 0, i64 1), align 4 + store i32 0, ptr %addr, align 4 ; Read the value of @ip, which now points at x[1] for thread 2. %0 = load ptr, ptr @ip, align 8 @@ -39,10 +41,12 @@ entry: define internal void @g() nounwind uwtable { entry: ; Set @ip to point to x[1] for thread 2. - store ptr getelementptr inbounds ([100 x i32], ptr @x, i64 0, i64 1), ptr @ip, align 8 + %p = call ptr @llvm.threadlocal.address(ptr @x) + %addr = getelementptr inbounds [100 x i32], ptr %p, i64 0, i64 1 + store ptr %addr, ptr @ip, align 8 ; Store 50 in x[1] for thread 2. - store i32 50, ptr getelementptr inbounds ([100 x i32], ptr @x, i64 0, i64 1), align 4 + store i32 50, ptr %addr, align 4 tail call void @signal() nounwind ret void -- GitLab From e441363f7da2da50449917f17ab4ed412f9e7cb3 Mon Sep 17 00:00:00 2001 From: Ryosuke Niwa Date: Mon, 29 Apr 2024 09:27:01 -0700 Subject: [PATCH 254/301] Fix a crash introduced by 3d5e9ab by adding a nullptr check. (#90301) --- .../Checkers/WebKit/UncountedCallArgsChecker.cpp | 7 ++++--- .../WebKit/call-args-regression-traverse-decl-crash.cpp | 7 +++++++ 2 files changed, 11 insertions(+), 3 deletions(-) create mode 100644 clang/test/Analysis/Checkers/WebKit/call-args-regression-traverse-decl-crash.cpp diff --git a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp index 741f33676158..ae494de58da3 100644 --- a/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp +++ b/clang/lib/StaticAnalyzer/Checkers/WebKit/UncountedCallArgsChecker.cpp @@ -53,10 +53,11 @@ public: bool shouldVisitTemplateInstantiations() const { return true; } bool shouldVisitImplicitCode() const { return false; } - bool TraverseDecl(Decl *D) { - if (isa(D) && isRefType(safeGetName(D))) + bool TraverseClassTemplateDecl(ClassTemplateDecl *Decl) { + if (isRefType(safeGetName(Decl))) return true; - return RecursiveASTVisitor::TraverseDecl(D); + return RecursiveASTVisitor::TraverseClassTemplateDecl( + Decl); } bool VisitCallExpr(const CallExpr *CE) { diff --git a/clang/test/Analysis/Checkers/WebKit/call-args-regression-traverse-decl-crash.cpp b/clang/test/Analysis/Checkers/WebKit/call-args-regression-traverse-decl-crash.cpp new file mode 100644 index 000000000000..3d8e822025f6 --- /dev/null +++ b/clang/test/Analysis/Checkers/WebKit/call-args-regression-traverse-decl-crash.cpp @@ -0,0 +1,7 @@ +// RUN: %clang_analyze_cc1 -analyzer-checker=alpha.webkit.UncountedCallArgsChecker -verify %s +// expected-no-diagnostics + +template struct T; +template